1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Define max FPO streams as 4 for now. Current implementation today 99 * only supports 1, but could be more in the future. Reduce array 100 * size to ensure the command size remains less than 64 bytes if 101 * adding new fields. 102 */ 103 #define DMUB_MAX_FPO_STREAMS 4 104 105 /* Maximum number of streams on any ASIC. */ 106 #define DMUB_MAX_STREAMS 6 107 108 /* Maximum number of planes on any ASIC. */ 109 #define DMUB_MAX_PLANES 6 110 111 /* Trace buffer offset for entry */ 112 #define TRACE_BUFFER_ENTRY_OFFSET 16 113 114 /** 115 * Maximum number of dirty rects supported by FW. 116 */ 117 #define DMUB_MAX_DIRTY_RECTS 3 118 119 /** 120 * 121 * PSR control version legacy 122 */ 123 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 124 /** 125 * PSR control version with multi edp support 126 */ 127 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 128 129 130 /** 131 * ABM control version legacy 132 */ 133 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 134 135 /** 136 * ABM control version with multi edp support 137 */ 138 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 139 140 /** 141 * Physical framebuffer address location, 64-bit. 142 */ 143 #ifndef PHYSICAL_ADDRESS_LOC 144 #define PHYSICAL_ADDRESS_LOC union large_integer 145 #endif 146 147 /** 148 * OS/FW agnostic memcpy 149 */ 150 #ifndef dmub_memcpy 151 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 152 #endif 153 154 /** 155 * OS/FW agnostic memset 156 */ 157 #ifndef dmub_memset 158 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 159 #endif 160 161 #if defined(__cplusplus) 162 extern "C" { 163 #endif 164 165 /** 166 * OS/FW agnostic udelay 167 */ 168 #ifndef dmub_udelay 169 #define dmub_udelay(microseconds) udelay(microseconds) 170 #endif 171 172 #pragma pack(push, 1) 173 /** 174 * union dmub_addr - DMUB physical/virtual 64-bit address. 175 */ 176 union dmub_addr { 177 struct { 178 uint32_t low_part; /**< Lower 32 bits */ 179 uint32_t high_part; /**< Upper 32 bits */ 180 } u; /*<< Low/high bit access */ 181 uint64_t quad_part; /*<< 64 bit address */ 182 }; 183 #pragma pack(pop) 184 185 /** 186 * Dirty rect definition. 187 */ 188 struct dmub_rect { 189 /** 190 * Dirty rect x offset. 191 */ 192 uint32_t x; 193 194 /** 195 * Dirty rect y offset. 196 */ 197 uint32_t y; 198 199 /** 200 * Dirty rect width. 201 */ 202 uint32_t width; 203 204 /** 205 * Dirty rect height. 206 */ 207 uint32_t height; 208 }; 209 210 /** 211 * Flags that can be set by driver to change some PSR behaviour. 212 */ 213 union dmub_psr_debug_flags { 214 /** 215 * Debug flags. 216 */ 217 struct { 218 /** 219 * Enable visual confirm in FW. 220 */ 221 uint32_t visual_confirm : 1; 222 223 /** 224 * Force all selective updates to bw full frame updates. 225 */ 226 uint32_t force_full_frame_update : 1; 227 228 /** 229 * Use HW Lock Mgr object to do HW locking in FW. 230 */ 231 uint32_t use_hw_lock_mgr : 1; 232 233 /** 234 * Use TPS3 signal when restore main link. 235 */ 236 uint32_t force_wakeup_by_tps3 : 1; 237 238 /** 239 * Back to back flip, therefore cannot power down PHY 240 */ 241 uint32_t back_to_back_flip : 1; 242 243 } bitfields; 244 245 /** 246 * Union for debug flags. 247 */ 248 uint32_t u32All; 249 }; 250 251 /** 252 * DMUB visual confirm color 253 */ 254 struct dmub_feature_caps { 255 /** 256 * Max PSR version supported by FW. 257 */ 258 uint8_t psr; 259 uint8_t fw_assisted_mclk_switch; 260 uint8_t reserved[4]; 261 uint8_t subvp_psr_support; 262 uint8_t gecc_enable; 263 }; 264 265 struct dmub_visual_confirm_color { 266 /** 267 * Maximum 10 bits color value 268 */ 269 uint16_t color_r_cr; 270 uint16_t color_g_y; 271 uint16_t color_b_cb; 272 uint16_t panel_inst; 273 }; 274 275 #if defined(__cplusplus) 276 } 277 #endif 278 279 //============================================================================== 280 //</DMUB_TYPES>================================================================= 281 //============================================================================== 282 //< DMUB_META>================================================================== 283 //============================================================================== 284 #pragma pack(push, 1) 285 286 /* Magic value for identifying dmub_fw_meta_info */ 287 #define DMUB_FW_META_MAGIC 0x444D5542 288 289 /* Offset from the end of the file to the dmub_fw_meta_info */ 290 #define DMUB_FW_META_OFFSET 0x24 291 292 /** 293 * struct dmub_fw_meta_info - metadata associated with fw binary 294 * 295 * NOTE: This should be considered a stable API. Fields should 296 * not be repurposed or reordered. New fields should be 297 * added instead to extend the structure. 298 * 299 * @magic_value: magic value identifying DMUB firmware meta info 300 * @fw_region_size: size of the firmware state region 301 * @trace_buffer_size: size of the tracebuffer region 302 * @fw_version: the firmware version information 303 * @dal_fw: 1 if the firmware is DAL 304 */ 305 struct dmub_fw_meta_info { 306 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 307 uint32_t fw_region_size; /**< size of the firmware state region */ 308 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 309 uint32_t fw_version; /**< the firmware version information */ 310 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 311 uint8_t reserved[3]; /**< padding bits */ 312 }; 313 314 /** 315 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 316 */ 317 union dmub_fw_meta { 318 struct dmub_fw_meta_info info; /**< metadata info */ 319 uint8_t reserved[64]; /**< padding bits */ 320 }; 321 322 #pragma pack(pop) 323 324 //============================================================================== 325 //< DMUB Trace Buffer>================================================================ 326 //============================================================================== 327 /** 328 * dmub_trace_code_t - firmware trace code, 32-bits 329 */ 330 typedef uint32_t dmub_trace_code_t; 331 332 /** 333 * struct dmcub_trace_buf_entry - Firmware trace entry 334 */ 335 struct dmcub_trace_buf_entry { 336 dmub_trace_code_t trace_code; /**< trace code for the event */ 337 uint32_t tick_count; /**< the tick count at time of trace */ 338 uint32_t param0; /**< trace defined parameter 0 */ 339 uint32_t param1; /**< trace defined parameter 1 */ 340 }; 341 342 //============================================================================== 343 //< DMUB_STATUS>================================================================ 344 //============================================================================== 345 346 /** 347 * DMCUB scratch registers can be used to determine firmware status. 348 * Current scratch register usage is as follows: 349 * 350 * SCRATCH0: FW Boot Status register 351 * SCRATCH5: LVTMA Status Register 352 * SCRATCH15: FW Boot Options register 353 */ 354 355 /** 356 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 357 */ 358 union dmub_fw_boot_status { 359 struct { 360 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 361 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 362 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 363 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 364 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 365 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 366 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 367 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 368 } bits; /**< status bits */ 369 uint32_t all; /**< 32-bit access to status bits */ 370 }; 371 372 /** 373 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 374 */ 375 enum dmub_fw_boot_status_bit { 376 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 377 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 378 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 379 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 380 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 381 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 382 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 383 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 384 }; 385 386 /* Register bit definition for SCRATCH5 */ 387 union dmub_lvtma_status { 388 struct { 389 uint32_t psp_ok : 1; 390 uint32_t edp_on : 1; 391 uint32_t reserved : 30; 392 } bits; 393 uint32_t all; 394 }; 395 396 enum dmub_lvtma_status_bit { 397 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 398 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 399 }; 400 401 /** 402 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 403 */ 404 union dmub_fw_boot_options { 405 struct { 406 uint32_t pemu_env : 1; /**< 1 if PEMU */ 407 uint32_t fpga_env : 1; /**< 1 if FPGA */ 408 uint32_t optimized_init : 1; /**< 1 if optimized init */ 409 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 410 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 411 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 412 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 413 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 414 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 415 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 416 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 417 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 418 uint32_t power_optimization: 1; 419 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 420 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 421 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 422 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 423 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 424 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 425 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 426 uint32_t reserved : 13; /**< reserved */ 427 } bits; /**< boot bits */ 428 uint32_t all; /**< 32-bit access to bits */ 429 }; 430 431 enum dmub_fw_boot_options_bit { 432 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 433 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 434 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 435 }; 436 437 //============================================================================== 438 //</DMUB_STATUS>================================================================ 439 //============================================================================== 440 //< DMUB_VBIOS>================================================================= 441 //============================================================================== 442 443 /* 444 * enum dmub_cmd_vbios_type - VBIOS commands. 445 * 446 * Command IDs should be treated as stable ABI. 447 * Do not reuse or modify IDs. 448 */ 449 enum dmub_cmd_vbios_type { 450 /** 451 * Configures the DIG encoder. 452 */ 453 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 454 /** 455 * Controls the PHY. 456 */ 457 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 458 /** 459 * Sets the pixel clock/symbol clock. 460 */ 461 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 462 /** 463 * Enables or disables power gating. 464 */ 465 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 466 /** 467 * Controls embedded panels. 468 */ 469 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 470 /** 471 * Query DP alt status on a transmitter. 472 */ 473 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 474 /** 475 * Controls domain power gating 476 */ 477 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 478 }; 479 480 //============================================================================== 481 //</DMUB_VBIOS>================================================================= 482 //============================================================================== 483 //< DMUB_GPINT>================================================================= 484 //============================================================================== 485 486 /** 487 * The shifts and masks below may alternatively be used to format and read 488 * the command register bits. 489 */ 490 491 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 492 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 493 494 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 495 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 496 497 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 498 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 499 500 /** 501 * Command responses. 502 */ 503 504 /** 505 * Return response for DMUB_GPINT__STOP_FW command. 506 */ 507 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 508 509 /** 510 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 511 */ 512 union dmub_gpint_data_register { 513 struct { 514 uint32_t param : 16; /**< 16-bit parameter */ 515 uint32_t command_code : 12; /**< GPINT command */ 516 uint32_t status : 4; /**< Command status bit */ 517 } bits; /**< GPINT bit access */ 518 uint32_t all; /**< GPINT 32-bit access */ 519 }; 520 521 /* 522 * enum dmub_gpint_command - GPINT command to DMCUB FW 523 * 524 * Command IDs should be treated as stable ABI. 525 * Do not reuse or modify IDs. 526 */ 527 enum dmub_gpint_command { 528 /** 529 * Invalid command, ignored. 530 */ 531 DMUB_GPINT__INVALID_COMMAND = 0, 532 /** 533 * DESC: Queries the firmware version. 534 * RETURN: Firmware version. 535 */ 536 DMUB_GPINT__GET_FW_VERSION = 1, 537 /** 538 * DESC: Halts the firmware. 539 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 540 */ 541 DMUB_GPINT__STOP_FW = 2, 542 /** 543 * DESC: Get PSR state from FW. 544 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 545 */ 546 DMUB_GPINT__GET_PSR_STATE = 7, 547 /** 548 * DESC: Notifies DMCUB of the currently active streams. 549 * ARGS: Stream mask, 1 bit per active stream index. 550 */ 551 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 552 /** 553 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 554 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 555 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 556 * RETURN: PSR residency in milli-percent. 557 */ 558 DMUB_GPINT__PSR_RESIDENCY = 9, 559 560 /** 561 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 562 */ 563 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 564 }; 565 566 /** 567 * INBOX0 generic command definition 568 */ 569 union dmub_inbox0_cmd_common { 570 struct { 571 uint32_t command_code: 8; /**< INBOX0 command code */ 572 uint32_t param: 24; /**< 24-bit parameter */ 573 } bits; 574 uint32_t all; 575 }; 576 577 /** 578 * INBOX0 hw_lock command definition 579 */ 580 union dmub_inbox0_cmd_lock_hw { 581 struct { 582 uint32_t command_code: 8; 583 584 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 585 uint32_t hw_lock_client: 2; 586 587 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 588 uint32_t otg_inst: 3; 589 uint32_t opp_inst: 3; 590 uint32_t dig_inst: 3; 591 592 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 593 uint32_t lock_pipe: 1; 594 uint32_t lock_cursor: 1; 595 uint32_t lock_dig: 1; 596 uint32_t triple_buffer_lock: 1; 597 598 uint32_t lock: 1; /**< Lock */ 599 uint32_t should_release: 1; /**< Release */ 600 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 601 } bits; 602 uint32_t all; 603 }; 604 605 union dmub_inbox0_data_register { 606 union dmub_inbox0_cmd_common inbox0_cmd_common; 607 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 608 }; 609 610 enum dmub_inbox0_command { 611 /** 612 * DESC: Invalid command, ignored. 613 */ 614 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 615 /** 616 * DESC: Notification to acquire/release HW lock 617 * ARGS: 618 */ 619 DMUB_INBOX0_CMD__HW_LOCK = 1, 620 }; 621 //============================================================================== 622 //</DMUB_GPINT>================================================================= 623 //============================================================================== 624 //< DMUB_CMD>=================================================================== 625 //============================================================================== 626 627 /** 628 * Size in bytes of each DMUB command. 629 */ 630 #define DMUB_RB_CMD_SIZE 64 631 632 /** 633 * Maximum number of items in the DMUB ringbuffer. 634 */ 635 #define DMUB_RB_MAX_ENTRY 128 636 637 /** 638 * Ringbuffer size in bytes. 639 */ 640 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 641 642 /** 643 * REG_SET mask for reg offload. 644 */ 645 #define REG_SET_MASK 0xFFFF 646 647 /* 648 * enum dmub_cmd_type - DMUB inbox command. 649 * 650 * Command IDs should be treated as stable ABI. 651 * Do not reuse or modify IDs. 652 */ 653 enum dmub_cmd_type { 654 /** 655 * Invalid command. 656 */ 657 DMUB_CMD__NULL = 0, 658 /** 659 * Read modify write register sequence offload. 660 */ 661 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 662 /** 663 * Field update register sequence offload. 664 */ 665 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 666 /** 667 * Burst write sequence offload. 668 */ 669 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 670 /** 671 * Reg wait sequence offload. 672 */ 673 DMUB_CMD__REG_REG_WAIT = 4, 674 /** 675 * Workaround to avoid HUBP underflow during NV12 playback. 676 */ 677 DMUB_CMD__PLAT_54186_WA = 5, 678 /** 679 * Command type used to query FW feature caps. 680 */ 681 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 682 /** 683 * Command type used to get visual confirm color. 684 */ 685 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 686 /** 687 * Command type used for all PSR commands. 688 */ 689 DMUB_CMD__PSR = 64, 690 /** 691 * Command type used for all MALL commands. 692 */ 693 DMUB_CMD__MALL = 65, 694 /** 695 * Command type used for all ABM commands. 696 */ 697 DMUB_CMD__ABM = 66, 698 /** 699 * Command type used to update dirty rects in FW. 700 */ 701 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 702 /** 703 * Command type used to update cursor info in FW. 704 */ 705 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 706 /** 707 * Command type used for HW locking in FW. 708 */ 709 DMUB_CMD__HW_LOCK = 69, 710 /** 711 * Command type used to access DP AUX. 712 */ 713 DMUB_CMD__DP_AUX_ACCESS = 70, 714 /** 715 * Command type used for OUTBOX1 notification enable 716 */ 717 DMUB_CMD__OUTBOX1_ENABLE = 71, 718 719 /** 720 * Command type used for all idle optimization commands. 721 */ 722 DMUB_CMD__IDLE_OPT = 72, 723 /** 724 * Command type used for all clock manager commands. 725 */ 726 DMUB_CMD__CLK_MGR = 73, 727 /** 728 * Command type used for all panel control commands. 729 */ 730 DMUB_CMD__PANEL_CNTL = 74, 731 /** 732 * Command type used for <TODO:description> 733 */ 734 DMUB_CMD__CAB_FOR_SS = 75, 735 736 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 737 738 /** 739 * Command type used for interfacing with DPIA. 740 */ 741 DMUB_CMD__DPIA = 77, 742 /** 743 * Command type used for EDID CEA parsing 744 */ 745 DMUB_CMD__EDID_CEA = 79, 746 /** 747 * Command type used for getting usbc cable ID 748 */ 749 DMUB_CMD_GET_USBC_CABLE_ID = 81, 750 /** 751 * Command type used to query HPD state. 752 */ 753 DMUB_CMD__QUERY_HPD_STATE = 82, 754 /** 755 * Command type used for all VBIOS interface commands. 756 */ 757 758 /** 759 * Command type used for all SECURE_DISPLAY commands. 760 */ 761 DMUB_CMD__SECURE_DISPLAY = 85, 762 763 /** 764 * Command type used to set DPIA HPD interrupt state 765 */ 766 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 767 768 DMUB_CMD__VBIOS = 128, 769 }; 770 771 /** 772 * enum dmub_out_cmd_type - DMUB outbox commands. 773 */ 774 enum dmub_out_cmd_type { 775 /** 776 * Invalid outbox command, ignored. 777 */ 778 DMUB_OUT_CMD__NULL = 0, 779 /** 780 * Command type used for DP AUX Reply data notification 781 */ 782 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 783 /** 784 * Command type used for DP HPD event notification 785 */ 786 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 787 /** 788 * Command type used for SET_CONFIG Reply notification 789 */ 790 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 791 /** 792 * Command type used for USB4 DPIA notification 793 */ 794 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 795 }; 796 797 /* DMUB_CMD__DPIA command sub-types. */ 798 enum dmub_cmd_dpia_type { 799 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 800 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 801 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 802 }; 803 804 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 805 enum dmub_cmd_dpia_notification_type { 806 DPIA_NOTIFY__BW_ALLOCATION = 0, 807 }; 808 809 #pragma pack(push, 1) 810 811 /** 812 * struct dmub_cmd_header - Common command header fields. 813 */ 814 struct dmub_cmd_header { 815 unsigned int type : 8; /**< command type */ 816 unsigned int sub_type : 8; /**< command sub type */ 817 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 818 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 819 unsigned int reserved0 : 6; /**< reserved bits */ 820 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 821 unsigned int reserved1 : 2; /**< reserved bits */ 822 }; 823 824 /* 825 * struct dmub_cmd_read_modify_write_sequence - Read modify write 826 * 827 * 60 payload bytes can hold up to 5 sets of read modify writes, 828 * each take 3 dwords. 829 * 830 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 831 * 832 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 833 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 834 */ 835 struct dmub_cmd_read_modify_write_sequence { 836 uint32_t addr; /**< register address */ 837 uint32_t modify_mask; /**< modify mask */ 838 uint32_t modify_value; /**< modify value */ 839 }; 840 841 /** 842 * Maximum number of ops in read modify write sequence. 843 */ 844 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 845 846 /** 847 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 848 */ 849 struct dmub_rb_cmd_read_modify_write { 850 struct dmub_cmd_header header; /**< command header */ 851 /** 852 * Read modify write sequence. 853 */ 854 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 855 }; 856 857 /* 858 * Update a register with specified masks and values sequeunce 859 * 860 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 861 * 862 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 863 * 864 * 865 * USE CASE: 866 * 1. auto-increment register where additional read would update pointer and produce wrong result 867 * 2. toggle a bit without read in the middle 868 */ 869 870 struct dmub_cmd_reg_field_update_sequence { 871 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 872 uint32_t modify_value; /**< value to update with */ 873 }; 874 875 /** 876 * Maximum number of ops in field update sequence. 877 */ 878 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 879 880 /** 881 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 882 */ 883 struct dmub_rb_cmd_reg_field_update_sequence { 884 struct dmub_cmd_header header; /**< command header */ 885 uint32_t addr; /**< register address */ 886 /** 887 * Field update sequence. 888 */ 889 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 890 }; 891 892 893 /** 894 * Maximum number of burst write values. 895 */ 896 #define DMUB_BURST_WRITE_VALUES__MAX 14 897 898 /* 899 * struct dmub_rb_cmd_burst_write - Burst write 900 * 901 * support use case such as writing out LUTs. 902 * 903 * 60 payload bytes can hold up to 14 values to write to given address 904 * 905 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 906 */ 907 struct dmub_rb_cmd_burst_write { 908 struct dmub_cmd_header header; /**< command header */ 909 uint32_t addr; /**< register start address */ 910 /** 911 * Burst write register values. 912 */ 913 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 914 }; 915 916 /** 917 * struct dmub_rb_cmd_common - Common command header 918 */ 919 struct dmub_rb_cmd_common { 920 struct dmub_cmd_header header; /**< command header */ 921 /** 922 * Padding to RB_CMD_SIZE 923 */ 924 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 925 }; 926 927 /** 928 * struct dmub_cmd_reg_wait_data - Register wait data 929 */ 930 struct dmub_cmd_reg_wait_data { 931 uint32_t addr; /**< Register address */ 932 uint32_t mask; /**< Mask for register bits */ 933 uint32_t condition_field_value; /**< Value to wait for */ 934 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 935 }; 936 937 /** 938 * struct dmub_rb_cmd_reg_wait - Register wait command 939 */ 940 struct dmub_rb_cmd_reg_wait { 941 struct dmub_cmd_header header; /**< Command header */ 942 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 943 }; 944 945 /** 946 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 947 * 948 * Reprograms surface parameters to avoid underflow. 949 */ 950 struct dmub_cmd_PLAT_54186_wa { 951 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 952 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 953 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 954 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 955 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 956 struct { 957 uint8_t hubp_inst : 4; /**< HUBP instance */ 958 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 959 uint8_t immediate :1; /**< Immediate flip */ 960 uint8_t vmid : 4; /**< VMID */ 961 uint8_t grph_stereo : 1; /**< 1 if stereo */ 962 uint32_t reserved : 21; /**< Reserved */ 963 } flip_params; /**< Pageflip parameters */ 964 uint32_t reserved[9]; /**< Reserved bits */ 965 }; 966 967 /** 968 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 969 */ 970 struct dmub_rb_cmd_PLAT_54186_wa { 971 struct dmub_cmd_header header; /**< Command header */ 972 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 973 }; 974 975 /** 976 * struct dmub_rb_cmd_mall - MALL command data. 977 */ 978 struct dmub_rb_cmd_mall { 979 struct dmub_cmd_header header; /**< Common command header */ 980 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 981 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 982 uint32_t tmr_delay; /**< Timer delay */ 983 uint32_t tmr_scale; /**< Timer scale */ 984 uint16_t cursor_width; /**< Cursor width in pixels */ 985 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 986 uint16_t cursor_height; /**< Cursor height in pixels */ 987 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 988 uint8_t debug_bits; /**< Debug bits */ 989 990 uint8_t reserved1; /**< Reserved bits */ 991 uint8_t reserved2; /**< Reserved bits */ 992 }; 993 994 /** 995 * enum dmub_cmd_cab_type - CAB command data. 996 */ 997 enum dmub_cmd_cab_type { 998 /** 999 * No idle optimizations (i.e. no CAB) 1000 */ 1001 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1002 /** 1003 * No DCN requests for memory 1004 */ 1005 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1006 /** 1007 * Fit surfaces in CAB (i.e. CAB enable) 1008 */ 1009 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1010 }; 1011 1012 /** 1013 * struct dmub_rb_cmd_cab - CAB command data. 1014 */ 1015 struct dmub_rb_cmd_cab_for_ss { 1016 struct dmub_cmd_header header; 1017 uint8_t cab_alloc_ways; /* total number of ways */ 1018 uint8_t debug_bits; /* debug bits */ 1019 }; 1020 1021 /** 1022 * Enum for indicating which MCLK switch mode per pipe 1023 */ 1024 enum mclk_switch_mode { 1025 NONE = 0, 1026 FPO = 1, 1027 SUBVP = 2, 1028 VBLANK = 3, 1029 }; 1030 1031 /* Per pipe struct which stores the MCLK switch mode 1032 * data to be sent to DMUB. 1033 * Named "v2" for now -- once FPO and SUBVP are fully merged 1034 * the type name can be updated 1035 */ 1036 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1037 union { 1038 struct { 1039 uint32_t pix_clk_100hz; 1040 uint16_t main_vblank_start; 1041 uint16_t main_vblank_end; 1042 uint16_t mall_region_lines; 1043 uint16_t prefetch_lines; 1044 uint16_t prefetch_to_mall_start_lines; 1045 uint16_t processing_delay_lines; 1046 uint16_t htotal; // required to calculate line time for multi-display cases 1047 uint16_t vtotal; 1048 uint8_t main_pipe_index; 1049 uint8_t phantom_pipe_index; 1050 /* Since the microschedule is calculated in terms of OTG lines, 1051 * include any scaling factors to make sure when we get accurate 1052 * conversion when programming MALL_START_LINE (which is in terms 1053 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1054 * is 1/2 (numerator = 1, denominator = 2). 1055 */ 1056 uint8_t scale_factor_numerator; 1057 uint8_t scale_factor_denominator; 1058 uint8_t is_drr; 1059 uint8_t main_split_pipe_index; 1060 uint8_t phantom_split_pipe_index; 1061 } subvp_data; 1062 1063 struct { 1064 uint32_t pix_clk_100hz; 1065 uint16_t vblank_start; 1066 uint16_t vblank_end; 1067 uint16_t vstartup_start; 1068 uint16_t vtotal; 1069 uint16_t htotal; 1070 uint8_t vblank_pipe_index; 1071 uint8_t padding[1]; 1072 struct { 1073 uint8_t drr_in_use; 1074 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1075 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1076 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1077 uint8_t use_ramping; // Use ramping or not 1078 uint8_t drr_vblank_start_margin; 1079 } drr_info; // DRR considered as part of SubVP + VBLANK case 1080 } vblank_data; 1081 } pipe_config; 1082 1083 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1084 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1085 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1086 */ 1087 uint8_t mode; // enum mclk_switch_mode 1088 }; 1089 1090 /** 1091 * Config data for Sub-VP and FPO 1092 * Named "v2" for now -- once FPO and SUBVP are fully merged 1093 * the type name can be updated 1094 */ 1095 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1096 uint16_t watermark_a_cache; 1097 uint8_t vertical_int_margin_us; 1098 uint8_t pstate_allow_width_us; 1099 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1100 }; 1101 1102 /** 1103 * DMUB rb command definition for Sub-VP and FPO 1104 * Named "v2" for now -- once FPO and SUBVP are fully merged 1105 * the type name can be updated 1106 */ 1107 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1108 struct dmub_cmd_header header; 1109 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1110 }; 1111 1112 /** 1113 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1114 */ 1115 enum dmub_cmd_idle_opt_type { 1116 /** 1117 * DCN hardware restore. 1118 */ 1119 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1120 1121 /** 1122 * DCN hardware save. 1123 */ 1124 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1125 1126 /** 1127 * DCN hardware notify idle. 1128 */ 1129 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1130 }; 1131 1132 /** 1133 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1134 */ 1135 struct dmub_rb_cmd_idle_opt_dcn_restore { 1136 struct dmub_cmd_header header; /**< header */ 1137 }; 1138 1139 /** 1140 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1141 */ 1142 struct dmub_dcn_notify_idle_cntl_data { 1143 uint8_t driver_idle; 1144 uint8_t pad[1]; 1145 }; 1146 1147 /** 1148 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1149 */ 1150 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1151 struct dmub_cmd_header header; /**< header */ 1152 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1153 }; 1154 1155 /** 1156 * struct dmub_clocks - Clock update notification. 1157 */ 1158 struct dmub_clocks { 1159 uint32_t dispclk_khz; /**< dispclk kHz */ 1160 uint32_t dppclk_khz; /**< dppclk kHz */ 1161 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1162 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1163 }; 1164 1165 /** 1166 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1167 */ 1168 enum dmub_cmd_clk_mgr_type { 1169 /** 1170 * Notify DMCUB of clock update. 1171 */ 1172 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1173 }; 1174 1175 /** 1176 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1177 */ 1178 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1179 struct dmub_cmd_header header; /**< header */ 1180 struct dmub_clocks clocks; /**< clock data */ 1181 }; 1182 1183 /** 1184 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1185 */ 1186 struct dmub_cmd_digx_encoder_control_data { 1187 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1188 }; 1189 1190 /** 1191 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1192 */ 1193 struct dmub_rb_cmd_digx_encoder_control { 1194 struct dmub_cmd_header header; /**< header */ 1195 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1196 }; 1197 1198 /** 1199 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1200 */ 1201 struct dmub_cmd_set_pixel_clock_data { 1202 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1203 }; 1204 1205 /** 1206 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1207 */ 1208 struct dmub_rb_cmd_set_pixel_clock { 1209 struct dmub_cmd_header header; /**< header */ 1210 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1211 }; 1212 1213 /** 1214 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1215 */ 1216 struct dmub_cmd_enable_disp_power_gating_data { 1217 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1218 }; 1219 1220 /** 1221 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1222 */ 1223 struct dmub_rb_cmd_enable_disp_power_gating { 1224 struct dmub_cmd_header header; /**< header */ 1225 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1226 }; 1227 1228 /** 1229 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1230 */ 1231 struct dmub_dig_transmitter_control_data_v1_7 { 1232 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1233 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1234 union { 1235 uint8_t digmode; /**< enum atom_encode_mode_def */ 1236 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1237 } mode_laneset; 1238 uint8_t lanenum; /**< Number of lanes */ 1239 union { 1240 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1241 } symclk_units; 1242 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1243 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1244 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1245 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1246 uint8_t reserved1; /**< For future use */ 1247 uint8_t reserved2[3]; /**< For future use */ 1248 uint32_t reserved3[11]; /**< For future use */ 1249 }; 1250 1251 /** 1252 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1253 */ 1254 union dmub_cmd_dig1_transmitter_control_data { 1255 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1256 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1257 }; 1258 1259 /** 1260 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1261 */ 1262 struct dmub_rb_cmd_dig1_transmitter_control { 1263 struct dmub_cmd_header header; /**< header */ 1264 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1265 }; 1266 1267 /** 1268 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1269 */ 1270 struct dmub_rb_cmd_domain_control_data { 1271 uint8_t inst : 6; /**< DOMAIN instance to control */ 1272 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1273 uint8_t reserved[3]; /**< Reserved for future use */ 1274 }; 1275 1276 /** 1277 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1278 */ 1279 struct dmub_rb_cmd_domain_control { 1280 struct dmub_cmd_header header; /**< header */ 1281 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1282 }; 1283 1284 /** 1285 * DPIA tunnel command parameters. 1286 */ 1287 struct dmub_cmd_dig_dpia_control_data { 1288 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1289 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1290 union { 1291 uint8_t digmode; /** enum atom_encode_mode_def */ 1292 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1293 } mode_laneset; 1294 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1295 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1296 uint8_t hpdsel; /** =0: HPD is not assigned */ 1297 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1298 uint8_t dpia_id; /** Index of DPIA */ 1299 uint8_t fec_rdy : 1; 1300 uint8_t reserved : 7; 1301 uint32_t reserved1; 1302 }; 1303 1304 /** 1305 * DMUB command for DPIA tunnel control. 1306 */ 1307 struct dmub_rb_cmd_dig1_dpia_control { 1308 struct dmub_cmd_header header; 1309 struct dmub_cmd_dig_dpia_control_data dpia_control; 1310 }; 1311 1312 /** 1313 * SET_CONFIG Command Payload 1314 */ 1315 struct set_config_cmd_payload { 1316 uint8_t msg_type; /* set config message type */ 1317 uint8_t msg_data; /* set config message data */ 1318 }; 1319 1320 /** 1321 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1322 */ 1323 struct dmub_cmd_set_config_control_data { 1324 struct set_config_cmd_payload cmd_pkt; 1325 uint8_t instance; /* DPIA instance */ 1326 uint8_t immed_status; /* Immediate status returned in case of error */ 1327 }; 1328 1329 /** 1330 * DMUB command structure for SET_CONFIG command. 1331 */ 1332 struct dmub_rb_cmd_set_config_access { 1333 struct dmub_cmd_header header; /* header */ 1334 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1335 }; 1336 1337 /** 1338 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1339 */ 1340 struct dmub_cmd_mst_alloc_slots_control_data { 1341 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1342 uint8_t instance; /* DPIA instance */ 1343 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1344 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1345 }; 1346 1347 /** 1348 * DMUB command structure for SET_ command. 1349 */ 1350 struct dmub_rb_cmd_set_mst_alloc_slots { 1351 struct dmub_cmd_header header; /* header */ 1352 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1353 }; 1354 1355 /** 1356 * DMUB command structure for DPIA HPD int enable control. 1357 */ 1358 struct dmub_rb_cmd_dpia_hpd_int_enable { 1359 struct dmub_cmd_header header; /* header */ 1360 uint32_t enable; /* dpia hpd interrupt enable */ 1361 }; 1362 1363 /** 1364 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1365 */ 1366 struct dmub_rb_cmd_dpphy_init { 1367 struct dmub_cmd_header header; /**< header */ 1368 uint8_t reserved[60]; /**< reserved bits */ 1369 }; 1370 1371 /** 1372 * enum dp_aux_request_action - DP AUX request command listing. 1373 * 1374 * 4 AUX request command bits are shifted to high nibble. 1375 */ 1376 enum dp_aux_request_action { 1377 /** I2C-over-AUX write request */ 1378 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1379 /** I2C-over-AUX read request */ 1380 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1381 /** I2C-over-AUX write status request */ 1382 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1383 /** I2C-over-AUX write request with MOT=1 */ 1384 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1385 /** I2C-over-AUX read request with MOT=1 */ 1386 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1387 /** I2C-over-AUX write status request with MOT=1 */ 1388 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1389 /** Native AUX write request */ 1390 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1391 /** Native AUX read request */ 1392 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1393 }; 1394 1395 /** 1396 * enum aux_return_code_type - DP AUX process return code listing. 1397 */ 1398 enum aux_return_code_type { 1399 /** AUX process succeeded */ 1400 AUX_RET_SUCCESS = 0, 1401 /** AUX process failed with unknown reason */ 1402 AUX_RET_ERROR_UNKNOWN, 1403 /** AUX process completed with invalid reply */ 1404 AUX_RET_ERROR_INVALID_REPLY, 1405 /** AUX process timed out */ 1406 AUX_RET_ERROR_TIMEOUT, 1407 /** HPD was low during AUX process */ 1408 AUX_RET_ERROR_HPD_DISCON, 1409 /** Failed to acquire AUX engine */ 1410 AUX_RET_ERROR_ENGINE_ACQUIRE, 1411 /** AUX request not supported */ 1412 AUX_RET_ERROR_INVALID_OPERATION, 1413 /** AUX process not available */ 1414 AUX_RET_ERROR_PROTOCOL_ERROR, 1415 }; 1416 1417 /** 1418 * enum aux_channel_type - DP AUX channel type listing. 1419 */ 1420 enum aux_channel_type { 1421 /** AUX thru Legacy DP AUX */ 1422 AUX_CHANNEL_LEGACY_DDC, 1423 /** AUX thru DPIA DP tunneling */ 1424 AUX_CHANNEL_DPIA 1425 }; 1426 1427 /** 1428 * struct aux_transaction_parameters - DP AUX request transaction data 1429 */ 1430 struct aux_transaction_parameters { 1431 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1432 uint8_t action; /**< enum dp_aux_request_action */ 1433 uint8_t length; /**< DP AUX request data length */ 1434 uint8_t reserved; /**< For future use */ 1435 uint32_t address; /**< DP AUX address */ 1436 uint8_t data[16]; /**< DP AUX write data */ 1437 }; 1438 1439 /** 1440 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1441 */ 1442 struct dmub_cmd_dp_aux_control_data { 1443 uint8_t instance; /**< AUX instance or DPIA instance */ 1444 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1445 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1446 uint8_t reserved0; /**< For future use */ 1447 uint16_t timeout; /**< timeout time in us */ 1448 uint16_t reserved1; /**< For future use */ 1449 enum aux_channel_type type; /**< enum aux_channel_type */ 1450 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1451 }; 1452 1453 /** 1454 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1455 */ 1456 struct dmub_rb_cmd_dp_aux_access { 1457 /** 1458 * Command header. 1459 */ 1460 struct dmub_cmd_header header; 1461 /** 1462 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1463 */ 1464 struct dmub_cmd_dp_aux_control_data aux_control; 1465 }; 1466 1467 /** 1468 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1469 */ 1470 struct dmub_rb_cmd_outbox1_enable { 1471 /** 1472 * Command header. 1473 */ 1474 struct dmub_cmd_header header; 1475 /** 1476 * enable: 0x0 -> disable outbox1 notification (default value) 1477 * 0x1 -> enable outbox1 notification 1478 */ 1479 uint32_t enable; 1480 }; 1481 1482 /* DP AUX Reply command - OutBox Cmd */ 1483 /** 1484 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1485 */ 1486 struct aux_reply_data { 1487 /** 1488 * Aux cmd 1489 */ 1490 uint8_t command; 1491 /** 1492 * Aux reply data length (max: 16 bytes) 1493 */ 1494 uint8_t length; 1495 /** 1496 * Alignment only 1497 */ 1498 uint8_t pad[2]; 1499 /** 1500 * Aux reply data 1501 */ 1502 uint8_t data[16]; 1503 }; 1504 1505 /** 1506 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1507 */ 1508 struct aux_reply_control_data { 1509 /** 1510 * Reserved for future use 1511 */ 1512 uint32_t handle; 1513 /** 1514 * Aux Instance 1515 */ 1516 uint8_t instance; 1517 /** 1518 * Aux transaction result: definition in enum aux_return_code_type 1519 */ 1520 uint8_t result; 1521 /** 1522 * Alignment only 1523 */ 1524 uint16_t pad; 1525 }; 1526 1527 /** 1528 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1529 */ 1530 struct dmub_rb_cmd_dp_aux_reply { 1531 /** 1532 * Command header. 1533 */ 1534 struct dmub_cmd_header header; 1535 /** 1536 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1537 */ 1538 struct aux_reply_control_data control; 1539 /** 1540 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1541 */ 1542 struct aux_reply_data reply_data; 1543 }; 1544 1545 /* DP HPD Notify command - OutBox Cmd */ 1546 /** 1547 * DP HPD Type 1548 */ 1549 enum dp_hpd_type { 1550 /** 1551 * Normal DP HPD 1552 */ 1553 DP_HPD = 0, 1554 /** 1555 * DP HPD short pulse 1556 */ 1557 DP_IRQ 1558 }; 1559 1560 /** 1561 * DP HPD Status 1562 */ 1563 enum dp_hpd_status { 1564 /** 1565 * DP_HPD status low 1566 */ 1567 DP_HPD_UNPLUG = 0, 1568 /** 1569 * DP_HPD status high 1570 */ 1571 DP_HPD_PLUG 1572 }; 1573 1574 /** 1575 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1576 */ 1577 struct dp_hpd_data { 1578 /** 1579 * DP HPD instance 1580 */ 1581 uint8_t instance; 1582 /** 1583 * HPD type 1584 */ 1585 uint8_t hpd_type; 1586 /** 1587 * HPD status: only for type: DP_HPD to indicate status 1588 */ 1589 uint8_t hpd_status; 1590 /** 1591 * Alignment only 1592 */ 1593 uint8_t pad; 1594 }; 1595 1596 /** 1597 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1598 */ 1599 struct dmub_rb_cmd_dp_hpd_notify { 1600 /** 1601 * Command header. 1602 */ 1603 struct dmub_cmd_header header; 1604 /** 1605 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1606 */ 1607 struct dp_hpd_data hpd_data; 1608 }; 1609 1610 /** 1611 * Definition of a SET_CONFIG reply from DPOA. 1612 */ 1613 enum set_config_status { 1614 SET_CONFIG_PENDING = 0, 1615 SET_CONFIG_ACK_RECEIVED, 1616 SET_CONFIG_RX_TIMEOUT, 1617 SET_CONFIG_UNKNOWN_ERROR, 1618 }; 1619 1620 /** 1621 * Definition of a set_config reply 1622 */ 1623 struct set_config_reply_control_data { 1624 uint8_t instance; /* DPIA Instance */ 1625 uint8_t status; /* Set Config reply */ 1626 uint16_t pad; /* Alignment */ 1627 }; 1628 1629 /** 1630 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1631 */ 1632 struct dmub_rb_cmd_dp_set_config_reply { 1633 struct dmub_cmd_header header; 1634 struct set_config_reply_control_data set_config_reply_control; 1635 }; 1636 1637 /** 1638 * Definition of a DPIA notification header 1639 */ 1640 struct dpia_notification_header { 1641 uint8_t instance; /**< DPIA Instance */ 1642 uint8_t reserved[3]; 1643 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 1644 }; 1645 1646 /** 1647 * Definition of the common data struct of DPIA notification 1648 */ 1649 struct dpia_notification_common { 1650 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 1651 - sizeof(struct dpia_notification_header)]; 1652 }; 1653 1654 /** 1655 * Definition of a DPIA notification data 1656 */ 1657 struct dpia_bw_allocation_notify_data { 1658 union { 1659 struct { 1660 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 1661 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 1662 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 1663 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 1664 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 1665 uint16_t reserved: 11; /**< Reserved */ 1666 } bits; 1667 1668 uint16_t flags; 1669 }; 1670 1671 uint8_t cm_id; /**< CM ID */ 1672 uint8_t group_id; /**< Group ID */ 1673 uint8_t granularity; /**< BW Allocation Granularity */ 1674 uint8_t estimated_bw; /**< Estimated_BW */ 1675 uint8_t allocated_bw; /**< Allocated_BW */ 1676 uint8_t reserved; 1677 }; 1678 1679 /** 1680 * union dpia_notify_data_type - DPIA Notification in Outbox command 1681 */ 1682 union dpia_notification_data { 1683 /** 1684 * DPIA Notification for common data struct 1685 */ 1686 struct dpia_notification_common common_data; 1687 1688 /** 1689 * DPIA Notification for DP BW Allocation support 1690 */ 1691 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 1692 }; 1693 1694 /** 1695 * Definition of a DPIA notification payload 1696 */ 1697 struct dpia_notification_payload { 1698 struct dpia_notification_header header; 1699 union dpia_notification_data data; /**< DPIA notification payload data */ 1700 }; 1701 1702 /** 1703 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 1704 */ 1705 struct dmub_rb_cmd_dpia_notification { 1706 struct dmub_cmd_header header; /**< DPIA notification header */ 1707 struct dpia_notification_payload payload; /**< DPIA notification payload */ 1708 }; 1709 1710 /** 1711 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1712 */ 1713 struct dmub_cmd_hpd_state_query_data { 1714 uint8_t instance; /**< HPD instance or DPIA instance */ 1715 uint8_t result; /**< For returning HPD state */ 1716 uint16_t pad; /** < Alignment */ 1717 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1718 enum aux_return_code_type status; /**< for returning the status of command */ 1719 }; 1720 1721 /** 1722 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1723 */ 1724 struct dmub_rb_cmd_query_hpd_state { 1725 /** 1726 * Command header. 1727 */ 1728 struct dmub_cmd_header header; 1729 /** 1730 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1731 */ 1732 struct dmub_cmd_hpd_state_query_data data; 1733 }; 1734 1735 /* 1736 * Command IDs should be treated as stable ABI. 1737 * Do not reuse or modify IDs. 1738 */ 1739 1740 /** 1741 * PSR command sub-types. 1742 */ 1743 enum dmub_cmd_psr_type { 1744 /** 1745 * Set PSR version support. 1746 */ 1747 DMUB_CMD__PSR_SET_VERSION = 0, 1748 /** 1749 * Copy driver-calculated parameters to PSR state. 1750 */ 1751 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1752 /** 1753 * Enable PSR. 1754 */ 1755 DMUB_CMD__PSR_ENABLE = 2, 1756 1757 /** 1758 * Disable PSR. 1759 */ 1760 DMUB_CMD__PSR_DISABLE = 3, 1761 1762 /** 1763 * Set PSR level. 1764 * PSR level is a 16-bit value dicated by driver that 1765 * will enable/disable different functionality. 1766 */ 1767 DMUB_CMD__PSR_SET_LEVEL = 4, 1768 1769 /** 1770 * Forces PSR enabled until an explicit PSR disable call. 1771 */ 1772 DMUB_CMD__PSR_FORCE_STATIC = 5, 1773 /** 1774 * Set vtotal in psr active for FreeSync PSR. 1775 */ 1776 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1777 /** 1778 * Set PSR power option 1779 */ 1780 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1781 }; 1782 1783 enum dmub_cmd_fams_type { 1784 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1785 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1786 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1787 /** 1788 * For SubVP set manual trigger in FW because it 1789 * triggers DRR_UPDATE_PENDING which SubVP relies 1790 * on (for any SubVP cases that use a DRR display) 1791 */ 1792 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1793 }; 1794 1795 /** 1796 * PSR versions. 1797 */ 1798 enum psr_version { 1799 /** 1800 * PSR version 1. 1801 */ 1802 PSR_VERSION_1 = 0, 1803 /** 1804 * Freesync PSR SU. 1805 */ 1806 PSR_VERSION_SU_1 = 1, 1807 /** 1808 * PSR not supported. 1809 */ 1810 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1811 }; 1812 1813 /** 1814 * enum dmub_cmd_mall_type - MALL commands 1815 */ 1816 enum dmub_cmd_mall_type { 1817 /** 1818 * Allows display refresh from MALL. 1819 */ 1820 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1821 /** 1822 * Disallows display refresh from MALL. 1823 */ 1824 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1825 /** 1826 * Cursor copy for MALL. 1827 */ 1828 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1829 /** 1830 * Controls DF requests. 1831 */ 1832 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1833 }; 1834 1835 /** 1836 * PHY Link rate for DP. 1837 */ 1838 enum phy_link_rate { 1839 /** 1840 * not supported. 1841 */ 1842 PHY_RATE_UNKNOWN = 0, 1843 /** 1844 * Rate_1 (RBR) - 1.62 Gbps/Lane 1845 */ 1846 PHY_RATE_162 = 1, 1847 /** 1848 * Rate_2 - 2.16 Gbps/Lane 1849 */ 1850 PHY_RATE_216 = 2, 1851 /** 1852 * Rate_3 - 2.43 Gbps/Lane 1853 */ 1854 PHY_RATE_243 = 3, 1855 /** 1856 * Rate_4 (HBR) - 2.70 Gbps/Lane 1857 */ 1858 PHY_RATE_270 = 4, 1859 /** 1860 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1861 */ 1862 PHY_RATE_324 = 5, 1863 /** 1864 * Rate_6 - 4.32 Gbps/Lane 1865 */ 1866 PHY_RATE_432 = 6, 1867 /** 1868 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1869 */ 1870 PHY_RATE_540 = 7, 1871 /** 1872 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1873 */ 1874 PHY_RATE_810 = 8, 1875 /** 1876 * UHBR10 - 10.0 Gbps/Lane 1877 */ 1878 PHY_RATE_1000 = 9, 1879 /** 1880 * UHBR13.5 - 13.5 Gbps/Lane 1881 */ 1882 PHY_RATE_1350 = 10, 1883 /** 1884 * UHBR10 - 20.0 Gbps/Lane 1885 */ 1886 PHY_RATE_2000 = 11, 1887 }; 1888 1889 /** 1890 * enum dmub_phy_fsm_state - PHY FSM states. 1891 * PHY FSM state to transit to during PSR enable/disable. 1892 */ 1893 enum dmub_phy_fsm_state { 1894 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1895 DMUB_PHY_FSM_RESET, 1896 DMUB_PHY_FSM_RESET_RELEASED, 1897 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1898 DMUB_PHY_FSM_INITIALIZED, 1899 DMUB_PHY_FSM_CALIBRATED, 1900 DMUB_PHY_FSM_CALIBRATED_LP, 1901 DMUB_PHY_FSM_CALIBRATED_PG, 1902 DMUB_PHY_FSM_POWER_DOWN, 1903 DMUB_PHY_FSM_PLL_EN, 1904 DMUB_PHY_FSM_TX_EN, 1905 DMUB_PHY_FSM_FAST_LP, 1906 }; 1907 1908 /** 1909 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1910 */ 1911 struct dmub_cmd_psr_copy_settings_data { 1912 /** 1913 * Flags that can be set by driver to change some PSR behaviour. 1914 */ 1915 union dmub_psr_debug_flags debug; 1916 /** 1917 * 16-bit value dicated by driver that will enable/disable different functionality. 1918 */ 1919 uint16_t psr_level; 1920 /** 1921 * DPP HW instance. 1922 */ 1923 uint8_t dpp_inst; 1924 /** 1925 * MPCC HW instance. 1926 * Not used in dmub fw, 1927 * dmub fw will get active opp by reading odm registers. 1928 */ 1929 uint8_t mpcc_inst; 1930 /** 1931 * OPP HW instance. 1932 * Not used in dmub fw, 1933 * dmub fw will get active opp by reading odm registers. 1934 */ 1935 uint8_t opp_inst; 1936 /** 1937 * OTG HW instance. 1938 */ 1939 uint8_t otg_inst; 1940 /** 1941 * DIG FE HW instance. 1942 */ 1943 uint8_t digfe_inst; 1944 /** 1945 * DIG BE HW instance. 1946 */ 1947 uint8_t digbe_inst; 1948 /** 1949 * DP PHY HW instance. 1950 */ 1951 uint8_t dpphy_inst; 1952 /** 1953 * AUX HW instance. 1954 */ 1955 uint8_t aux_inst; 1956 /** 1957 * Determines if SMU optimzations are enabled/disabled. 1958 */ 1959 uint8_t smu_optimizations_en; 1960 /** 1961 * Unused. 1962 * TODO: Remove. 1963 */ 1964 uint8_t frame_delay; 1965 /** 1966 * If RFB setup time is greater than the total VBLANK time, 1967 * it is not possible for the sink to capture the video frame 1968 * in the same frame the SDP is sent. In this case, 1969 * the frame capture indication bit should be set and an extra 1970 * static frame should be transmitted to the sink. 1971 */ 1972 uint8_t frame_cap_ind; 1973 /** 1974 * Granularity of Y offset supported by sink. 1975 */ 1976 uint8_t su_y_granularity; 1977 /** 1978 * Indicates whether sink should start capturing 1979 * immediately following active scan line, 1980 * or starting with the 2nd active scan line. 1981 */ 1982 uint8_t line_capture_indication; 1983 /** 1984 * Multi-display optimizations are implemented on certain ASICs. 1985 */ 1986 uint8_t multi_disp_optimizations_en; 1987 /** 1988 * The last possible line SDP may be transmitted without violating 1989 * the RFB setup time or entering the active video frame. 1990 */ 1991 uint16_t init_sdp_deadline; 1992 /** 1993 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1994 */ 1995 uint8_t rate_control_caps ; 1996 /* 1997 * Force PSRSU always doing full frame update 1998 */ 1999 uint8_t force_ffu_mode; 2000 /** 2001 * Length of each horizontal line in us. 2002 */ 2003 uint32_t line_time_in_us; 2004 /** 2005 * FEC enable status in driver 2006 */ 2007 uint8_t fec_enable_status; 2008 /** 2009 * FEC re-enable delay when PSR exit. 2010 * unit is 100us, range form 0~255(0xFF). 2011 */ 2012 uint8_t fec_enable_delay_in100us; 2013 /** 2014 * PSR control version. 2015 */ 2016 uint8_t cmd_version; 2017 /** 2018 * Panel Instance. 2019 * Panel instance to identify which psr_state to use 2020 * Currently the support is only for 0 or 1 2021 */ 2022 uint8_t panel_inst; 2023 /* 2024 * DSC enable status in driver 2025 */ 2026 uint8_t dsc_enable_status; 2027 /* 2028 * Use FSM state for PSR power up/down 2029 */ 2030 uint8_t use_phy_fsm; 2031 /** 2032 * frame delay for frame re-lock 2033 */ 2034 uint8_t relock_delay_frame_cnt; 2035 /** 2036 * Explicit padding to 2 byte boundary. 2037 */ 2038 uint8_t pad3; 2039 /** 2040 * DSC Slice height. 2041 */ 2042 uint16_t dsc_slice_height; 2043 /** 2044 * Explicit padding to 4 byte boundary. 2045 */ 2046 uint16_t pad; 2047 }; 2048 2049 /** 2050 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2051 */ 2052 struct dmub_rb_cmd_psr_copy_settings { 2053 /** 2054 * Command header. 2055 */ 2056 struct dmub_cmd_header header; 2057 /** 2058 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2059 */ 2060 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2061 }; 2062 2063 /** 2064 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2065 */ 2066 struct dmub_cmd_psr_set_level_data { 2067 /** 2068 * 16-bit value dicated by driver that will enable/disable different functionality. 2069 */ 2070 uint16_t psr_level; 2071 /** 2072 * PSR control version. 2073 */ 2074 uint8_t cmd_version; 2075 /** 2076 * Panel Instance. 2077 * Panel instance to identify which psr_state to use 2078 * Currently the support is only for 0 or 1 2079 */ 2080 uint8_t panel_inst; 2081 }; 2082 2083 /** 2084 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2085 */ 2086 struct dmub_rb_cmd_psr_set_level { 2087 /** 2088 * Command header. 2089 */ 2090 struct dmub_cmd_header header; 2091 /** 2092 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2093 */ 2094 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2095 }; 2096 2097 struct dmub_rb_cmd_psr_enable_data { 2098 /** 2099 * PSR control version. 2100 */ 2101 uint8_t cmd_version; 2102 /** 2103 * Panel Instance. 2104 * Panel instance to identify which psr_state to use 2105 * Currently the support is only for 0 or 1 2106 */ 2107 uint8_t panel_inst; 2108 /** 2109 * Phy state to enter. 2110 * Values to use are defined in dmub_phy_fsm_state 2111 */ 2112 uint8_t phy_fsm_state; 2113 /** 2114 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2115 * Set this using enum phy_link_rate. 2116 * This does not support HDMI/DP2 for now. 2117 */ 2118 uint8_t phy_rate; 2119 }; 2120 2121 /** 2122 * Definition of a DMUB_CMD__PSR_ENABLE command. 2123 * PSR enable/disable is controlled using the sub_type. 2124 */ 2125 struct dmub_rb_cmd_psr_enable { 2126 /** 2127 * Command header. 2128 */ 2129 struct dmub_cmd_header header; 2130 2131 struct dmub_rb_cmd_psr_enable_data data; 2132 }; 2133 2134 /** 2135 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2136 */ 2137 struct dmub_cmd_psr_set_version_data { 2138 /** 2139 * PSR version that FW should implement. 2140 */ 2141 enum psr_version version; 2142 /** 2143 * PSR control version. 2144 */ 2145 uint8_t cmd_version; 2146 /** 2147 * Panel Instance. 2148 * Panel instance to identify which psr_state to use 2149 * Currently the support is only for 0 or 1 2150 */ 2151 uint8_t panel_inst; 2152 /** 2153 * Explicit padding to 4 byte boundary. 2154 */ 2155 uint8_t pad[2]; 2156 }; 2157 2158 /** 2159 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2160 */ 2161 struct dmub_rb_cmd_psr_set_version { 2162 /** 2163 * Command header. 2164 */ 2165 struct dmub_cmd_header header; 2166 /** 2167 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2168 */ 2169 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2170 }; 2171 2172 struct dmub_cmd_psr_force_static_data { 2173 /** 2174 * PSR control version. 2175 */ 2176 uint8_t cmd_version; 2177 /** 2178 * Panel Instance. 2179 * Panel instance to identify which psr_state to use 2180 * Currently the support is only for 0 or 1 2181 */ 2182 uint8_t panel_inst; 2183 /** 2184 * Explicit padding to 4 byte boundary. 2185 */ 2186 uint8_t pad[2]; 2187 }; 2188 2189 /** 2190 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2191 */ 2192 struct dmub_rb_cmd_psr_force_static { 2193 /** 2194 * Command header. 2195 */ 2196 struct dmub_cmd_header header; 2197 /** 2198 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2199 */ 2200 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2201 }; 2202 2203 /** 2204 * PSR SU debug flags. 2205 */ 2206 union dmub_psr_su_debug_flags { 2207 /** 2208 * PSR SU debug flags. 2209 */ 2210 struct { 2211 /** 2212 * Update dirty rect in SW only. 2213 */ 2214 uint8_t update_dirty_rect_only : 1; 2215 /** 2216 * Reset the cursor/plane state before processing the call. 2217 */ 2218 uint8_t reset_state : 1; 2219 } bitfields; 2220 2221 /** 2222 * Union for debug flags. 2223 */ 2224 uint32_t u32All; 2225 }; 2226 2227 /** 2228 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2229 * This triggers a selective update for PSR SU. 2230 */ 2231 struct dmub_cmd_update_dirty_rect_data { 2232 /** 2233 * Dirty rects from OS. 2234 */ 2235 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2236 /** 2237 * PSR SU debug flags. 2238 */ 2239 union dmub_psr_su_debug_flags debug_flags; 2240 /** 2241 * OTG HW instance. 2242 */ 2243 uint8_t pipe_idx; 2244 /** 2245 * Number of dirty rects. 2246 */ 2247 uint8_t dirty_rect_count; 2248 /** 2249 * PSR control version. 2250 */ 2251 uint8_t cmd_version; 2252 /** 2253 * Panel Instance. 2254 * Panel instance to identify which psr_state to use 2255 * Currently the support is only for 0 or 1 2256 */ 2257 uint8_t panel_inst; 2258 }; 2259 2260 /** 2261 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2262 */ 2263 struct dmub_rb_cmd_update_dirty_rect { 2264 /** 2265 * Command header. 2266 */ 2267 struct dmub_cmd_header header; 2268 /** 2269 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2270 */ 2271 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2272 }; 2273 2274 /** 2275 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2276 */ 2277 union dmub_reg_cursor_control_cfg { 2278 struct { 2279 uint32_t cur_enable: 1; 2280 uint32_t reser0: 3; 2281 uint32_t cur_2x_magnify: 1; 2282 uint32_t reser1: 3; 2283 uint32_t mode: 3; 2284 uint32_t reser2: 5; 2285 uint32_t pitch: 2; 2286 uint32_t reser3: 6; 2287 uint32_t line_per_chunk: 5; 2288 uint32_t reser4: 3; 2289 } bits; 2290 uint32_t raw; 2291 }; 2292 struct dmub_cursor_position_cache_hubp { 2293 union dmub_reg_cursor_control_cfg cur_ctl; 2294 union dmub_reg_position_cfg { 2295 struct { 2296 uint32_t cur_x_pos: 16; 2297 uint32_t cur_y_pos: 16; 2298 } bits; 2299 uint32_t raw; 2300 } position; 2301 union dmub_reg_hot_spot_cfg { 2302 struct { 2303 uint32_t hot_x: 16; 2304 uint32_t hot_y: 16; 2305 } bits; 2306 uint32_t raw; 2307 } hot_spot; 2308 union dmub_reg_dst_offset_cfg { 2309 struct { 2310 uint32_t dst_x_offset: 13; 2311 uint32_t reserved: 19; 2312 } bits; 2313 uint32_t raw; 2314 } dst_offset; 2315 }; 2316 2317 union dmub_reg_cur0_control_cfg { 2318 struct { 2319 uint32_t cur0_enable: 1; 2320 uint32_t expansion_mode: 1; 2321 uint32_t reser0: 1; 2322 uint32_t cur0_rom_en: 1; 2323 uint32_t mode: 3; 2324 uint32_t reserved: 25; 2325 } bits; 2326 uint32_t raw; 2327 }; 2328 struct dmub_cursor_position_cache_dpp { 2329 union dmub_reg_cur0_control_cfg cur0_ctl; 2330 }; 2331 struct dmub_cursor_position_cfg { 2332 struct dmub_cursor_position_cache_hubp pHubp; 2333 struct dmub_cursor_position_cache_dpp pDpp; 2334 uint8_t pipe_idx; 2335 /* 2336 * Padding is required. To be 4 Bytes Aligned. 2337 */ 2338 uint8_t padding[3]; 2339 }; 2340 2341 struct dmub_cursor_attribute_cache_hubp { 2342 uint32_t SURFACE_ADDR_HIGH; 2343 uint32_t SURFACE_ADDR; 2344 union dmub_reg_cursor_control_cfg cur_ctl; 2345 union dmub_reg_cursor_size_cfg { 2346 struct { 2347 uint32_t width: 16; 2348 uint32_t height: 16; 2349 } bits; 2350 uint32_t raw; 2351 } size; 2352 union dmub_reg_cursor_settings_cfg { 2353 struct { 2354 uint32_t dst_y_offset: 8; 2355 uint32_t chunk_hdl_adjust: 2; 2356 uint32_t reserved: 22; 2357 } bits; 2358 uint32_t raw; 2359 } settings; 2360 }; 2361 struct dmub_cursor_attribute_cache_dpp { 2362 union dmub_reg_cur0_control_cfg cur0_ctl; 2363 }; 2364 struct dmub_cursor_attributes_cfg { 2365 struct dmub_cursor_attribute_cache_hubp aHubp; 2366 struct dmub_cursor_attribute_cache_dpp aDpp; 2367 }; 2368 2369 struct dmub_cmd_update_cursor_payload0 { 2370 /** 2371 * Cursor dirty rects. 2372 */ 2373 struct dmub_rect cursor_rect; 2374 /** 2375 * PSR SU debug flags. 2376 */ 2377 union dmub_psr_su_debug_flags debug_flags; 2378 /** 2379 * Cursor enable/disable. 2380 */ 2381 uint8_t enable; 2382 /** 2383 * OTG HW instance. 2384 */ 2385 uint8_t pipe_idx; 2386 /** 2387 * PSR control version. 2388 */ 2389 uint8_t cmd_version; 2390 /** 2391 * Panel Instance. 2392 * Panel instance to identify which psr_state to use 2393 * Currently the support is only for 0 or 1 2394 */ 2395 uint8_t panel_inst; 2396 /** 2397 * Cursor Position Register. 2398 * Registers contains Hubp & Dpp modules 2399 */ 2400 struct dmub_cursor_position_cfg position_cfg; 2401 }; 2402 2403 struct dmub_cmd_update_cursor_payload1 { 2404 struct dmub_cursor_attributes_cfg attribute_cfg; 2405 }; 2406 2407 union dmub_cmd_update_cursor_info_data { 2408 struct dmub_cmd_update_cursor_payload0 payload0; 2409 struct dmub_cmd_update_cursor_payload1 payload1; 2410 }; 2411 /** 2412 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2413 */ 2414 struct dmub_rb_cmd_update_cursor_info { 2415 /** 2416 * Command header. 2417 */ 2418 struct dmub_cmd_header header; 2419 /** 2420 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2421 */ 2422 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2423 }; 2424 2425 /** 2426 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2427 */ 2428 struct dmub_cmd_psr_set_vtotal_data { 2429 /** 2430 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2431 */ 2432 uint16_t psr_vtotal_idle; 2433 /** 2434 * PSR control version. 2435 */ 2436 uint8_t cmd_version; 2437 /** 2438 * Panel Instance. 2439 * Panel instance to identify which psr_state to use 2440 * Currently the support is only for 0 or 1 2441 */ 2442 uint8_t panel_inst; 2443 /* 2444 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2445 */ 2446 uint16_t psr_vtotal_su; 2447 /** 2448 * Explicit padding to 4 byte boundary. 2449 */ 2450 uint8_t pad2[2]; 2451 }; 2452 2453 /** 2454 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2455 */ 2456 struct dmub_rb_cmd_psr_set_vtotal { 2457 /** 2458 * Command header. 2459 */ 2460 struct dmub_cmd_header header; 2461 /** 2462 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2463 */ 2464 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2465 }; 2466 2467 /** 2468 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2469 */ 2470 struct dmub_cmd_psr_set_power_opt_data { 2471 /** 2472 * PSR control version. 2473 */ 2474 uint8_t cmd_version; 2475 /** 2476 * Panel Instance. 2477 * Panel instance to identify which psr_state to use 2478 * Currently the support is only for 0 or 1 2479 */ 2480 uint8_t panel_inst; 2481 /** 2482 * Explicit padding to 4 byte boundary. 2483 */ 2484 uint8_t pad[2]; 2485 /** 2486 * PSR power option 2487 */ 2488 uint32_t power_opt; 2489 }; 2490 2491 /** 2492 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2493 */ 2494 struct dmub_rb_cmd_psr_set_power_opt { 2495 /** 2496 * Command header. 2497 */ 2498 struct dmub_cmd_header header; 2499 /** 2500 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2501 */ 2502 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2503 }; 2504 2505 /** 2506 * Set of HW components that can be locked. 2507 * 2508 * Note: If updating with more HW components, fields 2509 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2510 */ 2511 union dmub_hw_lock_flags { 2512 /** 2513 * Set of HW components that can be locked. 2514 */ 2515 struct { 2516 /** 2517 * Lock/unlock OTG master update lock. 2518 */ 2519 uint8_t lock_pipe : 1; 2520 /** 2521 * Lock/unlock cursor. 2522 */ 2523 uint8_t lock_cursor : 1; 2524 /** 2525 * Lock/unlock global update lock. 2526 */ 2527 uint8_t lock_dig : 1; 2528 /** 2529 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2530 */ 2531 uint8_t triple_buffer_lock : 1; 2532 } bits; 2533 2534 /** 2535 * Union for HW Lock flags. 2536 */ 2537 uint8_t u8All; 2538 }; 2539 2540 /** 2541 * Instances of HW to be locked. 2542 * 2543 * Note: If updating with more HW components, fields 2544 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2545 */ 2546 struct dmub_hw_lock_inst_flags { 2547 /** 2548 * OTG HW instance for OTG master update lock. 2549 */ 2550 uint8_t otg_inst; 2551 /** 2552 * OPP instance for cursor lock. 2553 */ 2554 uint8_t opp_inst; 2555 /** 2556 * OTG HW instance for global update lock. 2557 * TODO: Remove, and re-use otg_inst. 2558 */ 2559 uint8_t dig_inst; 2560 /** 2561 * Explicit pad to 4 byte boundary. 2562 */ 2563 uint8_t pad; 2564 }; 2565 2566 /** 2567 * Clients that can acquire the HW Lock Manager. 2568 * 2569 * Note: If updating with more clients, fields in 2570 * dmub_inbox0_cmd_lock_hw must be updated to match. 2571 */ 2572 enum hw_lock_client { 2573 /** 2574 * Driver is the client of HW Lock Manager. 2575 */ 2576 HW_LOCK_CLIENT_DRIVER = 0, 2577 /** 2578 * PSR SU is the client of HW Lock Manager. 2579 */ 2580 HW_LOCK_CLIENT_PSR_SU = 1, 2581 /** 2582 * Invalid client. 2583 */ 2584 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2585 }; 2586 2587 /** 2588 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2589 */ 2590 struct dmub_cmd_lock_hw_data { 2591 /** 2592 * Specifies the client accessing HW Lock Manager. 2593 */ 2594 enum hw_lock_client client; 2595 /** 2596 * HW instances to be locked. 2597 */ 2598 struct dmub_hw_lock_inst_flags inst_flags; 2599 /** 2600 * Which components to be locked. 2601 */ 2602 union dmub_hw_lock_flags hw_locks; 2603 /** 2604 * Specifies lock/unlock. 2605 */ 2606 uint8_t lock; 2607 /** 2608 * HW can be unlocked separately from releasing the HW Lock Mgr. 2609 * This flag is set if the client wishes to release the object. 2610 */ 2611 uint8_t should_release; 2612 /** 2613 * Explicit padding to 4 byte boundary. 2614 */ 2615 uint8_t pad; 2616 }; 2617 2618 /** 2619 * Definition of a DMUB_CMD__HW_LOCK command. 2620 * Command is used by driver and FW. 2621 */ 2622 struct dmub_rb_cmd_lock_hw { 2623 /** 2624 * Command header. 2625 */ 2626 struct dmub_cmd_header header; 2627 /** 2628 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2629 */ 2630 struct dmub_cmd_lock_hw_data lock_hw_data; 2631 }; 2632 2633 /** 2634 * ABM command sub-types. 2635 */ 2636 enum dmub_cmd_abm_type { 2637 /** 2638 * Initialize parameters for ABM algorithm. 2639 * Data is passed through an indirect buffer. 2640 */ 2641 DMUB_CMD__ABM_INIT_CONFIG = 0, 2642 /** 2643 * Set OTG and panel HW instance. 2644 */ 2645 DMUB_CMD__ABM_SET_PIPE = 1, 2646 /** 2647 * Set user requested backklight level. 2648 */ 2649 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2650 /** 2651 * Set ABM operating/aggression level. 2652 */ 2653 DMUB_CMD__ABM_SET_LEVEL = 3, 2654 /** 2655 * Set ambient light level. 2656 */ 2657 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2658 /** 2659 * Enable/disable fractional duty cycle for backlight PWM. 2660 */ 2661 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2662 2663 /** 2664 * unregister vertical interrupt after steady state is reached 2665 */ 2666 DMUB_CMD__ABM_PAUSE = 6, 2667 }; 2668 2669 /** 2670 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2671 * Requirements: 2672 * - Padded explicitly to 32-bit boundary. 2673 * - Must ensure this structure matches the one on driver-side, 2674 * otherwise it won't be aligned. 2675 */ 2676 struct abm_config_table { 2677 /** 2678 * Gamma curve thresholds, used for crgb conversion. 2679 */ 2680 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2681 /** 2682 * Gamma curve offsets, used for crgb conversion. 2683 */ 2684 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2685 /** 2686 * Gamma curve slopes, used for crgb conversion. 2687 */ 2688 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2689 /** 2690 * Custom backlight curve thresholds. 2691 */ 2692 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2693 /** 2694 * Custom backlight curve offsets. 2695 */ 2696 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2697 /** 2698 * Ambient light thresholds. 2699 */ 2700 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2701 /** 2702 * Minimum programmable backlight. 2703 */ 2704 uint16_t min_abm_backlight; // 122B 2705 /** 2706 * Minimum reduction values. 2707 */ 2708 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2709 /** 2710 * Maximum reduction values. 2711 */ 2712 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2713 /** 2714 * Bright positive gain. 2715 */ 2716 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2717 /** 2718 * Dark negative gain. 2719 */ 2720 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2721 /** 2722 * Hybrid factor. 2723 */ 2724 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2725 /** 2726 * Contrast factor. 2727 */ 2728 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2729 /** 2730 * Deviation gain. 2731 */ 2732 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2733 /** 2734 * Minimum knee. 2735 */ 2736 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2737 /** 2738 * Maximum knee. 2739 */ 2740 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2741 /** 2742 * Unused. 2743 */ 2744 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2745 /** 2746 * Explicit padding to 4 byte boundary. 2747 */ 2748 uint8_t pad3[3]; // 229B 2749 /** 2750 * Backlight ramp reduction. 2751 */ 2752 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2753 /** 2754 * Backlight ramp start. 2755 */ 2756 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2757 }; 2758 2759 /** 2760 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2761 */ 2762 struct dmub_cmd_abm_set_pipe_data { 2763 /** 2764 * OTG HW instance. 2765 */ 2766 uint8_t otg_inst; 2767 2768 /** 2769 * Panel Control HW instance. 2770 */ 2771 uint8_t panel_inst; 2772 2773 /** 2774 * Controls how ABM will interpret a set pipe or set level command. 2775 */ 2776 uint8_t set_pipe_option; 2777 2778 /** 2779 * Unused. 2780 * TODO: Remove. 2781 */ 2782 uint8_t ramping_boundary; 2783 }; 2784 2785 /** 2786 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2787 */ 2788 struct dmub_rb_cmd_abm_set_pipe { 2789 /** 2790 * Command header. 2791 */ 2792 struct dmub_cmd_header header; 2793 2794 /** 2795 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2796 */ 2797 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2798 }; 2799 2800 /** 2801 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2802 */ 2803 struct dmub_cmd_abm_set_backlight_data { 2804 /** 2805 * Number of frames to ramp to backlight user level. 2806 */ 2807 uint32_t frame_ramp; 2808 2809 /** 2810 * Requested backlight level from user. 2811 */ 2812 uint32_t backlight_user_level; 2813 2814 /** 2815 * ABM control version. 2816 */ 2817 uint8_t version; 2818 2819 /** 2820 * Panel Control HW instance mask. 2821 * Bit 0 is Panel Control HW instance 0. 2822 * Bit 1 is Panel Control HW instance 1. 2823 */ 2824 uint8_t panel_mask; 2825 2826 /** 2827 * Explicit padding to 4 byte boundary. 2828 */ 2829 uint8_t pad[2]; 2830 }; 2831 2832 /** 2833 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2834 */ 2835 struct dmub_rb_cmd_abm_set_backlight { 2836 /** 2837 * Command header. 2838 */ 2839 struct dmub_cmd_header header; 2840 2841 /** 2842 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2843 */ 2844 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2845 }; 2846 2847 /** 2848 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2849 */ 2850 struct dmub_cmd_abm_set_level_data { 2851 /** 2852 * Set current ABM operating/aggression level. 2853 */ 2854 uint32_t level; 2855 2856 /** 2857 * ABM control version. 2858 */ 2859 uint8_t version; 2860 2861 /** 2862 * Panel Control HW instance mask. 2863 * Bit 0 is Panel Control HW instance 0. 2864 * Bit 1 is Panel Control HW instance 1. 2865 */ 2866 uint8_t panel_mask; 2867 2868 /** 2869 * Explicit padding to 4 byte boundary. 2870 */ 2871 uint8_t pad[2]; 2872 }; 2873 2874 /** 2875 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2876 */ 2877 struct dmub_rb_cmd_abm_set_level { 2878 /** 2879 * Command header. 2880 */ 2881 struct dmub_cmd_header header; 2882 2883 /** 2884 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2885 */ 2886 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2887 }; 2888 2889 /** 2890 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2891 */ 2892 struct dmub_cmd_abm_set_ambient_level_data { 2893 /** 2894 * Ambient light sensor reading from OS. 2895 */ 2896 uint32_t ambient_lux; 2897 2898 /** 2899 * ABM control version. 2900 */ 2901 uint8_t version; 2902 2903 /** 2904 * Panel Control HW instance mask. 2905 * Bit 0 is Panel Control HW instance 0. 2906 * Bit 1 is Panel Control HW instance 1. 2907 */ 2908 uint8_t panel_mask; 2909 2910 /** 2911 * Explicit padding to 4 byte boundary. 2912 */ 2913 uint8_t pad[2]; 2914 }; 2915 2916 /** 2917 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2918 */ 2919 struct dmub_rb_cmd_abm_set_ambient_level { 2920 /** 2921 * Command header. 2922 */ 2923 struct dmub_cmd_header header; 2924 2925 /** 2926 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2927 */ 2928 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2929 }; 2930 2931 /** 2932 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2933 */ 2934 struct dmub_cmd_abm_set_pwm_frac_data { 2935 /** 2936 * Enable/disable fractional duty cycle for backlight PWM. 2937 * TODO: Convert to uint8_t. 2938 */ 2939 uint32_t fractional_pwm; 2940 2941 /** 2942 * ABM control version. 2943 */ 2944 uint8_t version; 2945 2946 /** 2947 * Panel Control HW instance mask. 2948 * Bit 0 is Panel Control HW instance 0. 2949 * Bit 1 is Panel Control HW instance 1. 2950 */ 2951 uint8_t panel_mask; 2952 2953 /** 2954 * Explicit padding to 4 byte boundary. 2955 */ 2956 uint8_t pad[2]; 2957 }; 2958 2959 /** 2960 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2961 */ 2962 struct dmub_rb_cmd_abm_set_pwm_frac { 2963 /** 2964 * Command header. 2965 */ 2966 struct dmub_cmd_header header; 2967 2968 /** 2969 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2970 */ 2971 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2972 }; 2973 2974 /** 2975 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2976 */ 2977 struct dmub_cmd_abm_init_config_data { 2978 /** 2979 * Location of indirect buffer used to pass init data to ABM. 2980 */ 2981 union dmub_addr src; 2982 2983 /** 2984 * Indirect buffer length. 2985 */ 2986 uint16_t bytes; 2987 2988 2989 /** 2990 * ABM control version. 2991 */ 2992 uint8_t version; 2993 2994 /** 2995 * Panel Control HW instance mask. 2996 * Bit 0 is Panel Control HW instance 0. 2997 * Bit 1 is Panel Control HW instance 1. 2998 */ 2999 uint8_t panel_mask; 3000 3001 /** 3002 * Explicit padding to 4 byte boundary. 3003 */ 3004 uint8_t pad[2]; 3005 }; 3006 3007 /** 3008 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3009 */ 3010 struct dmub_rb_cmd_abm_init_config { 3011 /** 3012 * Command header. 3013 */ 3014 struct dmub_cmd_header header; 3015 3016 /** 3017 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3018 */ 3019 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3020 }; 3021 3022 /** 3023 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3024 */ 3025 3026 struct dmub_cmd_abm_pause_data { 3027 3028 /** 3029 * Panel Control HW instance mask. 3030 * Bit 0 is Panel Control HW instance 0. 3031 * Bit 1 is Panel Control HW instance 1. 3032 */ 3033 uint8_t panel_mask; 3034 3035 /** 3036 * OTG hw instance 3037 */ 3038 uint8_t otg_inst; 3039 3040 /** 3041 * Enable or disable ABM pause 3042 */ 3043 uint8_t enable; 3044 3045 /** 3046 * Explicit padding to 4 byte boundary. 3047 */ 3048 uint8_t pad[1]; 3049 }; 3050 3051 /** 3052 * Definition of a DMUB_CMD__ABM_PAUSE command. 3053 */ 3054 struct dmub_rb_cmd_abm_pause { 3055 /** 3056 * Command header. 3057 */ 3058 struct dmub_cmd_header header; 3059 3060 /** 3061 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3062 */ 3063 struct dmub_cmd_abm_pause_data abm_pause_data; 3064 }; 3065 3066 /** 3067 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3068 */ 3069 struct dmub_cmd_query_feature_caps_data { 3070 /** 3071 * DMUB feature capabilities. 3072 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3073 */ 3074 struct dmub_feature_caps feature_caps; 3075 }; 3076 3077 /** 3078 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3079 */ 3080 struct dmub_rb_cmd_query_feature_caps { 3081 /** 3082 * Command header. 3083 */ 3084 struct dmub_cmd_header header; 3085 /** 3086 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3087 */ 3088 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 3089 }; 3090 3091 /** 3092 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3093 */ 3094 struct dmub_cmd_visual_confirm_color_data { 3095 /** 3096 * DMUB feature capabilities. 3097 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3098 */ 3099 struct dmub_visual_confirm_color visual_confirm_color; 3100 }; 3101 3102 /** 3103 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3104 */ 3105 struct dmub_rb_cmd_get_visual_confirm_color { 3106 /** 3107 * Command header. 3108 */ 3109 struct dmub_cmd_header header; 3110 /** 3111 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3112 */ 3113 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3114 }; 3115 3116 struct dmub_optc_state { 3117 uint32_t v_total_max; 3118 uint32_t v_total_min; 3119 uint32_t tg_inst; 3120 }; 3121 3122 struct dmub_rb_cmd_drr_update { 3123 struct dmub_cmd_header header; 3124 struct dmub_optc_state dmub_optc_state_req; 3125 }; 3126 3127 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 3128 uint32_t pix_clk_100hz; 3129 uint8_t max_ramp_step; 3130 uint8_t pipes; 3131 uint8_t min_refresh_in_hz; 3132 uint8_t pipe_count; 3133 uint8_t pipe_index[4]; 3134 }; 3135 3136 struct dmub_cmd_fw_assisted_mclk_switch_config { 3137 uint8_t fams_enabled; 3138 uint8_t visual_confirm_enabled; 3139 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 3140 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 3141 }; 3142 3143 struct dmub_rb_cmd_fw_assisted_mclk_switch { 3144 struct dmub_cmd_header header; 3145 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 3146 }; 3147 3148 /** 3149 * enum dmub_cmd_panel_cntl_type - Panel control command. 3150 */ 3151 enum dmub_cmd_panel_cntl_type { 3152 /** 3153 * Initializes embedded panel hardware blocks. 3154 */ 3155 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3156 /** 3157 * Queries backlight info for the embedded panel. 3158 */ 3159 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3160 }; 3161 3162 /** 3163 * struct dmub_cmd_panel_cntl_data - Panel control data. 3164 */ 3165 struct dmub_cmd_panel_cntl_data { 3166 uint32_t inst; /**< panel instance */ 3167 uint32_t current_backlight; /* in/out */ 3168 uint32_t bl_pwm_cntl; /* in/out */ 3169 uint32_t bl_pwm_period_cntl; /* in/out */ 3170 uint32_t bl_pwm_ref_div1; /* in/out */ 3171 uint8_t is_backlight_on : 1; /* in/out */ 3172 uint8_t is_powered_on : 1; /* in/out */ 3173 uint8_t padding[3]; 3174 uint32_t bl_pwm_ref_div2; /* in/out */ 3175 uint8_t reserved[4]; 3176 }; 3177 3178 /** 3179 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3180 */ 3181 struct dmub_rb_cmd_panel_cntl { 3182 struct dmub_cmd_header header; /**< header */ 3183 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3184 }; 3185 3186 /** 3187 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3188 */ 3189 struct dmub_cmd_lvtma_control_data { 3190 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3191 uint8_t bypass_panel_control_wait; 3192 uint8_t reserved_0[2]; /**< For future use */ 3193 uint8_t panel_inst; /**< LVTMA control instance */ 3194 uint8_t reserved_1[3]; /**< For future use */ 3195 }; 3196 3197 /** 3198 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3199 */ 3200 struct dmub_rb_cmd_lvtma_control { 3201 /** 3202 * Command header. 3203 */ 3204 struct dmub_cmd_header header; 3205 /** 3206 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3207 */ 3208 struct dmub_cmd_lvtma_control_data data; 3209 }; 3210 3211 /** 3212 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3213 */ 3214 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3215 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3216 uint8_t is_usb; /**< is phy is usb */ 3217 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3218 uint8_t is_dp4; /**< is dp in 4 lane */ 3219 }; 3220 3221 /** 3222 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3223 */ 3224 struct dmub_rb_cmd_transmitter_query_dp_alt { 3225 struct dmub_cmd_header header; /**< header */ 3226 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3227 }; 3228 3229 /** 3230 * Maximum number of bytes a chunk sent to DMUB for parsing 3231 */ 3232 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3233 3234 /** 3235 * Represent a chunk of CEA blocks sent to DMUB for parsing 3236 */ 3237 struct dmub_cmd_send_edid_cea { 3238 uint16_t offset; /**< offset into the CEA block */ 3239 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3240 uint16_t cea_total_length; /**< total length of the CEA block */ 3241 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3242 uint8_t pad[3]; /**< padding and for future expansion */ 3243 }; 3244 3245 /** 3246 * Result of VSDB parsing from CEA block 3247 */ 3248 struct dmub_cmd_edid_cea_amd_vsdb { 3249 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3250 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3251 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3252 uint16_t min_frame_rate; /**< Maximum frame rate */ 3253 uint16_t max_frame_rate; /**< Minimum frame rate */ 3254 }; 3255 3256 /** 3257 * Result of sending a CEA chunk 3258 */ 3259 struct dmub_cmd_edid_cea_ack { 3260 uint16_t offset; /**< offset of the chunk into the CEA block */ 3261 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3262 uint8_t pad; /**< padding and for future expansion */ 3263 }; 3264 3265 /** 3266 * Specify whether the result is an ACK/NACK or the parsing has finished 3267 */ 3268 enum dmub_cmd_edid_cea_reply_type { 3269 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3270 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3271 }; 3272 3273 /** 3274 * Definition of a DMUB_CMD__EDID_CEA command. 3275 */ 3276 struct dmub_rb_cmd_edid_cea { 3277 struct dmub_cmd_header header; /**< Command header */ 3278 union dmub_cmd_edid_cea_data { 3279 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3280 struct dmub_cmd_edid_cea_output { /**< output with results */ 3281 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3282 union { 3283 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3284 struct dmub_cmd_edid_cea_ack ack; 3285 }; 3286 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3287 } data; /**< Command data */ 3288 3289 }; 3290 3291 /** 3292 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3293 */ 3294 struct dmub_cmd_cable_id_input { 3295 uint8_t phy_inst; /**< phy inst for cable id data */ 3296 }; 3297 3298 /** 3299 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3300 */ 3301 struct dmub_cmd_cable_id_output { 3302 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3303 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3304 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3305 uint8_t RESERVED :2; /**< reserved means not defined */ 3306 }; 3307 3308 /** 3309 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3310 */ 3311 struct dmub_rb_cmd_get_usbc_cable_id { 3312 struct dmub_cmd_header header; /**< Command header */ 3313 /** 3314 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3315 */ 3316 union dmub_cmd_cable_id_data { 3317 struct dmub_cmd_cable_id_input input; /**< Input */ 3318 struct dmub_cmd_cable_id_output output; /**< Output */ 3319 uint8_t output_raw; /**< Raw data output */ 3320 } data; 3321 }; 3322 3323 /** 3324 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3325 */ 3326 enum dmub_cmd_secure_display_type { 3327 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3328 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3329 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3330 }; 3331 3332 /** 3333 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3334 */ 3335 struct dmub_rb_cmd_secure_display { 3336 struct dmub_cmd_header header; 3337 /** 3338 * Data passed from driver to dmub firmware. 3339 */ 3340 struct dmub_cmd_roi_info { 3341 uint16_t x_start; 3342 uint16_t x_end; 3343 uint16_t y_start; 3344 uint16_t y_end; 3345 uint8_t otg_id; 3346 uint8_t phy_id; 3347 } roi_info; 3348 }; 3349 3350 /** 3351 * union dmub_rb_cmd - DMUB inbox command. 3352 */ 3353 union dmub_rb_cmd { 3354 /** 3355 * Elements shared with all commands. 3356 */ 3357 struct dmub_rb_cmd_common cmd_common; 3358 /** 3359 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3360 */ 3361 struct dmub_rb_cmd_read_modify_write read_modify_write; 3362 /** 3363 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3364 */ 3365 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3366 /** 3367 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3368 */ 3369 struct dmub_rb_cmd_burst_write burst_write; 3370 /** 3371 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3372 */ 3373 struct dmub_rb_cmd_reg_wait reg_wait; 3374 /** 3375 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3376 */ 3377 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3378 /** 3379 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3380 */ 3381 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3382 /** 3383 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3384 */ 3385 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3386 /** 3387 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3388 */ 3389 struct dmub_rb_cmd_dpphy_init dpphy_init; 3390 /** 3391 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3392 */ 3393 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3394 /** 3395 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3396 */ 3397 struct dmub_rb_cmd_domain_control domain_control; 3398 /** 3399 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3400 */ 3401 struct dmub_rb_cmd_psr_set_version psr_set_version; 3402 /** 3403 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3404 */ 3405 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3406 /** 3407 * Definition of a DMUB_CMD__PSR_ENABLE command. 3408 */ 3409 struct dmub_rb_cmd_psr_enable psr_enable; 3410 /** 3411 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3412 */ 3413 struct dmub_rb_cmd_psr_set_level psr_set_level; 3414 /** 3415 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3416 */ 3417 struct dmub_rb_cmd_psr_force_static psr_force_static; 3418 /** 3419 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3420 */ 3421 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3422 /** 3423 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3424 */ 3425 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3426 /** 3427 * Definition of a DMUB_CMD__HW_LOCK command. 3428 * Command is used by driver and FW. 3429 */ 3430 struct dmub_rb_cmd_lock_hw lock_hw; 3431 /** 3432 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3433 */ 3434 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3435 /** 3436 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3437 */ 3438 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3439 /** 3440 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3441 */ 3442 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3443 /** 3444 * Definition of a DMUB_CMD__MALL command. 3445 */ 3446 struct dmub_rb_cmd_mall mall; 3447 /** 3448 * Definition of a DMUB_CMD__CAB command. 3449 */ 3450 struct dmub_rb_cmd_cab_for_ss cab; 3451 3452 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3453 3454 /** 3455 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3456 */ 3457 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3458 3459 /** 3460 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3461 */ 3462 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3463 3464 /** 3465 * Definition of DMUB_CMD__PANEL_CNTL commands. 3466 */ 3467 struct dmub_rb_cmd_panel_cntl panel_cntl; 3468 /** 3469 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3470 */ 3471 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3472 3473 /** 3474 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3475 */ 3476 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3477 3478 /** 3479 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3480 */ 3481 struct dmub_rb_cmd_abm_set_level abm_set_level; 3482 3483 /** 3484 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3485 */ 3486 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3487 3488 /** 3489 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3490 */ 3491 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3492 3493 /** 3494 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3495 */ 3496 struct dmub_rb_cmd_abm_init_config abm_init_config; 3497 3498 /** 3499 * Definition of a DMUB_CMD__ABM_PAUSE command. 3500 */ 3501 struct dmub_rb_cmd_abm_pause abm_pause; 3502 3503 /** 3504 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3505 */ 3506 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3507 3508 /** 3509 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3510 */ 3511 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3512 3513 /** 3514 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3515 */ 3516 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3517 3518 /** 3519 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3520 */ 3521 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3522 struct dmub_rb_cmd_drr_update drr_update; 3523 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3524 3525 /** 3526 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3527 */ 3528 struct dmub_rb_cmd_lvtma_control lvtma_control; 3529 /** 3530 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3531 */ 3532 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3533 /** 3534 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3535 */ 3536 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3537 /** 3538 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3539 */ 3540 struct dmub_rb_cmd_set_config_access set_config_access; 3541 /** 3542 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3543 */ 3544 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3545 /** 3546 * Definition of a DMUB_CMD__EDID_CEA command. 3547 */ 3548 struct dmub_rb_cmd_edid_cea edid_cea; 3549 /** 3550 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3551 */ 3552 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3553 3554 /** 3555 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3556 */ 3557 struct dmub_rb_cmd_query_hpd_state query_hpd; 3558 /** 3559 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3560 */ 3561 struct dmub_rb_cmd_secure_display secure_display; 3562 3563 /** 3564 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3565 */ 3566 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3567 /** 3568 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 3569 */ 3570 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 3571 }; 3572 3573 /** 3574 * union dmub_rb_out_cmd - Outbox command 3575 */ 3576 union dmub_rb_out_cmd { 3577 /** 3578 * Parameters common to every command. 3579 */ 3580 struct dmub_rb_cmd_common cmd_common; 3581 /** 3582 * AUX reply command. 3583 */ 3584 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3585 /** 3586 * HPD notify command. 3587 */ 3588 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3589 /** 3590 * SET_CONFIG reply command. 3591 */ 3592 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3593 /** 3594 * DPIA notification command. 3595 */ 3596 struct dmub_rb_cmd_dpia_notification dpia_notification; 3597 }; 3598 #pragma pack(pop) 3599 3600 3601 //============================================================================== 3602 //</DMUB_CMD>=================================================================== 3603 //============================================================================== 3604 //< DMUB_RB>==================================================================== 3605 //============================================================================== 3606 3607 #if defined(__cplusplus) 3608 extern "C" { 3609 #endif 3610 3611 /** 3612 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3613 */ 3614 struct dmub_rb_init_params { 3615 void *ctx; /**< Caller provided context pointer */ 3616 void *base_address; /**< CPU base address for ring's data */ 3617 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3618 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3619 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3620 }; 3621 3622 /** 3623 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3624 */ 3625 struct dmub_rb { 3626 void *base_address; /**< CPU address for the ring's data */ 3627 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3628 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3629 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3630 3631 void *ctx; /**< Caller provided context pointer */ 3632 void *dmub; /**< Pointer to the DMUB interface */ 3633 }; 3634 3635 /** 3636 * @brief Checks if the ringbuffer is empty. 3637 * 3638 * @param rb DMUB Ringbuffer 3639 * @return true if empty 3640 * @return false otherwise 3641 */ 3642 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3643 { 3644 return (rb->wrpt == rb->rptr); 3645 } 3646 3647 /** 3648 * @brief Checks if the ringbuffer is full 3649 * 3650 * @param rb DMUB Ringbuffer 3651 * @return true if full 3652 * @return false otherwise 3653 */ 3654 static inline bool dmub_rb_full(struct dmub_rb *rb) 3655 { 3656 uint32_t data_count; 3657 3658 if (rb->wrpt >= rb->rptr) 3659 data_count = rb->wrpt - rb->rptr; 3660 else 3661 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3662 3663 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3664 } 3665 3666 /** 3667 * @brief Pushes a command into the ringbuffer 3668 * 3669 * @param rb DMUB ringbuffer 3670 * @param cmd The command to push 3671 * @return true if the ringbuffer was not full 3672 * @return false otherwise 3673 */ 3674 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3675 const union dmub_rb_cmd *cmd) 3676 { 3677 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3678 const uint64_t *src = (const uint64_t *)cmd; 3679 uint8_t i; 3680 3681 if (dmub_rb_full(rb)) 3682 return false; 3683 3684 // copying data 3685 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3686 *dst++ = *src++; 3687 3688 rb->wrpt += DMUB_RB_CMD_SIZE; 3689 3690 if (rb->wrpt >= rb->capacity) 3691 rb->wrpt %= rb->capacity; 3692 3693 return true; 3694 } 3695 3696 /** 3697 * @brief Pushes a command into the DMUB outbox ringbuffer 3698 * 3699 * @param rb DMUB outbox ringbuffer 3700 * @param cmd Outbox command 3701 * @return true if not full 3702 * @return false otherwise 3703 */ 3704 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3705 const union dmub_rb_out_cmd *cmd) 3706 { 3707 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3708 const uint8_t *src = (const uint8_t *)cmd; 3709 3710 if (dmub_rb_full(rb)) 3711 return false; 3712 3713 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3714 3715 rb->wrpt += DMUB_RB_CMD_SIZE; 3716 3717 if (rb->wrpt >= rb->capacity) 3718 rb->wrpt %= rb->capacity; 3719 3720 return true; 3721 } 3722 3723 /** 3724 * @brief Returns the next unprocessed command in the ringbuffer. 3725 * 3726 * @param rb DMUB ringbuffer 3727 * @param cmd The command to return 3728 * @return true if not empty 3729 * @return false otherwise 3730 */ 3731 static inline bool dmub_rb_front(struct dmub_rb *rb, 3732 union dmub_rb_cmd **cmd) 3733 { 3734 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3735 3736 if (dmub_rb_empty(rb)) 3737 return false; 3738 3739 *cmd = (union dmub_rb_cmd *)rb_cmd; 3740 3741 return true; 3742 } 3743 3744 /** 3745 * @brief Determines the next ringbuffer offset. 3746 * 3747 * @param rb DMUB inbox ringbuffer 3748 * @param num_cmds Number of commands 3749 * @param next_rptr The next offset in the ringbuffer 3750 */ 3751 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3752 uint32_t num_cmds, 3753 uint32_t *next_rptr) 3754 { 3755 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3756 3757 if (*next_rptr >= rb->capacity) 3758 *next_rptr %= rb->capacity; 3759 } 3760 3761 /** 3762 * @brief Returns a pointer to a command in the inbox. 3763 * 3764 * @param rb DMUB inbox ringbuffer 3765 * @param cmd The inbox command to return 3766 * @param rptr The ringbuffer offset 3767 * @return true if not empty 3768 * @return false otherwise 3769 */ 3770 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3771 union dmub_rb_cmd **cmd, 3772 uint32_t rptr) 3773 { 3774 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3775 3776 if (dmub_rb_empty(rb)) 3777 return false; 3778 3779 *cmd = (union dmub_rb_cmd *)rb_cmd; 3780 3781 return true; 3782 } 3783 3784 /** 3785 * @brief Returns the next unprocessed command in the outbox. 3786 * 3787 * @param rb DMUB outbox ringbuffer 3788 * @param cmd The outbox command to return 3789 * @return true if not empty 3790 * @return false otherwise 3791 */ 3792 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3793 union dmub_rb_out_cmd *cmd) 3794 { 3795 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3796 uint64_t *dst = (uint64_t *)cmd; 3797 uint8_t i; 3798 3799 if (dmub_rb_empty(rb)) 3800 return false; 3801 3802 // copying data 3803 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3804 *dst++ = *src++; 3805 3806 return true; 3807 } 3808 3809 /** 3810 * @brief Removes the front entry in the ringbuffer. 3811 * 3812 * @param rb DMUB ringbuffer 3813 * @return true if the command was removed 3814 * @return false if there were no commands 3815 */ 3816 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3817 { 3818 if (dmub_rb_empty(rb)) 3819 return false; 3820 3821 rb->rptr += DMUB_RB_CMD_SIZE; 3822 3823 if (rb->rptr >= rb->capacity) 3824 rb->rptr %= rb->capacity; 3825 3826 return true; 3827 } 3828 3829 /** 3830 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3831 * 3832 * Avoids a race condition where DMCUB accesses memory while 3833 * there are still writes in flight to framebuffer. 3834 * 3835 * @param rb DMUB ringbuffer 3836 */ 3837 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3838 { 3839 uint32_t rptr = rb->rptr; 3840 uint32_t wptr = rb->wrpt; 3841 3842 while (rptr != wptr) { 3843 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3844 uint8_t i; 3845 3846 /* Don't remove this. 3847 * The contents need to actually be read from the ring buffer 3848 * for this function to be effective. 3849 */ 3850 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3851 (void)READ_ONCE(*data++); 3852 3853 rptr += DMUB_RB_CMD_SIZE; 3854 if (rptr >= rb->capacity) 3855 rptr %= rb->capacity; 3856 } 3857 } 3858 3859 /** 3860 * @brief Initializes a DMCUB ringbuffer 3861 * 3862 * @param rb DMUB ringbuffer 3863 * @param init_params initial configuration for the ringbuffer 3864 */ 3865 static inline void dmub_rb_init(struct dmub_rb *rb, 3866 struct dmub_rb_init_params *init_params) 3867 { 3868 rb->base_address = init_params->base_address; 3869 rb->capacity = init_params->capacity; 3870 rb->rptr = init_params->read_ptr; 3871 rb->wrpt = init_params->write_ptr; 3872 } 3873 3874 /** 3875 * @brief Copies output data from in/out commands into the given command. 3876 * 3877 * @param rb DMUB ringbuffer 3878 * @param cmd Command to copy data into 3879 */ 3880 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3881 union dmub_rb_cmd *cmd) 3882 { 3883 // Copy rb entry back into command 3884 uint8_t *rd_ptr = (rb->rptr == 0) ? 3885 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3886 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3887 3888 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3889 } 3890 3891 #if defined(__cplusplus) 3892 } 3893 #endif 3894 3895 //============================================================================== 3896 //</DMUB_RB>==================================================================== 3897 //============================================================================== 3898 3899 #endif /* _DMUB_CMD_H_ */ 3900