1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 #include <stdarg.h> 43 44 #include "atomfirmware.h" 45 46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 47 48 /* Firmware versioning. */ 49 #ifdef DMUB_EXPOSE_VERSION 50 #define DMUB_FW_VERSION_GIT_HASH 0x9130ab830 51 #define DMUB_FW_VERSION_MAJOR 0 52 #define DMUB_FW_VERSION_MINOR 0 53 #define DMUB_FW_VERSION_REVISION 64 54 #define DMUB_FW_VERSION_TEST 0 55 #define DMUB_FW_VERSION_VBIOS 0 56 #define DMUB_FW_VERSION_HOTFIX 0 57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 62 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 63 64 #endif 65 66 //<DMUB_TYPES>================================================================== 67 /* Basic type definitions. */ 68 69 #define __forceinline inline 70 71 /** 72 * Flag from driver to indicate that ABM should be disabled gradually 73 * by slowly reversing all backlight programming and pixel compensation. 74 */ 75 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 76 77 /** 78 * Flag from driver to indicate that ABM should be disabled immediately 79 * and undo all backlight programming and pixel compensation. 80 */ 81 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 82 83 /** 84 * Flag from driver to indicate that ABM should be disabled immediately 85 * and keep the current backlight programming and pixel compensation. 86 */ 87 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 88 89 /** 90 * Flag from driver to set the current ABM pipe index or ABM operating level. 91 */ 92 #define SET_ABM_PIPE_NORMAL 1 93 94 /** 95 * Number of ambient light levels in ABM algorithm. 96 */ 97 #define NUM_AMBI_LEVEL 5 98 99 /** 100 * Number of operating/aggression levels in ABM algorithm. 101 */ 102 #define NUM_AGGR_LEVEL 4 103 104 /** 105 * Number of segments in the gamma curve. 106 */ 107 #define NUM_POWER_FN_SEGS 8 108 109 /** 110 * Number of segments in the backlight curve. 111 */ 112 #define NUM_BL_CURVE_SEGS 16 113 114 /* Maximum number of streams on any ASIC. */ 115 #define DMUB_MAX_STREAMS 6 116 117 /* Maximum number of planes on any ASIC. */ 118 #define DMUB_MAX_PLANES 6 119 120 #define DMUB_MAX_SUBVP_STREAMS 2 121 122 /* Trace buffer offset for entry */ 123 #define TRACE_BUFFER_ENTRY_OFFSET 16 124 125 /** 126 * ABM control version legacy 127 */ 128 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 129 130 /** 131 * ABM control version with multi edp support 132 */ 133 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 134 135 /** 136 * Physical framebuffer address location, 64-bit. 137 */ 138 #ifndef PHYSICAL_ADDRESS_LOC 139 #define PHYSICAL_ADDRESS_LOC union large_integer 140 #endif 141 142 /** 143 * OS/FW agnostic memcpy 144 */ 145 #ifndef dmub_memcpy 146 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 147 #endif 148 149 /** 150 * OS/FW agnostic memset 151 */ 152 #ifndef dmub_memset 153 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 154 #endif 155 156 #if defined(__cplusplus) 157 extern "C" { 158 #endif 159 160 /** 161 * OS/FW agnostic udelay 162 */ 163 #ifndef dmub_udelay 164 #define dmub_udelay(microseconds) udelay(microseconds) 165 #endif 166 167 /** 168 * union dmub_addr - DMUB physical/virtual 64-bit address. 169 */ 170 union dmub_addr { 171 struct { 172 uint32_t low_part; /**< Lower 32 bits */ 173 uint32_t high_part; /**< Upper 32 bits */ 174 } u; /*<< Low/high bit access */ 175 uint64_t quad_part; /*<< 64 bit address */ 176 }; 177 178 /** 179 * Flags that can be set by driver to change some PSR behaviour. 180 */ 181 union dmub_psr_debug_flags { 182 /** 183 * Debug flags. 184 */ 185 struct { 186 /** 187 * Enable visual confirm in FW. 188 */ 189 uint32_t visual_confirm : 1; 190 /** 191 * Use HW Lock Mgr object to do HW locking in FW. 192 */ 193 uint32_t use_hw_lock_mgr : 1; 194 195 /** 196 * Unused. 197 * TODO: Remove. 198 */ 199 uint32_t log_line_nums : 1; 200 } bitfields; 201 202 /** 203 * Union for debug flags. 204 */ 205 uint32_t u32All; 206 }; 207 208 /** 209 * DMUB feature capabilities. 210 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 211 */ 212 struct dmub_feature_caps { 213 /** 214 * Max PSR version supported by FW. 215 */ 216 uint8_t psr; 217 uint8_t reserved[7]; 218 }; 219 220 #if defined(__cplusplus) 221 } 222 #endif 223 224 //============================================================================== 225 //</DMUB_TYPES>================================================================= 226 //============================================================================== 227 //< DMUB_META>================================================================== 228 //============================================================================== 229 #pragma pack(push, 1) 230 231 /* Magic value for identifying dmub_fw_meta_info */ 232 #define DMUB_FW_META_MAGIC 0x444D5542 233 234 /* Offset from the end of the file to the dmub_fw_meta_info */ 235 #define DMUB_FW_META_OFFSET 0x24 236 237 /** 238 * struct dmub_fw_meta_info - metadata associated with fw binary 239 * 240 * NOTE: This should be considered a stable API. Fields should 241 * not be repurposed or reordered. New fields should be 242 * added instead to extend the structure. 243 * 244 * @magic_value: magic value identifying DMUB firmware meta info 245 * @fw_region_size: size of the firmware state region 246 * @trace_buffer_size: size of the tracebuffer region 247 * @fw_version: the firmware version information 248 * @dal_fw: 1 if the firmware is DAL 249 */ 250 struct dmub_fw_meta_info { 251 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 252 uint32_t fw_region_size; /**< size of the firmware state region */ 253 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 254 uint32_t fw_version; /**< the firmware version information */ 255 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 256 uint8_t reserved[3]; /**< padding bits */ 257 }; 258 259 /** 260 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 261 */ 262 union dmub_fw_meta { 263 struct dmub_fw_meta_info info; /**< metadata info */ 264 uint8_t reserved[64]; /**< padding bits */ 265 }; 266 267 #pragma pack(pop) 268 269 //============================================================================== 270 //< DMUB Trace Buffer>================================================================ 271 //============================================================================== 272 /** 273 * dmub_trace_code_t - firmware trace code, 32-bits 274 */ 275 typedef uint32_t dmub_trace_code_t; 276 277 /** 278 * struct dmcub_trace_buf_entry - Firmware trace entry 279 */ 280 struct dmcub_trace_buf_entry { 281 dmub_trace_code_t trace_code; /**< trace code for the event */ 282 uint32_t tick_count; /**< the tick count at time of trace */ 283 uint32_t param0; /**< trace defined parameter 0 */ 284 uint32_t param1; /**< trace defined parameter 1 */ 285 }; 286 287 //============================================================================== 288 //< DMUB_STATUS>================================================================ 289 //============================================================================== 290 291 /** 292 * DMCUB scratch registers can be used to determine firmware status. 293 * Current scratch register usage is as follows: 294 * 295 * SCRATCH0: FW Boot Status register 296 * SCRATCH15: FW Boot Options register 297 */ 298 299 /** 300 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 301 */ 302 union dmub_fw_boot_status { 303 struct { 304 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 305 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 306 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 307 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 308 } bits; /**< status bits */ 309 uint32_t all; /**< 32-bit access to status bits */ 310 }; 311 312 /** 313 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 314 */ 315 enum dmub_fw_boot_status_bit { 316 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 317 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 318 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 319 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 320 }; 321 322 /** 323 * union dmub_fw_boot_options - Boot option definitions for SCRATCH15 324 */ 325 union dmub_fw_boot_options { 326 struct { 327 uint32_t pemu_env : 1; /**< 1 if PEMU */ 328 uint32_t fpga_env : 1; /**< 1 if FPGA */ 329 uint32_t optimized_init : 1; /**< 1 if optimized init */ 330 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 331 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 332 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 333 uint32_t reserved_unreleased: 1; /**< reserved for an unreleased feature */ 334 uint32_t reserved : 25; /**< reserved */ 335 } bits; /**< boot bits */ 336 uint32_t all; /**< 32-bit access to bits */ 337 }; 338 339 enum dmub_fw_boot_options_bit { 340 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 341 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 342 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 343 }; 344 345 //============================================================================== 346 //</DMUB_STATUS>================================================================ 347 //============================================================================== 348 //< DMUB_VBIOS>================================================================= 349 //============================================================================== 350 351 /* 352 * enum dmub_cmd_vbios_type - VBIOS commands. 353 * 354 * Command IDs should be treated as stable ABI. 355 * Do not reuse or modify IDs. 356 */ 357 enum dmub_cmd_vbios_type { 358 /** 359 * Configures the DIG encoder. 360 */ 361 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 362 /** 363 * Controls the PHY. 364 */ 365 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 366 /** 367 * Sets the pixel clock/symbol clock. 368 */ 369 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 370 /** 371 * Enables or disables power gating. 372 */ 373 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 374 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 375 }; 376 377 //============================================================================== 378 //</DMUB_VBIOS>================================================================= 379 //============================================================================== 380 //< DMUB_GPINT>================================================================= 381 //============================================================================== 382 383 /** 384 * The shifts and masks below may alternatively be used to format and read 385 * the command register bits. 386 */ 387 388 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 389 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 390 391 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 392 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 393 394 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 395 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 396 397 /** 398 * Command responses. 399 */ 400 401 /** 402 * Return response for DMUB_GPINT__STOP_FW command. 403 */ 404 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 405 406 /** 407 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 408 */ 409 union dmub_gpint_data_register { 410 struct { 411 uint32_t param : 16; /**< 16-bit parameter */ 412 uint32_t command_code : 12; /**< GPINT command */ 413 uint32_t status : 4; /**< Command status bit */ 414 } bits; /**< GPINT bit access */ 415 uint32_t all; /**< GPINT 32-bit access */ 416 }; 417 418 /* 419 * enum dmub_gpint_command - GPINT command to DMCUB FW 420 * 421 * Command IDs should be treated as stable ABI. 422 * Do not reuse or modify IDs. 423 */ 424 enum dmub_gpint_command { 425 /** 426 * Invalid command, ignored. 427 */ 428 DMUB_GPINT__INVALID_COMMAND = 0, 429 /** 430 * DESC: Queries the firmware version. 431 * RETURN: Firmware version. 432 */ 433 DMUB_GPINT__GET_FW_VERSION = 1, 434 /** 435 * DESC: Halts the firmware. 436 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 437 */ 438 DMUB_GPINT__STOP_FW = 2, 439 /** 440 * DESC: Get PSR state from FW. 441 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 442 */ 443 DMUB_GPINT__GET_PSR_STATE = 7, 444 /** 445 * DESC: Notifies DMCUB of the currently active streams. 446 * ARGS: Stream mask, 1 bit per active stream index. 447 */ 448 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 449 /** 450 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 451 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 452 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 453 * RETURN: PSR residency in milli-percent. 454 */ 455 DMUB_GPINT__PSR_RESIDENCY = 9, 456 }; 457 458 //============================================================================== 459 //</DMUB_GPINT>================================================================= 460 //============================================================================== 461 //< DMUB_CMD>=================================================================== 462 //============================================================================== 463 464 /** 465 * Size in bytes of each DMUB command. 466 */ 467 #define DMUB_RB_CMD_SIZE 64 468 469 /** 470 * Maximum number of items in the DMUB ringbuffer. 471 */ 472 #define DMUB_RB_MAX_ENTRY 128 473 474 /** 475 * Ringbuffer size in bytes. 476 */ 477 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 478 479 /** 480 * REG_SET mask for reg offload. 481 */ 482 #define REG_SET_MASK 0xFFFF 483 484 /* 485 * enum dmub_cmd_type - DMUB inbox command. 486 * 487 * Command IDs should be treated as stable ABI. 488 * Do not reuse or modify IDs. 489 */ 490 enum dmub_cmd_type { 491 /** 492 * Invalid command. 493 */ 494 DMUB_CMD__NULL = 0, 495 /** 496 * Read modify write register sequence offload. 497 */ 498 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 499 /** 500 * Field update register sequence offload. 501 */ 502 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 503 /** 504 * Burst write sequence offload. 505 */ 506 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 507 /** 508 * Reg wait sequence offload. 509 */ 510 DMUB_CMD__REG_REG_WAIT = 4, 511 /** 512 * Workaround to avoid HUBP underflow during NV12 playback. 513 */ 514 DMUB_CMD__PLAT_54186_WA = 5, 515 /** 516 * Command type used to query FW feature caps. 517 */ 518 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 519 /** 520 * Command type used for all PSR commands. 521 */ 522 DMUB_CMD__PSR = 64, 523 /** 524 * Command type used for all MALL commands. 525 */ 526 DMUB_CMD__MALL = 65, 527 /** 528 * Command type used for all ABM commands. 529 */ 530 DMUB_CMD__ABM = 66, 531 /** 532 * Command type used for HW locking in FW. 533 */ 534 DMUB_CMD__HW_LOCK = 69, 535 /** 536 * Command type used to access DP AUX. 537 */ 538 DMUB_CMD__DP_AUX_ACCESS = 70, 539 /** 540 * Command type used for OUTBOX1 notification enable 541 */ 542 DMUB_CMD__OUTBOX1_ENABLE = 71, 543 /** 544 * Command type used for all VBIOS interface commands. 545 */ 546 DMUB_CMD__VBIOS = 128, 547 }; 548 549 /** 550 * enum dmub_out_cmd_type - DMUB outbox commands. 551 */ 552 enum dmub_out_cmd_type { 553 /** 554 * Invalid outbox command, ignored. 555 */ 556 DMUB_OUT_CMD__NULL = 0, 557 /** 558 * Command type used for DP AUX Reply data notification 559 */ 560 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 561 /** 562 * Command type used for DP HPD event notification 563 */ 564 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 565 }; 566 567 #pragma pack(push, 1) 568 569 /** 570 * struct dmub_cmd_header - Common command header fields. 571 */ 572 struct dmub_cmd_header { 573 unsigned int type : 8; /**< command type */ 574 unsigned int sub_type : 8; /**< command sub type */ 575 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 576 unsigned int reserved0 : 7; /**< reserved bits */ 577 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 578 unsigned int reserved1 : 2; /**< reserved bits */ 579 }; 580 581 /* 582 * struct dmub_cmd_read_modify_write_sequence - Read modify write 583 * 584 * 60 payload bytes can hold up to 5 sets of read modify writes, 585 * each take 3 dwords. 586 * 587 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 588 * 589 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 590 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 591 */ 592 struct dmub_cmd_read_modify_write_sequence { 593 uint32_t addr; /**< register address */ 594 uint32_t modify_mask; /**< modify mask */ 595 uint32_t modify_value; /**< modify value */ 596 }; 597 598 /** 599 * Maximum number of ops in read modify write sequence. 600 */ 601 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 602 603 /** 604 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 605 */ 606 struct dmub_rb_cmd_read_modify_write { 607 struct dmub_cmd_header header; /**< command header */ 608 /** 609 * Read modify write sequence. 610 */ 611 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 612 }; 613 614 /* 615 * Update a register with specified masks and values sequeunce 616 * 617 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 618 * 619 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 620 * 621 * 622 * USE CASE: 623 * 1. auto-increment register where additional read would update pointer and produce wrong result 624 * 2. toggle a bit without read in the middle 625 */ 626 627 struct dmub_cmd_reg_field_update_sequence { 628 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 629 uint32_t modify_value; /**< value to update with */ 630 }; 631 632 /** 633 * Maximum number of ops in field update sequence. 634 */ 635 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 636 637 /** 638 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 639 */ 640 struct dmub_rb_cmd_reg_field_update_sequence { 641 struct dmub_cmd_header header; /**< command header */ 642 uint32_t addr; /**< register address */ 643 /** 644 * Field update sequence. 645 */ 646 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 647 }; 648 649 650 /** 651 * Maximum number of burst write values. 652 */ 653 #define DMUB_BURST_WRITE_VALUES__MAX 14 654 655 /* 656 * struct dmub_rb_cmd_burst_write - Burst write 657 * 658 * support use case such as writing out LUTs. 659 * 660 * 60 payload bytes can hold up to 14 values to write to given address 661 * 662 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 663 */ 664 struct dmub_rb_cmd_burst_write { 665 struct dmub_cmd_header header; /**< command header */ 666 uint32_t addr; /**< register start address */ 667 /** 668 * Burst write register values. 669 */ 670 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 671 }; 672 673 /** 674 * struct dmub_rb_cmd_common - Common command header 675 */ 676 struct dmub_rb_cmd_common { 677 struct dmub_cmd_header header; /**< command header */ 678 /** 679 * Padding to RB_CMD_SIZE 680 */ 681 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 682 }; 683 684 /** 685 * struct dmub_cmd_reg_wait_data - Register wait data 686 */ 687 struct dmub_cmd_reg_wait_data { 688 uint32_t addr; /**< Register address */ 689 uint32_t mask; /**< Mask for register bits */ 690 uint32_t condition_field_value; /**< Value to wait for */ 691 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 692 }; 693 694 /** 695 * struct dmub_rb_cmd_reg_wait - Register wait command 696 */ 697 struct dmub_rb_cmd_reg_wait { 698 struct dmub_cmd_header header; /**< Command header */ 699 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 700 }; 701 702 /** 703 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 704 * 705 * Reprograms surface parameters to avoid underflow. 706 */ 707 struct dmub_cmd_PLAT_54186_wa { 708 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 709 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 710 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 711 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 712 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 713 struct { 714 uint8_t hubp_inst : 4; /**< HUBP instance */ 715 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 716 uint8_t immediate :1; /**< Immediate flip */ 717 uint8_t vmid : 4; /**< VMID */ 718 uint8_t grph_stereo : 1; /**< 1 if stereo */ 719 uint32_t reserved : 21; /**< Reserved */ 720 } flip_params; /**< Pageflip parameters */ 721 uint32_t reserved[9]; /**< Reserved bits */ 722 }; 723 724 /** 725 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 726 */ 727 struct dmub_rb_cmd_PLAT_54186_wa { 728 struct dmub_cmd_header header; /**< Command header */ 729 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 730 }; 731 732 /** 733 * struct dmub_rb_cmd_mall - MALL command data. 734 */ 735 struct dmub_rb_cmd_mall { 736 struct dmub_cmd_header header; /**< Common command header */ 737 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 738 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 739 uint32_t tmr_delay; /**< Timer delay */ 740 uint32_t tmr_scale; /**< Timer scale */ 741 uint16_t cursor_width; /**< Cursor width in pixels */ 742 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 743 uint16_t cursor_height; /**< Cursor height in pixels */ 744 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 745 uint8_t debug_bits; /**< Debug bits */ 746 747 uint8_t reserved1; /**< Reserved bits */ 748 uint8_t reserved2; /**< Reserved bits */ 749 }; 750 751 /** 752 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 753 */ 754 struct dmub_cmd_digx_encoder_control_data { 755 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 756 }; 757 758 /** 759 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 760 */ 761 struct dmub_rb_cmd_digx_encoder_control { 762 struct dmub_cmd_header header; /**< header */ 763 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 764 }; 765 766 /** 767 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 768 */ 769 struct dmub_cmd_set_pixel_clock_data { 770 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 771 }; 772 773 /** 774 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 775 */ 776 struct dmub_rb_cmd_set_pixel_clock { 777 struct dmub_cmd_header header; /**< header */ 778 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 779 }; 780 781 /** 782 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 783 */ 784 struct dmub_cmd_enable_disp_power_gating_data { 785 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 786 }; 787 788 /** 789 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 790 */ 791 struct dmub_rb_cmd_enable_disp_power_gating { 792 struct dmub_cmd_header header; /**< header */ 793 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 794 }; 795 796 /** 797 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 798 */ 799 struct dmub_dig_transmitter_control_data_v1_7 { 800 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 801 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 802 union { 803 uint8_t digmode; /**< enum atom_encode_mode_def */ 804 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 805 } mode_laneset; 806 uint8_t lanenum; /**< Number of lanes */ 807 union { 808 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 809 } symclk_units; 810 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 811 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 812 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 813 uint8_t reserved0; /**< For future use */ 814 uint8_t reserved1; /**< For future use */ 815 uint8_t reserved2[3]; /**< For future use */ 816 uint32_t reserved3[11]; /**< For future use */ 817 }; 818 819 /** 820 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 821 */ 822 union dmub_cmd_dig1_transmitter_control_data { 823 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 824 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 825 }; 826 827 /** 828 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 829 */ 830 struct dmub_rb_cmd_dig1_transmitter_control { 831 struct dmub_cmd_header header; /**< header */ 832 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 833 }; 834 835 /** 836 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 837 */ 838 struct dmub_rb_cmd_dpphy_init { 839 struct dmub_cmd_header header; /**< header */ 840 uint8_t reserved[60]; /**< reserved bits */ 841 }; 842 843 /** 844 * enum dp_aux_request_action - DP AUX request command listing. 845 * 846 * 4 AUX request command bits are shifted to high nibble. 847 */ 848 enum dp_aux_request_action { 849 /** I2C-over-AUX write request */ 850 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 851 /** I2C-over-AUX read request */ 852 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 853 /** I2C-over-AUX write status request */ 854 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 855 /** I2C-over-AUX write request with MOT=1 */ 856 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 857 /** I2C-over-AUX read request with MOT=1 */ 858 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 859 /** I2C-over-AUX write status request with MOT=1 */ 860 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 861 /** Native AUX write request */ 862 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 863 /** Native AUX read request */ 864 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 865 }; 866 867 /** 868 * enum aux_return_code_type - DP AUX process return code listing. 869 */ 870 enum aux_return_code_type { 871 /** AUX process succeeded */ 872 AUX_RET_SUCCESS = 0, 873 /** AUX process failed with unknown reason */ 874 AUX_RET_ERROR_UNKNOWN, 875 /** AUX process completed with invalid reply */ 876 AUX_RET_ERROR_INVALID_REPLY, 877 /** AUX process timed out */ 878 AUX_RET_ERROR_TIMEOUT, 879 /** HPD was low during AUX process */ 880 AUX_RET_ERROR_HPD_DISCON, 881 /** Failed to acquire AUX engine */ 882 AUX_RET_ERROR_ENGINE_ACQUIRE, 883 /** AUX request not supported */ 884 AUX_RET_ERROR_INVALID_OPERATION, 885 /** AUX process not available */ 886 AUX_RET_ERROR_PROTOCOL_ERROR, 887 }; 888 889 /** 890 * enum aux_channel_type - DP AUX channel type listing. 891 */ 892 enum aux_channel_type { 893 /** AUX thru Legacy DP AUX */ 894 AUX_CHANNEL_LEGACY_DDC, 895 /** AUX thru DPIA DP tunneling */ 896 AUX_CHANNEL_DPIA 897 }; 898 899 /** 900 * struct aux_transaction_parameters - DP AUX request transaction data 901 */ 902 struct aux_transaction_parameters { 903 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 904 uint8_t action; /**< enum dp_aux_request_action */ 905 uint8_t length; /**< DP AUX request data length */ 906 uint8_t reserved; /**< For future use */ 907 uint32_t address; /**< DP AUX address */ 908 uint8_t data[16]; /**< DP AUX write data */ 909 }; 910 911 /** 912 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 913 */ 914 struct dmub_cmd_dp_aux_control_data { 915 uint8_t instance; /**< AUX instance or DPIA instance */ 916 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 917 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 918 uint8_t reserved0; /**< For future use */ 919 uint16_t timeout; /**< timeout time in us */ 920 uint16_t reserved1; /**< For future use */ 921 enum aux_channel_type type; /**< enum aux_channel_type */ 922 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 923 }; 924 925 /** 926 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 927 */ 928 struct dmub_rb_cmd_dp_aux_access { 929 /** 930 * Command header. 931 */ 932 struct dmub_cmd_header header; 933 /** 934 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 935 */ 936 struct dmub_cmd_dp_aux_control_data aux_control; 937 }; 938 939 /** 940 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 941 */ 942 struct dmub_rb_cmd_outbox1_enable { 943 /** 944 * Command header. 945 */ 946 struct dmub_cmd_header header; 947 /** 948 * enable: 0x0 -> disable outbox1 notification (default value) 949 * 0x1 -> enable outbox1 notification 950 */ 951 uint32_t enable; 952 }; 953 954 /* DP AUX Reply command - OutBox Cmd */ 955 /** 956 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 957 */ 958 struct aux_reply_data { 959 /** 960 * Aux cmd 961 */ 962 uint8_t command; 963 /** 964 * Aux reply data length (max: 16 bytes) 965 */ 966 uint8_t length; 967 /** 968 * Alignment only 969 */ 970 uint8_t pad[2]; 971 /** 972 * Aux reply data 973 */ 974 uint8_t data[16]; 975 }; 976 977 /** 978 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 979 */ 980 struct aux_reply_control_data { 981 /** 982 * Reserved for future use 983 */ 984 uint32_t handle; 985 /** 986 * Aux Instance 987 */ 988 uint8_t instance; 989 /** 990 * Aux transaction result: definition in enum aux_return_code_type 991 */ 992 uint8_t result; 993 /** 994 * Alignment only 995 */ 996 uint16_t pad; 997 }; 998 999 /** 1000 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1001 */ 1002 struct dmub_rb_cmd_dp_aux_reply { 1003 /** 1004 * Command header. 1005 */ 1006 struct dmub_cmd_header header; 1007 /** 1008 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1009 */ 1010 struct aux_reply_control_data control; 1011 /** 1012 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1013 */ 1014 struct aux_reply_data reply_data; 1015 }; 1016 1017 /* DP HPD Notify command - OutBox Cmd */ 1018 /** 1019 * DP HPD Type 1020 */ 1021 enum dp_hpd_type { 1022 /** 1023 * Normal DP HPD 1024 */ 1025 DP_HPD = 0, 1026 /** 1027 * DP HPD short pulse 1028 */ 1029 DP_IRQ 1030 }; 1031 1032 /** 1033 * DP HPD Status 1034 */ 1035 enum dp_hpd_status { 1036 /** 1037 * DP_HPD status low 1038 */ 1039 DP_HPD_UNPLUG = 0, 1040 /** 1041 * DP_HPD status high 1042 */ 1043 DP_HPD_PLUG 1044 }; 1045 1046 /** 1047 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1048 */ 1049 struct dp_hpd_data { 1050 /** 1051 * DP HPD instance 1052 */ 1053 uint8_t instance; 1054 /** 1055 * HPD type 1056 */ 1057 uint8_t hpd_type; 1058 /** 1059 * HPD status: only for type: DP_HPD to indicate status 1060 */ 1061 uint8_t hpd_status; 1062 /** 1063 * Alignment only 1064 */ 1065 uint8_t pad; 1066 }; 1067 1068 /** 1069 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1070 */ 1071 struct dmub_rb_cmd_dp_hpd_notify { 1072 /** 1073 * Command header. 1074 */ 1075 struct dmub_cmd_header header; 1076 /** 1077 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1078 */ 1079 struct dp_hpd_data hpd_data; 1080 }; 1081 1082 /* 1083 * Command IDs should be treated as stable ABI. 1084 * Do not reuse or modify IDs. 1085 */ 1086 1087 /** 1088 * PSR command sub-types. 1089 */ 1090 enum dmub_cmd_psr_type { 1091 /** 1092 * Set PSR version support. 1093 */ 1094 DMUB_CMD__PSR_SET_VERSION = 0, 1095 /** 1096 * Copy driver-calculated parameters to PSR state. 1097 */ 1098 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1099 /** 1100 * Enable PSR. 1101 */ 1102 DMUB_CMD__PSR_ENABLE = 2, 1103 1104 /** 1105 * Disable PSR. 1106 */ 1107 DMUB_CMD__PSR_DISABLE = 3, 1108 1109 /** 1110 * Set PSR level. 1111 * PSR level is a 16-bit value dicated by driver that 1112 * will enable/disable different functionality. 1113 */ 1114 DMUB_CMD__PSR_SET_LEVEL = 4, 1115 1116 /** 1117 * Forces PSR enabled until an explicit PSR disable call. 1118 */ 1119 DMUB_CMD__PSR_FORCE_STATIC = 5, 1120 }; 1121 1122 /** 1123 * PSR versions. 1124 */ 1125 enum psr_version { 1126 /** 1127 * PSR version 1. 1128 */ 1129 PSR_VERSION_1 = 0, 1130 /** 1131 * PSR not supported. 1132 */ 1133 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1134 }; 1135 1136 /** 1137 * enum dmub_cmd_mall_type - MALL commands 1138 */ 1139 enum dmub_cmd_mall_type { 1140 /** 1141 * Allows display refresh from MALL. 1142 */ 1143 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1144 /** 1145 * Disallows display refresh from MALL. 1146 */ 1147 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1148 /** 1149 * Cursor copy for MALL. 1150 */ 1151 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1152 /** 1153 * Controls DF requests. 1154 */ 1155 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1156 }; 1157 1158 1159 /** 1160 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1161 */ 1162 struct dmub_cmd_psr_copy_settings_data { 1163 /** 1164 * Flags that can be set by driver to change some PSR behaviour. 1165 */ 1166 union dmub_psr_debug_flags debug; 1167 /** 1168 * 16-bit value dicated by driver that will enable/disable different functionality. 1169 */ 1170 uint16_t psr_level; 1171 /** 1172 * DPP HW instance. 1173 */ 1174 uint8_t dpp_inst; 1175 /** 1176 * MPCC HW instance. 1177 * Not used in dmub fw, 1178 * dmub fw will get active opp by reading odm registers. 1179 */ 1180 uint8_t mpcc_inst; 1181 /** 1182 * OPP HW instance. 1183 * Not used in dmub fw, 1184 * dmub fw will get active opp by reading odm registers. 1185 */ 1186 uint8_t opp_inst; 1187 /** 1188 * OTG HW instance. 1189 */ 1190 uint8_t otg_inst; 1191 /** 1192 * DIG FE HW instance. 1193 */ 1194 uint8_t digfe_inst; 1195 /** 1196 * DIG BE HW instance. 1197 */ 1198 uint8_t digbe_inst; 1199 /** 1200 * DP PHY HW instance. 1201 */ 1202 uint8_t dpphy_inst; 1203 /** 1204 * AUX HW instance. 1205 */ 1206 uint8_t aux_inst; 1207 /** 1208 * Determines if SMU optimzations are enabled/disabled. 1209 */ 1210 uint8_t smu_optimizations_en; 1211 /** 1212 * Unused. 1213 * TODO: Remove. 1214 */ 1215 uint8_t frame_delay; 1216 /** 1217 * If RFB setup time is greater than the total VBLANK time, 1218 * it is not possible for the sink to capture the video frame 1219 * in the same frame the SDP is sent. In this case, 1220 * the frame capture indication bit should be set and an extra 1221 * static frame should be transmitted to the sink. 1222 */ 1223 uint8_t frame_cap_ind; 1224 /** 1225 * Explicit padding to 4 byte boundary. 1226 */ 1227 uint8_t pad[2]; 1228 /** 1229 * Multi-display optimizations are implemented on certain ASICs. 1230 */ 1231 uint8_t multi_disp_optimizations_en; 1232 /** 1233 * The last possible line SDP may be transmitted without violating 1234 * the RFB setup time or entering the active video frame. 1235 */ 1236 uint16_t init_sdp_deadline; 1237 /** 1238 * Explicit padding to 4 byte boundary. 1239 */ 1240 uint16_t pad2; 1241 /** 1242 * Length of each horizontal line in us. 1243 */ 1244 uint32_t line_time_in_us; 1245 /** 1246 * FEC enable status in driver 1247 */ 1248 uint8_t fec_enable_status; 1249 /** 1250 * FEC re-enable delay when PSR exit. 1251 * unit is 100us, range form 0~255(0xFF). 1252 */ 1253 uint8_t fec_enable_delay_in100us; 1254 /** 1255 * Explicit padding to 4 byte boundary. 1256 */ 1257 uint8_t pad3[2]; 1258 }; 1259 1260 /** 1261 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1262 */ 1263 struct dmub_rb_cmd_psr_copy_settings { 1264 /** 1265 * Command header. 1266 */ 1267 struct dmub_cmd_header header; 1268 /** 1269 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1270 */ 1271 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1272 }; 1273 1274 /** 1275 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1276 */ 1277 struct dmub_cmd_psr_set_level_data { 1278 /** 1279 * 16-bit value dicated by driver that will enable/disable different functionality. 1280 */ 1281 uint16_t psr_level; 1282 /** 1283 * Explicit padding to 4 byte boundary. 1284 */ 1285 uint8_t pad[2]; 1286 }; 1287 1288 /** 1289 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1290 */ 1291 struct dmub_rb_cmd_psr_set_level { 1292 /** 1293 * Command header. 1294 */ 1295 struct dmub_cmd_header header; 1296 /** 1297 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1298 */ 1299 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1300 }; 1301 1302 /** 1303 * Definition of a DMUB_CMD__PSR_ENABLE command. 1304 * PSR enable/disable is controlled using the sub_type. 1305 */ 1306 struct dmub_rb_cmd_psr_enable { 1307 /** 1308 * Command header. 1309 */ 1310 struct dmub_cmd_header header; 1311 }; 1312 1313 /** 1314 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1315 */ 1316 struct dmub_cmd_psr_set_version_data { 1317 /** 1318 * PSR version that FW should implement. 1319 */ 1320 enum psr_version version; 1321 }; 1322 1323 /** 1324 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1325 */ 1326 struct dmub_rb_cmd_psr_set_version { 1327 /** 1328 * Command header. 1329 */ 1330 struct dmub_cmd_header header; 1331 /** 1332 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1333 */ 1334 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1335 }; 1336 1337 /** 1338 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1339 */ 1340 struct dmub_rb_cmd_psr_force_static { 1341 /** 1342 * Command header. 1343 */ 1344 struct dmub_cmd_header header; 1345 }; 1346 1347 /** 1348 * Set of HW components that can be locked. 1349 */ 1350 union dmub_hw_lock_flags { 1351 /** 1352 * Set of HW components that can be locked. 1353 */ 1354 struct { 1355 /** 1356 * Lock/unlock OTG master update lock. 1357 */ 1358 uint8_t lock_pipe : 1; 1359 /** 1360 * Lock/unlock cursor. 1361 */ 1362 uint8_t lock_cursor : 1; 1363 /** 1364 * Lock/unlock global update lock. 1365 */ 1366 uint8_t lock_dig : 1; 1367 /** 1368 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1369 */ 1370 uint8_t triple_buffer_lock : 1; 1371 } bits; 1372 1373 /** 1374 * Union for HW Lock flags. 1375 */ 1376 uint8_t u8All; 1377 }; 1378 1379 /** 1380 * Instances of HW to be locked. 1381 */ 1382 struct dmub_hw_lock_inst_flags { 1383 /** 1384 * OTG HW instance for OTG master update lock. 1385 */ 1386 uint8_t otg_inst; 1387 /** 1388 * OPP instance for cursor lock. 1389 */ 1390 uint8_t opp_inst; 1391 /** 1392 * OTG HW instance for global update lock. 1393 * TODO: Remove, and re-use otg_inst. 1394 */ 1395 uint8_t dig_inst; 1396 /** 1397 * Explicit pad to 4 byte boundary. 1398 */ 1399 uint8_t pad; 1400 }; 1401 1402 /** 1403 * Clients that can acquire the HW Lock Manager. 1404 */ 1405 enum hw_lock_client { 1406 /** 1407 * Driver is the client of HW Lock Manager. 1408 */ 1409 HW_LOCK_CLIENT_DRIVER = 0, 1410 /** 1411 * FW is the client of HW Lock Manager. 1412 */ 1413 HW_LOCK_CLIENT_FW, 1414 /** 1415 * Invalid client. 1416 */ 1417 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1418 }; 1419 1420 /** 1421 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1422 */ 1423 struct dmub_cmd_lock_hw_data { 1424 /** 1425 * Specifies the client accessing HW Lock Manager. 1426 */ 1427 enum hw_lock_client client; 1428 /** 1429 * HW instances to be locked. 1430 */ 1431 struct dmub_hw_lock_inst_flags inst_flags; 1432 /** 1433 * Which components to be locked. 1434 */ 1435 union dmub_hw_lock_flags hw_locks; 1436 /** 1437 * Specifies lock/unlock. 1438 */ 1439 uint8_t lock; 1440 /** 1441 * HW can be unlocked separately from releasing the HW Lock Mgr. 1442 * This flag is set if the client wishes to release the object. 1443 */ 1444 uint8_t should_release; 1445 /** 1446 * Explicit padding to 4 byte boundary. 1447 */ 1448 uint8_t pad; 1449 }; 1450 1451 /** 1452 * Definition of a DMUB_CMD__HW_LOCK command. 1453 * Command is used by driver and FW. 1454 */ 1455 struct dmub_rb_cmd_lock_hw { 1456 /** 1457 * Command header. 1458 */ 1459 struct dmub_cmd_header header; 1460 /** 1461 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1462 */ 1463 struct dmub_cmd_lock_hw_data lock_hw_data; 1464 }; 1465 1466 /** 1467 * ABM command sub-types. 1468 */ 1469 enum dmub_cmd_abm_type { 1470 /** 1471 * Initialize parameters for ABM algorithm. 1472 * Data is passed through an indirect buffer. 1473 */ 1474 DMUB_CMD__ABM_INIT_CONFIG = 0, 1475 /** 1476 * Set OTG and panel HW instance. 1477 */ 1478 DMUB_CMD__ABM_SET_PIPE = 1, 1479 /** 1480 * Set user requested backklight level. 1481 */ 1482 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1483 /** 1484 * Set ABM operating/aggression level. 1485 */ 1486 DMUB_CMD__ABM_SET_LEVEL = 3, 1487 /** 1488 * Set ambient light level. 1489 */ 1490 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1491 /** 1492 * Enable/disable fractional duty cycle for backlight PWM. 1493 */ 1494 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1495 }; 1496 1497 /** 1498 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1499 * Requirements: 1500 * - Padded explicitly to 32-bit boundary. 1501 * - Must ensure this structure matches the one on driver-side, 1502 * otherwise it won't be aligned. 1503 */ 1504 struct abm_config_table { 1505 /** 1506 * Gamma curve thresholds, used for crgb conversion. 1507 */ 1508 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1509 /** 1510 * Gamma curve offsets, used for crgb conversion. 1511 */ 1512 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1513 /** 1514 * Gamma curve slopes, used for crgb conversion. 1515 */ 1516 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1517 /** 1518 * Custom backlight curve thresholds. 1519 */ 1520 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 1521 /** 1522 * Custom backlight curve offsets. 1523 */ 1524 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 1525 /** 1526 * Ambient light thresholds. 1527 */ 1528 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 1529 /** 1530 * Minimum programmable backlight. 1531 */ 1532 uint16_t min_abm_backlight; // 122B 1533 /** 1534 * Minimum reduction values. 1535 */ 1536 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 1537 /** 1538 * Maximum reduction values. 1539 */ 1540 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 1541 /** 1542 * Bright positive gain. 1543 */ 1544 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 1545 /** 1546 * Dark negative gain. 1547 */ 1548 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 1549 /** 1550 * Hybrid factor. 1551 */ 1552 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 1553 /** 1554 * Contrast factor. 1555 */ 1556 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 1557 /** 1558 * Deviation gain. 1559 */ 1560 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 1561 /** 1562 * Minimum knee. 1563 */ 1564 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 1565 /** 1566 * Maximum knee. 1567 */ 1568 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 1569 /** 1570 * Unused. 1571 */ 1572 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 1573 /** 1574 * Explicit padding to 4 byte boundary. 1575 */ 1576 uint8_t pad3[3]; // 229B 1577 /** 1578 * Backlight ramp reduction. 1579 */ 1580 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 1581 /** 1582 * Backlight ramp start. 1583 */ 1584 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 1585 }; 1586 1587 /** 1588 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1589 */ 1590 struct dmub_cmd_abm_set_pipe_data { 1591 /** 1592 * OTG HW instance. 1593 */ 1594 uint8_t otg_inst; 1595 1596 /** 1597 * Panel Control HW instance. 1598 */ 1599 uint8_t panel_inst; 1600 1601 /** 1602 * Controls how ABM will interpret a set pipe or set level command. 1603 */ 1604 uint8_t set_pipe_option; 1605 1606 /** 1607 * Unused. 1608 * TODO: Remove. 1609 */ 1610 uint8_t ramping_boundary; 1611 }; 1612 1613 /** 1614 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1615 */ 1616 struct dmub_rb_cmd_abm_set_pipe { 1617 /** 1618 * Command header. 1619 */ 1620 struct dmub_cmd_header header; 1621 1622 /** 1623 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1624 */ 1625 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 1626 }; 1627 1628 /** 1629 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1630 */ 1631 struct dmub_cmd_abm_set_backlight_data { 1632 /** 1633 * Number of frames to ramp to backlight user level. 1634 */ 1635 uint32_t frame_ramp; 1636 1637 /** 1638 * Requested backlight level from user. 1639 */ 1640 uint32_t backlight_user_level; 1641 1642 /** 1643 * ABM control version. 1644 */ 1645 uint8_t version; 1646 1647 /** 1648 * Panel Control HW instance mask. 1649 * Bit 0 is Panel Control HW instance 0. 1650 * Bit 1 is Panel Control HW instance 1. 1651 */ 1652 uint8_t panel_mask; 1653 1654 /** 1655 * Explicit padding to 4 byte boundary. 1656 */ 1657 uint8_t pad[2]; 1658 }; 1659 1660 /** 1661 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 1662 */ 1663 struct dmub_rb_cmd_abm_set_backlight { 1664 /** 1665 * Command header. 1666 */ 1667 struct dmub_cmd_header header; 1668 1669 /** 1670 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1671 */ 1672 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 1673 }; 1674 1675 /** 1676 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1677 */ 1678 struct dmub_cmd_abm_set_level_data { 1679 /** 1680 * Set current ABM operating/aggression level. 1681 */ 1682 uint32_t level; 1683 1684 /** 1685 * ABM control version. 1686 */ 1687 uint8_t version; 1688 1689 /** 1690 * Panel Control HW instance mask. 1691 * Bit 0 is Panel Control HW instance 0. 1692 * Bit 1 is Panel Control HW instance 1. 1693 */ 1694 uint8_t panel_mask; 1695 1696 /** 1697 * Explicit padding to 4 byte boundary. 1698 */ 1699 uint8_t pad[2]; 1700 }; 1701 1702 /** 1703 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 1704 */ 1705 struct dmub_rb_cmd_abm_set_level { 1706 /** 1707 * Command header. 1708 */ 1709 struct dmub_cmd_header header; 1710 1711 /** 1712 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1713 */ 1714 struct dmub_cmd_abm_set_level_data abm_set_level_data; 1715 }; 1716 1717 /** 1718 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1719 */ 1720 struct dmub_cmd_abm_set_ambient_level_data { 1721 /** 1722 * Ambient light sensor reading from OS. 1723 */ 1724 uint32_t ambient_lux; 1725 1726 /** 1727 * ABM control version. 1728 */ 1729 uint8_t version; 1730 1731 /** 1732 * Panel Control HW instance mask. 1733 * Bit 0 is Panel Control HW instance 0. 1734 * Bit 1 is Panel Control HW instance 1. 1735 */ 1736 uint8_t panel_mask; 1737 1738 /** 1739 * Explicit padding to 4 byte boundary. 1740 */ 1741 uint8_t pad[2]; 1742 }; 1743 1744 /** 1745 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1746 */ 1747 struct dmub_rb_cmd_abm_set_ambient_level { 1748 /** 1749 * Command header. 1750 */ 1751 struct dmub_cmd_header header; 1752 1753 /** 1754 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1755 */ 1756 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 1757 }; 1758 1759 /** 1760 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1761 */ 1762 struct dmub_cmd_abm_set_pwm_frac_data { 1763 /** 1764 * Enable/disable fractional duty cycle for backlight PWM. 1765 * TODO: Convert to uint8_t. 1766 */ 1767 uint32_t fractional_pwm; 1768 1769 /** 1770 * ABM control version. 1771 */ 1772 uint8_t version; 1773 1774 /** 1775 * Panel Control HW instance mask. 1776 * Bit 0 is Panel Control HW instance 0. 1777 * Bit 1 is Panel Control HW instance 1. 1778 */ 1779 uint8_t panel_mask; 1780 1781 /** 1782 * Explicit padding to 4 byte boundary. 1783 */ 1784 uint8_t pad[2]; 1785 }; 1786 1787 /** 1788 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 1789 */ 1790 struct dmub_rb_cmd_abm_set_pwm_frac { 1791 /** 1792 * Command header. 1793 */ 1794 struct dmub_cmd_header header; 1795 1796 /** 1797 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1798 */ 1799 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 1800 }; 1801 1802 /** 1803 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 1804 */ 1805 struct dmub_cmd_abm_init_config_data { 1806 /** 1807 * Location of indirect buffer used to pass init data to ABM. 1808 */ 1809 union dmub_addr src; 1810 1811 /** 1812 * Indirect buffer length. 1813 */ 1814 uint16_t bytes; 1815 1816 1817 /** 1818 * ABM control version. 1819 */ 1820 uint8_t version; 1821 1822 /** 1823 * Panel Control HW instance mask. 1824 * Bit 0 is Panel Control HW instance 0. 1825 * Bit 1 is Panel Control HW instance 1. 1826 */ 1827 uint8_t panel_mask; 1828 1829 /** 1830 * Explicit padding to 4 byte boundary. 1831 */ 1832 uint8_t pad[2]; 1833 }; 1834 1835 /** 1836 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 1837 */ 1838 struct dmub_rb_cmd_abm_init_config { 1839 /** 1840 * Command header. 1841 */ 1842 struct dmub_cmd_header header; 1843 1844 /** 1845 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 1846 */ 1847 struct dmub_cmd_abm_init_config_data abm_init_config_data; 1848 }; 1849 1850 /** 1851 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 1852 */ 1853 struct dmub_cmd_query_feature_caps_data { 1854 /** 1855 * DMUB feature capabilities. 1856 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 1857 */ 1858 struct dmub_feature_caps feature_caps; 1859 }; 1860 1861 /** 1862 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 1863 */ 1864 struct dmub_rb_cmd_query_feature_caps { 1865 /** 1866 * Command header. 1867 */ 1868 struct dmub_cmd_header header; 1869 /** 1870 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 1871 */ 1872 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 1873 }; 1874 1875 struct dmub_optc_state { 1876 uint32_t v_total_max; 1877 uint32_t v_total_min; 1878 uint32_t v_total_mid; 1879 uint32_t v_total_mid_frame_num; 1880 uint32_t tg_inst; 1881 uint32_t enable_manual_trigger; 1882 uint32_t clear_force_vsync; 1883 }; 1884 1885 struct dmub_rb_cmd_drr_update { 1886 struct dmub_cmd_header header; 1887 struct dmub_optc_state dmub_optc_state_req; 1888 }; 1889 1890 /** 1891 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1892 */ 1893 struct dmub_cmd_lvtma_control_data { 1894 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 1895 uint8_t reserved_0[3]; /**< For future use */ 1896 uint8_t panel_inst; /**< LVTMA control instance */ 1897 uint8_t reserved_1[3]; /**< For future use */ 1898 }; 1899 1900 /** 1901 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1902 */ 1903 struct dmub_rb_cmd_lvtma_control { 1904 /** 1905 * Command header. 1906 */ 1907 struct dmub_cmd_header header; 1908 /** 1909 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1910 */ 1911 struct dmub_cmd_lvtma_control_data data; 1912 }; 1913 1914 /** 1915 * union dmub_rb_cmd - DMUB inbox command. 1916 */ 1917 union dmub_rb_cmd { 1918 struct dmub_rb_cmd_lock_hw lock_hw; 1919 /** 1920 * Elements shared with all commands. 1921 */ 1922 struct dmub_rb_cmd_common cmd_common; 1923 /** 1924 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 1925 */ 1926 struct dmub_rb_cmd_read_modify_write read_modify_write; 1927 /** 1928 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 1929 */ 1930 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 1931 /** 1932 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 1933 */ 1934 struct dmub_rb_cmd_burst_write burst_write; 1935 /** 1936 * Definition of a DMUB_CMD__REG_REG_WAIT command. 1937 */ 1938 struct dmub_rb_cmd_reg_wait reg_wait; 1939 /** 1940 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 1941 */ 1942 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 1943 /** 1944 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 1945 */ 1946 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 1947 /** 1948 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 1949 */ 1950 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 1951 /** 1952 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 1953 */ 1954 struct dmub_rb_cmd_dpphy_init dpphy_init; 1955 /** 1956 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 1957 */ 1958 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 1959 /** 1960 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1961 */ 1962 struct dmub_rb_cmd_psr_set_version psr_set_version; 1963 /** 1964 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1965 */ 1966 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 1967 /** 1968 * Definition of a DMUB_CMD__PSR_ENABLE command. 1969 */ 1970 struct dmub_rb_cmd_psr_enable psr_enable; 1971 /** 1972 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1973 */ 1974 struct dmub_rb_cmd_psr_set_level psr_set_level; 1975 /** 1976 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1977 */ 1978 struct dmub_rb_cmd_psr_force_static psr_force_static; 1979 /** 1980 * Definition of a DMUB_CMD__PLAT_54186_WA command. 1981 */ 1982 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 1983 /** 1984 * Definition of a DMUB_CMD__MALL command. 1985 */ 1986 struct dmub_rb_cmd_mall mall; 1987 /** 1988 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1989 */ 1990 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 1991 1992 /** 1993 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 1994 */ 1995 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 1996 1997 /** 1998 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 1999 */ 2000 struct dmub_rb_cmd_abm_set_level abm_set_level; 2001 2002 /** 2003 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2004 */ 2005 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2006 2007 /** 2008 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2009 */ 2010 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2011 2012 /** 2013 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2014 */ 2015 struct dmub_rb_cmd_abm_init_config abm_init_config; 2016 2017 /** 2018 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2019 */ 2020 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2021 2022 /** 2023 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2024 */ 2025 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2026 2027 /** 2028 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2029 */ 2030 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2031 struct dmub_rb_cmd_drr_update drr_update; 2032 /** 2033 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2034 */ 2035 struct dmub_rb_cmd_lvtma_control lvtma_control; 2036 }; 2037 2038 /** 2039 * union dmub_rb_out_cmd - Outbox command 2040 */ 2041 union dmub_rb_out_cmd { 2042 /** 2043 * Parameters common to every command. 2044 */ 2045 struct dmub_rb_cmd_common cmd_common; 2046 /** 2047 * AUX reply command. 2048 */ 2049 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2050 /** 2051 * HPD notify command. 2052 */ 2053 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2054 }; 2055 #pragma pack(pop) 2056 2057 2058 //============================================================================== 2059 //</DMUB_CMD>=================================================================== 2060 //============================================================================== 2061 //< DMUB_RB>==================================================================== 2062 //============================================================================== 2063 2064 #if defined(__cplusplus) 2065 extern "C" { 2066 #endif 2067 2068 /** 2069 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2070 */ 2071 struct dmub_rb_init_params { 2072 void *ctx; /**< Caller provided context pointer */ 2073 void *base_address; /**< CPU base address for ring's data */ 2074 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2075 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2076 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2077 }; 2078 2079 /** 2080 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2081 */ 2082 struct dmub_rb { 2083 void *base_address; /**< CPU address for the ring's data */ 2084 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2085 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2086 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2087 2088 void *ctx; /**< Caller provided context pointer */ 2089 void *dmub; /**< Pointer to the DMUB interface */ 2090 }; 2091 2092 /** 2093 * @brief Checks if the ringbuffer is empty. 2094 * 2095 * @param rb DMUB Ringbuffer 2096 * @return true if empty 2097 * @return false otherwise 2098 */ 2099 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2100 { 2101 return (rb->wrpt == rb->rptr); 2102 } 2103 2104 /** 2105 * @brief Checks if the ringbuffer is full 2106 * 2107 * @param rb DMUB Ringbuffer 2108 * @return true if full 2109 * @return false otherwise 2110 */ 2111 static inline bool dmub_rb_full(struct dmub_rb *rb) 2112 { 2113 uint32_t data_count; 2114 2115 if (rb->wrpt >= rb->rptr) 2116 data_count = rb->wrpt - rb->rptr; 2117 else 2118 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2119 2120 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2121 } 2122 2123 /** 2124 * @brief Pushes a command into the ringbuffer 2125 * 2126 * @param rb DMUB ringbuffer 2127 * @param cmd The command to push 2128 * @return true if the ringbuffer was not full 2129 * @return false otherwise 2130 */ 2131 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2132 const union dmub_rb_cmd *cmd) 2133 { 2134 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 2135 const uint64_t *src = (const uint64_t *)cmd; 2136 uint8_t i; 2137 2138 if (dmub_rb_full(rb)) 2139 return false; 2140 2141 // copying data 2142 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2143 *dst++ = *src++; 2144 2145 rb->wrpt += DMUB_RB_CMD_SIZE; 2146 2147 if (rb->wrpt >= rb->capacity) 2148 rb->wrpt %= rb->capacity; 2149 2150 return true; 2151 } 2152 2153 /** 2154 * @brief Pushes a command into the DMUB outbox ringbuffer 2155 * 2156 * @param rb DMUB outbox ringbuffer 2157 * @param cmd Outbox command 2158 * @return true if not full 2159 * @return false otherwise 2160 */ 2161 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2162 const union dmub_rb_out_cmd *cmd) 2163 { 2164 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2165 const uint8_t *src = (uint8_t *)cmd; 2166 2167 if (dmub_rb_full(rb)) 2168 return false; 2169 2170 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2171 2172 rb->wrpt += DMUB_RB_CMD_SIZE; 2173 2174 if (rb->wrpt >= rb->capacity) 2175 rb->wrpt %= rb->capacity; 2176 2177 return true; 2178 } 2179 2180 /** 2181 * @brief Returns the next unprocessed command in the ringbuffer. 2182 * 2183 * @param rb DMUB ringbuffer 2184 * @param cmd The command to return 2185 * @return true if not empty 2186 * @return false otherwise 2187 */ 2188 static inline bool dmub_rb_front(struct dmub_rb *rb, 2189 union dmub_rb_cmd **cmd) 2190 { 2191 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2192 2193 if (dmub_rb_empty(rb)) 2194 return false; 2195 2196 *cmd = (union dmub_rb_cmd *)rb_cmd; 2197 2198 return true; 2199 } 2200 2201 /** 2202 * @brief Returns the next unprocessed command in the outbox. 2203 * 2204 * @param rb DMUB outbox ringbuffer 2205 * @param cmd The outbox command to return 2206 * @return true if not empty 2207 * @return false otherwise 2208 */ 2209 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2210 union dmub_rb_out_cmd *cmd) 2211 { 2212 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 2213 uint64_t *dst = (uint64_t *)cmd; 2214 uint8_t i; 2215 2216 if (dmub_rb_empty(rb)) 2217 return false; 2218 2219 // copying data 2220 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2221 *dst++ = *src++; 2222 2223 return true; 2224 } 2225 2226 /** 2227 * @brief Removes the front entry in the ringbuffer. 2228 * 2229 * @param rb DMUB ringbuffer 2230 * @return true if the command was removed 2231 * @return false if there were no commands 2232 */ 2233 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 2234 { 2235 if (dmub_rb_empty(rb)) 2236 return false; 2237 2238 rb->rptr += DMUB_RB_CMD_SIZE; 2239 2240 if (rb->rptr >= rb->capacity) 2241 rb->rptr %= rb->capacity; 2242 2243 return true; 2244 } 2245 2246 /** 2247 * @brief Flushes commands in the ringbuffer to framebuffer memory. 2248 * 2249 * Avoids a race condition where DMCUB accesses memory while 2250 * there are still writes in flight to framebuffer. 2251 * 2252 * @param rb DMUB ringbuffer 2253 */ 2254 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 2255 { 2256 uint32_t rptr = rb->rptr; 2257 uint32_t wptr = rb->wrpt; 2258 2259 while (rptr != wptr) { 2260 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 2261 uint8_t i; 2262 2263 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2264 *data++; 2265 2266 rptr += DMUB_RB_CMD_SIZE; 2267 if (rptr >= rb->capacity) 2268 rptr %= rb->capacity; 2269 } 2270 } 2271 2272 /** 2273 * @brief Initializes a DMCUB ringbuffer 2274 * 2275 * @param rb DMUB ringbuffer 2276 * @param init_params initial configuration for the ringbuffer 2277 */ 2278 static inline void dmub_rb_init(struct dmub_rb *rb, 2279 struct dmub_rb_init_params *init_params) 2280 { 2281 rb->base_address = init_params->base_address; 2282 rb->capacity = init_params->capacity; 2283 rb->rptr = init_params->read_ptr; 2284 rb->wrpt = init_params->write_ptr; 2285 } 2286 2287 /** 2288 * @brief Copies output data from in/out commands into the given command. 2289 * 2290 * @param rb DMUB ringbuffer 2291 * @param cmd Command to copy data into 2292 */ 2293 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 2294 union dmub_rb_cmd *cmd) 2295 { 2296 // Copy rb entry back into command 2297 uint8_t *rd_ptr = (rb->rptr == 0) ? 2298 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 2299 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 2300 2301 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 2302 } 2303 2304 #if defined(__cplusplus) 2305 } 2306 #endif 2307 2308 //============================================================================== 2309 //</DMUB_RB>==================================================================== 2310 //============================================================================== 2311 2312 #endif /* _DMUB_CMD_H_ */ 2313