1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 #include <stdarg.h> 43 44 #include "atomfirmware.h" 45 46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 47 48 /* Firmware versioning. */ 49 #ifdef DMUB_EXPOSE_VERSION 50 #define DMUB_FW_VERSION_GIT_HASH 0xf3da2b656 51 #define DMUB_FW_VERSION_MAJOR 0 52 #define DMUB_FW_VERSION_MINOR 0 53 #define DMUB_FW_VERSION_REVISION 71 54 #define DMUB_FW_VERSION_TEST 0 55 #define DMUB_FW_VERSION_VBIOS 0 56 #define DMUB_FW_VERSION_HOTFIX 0 57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 62 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 63 64 #endif 65 66 //<DMUB_TYPES>================================================================== 67 /* Basic type definitions. */ 68 69 #define __forceinline inline 70 71 /** 72 * Flag from driver to indicate that ABM should be disabled gradually 73 * by slowly reversing all backlight programming and pixel compensation. 74 */ 75 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 76 77 /** 78 * Flag from driver to indicate that ABM should be disabled immediately 79 * and undo all backlight programming and pixel compensation. 80 */ 81 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 82 83 /** 84 * Flag from driver to indicate that ABM should be disabled immediately 85 * and keep the current backlight programming and pixel compensation. 86 */ 87 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 88 89 /** 90 * Flag from driver to set the current ABM pipe index or ABM operating level. 91 */ 92 #define SET_ABM_PIPE_NORMAL 1 93 94 /** 95 * Number of ambient light levels in ABM algorithm. 96 */ 97 #define NUM_AMBI_LEVEL 5 98 99 /** 100 * Number of operating/aggression levels in ABM algorithm. 101 */ 102 #define NUM_AGGR_LEVEL 4 103 104 /** 105 * Number of segments in the gamma curve. 106 */ 107 #define NUM_POWER_FN_SEGS 8 108 109 /** 110 * Number of segments in the backlight curve. 111 */ 112 #define NUM_BL_CURVE_SEGS 16 113 114 /* Maximum number of streams on any ASIC. */ 115 #define DMUB_MAX_STREAMS 6 116 117 /* Maximum number of planes on any ASIC. */ 118 #define DMUB_MAX_PLANES 6 119 120 /* Trace buffer offset for entry */ 121 #define TRACE_BUFFER_ENTRY_OFFSET 16 122 123 /** 124 * 125 * PSR control version legacy 126 */ 127 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 128 /** 129 * PSR control version with multi edp support 130 */ 131 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 132 133 134 /** 135 * ABM control version legacy 136 */ 137 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 138 139 /** 140 * ABM control version with multi edp support 141 */ 142 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 143 144 /** 145 * Physical framebuffer address location, 64-bit. 146 */ 147 #ifndef PHYSICAL_ADDRESS_LOC 148 #define PHYSICAL_ADDRESS_LOC union large_integer 149 #endif 150 151 /** 152 * OS/FW agnostic memcpy 153 */ 154 #ifndef dmub_memcpy 155 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 156 #endif 157 158 /** 159 * OS/FW agnostic memset 160 */ 161 #ifndef dmub_memset 162 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 163 #endif 164 165 #if defined(__cplusplus) 166 extern "C" { 167 #endif 168 169 /** 170 * OS/FW agnostic udelay 171 */ 172 #ifndef dmub_udelay 173 #define dmub_udelay(microseconds) udelay(microseconds) 174 #endif 175 176 /** 177 * Number of nanoseconds per DMUB tick. 178 * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default. 179 * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true. 180 */ 181 #define NS_PER_DMUB_TICK 10 182 183 /** 184 * union dmub_addr - DMUB physical/virtual 64-bit address. 185 */ 186 union dmub_addr { 187 struct { 188 uint32_t low_part; /**< Lower 32 bits */ 189 uint32_t high_part; /**< Upper 32 bits */ 190 } u; /*<< Low/high bit access */ 191 uint64_t quad_part; /*<< 64 bit address */ 192 }; 193 194 /** 195 * Flags that can be set by driver to change some PSR behaviour. 196 */ 197 union dmub_psr_debug_flags { 198 /** 199 * Debug flags. 200 */ 201 struct { 202 /** 203 * Enable visual confirm in FW. 204 */ 205 uint32_t visual_confirm : 1; 206 /** 207 * Use HW Lock Mgr object to do HW locking in FW. 208 */ 209 uint32_t use_hw_lock_mgr : 1; 210 211 /** 212 * Unused. 213 * TODO: Remove. 214 */ 215 uint32_t log_line_nums : 1; 216 } bitfields; 217 218 /** 219 * Union for debug flags. 220 */ 221 uint32_t u32All; 222 }; 223 224 /** 225 * DMUB feature capabilities. 226 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 227 */ 228 struct dmub_feature_caps { 229 /** 230 * Max PSR version supported by FW. 231 */ 232 uint8_t psr; 233 uint8_t reserved[7]; 234 }; 235 236 #if defined(__cplusplus) 237 } 238 #endif 239 240 //============================================================================== 241 //</DMUB_TYPES>================================================================= 242 //============================================================================== 243 //< DMUB_META>================================================================== 244 //============================================================================== 245 #pragma pack(push, 1) 246 247 /* Magic value for identifying dmub_fw_meta_info */ 248 #define DMUB_FW_META_MAGIC 0x444D5542 249 250 /* Offset from the end of the file to the dmub_fw_meta_info */ 251 #define DMUB_FW_META_OFFSET 0x24 252 253 /** 254 * struct dmub_fw_meta_info - metadata associated with fw binary 255 * 256 * NOTE: This should be considered a stable API. Fields should 257 * not be repurposed or reordered. New fields should be 258 * added instead to extend the structure. 259 * 260 * @magic_value: magic value identifying DMUB firmware meta info 261 * @fw_region_size: size of the firmware state region 262 * @trace_buffer_size: size of the tracebuffer region 263 * @fw_version: the firmware version information 264 * @dal_fw: 1 if the firmware is DAL 265 */ 266 struct dmub_fw_meta_info { 267 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 268 uint32_t fw_region_size; /**< size of the firmware state region */ 269 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 270 uint32_t fw_version; /**< the firmware version information */ 271 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 272 uint8_t reserved[3]; /**< padding bits */ 273 }; 274 275 /** 276 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 277 */ 278 union dmub_fw_meta { 279 struct dmub_fw_meta_info info; /**< metadata info */ 280 uint8_t reserved[64]; /**< padding bits */ 281 }; 282 283 #pragma pack(pop) 284 285 //============================================================================== 286 //< DMUB Trace Buffer>================================================================ 287 //============================================================================== 288 /** 289 * dmub_trace_code_t - firmware trace code, 32-bits 290 */ 291 typedef uint32_t dmub_trace_code_t; 292 293 /** 294 * struct dmcub_trace_buf_entry - Firmware trace entry 295 */ 296 struct dmcub_trace_buf_entry { 297 dmub_trace_code_t trace_code; /**< trace code for the event */ 298 uint32_t tick_count; /**< the tick count at time of trace */ 299 uint32_t param0; /**< trace defined parameter 0 */ 300 uint32_t param1; /**< trace defined parameter 1 */ 301 }; 302 303 //============================================================================== 304 //< DMUB_STATUS>================================================================ 305 //============================================================================== 306 307 /** 308 * DMCUB scratch registers can be used to determine firmware status. 309 * Current scratch register usage is as follows: 310 * 311 * SCRATCH0: FW Boot Status register 312 * SCRATCH5: LVTMA Status Register 313 * SCRATCH15: FW Boot Options register 314 */ 315 316 /** 317 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 318 */ 319 union dmub_fw_boot_status { 320 struct { 321 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 322 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 323 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 324 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 325 } bits; /**< status bits */ 326 uint32_t all; /**< 32-bit access to status bits */ 327 }; 328 329 /** 330 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 331 */ 332 enum dmub_fw_boot_status_bit { 333 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 334 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 335 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 336 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 337 }; 338 339 /* Register bit definition for SCRATCH5 */ 340 union dmub_lvtma_status { 341 struct { 342 uint32_t psp_ok : 1; 343 uint32_t edp_on : 1; 344 uint32_t reserved : 30; 345 } bits; 346 uint32_t all; 347 }; 348 349 enum dmub_lvtma_status_bit { 350 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 351 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 352 }; 353 354 /** 355 * union dmub_fw_boot_options - Boot option definitions for SCRATCH15 356 */ 357 union dmub_fw_boot_options { 358 struct { 359 uint32_t pemu_env : 1; /**< 1 if PEMU */ 360 uint32_t fpga_env : 1; /**< 1 if FPGA */ 361 uint32_t optimized_init : 1; /**< 1 if optimized init */ 362 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 363 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 364 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 365 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 366 uint32_t reserved : 25; /**< reserved */ 367 } bits; /**< boot bits */ 368 uint32_t all; /**< 32-bit access to bits */ 369 }; 370 371 enum dmub_fw_boot_options_bit { 372 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 373 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 374 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 375 }; 376 377 //============================================================================== 378 //</DMUB_STATUS>================================================================ 379 //============================================================================== 380 //< DMUB_VBIOS>================================================================= 381 //============================================================================== 382 383 /* 384 * enum dmub_cmd_vbios_type - VBIOS commands. 385 * 386 * Command IDs should be treated as stable ABI. 387 * Do not reuse or modify IDs. 388 */ 389 enum dmub_cmd_vbios_type { 390 /** 391 * Configures the DIG encoder. 392 */ 393 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 394 /** 395 * Controls the PHY. 396 */ 397 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 398 /** 399 * Sets the pixel clock/symbol clock. 400 */ 401 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 402 /** 403 * Enables or disables power gating. 404 */ 405 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 406 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 407 }; 408 409 //============================================================================== 410 //</DMUB_VBIOS>================================================================= 411 //============================================================================== 412 //< DMUB_GPINT>================================================================= 413 //============================================================================== 414 415 /** 416 * The shifts and masks below may alternatively be used to format and read 417 * the command register bits. 418 */ 419 420 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 421 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 422 423 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 424 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 425 426 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 427 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 428 429 /** 430 * Command responses. 431 */ 432 433 /** 434 * Return response for DMUB_GPINT__STOP_FW command. 435 */ 436 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 437 438 /** 439 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 440 */ 441 union dmub_gpint_data_register { 442 struct { 443 uint32_t param : 16; /**< 16-bit parameter */ 444 uint32_t command_code : 12; /**< GPINT command */ 445 uint32_t status : 4; /**< Command status bit */ 446 } bits; /**< GPINT bit access */ 447 uint32_t all; /**< GPINT 32-bit access */ 448 }; 449 450 /* 451 * enum dmub_gpint_command - GPINT command to DMCUB FW 452 * 453 * Command IDs should be treated as stable ABI. 454 * Do not reuse or modify IDs. 455 */ 456 enum dmub_gpint_command { 457 /** 458 * Invalid command, ignored. 459 */ 460 DMUB_GPINT__INVALID_COMMAND = 0, 461 /** 462 * DESC: Queries the firmware version. 463 * RETURN: Firmware version. 464 */ 465 DMUB_GPINT__GET_FW_VERSION = 1, 466 /** 467 * DESC: Halts the firmware. 468 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 469 */ 470 DMUB_GPINT__STOP_FW = 2, 471 /** 472 * DESC: Get PSR state from FW. 473 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 474 */ 475 DMUB_GPINT__GET_PSR_STATE = 7, 476 /** 477 * DESC: Notifies DMCUB of the currently active streams. 478 * ARGS: Stream mask, 1 bit per active stream index. 479 */ 480 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 481 /** 482 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 483 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 484 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 485 * RETURN: PSR residency in milli-percent. 486 */ 487 DMUB_GPINT__PSR_RESIDENCY = 9, 488 }; 489 490 /** 491 * INBOX0 generic command definition 492 */ 493 union dmub_inbox0_cmd_common { 494 struct { 495 uint32_t command_code: 8; /**< INBOX0 command code */ 496 uint32_t param: 24; /**< 24-bit parameter */ 497 } bits; 498 uint32_t all; 499 }; 500 501 /** 502 * INBOX0 hw_lock command definition 503 */ 504 union dmub_inbox0_cmd_lock_hw { 505 struct { 506 uint32_t command_code: 8; 507 508 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 509 uint32_t hw_lock_client: 1; 510 511 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 512 uint32_t otg_inst: 3; 513 uint32_t opp_inst: 3; 514 uint32_t dig_inst: 3; 515 516 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 517 uint32_t lock_pipe: 1; 518 uint32_t lock_cursor: 1; 519 uint32_t lock_dig: 1; 520 uint32_t triple_buffer_lock: 1; 521 522 uint32_t lock: 1; /**< Lock */ 523 uint32_t should_release: 1; /**< Release */ 524 uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ 525 } bits; 526 uint32_t all; 527 }; 528 529 union dmub_inbox0_data_register { 530 union dmub_inbox0_cmd_common inbox0_cmd_common; 531 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 532 }; 533 534 enum dmub_inbox0_command { 535 /** 536 * DESC: Invalid command, ignored. 537 */ 538 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 539 /** 540 * DESC: Notification to acquire/release HW lock 541 * ARGS: 542 */ 543 DMUB_INBOX0_CMD__HW_LOCK = 1, 544 }; 545 //============================================================================== 546 //</DMUB_GPINT>================================================================= 547 //============================================================================== 548 //< DMUB_CMD>=================================================================== 549 //============================================================================== 550 551 /** 552 * Size in bytes of each DMUB command. 553 */ 554 #define DMUB_RB_CMD_SIZE 64 555 556 /** 557 * Maximum number of items in the DMUB ringbuffer. 558 */ 559 #define DMUB_RB_MAX_ENTRY 128 560 561 /** 562 * Ringbuffer size in bytes. 563 */ 564 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 565 566 /** 567 * REG_SET mask for reg offload. 568 */ 569 #define REG_SET_MASK 0xFFFF 570 571 /* 572 * enum dmub_cmd_type - DMUB inbox command. 573 * 574 * Command IDs should be treated as stable ABI. 575 * Do not reuse or modify IDs. 576 */ 577 enum dmub_cmd_type { 578 /** 579 * Invalid command. 580 */ 581 DMUB_CMD__NULL = 0, 582 /** 583 * Read modify write register sequence offload. 584 */ 585 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 586 /** 587 * Field update register sequence offload. 588 */ 589 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 590 /** 591 * Burst write sequence offload. 592 */ 593 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 594 /** 595 * Reg wait sequence offload. 596 */ 597 DMUB_CMD__REG_REG_WAIT = 4, 598 /** 599 * Workaround to avoid HUBP underflow during NV12 playback. 600 */ 601 DMUB_CMD__PLAT_54186_WA = 5, 602 /** 603 * Command type used to query FW feature caps. 604 */ 605 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 606 /** 607 * Command type used for all PSR commands. 608 */ 609 DMUB_CMD__PSR = 64, 610 /** 611 * Command type used for all MALL commands. 612 */ 613 DMUB_CMD__MALL = 65, 614 /** 615 * Command type used for all ABM commands. 616 */ 617 DMUB_CMD__ABM = 66, 618 /** 619 * Command type used for HW locking in FW. 620 */ 621 DMUB_CMD__HW_LOCK = 69, 622 /** 623 * Command type used to access DP AUX. 624 */ 625 DMUB_CMD__DP_AUX_ACCESS = 70, 626 /** 627 * Command type used for OUTBOX1 notification enable 628 */ 629 DMUB_CMD__OUTBOX1_ENABLE = 71, 630 /** 631 * Command type used for all idle optimization commands. 632 */ 633 DMUB_CMD__IDLE_OPT = 72, 634 /** 635 * Command type used for all clock manager commands. 636 */ 637 DMUB_CMD__CLK_MGR = 73, 638 /** 639 * Command type used for all panel control commands. 640 */ 641 DMUB_CMD__PANEL_CNTL = 74, 642 /** 643 * Command type used for EDID CEA parsing 644 */ 645 DMUB_CMD__EDID_CEA = 79, 646 /** 647 * Command type used for all VBIOS interface commands. 648 */ 649 DMUB_CMD__VBIOS = 128, 650 }; 651 652 /** 653 * enum dmub_out_cmd_type - DMUB outbox commands. 654 */ 655 enum dmub_out_cmd_type { 656 /** 657 * Invalid outbox command, ignored. 658 */ 659 DMUB_OUT_CMD__NULL = 0, 660 /** 661 * Command type used for DP AUX Reply data notification 662 */ 663 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 664 }; 665 666 #pragma pack(push, 1) 667 668 /** 669 * struct dmub_cmd_header - Common command header fields. 670 */ 671 struct dmub_cmd_header { 672 unsigned int type : 8; /**< command type */ 673 unsigned int sub_type : 8; /**< command sub type */ 674 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 675 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 676 unsigned int reserved0 : 6; /**< reserved bits */ 677 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 678 unsigned int reserved1 : 2; /**< reserved bits */ 679 }; 680 681 /* 682 * struct dmub_cmd_read_modify_write_sequence - Read modify write 683 * 684 * 60 payload bytes can hold up to 5 sets of read modify writes, 685 * each take 3 dwords. 686 * 687 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 688 * 689 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 690 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 691 */ 692 struct dmub_cmd_read_modify_write_sequence { 693 uint32_t addr; /**< register address */ 694 uint32_t modify_mask; /**< modify mask */ 695 uint32_t modify_value; /**< modify value */ 696 }; 697 698 /** 699 * Maximum number of ops in read modify write sequence. 700 */ 701 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 702 703 /** 704 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 705 */ 706 struct dmub_rb_cmd_read_modify_write { 707 struct dmub_cmd_header header; /**< command header */ 708 /** 709 * Read modify write sequence. 710 */ 711 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 712 }; 713 714 /* 715 * Update a register with specified masks and values sequeunce 716 * 717 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 718 * 719 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 720 * 721 * 722 * USE CASE: 723 * 1. auto-increment register where additional read would update pointer and produce wrong result 724 * 2. toggle a bit without read in the middle 725 */ 726 727 struct dmub_cmd_reg_field_update_sequence { 728 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 729 uint32_t modify_value; /**< value to update with */ 730 }; 731 732 /** 733 * Maximum number of ops in field update sequence. 734 */ 735 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 736 737 /** 738 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 739 */ 740 struct dmub_rb_cmd_reg_field_update_sequence { 741 struct dmub_cmd_header header; /**< command header */ 742 uint32_t addr; /**< register address */ 743 /** 744 * Field update sequence. 745 */ 746 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 747 }; 748 749 750 /** 751 * Maximum number of burst write values. 752 */ 753 #define DMUB_BURST_WRITE_VALUES__MAX 14 754 755 /* 756 * struct dmub_rb_cmd_burst_write - Burst write 757 * 758 * support use case such as writing out LUTs. 759 * 760 * 60 payload bytes can hold up to 14 values to write to given address 761 * 762 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 763 */ 764 struct dmub_rb_cmd_burst_write { 765 struct dmub_cmd_header header; /**< command header */ 766 uint32_t addr; /**< register start address */ 767 /** 768 * Burst write register values. 769 */ 770 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 771 }; 772 773 /** 774 * struct dmub_rb_cmd_common - Common command header 775 */ 776 struct dmub_rb_cmd_common { 777 struct dmub_cmd_header header; /**< command header */ 778 /** 779 * Padding to RB_CMD_SIZE 780 */ 781 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 782 }; 783 784 /** 785 * struct dmub_cmd_reg_wait_data - Register wait data 786 */ 787 struct dmub_cmd_reg_wait_data { 788 uint32_t addr; /**< Register address */ 789 uint32_t mask; /**< Mask for register bits */ 790 uint32_t condition_field_value; /**< Value to wait for */ 791 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 792 }; 793 794 /** 795 * struct dmub_rb_cmd_reg_wait - Register wait command 796 */ 797 struct dmub_rb_cmd_reg_wait { 798 struct dmub_cmd_header header; /**< Command header */ 799 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 800 }; 801 802 /** 803 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 804 * 805 * Reprograms surface parameters to avoid underflow. 806 */ 807 struct dmub_cmd_PLAT_54186_wa { 808 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 809 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 810 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 811 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 812 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 813 struct { 814 uint8_t hubp_inst : 4; /**< HUBP instance */ 815 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 816 uint8_t immediate :1; /**< Immediate flip */ 817 uint8_t vmid : 4; /**< VMID */ 818 uint8_t grph_stereo : 1; /**< 1 if stereo */ 819 uint32_t reserved : 21; /**< Reserved */ 820 } flip_params; /**< Pageflip parameters */ 821 uint32_t reserved[9]; /**< Reserved bits */ 822 }; 823 824 /** 825 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 826 */ 827 struct dmub_rb_cmd_PLAT_54186_wa { 828 struct dmub_cmd_header header; /**< Command header */ 829 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 830 }; 831 832 /** 833 * struct dmub_rb_cmd_mall - MALL command data. 834 */ 835 struct dmub_rb_cmd_mall { 836 struct dmub_cmd_header header; /**< Common command header */ 837 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 838 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 839 uint32_t tmr_delay; /**< Timer delay */ 840 uint32_t tmr_scale; /**< Timer scale */ 841 uint16_t cursor_width; /**< Cursor width in pixels */ 842 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 843 uint16_t cursor_height; /**< Cursor height in pixels */ 844 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 845 uint8_t debug_bits; /**< Debug bits */ 846 847 uint8_t reserved1; /**< Reserved bits */ 848 uint8_t reserved2; /**< Reserved bits */ 849 }; 850 851 /** 852 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 853 */ 854 enum dmub_cmd_idle_opt_type { 855 /** 856 * DCN hardware restore. 857 */ 858 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 859 860 /** 861 * DCN hardware save. 862 */ 863 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 864 }; 865 866 /** 867 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 868 */ 869 struct dmub_rb_cmd_idle_opt_dcn_restore { 870 struct dmub_cmd_header header; /**< header */ 871 }; 872 873 /** 874 * struct dmub_clocks - Clock update notification. 875 */ 876 struct dmub_clocks { 877 uint32_t dispclk_khz; /**< dispclk kHz */ 878 uint32_t dppclk_khz; /**< dppclk kHz */ 879 uint32_t dcfclk_khz; /**< dcfclk kHz */ 880 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 881 }; 882 883 /** 884 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 885 */ 886 enum dmub_cmd_clk_mgr_type { 887 /** 888 * Notify DMCUB of clock update. 889 */ 890 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 891 }; 892 893 /** 894 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 895 */ 896 struct dmub_rb_cmd_clk_mgr_notify_clocks { 897 struct dmub_cmd_header header; /**< header */ 898 struct dmub_clocks clocks; /**< clock data */ 899 }; 900 901 /** 902 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 903 */ 904 struct dmub_cmd_digx_encoder_control_data { 905 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 906 }; 907 908 /** 909 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 910 */ 911 struct dmub_rb_cmd_digx_encoder_control { 912 struct dmub_cmd_header header; /**< header */ 913 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 914 }; 915 916 /** 917 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 918 */ 919 struct dmub_cmd_set_pixel_clock_data { 920 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 921 }; 922 923 /** 924 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 925 */ 926 struct dmub_rb_cmd_set_pixel_clock { 927 struct dmub_cmd_header header; /**< header */ 928 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 929 }; 930 931 /** 932 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 933 */ 934 struct dmub_cmd_enable_disp_power_gating_data { 935 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 936 }; 937 938 /** 939 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 940 */ 941 struct dmub_rb_cmd_enable_disp_power_gating { 942 struct dmub_cmd_header header; /**< header */ 943 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 944 }; 945 946 /** 947 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 948 */ 949 struct dmub_dig_transmitter_control_data_v1_7 { 950 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 951 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 952 union { 953 uint8_t digmode; /**< enum atom_encode_mode_def */ 954 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 955 } mode_laneset; 956 uint8_t lanenum; /**< Number of lanes */ 957 union { 958 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 959 } symclk_units; 960 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 961 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 962 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 963 uint8_t reserved0; /**< For future use */ 964 uint8_t reserved1; /**< For future use */ 965 uint8_t reserved2[3]; /**< For future use */ 966 uint32_t reserved3[11]; /**< For future use */ 967 }; 968 969 /** 970 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 971 */ 972 union dmub_cmd_dig1_transmitter_control_data { 973 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 974 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 975 }; 976 977 /** 978 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 979 */ 980 struct dmub_rb_cmd_dig1_transmitter_control { 981 struct dmub_cmd_header header; /**< header */ 982 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 983 }; 984 985 /** 986 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 987 */ 988 struct dmub_rb_cmd_dpphy_init { 989 struct dmub_cmd_header header; /**< header */ 990 uint8_t reserved[60]; /**< reserved bits */ 991 }; 992 993 /** 994 * enum dp_aux_request_action - DP AUX request command listing. 995 * 996 * 4 AUX request command bits are shifted to high nibble. 997 */ 998 enum dp_aux_request_action { 999 /** I2C-over-AUX write request */ 1000 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1001 /** I2C-over-AUX read request */ 1002 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1003 /** I2C-over-AUX write status request */ 1004 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1005 /** I2C-over-AUX write request with MOT=1 */ 1006 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1007 /** I2C-over-AUX read request with MOT=1 */ 1008 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1009 /** I2C-over-AUX write status request with MOT=1 */ 1010 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1011 /** Native AUX write request */ 1012 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1013 /** Native AUX read request */ 1014 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1015 }; 1016 1017 /** 1018 * enum aux_return_code_type - DP AUX process return code listing. 1019 */ 1020 enum aux_return_code_type { 1021 /** AUX process succeeded */ 1022 AUX_RET_SUCCESS = 0, 1023 /** AUX process failed with unknown reason */ 1024 AUX_RET_ERROR_UNKNOWN, 1025 /** AUX process completed with invalid reply */ 1026 AUX_RET_ERROR_INVALID_REPLY, 1027 /** AUX process timed out */ 1028 AUX_RET_ERROR_TIMEOUT, 1029 /** HPD was low during AUX process */ 1030 AUX_RET_ERROR_HPD_DISCON, 1031 /** Failed to acquire AUX engine */ 1032 AUX_RET_ERROR_ENGINE_ACQUIRE, 1033 /** AUX request not supported */ 1034 AUX_RET_ERROR_INVALID_OPERATION, 1035 /** AUX process not available */ 1036 AUX_RET_ERROR_PROTOCOL_ERROR, 1037 }; 1038 1039 /** 1040 * enum aux_channel_type - DP AUX channel type listing. 1041 */ 1042 enum aux_channel_type { 1043 /** AUX thru Legacy DP AUX */ 1044 AUX_CHANNEL_LEGACY_DDC, 1045 /** AUX thru DPIA DP tunneling */ 1046 AUX_CHANNEL_DPIA 1047 }; 1048 1049 /** 1050 * struct aux_transaction_parameters - DP AUX request transaction data 1051 */ 1052 struct aux_transaction_parameters { 1053 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1054 uint8_t action; /**< enum dp_aux_request_action */ 1055 uint8_t length; /**< DP AUX request data length */ 1056 uint8_t reserved; /**< For future use */ 1057 uint32_t address; /**< DP AUX address */ 1058 uint8_t data[16]; /**< DP AUX write data */ 1059 }; 1060 1061 /** 1062 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1063 */ 1064 struct dmub_cmd_dp_aux_control_data { 1065 uint8_t instance; /**< AUX instance or DPIA instance */ 1066 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1067 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1068 uint8_t reserved0; /**< For future use */ 1069 uint16_t timeout; /**< timeout time in us */ 1070 uint16_t reserved1; /**< For future use */ 1071 enum aux_channel_type type; /**< enum aux_channel_type */ 1072 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1073 }; 1074 1075 /** 1076 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1077 */ 1078 struct dmub_rb_cmd_dp_aux_access { 1079 /** 1080 * Command header. 1081 */ 1082 struct dmub_cmd_header header; 1083 /** 1084 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1085 */ 1086 struct dmub_cmd_dp_aux_control_data aux_control; 1087 }; 1088 1089 /** 1090 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1091 */ 1092 struct dmub_rb_cmd_outbox1_enable { 1093 /** 1094 * Command header. 1095 */ 1096 struct dmub_cmd_header header; 1097 /** 1098 * enable: 0x0 -> disable outbox1 notification (default value) 1099 * 0x1 -> enable outbox1 notification 1100 */ 1101 uint32_t enable; 1102 }; 1103 1104 /* DP AUX Reply command - OutBox Cmd */ 1105 /** 1106 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1107 */ 1108 struct aux_reply_data { 1109 /** 1110 * Aux cmd 1111 */ 1112 uint8_t command; 1113 /** 1114 * Aux reply data length (max: 16 bytes) 1115 */ 1116 uint8_t length; 1117 /** 1118 * Alignment only 1119 */ 1120 uint8_t pad[2]; 1121 /** 1122 * Aux reply data 1123 */ 1124 uint8_t data[16]; 1125 }; 1126 1127 /** 1128 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1129 */ 1130 struct aux_reply_control_data { 1131 /** 1132 * Reserved for future use 1133 */ 1134 uint32_t handle; 1135 /** 1136 * Aux Instance 1137 */ 1138 uint8_t instance; 1139 /** 1140 * Aux transaction result: definition in enum aux_return_code_type 1141 */ 1142 uint8_t result; 1143 /** 1144 * Alignment only 1145 */ 1146 uint16_t pad; 1147 }; 1148 1149 /** 1150 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1151 */ 1152 struct dmub_rb_cmd_dp_aux_reply { 1153 /** 1154 * Command header. 1155 */ 1156 struct dmub_cmd_header header; 1157 /** 1158 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1159 */ 1160 struct aux_reply_control_data control; 1161 /** 1162 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1163 */ 1164 struct aux_reply_data reply_data; 1165 }; 1166 1167 /* DP HPD Notify command - OutBox Cmd */ 1168 /** 1169 * DP HPD Type 1170 */ 1171 enum dp_hpd_type { 1172 /** 1173 * Normal DP HPD 1174 */ 1175 DP_HPD = 0, 1176 /** 1177 * DP HPD short pulse 1178 */ 1179 DP_IRQ 1180 }; 1181 1182 /** 1183 * DP HPD Status 1184 */ 1185 enum dp_hpd_status { 1186 /** 1187 * DP_HPD status low 1188 */ 1189 DP_HPD_UNPLUG = 0, 1190 /** 1191 * DP_HPD status high 1192 */ 1193 DP_HPD_PLUG 1194 }; 1195 1196 /** 1197 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1198 */ 1199 struct dp_hpd_data { 1200 /** 1201 * DP HPD instance 1202 */ 1203 uint8_t instance; 1204 /** 1205 * HPD type 1206 */ 1207 uint8_t hpd_type; 1208 /** 1209 * HPD status: only for type: DP_HPD to indicate status 1210 */ 1211 uint8_t hpd_status; 1212 /** 1213 * Alignment only 1214 */ 1215 uint8_t pad; 1216 }; 1217 1218 /** 1219 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1220 */ 1221 struct dmub_rb_cmd_dp_hpd_notify { 1222 /** 1223 * Command header. 1224 */ 1225 struct dmub_cmd_header header; 1226 /** 1227 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1228 */ 1229 struct dp_hpd_data hpd_data; 1230 }; 1231 1232 /* 1233 * Command IDs should be treated as stable ABI. 1234 * Do not reuse or modify IDs. 1235 */ 1236 1237 /** 1238 * PSR command sub-types. 1239 */ 1240 enum dmub_cmd_psr_type { 1241 /** 1242 * Set PSR version support. 1243 */ 1244 DMUB_CMD__PSR_SET_VERSION = 0, 1245 /** 1246 * Copy driver-calculated parameters to PSR state. 1247 */ 1248 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1249 /** 1250 * Enable PSR. 1251 */ 1252 DMUB_CMD__PSR_ENABLE = 2, 1253 1254 /** 1255 * Disable PSR. 1256 */ 1257 DMUB_CMD__PSR_DISABLE = 3, 1258 1259 /** 1260 * Set PSR level. 1261 * PSR level is a 16-bit value dicated by driver that 1262 * will enable/disable different functionality. 1263 */ 1264 DMUB_CMD__PSR_SET_LEVEL = 4, 1265 1266 /** 1267 * Forces PSR enabled until an explicit PSR disable call. 1268 */ 1269 DMUB_CMD__PSR_FORCE_STATIC = 5, 1270 }; 1271 1272 /** 1273 * PSR versions. 1274 */ 1275 enum psr_version { 1276 /** 1277 * PSR version 1. 1278 */ 1279 PSR_VERSION_1 = 0, 1280 /** 1281 * PSR not supported. 1282 */ 1283 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1284 }; 1285 1286 /** 1287 * enum dmub_cmd_mall_type - MALL commands 1288 */ 1289 enum dmub_cmd_mall_type { 1290 /** 1291 * Allows display refresh from MALL. 1292 */ 1293 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1294 /** 1295 * Disallows display refresh from MALL. 1296 */ 1297 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1298 /** 1299 * Cursor copy for MALL. 1300 */ 1301 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1302 /** 1303 * Controls DF requests. 1304 */ 1305 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1306 }; 1307 1308 1309 /** 1310 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1311 */ 1312 struct dmub_cmd_psr_copy_settings_data { 1313 /** 1314 * Flags that can be set by driver to change some PSR behaviour. 1315 */ 1316 union dmub_psr_debug_flags debug; 1317 /** 1318 * 16-bit value dicated by driver that will enable/disable different functionality. 1319 */ 1320 uint16_t psr_level; 1321 /** 1322 * DPP HW instance. 1323 */ 1324 uint8_t dpp_inst; 1325 /** 1326 * MPCC HW instance. 1327 * Not used in dmub fw, 1328 * dmub fw will get active opp by reading odm registers. 1329 */ 1330 uint8_t mpcc_inst; 1331 /** 1332 * OPP HW instance. 1333 * Not used in dmub fw, 1334 * dmub fw will get active opp by reading odm registers. 1335 */ 1336 uint8_t opp_inst; 1337 /** 1338 * OTG HW instance. 1339 */ 1340 uint8_t otg_inst; 1341 /** 1342 * DIG FE HW instance. 1343 */ 1344 uint8_t digfe_inst; 1345 /** 1346 * DIG BE HW instance. 1347 */ 1348 uint8_t digbe_inst; 1349 /** 1350 * DP PHY HW instance. 1351 */ 1352 uint8_t dpphy_inst; 1353 /** 1354 * AUX HW instance. 1355 */ 1356 uint8_t aux_inst; 1357 /** 1358 * Determines if SMU optimzations are enabled/disabled. 1359 */ 1360 uint8_t smu_optimizations_en; 1361 /** 1362 * Unused. 1363 * TODO: Remove. 1364 */ 1365 uint8_t frame_delay; 1366 /** 1367 * If RFB setup time is greater than the total VBLANK time, 1368 * it is not possible for the sink to capture the video frame 1369 * in the same frame the SDP is sent. In this case, 1370 * the frame capture indication bit should be set and an extra 1371 * static frame should be transmitted to the sink. 1372 */ 1373 uint8_t frame_cap_ind; 1374 /** 1375 * Explicit padding to 4 byte boundary. 1376 */ 1377 uint8_t pad[2]; 1378 /** 1379 * Multi-display optimizations are implemented on certain ASICs. 1380 */ 1381 uint8_t multi_disp_optimizations_en; 1382 /** 1383 * The last possible line SDP may be transmitted without violating 1384 * the RFB setup time or entering the active video frame. 1385 */ 1386 uint16_t init_sdp_deadline; 1387 /** 1388 * Explicit padding to 4 byte boundary. 1389 */ 1390 uint16_t pad2; 1391 /** 1392 * Length of each horizontal line in us. 1393 */ 1394 uint32_t line_time_in_us; 1395 /** 1396 * FEC enable status in driver 1397 */ 1398 uint8_t fec_enable_status; 1399 /** 1400 * FEC re-enable delay when PSR exit. 1401 * unit is 100us, range form 0~255(0xFF). 1402 */ 1403 uint8_t fec_enable_delay_in100us; 1404 /** 1405 * PSR control version. 1406 */ 1407 uint8_t cmd_version; 1408 /** 1409 * Panel Instance. 1410 * Panel isntance to identify which psr_state to use 1411 * Currently the support is only for 0 or 1 1412 */ 1413 uint8_t panel_inst; 1414 }; 1415 1416 /** 1417 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1418 */ 1419 struct dmub_rb_cmd_psr_copy_settings { 1420 /** 1421 * Command header. 1422 */ 1423 struct dmub_cmd_header header; 1424 /** 1425 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1426 */ 1427 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1428 }; 1429 1430 /** 1431 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1432 */ 1433 struct dmub_cmd_psr_set_level_data { 1434 /** 1435 * 16-bit value dicated by driver that will enable/disable different functionality. 1436 */ 1437 uint16_t psr_level; 1438 /** 1439 * PSR control version. 1440 */ 1441 uint8_t cmd_version; 1442 /** 1443 * Panel Instance. 1444 * Panel isntance to identify which psr_state to use 1445 * Currently the support is only for 0 or 1 1446 */ 1447 uint8_t panel_inst; 1448 }; 1449 1450 /** 1451 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1452 */ 1453 struct dmub_rb_cmd_psr_set_level { 1454 /** 1455 * Command header. 1456 */ 1457 struct dmub_cmd_header header; 1458 /** 1459 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1460 */ 1461 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1462 }; 1463 1464 struct dmub_rb_cmd_psr_enable_data { 1465 /** 1466 * PSR control version. 1467 */ 1468 uint8_t cmd_version; 1469 /** 1470 * Panel Instance. 1471 * Panel isntance to identify which psr_state to use 1472 * Currently the support is only for 0 or 1 1473 */ 1474 uint8_t panel_inst; 1475 /** 1476 * Explicit padding to 4 byte boundary. 1477 */ 1478 uint8_t pad[2]; 1479 }; 1480 1481 /** 1482 * Definition of a DMUB_CMD__PSR_ENABLE command. 1483 * PSR enable/disable is controlled using the sub_type. 1484 */ 1485 struct dmub_rb_cmd_psr_enable { 1486 /** 1487 * Command header. 1488 */ 1489 struct dmub_cmd_header header; 1490 1491 struct dmub_rb_cmd_psr_enable_data data; 1492 }; 1493 1494 /** 1495 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1496 */ 1497 struct dmub_cmd_psr_set_version_data { 1498 /** 1499 * PSR version that FW should implement. 1500 */ 1501 enum psr_version version; 1502 /** 1503 * PSR control version. 1504 */ 1505 uint8_t cmd_version; 1506 /** 1507 * Panel Instance. 1508 * Panel isntance to identify which psr_state to use 1509 * Currently the support is only for 0 or 1 1510 */ 1511 uint8_t panel_inst; 1512 /** 1513 * Explicit padding to 4 byte boundary. 1514 */ 1515 uint8_t pad[2]; 1516 }; 1517 1518 /** 1519 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1520 */ 1521 struct dmub_rb_cmd_psr_set_version { 1522 /** 1523 * Command header. 1524 */ 1525 struct dmub_cmd_header header; 1526 /** 1527 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1528 */ 1529 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1530 }; 1531 1532 struct dmub_cmd_psr_force_static_data { 1533 /** 1534 * PSR control version. 1535 */ 1536 uint8_t cmd_version; 1537 /** 1538 * Panel Instance. 1539 * Panel isntance to identify which psr_state to use 1540 * Currently the support is only for 0 or 1 1541 */ 1542 uint8_t panel_inst; 1543 /** 1544 * Explicit padding to 4 byte boundary. 1545 */ 1546 uint8_t pad[2]; 1547 }; 1548 1549 /** 1550 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1551 */ 1552 struct dmub_rb_cmd_psr_force_static { 1553 /** 1554 * Command header. 1555 */ 1556 struct dmub_cmd_header header; 1557 /** 1558 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1559 */ 1560 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1561 }; 1562 1563 /** 1564 * Set of HW components that can be locked. 1565 * 1566 * Note: If updating with more HW components, fields 1567 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1568 */ 1569 union dmub_hw_lock_flags { 1570 /** 1571 * Set of HW components that can be locked. 1572 */ 1573 struct { 1574 /** 1575 * Lock/unlock OTG master update lock. 1576 */ 1577 uint8_t lock_pipe : 1; 1578 /** 1579 * Lock/unlock cursor. 1580 */ 1581 uint8_t lock_cursor : 1; 1582 /** 1583 * Lock/unlock global update lock. 1584 */ 1585 uint8_t lock_dig : 1; 1586 /** 1587 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1588 */ 1589 uint8_t triple_buffer_lock : 1; 1590 } bits; 1591 1592 /** 1593 * Union for HW Lock flags. 1594 */ 1595 uint8_t u8All; 1596 }; 1597 1598 /** 1599 * Instances of HW to be locked. 1600 * 1601 * Note: If updating with more HW components, fields 1602 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1603 */ 1604 struct dmub_hw_lock_inst_flags { 1605 /** 1606 * OTG HW instance for OTG master update lock. 1607 */ 1608 uint8_t otg_inst; 1609 /** 1610 * OPP instance for cursor lock. 1611 */ 1612 uint8_t opp_inst; 1613 /** 1614 * OTG HW instance for global update lock. 1615 * TODO: Remove, and re-use otg_inst. 1616 */ 1617 uint8_t dig_inst; 1618 /** 1619 * Explicit pad to 4 byte boundary. 1620 */ 1621 uint8_t pad; 1622 }; 1623 1624 /** 1625 * Clients that can acquire the HW Lock Manager. 1626 * 1627 * Note: If updating with more clients, fields in 1628 * dmub_inbox0_cmd_lock_hw must be updated to match. 1629 */ 1630 enum hw_lock_client { 1631 /** 1632 * Driver is the client of HW Lock Manager. 1633 */ 1634 HW_LOCK_CLIENT_DRIVER = 0, 1635 /** 1636 * Invalid client. 1637 */ 1638 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1639 }; 1640 1641 /** 1642 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1643 */ 1644 struct dmub_cmd_lock_hw_data { 1645 /** 1646 * Specifies the client accessing HW Lock Manager. 1647 */ 1648 enum hw_lock_client client; 1649 /** 1650 * HW instances to be locked. 1651 */ 1652 struct dmub_hw_lock_inst_flags inst_flags; 1653 /** 1654 * Which components to be locked. 1655 */ 1656 union dmub_hw_lock_flags hw_locks; 1657 /** 1658 * Specifies lock/unlock. 1659 */ 1660 uint8_t lock; 1661 /** 1662 * HW can be unlocked separately from releasing the HW Lock Mgr. 1663 * This flag is set if the client wishes to release the object. 1664 */ 1665 uint8_t should_release; 1666 /** 1667 * Explicit padding to 4 byte boundary. 1668 */ 1669 uint8_t pad; 1670 }; 1671 1672 /** 1673 * Definition of a DMUB_CMD__HW_LOCK command. 1674 * Command is used by driver and FW. 1675 */ 1676 struct dmub_rb_cmd_lock_hw { 1677 /** 1678 * Command header. 1679 */ 1680 struct dmub_cmd_header header; 1681 /** 1682 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1683 */ 1684 struct dmub_cmd_lock_hw_data lock_hw_data; 1685 }; 1686 1687 /** 1688 * ABM command sub-types. 1689 */ 1690 enum dmub_cmd_abm_type { 1691 /** 1692 * Initialize parameters for ABM algorithm. 1693 * Data is passed through an indirect buffer. 1694 */ 1695 DMUB_CMD__ABM_INIT_CONFIG = 0, 1696 /** 1697 * Set OTG and panel HW instance. 1698 */ 1699 DMUB_CMD__ABM_SET_PIPE = 1, 1700 /** 1701 * Set user requested backklight level. 1702 */ 1703 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1704 /** 1705 * Set ABM operating/aggression level. 1706 */ 1707 DMUB_CMD__ABM_SET_LEVEL = 3, 1708 /** 1709 * Set ambient light level. 1710 */ 1711 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1712 /** 1713 * Enable/disable fractional duty cycle for backlight PWM. 1714 */ 1715 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1716 }; 1717 1718 /** 1719 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1720 * Requirements: 1721 * - Padded explicitly to 32-bit boundary. 1722 * - Must ensure this structure matches the one on driver-side, 1723 * otherwise it won't be aligned. 1724 */ 1725 struct abm_config_table { 1726 /** 1727 * Gamma curve thresholds, used for crgb conversion. 1728 */ 1729 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1730 /** 1731 * Gamma curve offsets, used for crgb conversion. 1732 */ 1733 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1734 /** 1735 * Gamma curve slopes, used for crgb conversion. 1736 */ 1737 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1738 /** 1739 * Custom backlight curve thresholds. 1740 */ 1741 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 1742 /** 1743 * Custom backlight curve offsets. 1744 */ 1745 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 1746 /** 1747 * Ambient light thresholds. 1748 */ 1749 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 1750 /** 1751 * Minimum programmable backlight. 1752 */ 1753 uint16_t min_abm_backlight; // 122B 1754 /** 1755 * Minimum reduction values. 1756 */ 1757 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 1758 /** 1759 * Maximum reduction values. 1760 */ 1761 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 1762 /** 1763 * Bright positive gain. 1764 */ 1765 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 1766 /** 1767 * Dark negative gain. 1768 */ 1769 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 1770 /** 1771 * Hybrid factor. 1772 */ 1773 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 1774 /** 1775 * Contrast factor. 1776 */ 1777 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 1778 /** 1779 * Deviation gain. 1780 */ 1781 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 1782 /** 1783 * Minimum knee. 1784 */ 1785 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 1786 /** 1787 * Maximum knee. 1788 */ 1789 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 1790 /** 1791 * Unused. 1792 */ 1793 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 1794 /** 1795 * Explicit padding to 4 byte boundary. 1796 */ 1797 uint8_t pad3[3]; // 229B 1798 /** 1799 * Backlight ramp reduction. 1800 */ 1801 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 1802 /** 1803 * Backlight ramp start. 1804 */ 1805 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 1806 }; 1807 1808 /** 1809 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1810 */ 1811 struct dmub_cmd_abm_set_pipe_data { 1812 /** 1813 * OTG HW instance. 1814 */ 1815 uint8_t otg_inst; 1816 1817 /** 1818 * Panel Control HW instance. 1819 */ 1820 uint8_t panel_inst; 1821 1822 /** 1823 * Controls how ABM will interpret a set pipe or set level command. 1824 */ 1825 uint8_t set_pipe_option; 1826 1827 /** 1828 * Unused. 1829 * TODO: Remove. 1830 */ 1831 uint8_t ramping_boundary; 1832 }; 1833 1834 /** 1835 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1836 */ 1837 struct dmub_rb_cmd_abm_set_pipe { 1838 /** 1839 * Command header. 1840 */ 1841 struct dmub_cmd_header header; 1842 1843 /** 1844 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1845 */ 1846 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 1847 }; 1848 1849 /** 1850 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1851 */ 1852 struct dmub_cmd_abm_set_backlight_data { 1853 /** 1854 * Number of frames to ramp to backlight user level. 1855 */ 1856 uint32_t frame_ramp; 1857 1858 /** 1859 * Requested backlight level from user. 1860 */ 1861 uint32_t backlight_user_level; 1862 1863 /** 1864 * ABM control version. 1865 */ 1866 uint8_t version; 1867 1868 /** 1869 * Panel Control HW instance mask. 1870 * Bit 0 is Panel Control HW instance 0. 1871 * Bit 1 is Panel Control HW instance 1. 1872 */ 1873 uint8_t panel_mask; 1874 1875 /** 1876 * Explicit padding to 4 byte boundary. 1877 */ 1878 uint8_t pad[2]; 1879 }; 1880 1881 /** 1882 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 1883 */ 1884 struct dmub_rb_cmd_abm_set_backlight { 1885 /** 1886 * Command header. 1887 */ 1888 struct dmub_cmd_header header; 1889 1890 /** 1891 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1892 */ 1893 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 1894 }; 1895 1896 /** 1897 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1898 */ 1899 struct dmub_cmd_abm_set_level_data { 1900 /** 1901 * Set current ABM operating/aggression level. 1902 */ 1903 uint32_t level; 1904 1905 /** 1906 * ABM control version. 1907 */ 1908 uint8_t version; 1909 1910 /** 1911 * Panel Control HW instance mask. 1912 * Bit 0 is Panel Control HW instance 0. 1913 * Bit 1 is Panel Control HW instance 1. 1914 */ 1915 uint8_t panel_mask; 1916 1917 /** 1918 * Explicit padding to 4 byte boundary. 1919 */ 1920 uint8_t pad[2]; 1921 }; 1922 1923 /** 1924 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 1925 */ 1926 struct dmub_rb_cmd_abm_set_level { 1927 /** 1928 * Command header. 1929 */ 1930 struct dmub_cmd_header header; 1931 1932 /** 1933 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1934 */ 1935 struct dmub_cmd_abm_set_level_data abm_set_level_data; 1936 }; 1937 1938 /** 1939 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1940 */ 1941 struct dmub_cmd_abm_set_ambient_level_data { 1942 /** 1943 * Ambient light sensor reading from OS. 1944 */ 1945 uint32_t ambient_lux; 1946 1947 /** 1948 * ABM control version. 1949 */ 1950 uint8_t version; 1951 1952 /** 1953 * Panel Control HW instance mask. 1954 * Bit 0 is Panel Control HW instance 0. 1955 * Bit 1 is Panel Control HW instance 1. 1956 */ 1957 uint8_t panel_mask; 1958 1959 /** 1960 * Explicit padding to 4 byte boundary. 1961 */ 1962 uint8_t pad[2]; 1963 }; 1964 1965 /** 1966 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1967 */ 1968 struct dmub_rb_cmd_abm_set_ambient_level { 1969 /** 1970 * Command header. 1971 */ 1972 struct dmub_cmd_header header; 1973 1974 /** 1975 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1976 */ 1977 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 1978 }; 1979 1980 /** 1981 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1982 */ 1983 struct dmub_cmd_abm_set_pwm_frac_data { 1984 /** 1985 * Enable/disable fractional duty cycle for backlight PWM. 1986 * TODO: Convert to uint8_t. 1987 */ 1988 uint32_t fractional_pwm; 1989 1990 /** 1991 * ABM control version. 1992 */ 1993 uint8_t version; 1994 1995 /** 1996 * Panel Control HW instance mask. 1997 * Bit 0 is Panel Control HW instance 0. 1998 * Bit 1 is Panel Control HW instance 1. 1999 */ 2000 uint8_t panel_mask; 2001 2002 /** 2003 * Explicit padding to 4 byte boundary. 2004 */ 2005 uint8_t pad[2]; 2006 }; 2007 2008 /** 2009 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2010 */ 2011 struct dmub_rb_cmd_abm_set_pwm_frac { 2012 /** 2013 * Command header. 2014 */ 2015 struct dmub_cmd_header header; 2016 2017 /** 2018 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2019 */ 2020 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2021 }; 2022 2023 /** 2024 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2025 */ 2026 struct dmub_cmd_abm_init_config_data { 2027 /** 2028 * Location of indirect buffer used to pass init data to ABM. 2029 */ 2030 union dmub_addr src; 2031 2032 /** 2033 * Indirect buffer length. 2034 */ 2035 uint16_t bytes; 2036 2037 2038 /** 2039 * ABM control version. 2040 */ 2041 uint8_t version; 2042 2043 /** 2044 * Panel Control HW instance mask. 2045 * Bit 0 is Panel Control HW instance 0. 2046 * Bit 1 is Panel Control HW instance 1. 2047 */ 2048 uint8_t panel_mask; 2049 2050 /** 2051 * Explicit padding to 4 byte boundary. 2052 */ 2053 uint8_t pad[2]; 2054 }; 2055 2056 /** 2057 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2058 */ 2059 struct dmub_rb_cmd_abm_init_config { 2060 /** 2061 * Command header. 2062 */ 2063 struct dmub_cmd_header header; 2064 2065 /** 2066 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2067 */ 2068 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2069 }; 2070 2071 /** 2072 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2073 */ 2074 struct dmub_cmd_query_feature_caps_data { 2075 /** 2076 * DMUB feature capabilities. 2077 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2078 */ 2079 struct dmub_feature_caps feature_caps; 2080 }; 2081 2082 /** 2083 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2084 */ 2085 struct dmub_rb_cmd_query_feature_caps { 2086 /** 2087 * Command header. 2088 */ 2089 struct dmub_cmd_header header; 2090 /** 2091 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2092 */ 2093 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2094 }; 2095 2096 struct dmub_optc_state { 2097 uint32_t v_total_max; 2098 uint32_t v_total_min; 2099 uint32_t v_total_mid; 2100 uint32_t v_total_mid_frame_num; 2101 uint32_t tg_inst; 2102 uint32_t enable_manual_trigger; 2103 uint32_t clear_force_vsync; 2104 }; 2105 2106 struct dmub_rb_cmd_drr_update { 2107 struct dmub_cmd_header header; 2108 struct dmub_optc_state dmub_optc_state_req; 2109 }; 2110 2111 /** 2112 * enum dmub_cmd_panel_cntl_type - Panel control command. 2113 */ 2114 enum dmub_cmd_panel_cntl_type { 2115 /** 2116 * Initializes embedded panel hardware blocks. 2117 */ 2118 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2119 /** 2120 * Queries backlight info for the embedded panel. 2121 */ 2122 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2123 }; 2124 2125 /** 2126 * struct dmub_cmd_panel_cntl_data - Panel control data. 2127 */ 2128 struct dmub_cmd_panel_cntl_data { 2129 uint32_t inst; /**< panel instance */ 2130 uint32_t current_backlight; /* in/out */ 2131 uint32_t bl_pwm_cntl; /* in/out */ 2132 uint32_t bl_pwm_period_cntl; /* in/out */ 2133 uint32_t bl_pwm_ref_div1; /* in/out */ 2134 uint8_t is_backlight_on : 1; /* in/out */ 2135 uint8_t is_powered_on : 1; /* in/out */ 2136 }; 2137 2138 /** 2139 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2140 */ 2141 struct dmub_rb_cmd_panel_cntl { 2142 struct dmub_cmd_header header; /**< header */ 2143 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2144 }; 2145 2146 /** 2147 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2148 */ 2149 struct dmub_cmd_lvtma_control_data { 2150 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2151 uint8_t reserved_0[3]; /**< For future use */ 2152 uint8_t panel_inst; /**< LVTMA control instance */ 2153 uint8_t reserved_1[3]; /**< For future use */ 2154 }; 2155 2156 /** 2157 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2158 */ 2159 struct dmub_rb_cmd_lvtma_control { 2160 /** 2161 * Command header. 2162 */ 2163 struct dmub_cmd_header header; 2164 /** 2165 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2166 */ 2167 struct dmub_cmd_lvtma_control_data data; 2168 }; 2169 2170 /** 2171 * Maximum number of bytes a chunk sent to DMUB for parsing 2172 */ 2173 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2174 2175 /** 2176 * Represent a chunk of CEA blocks sent to DMUB for parsing 2177 */ 2178 struct dmub_cmd_send_edid_cea { 2179 uint16_t offset; /**< offset into the CEA block */ 2180 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2181 uint16_t total_length; /**< total length of the CEA block */ 2182 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2183 uint8_t pad[3]; /**< padding and for future expansion */ 2184 }; 2185 2186 /** 2187 * Result of VSDB parsing from CEA block 2188 */ 2189 struct dmub_cmd_edid_cea_amd_vsdb { 2190 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2191 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2192 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2193 uint16_t min_frame_rate; /**< Maximum frame rate */ 2194 uint16_t max_frame_rate; /**< Minimum frame rate */ 2195 }; 2196 2197 /** 2198 * Result of sending a CEA chunk 2199 */ 2200 struct dmub_cmd_edid_cea_ack { 2201 uint16_t offset; /**< offset of the chunk into the CEA block */ 2202 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2203 uint8_t pad; /**< padding and for future expansion */ 2204 }; 2205 2206 /** 2207 * Specify whether the result is an ACK/NACK or the parsing has finished 2208 */ 2209 enum dmub_cmd_edid_cea_reply_type { 2210 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2211 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2212 }; 2213 2214 /** 2215 * Definition of a DMUB_CMD__EDID_CEA command. 2216 */ 2217 struct dmub_rb_cmd_edid_cea { 2218 struct dmub_cmd_header header; /**< Command header */ 2219 union dmub_cmd_edid_cea_data { 2220 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2221 struct dmub_cmd_edid_cea_output { /**< output with results */ 2222 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2223 union { 2224 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2225 struct dmub_cmd_edid_cea_ack ack; 2226 }; 2227 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2228 } data; /**< Command data */ 2229 2230 }; 2231 2232 /** 2233 * union dmub_rb_cmd - DMUB inbox command. 2234 */ 2235 union dmub_rb_cmd { 2236 struct dmub_rb_cmd_lock_hw lock_hw; 2237 /** 2238 * Elements shared with all commands. 2239 */ 2240 struct dmub_rb_cmd_common cmd_common; 2241 /** 2242 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2243 */ 2244 struct dmub_rb_cmd_read_modify_write read_modify_write; 2245 /** 2246 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2247 */ 2248 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2249 /** 2250 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2251 */ 2252 struct dmub_rb_cmd_burst_write burst_write; 2253 /** 2254 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2255 */ 2256 struct dmub_rb_cmd_reg_wait reg_wait; 2257 /** 2258 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2259 */ 2260 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2261 /** 2262 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2263 */ 2264 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2265 /** 2266 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2267 */ 2268 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2269 /** 2270 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2271 */ 2272 struct dmub_rb_cmd_dpphy_init dpphy_init; 2273 /** 2274 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2275 */ 2276 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2277 /** 2278 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2279 */ 2280 struct dmub_rb_cmd_psr_set_version psr_set_version; 2281 /** 2282 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2283 */ 2284 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2285 /** 2286 * Definition of a DMUB_CMD__PSR_ENABLE command. 2287 */ 2288 struct dmub_rb_cmd_psr_enable psr_enable; 2289 /** 2290 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2291 */ 2292 struct dmub_rb_cmd_psr_set_level psr_set_level; 2293 /** 2294 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2295 */ 2296 struct dmub_rb_cmd_psr_force_static psr_force_static; 2297 /** 2298 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2299 */ 2300 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2301 /** 2302 * Definition of a DMUB_CMD__MALL command. 2303 */ 2304 struct dmub_rb_cmd_mall mall; 2305 /** 2306 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2307 */ 2308 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2309 2310 /** 2311 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2312 */ 2313 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2314 2315 /** 2316 * Definition of DMUB_CMD__PANEL_CNTL commands. 2317 */ 2318 struct dmub_rb_cmd_panel_cntl panel_cntl; 2319 /** 2320 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2321 */ 2322 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2323 2324 /** 2325 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2326 */ 2327 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2328 2329 /** 2330 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2331 */ 2332 struct dmub_rb_cmd_abm_set_level abm_set_level; 2333 2334 /** 2335 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2336 */ 2337 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2338 2339 /** 2340 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2341 */ 2342 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2343 2344 /** 2345 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2346 */ 2347 struct dmub_rb_cmd_abm_init_config abm_init_config; 2348 2349 /** 2350 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2351 */ 2352 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2353 2354 /** 2355 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2356 */ 2357 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2358 2359 /** 2360 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2361 */ 2362 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2363 struct dmub_rb_cmd_drr_update drr_update; 2364 /** 2365 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2366 */ 2367 struct dmub_rb_cmd_lvtma_control lvtma_control; 2368 /** 2369 * Definition of a DMUB_CMD__EDID_CEA command. 2370 */ 2371 struct dmub_rb_cmd_edid_cea edid_cea; 2372 }; 2373 2374 /** 2375 * union dmub_rb_out_cmd - Outbox command 2376 */ 2377 union dmub_rb_out_cmd { 2378 /** 2379 * Parameters common to every command. 2380 */ 2381 struct dmub_rb_cmd_common cmd_common; 2382 /** 2383 * AUX reply command. 2384 */ 2385 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2386 /** 2387 * HPD notify command. 2388 */ 2389 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2390 }; 2391 #pragma pack(pop) 2392 2393 2394 //============================================================================== 2395 //</DMUB_CMD>=================================================================== 2396 //============================================================================== 2397 //< DMUB_RB>==================================================================== 2398 //============================================================================== 2399 2400 #if defined(__cplusplus) 2401 extern "C" { 2402 #endif 2403 2404 /** 2405 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2406 */ 2407 struct dmub_rb_init_params { 2408 void *ctx; /**< Caller provided context pointer */ 2409 void *base_address; /**< CPU base address for ring's data */ 2410 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2411 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2412 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2413 }; 2414 2415 /** 2416 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2417 */ 2418 struct dmub_rb { 2419 void *base_address; /**< CPU address for the ring's data */ 2420 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2421 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2422 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2423 2424 void *ctx; /**< Caller provided context pointer */ 2425 void *dmub; /**< Pointer to the DMUB interface */ 2426 }; 2427 2428 /** 2429 * @brief Checks if the ringbuffer is empty. 2430 * 2431 * @param rb DMUB Ringbuffer 2432 * @return true if empty 2433 * @return false otherwise 2434 */ 2435 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2436 { 2437 return (rb->wrpt == rb->rptr); 2438 } 2439 2440 /** 2441 * @brief Checks if the ringbuffer is full 2442 * 2443 * @param rb DMUB Ringbuffer 2444 * @return true if full 2445 * @return false otherwise 2446 */ 2447 static inline bool dmub_rb_full(struct dmub_rb *rb) 2448 { 2449 uint32_t data_count; 2450 2451 if (rb->wrpt >= rb->rptr) 2452 data_count = rb->wrpt - rb->rptr; 2453 else 2454 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2455 2456 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2457 } 2458 2459 /** 2460 * @brief Pushes a command into the ringbuffer 2461 * 2462 * @param rb DMUB ringbuffer 2463 * @param cmd The command to push 2464 * @return true if the ringbuffer was not full 2465 * @return false otherwise 2466 */ 2467 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2468 const union dmub_rb_cmd *cmd) 2469 { 2470 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 2471 const uint64_t *src = (const uint64_t *)cmd; 2472 uint8_t i; 2473 2474 if (dmub_rb_full(rb)) 2475 return false; 2476 2477 // copying data 2478 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2479 *dst++ = *src++; 2480 2481 rb->wrpt += DMUB_RB_CMD_SIZE; 2482 2483 if (rb->wrpt >= rb->capacity) 2484 rb->wrpt %= rb->capacity; 2485 2486 return true; 2487 } 2488 2489 /** 2490 * @brief Pushes a command into the DMUB outbox ringbuffer 2491 * 2492 * @param rb DMUB outbox ringbuffer 2493 * @param cmd Outbox command 2494 * @return true if not full 2495 * @return false otherwise 2496 */ 2497 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2498 const union dmub_rb_out_cmd *cmd) 2499 { 2500 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2501 const uint8_t *src = (uint8_t *)cmd; 2502 2503 if (dmub_rb_full(rb)) 2504 return false; 2505 2506 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2507 2508 rb->wrpt += DMUB_RB_CMD_SIZE; 2509 2510 if (rb->wrpt >= rb->capacity) 2511 rb->wrpt %= rb->capacity; 2512 2513 return true; 2514 } 2515 2516 /** 2517 * @brief Returns the next unprocessed command in the ringbuffer. 2518 * 2519 * @param rb DMUB ringbuffer 2520 * @param cmd The command to return 2521 * @return true if not empty 2522 * @return false otherwise 2523 */ 2524 static inline bool dmub_rb_front(struct dmub_rb *rb, 2525 union dmub_rb_cmd **cmd) 2526 { 2527 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2528 2529 if (dmub_rb_empty(rb)) 2530 return false; 2531 2532 *cmd = (union dmub_rb_cmd *)rb_cmd; 2533 2534 return true; 2535 } 2536 2537 /** 2538 * @brief Determines the next ringbuffer offset. 2539 * 2540 * @param rb DMUB inbox ringbuffer 2541 * @param num_cmds Number of commands 2542 * @param next_rptr The next offset in the ringbuffer 2543 */ 2544 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2545 uint32_t num_cmds, 2546 uint32_t *next_rptr) 2547 { 2548 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2549 2550 if (*next_rptr >= rb->capacity) 2551 *next_rptr %= rb->capacity; 2552 } 2553 2554 /** 2555 * @brief Returns a pointer to a command in the inbox. 2556 * 2557 * @param rb DMUB inbox ringbuffer 2558 * @param cmd The inbox command to return 2559 * @param rptr The ringbuffer offset 2560 * @return true if not empty 2561 * @return false otherwise 2562 */ 2563 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 2564 union dmub_rb_cmd **cmd, 2565 uint32_t rptr) 2566 { 2567 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 2568 2569 if (dmub_rb_empty(rb)) 2570 return false; 2571 2572 *cmd = (union dmub_rb_cmd *)rb_cmd; 2573 2574 return true; 2575 } 2576 2577 /** 2578 * @brief Returns the next unprocessed command in the outbox. 2579 * 2580 * @param rb DMUB outbox ringbuffer 2581 * @param cmd The outbox command to return 2582 * @return true if not empty 2583 * @return false otherwise 2584 */ 2585 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2586 union dmub_rb_out_cmd *cmd) 2587 { 2588 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 2589 uint64_t *dst = (uint64_t *)cmd; 2590 uint8_t i; 2591 2592 if (dmub_rb_empty(rb)) 2593 return false; 2594 2595 // copying data 2596 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2597 *dst++ = *src++; 2598 2599 return true; 2600 } 2601 2602 /** 2603 * @brief Removes the front entry in the ringbuffer. 2604 * 2605 * @param rb DMUB ringbuffer 2606 * @return true if the command was removed 2607 * @return false if there were no commands 2608 */ 2609 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 2610 { 2611 if (dmub_rb_empty(rb)) 2612 return false; 2613 2614 rb->rptr += DMUB_RB_CMD_SIZE; 2615 2616 if (rb->rptr >= rb->capacity) 2617 rb->rptr %= rb->capacity; 2618 2619 return true; 2620 } 2621 2622 /** 2623 * @brief Flushes commands in the ringbuffer to framebuffer memory. 2624 * 2625 * Avoids a race condition where DMCUB accesses memory while 2626 * there are still writes in flight to framebuffer. 2627 * 2628 * @param rb DMUB ringbuffer 2629 */ 2630 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 2631 { 2632 uint32_t rptr = rb->rptr; 2633 uint32_t wptr = rb->wrpt; 2634 2635 while (rptr != wptr) { 2636 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 2637 uint8_t i; 2638 2639 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2640 *data++; 2641 2642 rptr += DMUB_RB_CMD_SIZE; 2643 if (rptr >= rb->capacity) 2644 rptr %= rb->capacity; 2645 } 2646 } 2647 2648 /** 2649 * @brief Initializes a DMCUB ringbuffer 2650 * 2651 * @param rb DMUB ringbuffer 2652 * @param init_params initial configuration for the ringbuffer 2653 */ 2654 static inline void dmub_rb_init(struct dmub_rb *rb, 2655 struct dmub_rb_init_params *init_params) 2656 { 2657 rb->base_address = init_params->base_address; 2658 rb->capacity = init_params->capacity; 2659 rb->rptr = init_params->read_ptr; 2660 rb->wrpt = init_params->write_ptr; 2661 } 2662 2663 /** 2664 * @brief Copies output data from in/out commands into the given command. 2665 * 2666 * @param rb DMUB ringbuffer 2667 * @param cmd Command to copy data into 2668 */ 2669 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 2670 union dmub_rb_cmd *cmd) 2671 { 2672 // Copy rb entry back into command 2673 uint8_t *rd_ptr = (rb->rptr == 0) ? 2674 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 2675 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 2676 2677 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 2678 } 2679 2680 #if defined(__cplusplus) 2681 } 2682 #endif 2683 2684 //============================================================================== 2685 //</DMUB_RB>==================================================================== 2686 //============================================================================== 2687 2688 #endif /* _DMUB_CMD_H_ */ 2689