1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 /* Firmware versioning. */ 48 #ifdef DMUB_EXPOSE_VERSION 49 #define DMUB_FW_VERSION_GIT_HASH 0x929554ba 50 #define DMUB_FW_VERSION_MAJOR 0 51 #define DMUB_FW_VERSION_MINOR 0 52 #define DMUB_FW_VERSION_REVISION 108 53 #define DMUB_FW_VERSION_TEST 0 54 #define DMUB_FW_VERSION_VBIOS 0 55 #define DMUB_FW_VERSION_HOTFIX 0 56 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 57 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 58 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 59 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 60 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 61 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 62 63 #endif 64 65 //<DMUB_TYPES>================================================================== 66 /* Basic type definitions. */ 67 68 #define __forceinline inline 69 70 /** 71 * Flag from driver to indicate that ABM should be disabled gradually 72 * by slowly reversing all backlight programming and pixel compensation. 73 */ 74 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 75 76 /** 77 * Flag from driver to indicate that ABM should be disabled immediately 78 * and undo all backlight programming and pixel compensation. 79 */ 80 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 81 82 /** 83 * Flag from driver to indicate that ABM should be disabled immediately 84 * and keep the current backlight programming and pixel compensation. 85 */ 86 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 87 88 /** 89 * Flag from driver to set the current ABM pipe index or ABM operating level. 90 */ 91 #define SET_ABM_PIPE_NORMAL 1 92 93 /** 94 * Number of ambient light levels in ABM algorithm. 95 */ 96 #define NUM_AMBI_LEVEL 5 97 98 /** 99 * Number of operating/aggression levels in ABM algorithm. 100 */ 101 #define NUM_AGGR_LEVEL 4 102 103 /** 104 * Number of segments in the gamma curve. 105 */ 106 #define NUM_POWER_FN_SEGS 8 107 108 /** 109 * Number of segments in the backlight curve. 110 */ 111 #define NUM_BL_CURVE_SEGS 16 112 113 /* Maximum number of streams on any ASIC. */ 114 #define DMUB_MAX_STREAMS 6 115 116 /* Maximum number of planes on any ASIC. */ 117 #define DMUB_MAX_PLANES 6 118 119 /* Trace buffer offset for entry */ 120 #define TRACE_BUFFER_ENTRY_OFFSET 16 121 122 /** 123 * 124 * PSR control version legacy 125 */ 126 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 127 /** 128 * PSR control version with multi edp support 129 */ 130 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 131 132 133 /** 134 * ABM control version legacy 135 */ 136 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 137 138 /** 139 * ABM control version with multi edp support 140 */ 141 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 142 143 /** 144 * Physical framebuffer address location, 64-bit. 145 */ 146 #ifndef PHYSICAL_ADDRESS_LOC 147 #define PHYSICAL_ADDRESS_LOC union large_integer 148 #endif 149 150 /** 151 * OS/FW agnostic memcpy 152 */ 153 #ifndef dmub_memcpy 154 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 155 #endif 156 157 /** 158 * OS/FW agnostic memset 159 */ 160 #ifndef dmub_memset 161 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 162 #endif 163 164 #if defined(__cplusplus) 165 extern "C" { 166 #endif 167 168 /** 169 * OS/FW agnostic udelay 170 */ 171 #ifndef dmub_udelay 172 #define dmub_udelay(microseconds) udelay(microseconds) 173 #endif 174 175 /** 176 * union dmub_addr - DMUB physical/virtual 64-bit address. 177 */ 178 union dmub_addr { 179 struct { 180 uint32_t low_part; /**< Lower 32 bits */ 181 uint32_t high_part; /**< Upper 32 bits */ 182 } u; /*<< Low/high bit access */ 183 uint64_t quad_part; /*<< 64 bit address */ 184 }; 185 186 /** 187 * Flags that can be set by driver to change some PSR behaviour. 188 */ 189 union dmub_psr_debug_flags { 190 /** 191 * Debug flags. 192 */ 193 struct { 194 /** 195 * Enable visual confirm in FW. 196 */ 197 uint32_t visual_confirm : 1; 198 /** 199 * Use HW Lock Mgr object to do HW locking in FW. 200 */ 201 uint32_t use_hw_lock_mgr : 1; 202 203 /** 204 * Use TPS3 signal when restore main link. 205 */ 206 uint32_t force_wakeup_by_tps3 : 1; 207 } bitfields; 208 209 /** 210 * Union for debug flags. 211 */ 212 uint32_t u32All; 213 }; 214 215 /** 216 * DMUB feature capabilities. 217 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 218 */ 219 struct dmub_feature_caps { 220 /** 221 * Max PSR version supported by FW. 222 */ 223 uint8_t psr; 224 uint8_t reserved[7]; 225 }; 226 227 #if defined(__cplusplus) 228 } 229 #endif 230 231 //============================================================================== 232 //</DMUB_TYPES>================================================================= 233 //============================================================================== 234 //< DMUB_META>================================================================== 235 //============================================================================== 236 #pragma pack(push, 1) 237 238 /* Magic value for identifying dmub_fw_meta_info */ 239 #define DMUB_FW_META_MAGIC 0x444D5542 240 241 /* Offset from the end of the file to the dmub_fw_meta_info */ 242 #define DMUB_FW_META_OFFSET 0x24 243 244 /** 245 * struct dmub_fw_meta_info - metadata associated with fw binary 246 * 247 * NOTE: This should be considered a stable API. Fields should 248 * not be repurposed or reordered. New fields should be 249 * added instead to extend the structure. 250 * 251 * @magic_value: magic value identifying DMUB firmware meta info 252 * @fw_region_size: size of the firmware state region 253 * @trace_buffer_size: size of the tracebuffer region 254 * @fw_version: the firmware version information 255 * @dal_fw: 1 if the firmware is DAL 256 */ 257 struct dmub_fw_meta_info { 258 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 259 uint32_t fw_region_size; /**< size of the firmware state region */ 260 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 261 uint32_t fw_version; /**< the firmware version information */ 262 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 263 uint8_t reserved[3]; /**< padding bits */ 264 }; 265 266 /** 267 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 268 */ 269 union dmub_fw_meta { 270 struct dmub_fw_meta_info info; /**< metadata info */ 271 uint8_t reserved[64]; /**< padding bits */ 272 }; 273 274 #pragma pack(pop) 275 276 //============================================================================== 277 //< DMUB Trace Buffer>================================================================ 278 //============================================================================== 279 /** 280 * dmub_trace_code_t - firmware trace code, 32-bits 281 */ 282 typedef uint32_t dmub_trace_code_t; 283 284 /** 285 * struct dmcub_trace_buf_entry - Firmware trace entry 286 */ 287 struct dmcub_trace_buf_entry { 288 dmub_trace_code_t trace_code; /**< trace code for the event */ 289 uint32_t tick_count; /**< the tick count at time of trace */ 290 uint32_t param0; /**< trace defined parameter 0 */ 291 uint32_t param1; /**< trace defined parameter 1 */ 292 }; 293 294 //============================================================================== 295 //< DMUB_STATUS>================================================================ 296 //============================================================================== 297 298 /** 299 * DMCUB scratch registers can be used to determine firmware status. 300 * Current scratch register usage is as follows: 301 * 302 * SCRATCH0: FW Boot Status register 303 * SCRATCH5: LVTMA Status Register 304 * SCRATCH15: FW Boot Options register 305 */ 306 307 /** 308 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 309 */ 310 union dmub_fw_boot_status { 311 struct { 312 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 313 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 314 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 315 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 316 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 317 uint32_t reserved : 1; 318 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 319 320 } bits; /**< status bits */ 321 uint32_t all; /**< 32-bit access to status bits */ 322 }; 323 324 /** 325 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 326 */ 327 enum dmub_fw_boot_status_bit { 328 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 329 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 330 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 331 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 332 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 333 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 334 }; 335 336 /* Register bit definition for SCRATCH5 */ 337 union dmub_lvtma_status { 338 struct { 339 uint32_t psp_ok : 1; 340 uint32_t edp_on : 1; 341 uint32_t reserved : 30; 342 } bits; 343 uint32_t all; 344 }; 345 346 enum dmub_lvtma_status_bit { 347 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 348 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 349 }; 350 351 /** 352 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 353 */ 354 union dmub_fw_boot_options { 355 struct { 356 uint32_t pemu_env : 1; /**< 1 if PEMU */ 357 uint32_t fpga_env : 1; /**< 1 if FPGA */ 358 uint32_t optimized_init : 1; /**< 1 if optimized init */ 359 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 360 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 361 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 362 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 363 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 364 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 365 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 366 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 367 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 368 uint32_t power_optimization: 1; 369 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 370 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 371 372 uint32_t reserved : 18; /**< reserved */ 373 } bits; /**< boot bits */ 374 uint32_t all; /**< 32-bit access to bits */ 375 }; 376 377 enum dmub_fw_boot_options_bit { 378 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 379 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 380 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 381 }; 382 383 //============================================================================== 384 //</DMUB_STATUS>================================================================ 385 //============================================================================== 386 //< DMUB_VBIOS>================================================================= 387 //============================================================================== 388 389 /* 390 * enum dmub_cmd_vbios_type - VBIOS commands. 391 * 392 * Command IDs should be treated as stable ABI. 393 * Do not reuse or modify IDs. 394 */ 395 enum dmub_cmd_vbios_type { 396 /** 397 * Configures the DIG encoder. 398 */ 399 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 400 /** 401 * Controls the PHY. 402 */ 403 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 404 /** 405 * Sets the pixel clock/symbol clock. 406 */ 407 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 408 /** 409 * Enables or disables power gating. 410 */ 411 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 412 /** 413 * Controls embedded panels. 414 */ 415 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 416 /** 417 * Query DP alt status on a transmitter. 418 */ 419 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 420 }; 421 422 //============================================================================== 423 //</DMUB_VBIOS>================================================================= 424 //============================================================================== 425 //< DMUB_GPINT>================================================================= 426 //============================================================================== 427 428 /** 429 * The shifts and masks below may alternatively be used to format and read 430 * the command register bits. 431 */ 432 433 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 434 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 435 436 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 437 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 438 439 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 440 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 441 442 /** 443 * Command responses. 444 */ 445 446 /** 447 * Return response for DMUB_GPINT__STOP_FW command. 448 */ 449 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 450 451 /** 452 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 453 */ 454 union dmub_gpint_data_register { 455 struct { 456 uint32_t param : 16; /**< 16-bit parameter */ 457 uint32_t command_code : 12; /**< GPINT command */ 458 uint32_t status : 4; /**< Command status bit */ 459 } bits; /**< GPINT bit access */ 460 uint32_t all; /**< GPINT 32-bit access */ 461 }; 462 463 /* 464 * enum dmub_gpint_command - GPINT command to DMCUB FW 465 * 466 * Command IDs should be treated as stable ABI. 467 * Do not reuse or modify IDs. 468 */ 469 enum dmub_gpint_command { 470 /** 471 * Invalid command, ignored. 472 */ 473 DMUB_GPINT__INVALID_COMMAND = 0, 474 /** 475 * DESC: Queries the firmware version. 476 * RETURN: Firmware version. 477 */ 478 DMUB_GPINT__GET_FW_VERSION = 1, 479 /** 480 * DESC: Halts the firmware. 481 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 482 */ 483 DMUB_GPINT__STOP_FW = 2, 484 /** 485 * DESC: Get PSR state from FW. 486 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 487 */ 488 DMUB_GPINT__GET_PSR_STATE = 7, 489 /** 490 * DESC: Notifies DMCUB of the currently active streams. 491 * ARGS: Stream mask, 1 bit per active stream index. 492 */ 493 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 494 /** 495 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 496 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 497 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 498 * RETURN: PSR residency in milli-percent. 499 */ 500 DMUB_GPINT__PSR_RESIDENCY = 9, 501 502 /** 503 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 504 */ 505 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 506 }; 507 508 /** 509 * INBOX0 generic command definition 510 */ 511 union dmub_inbox0_cmd_common { 512 struct { 513 uint32_t command_code: 8; /**< INBOX0 command code */ 514 uint32_t param: 24; /**< 24-bit parameter */ 515 } bits; 516 uint32_t all; 517 }; 518 519 /** 520 * INBOX0 hw_lock command definition 521 */ 522 union dmub_inbox0_cmd_lock_hw { 523 struct { 524 uint32_t command_code: 8; 525 526 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 527 uint32_t hw_lock_client: 2; 528 529 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 530 uint32_t otg_inst: 3; 531 uint32_t opp_inst: 3; 532 uint32_t dig_inst: 3; 533 534 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 535 uint32_t lock_pipe: 1; 536 uint32_t lock_cursor: 1; 537 uint32_t lock_dig: 1; 538 uint32_t triple_buffer_lock: 1; 539 540 uint32_t lock: 1; /**< Lock */ 541 uint32_t should_release: 1; /**< Release */ 542 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 543 } bits; 544 uint32_t all; 545 }; 546 547 union dmub_inbox0_data_register { 548 union dmub_inbox0_cmd_common inbox0_cmd_common; 549 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 550 }; 551 552 enum dmub_inbox0_command { 553 /** 554 * DESC: Invalid command, ignored. 555 */ 556 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 557 /** 558 * DESC: Notification to acquire/release HW lock 559 * ARGS: 560 */ 561 DMUB_INBOX0_CMD__HW_LOCK = 1, 562 }; 563 //============================================================================== 564 //</DMUB_GPINT>================================================================= 565 //============================================================================== 566 //< DMUB_CMD>=================================================================== 567 //============================================================================== 568 569 /** 570 * Size in bytes of each DMUB command. 571 */ 572 #define DMUB_RB_CMD_SIZE 64 573 574 /** 575 * Maximum number of items in the DMUB ringbuffer. 576 */ 577 #define DMUB_RB_MAX_ENTRY 128 578 579 /** 580 * Ringbuffer size in bytes. 581 */ 582 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 583 584 /** 585 * REG_SET mask for reg offload. 586 */ 587 #define REG_SET_MASK 0xFFFF 588 589 /* 590 * enum dmub_cmd_type - DMUB inbox command. 591 * 592 * Command IDs should be treated as stable ABI. 593 * Do not reuse or modify IDs. 594 */ 595 enum dmub_cmd_type { 596 /** 597 * Invalid command. 598 */ 599 DMUB_CMD__NULL = 0, 600 /** 601 * Read modify write register sequence offload. 602 */ 603 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 604 /** 605 * Field update register sequence offload. 606 */ 607 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 608 /** 609 * Burst write sequence offload. 610 */ 611 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 612 /** 613 * Reg wait sequence offload. 614 */ 615 DMUB_CMD__REG_REG_WAIT = 4, 616 /** 617 * Workaround to avoid HUBP underflow during NV12 playback. 618 */ 619 DMUB_CMD__PLAT_54186_WA = 5, 620 /** 621 * Command type used to query FW feature caps. 622 */ 623 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 624 /** 625 * Command type used for all PSR commands. 626 */ 627 DMUB_CMD__PSR = 64, 628 /** 629 * Command type used for all MALL commands. 630 */ 631 DMUB_CMD__MALL = 65, 632 /** 633 * Command type used for all ABM commands. 634 */ 635 DMUB_CMD__ABM = 66, 636 /** 637 * Command type used for HW locking in FW. 638 */ 639 DMUB_CMD__HW_LOCK = 69, 640 /** 641 * Command type used to access DP AUX. 642 */ 643 DMUB_CMD__DP_AUX_ACCESS = 70, 644 /** 645 * Command type used for OUTBOX1 notification enable 646 */ 647 DMUB_CMD__OUTBOX1_ENABLE = 71, 648 649 /** 650 * Command type used for all idle optimization commands. 651 */ 652 DMUB_CMD__IDLE_OPT = 72, 653 /** 654 * Command type used for all clock manager commands. 655 */ 656 DMUB_CMD__CLK_MGR = 73, 657 /** 658 * Command type used for all panel control commands. 659 */ 660 DMUB_CMD__PANEL_CNTL = 74, 661 662 /** 663 * Command type used for interfacing with DPIA. 664 */ 665 DMUB_CMD__DPIA = 77, 666 /** 667 * Command type used for EDID CEA parsing 668 */ 669 DMUB_CMD__EDID_CEA = 79, 670 /** 671 * Command type used for getting usbc cable ID 672 */ 673 DMUB_CMD_GET_USBC_CABLE_ID = 81, 674 /** 675 * Command type used for all VBIOS interface commands. 676 */ 677 DMUB_CMD__VBIOS = 128, 678 }; 679 680 /** 681 * enum dmub_out_cmd_type - DMUB outbox commands. 682 */ 683 enum dmub_out_cmd_type { 684 /** 685 * Invalid outbox command, ignored. 686 */ 687 DMUB_OUT_CMD__NULL = 0, 688 /** 689 * Command type used for DP AUX Reply data notification 690 */ 691 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 692 /** 693 * Command type used for DP HPD event notification 694 */ 695 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 696 /** 697 * Command type used for SET_CONFIG Reply notification 698 */ 699 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 700 }; 701 702 /* DMUB_CMD__DPIA command sub-types. */ 703 enum dmub_cmd_dpia_type { 704 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 705 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 706 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 707 }; 708 709 #pragma pack(push, 1) 710 711 /** 712 * struct dmub_cmd_header - Common command header fields. 713 */ 714 struct dmub_cmd_header { 715 unsigned int type : 8; /**< command type */ 716 unsigned int sub_type : 8; /**< command sub type */ 717 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 718 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 719 unsigned int reserved0 : 6; /**< reserved bits */ 720 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 721 unsigned int reserved1 : 2; /**< reserved bits */ 722 }; 723 724 /* 725 * struct dmub_cmd_read_modify_write_sequence - Read modify write 726 * 727 * 60 payload bytes can hold up to 5 sets of read modify writes, 728 * each take 3 dwords. 729 * 730 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 731 * 732 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 733 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 734 */ 735 struct dmub_cmd_read_modify_write_sequence { 736 uint32_t addr; /**< register address */ 737 uint32_t modify_mask; /**< modify mask */ 738 uint32_t modify_value; /**< modify value */ 739 }; 740 741 /** 742 * Maximum number of ops in read modify write sequence. 743 */ 744 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 745 746 /** 747 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 748 */ 749 struct dmub_rb_cmd_read_modify_write { 750 struct dmub_cmd_header header; /**< command header */ 751 /** 752 * Read modify write sequence. 753 */ 754 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 755 }; 756 757 /* 758 * Update a register with specified masks and values sequeunce 759 * 760 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 761 * 762 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 763 * 764 * 765 * USE CASE: 766 * 1. auto-increment register where additional read would update pointer and produce wrong result 767 * 2. toggle a bit without read in the middle 768 */ 769 770 struct dmub_cmd_reg_field_update_sequence { 771 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 772 uint32_t modify_value; /**< value to update with */ 773 }; 774 775 /** 776 * Maximum number of ops in field update sequence. 777 */ 778 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 779 780 /** 781 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 782 */ 783 struct dmub_rb_cmd_reg_field_update_sequence { 784 struct dmub_cmd_header header; /**< command header */ 785 uint32_t addr; /**< register address */ 786 /** 787 * Field update sequence. 788 */ 789 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 790 }; 791 792 793 /** 794 * Maximum number of burst write values. 795 */ 796 #define DMUB_BURST_WRITE_VALUES__MAX 14 797 798 /* 799 * struct dmub_rb_cmd_burst_write - Burst write 800 * 801 * support use case such as writing out LUTs. 802 * 803 * 60 payload bytes can hold up to 14 values to write to given address 804 * 805 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 806 */ 807 struct dmub_rb_cmd_burst_write { 808 struct dmub_cmd_header header; /**< command header */ 809 uint32_t addr; /**< register start address */ 810 /** 811 * Burst write register values. 812 */ 813 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 814 }; 815 816 /** 817 * struct dmub_rb_cmd_common - Common command header 818 */ 819 struct dmub_rb_cmd_common { 820 struct dmub_cmd_header header; /**< command header */ 821 /** 822 * Padding to RB_CMD_SIZE 823 */ 824 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 825 }; 826 827 /** 828 * struct dmub_cmd_reg_wait_data - Register wait data 829 */ 830 struct dmub_cmd_reg_wait_data { 831 uint32_t addr; /**< Register address */ 832 uint32_t mask; /**< Mask for register bits */ 833 uint32_t condition_field_value; /**< Value to wait for */ 834 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 835 }; 836 837 /** 838 * struct dmub_rb_cmd_reg_wait - Register wait command 839 */ 840 struct dmub_rb_cmd_reg_wait { 841 struct dmub_cmd_header header; /**< Command header */ 842 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 843 }; 844 845 /** 846 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 847 * 848 * Reprograms surface parameters to avoid underflow. 849 */ 850 struct dmub_cmd_PLAT_54186_wa { 851 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 852 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 853 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 854 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 855 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 856 struct { 857 uint8_t hubp_inst : 4; /**< HUBP instance */ 858 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 859 uint8_t immediate :1; /**< Immediate flip */ 860 uint8_t vmid : 4; /**< VMID */ 861 uint8_t grph_stereo : 1; /**< 1 if stereo */ 862 uint32_t reserved : 21; /**< Reserved */ 863 } flip_params; /**< Pageflip parameters */ 864 uint32_t reserved[9]; /**< Reserved bits */ 865 }; 866 867 /** 868 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 869 */ 870 struct dmub_rb_cmd_PLAT_54186_wa { 871 struct dmub_cmd_header header; /**< Command header */ 872 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 873 }; 874 875 /** 876 * struct dmub_rb_cmd_mall - MALL command data. 877 */ 878 struct dmub_rb_cmd_mall { 879 struct dmub_cmd_header header; /**< Common command header */ 880 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 881 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 882 uint32_t tmr_delay; /**< Timer delay */ 883 uint32_t tmr_scale; /**< Timer scale */ 884 uint16_t cursor_width; /**< Cursor width in pixels */ 885 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 886 uint16_t cursor_height; /**< Cursor height in pixels */ 887 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 888 uint8_t debug_bits; /**< Debug bits */ 889 890 uint8_t reserved1; /**< Reserved bits */ 891 uint8_t reserved2; /**< Reserved bits */ 892 }; 893 894 /** 895 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 896 */ 897 enum dmub_cmd_idle_opt_type { 898 /** 899 * DCN hardware restore. 900 */ 901 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 902 903 /** 904 * DCN hardware save. 905 */ 906 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 907 }; 908 909 /** 910 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 911 */ 912 struct dmub_rb_cmd_idle_opt_dcn_restore { 913 struct dmub_cmd_header header; /**< header */ 914 }; 915 916 /** 917 * struct dmub_clocks - Clock update notification. 918 */ 919 struct dmub_clocks { 920 uint32_t dispclk_khz; /**< dispclk kHz */ 921 uint32_t dppclk_khz; /**< dppclk kHz */ 922 uint32_t dcfclk_khz; /**< dcfclk kHz */ 923 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 924 }; 925 926 /** 927 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 928 */ 929 enum dmub_cmd_clk_mgr_type { 930 /** 931 * Notify DMCUB of clock update. 932 */ 933 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 934 }; 935 936 /** 937 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 938 */ 939 struct dmub_rb_cmd_clk_mgr_notify_clocks { 940 struct dmub_cmd_header header; /**< header */ 941 struct dmub_clocks clocks; /**< clock data */ 942 }; 943 944 /** 945 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 946 */ 947 struct dmub_cmd_digx_encoder_control_data { 948 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 949 }; 950 951 /** 952 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 953 */ 954 struct dmub_rb_cmd_digx_encoder_control { 955 struct dmub_cmd_header header; /**< header */ 956 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 957 }; 958 959 /** 960 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 961 */ 962 struct dmub_cmd_set_pixel_clock_data { 963 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 964 }; 965 966 /** 967 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 968 */ 969 struct dmub_rb_cmd_set_pixel_clock { 970 struct dmub_cmd_header header; /**< header */ 971 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 972 }; 973 974 /** 975 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 976 */ 977 struct dmub_cmd_enable_disp_power_gating_data { 978 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 979 }; 980 981 /** 982 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 983 */ 984 struct dmub_rb_cmd_enable_disp_power_gating { 985 struct dmub_cmd_header header; /**< header */ 986 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 987 }; 988 989 /** 990 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 991 */ 992 struct dmub_dig_transmitter_control_data_v1_7 { 993 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 994 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 995 union { 996 uint8_t digmode; /**< enum atom_encode_mode_def */ 997 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 998 } mode_laneset; 999 uint8_t lanenum; /**< Number of lanes */ 1000 union { 1001 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1002 } symclk_units; 1003 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1004 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1005 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1006 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1007 uint8_t reserved1; /**< For future use */ 1008 uint8_t reserved2[3]; /**< For future use */ 1009 uint32_t reserved3[11]; /**< For future use */ 1010 }; 1011 1012 /** 1013 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1014 */ 1015 union dmub_cmd_dig1_transmitter_control_data { 1016 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1017 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1018 }; 1019 1020 /** 1021 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1022 */ 1023 struct dmub_rb_cmd_dig1_transmitter_control { 1024 struct dmub_cmd_header header; /**< header */ 1025 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1026 }; 1027 1028 /** 1029 * DPIA tunnel command parameters. 1030 */ 1031 struct dmub_cmd_dig_dpia_control_data { 1032 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1033 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1034 union { 1035 uint8_t digmode; /** enum atom_encode_mode_def */ 1036 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1037 } mode_laneset; 1038 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1039 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1040 uint8_t hpdsel; /** =0: HPD is not assigned */ 1041 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1042 uint8_t dpia_id; /** Index of DPIA */ 1043 uint8_t fec_rdy : 1; 1044 uint8_t reserved : 7; 1045 uint32_t reserved1; 1046 }; 1047 1048 /** 1049 * DMUB command for DPIA tunnel control. 1050 */ 1051 struct dmub_rb_cmd_dig1_dpia_control { 1052 struct dmub_cmd_header header; 1053 struct dmub_cmd_dig_dpia_control_data dpia_control; 1054 }; 1055 1056 /** 1057 * SET_CONFIG Command Payload 1058 */ 1059 struct set_config_cmd_payload { 1060 uint8_t msg_type; /* set config message type */ 1061 uint8_t msg_data; /* set config message data */ 1062 }; 1063 1064 /** 1065 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1066 */ 1067 struct dmub_cmd_set_config_control_data { 1068 struct set_config_cmd_payload cmd_pkt; 1069 uint8_t instance; /* DPIA instance */ 1070 uint8_t immed_status; /* Immediate status returned in case of error */ 1071 }; 1072 1073 /** 1074 * DMUB command structure for SET_CONFIG command. 1075 */ 1076 struct dmub_rb_cmd_set_config_access { 1077 struct dmub_cmd_header header; /* header */ 1078 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1079 }; 1080 1081 /** 1082 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1083 */ 1084 struct dmub_cmd_mst_alloc_slots_control_data { 1085 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1086 uint8_t instance; /* DPIA instance */ 1087 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1088 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1089 }; 1090 1091 /** 1092 * DMUB command structure for SET_ command. 1093 */ 1094 struct dmub_rb_cmd_set_mst_alloc_slots { 1095 struct dmub_cmd_header header; /* header */ 1096 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1097 }; 1098 1099 /** 1100 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1101 */ 1102 struct dmub_rb_cmd_dpphy_init { 1103 struct dmub_cmd_header header; /**< header */ 1104 uint8_t reserved[60]; /**< reserved bits */ 1105 }; 1106 1107 /** 1108 * enum dp_aux_request_action - DP AUX request command listing. 1109 * 1110 * 4 AUX request command bits are shifted to high nibble. 1111 */ 1112 enum dp_aux_request_action { 1113 /** I2C-over-AUX write request */ 1114 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1115 /** I2C-over-AUX read request */ 1116 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1117 /** I2C-over-AUX write status request */ 1118 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1119 /** I2C-over-AUX write request with MOT=1 */ 1120 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1121 /** I2C-over-AUX read request with MOT=1 */ 1122 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1123 /** I2C-over-AUX write status request with MOT=1 */ 1124 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1125 /** Native AUX write request */ 1126 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1127 /** Native AUX read request */ 1128 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1129 }; 1130 1131 /** 1132 * enum aux_return_code_type - DP AUX process return code listing. 1133 */ 1134 enum aux_return_code_type { 1135 /** AUX process succeeded */ 1136 AUX_RET_SUCCESS = 0, 1137 /** AUX process failed with unknown reason */ 1138 AUX_RET_ERROR_UNKNOWN, 1139 /** AUX process completed with invalid reply */ 1140 AUX_RET_ERROR_INVALID_REPLY, 1141 /** AUX process timed out */ 1142 AUX_RET_ERROR_TIMEOUT, 1143 /** HPD was low during AUX process */ 1144 AUX_RET_ERROR_HPD_DISCON, 1145 /** Failed to acquire AUX engine */ 1146 AUX_RET_ERROR_ENGINE_ACQUIRE, 1147 /** AUX request not supported */ 1148 AUX_RET_ERROR_INVALID_OPERATION, 1149 /** AUX process not available */ 1150 AUX_RET_ERROR_PROTOCOL_ERROR, 1151 }; 1152 1153 /** 1154 * enum aux_channel_type - DP AUX channel type listing. 1155 */ 1156 enum aux_channel_type { 1157 /** AUX thru Legacy DP AUX */ 1158 AUX_CHANNEL_LEGACY_DDC, 1159 /** AUX thru DPIA DP tunneling */ 1160 AUX_CHANNEL_DPIA 1161 }; 1162 1163 /** 1164 * struct aux_transaction_parameters - DP AUX request transaction data 1165 */ 1166 struct aux_transaction_parameters { 1167 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1168 uint8_t action; /**< enum dp_aux_request_action */ 1169 uint8_t length; /**< DP AUX request data length */ 1170 uint8_t reserved; /**< For future use */ 1171 uint32_t address; /**< DP AUX address */ 1172 uint8_t data[16]; /**< DP AUX write data */ 1173 }; 1174 1175 /** 1176 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1177 */ 1178 struct dmub_cmd_dp_aux_control_data { 1179 uint8_t instance; /**< AUX instance or DPIA instance */ 1180 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1181 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1182 uint8_t reserved0; /**< For future use */ 1183 uint16_t timeout; /**< timeout time in us */ 1184 uint16_t reserved1; /**< For future use */ 1185 enum aux_channel_type type; /**< enum aux_channel_type */ 1186 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1187 }; 1188 1189 /** 1190 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1191 */ 1192 struct dmub_rb_cmd_dp_aux_access { 1193 /** 1194 * Command header. 1195 */ 1196 struct dmub_cmd_header header; 1197 /** 1198 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1199 */ 1200 struct dmub_cmd_dp_aux_control_data aux_control; 1201 }; 1202 1203 /** 1204 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1205 */ 1206 struct dmub_rb_cmd_outbox1_enable { 1207 /** 1208 * Command header. 1209 */ 1210 struct dmub_cmd_header header; 1211 /** 1212 * enable: 0x0 -> disable outbox1 notification (default value) 1213 * 0x1 -> enable outbox1 notification 1214 */ 1215 uint32_t enable; 1216 }; 1217 1218 /* DP AUX Reply command - OutBox Cmd */ 1219 /** 1220 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1221 */ 1222 struct aux_reply_data { 1223 /** 1224 * Aux cmd 1225 */ 1226 uint8_t command; 1227 /** 1228 * Aux reply data length (max: 16 bytes) 1229 */ 1230 uint8_t length; 1231 /** 1232 * Alignment only 1233 */ 1234 uint8_t pad[2]; 1235 /** 1236 * Aux reply data 1237 */ 1238 uint8_t data[16]; 1239 }; 1240 1241 /** 1242 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1243 */ 1244 struct aux_reply_control_data { 1245 /** 1246 * Reserved for future use 1247 */ 1248 uint32_t handle; 1249 /** 1250 * Aux Instance 1251 */ 1252 uint8_t instance; 1253 /** 1254 * Aux transaction result: definition in enum aux_return_code_type 1255 */ 1256 uint8_t result; 1257 /** 1258 * Alignment only 1259 */ 1260 uint16_t pad; 1261 }; 1262 1263 /** 1264 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1265 */ 1266 struct dmub_rb_cmd_dp_aux_reply { 1267 /** 1268 * Command header. 1269 */ 1270 struct dmub_cmd_header header; 1271 /** 1272 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1273 */ 1274 struct aux_reply_control_data control; 1275 /** 1276 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1277 */ 1278 struct aux_reply_data reply_data; 1279 }; 1280 1281 /* DP HPD Notify command - OutBox Cmd */ 1282 /** 1283 * DP HPD Type 1284 */ 1285 enum dp_hpd_type { 1286 /** 1287 * Normal DP HPD 1288 */ 1289 DP_HPD = 0, 1290 /** 1291 * DP HPD short pulse 1292 */ 1293 DP_IRQ 1294 }; 1295 1296 /** 1297 * DP HPD Status 1298 */ 1299 enum dp_hpd_status { 1300 /** 1301 * DP_HPD status low 1302 */ 1303 DP_HPD_UNPLUG = 0, 1304 /** 1305 * DP_HPD status high 1306 */ 1307 DP_HPD_PLUG 1308 }; 1309 1310 /** 1311 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1312 */ 1313 struct dp_hpd_data { 1314 /** 1315 * DP HPD instance 1316 */ 1317 uint8_t instance; 1318 /** 1319 * HPD type 1320 */ 1321 uint8_t hpd_type; 1322 /** 1323 * HPD status: only for type: DP_HPD to indicate status 1324 */ 1325 uint8_t hpd_status; 1326 /** 1327 * Alignment only 1328 */ 1329 uint8_t pad; 1330 }; 1331 1332 /** 1333 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1334 */ 1335 struct dmub_rb_cmd_dp_hpd_notify { 1336 /** 1337 * Command header. 1338 */ 1339 struct dmub_cmd_header header; 1340 /** 1341 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1342 */ 1343 struct dp_hpd_data hpd_data; 1344 }; 1345 1346 /** 1347 * Definition of a SET_CONFIG reply from DPOA. 1348 */ 1349 enum set_config_status { 1350 SET_CONFIG_PENDING = 0, 1351 SET_CONFIG_ACK_RECEIVED, 1352 SET_CONFIG_RX_TIMEOUT, 1353 SET_CONFIG_UNKNOWN_ERROR, 1354 }; 1355 1356 /** 1357 * Definition of a set_config reply 1358 */ 1359 struct set_config_reply_control_data { 1360 uint8_t instance; /* DPIA Instance */ 1361 uint8_t status; /* Set Config reply */ 1362 uint16_t pad; /* Alignment */ 1363 }; 1364 1365 /** 1366 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1367 */ 1368 struct dmub_rb_cmd_dp_set_config_reply { 1369 struct dmub_cmd_header header; 1370 struct set_config_reply_control_data set_config_reply_control; 1371 }; 1372 1373 /* 1374 * Command IDs should be treated as stable ABI. 1375 * Do not reuse or modify IDs. 1376 */ 1377 1378 /** 1379 * PSR command sub-types. 1380 */ 1381 enum dmub_cmd_psr_type { 1382 /** 1383 * Set PSR version support. 1384 */ 1385 DMUB_CMD__PSR_SET_VERSION = 0, 1386 /** 1387 * Copy driver-calculated parameters to PSR state. 1388 */ 1389 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1390 /** 1391 * Enable PSR. 1392 */ 1393 DMUB_CMD__PSR_ENABLE = 2, 1394 1395 /** 1396 * Disable PSR. 1397 */ 1398 DMUB_CMD__PSR_DISABLE = 3, 1399 1400 /** 1401 * Set PSR level. 1402 * PSR level is a 16-bit value dicated by driver that 1403 * will enable/disable different functionality. 1404 */ 1405 DMUB_CMD__PSR_SET_LEVEL = 4, 1406 1407 /** 1408 * Forces PSR enabled until an explicit PSR disable call. 1409 */ 1410 DMUB_CMD__PSR_FORCE_STATIC = 5, 1411 /** 1412 * Set PSR power option 1413 */ 1414 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1415 }; 1416 1417 /** 1418 * PSR versions. 1419 */ 1420 enum psr_version { 1421 /** 1422 * PSR version 1. 1423 */ 1424 PSR_VERSION_1 = 0, 1425 /** 1426 * PSR not supported. 1427 */ 1428 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1429 }; 1430 1431 /** 1432 * enum dmub_cmd_mall_type - MALL commands 1433 */ 1434 enum dmub_cmd_mall_type { 1435 /** 1436 * Allows display refresh from MALL. 1437 */ 1438 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1439 /** 1440 * Disallows display refresh from MALL. 1441 */ 1442 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1443 /** 1444 * Cursor copy for MALL. 1445 */ 1446 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1447 /** 1448 * Controls DF requests. 1449 */ 1450 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1451 }; 1452 1453 /** 1454 * PHY Link rate for DP. 1455 */ 1456 enum phy_link_rate { 1457 /** 1458 * not supported. 1459 */ 1460 PHY_RATE_UNKNOWN = 0, 1461 /** 1462 * Rate_1 (RBR) - 1.62 Gbps/Lane 1463 */ 1464 PHY_RATE_162 = 1, 1465 /** 1466 * Rate_2 - 2.16 Gbps/Lane 1467 */ 1468 PHY_RATE_216 = 2, 1469 /** 1470 * Rate_3 - 2.43 Gbps/Lane 1471 */ 1472 PHY_RATE_243 = 3, 1473 /** 1474 * Rate_4 (HBR) - 2.70 Gbps/Lane 1475 */ 1476 PHY_RATE_270 = 4, 1477 /** 1478 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1479 */ 1480 PHY_RATE_324 = 5, 1481 /** 1482 * Rate_6 - 4.32 Gbps/Lane 1483 */ 1484 PHY_RATE_432 = 6, 1485 /** 1486 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1487 */ 1488 PHY_RATE_540 = 7, 1489 /** 1490 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1491 */ 1492 PHY_RATE_810 = 8, 1493 /** 1494 * UHBR10 - 10.0 Gbps/Lane 1495 */ 1496 PHY_RATE_1000 = 9, 1497 /** 1498 * UHBR13.5 - 13.5 Gbps/Lane 1499 */ 1500 PHY_RATE_1350 = 10, 1501 /** 1502 * UHBR10 - 20.0 Gbps/Lane 1503 */ 1504 PHY_RATE_2000 = 11, 1505 }; 1506 1507 /** 1508 * enum dmub_phy_fsm_state - PHY FSM states. 1509 * PHY FSM state to transit to during PSR enable/disable. 1510 */ 1511 enum dmub_phy_fsm_state { 1512 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1513 DMUB_PHY_FSM_RESET, 1514 DMUB_PHY_FSM_RESET_RELEASED, 1515 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1516 DMUB_PHY_FSM_INITIALIZED, 1517 DMUB_PHY_FSM_CALIBRATED, 1518 DMUB_PHY_FSM_CALIBRATED_LP, 1519 DMUB_PHY_FSM_CALIBRATED_PG, 1520 DMUB_PHY_FSM_POWER_DOWN, 1521 DMUB_PHY_FSM_PLL_EN, 1522 DMUB_PHY_FSM_TX_EN, 1523 DMUB_PHY_FSM_FAST_LP, 1524 }; 1525 1526 1527 1528 /** 1529 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1530 */ 1531 struct dmub_cmd_psr_copy_settings_data { 1532 /** 1533 * Flags that can be set by driver to change some PSR behaviour. 1534 */ 1535 union dmub_psr_debug_flags debug; 1536 /** 1537 * 16-bit value dicated by driver that will enable/disable different functionality. 1538 */ 1539 uint16_t psr_level; 1540 /** 1541 * DPP HW instance. 1542 */ 1543 uint8_t dpp_inst; 1544 /** 1545 * MPCC HW instance. 1546 * Not used in dmub fw, 1547 * dmub fw will get active opp by reading odm registers. 1548 */ 1549 uint8_t mpcc_inst; 1550 /** 1551 * OPP HW instance. 1552 * Not used in dmub fw, 1553 * dmub fw will get active opp by reading odm registers. 1554 */ 1555 uint8_t opp_inst; 1556 /** 1557 * OTG HW instance. 1558 */ 1559 uint8_t otg_inst; 1560 /** 1561 * DIG FE HW instance. 1562 */ 1563 uint8_t digfe_inst; 1564 /** 1565 * DIG BE HW instance. 1566 */ 1567 uint8_t digbe_inst; 1568 /** 1569 * DP PHY HW instance. 1570 */ 1571 uint8_t dpphy_inst; 1572 /** 1573 * AUX HW instance. 1574 */ 1575 uint8_t aux_inst; 1576 /** 1577 * Determines if SMU optimzations are enabled/disabled. 1578 */ 1579 uint8_t smu_optimizations_en; 1580 /** 1581 * Unused. 1582 * TODO: Remove. 1583 */ 1584 uint8_t frame_delay; 1585 /** 1586 * If RFB setup time is greater than the total VBLANK time, 1587 * it is not possible for the sink to capture the video frame 1588 * in the same frame the SDP is sent. In this case, 1589 * the frame capture indication bit should be set and an extra 1590 * static frame should be transmitted to the sink. 1591 */ 1592 uint8_t frame_cap_ind; 1593 /** 1594 * Explicit padding to 4 byte boundary. 1595 */ 1596 uint8_t pad[2]; 1597 /** 1598 * Multi-display optimizations are implemented on certain ASICs. 1599 */ 1600 uint8_t multi_disp_optimizations_en; 1601 /** 1602 * The last possible line SDP may be transmitted without violating 1603 * the RFB setup time or entering the active video frame. 1604 */ 1605 uint16_t init_sdp_deadline; 1606 /** 1607 * Explicit padding to 4 byte boundary. 1608 */ 1609 uint16_t pad2; 1610 /** 1611 * Length of each horizontal line in us. 1612 */ 1613 uint32_t line_time_in_us; 1614 /** 1615 * FEC enable status in driver 1616 */ 1617 uint8_t fec_enable_status; 1618 /** 1619 * FEC re-enable delay when PSR exit. 1620 * unit is 100us, range form 0~255(0xFF). 1621 */ 1622 uint8_t fec_enable_delay_in100us; 1623 /** 1624 * PSR control version. 1625 */ 1626 uint8_t cmd_version; 1627 /** 1628 * Panel Instance. 1629 * Panel isntance to identify which psr_state to use 1630 * Currently the support is only for 0 or 1 1631 */ 1632 uint8_t panel_inst; 1633 /* 1634 * DSC enable status in driver 1635 */ 1636 uint8_t dsc_enable_status; 1637 /* 1638 * Use FSM state for PSR power up/down 1639 */ 1640 uint8_t use_phy_fsm; 1641 /** 1642 * Explicit padding to 2 byte boundary. 1643 */ 1644 uint8_t pad3[2]; 1645 }; 1646 1647 /** 1648 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1649 */ 1650 struct dmub_rb_cmd_psr_copy_settings { 1651 /** 1652 * Command header. 1653 */ 1654 struct dmub_cmd_header header; 1655 /** 1656 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1657 */ 1658 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1659 }; 1660 1661 /** 1662 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1663 */ 1664 struct dmub_cmd_psr_set_level_data { 1665 /** 1666 * 16-bit value dicated by driver that will enable/disable different functionality. 1667 */ 1668 uint16_t psr_level; 1669 /** 1670 * PSR control version. 1671 */ 1672 uint8_t cmd_version; 1673 /** 1674 * Panel Instance. 1675 * Panel isntance to identify which psr_state to use 1676 * Currently the support is only for 0 or 1 1677 */ 1678 uint8_t panel_inst; 1679 }; 1680 1681 /** 1682 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1683 */ 1684 struct dmub_rb_cmd_psr_set_level { 1685 /** 1686 * Command header. 1687 */ 1688 struct dmub_cmd_header header; 1689 /** 1690 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1691 */ 1692 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1693 }; 1694 1695 struct dmub_rb_cmd_psr_enable_data { 1696 /** 1697 * PSR control version. 1698 */ 1699 uint8_t cmd_version; 1700 /** 1701 * Panel Instance. 1702 * Panel isntance to identify which psr_state to use 1703 * Currently the support is only for 0 or 1 1704 */ 1705 uint8_t panel_inst; 1706 /** 1707 * Explicit padding to 4 byte boundary. 1708 */ 1709 uint8_t pad[2]; 1710 }; 1711 1712 /** 1713 * Definition of a DMUB_CMD__PSR_ENABLE command. 1714 * PSR enable/disable is controlled using the sub_type. 1715 */ 1716 struct dmub_rb_cmd_psr_enable { 1717 /** 1718 * Command header. 1719 */ 1720 struct dmub_cmd_header header; 1721 1722 struct dmub_rb_cmd_psr_enable_data data; 1723 }; 1724 1725 /** 1726 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1727 */ 1728 struct dmub_cmd_psr_set_version_data { 1729 /** 1730 * PSR version that FW should implement. 1731 */ 1732 enum psr_version version; 1733 /** 1734 * PSR control version. 1735 */ 1736 uint8_t cmd_version; 1737 /** 1738 * Panel Instance. 1739 * Panel isntance to identify which psr_state to use 1740 * Currently the support is only for 0 or 1 1741 */ 1742 uint8_t panel_inst; 1743 /** 1744 * Explicit padding to 4 byte boundary. 1745 */ 1746 uint8_t pad[2]; 1747 }; 1748 1749 /** 1750 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1751 */ 1752 struct dmub_rb_cmd_psr_set_version { 1753 /** 1754 * Command header. 1755 */ 1756 struct dmub_cmd_header header; 1757 /** 1758 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1759 */ 1760 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1761 }; 1762 1763 struct dmub_cmd_psr_force_static_data { 1764 /** 1765 * PSR control version. 1766 */ 1767 uint8_t cmd_version; 1768 /** 1769 * Panel Instance. 1770 * Panel isntance to identify which psr_state to use 1771 * Currently the support is only for 0 or 1 1772 */ 1773 uint8_t panel_inst; 1774 /** 1775 * Phy state to enter. 1776 * Values to use are defined in dmub_phy_fsm_state 1777 */ 1778 uint8_t phy_fsm_state; 1779 /** 1780 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1781 * Set this using enum phy_link_rate. 1782 * This does not support HDMI/DP2 for now. 1783 */ 1784 uint8_t phy_rate; 1785 }; 1786 1787 /** 1788 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1789 */ 1790 struct dmub_rb_cmd_psr_force_static { 1791 /** 1792 * Command header. 1793 */ 1794 struct dmub_cmd_header header; 1795 /** 1796 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1797 */ 1798 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1799 }; 1800 1801 /** 1802 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 1803 */ 1804 struct dmub_cmd_psr_set_power_opt_data { 1805 /** 1806 * PSR control version. 1807 */ 1808 uint8_t cmd_version; 1809 /** 1810 * Panel Instance. 1811 * Panel isntance to identify which psr_state to use 1812 * Currently the support is only for 0 or 1 1813 */ 1814 uint8_t panel_inst; 1815 /** 1816 * Explicit padding to 4 byte boundary. 1817 */ 1818 uint8_t pad[2]; 1819 /** 1820 * PSR power option 1821 */ 1822 uint32_t power_opt; 1823 }; 1824 1825 /** 1826 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1827 */ 1828 struct dmub_rb_cmd_psr_set_power_opt { 1829 /** 1830 * Command header. 1831 */ 1832 struct dmub_cmd_header header; 1833 /** 1834 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1835 */ 1836 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 1837 }; 1838 1839 /** 1840 * Set of HW components that can be locked. 1841 * 1842 * Note: If updating with more HW components, fields 1843 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1844 */ 1845 union dmub_hw_lock_flags { 1846 /** 1847 * Set of HW components that can be locked. 1848 */ 1849 struct { 1850 /** 1851 * Lock/unlock OTG master update lock. 1852 */ 1853 uint8_t lock_pipe : 1; 1854 /** 1855 * Lock/unlock cursor. 1856 */ 1857 uint8_t lock_cursor : 1; 1858 /** 1859 * Lock/unlock global update lock. 1860 */ 1861 uint8_t lock_dig : 1; 1862 /** 1863 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1864 */ 1865 uint8_t triple_buffer_lock : 1; 1866 } bits; 1867 1868 /** 1869 * Union for HW Lock flags. 1870 */ 1871 uint8_t u8All; 1872 }; 1873 1874 /** 1875 * Instances of HW to be locked. 1876 * 1877 * Note: If updating with more HW components, fields 1878 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1879 */ 1880 struct dmub_hw_lock_inst_flags { 1881 /** 1882 * OTG HW instance for OTG master update lock. 1883 */ 1884 uint8_t otg_inst; 1885 /** 1886 * OPP instance for cursor lock. 1887 */ 1888 uint8_t opp_inst; 1889 /** 1890 * OTG HW instance for global update lock. 1891 * TODO: Remove, and re-use otg_inst. 1892 */ 1893 uint8_t dig_inst; 1894 /** 1895 * Explicit pad to 4 byte boundary. 1896 */ 1897 uint8_t pad; 1898 }; 1899 1900 /** 1901 * Clients that can acquire the HW Lock Manager. 1902 * 1903 * Note: If updating with more clients, fields in 1904 * dmub_inbox0_cmd_lock_hw must be updated to match. 1905 */ 1906 enum hw_lock_client { 1907 /** 1908 * Driver is the client of HW Lock Manager. 1909 */ 1910 HW_LOCK_CLIENT_DRIVER = 0, 1911 /** 1912 * Invalid client. 1913 */ 1914 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1915 }; 1916 1917 /** 1918 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1919 */ 1920 struct dmub_cmd_lock_hw_data { 1921 /** 1922 * Specifies the client accessing HW Lock Manager. 1923 */ 1924 enum hw_lock_client client; 1925 /** 1926 * HW instances to be locked. 1927 */ 1928 struct dmub_hw_lock_inst_flags inst_flags; 1929 /** 1930 * Which components to be locked. 1931 */ 1932 union dmub_hw_lock_flags hw_locks; 1933 /** 1934 * Specifies lock/unlock. 1935 */ 1936 uint8_t lock; 1937 /** 1938 * HW can be unlocked separately from releasing the HW Lock Mgr. 1939 * This flag is set if the client wishes to release the object. 1940 */ 1941 uint8_t should_release; 1942 /** 1943 * Explicit padding to 4 byte boundary. 1944 */ 1945 uint8_t pad; 1946 }; 1947 1948 /** 1949 * Definition of a DMUB_CMD__HW_LOCK command. 1950 * Command is used by driver and FW. 1951 */ 1952 struct dmub_rb_cmd_lock_hw { 1953 /** 1954 * Command header. 1955 */ 1956 struct dmub_cmd_header header; 1957 /** 1958 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1959 */ 1960 struct dmub_cmd_lock_hw_data lock_hw_data; 1961 }; 1962 1963 /** 1964 * ABM command sub-types. 1965 */ 1966 enum dmub_cmd_abm_type { 1967 /** 1968 * Initialize parameters for ABM algorithm. 1969 * Data is passed through an indirect buffer. 1970 */ 1971 DMUB_CMD__ABM_INIT_CONFIG = 0, 1972 /** 1973 * Set OTG and panel HW instance. 1974 */ 1975 DMUB_CMD__ABM_SET_PIPE = 1, 1976 /** 1977 * Set user requested backklight level. 1978 */ 1979 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1980 /** 1981 * Set ABM operating/aggression level. 1982 */ 1983 DMUB_CMD__ABM_SET_LEVEL = 3, 1984 /** 1985 * Set ambient light level. 1986 */ 1987 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1988 /** 1989 * Enable/disable fractional duty cycle for backlight PWM. 1990 */ 1991 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1992 1993 /** 1994 * unregister vertical interrupt after steady state is reached 1995 */ 1996 DMUB_CMD__ABM_PAUSE = 6, 1997 }; 1998 1999 /** 2000 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2001 * Requirements: 2002 * - Padded explicitly to 32-bit boundary. 2003 * - Must ensure this structure matches the one on driver-side, 2004 * otherwise it won't be aligned. 2005 */ 2006 struct abm_config_table { 2007 /** 2008 * Gamma curve thresholds, used for crgb conversion. 2009 */ 2010 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2011 /** 2012 * Gamma curve offsets, used for crgb conversion. 2013 */ 2014 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2015 /** 2016 * Gamma curve slopes, used for crgb conversion. 2017 */ 2018 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2019 /** 2020 * Custom backlight curve thresholds. 2021 */ 2022 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2023 /** 2024 * Custom backlight curve offsets. 2025 */ 2026 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2027 /** 2028 * Ambient light thresholds. 2029 */ 2030 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2031 /** 2032 * Minimum programmable backlight. 2033 */ 2034 uint16_t min_abm_backlight; // 122B 2035 /** 2036 * Minimum reduction values. 2037 */ 2038 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2039 /** 2040 * Maximum reduction values. 2041 */ 2042 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2043 /** 2044 * Bright positive gain. 2045 */ 2046 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2047 /** 2048 * Dark negative gain. 2049 */ 2050 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2051 /** 2052 * Hybrid factor. 2053 */ 2054 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2055 /** 2056 * Contrast factor. 2057 */ 2058 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2059 /** 2060 * Deviation gain. 2061 */ 2062 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2063 /** 2064 * Minimum knee. 2065 */ 2066 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2067 /** 2068 * Maximum knee. 2069 */ 2070 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2071 /** 2072 * Unused. 2073 */ 2074 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2075 /** 2076 * Explicit padding to 4 byte boundary. 2077 */ 2078 uint8_t pad3[3]; // 229B 2079 /** 2080 * Backlight ramp reduction. 2081 */ 2082 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2083 /** 2084 * Backlight ramp start. 2085 */ 2086 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2087 }; 2088 2089 /** 2090 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2091 */ 2092 struct dmub_cmd_abm_set_pipe_data { 2093 /** 2094 * OTG HW instance. 2095 */ 2096 uint8_t otg_inst; 2097 2098 /** 2099 * Panel Control HW instance. 2100 */ 2101 uint8_t panel_inst; 2102 2103 /** 2104 * Controls how ABM will interpret a set pipe or set level command. 2105 */ 2106 uint8_t set_pipe_option; 2107 2108 /** 2109 * Unused. 2110 * TODO: Remove. 2111 */ 2112 uint8_t ramping_boundary; 2113 }; 2114 2115 /** 2116 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2117 */ 2118 struct dmub_rb_cmd_abm_set_pipe { 2119 /** 2120 * Command header. 2121 */ 2122 struct dmub_cmd_header header; 2123 2124 /** 2125 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2126 */ 2127 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2128 }; 2129 2130 /** 2131 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2132 */ 2133 struct dmub_cmd_abm_set_backlight_data { 2134 /** 2135 * Number of frames to ramp to backlight user level. 2136 */ 2137 uint32_t frame_ramp; 2138 2139 /** 2140 * Requested backlight level from user. 2141 */ 2142 uint32_t backlight_user_level; 2143 2144 /** 2145 * ABM control version. 2146 */ 2147 uint8_t version; 2148 2149 /** 2150 * Panel Control HW instance mask. 2151 * Bit 0 is Panel Control HW instance 0. 2152 * Bit 1 is Panel Control HW instance 1. 2153 */ 2154 uint8_t panel_mask; 2155 2156 /** 2157 * Explicit padding to 4 byte boundary. 2158 */ 2159 uint8_t pad[2]; 2160 }; 2161 2162 /** 2163 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2164 */ 2165 struct dmub_rb_cmd_abm_set_backlight { 2166 /** 2167 * Command header. 2168 */ 2169 struct dmub_cmd_header header; 2170 2171 /** 2172 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2173 */ 2174 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2175 }; 2176 2177 /** 2178 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2179 */ 2180 struct dmub_cmd_abm_set_level_data { 2181 /** 2182 * Set current ABM operating/aggression level. 2183 */ 2184 uint32_t level; 2185 2186 /** 2187 * ABM control version. 2188 */ 2189 uint8_t version; 2190 2191 /** 2192 * Panel Control HW instance mask. 2193 * Bit 0 is Panel Control HW instance 0. 2194 * Bit 1 is Panel Control HW instance 1. 2195 */ 2196 uint8_t panel_mask; 2197 2198 /** 2199 * Explicit padding to 4 byte boundary. 2200 */ 2201 uint8_t pad[2]; 2202 }; 2203 2204 /** 2205 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2206 */ 2207 struct dmub_rb_cmd_abm_set_level { 2208 /** 2209 * Command header. 2210 */ 2211 struct dmub_cmd_header header; 2212 2213 /** 2214 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2215 */ 2216 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2217 }; 2218 2219 /** 2220 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2221 */ 2222 struct dmub_cmd_abm_set_ambient_level_data { 2223 /** 2224 * Ambient light sensor reading from OS. 2225 */ 2226 uint32_t ambient_lux; 2227 2228 /** 2229 * ABM control version. 2230 */ 2231 uint8_t version; 2232 2233 /** 2234 * Panel Control HW instance mask. 2235 * Bit 0 is Panel Control HW instance 0. 2236 * Bit 1 is Panel Control HW instance 1. 2237 */ 2238 uint8_t panel_mask; 2239 2240 /** 2241 * Explicit padding to 4 byte boundary. 2242 */ 2243 uint8_t pad[2]; 2244 }; 2245 2246 /** 2247 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2248 */ 2249 struct dmub_rb_cmd_abm_set_ambient_level { 2250 /** 2251 * Command header. 2252 */ 2253 struct dmub_cmd_header header; 2254 2255 /** 2256 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2257 */ 2258 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2259 }; 2260 2261 /** 2262 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2263 */ 2264 struct dmub_cmd_abm_set_pwm_frac_data { 2265 /** 2266 * Enable/disable fractional duty cycle for backlight PWM. 2267 * TODO: Convert to uint8_t. 2268 */ 2269 uint32_t fractional_pwm; 2270 2271 /** 2272 * ABM control version. 2273 */ 2274 uint8_t version; 2275 2276 /** 2277 * Panel Control HW instance mask. 2278 * Bit 0 is Panel Control HW instance 0. 2279 * Bit 1 is Panel Control HW instance 1. 2280 */ 2281 uint8_t panel_mask; 2282 2283 /** 2284 * Explicit padding to 4 byte boundary. 2285 */ 2286 uint8_t pad[2]; 2287 }; 2288 2289 /** 2290 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2291 */ 2292 struct dmub_rb_cmd_abm_set_pwm_frac { 2293 /** 2294 * Command header. 2295 */ 2296 struct dmub_cmd_header header; 2297 2298 /** 2299 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2300 */ 2301 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2302 }; 2303 2304 /** 2305 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2306 */ 2307 struct dmub_cmd_abm_init_config_data { 2308 /** 2309 * Location of indirect buffer used to pass init data to ABM. 2310 */ 2311 union dmub_addr src; 2312 2313 /** 2314 * Indirect buffer length. 2315 */ 2316 uint16_t bytes; 2317 2318 2319 /** 2320 * ABM control version. 2321 */ 2322 uint8_t version; 2323 2324 /** 2325 * Panel Control HW instance mask. 2326 * Bit 0 is Panel Control HW instance 0. 2327 * Bit 1 is Panel Control HW instance 1. 2328 */ 2329 uint8_t panel_mask; 2330 2331 /** 2332 * Explicit padding to 4 byte boundary. 2333 */ 2334 uint8_t pad[2]; 2335 }; 2336 2337 /** 2338 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2339 */ 2340 struct dmub_rb_cmd_abm_init_config { 2341 /** 2342 * Command header. 2343 */ 2344 struct dmub_cmd_header header; 2345 2346 /** 2347 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2348 */ 2349 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2350 }; 2351 2352 /** 2353 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2354 */ 2355 2356 struct dmub_cmd_abm_pause_data { 2357 2358 /** 2359 * Panel Control HW instance mask. 2360 * Bit 0 is Panel Control HW instance 0. 2361 * Bit 1 is Panel Control HW instance 1. 2362 */ 2363 uint8_t panel_mask; 2364 2365 /** 2366 * OTG hw instance 2367 */ 2368 uint8_t otg_inst; 2369 2370 /** 2371 * Enable or disable ABM pause 2372 */ 2373 uint8_t enable; 2374 2375 /** 2376 * Explicit padding to 4 byte boundary. 2377 */ 2378 uint8_t pad[1]; 2379 }; 2380 2381 /** 2382 * Definition of a DMUB_CMD__ABM_PAUSE command. 2383 */ 2384 struct dmub_rb_cmd_abm_pause { 2385 /** 2386 * Command header. 2387 */ 2388 struct dmub_cmd_header header; 2389 2390 /** 2391 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2392 */ 2393 struct dmub_cmd_abm_pause_data abm_pause_data; 2394 }; 2395 2396 /** 2397 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2398 */ 2399 struct dmub_cmd_query_feature_caps_data { 2400 /** 2401 * DMUB feature capabilities. 2402 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2403 */ 2404 struct dmub_feature_caps feature_caps; 2405 }; 2406 2407 /** 2408 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2409 */ 2410 struct dmub_rb_cmd_query_feature_caps { 2411 /** 2412 * Command header. 2413 */ 2414 struct dmub_cmd_header header; 2415 /** 2416 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2417 */ 2418 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2419 }; 2420 2421 struct dmub_optc_state { 2422 uint32_t v_total_max; 2423 uint32_t v_total_min; 2424 uint32_t v_total_mid; 2425 uint32_t v_total_mid_frame_num; 2426 uint32_t tg_inst; 2427 uint32_t enable_manual_trigger; 2428 uint32_t clear_force_vsync; 2429 }; 2430 2431 struct dmub_rb_cmd_drr_update { 2432 struct dmub_cmd_header header; 2433 struct dmub_optc_state dmub_optc_state_req; 2434 }; 2435 2436 /** 2437 * enum dmub_cmd_panel_cntl_type - Panel control command. 2438 */ 2439 enum dmub_cmd_panel_cntl_type { 2440 /** 2441 * Initializes embedded panel hardware blocks. 2442 */ 2443 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2444 /** 2445 * Queries backlight info for the embedded panel. 2446 */ 2447 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2448 }; 2449 2450 /** 2451 * struct dmub_cmd_panel_cntl_data - Panel control data. 2452 */ 2453 struct dmub_cmd_panel_cntl_data { 2454 uint32_t inst; /**< panel instance */ 2455 uint32_t current_backlight; /* in/out */ 2456 uint32_t bl_pwm_cntl; /* in/out */ 2457 uint32_t bl_pwm_period_cntl; /* in/out */ 2458 uint32_t bl_pwm_ref_div1; /* in/out */ 2459 uint8_t is_backlight_on : 1; /* in/out */ 2460 uint8_t is_powered_on : 1; /* in/out */ 2461 uint8_t padding[3]; 2462 uint32_t bl_pwm_ref_div2; /* in/out */ 2463 uint8_t reserved[4]; 2464 }; 2465 2466 /** 2467 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2468 */ 2469 struct dmub_rb_cmd_panel_cntl { 2470 struct dmub_cmd_header header; /**< header */ 2471 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2472 }; 2473 2474 /** 2475 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2476 */ 2477 struct dmub_cmd_lvtma_control_data { 2478 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2479 uint8_t reserved_0[3]; /**< For future use */ 2480 uint8_t panel_inst; /**< LVTMA control instance */ 2481 uint8_t reserved_1[3]; /**< For future use */ 2482 }; 2483 2484 /** 2485 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2486 */ 2487 struct dmub_rb_cmd_lvtma_control { 2488 /** 2489 * Command header. 2490 */ 2491 struct dmub_cmd_header header; 2492 /** 2493 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2494 */ 2495 struct dmub_cmd_lvtma_control_data data; 2496 }; 2497 2498 /** 2499 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2500 */ 2501 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 2502 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2503 uint8_t is_usb; /**< is phy is usb */ 2504 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 2505 uint8_t is_dp4; /**< is dp in 4 lane */ 2506 }; 2507 2508 /** 2509 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2510 */ 2511 struct dmub_rb_cmd_transmitter_query_dp_alt { 2512 struct dmub_cmd_header header; /**< header */ 2513 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 2514 }; 2515 2516 /** 2517 * Maximum number of bytes a chunk sent to DMUB for parsing 2518 */ 2519 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2520 2521 /** 2522 * Represent a chunk of CEA blocks sent to DMUB for parsing 2523 */ 2524 struct dmub_cmd_send_edid_cea { 2525 uint16_t offset; /**< offset into the CEA block */ 2526 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2527 uint16_t cea_total_length; /**< total length of the CEA block */ 2528 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2529 uint8_t pad[3]; /**< padding and for future expansion */ 2530 }; 2531 2532 /** 2533 * Result of VSDB parsing from CEA block 2534 */ 2535 struct dmub_cmd_edid_cea_amd_vsdb { 2536 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2537 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2538 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2539 uint16_t min_frame_rate; /**< Maximum frame rate */ 2540 uint16_t max_frame_rate; /**< Minimum frame rate */ 2541 }; 2542 2543 /** 2544 * Result of sending a CEA chunk 2545 */ 2546 struct dmub_cmd_edid_cea_ack { 2547 uint16_t offset; /**< offset of the chunk into the CEA block */ 2548 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2549 uint8_t pad; /**< padding and for future expansion */ 2550 }; 2551 2552 /** 2553 * Specify whether the result is an ACK/NACK or the parsing has finished 2554 */ 2555 enum dmub_cmd_edid_cea_reply_type { 2556 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2557 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2558 }; 2559 2560 /** 2561 * Definition of a DMUB_CMD__EDID_CEA command. 2562 */ 2563 struct dmub_rb_cmd_edid_cea { 2564 struct dmub_cmd_header header; /**< Command header */ 2565 union dmub_cmd_edid_cea_data { 2566 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2567 struct dmub_cmd_edid_cea_output { /**< output with results */ 2568 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2569 union { 2570 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2571 struct dmub_cmd_edid_cea_ack ack; 2572 }; 2573 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2574 } data; /**< Command data */ 2575 2576 }; 2577 2578 /** 2579 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 2580 */ 2581 struct dmub_cmd_cable_id_input { 2582 uint8_t phy_inst; /**< phy inst for cable id data */ 2583 }; 2584 2585 /** 2586 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 2587 */ 2588 struct dmub_cmd_cable_id_output { 2589 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 2590 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 2591 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 2592 uint8_t RESERVED :2; /**< reserved means not defined */ 2593 }; 2594 2595 /** 2596 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 2597 */ 2598 struct dmub_rb_cmd_get_usbc_cable_id { 2599 struct dmub_cmd_header header; /**< Command header */ 2600 /** 2601 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 2602 */ 2603 union dmub_cmd_cable_id_data { 2604 struct dmub_cmd_cable_id_input input; /**< Input */ 2605 struct dmub_cmd_cable_id_output output; /**< Output */ 2606 uint8_t output_raw; /**< Raw data output */ 2607 } data; 2608 }; 2609 2610 /** 2611 * union dmub_rb_cmd - DMUB inbox command. 2612 */ 2613 union dmub_rb_cmd { 2614 struct dmub_rb_cmd_lock_hw lock_hw; 2615 /** 2616 * Elements shared with all commands. 2617 */ 2618 struct dmub_rb_cmd_common cmd_common; 2619 /** 2620 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2621 */ 2622 struct dmub_rb_cmd_read_modify_write read_modify_write; 2623 /** 2624 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2625 */ 2626 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2627 /** 2628 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2629 */ 2630 struct dmub_rb_cmd_burst_write burst_write; 2631 /** 2632 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2633 */ 2634 struct dmub_rb_cmd_reg_wait reg_wait; 2635 /** 2636 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2637 */ 2638 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2639 /** 2640 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2641 */ 2642 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2643 /** 2644 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2645 */ 2646 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2647 /** 2648 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2649 */ 2650 struct dmub_rb_cmd_dpphy_init dpphy_init; 2651 /** 2652 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2653 */ 2654 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2655 /** 2656 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2657 */ 2658 struct dmub_rb_cmd_psr_set_version psr_set_version; 2659 /** 2660 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2661 */ 2662 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2663 /** 2664 * Definition of a DMUB_CMD__PSR_ENABLE command. 2665 */ 2666 struct dmub_rb_cmd_psr_enable psr_enable; 2667 /** 2668 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2669 */ 2670 struct dmub_rb_cmd_psr_set_level psr_set_level; 2671 /** 2672 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2673 */ 2674 struct dmub_rb_cmd_psr_force_static psr_force_static; 2675 /** 2676 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2677 */ 2678 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 2679 /** 2680 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2681 */ 2682 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2683 /** 2684 * Definition of a DMUB_CMD__MALL command. 2685 */ 2686 struct dmub_rb_cmd_mall mall; 2687 /** 2688 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2689 */ 2690 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2691 2692 /** 2693 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2694 */ 2695 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2696 2697 /** 2698 * Definition of DMUB_CMD__PANEL_CNTL commands. 2699 */ 2700 struct dmub_rb_cmd_panel_cntl panel_cntl; 2701 /** 2702 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2703 */ 2704 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2705 2706 /** 2707 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2708 */ 2709 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2710 2711 /** 2712 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2713 */ 2714 struct dmub_rb_cmd_abm_set_level abm_set_level; 2715 2716 /** 2717 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2718 */ 2719 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2720 2721 /** 2722 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2723 */ 2724 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2725 2726 /** 2727 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2728 */ 2729 struct dmub_rb_cmd_abm_init_config abm_init_config; 2730 2731 /** 2732 * Definition of a DMUB_CMD__ABM_PAUSE command. 2733 */ 2734 struct dmub_rb_cmd_abm_pause abm_pause; 2735 2736 /** 2737 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2738 */ 2739 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2740 2741 /** 2742 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2743 */ 2744 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2745 2746 /** 2747 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2748 */ 2749 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2750 struct dmub_rb_cmd_drr_update drr_update; 2751 /** 2752 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2753 */ 2754 struct dmub_rb_cmd_lvtma_control lvtma_control; 2755 /** 2756 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2757 */ 2758 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 2759 /** 2760 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 2761 */ 2762 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 2763 /** 2764 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 2765 */ 2766 struct dmub_rb_cmd_set_config_access set_config_access; 2767 /** 2768 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2769 */ 2770 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 2771 /** 2772 * Definition of a DMUB_CMD__EDID_CEA command. 2773 */ 2774 struct dmub_rb_cmd_edid_cea edid_cea; 2775 /** 2776 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 2777 */ 2778 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 2779 }; 2780 2781 /** 2782 * union dmub_rb_out_cmd - Outbox command 2783 */ 2784 union dmub_rb_out_cmd { 2785 /** 2786 * Parameters common to every command. 2787 */ 2788 struct dmub_rb_cmd_common cmd_common; 2789 /** 2790 * AUX reply command. 2791 */ 2792 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2793 /** 2794 * HPD notify command. 2795 */ 2796 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2797 /** 2798 * SET_CONFIG reply command. 2799 */ 2800 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 2801 }; 2802 #pragma pack(pop) 2803 2804 2805 //============================================================================== 2806 //</DMUB_CMD>=================================================================== 2807 //============================================================================== 2808 //< DMUB_RB>==================================================================== 2809 //============================================================================== 2810 2811 #if defined(__cplusplus) 2812 extern "C" { 2813 #endif 2814 2815 /** 2816 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2817 */ 2818 struct dmub_rb_init_params { 2819 void *ctx; /**< Caller provided context pointer */ 2820 void *base_address; /**< CPU base address for ring's data */ 2821 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2822 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2823 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2824 }; 2825 2826 /** 2827 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2828 */ 2829 struct dmub_rb { 2830 void *base_address; /**< CPU address for the ring's data */ 2831 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2832 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2833 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2834 2835 void *ctx; /**< Caller provided context pointer */ 2836 void *dmub; /**< Pointer to the DMUB interface */ 2837 }; 2838 2839 /** 2840 * @brief Checks if the ringbuffer is empty. 2841 * 2842 * @param rb DMUB Ringbuffer 2843 * @return true if empty 2844 * @return false otherwise 2845 */ 2846 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2847 { 2848 return (rb->wrpt == rb->rptr); 2849 } 2850 2851 /** 2852 * @brief Checks if the ringbuffer is full 2853 * 2854 * @param rb DMUB Ringbuffer 2855 * @return true if full 2856 * @return false otherwise 2857 */ 2858 static inline bool dmub_rb_full(struct dmub_rb *rb) 2859 { 2860 uint32_t data_count; 2861 2862 if (rb->wrpt >= rb->rptr) 2863 data_count = rb->wrpt - rb->rptr; 2864 else 2865 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2866 2867 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2868 } 2869 2870 /** 2871 * @brief Pushes a command into the ringbuffer 2872 * 2873 * @param rb DMUB ringbuffer 2874 * @param cmd The command to push 2875 * @return true if the ringbuffer was not full 2876 * @return false otherwise 2877 */ 2878 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2879 const union dmub_rb_cmd *cmd) 2880 { 2881 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 2882 const uint64_t *src = (const uint64_t *)cmd; 2883 uint8_t i; 2884 2885 if (dmub_rb_full(rb)) 2886 return false; 2887 2888 // copying data 2889 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2890 *dst++ = *src++; 2891 2892 rb->wrpt += DMUB_RB_CMD_SIZE; 2893 2894 if (rb->wrpt >= rb->capacity) 2895 rb->wrpt %= rb->capacity; 2896 2897 return true; 2898 } 2899 2900 /** 2901 * @brief Pushes a command into the DMUB outbox ringbuffer 2902 * 2903 * @param rb DMUB outbox ringbuffer 2904 * @param cmd Outbox command 2905 * @return true if not full 2906 * @return false otherwise 2907 */ 2908 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2909 const union dmub_rb_out_cmd *cmd) 2910 { 2911 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2912 const uint8_t *src = (const uint8_t *)cmd; 2913 2914 if (dmub_rb_full(rb)) 2915 return false; 2916 2917 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2918 2919 rb->wrpt += DMUB_RB_CMD_SIZE; 2920 2921 if (rb->wrpt >= rb->capacity) 2922 rb->wrpt %= rb->capacity; 2923 2924 return true; 2925 } 2926 2927 /** 2928 * @brief Returns the next unprocessed command in the ringbuffer. 2929 * 2930 * @param rb DMUB ringbuffer 2931 * @param cmd The command to return 2932 * @return true if not empty 2933 * @return false otherwise 2934 */ 2935 static inline bool dmub_rb_front(struct dmub_rb *rb, 2936 union dmub_rb_cmd **cmd) 2937 { 2938 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2939 2940 if (dmub_rb_empty(rb)) 2941 return false; 2942 2943 *cmd = (union dmub_rb_cmd *)rb_cmd; 2944 2945 return true; 2946 } 2947 2948 /** 2949 * @brief Determines the next ringbuffer offset. 2950 * 2951 * @param rb DMUB inbox ringbuffer 2952 * @param num_cmds Number of commands 2953 * @param next_rptr The next offset in the ringbuffer 2954 */ 2955 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2956 uint32_t num_cmds, 2957 uint32_t *next_rptr) 2958 { 2959 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2960 2961 if (*next_rptr >= rb->capacity) 2962 *next_rptr %= rb->capacity; 2963 } 2964 2965 /** 2966 * @brief Returns a pointer to a command in the inbox. 2967 * 2968 * @param rb DMUB inbox ringbuffer 2969 * @param cmd The inbox command to return 2970 * @param rptr The ringbuffer offset 2971 * @return true if not empty 2972 * @return false otherwise 2973 */ 2974 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 2975 union dmub_rb_cmd **cmd, 2976 uint32_t rptr) 2977 { 2978 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 2979 2980 if (dmub_rb_empty(rb)) 2981 return false; 2982 2983 *cmd = (union dmub_rb_cmd *)rb_cmd; 2984 2985 return true; 2986 } 2987 2988 /** 2989 * @brief Returns the next unprocessed command in the outbox. 2990 * 2991 * @param rb DMUB outbox ringbuffer 2992 * @param cmd The outbox command to return 2993 * @return true if not empty 2994 * @return false otherwise 2995 */ 2996 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2997 union dmub_rb_out_cmd *cmd) 2998 { 2999 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3000 uint64_t *dst = (uint64_t *)cmd; 3001 uint8_t i; 3002 3003 if (dmub_rb_empty(rb)) 3004 return false; 3005 3006 // copying data 3007 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3008 *dst++ = *src++; 3009 3010 return true; 3011 } 3012 3013 /** 3014 * @brief Removes the front entry in the ringbuffer. 3015 * 3016 * @param rb DMUB ringbuffer 3017 * @return true if the command was removed 3018 * @return false if there were no commands 3019 */ 3020 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3021 { 3022 if (dmub_rb_empty(rb)) 3023 return false; 3024 3025 rb->rptr += DMUB_RB_CMD_SIZE; 3026 3027 if (rb->rptr >= rb->capacity) 3028 rb->rptr %= rb->capacity; 3029 3030 return true; 3031 } 3032 3033 /** 3034 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3035 * 3036 * Avoids a race condition where DMCUB accesses memory while 3037 * there are still writes in flight to framebuffer. 3038 * 3039 * @param rb DMUB ringbuffer 3040 */ 3041 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3042 { 3043 uint32_t rptr = rb->rptr; 3044 uint32_t wptr = rb->wrpt; 3045 3046 while (rptr != wptr) { 3047 uint64_t volatile *data = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rptr); 3048 //uint64_t volatile *p = (uint64_t volatile *)data; 3049 uint64_t temp; 3050 uint8_t i; 3051 3052 /* Don't remove this. 3053 * The contents need to actually be read from the ring buffer 3054 * for this function to be effective. 3055 */ 3056 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3057 temp = *data++; 3058 3059 rptr += DMUB_RB_CMD_SIZE; 3060 if (rptr >= rb->capacity) 3061 rptr %= rb->capacity; 3062 } 3063 } 3064 3065 /** 3066 * @brief Initializes a DMCUB ringbuffer 3067 * 3068 * @param rb DMUB ringbuffer 3069 * @param init_params initial configuration for the ringbuffer 3070 */ 3071 static inline void dmub_rb_init(struct dmub_rb *rb, 3072 struct dmub_rb_init_params *init_params) 3073 { 3074 rb->base_address = init_params->base_address; 3075 rb->capacity = init_params->capacity; 3076 rb->rptr = init_params->read_ptr; 3077 rb->wrpt = init_params->write_ptr; 3078 } 3079 3080 /** 3081 * @brief Copies output data from in/out commands into the given command. 3082 * 3083 * @param rb DMUB ringbuffer 3084 * @param cmd Command to copy data into 3085 */ 3086 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3087 union dmub_rb_cmd *cmd) 3088 { 3089 // Copy rb entry back into command 3090 uint8_t *rd_ptr = (rb->rptr == 0) ? 3091 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3092 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3093 3094 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3095 } 3096 3097 #if defined(__cplusplus) 3098 } 3099 #endif 3100 3101 //============================================================================== 3102 //</DMUB_RB>==================================================================== 3103 //============================================================================== 3104 3105 #endif /* _DMUB_CMD_H_ */ 3106