1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 #include <stdarg.h> 43 44 #include "atomfirmware.h" 45 46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 47 48 /* Firmware versioning. */ 49 #ifdef DMUB_EXPOSE_VERSION 50 #define DMUB_FW_VERSION_GIT_HASH 0x2fe298ec9 51 #define DMUB_FW_VERSION_MAJOR 0 52 #define DMUB_FW_VERSION_MINOR 0 53 #define DMUB_FW_VERSION_REVISION 72 54 #define DMUB_FW_VERSION_TEST 0 55 #define DMUB_FW_VERSION_VBIOS 0 56 #define DMUB_FW_VERSION_HOTFIX 0 57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 62 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 63 64 #endif 65 66 //<DMUB_TYPES>================================================================== 67 /* Basic type definitions. */ 68 69 #define __forceinline inline 70 71 /** 72 * Flag from driver to indicate that ABM should be disabled gradually 73 * by slowly reversing all backlight programming and pixel compensation. 74 */ 75 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 76 77 /** 78 * Flag from driver to indicate that ABM should be disabled immediately 79 * and undo all backlight programming and pixel compensation. 80 */ 81 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 82 83 /** 84 * Flag from driver to indicate that ABM should be disabled immediately 85 * and keep the current backlight programming and pixel compensation. 86 */ 87 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 88 89 /** 90 * Flag from driver to set the current ABM pipe index or ABM operating level. 91 */ 92 #define SET_ABM_PIPE_NORMAL 1 93 94 /** 95 * Number of ambient light levels in ABM algorithm. 96 */ 97 #define NUM_AMBI_LEVEL 5 98 99 /** 100 * Number of operating/aggression levels in ABM algorithm. 101 */ 102 #define NUM_AGGR_LEVEL 4 103 104 /** 105 * Number of segments in the gamma curve. 106 */ 107 #define NUM_POWER_FN_SEGS 8 108 109 /** 110 * Number of segments in the backlight curve. 111 */ 112 #define NUM_BL_CURVE_SEGS 16 113 114 /* Maximum number of streams on any ASIC. */ 115 #define DMUB_MAX_STREAMS 6 116 117 /* Maximum number of planes on any ASIC. */ 118 #define DMUB_MAX_PLANES 6 119 120 /* Trace buffer offset for entry */ 121 #define TRACE_BUFFER_ENTRY_OFFSET 16 122 123 /** 124 * 125 * PSR control version legacy 126 */ 127 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 128 /** 129 * PSR control version with multi edp support 130 */ 131 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 132 133 134 /** 135 * ABM control version legacy 136 */ 137 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 138 139 /** 140 * ABM control version with multi edp support 141 */ 142 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 143 144 /** 145 * Physical framebuffer address location, 64-bit. 146 */ 147 #ifndef PHYSICAL_ADDRESS_LOC 148 #define PHYSICAL_ADDRESS_LOC union large_integer 149 #endif 150 151 /** 152 * OS/FW agnostic memcpy 153 */ 154 #ifndef dmub_memcpy 155 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 156 #endif 157 158 /** 159 * OS/FW agnostic memset 160 */ 161 #ifndef dmub_memset 162 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 163 #endif 164 165 #if defined(__cplusplus) 166 extern "C" { 167 #endif 168 169 /** 170 * OS/FW agnostic udelay 171 */ 172 #ifndef dmub_udelay 173 #define dmub_udelay(microseconds) udelay(microseconds) 174 #endif 175 176 /** 177 * Number of nanoseconds per DMUB tick. 178 * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default. 179 * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true. 180 */ 181 #define NS_PER_DMUB_TICK 10 182 183 /** 184 * union dmub_addr - DMUB physical/virtual 64-bit address. 185 */ 186 union dmub_addr { 187 struct { 188 uint32_t low_part; /**< Lower 32 bits */ 189 uint32_t high_part; /**< Upper 32 bits */ 190 } u; /*<< Low/high bit access */ 191 uint64_t quad_part; /*<< 64 bit address */ 192 }; 193 194 /** 195 * Flags that can be set by driver to change some PSR behaviour. 196 */ 197 union dmub_psr_debug_flags { 198 /** 199 * Debug flags. 200 */ 201 struct { 202 /** 203 * Enable visual confirm in FW. 204 */ 205 uint32_t visual_confirm : 1; 206 /** 207 * Use HW Lock Mgr object to do HW locking in FW. 208 */ 209 uint32_t use_hw_lock_mgr : 1; 210 211 /** 212 * Unused. 213 * TODO: Remove. 214 */ 215 uint32_t log_line_nums : 1; 216 } bitfields; 217 218 /** 219 * Union for debug flags. 220 */ 221 uint32_t u32All; 222 }; 223 224 /** 225 * DMUB feature capabilities. 226 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 227 */ 228 struct dmub_feature_caps { 229 /** 230 * Max PSR version supported by FW. 231 */ 232 uint8_t psr; 233 uint8_t reserved[7]; 234 }; 235 236 #if defined(__cplusplus) 237 } 238 #endif 239 240 //============================================================================== 241 //</DMUB_TYPES>================================================================= 242 //============================================================================== 243 //< DMUB_META>================================================================== 244 //============================================================================== 245 #pragma pack(push, 1) 246 247 /* Magic value for identifying dmub_fw_meta_info */ 248 #define DMUB_FW_META_MAGIC 0x444D5542 249 250 /* Offset from the end of the file to the dmub_fw_meta_info */ 251 #define DMUB_FW_META_OFFSET 0x24 252 253 /** 254 * struct dmub_fw_meta_info - metadata associated with fw binary 255 * 256 * NOTE: This should be considered a stable API. Fields should 257 * not be repurposed or reordered. New fields should be 258 * added instead to extend the structure. 259 * 260 * @magic_value: magic value identifying DMUB firmware meta info 261 * @fw_region_size: size of the firmware state region 262 * @trace_buffer_size: size of the tracebuffer region 263 * @fw_version: the firmware version information 264 * @dal_fw: 1 if the firmware is DAL 265 */ 266 struct dmub_fw_meta_info { 267 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 268 uint32_t fw_region_size; /**< size of the firmware state region */ 269 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 270 uint32_t fw_version; /**< the firmware version information */ 271 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 272 uint8_t reserved[3]; /**< padding bits */ 273 }; 274 275 /** 276 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 277 */ 278 union dmub_fw_meta { 279 struct dmub_fw_meta_info info; /**< metadata info */ 280 uint8_t reserved[64]; /**< padding bits */ 281 }; 282 283 #pragma pack(pop) 284 285 //============================================================================== 286 //< DMUB Trace Buffer>================================================================ 287 //============================================================================== 288 /** 289 * dmub_trace_code_t - firmware trace code, 32-bits 290 */ 291 typedef uint32_t dmub_trace_code_t; 292 293 /** 294 * struct dmcub_trace_buf_entry - Firmware trace entry 295 */ 296 struct dmcub_trace_buf_entry { 297 dmub_trace_code_t trace_code; /**< trace code for the event */ 298 uint32_t tick_count; /**< the tick count at time of trace */ 299 uint32_t param0; /**< trace defined parameter 0 */ 300 uint32_t param1; /**< trace defined parameter 1 */ 301 }; 302 303 //============================================================================== 304 //< DMUB_STATUS>================================================================ 305 //============================================================================== 306 307 /** 308 * DMCUB scratch registers can be used to determine firmware status. 309 * Current scratch register usage is as follows: 310 * 311 * SCRATCH0: FW Boot Status register 312 * SCRATCH5: LVTMA Status Register 313 * SCRATCH15: FW Boot Options register 314 */ 315 316 /** 317 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 318 */ 319 union dmub_fw_boot_status { 320 struct { 321 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 322 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 323 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 324 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 325 } bits; /**< status bits */ 326 uint32_t all; /**< 32-bit access to status bits */ 327 }; 328 329 /** 330 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 331 */ 332 enum dmub_fw_boot_status_bit { 333 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 334 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 335 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 336 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 337 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 338 }; 339 340 /* Register bit definition for SCRATCH5 */ 341 union dmub_lvtma_status { 342 struct { 343 uint32_t psp_ok : 1; 344 uint32_t edp_on : 1; 345 uint32_t reserved : 30; 346 } bits; 347 uint32_t all; 348 }; 349 350 enum dmub_lvtma_status_bit { 351 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 352 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 353 }; 354 355 /** 356 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 357 */ 358 union dmub_fw_boot_options { 359 struct { 360 uint32_t pemu_env : 1; /**< 1 if PEMU */ 361 uint32_t fpga_env : 1; /**< 1 if FPGA */ 362 uint32_t optimized_init : 1; /**< 1 if optimized init */ 363 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 364 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 365 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 366 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 367 uint32_t reserved2: 1; /**< reserved for an unreleased feature */ 368 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 369 uint32_t reserved : 23; /**< reserved */ 370 } bits; /**< boot bits */ 371 uint32_t all; /**< 32-bit access to bits */ 372 }; 373 374 enum dmub_fw_boot_options_bit { 375 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 376 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 377 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 378 }; 379 380 //============================================================================== 381 //</DMUB_STATUS>================================================================ 382 //============================================================================== 383 //< DMUB_VBIOS>================================================================= 384 //============================================================================== 385 386 /* 387 * enum dmub_cmd_vbios_type - VBIOS commands. 388 * 389 * Command IDs should be treated as stable ABI. 390 * Do not reuse or modify IDs. 391 */ 392 enum dmub_cmd_vbios_type { 393 /** 394 * Configures the DIG encoder. 395 */ 396 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 397 /** 398 * Controls the PHY. 399 */ 400 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 401 /** 402 * Sets the pixel clock/symbol clock. 403 */ 404 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 405 /** 406 * Enables or disables power gating. 407 */ 408 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 409 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 410 }; 411 412 //============================================================================== 413 //</DMUB_VBIOS>================================================================= 414 //============================================================================== 415 //< DMUB_GPINT>================================================================= 416 //============================================================================== 417 418 /** 419 * The shifts and masks below may alternatively be used to format and read 420 * the command register bits. 421 */ 422 423 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 424 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 425 426 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 427 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 428 429 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 430 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 431 432 /** 433 * Command responses. 434 */ 435 436 /** 437 * Return response for DMUB_GPINT__STOP_FW command. 438 */ 439 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 440 441 /** 442 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 443 */ 444 union dmub_gpint_data_register { 445 struct { 446 uint32_t param : 16; /**< 16-bit parameter */ 447 uint32_t command_code : 12; /**< GPINT command */ 448 uint32_t status : 4; /**< Command status bit */ 449 } bits; /**< GPINT bit access */ 450 uint32_t all; /**< GPINT 32-bit access */ 451 }; 452 453 /* 454 * enum dmub_gpint_command - GPINT command to DMCUB FW 455 * 456 * Command IDs should be treated as stable ABI. 457 * Do not reuse or modify IDs. 458 */ 459 enum dmub_gpint_command { 460 /** 461 * Invalid command, ignored. 462 */ 463 DMUB_GPINT__INVALID_COMMAND = 0, 464 /** 465 * DESC: Queries the firmware version. 466 * RETURN: Firmware version. 467 */ 468 DMUB_GPINT__GET_FW_VERSION = 1, 469 /** 470 * DESC: Halts the firmware. 471 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 472 */ 473 DMUB_GPINT__STOP_FW = 2, 474 /** 475 * DESC: Get PSR state from FW. 476 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 477 */ 478 DMUB_GPINT__GET_PSR_STATE = 7, 479 /** 480 * DESC: Notifies DMCUB of the currently active streams. 481 * ARGS: Stream mask, 1 bit per active stream index. 482 */ 483 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 484 /** 485 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 486 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 487 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 488 * RETURN: PSR residency in milli-percent. 489 */ 490 DMUB_GPINT__PSR_RESIDENCY = 9, 491 }; 492 493 /** 494 * INBOX0 generic command definition 495 */ 496 union dmub_inbox0_cmd_common { 497 struct { 498 uint32_t command_code: 8; /**< INBOX0 command code */ 499 uint32_t param: 24; /**< 24-bit parameter */ 500 } bits; 501 uint32_t all; 502 }; 503 504 /** 505 * INBOX0 hw_lock command definition 506 */ 507 union dmub_inbox0_cmd_lock_hw { 508 struct { 509 uint32_t command_code: 8; 510 511 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 512 uint32_t hw_lock_client: 1; 513 514 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 515 uint32_t otg_inst: 3; 516 uint32_t opp_inst: 3; 517 uint32_t dig_inst: 3; 518 519 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 520 uint32_t lock_pipe: 1; 521 uint32_t lock_cursor: 1; 522 uint32_t lock_dig: 1; 523 uint32_t triple_buffer_lock: 1; 524 525 uint32_t lock: 1; /**< Lock */ 526 uint32_t should_release: 1; /**< Release */ 527 uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ 528 } bits; 529 uint32_t all; 530 }; 531 532 union dmub_inbox0_data_register { 533 union dmub_inbox0_cmd_common inbox0_cmd_common; 534 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 535 }; 536 537 enum dmub_inbox0_command { 538 /** 539 * DESC: Invalid command, ignored. 540 */ 541 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 542 /** 543 * DESC: Notification to acquire/release HW lock 544 * ARGS: 545 */ 546 DMUB_INBOX0_CMD__HW_LOCK = 1, 547 }; 548 //============================================================================== 549 //</DMUB_GPINT>================================================================= 550 //============================================================================== 551 //< DMUB_CMD>=================================================================== 552 //============================================================================== 553 554 /** 555 * Size in bytes of each DMUB command. 556 */ 557 #define DMUB_RB_CMD_SIZE 64 558 559 /** 560 * Maximum number of items in the DMUB ringbuffer. 561 */ 562 #define DMUB_RB_MAX_ENTRY 128 563 564 /** 565 * Ringbuffer size in bytes. 566 */ 567 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 568 569 /** 570 * REG_SET mask for reg offload. 571 */ 572 #define REG_SET_MASK 0xFFFF 573 574 /* 575 * enum dmub_cmd_type - DMUB inbox command. 576 * 577 * Command IDs should be treated as stable ABI. 578 * Do not reuse or modify IDs. 579 */ 580 enum dmub_cmd_type { 581 /** 582 * Invalid command. 583 */ 584 DMUB_CMD__NULL = 0, 585 /** 586 * Read modify write register sequence offload. 587 */ 588 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 589 /** 590 * Field update register sequence offload. 591 */ 592 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 593 /** 594 * Burst write sequence offload. 595 */ 596 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 597 /** 598 * Reg wait sequence offload. 599 */ 600 DMUB_CMD__REG_REG_WAIT = 4, 601 /** 602 * Workaround to avoid HUBP underflow during NV12 playback. 603 */ 604 DMUB_CMD__PLAT_54186_WA = 5, 605 /** 606 * Command type used to query FW feature caps. 607 */ 608 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 609 /** 610 * Command type used for all PSR commands. 611 */ 612 DMUB_CMD__PSR = 64, 613 /** 614 * Command type used for all MALL commands. 615 */ 616 DMUB_CMD__MALL = 65, 617 /** 618 * Command type used for all ABM commands. 619 */ 620 DMUB_CMD__ABM = 66, 621 /** 622 * Command type used for HW locking in FW. 623 */ 624 DMUB_CMD__HW_LOCK = 69, 625 /** 626 * Command type used to access DP AUX. 627 */ 628 DMUB_CMD__DP_AUX_ACCESS = 70, 629 /** 630 * Command type used for OUTBOX1 notification enable 631 */ 632 DMUB_CMD__OUTBOX1_ENABLE = 71, 633 /** 634 * Command type used for all idle optimization commands. 635 */ 636 DMUB_CMD__IDLE_OPT = 72, 637 /** 638 * Command type used for all clock manager commands. 639 */ 640 DMUB_CMD__CLK_MGR = 73, 641 /** 642 * Command type used for all panel control commands. 643 */ 644 DMUB_CMD__PANEL_CNTL = 74, 645 /** 646 * Command type used for EDID CEA parsing 647 */ 648 DMUB_CMD__EDID_CEA = 79, 649 /** 650 * Command type used for all VBIOS interface commands. 651 */ 652 DMUB_CMD__VBIOS = 128, 653 }; 654 655 /** 656 * enum dmub_out_cmd_type - DMUB outbox commands. 657 */ 658 enum dmub_out_cmd_type { 659 /** 660 * Invalid outbox command, ignored. 661 */ 662 DMUB_OUT_CMD__NULL = 0, 663 /** 664 * Command type used for DP AUX Reply data notification 665 */ 666 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 667 }; 668 669 #pragma pack(push, 1) 670 671 /** 672 * struct dmub_cmd_header - Common command header fields. 673 */ 674 struct dmub_cmd_header { 675 unsigned int type : 8; /**< command type */ 676 unsigned int sub_type : 8; /**< command sub type */ 677 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 678 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 679 unsigned int reserved0 : 6; /**< reserved bits */ 680 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 681 unsigned int reserved1 : 2; /**< reserved bits */ 682 }; 683 684 /* 685 * struct dmub_cmd_read_modify_write_sequence - Read modify write 686 * 687 * 60 payload bytes can hold up to 5 sets of read modify writes, 688 * each take 3 dwords. 689 * 690 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 691 * 692 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 693 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 694 */ 695 struct dmub_cmd_read_modify_write_sequence { 696 uint32_t addr; /**< register address */ 697 uint32_t modify_mask; /**< modify mask */ 698 uint32_t modify_value; /**< modify value */ 699 }; 700 701 /** 702 * Maximum number of ops in read modify write sequence. 703 */ 704 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 705 706 /** 707 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 708 */ 709 struct dmub_rb_cmd_read_modify_write { 710 struct dmub_cmd_header header; /**< command header */ 711 /** 712 * Read modify write sequence. 713 */ 714 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 715 }; 716 717 /* 718 * Update a register with specified masks and values sequeunce 719 * 720 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 721 * 722 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 723 * 724 * 725 * USE CASE: 726 * 1. auto-increment register where additional read would update pointer and produce wrong result 727 * 2. toggle a bit without read in the middle 728 */ 729 730 struct dmub_cmd_reg_field_update_sequence { 731 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 732 uint32_t modify_value; /**< value to update with */ 733 }; 734 735 /** 736 * Maximum number of ops in field update sequence. 737 */ 738 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 739 740 /** 741 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 742 */ 743 struct dmub_rb_cmd_reg_field_update_sequence { 744 struct dmub_cmd_header header; /**< command header */ 745 uint32_t addr; /**< register address */ 746 /** 747 * Field update sequence. 748 */ 749 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 750 }; 751 752 753 /** 754 * Maximum number of burst write values. 755 */ 756 #define DMUB_BURST_WRITE_VALUES__MAX 14 757 758 /* 759 * struct dmub_rb_cmd_burst_write - Burst write 760 * 761 * support use case such as writing out LUTs. 762 * 763 * 60 payload bytes can hold up to 14 values to write to given address 764 * 765 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 766 */ 767 struct dmub_rb_cmd_burst_write { 768 struct dmub_cmd_header header; /**< command header */ 769 uint32_t addr; /**< register start address */ 770 /** 771 * Burst write register values. 772 */ 773 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 774 }; 775 776 /** 777 * struct dmub_rb_cmd_common - Common command header 778 */ 779 struct dmub_rb_cmd_common { 780 struct dmub_cmd_header header; /**< command header */ 781 /** 782 * Padding to RB_CMD_SIZE 783 */ 784 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 785 }; 786 787 /** 788 * struct dmub_cmd_reg_wait_data - Register wait data 789 */ 790 struct dmub_cmd_reg_wait_data { 791 uint32_t addr; /**< Register address */ 792 uint32_t mask; /**< Mask for register bits */ 793 uint32_t condition_field_value; /**< Value to wait for */ 794 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 795 }; 796 797 /** 798 * struct dmub_rb_cmd_reg_wait - Register wait command 799 */ 800 struct dmub_rb_cmd_reg_wait { 801 struct dmub_cmd_header header; /**< Command header */ 802 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 803 }; 804 805 /** 806 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 807 * 808 * Reprograms surface parameters to avoid underflow. 809 */ 810 struct dmub_cmd_PLAT_54186_wa { 811 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 812 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 813 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 814 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 815 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 816 struct { 817 uint8_t hubp_inst : 4; /**< HUBP instance */ 818 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 819 uint8_t immediate :1; /**< Immediate flip */ 820 uint8_t vmid : 4; /**< VMID */ 821 uint8_t grph_stereo : 1; /**< 1 if stereo */ 822 uint32_t reserved : 21; /**< Reserved */ 823 } flip_params; /**< Pageflip parameters */ 824 uint32_t reserved[9]; /**< Reserved bits */ 825 }; 826 827 /** 828 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 829 */ 830 struct dmub_rb_cmd_PLAT_54186_wa { 831 struct dmub_cmd_header header; /**< Command header */ 832 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 833 }; 834 835 /** 836 * struct dmub_rb_cmd_mall - MALL command data. 837 */ 838 struct dmub_rb_cmd_mall { 839 struct dmub_cmd_header header; /**< Common command header */ 840 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 841 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 842 uint32_t tmr_delay; /**< Timer delay */ 843 uint32_t tmr_scale; /**< Timer scale */ 844 uint16_t cursor_width; /**< Cursor width in pixels */ 845 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 846 uint16_t cursor_height; /**< Cursor height in pixels */ 847 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 848 uint8_t debug_bits; /**< Debug bits */ 849 850 uint8_t reserved1; /**< Reserved bits */ 851 uint8_t reserved2; /**< Reserved bits */ 852 }; 853 854 /** 855 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 856 */ 857 enum dmub_cmd_idle_opt_type { 858 /** 859 * DCN hardware restore. 860 */ 861 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 862 }; 863 864 /** 865 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 866 */ 867 struct dmub_rb_cmd_idle_opt_dcn_restore { 868 struct dmub_cmd_header header; /**< header */ 869 }; 870 871 /** 872 * struct dmub_clocks - Clock update notification. 873 */ 874 struct dmub_clocks { 875 uint32_t dispclk_khz; /**< dispclk kHz */ 876 uint32_t dppclk_khz; /**< dppclk kHz */ 877 uint32_t dcfclk_khz; /**< dcfclk kHz */ 878 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 879 }; 880 881 /** 882 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 883 */ 884 enum dmub_cmd_clk_mgr_type { 885 /** 886 * Notify DMCUB of clock update. 887 */ 888 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 889 }; 890 891 /** 892 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 893 */ 894 struct dmub_rb_cmd_clk_mgr_notify_clocks { 895 struct dmub_cmd_header header; /**< header */ 896 struct dmub_clocks clocks; /**< clock data */ 897 }; 898 899 /** 900 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 901 */ 902 struct dmub_cmd_digx_encoder_control_data { 903 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 904 }; 905 906 /** 907 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 908 */ 909 struct dmub_rb_cmd_digx_encoder_control { 910 struct dmub_cmd_header header; /**< header */ 911 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 912 }; 913 914 /** 915 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 916 */ 917 struct dmub_cmd_set_pixel_clock_data { 918 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 919 }; 920 921 /** 922 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 923 */ 924 struct dmub_rb_cmd_set_pixel_clock { 925 struct dmub_cmd_header header; /**< header */ 926 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 927 }; 928 929 /** 930 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 931 */ 932 struct dmub_cmd_enable_disp_power_gating_data { 933 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 934 }; 935 936 /** 937 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 938 */ 939 struct dmub_rb_cmd_enable_disp_power_gating { 940 struct dmub_cmd_header header; /**< header */ 941 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 942 }; 943 944 /** 945 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 946 */ 947 struct dmub_dig_transmitter_control_data_v1_7 { 948 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 949 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 950 union { 951 uint8_t digmode; /**< enum atom_encode_mode_def */ 952 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 953 } mode_laneset; 954 uint8_t lanenum; /**< Number of lanes */ 955 union { 956 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 957 } symclk_units; 958 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 959 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 960 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 961 uint8_t reserved0; /**< For future use */ 962 uint8_t reserved1; /**< For future use */ 963 uint8_t reserved2[3]; /**< For future use */ 964 uint32_t reserved3[11]; /**< For future use */ 965 }; 966 967 /** 968 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 969 */ 970 union dmub_cmd_dig1_transmitter_control_data { 971 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 972 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 973 }; 974 975 /** 976 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 977 */ 978 struct dmub_rb_cmd_dig1_transmitter_control { 979 struct dmub_cmd_header header; /**< header */ 980 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 981 }; 982 983 /** 984 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 985 */ 986 struct dmub_rb_cmd_dpphy_init { 987 struct dmub_cmd_header header; /**< header */ 988 uint8_t reserved[60]; /**< reserved bits */ 989 }; 990 991 /** 992 * enum dp_aux_request_action - DP AUX request command listing. 993 * 994 * 4 AUX request command bits are shifted to high nibble. 995 */ 996 enum dp_aux_request_action { 997 /** I2C-over-AUX write request */ 998 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 999 /** I2C-over-AUX read request */ 1000 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1001 /** I2C-over-AUX write status request */ 1002 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1003 /** I2C-over-AUX write request with MOT=1 */ 1004 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1005 /** I2C-over-AUX read request with MOT=1 */ 1006 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1007 /** I2C-over-AUX write status request with MOT=1 */ 1008 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1009 /** Native AUX write request */ 1010 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1011 /** Native AUX read request */ 1012 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1013 }; 1014 1015 /** 1016 * enum aux_return_code_type - DP AUX process return code listing. 1017 */ 1018 enum aux_return_code_type { 1019 /** AUX process succeeded */ 1020 AUX_RET_SUCCESS = 0, 1021 /** AUX process failed with unknown reason */ 1022 AUX_RET_ERROR_UNKNOWN, 1023 /** AUX process completed with invalid reply */ 1024 AUX_RET_ERROR_INVALID_REPLY, 1025 /** AUX process timed out */ 1026 AUX_RET_ERROR_TIMEOUT, 1027 /** HPD was low during AUX process */ 1028 AUX_RET_ERROR_HPD_DISCON, 1029 /** Failed to acquire AUX engine */ 1030 AUX_RET_ERROR_ENGINE_ACQUIRE, 1031 /** AUX request not supported */ 1032 AUX_RET_ERROR_INVALID_OPERATION, 1033 /** AUX process not available */ 1034 AUX_RET_ERROR_PROTOCOL_ERROR, 1035 }; 1036 1037 /** 1038 * enum aux_channel_type - DP AUX channel type listing. 1039 */ 1040 enum aux_channel_type { 1041 /** AUX thru Legacy DP AUX */ 1042 AUX_CHANNEL_LEGACY_DDC, 1043 /** AUX thru DPIA DP tunneling */ 1044 AUX_CHANNEL_DPIA 1045 }; 1046 1047 /** 1048 * struct aux_transaction_parameters - DP AUX request transaction data 1049 */ 1050 struct aux_transaction_parameters { 1051 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1052 uint8_t action; /**< enum dp_aux_request_action */ 1053 uint8_t length; /**< DP AUX request data length */ 1054 uint8_t reserved; /**< For future use */ 1055 uint32_t address; /**< DP AUX address */ 1056 uint8_t data[16]; /**< DP AUX write data */ 1057 }; 1058 1059 /** 1060 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1061 */ 1062 struct dmub_cmd_dp_aux_control_data { 1063 uint8_t instance; /**< AUX instance or DPIA instance */ 1064 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1065 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1066 uint8_t reserved0; /**< For future use */ 1067 uint16_t timeout; /**< timeout time in us */ 1068 uint16_t reserved1; /**< For future use */ 1069 enum aux_channel_type type; /**< enum aux_channel_type */ 1070 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1071 }; 1072 1073 /** 1074 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1075 */ 1076 struct dmub_rb_cmd_dp_aux_access { 1077 /** 1078 * Command header. 1079 */ 1080 struct dmub_cmd_header header; 1081 /** 1082 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1083 */ 1084 struct dmub_cmd_dp_aux_control_data aux_control; 1085 }; 1086 1087 /** 1088 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1089 */ 1090 struct dmub_rb_cmd_outbox1_enable { 1091 /** 1092 * Command header. 1093 */ 1094 struct dmub_cmd_header header; 1095 /** 1096 * enable: 0x0 -> disable outbox1 notification (default value) 1097 * 0x1 -> enable outbox1 notification 1098 */ 1099 uint32_t enable; 1100 }; 1101 1102 /* DP AUX Reply command - OutBox Cmd */ 1103 /** 1104 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1105 */ 1106 struct aux_reply_data { 1107 /** 1108 * Aux cmd 1109 */ 1110 uint8_t command; 1111 /** 1112 * Aux reply data length (max: 16 bytes) 1113 */ 1114 uint8_t length; 1115 /** 1116 * Alignment only 1117 */ 1118 uint8_t pad[2]; 1119 /** 1120 * Aux reply data 1121 */ 1122 uint8_t data[16]; 1123 }; 1124 1125 /** 1126 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1127 */ 1128 struct aux_reply_control_data { 1129 /** 1130 * Reserved for future use 1131 */ 1132 uint32_t handle; 1133 /** 1134 * Aux Instance 1135 */ 1136 uint8_t instance; 1137 /** 1138 * Aux transaction result: definition in enum aux_return_code_type 1139 */ 1140 uint8_t result; 1141 /** 1142 * Alignment only 1143 */ 1144 uint16_t pad; 1145 }; 1146 1147 /** 1148 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1149 */ 1150 struct dmub_rb_cmd_dp_aux_reply { 1151 /** 1152 * Command header. 1153 */ 1154 struct dmub_cmd_header header; 1155 /** 1156 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1157 */ 1158 struct aux_reply_control_data control; 1159 /** 1160 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1161 */ 1162 struct aux_reply_data reply_data; 1163 }; 1164 1165 /* DP HPD Notify command - OutBox Cmd */ 1166 /** 1167 * DP HPD Type 1168 */ 1169 enum dp_hpd_type { 1170 /** 1171 * Normal DP HPD 1172 */ 1173 DP_HPD = 0, 1174 /** 1175 * DP HPD short pulse 1176 */ 1177 DP_IRQ 1178 }; 1179 1180 /** 1181 * DP HPD Status 1182 */ 1183 enum dp_hpd_status { 1184 /** 1185 * DP_HPD status low 1186 */ 1187 DP_HPD_UNPLUG = 0, 1188 /** 1189 * DP_HPD status high 1190 */ 1191 DP_HPD_PLUG 1192 }; 1193 1194 /** 1195 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1196 */ 1197 struct dp_hpd_data { 1198 /** 1199 * DP HPD instance 1200 */ 1201 uint8_t instance; 1202 /** 1203 * HPD type 1204 */ 1205 uint8_t hpd_type; 1206 /** 1207 * HPD status: only for type: DP_HPD to indicate status 1208 */ 1209 uint8_t hpd_status; 1210 /** 1211 * Alignment only 1212 */ 1213 uint8_t pad; 1214 }; 1215 1216 /** 1217 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1218 */ 1219 struct dmub_rb_cmd_dp_hpd_notify { 1220 /** 1221 * Command header. 1222 */ 1223 struct dmub_cmd_header header; 1224 /** 1225 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1226 */ 1227 struct dp_hpd_data hpd_data; 1228 }; 1229 1230 /* 1231 * Command IDs should be treated as stable ABI. 1232 * Do not reuse or modify IDs. 1233 */ 1234 1235 /** 1236 * PSR command sub-types. 1237 */ 1238 enum dmub_cmd_psr_type { 1239 /** 1240 * Set PSR version support. 1241 */ 1242 DMUB_CMD__PSR_SET_VERSION = 0, 1243 /** 1244 * Copy driver-calculated parameters to PSR state. 1245 */ 1246 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1247 /** 1248 * Enable PSR. 1249 */ 1250 DMUB_CMD__PSR_ENABLE = 2, 1251 1252 /** 1253 * Disable PSR. 1254 */ 1255 DMUB_CMD__PSR_DISABLE = 3, 1256 1257 /** 1258 * Set PSR level. 1259 * PSR level is a 16-bit value dicated by driver that 1260 * will enable/disable different functionality. 1261 */ 1262 DMUB_CMD__PSR_SET_LEVEL = 4, 1263 1264 /** 1265 * Forces PSR enabled until an explicit PSR disable call. 1266 */ 1267 DMUB_CMD__PSR_FORCE_STATIC = 5, 1268 }; 1269 1270 /** 1271 * PSR versions. 1272 */ 1273 enum psr_version { 1274 /** 1275 * PSR version 1. 1276 */ 1277 PSR_VERSION_1 = 0, 1278 /** 1279 * PSR not supported. 1280 */ 1281 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1282 }; 1283 1284 /** 1285 * enum dmub_cmd_mall_type - MALL commands 1286 */ 1287 enum dmub_cmd_mall_type { 1288 /** 1289 * Allows display refresh from MALL. 1290 */ 1291 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1292 /** 1293 * Disallows display refresh from MALL. 1294 */ 1295 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1296 /** 1297 * Cursor copy for MALL. 1298 */ 1299 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1300 /** 1301 * Controls DF requests. 1302 */ 1303 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1304 }; 1305 1306 1307 /** 1308 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1309 */ 1310 struct dmub_cmd_psr_copy_settings_data { 1311 /** 1312 * Flags that can be set by driver to change some PSR behaviour. 1313 */ 1314 union dmub_psr_debug_flags debug; 1315 /** 1316 * 16-bit value dicated by driver that will enable/disable different functionality. 1317 */ 1318 uint16_t psr_level; 1319 /** 1320 * DPP HW instance. 1321 */ 1322 uint8_t dpp_inst; 1323 /** 1324 * MPCC HW instance. 1325 * Not used in dmub fw, 1326 * dmub fw will get active opp by reading odm registers. 1327 */ 1328 uint8_t mpcc_inst; 1329 /** 1330 * OPP HW instance. 1331 * Not used in dmub fw, 1332 * dmub fw will get active opp by reading odm registers. 1333 */ 1334 uint8_t opp_inst; 1335 /** 1336 * OTG HW instance. 1337 */ 1338 uint8_t otg_inst; 1339 /** 1340 * DIG FE HW instance. 1341 */ 1342 uint8_t digfe_inst; 1343 /** 1344 * DIG BE HW instance. 1345 */ 1346 uint8_t digbe_inst; 1347 /** 1348 * DP PHY HW instance. 1349 */ 1350 uint8_t dpphy_inst; 1351 /** 1352 * AUX HW instance. 1353 */ 1354 uint8_t aux_inst; 1355 /** 1356 * Determines if SMU optimzations are enabled/disabled. 1357 */ 1358 uint8_t smu_optimizations_en; 1359 /** 1360 * Unused. 1361 * TODO: Remove. 1362 */ 1363 uint8_t frame_delay; 1364 /** 1365 * If RFB setup time is greater than the total VBLANK time, 1366 * it is not possible for the sink to capture the video frame 1367 * in the same frame the SDP is sent. In this case, 1368 * the frame capture indication bit should be set and an extra 1369 * static frame should be transmitted to the sink. 1370 */ 1371 uint8_t frame_cap_ind; 1372 /** 1373 * Explicit padding to 4 byte boundary. 1374 */ 1375 uint8_t pad[2]; 1376 /** 1377 * Multi-display optimizations are implemented on certain ASICs. 1378 */ 1379 uint8_t multi_disp_optimizations_en; 1380 /** 1381 * The last possible line SDP may be transmitted without violating 1382 * the RFB setup time or entering the active video frame. 1383 */ 1384 uint16_t init_sdp_deadline; 1385 /** 1386 * Explicit padding to 4 byte boundary. 1387 */ 1388 uint16_t pad2; 1389 /** 1390 * Length of each horizontal line in us. 1391 */ 1392 uint32_t line_time_in_us; 1393 /** 1394 * FEC enable status in driver 1395 */ 1396 uint8_t fec_enable_status; 1397 /** 1398 * FEC re-enable delay when PSR exit. 1399 * unit is 100us, range form 0~255(0xFF). 1400 */ 1401 uint8_t fec_enable_delay_in100us; 1402 /** 1403 * PSR control version. 1404 */ 1405 uint8_t cmd_version; 1406 /** 1407 * Panel Instance. 1408 * Panel isntance to identify which psr_state to use 1409 * Currently the support is only for 0 or 1 1410 */ 1411 uint8_t panel_inst; 1412 }; 1413 1414 /** 1415 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1416 */ 1417 struct dmub_rb_cmd_psr_copy_settings { 1418 /** 1419 * Command header. 1420 */ 1421 struct dmub_cmd_header header; 1422 /** 1423 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1424 */ 1425 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1426 }; 1427 1428 /** 1429 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1430 */ 1431 struct dmub_cmd_psr_set_level_data { 1432 /** 1433 * 16-bit value dicated by driver that will enable/disable different functionality. 1434 */ 1435 uint16_t psr_level; 1436 /** 1437 * PSR control version. 1438 */ 1439 uint8_t cmd_version; 1440 /** 1441 * Panel Instance. 1442 * Panel isntance to identify which psr_state to use 1443 * Currently the support is only for 0 or 1 1444 */ 1445 uint8_t panel_inst; 1446 }; 1447 1448 /** 1449 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1450 */ 1451 struct dmub_rb_cmd_psr_set_level { 1452 /** 1453 * Command header. 1454 */ 1455 struct dmub_cmd_header header; 1456 /** 1457 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1458 */ 1459 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1460 }; 1461 1462 struct dmub_rb_cmd_psr_enable_data { 1463 /** 1464 * PSR control version. 1465 */ 1466 uint8_t cmd_version; 1467 /** 1468 * Panel Instance. 1469 * Panel isntance to identify which psr_state to use 1470 * Currently the support is only for 0 or 1 1471 */ 1472 uint8_t panel_inst; 1473 /** 1474 * Explicit padding to 4 byte boundary. 1475 */ 1476 uint8_t pad[2]; 1477 }; 1478 1479 /** 1480 * Definition of a DMUB_CMD__PSR_ENABLE command. 1481 * PSR enable/disable is controlled using the sub_type. 1482 */ 1483 struct dmub_rb_cmd_psr_enable { 1484 /** 1485 * Command header. 1486 */ 1487 struct dmub_cmd_header header; 1488 1489 struct dmub_rb_cmd_psr_enable_data data; 1490 }; 1491 1492 /** 1493 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1494 */ 1495 struct dmub_cmd_psr_set_version_data { 1496 /** 1497 * PSR version that FW should implement. 1498 */ 1499 enum psr_version version; 1500 /** 1501 * PSR control version. 1502 */ 1503 uint8_t cmd_version; 1504 /** 1505 * Panel Instance. 1506 * Panel isntance to identify which psr_state to use 1507 * Currently the support is only for 0 or 1 1508 */ 1509 uint8_t panel_inst; 1510 /** 1511 * Explicit padding to 4 byte boundary. 1512 */ 1513 uint8_t pad[2]; 1514 }; 1515 1516 /** 1517 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1518 */ 1519 struct dmub_rb_cmd_psr_set_version { 1520 /** 1521 * Command header. 1522 */ 1523 struct dmub_cmd_header header; 1524 /** 1525 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1526 */ 1527 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1528 }; 1529 1530 struct dmub_cmd_psr_force_static_data { 1531 /** 1532 * PSR control version. 1533 */ 1534 uint8_t cmd_version; 1535 /** 1536 * Panel Instance. 1537 * Panel isntance to identify which psr_state to use 1538 * Currently the support is only for 0 or 1 1539 */ 1540 uint8_t panel_inst; 1541 /** 1542 * Explicit padding to 4 byte boundary. 1543 */ 1544 uint8_t pad[2]; 1545 }; 1546 1547 /** 1548 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1549 */ 1550 struct dmub_rb_cmd_psr_force_static { 1551 /** 1552 * Command header. 1553 */ 1554 struct dmub_cmd_header header; 1555 /** 1556 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1557 */ 1558 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1559 }; 1560 1561 /** 1562 * Set of HW components that can be locked. 1563 * 1564 * Note: If updating with more HW components, fields 1565 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1566 */ 1567 union dmub_hw_lock_flags { 1568 /** 1569 * Set of HW components that can be locked. 1570 */ 1571 struct { 1572 /** 1573 * Lock/unlock OTG master update lock. 1574 */ 1575 uint8_t lock_pipe : 1; 1576 /** 1577 * Lock/unlock cursor. 1578 */ 1579 uint8_t lock_cursor : 1; 1580 /** 1581 * Lock/unlock global update lock. 1582 */ 1583 uint8_t lock_dig : 1; 1584 /** 1585 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1586 */ 1587 uint8_t triple_buffer_lock : 1; 1588 } bits; 1589 1590 /** 1591 * Union for HW Lock flags. 1592 */ 1593 uint8_t u8All; 1594 }; 1595 1596 /** 1597 * Instances of HW to be locked. 1598 * 1599 * Note: If updating with more HW components, fields 1600 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1601 */ 1602 struct dmub_hw_lock_inst_flags { 1603 /** 1604 * OTG HW instance for OTG master update lock. 1605 */ 1606 uint8_t otg_inst; 1607 /** 1608 * OPP instance for cursor lock. 1609 */ 1610 uint8_t opp_inst; 1611 /** 1612 * OTG HW instance for global update lock. 1613 * TODO: Remove, and re-use otg_inst. 1614 */ 1615 uint8_t dig_inst; 1616 /** 1617 * Explicit pad to 4 byte boundary. 1618 */ 1619 uint8_t pad; 1620 }; 1621 1622 /** 1623 * Clients that can acquire the HW Lock Manager. 1624 * 1625 * Note: If updating with more clients, fields in 1626 * dmub_inbox0_cmd_lock_hw must be updated to match. 1627 */ 1628 enum hw_lock_client { 1629 /** 1630 * Driver is the client of HW Lock Manager. 1631 */ 1632 HW_LOCK_CLIENT_DRIVER = 0, 1633 /** 1634 * Invalid client. 1635 */ 1636 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1637 }; 1638 1639 /** 1640 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1641 */ 1642 struct dmub_cmd_lock_hw_data { 1643 /** 1644 * Specifies the client accessing HW Lock Manager. 1645 */ 1646 enum hw_lock_client client; 1647 /** 1648 * HW instances to be locked. 1649 */ 1650 struct dmub_hw_lock_inst_flags inst_flags; 1651 /** 1652 * Which components to be locked. 1653 */ 1654 union dmub_hw_lock_flags hw_locks; 1655 /** 1656 * Specifies lock/unlock. 1657 */ 1658 uint8_t lock; 1659 /** 1660 * HW can be unlocked separately from releasing the HW Lock Mgr. 1661 * This flag is set if the client wishes to release the object. 1662 */ 1663 uint8_t should_release; 1664 /** 1665 * Explicit padding to 4 byte boundary. 1666 */ 1667 uint8_t pad; 1668 }; 1669 1670 /** 1671 * Definition of a DMUB_CMD__HW_LOCK command. 1672 * Command is used by driver and FW. 1673 */ 1674 struct dmub_rb_cmd_lock_hw { 1675 /** 1676 * Command header. 1677 */ 1678 struct dmub_cmd_header header; 1679 /** 1680 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1681 */ 1682 struct dmub_cmd_lock_hw_data lock_hw_data; 1683 }; 1684 1685 /** 1686 * ABM command sub-types. 1687 */ 1688 enum dmub_cmd_abm_type { 1689 /** 1690 * Initialize parameters for ABM algorithm. 1691 * Data is passed through an indirect buffer. 1692 */ 1693 DMUB_CMD__ABM_INIT_CONFIG = 0, 1694 /** 1695 * Set OTG and panel HW instance. 1696 */ 1697 DMUB_CMD__ABM_SET_PIPE = 1, 1698 /** 1699 * Set user requested backklight level. 1700 */ 1701 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1702 /** 1703 * Set ABM operating/aggression level. 1704 */ 1705 DMUB_CMD__ABM_SET_LEVEL = 3, 1706 /** 1707 * Set ambient light level. 1708 */ 1709 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1710 /** 1711 * Enable/disable fractional duty cycle for backlight PWM. 1712 */ 1713 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1714 }; 1715 1716 /** 1717 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1718 * Requirements: 1719 * - Padded explicitly to 32-bit boundary. 1720 * - Must ensure this structure matches the one on driver-side, 1721 * otherwise it won't be aligned. 1722 */ 1723 struct abm_config_table { 1724 /** 1725 * Gamma curve thresholds, used for crgb conversion. 1726 */ 1727 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1728 /** 1729 * Gamma curve offsets, used for crgb conversion. 1730 */ 1731 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1732 /** 1733 * Gamma curve slopes, used for crgb conversion. 1734 */ 1735 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1736 /** 1737 * Custom backlight curve thresholds. 1738 */ 1739 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 1740 /** 1741 * Custom backlight curve offsets. 1742 */ 1743 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 1744 /** 1745 * Ambient light thresholds. 1746 */ 1747 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 1748 /** 1749 * Minimum programmable backlight. 1750 */ 1751 uint16_t min_abm_backlight; // 122B 1752 /** 1753 * Minimum reduction values. 1754 */ 1755 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 1756 /** 1757 * Maximum reduction values. 1758 */ 1759 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 1760 /** 1761 * Bright positive gain. 1762 */ 1763 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 1764 /** 1765 * Dark negative gain. 1766 */ 1767 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 1768 /** 1769 * Hybrid factor. 1770 */ 1771 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 1772 /** 1773 * Contrast factor. 1774 */ 1775 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 1776 /** 1777 * Deviation gain. 1778 */ 1779 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 1780 /** 1781 * Minimum knee. 1782 */ 1783 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 1784 /** 1785 * Maximum knee. 1786 */ 1787 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 1788 /** 1789 * Unused. 1790 */ 1791 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 1792 /** 1793 * Explicit padding to 4 byte boundary. 1794 */ 1795 uint8_t pad3[3]; // 229B 1796 /** 1797 * Backlight ramp reduction. 1798 */ 1799 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 1800 /** 1801 * Backlight ramp start. 1802 */ 1803 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 1804 }; 1805 1806 /** 1807 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1808 */ 1809 struct dmub_cmd_abm_set_pipe_data { 1810 /** 1811 * OTG HW instance. 1812 */ 1813 uint8_t otg_inst; 1814 1815 /** 1816 * Panel Control HW instance. 1817 */ 1818 uint8_t panel_inst; 1819 1820 /** 1821 * Controls how ABM will interpret a set pipe or set level command. 1822 */ 1823 uint8_t set_pipe_option; 1824 1825 /** 1826 * Unused. 1827 * TODO: Remove. 1828 */ 1829 uint8_t ramping_boundary; 1830 }; 1831 1832 /** 1833 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1834 */ 1835 struct dmub_rb_cmd_abm_set_pipe { 1836 /** 1837 * Command header. 1838 */ 1839 struct dmub_cmd_header header; 1840 1841 /** 1842 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1843 */ 1844 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 1845 }; 1846 1847 /** 1848 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1849 */ 1850 struct dmub_cmd_abm_set_backlight_data { 1851 /** 1852 * Number of frames to ramp to backlight user level. 1853 */ 1854 uint32_t frame_ramp; 1855 1856 /** 1857 * Requested backlight level from user. 1858 */ 1859 uint32_t backlight_user_level; 1860 1861 /** 1862 * ABM control version. 1863 */ 1864 uint8_t version; 1865 1866 /** 1867 * Panel Control HW instance mask. 1868 * Bit 0 is Panel Control HW instance 0. 1869 * Bit 1 is Panel Control HW instance 1. 1870 */ 1871 uint8_t panel_mask; 1872 1873 /** 1874 * Explicit padding to 4 byte boundary. 1875 */ 1876 uint8_t pad[2]; 1877 }; 1878 1879 /** 1880 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 1881 */ 1882 struct dmub_rb_cmd_abm_set_backlight { 1883 /** 1884 * Command header. 1885 */ 1886 struct dmub_cmd_header header; 1887 1888 /** 1889 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1890 */ 1891 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 1892 }; 1893 1894 /** 1895 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1896 */ 1897 struct dmub_cmd_abm_set_level_data { 1898 /** 1899 * Set current ABM operating/aggression level. 1900 */ 1901 uint32_t level; 1902 1903 /** 1904 * ABM control version. 1905 */ 1906 uint8_t version; 1907 1908 /** 1909 * Panel Control HW instance mask. 1910 * Bit 0 is Panel Control HW instance 0. 1911 * Bit 1 is Panel Control HW instance 1. 1912 */ 1913 uint8_t panel_mask; 1914 1915 /** 1916 * Explicit padding to 4 byte boundary. 1917 */ 1918 uint8_t pad[2]; 1919 }; 1920 1921 /** 1922 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 1923 */ 1924 struct dmub_rb_cmd_abm_set_level { 1925 /** 1926 * Command header. 1927 */ 1928 struct dmub_cmd_header header; 1929 1930 /** 1931 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1932 */ 1933 struct dmub_cmd_abm_set_level_data abm_set_level_data; 1934 }; 1935 1936 /** 1937 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1938 */ 1939 struct dmub_cmd_abm_set_ambient_level_data { 1940 /** 1941 * Ambient light sensor reading from OS. 1942 */ 1943 uint32_t ambient_lux; 1944 1945 /** 1946 * ABM control version. 1947 */ 1948 uint8_t version; 1949 1950 /** 1951 * Panel Control HW instance mask. 1952 * Bit 0 is Panel Control HW instance 0. 1953 * Bit 1 is Panel Control HW instance 1. 1954 */ 1955 uint8_t panel_mask; 1956 1957 /** 1958 * Explicit padding to 4 byte boundary. 1959 */ 1960 uint8_t pad[2]; 1961 }; 1962 1963 /** 1964 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1965 */ 1966 struct dmub_rb_cmd_abm_set_ambient_level { 1967 /** 1968 * Command header. 1969 */ 1970 struct dmub_cmd_header header; 1971 1972 /** 1973 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1974 */ 1975 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 1976 }; 1977 1978 /** 1979 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1980 */ 1981 struct dmub_cmd_abm_set_pwm_frac_data { 1982 /** 1983 * Enable/disable fractional duty cycle for backlight PWM. 1984 * TODO: Convert to uint8_t. 1985 */ 1986 uint32_t fractional_pwm; 1987 1988 /** 1989 * ABM control version. 1990 */ 1991 uint8_t version; 1992 1993 /** 1994 * Panel Control HW instance mask. 1995 * Bit 0 is Panel Control HW instance 0. 1996 * Bit 1 is Panel Control HW instance 1. 1997 */ 1998 uint8_t panel_mask; 1999 2000 /** 2001 * Explicit padding to 4 byte boundary. 2002 */ 2003 uint8_t pad[2]; 2004 }; 2005 2006 /** 2007 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2008 */ 2009 struct dmub_rb_cmd_abm_set_pwm_frac { 2010 /** 2011 * Command header. 2012 */ 2013 struct dmub_cmd_header header; 2014 2015 /** 2016 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2017 */ 2018 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2019 }; 2020 2021 /** 2022 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2023 */ 2024 struct dmub_cmd_abm_init_config_data { 2025 /** 2026 * Location of indirect buffer used to pass init data to ABM. 2027 */ 2028 union dmub_addr src; 2029 2030 /** 2031 * Indirect buffer length. 2032 */ 2033 uint16_t bytes; 2034 2035 2036 /** 2037 * ABM control version. 2038 */ 2039 uint8_t version; 2040 2041 /** 2042 * Panel Control HW instance mask. 2043 * Bit 0 is Panel Control HW instance 0. 2044 * Bit 1 is Panel Control HW instance 1. 2045 */ 2046 uint8_t panel_mask; 2047 2048 /** 2049 * Explicit padding to 4 byte boundary. 2050 */ 2051 uint8_t pad[2]; 2052 }; 2053 2054 /** 2055 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2056 */ 2057 struct dmub_rb_cmd_abm_init_config { 2058 /** 2059 * Command header. 2060 */ 2061 struct dmub_cmd_header header; 2062 2063 /** 2064 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2065 */ 2066 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2067 }; 2068 2069 /** 2070 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2071 */ 2072 struct dmub_cmd_query_feature_caps_data { 2073 /** 2074 * DMUB feature capabilities. 2075 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2076 */ 2077 struct dmub_feature_caps feature_caps; 2078 }; 2079 2080 /** 2081 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2082 */ 2083 struct dmub_rb_cmd_query_feature_caps { 2084 /** 2085 * Command header. 2086 */ 2087 struct dmub_cmd_header header; 2088 /** 2089 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2090 */ 2091 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2092 }; 2093 2094 struct dmub_optc_state { 2095 uint32_t v_total_max; 2096 uint32_t v_total_min; 2097 uint32_t v_total_mid; 2098 uint32_t v_total_mid_frame_num; 2099 uint32_t tg_inst; 2100 uint32_t enable_manual_trigger; 2101 uint32_t clear_force_vsync; 2102 }; 2103 2104 struct dmub_rb_cmd_drr_update { 2105 struct dmub_cmd_header header; 2106 struct dmub_optc_state dmub_optc_state_req; 2107 }; 2108 2109 /** 2110 * enum dmub_cmd_panel_cntl_type - Panel control command. 2111 */ 2112 enum dmub_cmd_panel_cntl_type { 2113 /** 2114 * Initializes embedded panel hardware blocks. 2115 */ 2116 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2117 /** 2118 * Queries backlight info for the embedded panel. 2119 */ 2120 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2121 }; 2122 2123 /** 2124 * struct dmub_cmd_panel_cntl_data - Panel control data. 2125 */ 2126 struct dmub_cmd_panel_cntl_data { 2127 uint32_t inst; /**< panel instance */ 2128 uint32_t current_backlight; /* in/out */ 2129 uint32_t bl_pwm_cntl; /* in/out */ 2130 uint32_t bl_pwm_period_cntl; /* in/out */ 2131 uint32_t bl_pwm_ref_div1; /* in/out */ 2132 uint8_t is_backlight_on : 1; /* in/out */ 2133 uint8_t is_powered_on : 1; /* in/out */ 2134 }; 2135 2136 /** 2137 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2138 */ 2139 struct dmub_rb_cmd_panel_cntl { 2140 struct dmub_cmd_header header; /**< header */ 2141 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2142 }; 2143 2144 /** 2145 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2146 */ 2147 struct dmub_cmd_lvtma_control_data { 2148 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2149 uint8_t reserved_0[3]; /**< For future use */ 2150 uint8_t panel_inst; /**< LVTMA control instance */ 2151 uint8_t reserved_1[3]; /**< For future use */ 2152 }; 2153 2154 /** 2155 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2156 */ 2157 struct dmub_rb_cmd_lvtma_control { 2158 /** 2159 * Command header. 2160 */ 2161 struct dmub_cmd_header header; 2162 /** 2163 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2164 */ 2165 struct dmub_cmd_lvtma_control_data data; 2166 }; 2167 2168 /** 2169 * Maximum number of bytes a chunk sent to DMUB for parsing 2170 */ 2171 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2172 2173 /** 2174 * Represent a chunk of CEA blocks sent to DMUB for parsing 2175 */ 2176 struct dmub_cmd_send_edid_cea { 2177 uint16_t offset; /**< offset into the CEA block */ 2178 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2179 uint16_t total_length; /**< total length of the CEA block */ 2180 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2181 uint8_t pad[3]; /**< padding and for future expansion */ 2182 }; 2183 2184 /** 2185 * Result of VSDB parsing from CEA block 2186 */ 2187 struct dmub_cmd_edid_cea_amd_vsdb { 2188 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2189 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2190 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2191 uint16_t min_frame_rate; /**< Maximum frame rate */ 2192 uint16_t max_frame_rate; /**< Minimum frame rate */ 2193 }; 2194 2195 /** 2196 * Result of sending a CEA chunk 2197 */ 2198 struct dmub_cmd_edid_cea_ack { 2199 uint16_t offset; /**< offset of the chunk into the CEA block */ 2200 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2201 uint8_t pad; /**< padding and for future expansion */ 2202 }; 2203 2204 /** 2205 * Specify whether the result is an ACK/NACK or the parsing has finished 2206 */ 2207 enum dmub_cmd_edid_cea_reply_type { 2208 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2209 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2210 }; 2211 2212 /** 2213 * Definition of a DMUB_CMD__EDID_CEA command. 2214 */ 2215 struct dmub_rb_cmd_edid_cea { 2216 struct dmub_cmd_header header; /**< Command header */ 2217 union dmub_cmd_edid_cea_data { 2218 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2219 struct dmub_cmd_edid_cea_output { /**< output with results */ 2220 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2221 union { 2222 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2223 struct dmub_cmd_edid_cea_ack ack; 2224 }; 2225 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2226 } data; /**< Command data */ 2227 2228 }; 2229 2230 /** 2231 * union dmub_rb_cmd - DMUB inbox command. 2232 */ 2233 union dmub_rb_cmd { 2234 struct dmub_rb_cmd_lock_hw lock_hw; 2235 /** 2236 * Elements shared with all commands. 2237 */ 2238 struct dmub_rb_cmd_common cmd_common; 2239 /** 2240 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2241 */ 2242 struct dmub_rb_cmd_read_modify_write read_modify_write; 2243 /** 2244 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2245 */ 2246 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2247 /** 2248 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2249 */ 2250 struct dmub_rb_cmd_burst_write burst_write; 2251 /** 2252 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2253 */ 2254 struct dmub_rb_cmd_reg_wait reg_wait; 2255 /** 2256 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2257 */ 2258 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2259 /** 2260 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2261 */ 2262 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2263 /** 2264 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2265 */ 2266 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2267 /** 2268 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2269 */ 2270 struct dmub_rb_cmd_dpphy_init dpphy_init; 2271 /** 2272 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2273 */ 2274 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2275 /** 2276 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2277 */ 2278 struct dmub_rb_cmd_psr_set_version psr_set_version; 2279 /** 2280 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2281 */ 2282 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2283 /** 2284 * Definition of a DMUB_CMD__PSR_ENABLE command. 2285 */ 2286 struct dmub_rb_cmd_psr_enable psr_enable; 2287 /** 2288 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2289 */ 2290 struct dmub_rb_cmd_psr_set_level psr_set_level; 2291 /** 2292 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2293 */ 2294 struct dmub_rb_cmd_psr_force_static psr_force_static; 2295 /** 2296 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2297 */ 2298 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2299 /** 2300 * Definition of a DMUB_CMD__MALL command. 2301 */ 2302 struct dmub_rb_cmd_mall mall; 2303 /** 2304 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2305 */ 2306 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2307 2308 /** 2309 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2310 */ 2311 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2312 2313 /** 2314 * Definition of DMUB_CMD__PANEL_CNTL commands. 2315 */ 2316 struct dmub_rb_cmd_panel_cntl panel_cntl; 2317 /** 2318 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2319 */ 2320 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2321 2322 /** 2323 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2324 */ 2325 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2326 2327 /** 2328 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2329 */ 2330 struct dmub_rb_cmd_abm_set_level abm_set_level; 2331 2332 /** 2333 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2334 */ 2335 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2336 2337 /** 2338 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2339 */ 2340 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2341 2342 /** 2343 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2344 */ 2345 struct dmub_rb_cmd_abm_init_config abm_init_config; 2346 2347 /** 2348 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2349 */ 2350 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2351 2352 /** 2353 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2354 */ 2355 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2356 2357 /** 2358 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2359 */ 2360 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2361 struct dmub_rb_cmd_drr_update drr_update; 2362 /** 2363 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2364 */ 2365 struct dmub_rb_cmd_lvtma_control lvtma_control; 2366 /** 2367 * Definition of a DMUB_CMD__EDID_CEA command. 2368 */ 2369 struct dmub_rb_cmd_edid_cea edid_cea; 2370 }; 2371 2372 /** 2373 * union dmub_rb_out_cmd - Outbox command 2374 */ 2375 union dmub_rb_out_cmd { 2376 /** 2377 * Parameters common to every command. 2378 */ 2379 struct dmub_rb_cmd_common cmd_common; 2380 /** 2381 * AUX reply command. 2382 */ 2383 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2384 /** 2385 * HPD notify command. 2386 */ 2387 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2388 }; 2389 #pragma pack(pop) 2390 2391 2392 //============================================================================== 2393 //</DMUB_CMD>=================================================================== 2394 //============================================================================== 2395 //< DMUB_RB>==================================================================== 2396 //============================================================================== 2397 2398 #if defined(__cplusplus) 2399 extern "C" { 2400 #endif 2401 2402 /** 2403 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2404 */ 2405 struct dmub_rb_init_params { 2406 void *ctx; /**< Caller provided context pointer */ 2407 void *base_address; /**< CPU base address for ring's data */ 2408 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2409 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2410 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2411 }; 2412 2413 /** 2414 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2415 */ 2416 struct dmub_rb { 2417 void *base_address; /**< CPU address for the ring's data */ 2418 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2419 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2420 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2421 2422 void *ctx; /**< Caller provided context pointer */ 2423 void *dmub; /**< Pointer to the DMUB interface */ 2424 }; 2425 2426 /** 2427 * @brief Checks if the ringbuffer is empty. 2428 * 2429 * @param rb DMUB Ringbuffer 2430 * @return true if empty 2431 * @return false otherwise 2432 */ 2433 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2434 { 2435 return (rb->wrpt == rb->rptr); 2436 } 2437 2438 /** 2439 * @brief Checks if the ringbuffer is full 2440 * 2441 * @param rb DMUB Ringbuffer 2442 * @return true if full 2443 * @return false otherwise 2444 */ 2445 static inline bool dmub_rb_full(struct dmub_rb *rb) 2446 { 2447 uint32_t data_count; 2448 2449 if (rb->wrpt >= rb->rptr) 2450 data_count = rb->wrpt - rb->rptr; 2451 else 2452 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2453 2454 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2455 } 2456 2457 /** 2458 * @brief Pushes a command into the ringbuffer 2459 * 2460 * @param rb DMUB ringbuffer 2461 * @param cmd The command to push 2462 * @return true if the ringbuffer was not full 2463 * @return false otherwise 2464 */ 2465 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2466 const union dmub_rb_cmd *cmd) 2467 { 2468 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 2469 const uint64_t *src = (const uint64_t *)cmd; 2470 uint8_t i; 2471 2472 if (dmub_rb_full(rb)) 2473 return false; 2474 2475 // copying data 2476 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2477 *dst++ = *src++; 2478 2479 rb->wrpt += DMUB_RB_CMD_SIZE; 2480 2481 if (rb->wrpt >= rb->capacity) 2482 rb->wrpt %= rb->capacity; 2483 2484 return true; 2485 } 2486 2487 /** 2488 * @brief Pushes a command into the DMUB outbox ringbuffer 2489 * 2490 * @param rb DMUB outbox ringbuffer 2491 * @param cmd Outbox command 2492 * @return true if not full 2493 * @return false otherwise 2494 */ 2495 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2496 const union dmub_rb_out_cmd *cmd) 2497 { 2498 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2499 const uint8_t *src = (uint8_t *)cmd; 2500 2501 if (dmub_rb_full(rb)) 2502 return false; 2503 2504 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2505 2506 rb->wrpt += DMUB_RB_CMD_SIZE; 2507 2508 if (rb->wrpt >= rb->capacity) 2509 rb->wrpt %= rb->capacity; 2510 2511 return true; 2512 } 2513 2514 /** 2515 * @brief Returns the next unprocessed command in the ringbuffer. 2516 * 2517 * @param rb DMUB ringbuffer 2518 * @param cmd The command to return 2519 * @return true if not empty 2520 * @return false otherwise 2521 */ 2522 static inline bool dmub_rb_front(struct dmub_rb *rb, 2523 union dmub_rb_cmd **cmd) 2524 { 2525 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2526 2527 if (dmub_rb_empty(rb)) 2528 return false; 2529 2530 *cmd = (union dmub_rb_cmd *)rb_cmd; 2531 2532 return true; 2533 } 2534 2535 /** 2536 * @brief Determines the next ringbuffer offset. 2537 * 2538 * @param rb DMUB inbox ringbuffer 2539 * @param num_cmds Number of commands 2540 * @param next_rptr The next offset in the ringbuffer 2541 */ 2542 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2543 uint32_t num_cmds, 2544 uint32_t *next_rptr) 2545 { 2546 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2547 2548 if (*next_rptr >= rb->capacity) 2549 *next_rptr %= rb->capacity; 2550 } 2551 2552 /** 2553 * @brief Returns a pointer to a command in the inbox. 2554 * 2555 * @param rb DMUB inbox ringbuffer 2556 * @param cmd The inbox command to return 2557 * @param rptr The ringbuffer offset 2558 * @return true if not empty 2559 * @return false otherwise 2560 */ 2561 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 2562 union dmub_rb_cmd **cmd, 2563 uint32_t rptr) 2564 { 2565 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 2566 2567 if (dmub_rb_empty(rb)) 2568 return false; 2569 2570 *cmd = (union dmub_rb_cmd *)rb_cmd; 2571 2572 return true; 2573 } 2574 2575 /** 2576 * @brief Returns the next unprocessed command in the outbox. 2577 * 2578 * @param rb DMUB outbox ringbuffer 2579 * @param cmd The outbox command to return 2580 * @return true if not empty 2581 * @return false otherwise 2582 */ 2583 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2584 union dmub_rb_out_cmd *cmd) 2585 { 2586 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 2587 uint64_t *dst = (uint64_t *)cmd; 2588 uint8_t i; 2589 2590 if (dmub_rb_empty(rb)) 2591 return false; 2592 2593 // copying data 2594 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2595 *dst++ = *src++; 2596 2597 return true; 2598 } 2599 2600 /** 2601 * @brief Removes the front entry in the ringbuffer. 2602 * 2603 * @param rb DMUB ringbuffer 2604 * @return true if the command was removed 2605 * @return false if there were no commands 2606 */ 2607 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 2608 { 2609 if (dmub_rb_empty(rb)) 2610 return false; 2611 2612 rb->rptr += DMUB_RB_CMD_SIZE; 2613 2614 if (rb->rptr >= rb->capacity) 2615 rb->rptr %= rb->capacity; 2616 2617 return true; 2618 } 2619 2620 /** 2621 * @brief Flushes commands in the ringbuffer to framebuffer memory. 2622 * 2623 * Avoids a race condition where DMCUB accesses memory while 2624 * there are still writes in flight to framebuffer. 2625 * 2626 * @param rb DMUB ringbuffer 2627 */ 2628 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 2629 { 2630 uint32_t rptr = rb->rptr; 2631 uint32_t wptr = rb->wrpt; 2632 2633 while (rptr != wptr) { 2634 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 2635 uint8_t i; 2636 2637 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2638 *data++; 2639 2640 rptr += DMUB_RB_CMD_SIZE; 2641 if (rptr >= rb->capacity) 2642 rptr %= rb->capacity; 2643 } 2644 } 2645 2646 /** 2647 * @brief Initializes a DMCUB ringbuffer 2648 * 2649 * @param rb DMUB ringbuffer 2650 * @param init_params initial configuration for the ringbuffer 2651 */ 2652 static inline void dmub_rb_init(struct dmub_rb *rb, 2653 struct dmub_rb_init_params *init_params) 2654 { 2655 rb->base_address = init_params->base_address; 2656 rb->capacity = init_params->capacity; 2657 rb->rptr = init_params->read_ptr; 2658 rb->wrpt = init_params->write_ptr; 2659 } 2660 2661 /** 2662 * @brief Copies output data from in/out commands into the given command. 2663 * 2664 * @param rb DMUB ringbuffer 2665 * @param cmd Command to copy data into 2666 */ 2667 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 2668 union dmub_rb_cmd *cmd) 2669 { 2670 // Copy rb entry back into command 2671 uint8_t *rd_ptr = (rb->rptr == 0) ? 2672 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 2673 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 2674 2675 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 2676 } 2677 2678 #if defined(__cplusplus) 2679 } 2680 #endif 2681 2682 //============================================================================== 2683 //</DMUB_RB>==================================================================== 2684 //============================================================================== 2685 2686 #endif /* _DMUB_CMD_H_ */ 2687