1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Maximum number of streams on any ASIC. */ 99 #define DMUB_MAX_STREAMS 6 100 101 /* Maximum number of planes on any ASIC. */ 102 #define DMUB_MAX_PLANES 6 103 104 /* Trace buffer offset for entry */ 105 #define TRACE_BUFFER_ENTRY_OFFSET 16 106 107 /** 108 * Maximum number of dirty rects supported by FW. 109 */ 110 #define DMUB_MAX_DIRTY_RECTS 3 111 112 /** 113 * 114 * PSR control version legacy 115 */ 116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117 /** 118 * PSR control version with multi edp support 119 */ 120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121 122 123 /** 124 * ABM control version legacy 125 */ 126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127 128 /** 129 * ABM control version with multi edp support 130 */ 131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132 133 /** 134 * Physical framebuffer address location, 64-bit. 135 */ 136 #ifndef PHYSICAL_ADDRESS_LOC 137 #define PHYSICAL_ADDRESS_LOC union large_integer 138 #endif 139 140 /** 141 * OS/FW agnostic memcpy 142 */ 143 #ifndef dmub_memcpy 144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 145 #endif 146 147 /** 148 * OS/FW agnostic memset 149 */ 150 #ifndef dmub_memset 151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 152 #endif 153 154 #if defined(__cplusplus) 155 extern "C" { 156 #endif 157 158 /** 159 * OS/FW agnostic udelay 160 */ 161 #ifndef dmub_udelay 162 #define dmub_udelay(microseconds) udelay(microseconds) 163 #endif 164 165 /** 166 * union dmub_addr - DMUB physical/virtual 64-bit address. 167 */ 168 union dmub_addr { 169 struct { 170 uint32_t low_part; /**< Lower 32 bits */ 171 uint32_t high_part; /**< Upper 32 bits */ 172 } u; /*<< Low/high bit access */ 173 uint64_t quad_part; /*<< 64 bit address */ 174 }; 175 176 /** 177 * Dirty rect definition. 178 */ 179 struct dmub_rect { 180 /** 181 * Dirty rect x offset. 182 */ 183 uint32_t x; 184 185 /** 186 * Dirty rect y offset. 187 */ 188 uint32_t y; 189 190 /** 191 * Dirty rect width. 192 */ 193 uint32_t width; 194 195 /** 196 * Dirty rect height. 197 */ 198 uint32_t height; 199 }; 200 201 /** 202 * Flags that can be set by driver to change some PSR behaviour. 203 */ 204 union dmub_psr_debug_flags { 205 /** 206 * Debug flags. 207 */ 208 struct { 209 /** 210 * Enable visual confirm in FW. 211 */ 212 uint32_t visual_confirm : 1; 213 214 /** 215 * Force all selective updates to bw full frame updates. 216 */ 217 uint32_t force_full_frame_update : 1; 218 219 /** 220 * Use HW Lock Mgr object to do HW locking in FW. 221 */ 222 uint32_t use_hw_lock_mgr : 1; 223 224 /** 225 * Use TPS3 signal when restore main link. 226 */ 227 uint32_t force_wakeup_by_tps3 : 1; 228 229 /** 230 * Back to back flip, therefore cannot power down PHY 231 */ 232 uint32_t back_to_back_flip : 1; 233 234 } bitfields; 235 236 /** 237 * Union for debug flags. 238 */ 239 uint32_t u32All; 240 }; 241 242 /** 243 * DMUB visual confirm color 244 */ 245 struct dmub_feature_caps { 246 /** 247 * Max PSR version supported by FW. 248 */ 249 uint8_t psr; 250 uint8_t fw_assisted_mclk_switch; 251 uint8_t reserved[6]; 252 }; 253 254 struct dmub_visual_confirm_color { 255 /** 256 * Maximum 10 bits color value 257 */ 258 uint16_t color_r_cr; 259 uint16_t color_g_y; 260 uint16_t color_b_cb; 261 uint16_t panel_inst; 262 }; 263 264 #if defined(__cplusplus) 265 } 266 #endif 267 268 //============================================================================== 269 //</DMUB_TYPES>================================================================= 270 //============================================================================== 271 //< DMUB_META>================================================================== 272 //============================================================================== 273 #pragma pack(push, 1) 274 275 /* Magic value for identifying dmub_fw_meta_info */ 276 #define DMUB_FW_META_MAGIC 0x444D5542 277 278 /* Offset from the end of the file to the dmub_fw_meta_info */ 279 #define DMUB_FW_META_OFFSET 0x24 280 281 /** 282 * struct dmub_fw_meta_info - metadata associated with fw binary 283 * 284 * NOTE: This should be considered a stable API. Fields should 285 * not be repurposed or reordered. New fields should be 286 * added instead to extend the structure. 287 * 288 * @magic_value: magic value identifying DMUB firmware meta info 289 * @fw_region_size: size of the firmware state region 290 * @trace_buffer_size: size of the tracebuffer region 291 * @fw_version: the firmware version information 292 * @dal_fw: 1 if the firmware is DAL 293 */ 294 struct dmub_fw_meta_info { 295 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 296 uint32_t fw_region_size; /**< size of the firmware state region */ 297 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 298 uint32_t fw_version; /**< the firmware version information */ 299 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 300 uint8_t reserved[3]; /**< padding bits */ 301 }; 302 303 /** 304 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 305 */ 306 union dmub_fw_meta { 307 struct dmub_fw_meta_info info; /**< metadata info */ 308 uint8_t reserved[64]; /**< padding bits */ 309 }; 310 311 #pragma pack(pop) 312 313 //============================================================================== 314 //< DMUB Trace Buffer>================================================================ 315 //============================================================================== 316 /** 317 * dmub_trace_code_t - firmware trace code, 32-bits 318 */ 319 typedef uint32_t dmub_trace_code_t; 320 321 /** 322 * struct dmcub_trace_buf_entry - Firmware trace entry 323 */ 324 struct dmcub_trace_buf_entry { 325 dmub_trace_code_t trace_code; /**< trace code for the event */ 326 uint32_t tick_count; /**< the tick count at time of trace */ 327 uint32_t param0; /**< trace defined parameter 0 */ 328 uint32_t param1; /**< trace defined parameter 1 */ 329 }; 330 331 //============================================================================== 332 //< DMUB_STATUS>================================================================ 333 //============================================================================== 334 335 /** 336 * DMCUB scratch registers can be used to determine firmware status. 337 * Current scratch register usage is as follows: 338 * 339 * SCRATCH0: FW Boot Status register 340 * SCRATCH5: LVTMA Status Register 341 * SCRATCH15: FW Boot Options register 342 */ 343 344 /** 345 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 346 */ 347 union dmub_fw_boot_status { 348 struct { 349 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 350 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 351 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 352 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 353 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 354 uint32_t reserved : 1; 355 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 356 357 } bits; /**< status bits */ 358 uint32_t all; /**< 32-bit access to status bits */ 359 }; 360 361 /** 362 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 363 */ 364 enum dmub_fw_boot_status_bit { 365 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 366 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 367 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 368 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 369 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 370 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 371 }; 372 373 /* Register bit definition for SCRATCH5 */ 374 union dmub_lvtma_status { 375 struct { 376 uint32_t psp_ok : 1; 377 uint32_t edp_on : 1; 378 uint32_t reserved : 30; 379 } bits; 380 uint32_t all; 381 }; 382 383 enum dmub_lvtma_status_bit { 384 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 385 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 386 }; 387 388 /** 389 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 390 */ 391 union dmub_fw_boot_options { 392 struct { 393 uint32_t pemu_env : 1; /**< 1 if PEMU */ 394 uint32_t fpga_env : 1; /**< 1 if FPGA */ 395 uint32_t optimized_init : 1; /**< 1 if optimized init */ 396 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 397 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 398 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 399 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 400 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 401 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 402 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 403 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 404 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 405 uint32_t power_optimization: 1; 406 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 407 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 408 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 409 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 410 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 411 412 uint32_t reserved : 15; /**< reserved */ 413 } bits; /**< boot bits */ 414 uint32_t all; /**< 32-bit access to bits */ 415 }; 416 417 enum dmub_fw_boot_options_bit { 418 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 419 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 420 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 421 }; 422 423 //============================================================================== 424 //</DMUB_STATUS>================================================================ 425 //============================================================================== 426 //< DMUB_VBIOS>================================================================= 427 //============================================================================== 428 429 /* 430 * enum dmub_cmd_vbios_type - VBIOS commands. 431 * 432 * Command IDs should be treated as stable ABI. 433 * Do not reuse or modify IDs. 434 */ 435 enum dmub_cmd_vbios_type { 436 /** 437 * Configures the DIG encoder. 438 */ 439 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 440 /** 441 * Controls the PHY. 442 */ 443 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 444 /** 445 * Sets the pixel clock/symbol clock. 446 */ 447 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 448 /** 449 * Enables or disables power gating. 450 */ 451 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 452 /** 453 * Controls embedded panels. 454 */ 455 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 456 /** 457 * Query DP alt status on a transmitter. 458 */ 459 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 460 }; 461 462 //============================================================================== 463 //</DMUB_VBIOS>================================================================= 464 //============================================================================== 465 //< DMUB_GPINT>================================================================= 466 //============================================================================== 467 468 /** 469 * The shifts and masks below may alternatively be used to format and read 470 * the command register bits. 471 */ 472 473 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 474 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 475 476 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 477 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 478 479 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 480 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 481 482 /** 483 * Command responses. 484 */ 485 486 /** 487 * Return response for DMUB_GPINT__STOP_FW command. 488 */ 489 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 490 491 /** 492 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 493 */ 494 union dmub_gpint_data_register { 495 struct { 496 uint32_t param : 16; /**< 16-bit parameter */ 497 uint32_t command_code : 12; /**< GPINT command */ 498 uint32_t status : 4; /**< Command status bit */ 499 } bits; /**< GPINT bit access */ 500 uint32_t all; /**< GPINT 32-bit access */ 501 }; 502 503 /* 504 * enum dmub_gpint_command - GPINT command to DMCUB FW 505 * 506 * Command IDs should be treated as stable ABI. 507 * Do not reuse or modify IDs. 508 */ 509 enum dmub_gpint_command { 510 /** 511 * Invalid command, ignored. 512 */ 513 DMUB_GPINT__INVALID_COMMAND = 0, 514 /** 515 * DESC: Queries the firmware version. 516 * RETURN: Firmware version. 517 */ 518 DMUB_GPINT__GET_FW_VERSION = 1, 519 /** 520 * DESC: Halts the firmware. 521 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 522 */ 523 DMUB_GPINT__STOP_FW = 2, 524 /** 525 * DESC: Get PSR state from FW. 526 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 527 */ 528 DMUB_GPINT__GET_PSR_STATE = 7, 529 /** 530 * DESC: Notifies DMCUB of the currently active streams. 531 * ARGS: Stream mask, 1 bit per active stream index. 532 */ 533 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 534 /** 535 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 536 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 537 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 538 * RETURN: PSR residency in milli-percent. 539 */ 540 DMUB_GPINT__PSR_RESIDENCY = 9, 541 542 /** 543 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 544 */ 545 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 546 }; 547 548 /** 549 * INBOX0 generic command definition 550 */ 551 union dmub_inbox0_cmd_common { 552 struct { 553 uint32_t command_code: 8; /**< INBOX0 command code */ 554 uint32_t param: 24; /**< 24-bit parameter */ 555 } bits; 556 uint32_t all; 557 }; 558 559 /** 560 * INBOX0 hw_lock command definition 561 */ 562 union dmub_inbox0_cmd_lock_hw { 563 struct { 564 uint32_t command_code: 8; 565 566 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 567 uint32_t hw_lock_client: 2; 568 569 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 570 uint32_t otg_inst: 3; 571 uint32_t opp_inst: 3; 572 uint32_t dig_inst: 3; 573 574 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 575 uint32_t lock_pipe: 1; 576 uint32_t lock_cursor: 1; 577 uint32_t lock_dig: 1; 578 uint32_t triple_buffer_lock: 1; 579 580 uint32_t lock: 1; /**< Lock */ 581 uint32_t should_release: 1; /**< Release */ 582 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 583 } bits; 584 uint32_t all; 585 }; 586 587 union dmub_inbox0_data_register { 588 union dmub_inbox0_cmd_common inbox0_cmd_common; 589 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 590 }; 591 592 enum dmub_inbox0_command { 593 /** 594 * DESC: Invalid command, ignored. 595 */ 596 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 597 /** 598 * DESC: Notification to acquire/release HW lock 599 * ARGS: 600 */ 601 DMUB_INBOX0_CMD__HW_LOCK = 1, 602 }; 603 //============================================================================== 604 //</DMUB_GPINT>================================================================= 605 //============================================================================== 606 //< DMUB_CMD>=================================================================== 607 //============================================================================== 608 609 /** 610 * Size in bytes of each DMUB command. 611 */ 612 #define DMUB_RB_CMD_SIZE 64 613 614 /** 615 * Maximum number of items in the DMUB ringbuffer. 616 */ 617 #define DMUB_RB_MAX_ENTRY 128 618 619 /** 620 * Ringbuffer size in bytes. 621 */ 622 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 623 624 /** 625 * REG_SET mask for reg offload. 626 */ 627 #define REG_SET_MASK 0xFFFF 628 629 /* 630 * enum dmub_cmd_type - DMUB inbox command. 631 * 632 * Command IDs should be treated as stable ABI. 633 * Do not reuse or modify IDs. 634 */ 635 enum dmub_cmd_type { 636 /** 637 * Invalid command. 638 */ 639 DMUB_CMD__NULL = 0, 640 /** 641 * Read modify write register sequence offload. 642 */ 643 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 644 /** 645 * Field update register sequence offload. 646 */ 647 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 648 /** 649 * Burst write sequence offload. 650 */ 651 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 652 /** 653 * Reg wait sequence offload. 654 */ 655 DMUB_CMD__REG_REG_WAIT = 4, 656 /** 657 * Workaround to avoid HUBP underflow during NV12 playback. 658 */ 659 DMUB_CMD__PLAT_54186_WA = 5, 660 /** 661 * Command type used to query FW feature caps. 662 */ 663 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 664 /** 665 * Command type used to get visual confirm color. 666 */ 667 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 668 /** 669 * Command type used for all PSR commands. 670 */ 671 DMUB_CMD__PSR = 64, 672 /** 673 * Command type used for all MALL commands. 674 */ 675 DMUB_CMD__MALL = 65, 676 /** 677 * Command type used for all ABM commands. 678 */ 679 DMUB_CMD__ABM = 66, 680 /** 681 * Command type used to update dirty rects in FW. 682 */ 683 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 684 /** 685 * Command type used to update cursor info in FW. 686 */ 687 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 688 /** 689 * Command type used for HW locking in FW. 690 */ 691 DMUB_CMD__HW_LOCK = 69, 692 /** 693 * Command type used to access DP AUX. 694 */ 695 DMUB_CMD__DP_AUX_ACCESS = 70, 696 /** 697 * Command type used for OUTBOX1 notification enable 698 */ 699 DMUB_CMD__OUTBOX1_ENABLE = 71, 700 701 /** 702 * Command type used for all idle optimization commands. 703 */ 704 DMUB_CMD__IDLE_OPT = 72, 705 /** 706 * Command type used for all clock manager commands. 707 */ 708 DMUB_CMD__CLK_MGR = 73, 709 /** 710 * Command type used for all panel control commands. 711 */ 712 DMUB_CMD__PANEL_CNTL = 74, 713 /** 714 * Command type used for <TODO:description> 715 */ 716 DMUB_CMD__CAB_FOR_SS = 75, 717 718 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 719 720 /** 721 * Command type used for interfacing with DPIA. 722 */ 723 DMUB_CMD__DPIA = 77, 724 /** 725 * Command type used for EDID CEA parsing 726 */ 727 DMUB_CMD__EDID_CEA = 79, 728 /** 729 * Command type used for getting usbc cable ID 730 */ 731 DMUB_CMD_GET_USBC_CABLE_ID = 81, 732 /** 733 * Command type used to query HPD state. 734 */ 735 DMUB_CMD__QUERY_HPD_STATE = 82, 736 /** 737 * Command type used for all VBIOS interface commands. 738 */ 739 740 /** 741 * Command type used for all SECURE_DISPLAY commands. 742 */ 743 DMUB_CMD__SECURE_DISPLAY = 85, 744 745 /** 746 * Command type used to set DPIA HPD interrupt state 747 */ 748 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 749 750 DMUB_CMD__VBIOS = 128, 751 }; 752 753 /** 754 * enum dmub_out_cmd_type - DMUB outbox commands. 755 */ 756 enum dmub_out_cmd_type { 757 /** 758 * Invalid outbox command, ignored. 759 */ 760 DMUB_OUT_CMD__NULL = 0, 761 /** 762 * Command type used for DP AUX Reply data notification 763 */ 764 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 765 /** 766 * Command type used for DP HPD event notification 767 */ 768 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 769 /** 770 * Command type used for SET_CONFIG Reply notification 771 */ 772 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 773 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5 774 }; 775 776 /* DMUB_CMD__DPIA command sub-types. */ 777 enum dmub_cmd_dpia_type { 778 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 779 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 780 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 781 }; 782 783 #pragma pack(push, 1) 784 785 /** 786 * struct dmub_cmd_header - Common command header fields. 787 */ 788 struct dmub_cmd_header { 789 unsigned int type : 8; /**< command type */ 790 unsigned int sub_type : 8; /**< command sub type */ 791 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 792 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 793 unsigned int reserved0 : 6; /**< reserved bits */ 794 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 795 unsigned int reserved1 : 2; /**< reserved bits */ 796 }; 797 798 /* 799 * struct dmub_cmd_read_modify_write_sequence - Read modify write 800 * 801 * 60 payload bytes can hold up to 5 sets of read modify writes, 802 * each take 3 dwords. 803 * 804 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 805 * 806 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 807 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 808 */ 809 struct dmub_cmd_read_modify_write_sequence { 810 uint32_t addr; /**< register address */ 811 uint32_t modify_mask; /**< modify mask */ 812 uint32_t modify_value; /**< modify value */ 813 }; 814 815 /** 816 * Maximum number of ops in read modify write sequence. 817 */ 818 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 819 820 /** 821 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 822 */ 823 struct dmub_rb_cmd_read_modify_write { 824 struct dmub_cmd_header header; /**< command header */ 825 /** 826 * Read modify write sequence. 827 */ 828 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 829 }; 830 831 /* 832 * Update a register with specified masks and values sequeunce 833 * 834 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 835 * 836 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 837 * 838 * 839 * USE CASE: 840 * 1. auto-increment register where additional read would update pointer and produce wrong result 841 * 2. toggle a bit without read in the middle 842 */ 843 844 struct dmub_cmd_reg_field_update_sequence { 845 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 846 uint32_t modify_value; /**< value to update with */ 847 }; 848 849 /** 850 * Maximum number of ops in field update sequence. 851 */ 852 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 853 854 /** 855 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 856 */ 857 struct dmub_rb_cmd_reg_field_update_sequence { 858 struct dmub_cmd_header header; /**< command header */ 859 uint32_t addr; /**< register address */ 860 /** 861 * Field update sequence. 862 */ 863 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 864 }; 865 866 867 /** 868 * Maximum number of burst write values. 869 */ 870 #define DMUB_BURST_WRITE_VALUES__MAX 14 871 872 /* 873 * struct dmub_rb_cmd_burst_write - Burst write 874 * 875 * support use case such as writing out LUTs. 876 * 877 * 60 payload bytes can hold up to 14 values to write to given address 878 * 879 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 880 */ 881 struct dmub_rb_cmd_burst_write { 882 struct dmub_cmd_header header; /**< command header */ 883 uint32_t addr; /**< register start address */ 884 /** 885 * Burst write register values. 886 */ 887 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 888 }; 889 890 /** 891 * struct dmub_rb_cmd_common - Common command header 892 */ 893 struct dmub_rb_cmd_common { 894 struct dmub_cmd_header header; /**< command header */ 895 /** 896 * Padding to RB_CMD_SIZE 897 */ 898 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 899 }; 900 901 /** 902 * struct dmub_cmd_reg_wait_data - Register wait data 903 */ 904 struct dmub_cmd_reg_wait_data { 905 uint32_t addr; /**< Register address */ 906 uint32_t mask; /**< Mask for register bits */ 907 uint32_t condition_field_value; /**< Value to wait for */ 908 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 909 }; 910 911 /** 912 * struct dmub_rb_cmd_reg_wait - Register wait command 913 */ 914 struct dmub_rb_cmd_reg_wait { 915 struct dmub_cmd_header header; /**< Command header */ 916 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 917 }; 918 919 /** 920 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 921 * 922 * Reprograms surface parameters to avoid underflow. 923 */ 924 struct dmub_cmd_PLAT_54186_wa { 925 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 926 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 927 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 928 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 929 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 930 struct { 931 uint8_t hubp_inst : 4; /**< HUBP instance */ 932 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 933 uint8_t immediate :1; /**< Immediate flip */ 934 uint8_t vmid : 4; /**< VMID */ 935 uint8_t grph_stereo : 1; /**< 1 if stereo */ 936 uint32_t reserved : 21; /**< Reserved */ 937 } flip_params; /**< Pageflip parameters */ 938 uint32_t reserved[9]; /**< Reserved bits */ 939 }; 940 941 /** 942 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 943 */ 944 struct dmub_rb_cmd_PLAT_54186_wa { 945 struct dmub_cmd_header header; /**< Command header */ 946 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 947 }; 948 949 /** 950 * struct dmub_rb_cmd_mall - MALL command data. 951 */ 952 struct dmub_rb_cmd_mall { 953 struct dmub_cmd_header header; /**< Common command header */ 954 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 955 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 956 uint32_t tmr_delay; /**< Timer delay */ 957 uint32_t tmr_scale; /**< Timer scale */ 958 uint16_t cursor_width; /**< Cursor width in pixels */ 959 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 960 uint16_t cursor_height; /**< Cursor height in pixels */ 961 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 962 uint8_t debug_bits; /**< Debug bits */ 963 964 uint8_t reserved1; /**< Reserved bits */ 965 uint8_t reserved2; /**< Reserved bits */ 966 }; 967 968 /** 969 * enum dmub_cmd_cab_type - TODO: 970 */ 971 enum dmub_cmd_cab_type { 972 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 973 DMUB_CMD__CAB_NO_DCN_REQ = 1, 974 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 975 }; 976 977 /** 978 * struct dmub_rb_cmd_cab_for_ss - TODO: 979 */ 980 struct dmub_rb_cmd_cab_for_ss { 981 struct dmub_cmd_header header; 982 uint8_t cab_alloc_ways; /* total number of ways */ 983 uint8_t debug_bits; /* debug bits */ 984 }; 985 986 enum mclk_switch_mode { 987 NONE = 0, 988 FPO = 1, 989 SUBVP = 2, 990 VBLANK = 3, 991 }; 992 993 /* Per pipe struct which stores the MCLK switch mode 994 * data to be sent to DMUB. 995 * Named "v2" for now -- once FPO and SUBVP are fully merged 996 * the type name can be updated 997 */ 998 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 999 union { 1000 struct { 1001 uint32_t pix_clk_100hz; 1002 uint16_t main_vblank_start; 1003 uint16_t main_vblank_end; 1004 uint16_t mall_region_lines; 1005 uint16_t prefetch_lines; 1006 uint16_t prefetch_to_mall_start_lines; 1007 uint16_t processing_delay_lines; 1008 uint16_t htotal; // required to calculate line time for multi-display cases 1009 uint16_t vtotal; 1010 uint8_t main_pipe_index; 1011 uint8_t phantom_pipe_index; 1012 /* Since the microschedule is calculated in terms of OTG lines, 1013 * include any scaling factors to make sure when we get accurate 1014 * conversion when programming MALL_START_LINE (which is in terms 1015 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1016 * is 1/2 (numerator = 1, denominator = 2). 1017 */ 1018 uint8_t scale_factor_numerator; 1019 uint8_t scale_factor_denominator; 1020 uint8_t is_drr; 1021 uint8_t main_split_pipe_index; 1022 uint8_t phantom_split_pipe_index; 1023 } subvp_data; 1024 1025 struct { 1026 uint32_t pix_clk_100hz; 1027 uint16_t vblank_start; 1028 uint16_t vblank_end; 1029 uint16_t vstartup_start; 1030 uint16_t vtotal; 1031 uint16_t htotal; 1032 uint8_t vblank_pipe_index; 1033 uint8_t padding[1]; 1034 struct { 1035 uint8_t drr_in_use; 1036 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1037 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1038 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1039 uint8_t use_ramping; // Use ramping or not 1040 uint8_t drr_vblank_start_margin; 1041 } drr_info; // DRR considered as part of SubVP + VBLANK case 1042 } vblank_data; 1043 } pipe_config; 1044 1045 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1046 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1047 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1048 */ 1049 uint8_t mode; // enum mclk_switch_mode 1050 }; 1051 1052 /** 1053 * Config data for Sub-VP and FPO 1054 * Named "v2" for now -- once FPO and SUBVP are fully merged 1055 * the type name can be updated 1056 */ 1057 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1058 uint16_t watermark_a_cache; 1059 uint8_t vertical_int_margin_us; 1060 uint8_t pstate_allow_width_us; 1061 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1062 }; 1063 1064 /** 1065 * DMUB rb command definition for Sub-VP and FPO 1066 * Named "v2" for now -- once FPO and SUBVP are fully merged 1067 * the type name can be updated 1068 */ 1069 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1070 struct dmub_cmd_header header; 1071 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1072 }; 1073 1074 /** 1075 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1076 */ 1077 enum dmub_cmd_idle_opt_type { 1078 /** 1079 * DCN hardware restore. 1080 */ 1081 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1082 1083 /** 1084 * DCN hardware save. 1085 */ 1086 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1087 }; 1088 1089 /** 1090 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1091 */ 1092 struct dmub_rb_cmd_idle_opt_dcn_restore { 1093 struct dmub_cmd_header header; /**< header */ 1094 }; 1095 1096 /** 1097 * struct dmub_clocks - Clock update notification. 1098 */ 1099 struct dmub_clocks { 1100 uint32_t dispclk_khz; /**< dispclk kHz */ 1101 uint32_t dppclk_khz; /**< dppclk kHz */ 1102 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1103 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1104 }; 1105 1106 /** 1107 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1108 */ 1109 enum dmub_cmd_clk_mgr_type { 1110 /** 1111 * Notify DMCUB of clock update. 1112 */ 1113 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1114 }; 1115 1116 /** 1117 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1118 */ 1119 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1120 struct dmub_cmd_header header; /**< header */ 1121 struct dmub_clocks clocks; /**< clock data */ 1122 }; 1123 1124 /** 1125 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1126 */ 1127 struct dmub_cmd_digx_encoder_control_data { 1128 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1129 }; 1130 1131 /** 1132 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1133 */ 1134 struct dmub_rb_cmd_digx_encoder_control { 1135 struct dmub_cmd_header header; /**< header */ 1136 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1137 }; 1138 1139 /** 1140 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1141 */ 1142 struct dmub_cmd_set_pixel_clock_data { 1143 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1144 }; 1145 1146 /** 1147 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1148 */ 1149 struct dmub_rb_cmd_set_pixel_clock { 1150 struct dmub_cmd_header header; /**< header */ 1151 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1152 }; 1153 1154 /** 1155 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1156 */ 1157 struct dmub_cmd_enable_disp_power_gating_data { 1158 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1159 }; 1160 1161 /** 1162 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1163 */ 1164 struct dmub_rb_cmd_enable_disp_power_gating { 1165 struct dmub_cmd_header header; /**< header */ 1166 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1167 }; 1168 1169 /** 1170 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1171 */ 1172 struct dmub_dig_transmitter_control_data_v1_7 { 1173 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1174 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1175 union { 1176 uint8_t digmode; /**< enum atom_encode_mode_def */ 1177 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1178 } mode_laneset; 1179 uint8_t lanenum; /**< Number of lanes */ 1180 union { 1181 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1182 } symclk_units; 1183 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1184 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1185 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1186 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1187 uint8_t reserved1; /**< For future use */ 1188 uint8_t reserved2[3]; /**< For future use */ 1189 uint32_t reserved3[11]; /**< For future use */ 1190 }; 1191 1192 /** 1193 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1194 */ 1195 union dmub_cmd_dig1_transmitter_control_data { 1196 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1197 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1198 }; 1199 1200 /** 1201 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1202 */ 1203 struct dmub_rb_cmd_dig1_transmitter_control { 1204 struct dmub_cmd_header header; /**< header */ 1205 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1206 }; 1207 1208 /** 1209 * DPIA tunnel command parameters. 1210 */ 1211 struct dmub_cmd_dig_dpia_control_data { 1212 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1213 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1214 union { 1215 uint8_t digmode; /** enum atom_encode_mode_def */ 1216 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1217 } mode_laneset; 1218 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1219 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1220 uint8_t hpdsel; /** =0: HPD is not assigned */ 1221 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1222 uint8_t dpia_id; /** Index of DPIA */ 1223 uint8_t fec_rdy : 1; 1224 uint8_t reserved : 7; 1225 uint32_t reserved1; 1226 }; 1227 1228 /** 1229 * DMUB command for DPIA tunnel control. 1230 */ 1231 struct dmub_rb_cmd_dig1_dpia_control { 1232 struct dmub_cmd_header header; 1233 struct dmub_cmd_dig_dpia_control_data dpia_control; 1234 }; 1235 1236 /** 1237 * SET_CONFIG Command Payload 1238 */ 1239 struct set_config_cmd_payload { 1240 uint8_t msg_type; /* set config message type */ 1241 uint8_t msg_data; /* set config message data */ 1242 }; 1243 1244 /** 1245 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1246 */ 1247 struct dmub_cmd_set_config_control_data { 1248 struct set_config_cmd_payload cmd_pkt; 1249 uint8_t instance; /* DPIA instance */ 1250 uint8_t immed_status; /* Immediate status returned in case of error */ 1251 }; 1252 1253 /** 1254 * DMUB command structure for SET_CONFIG command. 1255 */ 1256 struct dmub_rb_cmd_set_config_access { 1257 struct dmub_cmd_header header; /* header */ 1258 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1259 }; 1260 1261 /** 1262 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1263 */ 1264 struct dmub_cmd_mst_alloc_slots_control_data { 1265 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1266 uint8_t instance; /* DPIA instance */ 1267 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1268 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1269 }; 1270 1271 /** 1272 * DMUB command structure for SET_ command. 1273 */ 1274 struct dmub_rb_cmd_set_mst_alloc_slots { 1275 struct dmub_cmd_header header; /* header */ 1276 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1277 }; 1278 1279 /** 1280 * DMUB command structure for DPIA HPD int enable control. 1281 */ 1282 struct dmub_rb_cmd_dpia_hpd_int_enable { 1283 struct dmub_cmd_header header; /* header */ 1284 uint32_t enable; /* dpia hpd interrupt enable */ 1285 }; 1286 1287 /** 1288 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1289 */ 1290 struct dmub_rb_cmd_dpphy_init { 1291 struct dmub_cmd_header header; /**< header */ 1292 uint8_t reserved[60]; /**< reserved bits */ 1293 }; 1294 1295 /** 1296 * enum dp_aux_request_action - DP AUX request command listing. 1297 * 1298 * 4 AUX request command bits are shifted to high nibble. 1299 */ 1300 enum dp_aux_request_action { 1301 /** I2C-over-AUX write request */ 1302 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1303 /** I2C-over-AUX read request */ 1304 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1305 /** I2C-over-AUX write status request */ 1306 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1307 /** I2C-over-AUX write request with MOT=1 */ 1308 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1309 /** I2C-over-AUX read request with MOT=1 */ 1310 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1311 /** I2C-over-AUX write status request with MOT=1 */ 1312 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1313 /** Native AUX write request */ 1314 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1315 /** Native AUX read request */ 1316 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1317 }; 1318 1319 /** 1320 * enum aux_return_code_type - DP AUX process return code listing. 1321 */ 1322 enum aux_return_code_type { 1323 /** AUX process succeeded */ 1324 AUX_RET_SUCCESS = 0, 1325 /** AUX process failed with unknown reason */ 1326 AUX_RET_ERROR_UNKNOWN, 1327 /** AUX process completed with invalid reply */ 1328 AUX_RET_ERROR_INVALID_REPLY, 1329 /** AUX process timed out */ 1330 AUX_RET_ERROR_TIMEOUT, 1331 /** HPD was low during AUX process */ 1332 AUX_RET_ERROR_HPD_DISCON, 1333 /** Failed to acquire AUX engine */ 1334 AUX_RET_ERROR_ENGINE_ACQUIRE, 1335 /** AUX request not supported */ 1336 AUX_RET_ERROR_INVALID_OPERATION, 1337 /** AUX process not available */ 1338 AUX_RET_ERROR_PROTOCOL_ERROR, 1339 }; 1340 1341 /** 1342 * enum aux_channel_type - DP AUX channel type listing. 1343 */ 1344 enum aux_channel_type { 1345 /** AUX thru Legacy DP AUX */ 1346 AUX_CHANNEL_LEGACY_DDC, 1347 /** AUX thru DPIA DP tunneling */ 1348 AUX_CHANNEL_DPIA 1349 }; 1350 1351 /** 1352 * struct aux_transaction_parameters - DP AUX request transaction data 1353 */ 1354 struct aux_transaction_parameters { 1355 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1356 uint8_t action; /**< enum dp_aux_request_action */ 1357 uint8_t length; /**< DP AUX request data length */ 1358 uint8_t reserved; /**< For future use */ 1359 uint32_t address; /**< DP AUX address */ 1360 uint8_t data[16]; /**< DP AUX write data */ 1361 }; 1362 1363 /** 1364 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1365 */ 1366 struct dmub_cmd_dp_aux_control_data { 1367 uint8_t instance; /**< AUX instance or DPIA instance */ 1368 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1369 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1370 uint8_t reserved0; /**< For future use */ 1371 uint16_t timeout; /**< timeout time in us */ 1372 uint16_t reserved1; /**< For future use */ 1373 enum aux_channel_type type; /**< enum aux_channel_type */ 1374 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1375 }; 1376 1377 /** 1378 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1379 */ 1380 struct dmub_rb_cmd_dp_aux_access { 1381 /** 1382 * Command header. 1383 */ 1384 struct dmub_cmd_header header; 1385 /** 1386 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1387 */ 1388 struct dmub_cmd_dp_aux_control_data aux_control; 1389 }; 1390 1391 /** 1392 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1393 */ 1394 struct dmub_rb_cmd_outbox1_enable { 1395 /** 1396 * Command header. 1397 */ 1398 struct dmub_cmd_header header; 1399 /** 1400 * enable: 0x0 -> disable outbox1 notification (default value) 1401 * 0x1 -> enable outbox1 notification 1402 */ 1403 uint32_t enable; 1404 }; 1405 1406 /* DP AUX Reply command - OutBox Cmd */ 1407 /** 1408 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1409 */ 1410 struct aux_reply_data { 1411 /** 1412 * Aux cmd 1413 */ 1414 uint8_t command; 1415 /** 1416 * Aux reply data length (max: 16 bytes) 1417 */ 1418 uint8_t length; 1419 /** 1420 * Alignment only 1421 */ 1422 uint8_t pad[2]; 1423 /** 1424 * Aux reply data 1425 */ 1426 uint8_t data[16]; 1427 }; 1428 1429 /** 1430 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1431 */ 1432 struct aux_reply_control_data { 1433 /** 1434 * Reserved for future use 1435 */ 1436 uint32_t handle; 1437 /** 1438 * Aux Instance 1439 */ 1440 uint8_t instance; 1441 /** 1442 * Aux transaction result: definition in enum aux_return_code_type 1443 */ 1444 uint8_t result; 1445 /** 1446 * Alignment only 1447 */ 1448 uint16_t pad; 1449 }; 1450 1451 /** 1452 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1453 */ 1454 struct dmub_rb_cmd_dp_aux_reply { 1455 /** 1456 * Command header. 1457 */ 1458 struct dmub_cmd_header header; 1459 /** 1460 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1461 */ 1462 struct aux_reply_control_data control; 1463 /** 1464 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1465 */ 1466 struct aux_reply_data reply_data; 1467 }; 1468 1469 /* DP HPD Notify command - OutBox Cmd */ 1470 /** 1471 * DP HPD Type 1472 */ 1473 enum dp_hpd_type { 1474 /** 1475 * Normal DP HPD 1476 */ 1477 DP_HPD = 0, 1478 /** 1479 * DP HPD short pulse 1480 */ 1481 DP_IRQ 1482 }; 1483 1484 /** 1485 * DP HPD Status 1486 */ 1487 enum dp_hpd_status { 1488 /** 1489 * DP_HPD status low 1490 */ 1491 DP_HPD_UNPLUG = 0, 1492 /** 1493 * DP_HPD status high 1494 */ 1495 DP_HPD_PLUG 1496 }; 1497 1498 /** 1499 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1500 */ 1501 struct dp_hpd_data { 1502 /** 1503 * DP HPD instance 1504 */ 1505 uint8_t instance; 1506 /** 1507 * HPD type 1508 */ 1509 uint8_t hpd_type; 1510 /** 1511 * HPD status: only for type: DP_HPD to indicate status 1512 */ 1513 uint8_t hpd_status; 1514 /** 1515 * Alignment only 1516 */ 1517 uint8_t pad; 1518 }; 1519 1520 /** 1521 * DPIA NOTIFICATION Response Type 1522 */ 1523 enum dpia_notify_bw_alloc_status { 1524 1525 DPIA_BW_REQ_FAILED = 0, 1526 DPIA_BW_REQ_SUCCESS, 1527 DPIA_EST_BW_CHANGED, 1528 DPIA_BW_ALLOC_CAPS_CHANGED 1529 }; 1530 1531 /* DMUB_OUT_CMD__DPIA_NOTIFY Reply command - OutBox Cmd */ 1532 /** 1533 * Data passed to driver from FW in a DMUB_OUT_CMD__DPIA_NOTIFY command. 1534 */ 1535 struct dpia_notification_reply_data { 1536 uint8_t allocated_bw; 1537 uint8_t estimated_bw; 1538 }; 1539 1540 struct dpia_notification_common { 1541 bool shared; 1542 }; 1543 1544 struct dpia_bw_allocation_notify_data { 1545 union { 1546 struct { 1547 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 1548 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 1549 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 1550 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 1551 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 1552 uint16_t reserved: 11; 1553 } bits; 1554 uint16_t flags; 1555 }; 1556 uint8_t cm_id; /**< CM ID */ 1557 uint8_t group_id; /**< Group ID */ 1558 uint8_t granularity; /**< BW Allocation Granularity */ 1559 uint8_t estimated_bw; /**< Estimated_BW */ 1560 uint8_t allocated_bw; /**< Allocated_BW */ 1561 uint8_t reserved; 1562 }; 1563 1564 union dpia_notification_data { 1565 struct dpia_notification_common common_data; 1566 struct dpia_bw_allocation_notify_data dpia_bw_alloc; /**< Used for DPIA BW Allocation mode notification */ 1567 }; 1568 1569 enum dmub_cmd_dpia_notification_type { 1570 DPIA_NOTIFY__BW_ALLOCATION = 0, 1571 }; 1572 1573 struct dpia_notification_header { 1574 uint8_t instance; /**< DPIA Instance */ 1575 uint8_t reserved[3]; 1576 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 1577 }; 1578 1579 struct dpia_notification_payload { 1580 struct dpia_notification_header header; 1581 union dpia_notification_data data; /**< DPIA notification data */ 1582 }; 1583 1584 /** 1585 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFY command. 1586 */ 1587 struct dmub_rb_cmd_dpia_notification { 1588 /** 1589 * Command header. 1590 */ 1591 struct dmub_cmd_header header; /**< DPIA notification header */ 1592 /** 1593 * Data passed to driver from FW in a DMUB_OUT_CMD__DPIA_NOTIFY command. 1594 */ 1595 struct dpia_notification_payload payload; /**< DPIA notification payload */ 1596 }; 1597 1598 /** 1599 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1600 */ 1601 struct dmub_rb_cmd_dp_hpd_notify { 1602 /** 1603 * Command header. 1604 */ 1605 struct dmub_cmd_header header; 1606 /** 1607 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1608 */ 1609 struct dp_hpd_data hpd_data; 1610 }; 1611 1612 /** 1613 * Definition of a SET_CONFIG reply from DPOA. 1614 */ 1615 enum set_config_status { 1616 SET_CONFIG_PENDING = 0, 1617 SET_CONFIG_ACK_RECEIVED, 1618 SET_CONFIG_RX_TIMEOUT, 1619 SET_CONFIG_UNKNOWN_ERROR, 1620 }; 1621 1622 /** 1623 * Definition of a set_config reply 1624 */ 1625 struct set_config_reply_control_data { 1626 uint8_t instance; /* DPIA Instance */ 1627 uint8_t status; /* Set Config reply */ 1628 uint16_t pad; /* Alignment */ 1629 }; 1630 1631 /** 1632 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1633 */ 1634 struct dmub_rb_cmd_dp_set_config_reply { 1635 struct dmub_cmd_header header; 1636 struct set_config_reply_control_data set_config_reply_control; 1637 }; 1638 1639 /** 1640 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1641 */ 1642 struct dmub_cmd_hpd_state_query_data { 1643 uint8_t instance; /**< HPD instance or DPIA instance */ 1644 uint8_t result; /**< For returning HPD state */ 1645 uint16_t pad; /** < Alignment */ 1646 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1647 enum aux_return_code_type status; /**< for returning the status of command */ 1648 }; 1649 1650 /** 1651 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1652 */ 1653 struct dmub_rb_cmd_query_hpd_state { 1654 /** 1655 * Command header. 1656 */ 1657 struct dmub_cmd_header header; 1658 /** 1659 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1660 */ 1661 struct dmub_cmd_hpd_state_query_data data; 1662 }; 1663 1664 /* 1665 * Command IDs should be treated as stable ABI. 1666 * Do not reuse or modify IDs. 1667 */ 1668 1669 /** 1670 * PSR command sub-types. 1671 */ 1672 enum dmub_cmd_psr_type { 1673 /** 1674 * Set PSR version support. 1675 */ 1676 DMUB_CMD__PSR_SET_VERSION = 0, 1677 /** 1678 * Copy driver-calculated parameters to PSR state. 1679 */ 1680 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1681 /** 1682 * Enable PSR. 1683 */ 1684 DMUB_CMD__PSR_ENABLE = 2, 1685 1686 /** 1687 * Disable PSR. 1688 */ 1689 DMUB_CMD__PSR_DISABLE = 3, 1690 1691 /** 1692 * Set PSR level. 1693 * PSR level is a 16-bit value dicated by driver that 1694 * will enable/disable different functionality. 1695 */ 1696 DMUB_CMD__PSR_SET_LEVEL = 4, 1697 1698 /** 1699 * Forces PSR enabled until an explicit PSR disable call. 1700 */ 1701 DMUB_CMD__PSR_FORCE_STATIC = 5, 1702 /** 1703 * Set vtotal in psr active for FreeSync PSR. 1704 */ 1705 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1706 /** 1707 * Set PSR power option 1708 */ 1709 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1710 }; 1711 1712 enum dmub_cmd_fams_type { 1713 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1714 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1715 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1716 /** 1717 * For SubVP set manual trigger in FW because it 1718 * triggers DRR_UPDATE_PENDING which SubVP relies 1719 * on (for any SubVP cases that use a DRR display) 1720 */ 1721 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1722 }; 1723 1724 /** 1725 * PSR versions. 1726 */ 1727 enum psr_version { 1728 /** 1729 * PSR version 1. 1730 */ 1731 PSR_VERSION_1 = 0, 1732 /** 1733 * Freesync PSR SU. 1734 */ 1735 PSR_VERSION_SU_1 = 1, 1736 /** 1737 * PSR not supported. 1738 */ 1739 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1740 }; 1741 1742 /** 1743 * enum dmub_cmd_mall_type - MALL commands 1744 */ 1745 enum dmub_cmd_mall_type { 1746 /** 1747 * Allows display refresh from MALL. 1748 */ 1749 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1750 /** 1751 * Disallows display refresh from MALL. 1752 */ 1753 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1754 /** 1755 * Cursor copy for MALL. 1756 */ 1757 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1758 /** 1759 * Controls DF requests. 1760 */ 1761 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1762 }; 1763 1764 /** 1765 * PHY Link rate for DP. 1766 */ 1767 enum phy_link_rate { 1768 /** 1769 * not supported. 1770 */ 1771 PHY_RATE_UNKNOWN = 0, 1772 /** 1773 * Rate_1 (RBR) - 1.62 Gbps/Lane 1774 */ 1775 PHY_RATE_162 = 1, 1776 /** 1777 * Rate_2 - 2.16 Gbps/Lane 1778 */ 1779 PHY_RATE_216 = 2, 1780 /** 1781 * Rate_3 - 2.43 Gbps/Lane 1782 */ 1783 PHY_RATE_243 = 3, 1784 /** 1785 * Rate_4 (HBR) - 2.70 Gbps/Lane 1786 */ 1787 PHY_RATE_270 = 4, 1788 /** 1789 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1790 */ 1791 PHY_RATE_324 = 5, 1792 /** 1793 * Rate_6 - 4.32 Gbps/Lane 1794 */ 1795 PHY_RATE_432 = 6, 1796 /** 1797 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1798 */ 1799 PHY_RATE_540 = 7, 1800 /** 1801 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1802 */ 1803 PHY_RATE_810 = 8, 1804 /** 1805 * UHBR10 - 10.0 Gbps/Lane 1806 */ 1807 PHY_RATE_1000 = 9, 1808 /** 1809 * UHBR13.5 - 13.5 Gbps/Lane 1810 */ 1811 PHY_RATE_1350 = 10, 1812 /** 1813 * UHBR10 - 20.0 Gbps/Lane 1814 */ 1815 PHY_RATE_2000 = 11, 1816 }; 1817 1818 /** 1819 * enum dmub_phy_fsm_state - PHY FSM states. 1820 * PHY FSM state to transit to during PSR enable/disable. 1821 */ 1822 enum dmub_phy_fsm_state { 1823 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1824 DMUB_PHY_FSM_RESET, 1825 DMUB_PHY_FSM_RESET_RELEASED, 1826 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1827 DMUB_PHY_FSM_INITIALIZED, 1828 DMUB_PHY_FSM_CALIBRATED, 1829 DMUB_PHY_FSM_CALIBRATED_LP, 1830 DMUB_PHY_FSM_CALIBRATED_PG, 1831 DMUB_PHY_FSM_POWER_DOWN, 1832 DMUB_PHY_FSM_PLL_EN, 1833 DMUB_PHY_FSM_TX_EN, 1834 DMUB_PHY_FSM_FAST_LP, 1835 }; 1836 1837 /** 1838 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1839 */ 1840 struct dmub_cmd_psr_copy_settings_data { 1841 /** 1842 * Flags that can be set by driver to change some PSR behaviour. 1843 */ 1844 union dmub_psr_debug_flags debug; 1845 /** 1846 * 16-bit value dicated by driver that will enable/disable different functionality. 1847 */ 1848 uint16_t psr_level; 1849 /** 1850 * DPP HW instance. 1851 */ 1852 uint8_t dpp_inst; 1853 /** 1854 * MPCC HW instance. 1855 * Not used in dmub fw, 1856 * dmub fw will get active opp by reading odm registers. 1857 */ 1858 uint8_t mpcc_inst; 1859 /** 1860 * OPP HW instance. 1861 * Not used in dmub fw, 1862 * dmub fw will get active opp by reading odm registers. 1863 */ 1864 uint8_t opp_inst; 1865 /** 1866 * OTG HW instance. 1867 */ 1868 uint8_t otg_inst; 1869 /** 1870 * DIG FE HW instance. 1871 */ 1872 uint8_t digfe_inst; 1873 /** 1874 * DIG BE HW instance. 1875 */ 1876 uint8_t digbe_inst; 1877 /** 1878 * DP PHY HW instance. 1879 */ 1880 uint8_t dpphy_inst; 1881 /** 1882 * AUX HW instance. 1883 */ 1884 uint8_t aux_inst; 1885 /** 1886 * Determines if SMU optimzations are enabled/disabled. 1887 */ 1888 uint8_t smu_optimizations_en; 1889 /** 1890 * Unused. 1891 * TODO: Remove. 1892 */ 1893 uint8_t frame_delay; 1894 /** 1895 * If RFB setup time is greater than the total VBLANK time, 1896 * it is not possible for the sink to capture the video frame 1897 * in the same frame the SDP is sent. In this case, 1898 * the frame capture indication bit should be set and an extra 1899 * static frame should be transmitted to the sink. 1900 */ 1901 uint8_t frame_cap_ind; 1902 /** 1903 * Granularity of Y offset supported by sink. 1904 */ 1905 uint8_t su_y_granularity; 1906 /** 1907 * Indicates whether sink should start capturing 1908 * immediately following active scan line, 1909 * or starting with the 2nd active scan line. 1910 */ 1911 uint8_t line_capture_indication; 1912 /** 1913 * Multi-display optimizations are implemented on certain ASICs. 1914 */ 1915 uint8_t multi_disp_optimizations_en; 1916 /** 1917 * The last possible line SDP may be transmitted without violating 1918 * the RFB setup time or entering the active video frame. 1919 */ 1920 uint16_t init_sdp_deadline; 1921 /** 1922 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1923 */ 1924 uint8_t rate_control_caps ; 1925 /* 1926 * Force PSRSU always doing full frame update 1927 */ 1928 uint8_t force_ffu_mode; 1929 /** 1930 * Length of each horizontal line in us. 1931 */ 1932 uint32_t line_time_in_us; 1933 /** 1934 * FEC enable status in driver 1935 */ 1936 uint8_t fec_enable_status; 1937 /** 1938 * FEC re-enable delay when PSR exit. 1939 * unit is 100us, range form 0~255(0xFF). 1940 */ 1941 uint8_t fec_enable_delay_in100us; 1942 /** 1943 * PSR control version. 1944 */ 1945 uint8_t cmd_version; 1946 /** 1947 * Panel Instance. 1948 * Panel isntance to identify which psr_state to use 1949 * Currently the support is only for 0 or 1 1950 */ 1951 uint8_t panel_inst; 1952 /* 1953 * DSC enable status in driver 1954 */ 1955 uint8_t dsc_enable_status; 1956 /* 1957 * Use FSM state for PSR power up/down 1958 */ 1959 uint8_t use_phy_fsm; 1960 /** 1961 * frame delay for frame re-lock 1962 */ 1963 uint8_t relock_delay_frame_cnt; 1964 /** 1965 * Explicit padding to 2 byte boundary. 1966 */ 1967 uint8_t pad3; 1968 }; 1969 1970 /** 1971 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1972 */ 1973 struct dmub_rb_cmd_psr_copy_settings { 1974 /** 1975 * Command header. 1976 */ 1977 struct dmub_cmd_header header; 1978 /** 1979 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1980 */ 1981 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1982 }; 1983 1984 /** 1985 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1986 */ 1987 struct dmub_cmd_psr_set_level_data { 1988 /** 1989 * 16-bit value dicated by driver that will enable/disable different functionality. 1990 */ 1991 uint16_t psr_level; 1992 /** 1993 * PSR control version. 1994 */ 1995 uint8_t cmd_version; 1996 /** 1997 * Panel Instance. 1998 * Panel isntance to identify which psr_state to use 1999 * Currently the support is only for 0 or 1 2000 */ 2001 uint8_t panel_inst; 2002 }; 2003 2004 /** 2005 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2006 */ 2007 struct dmub_rb_cmd_psr_set_level { 2008 /** 2009 * Command header. 2010 */ 2011 struct dmub_cmd_header header; 2012 /** 2013 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2014 */ 2015 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2016 }; 2017 2018 struct dmub_rb_cmd_psr_enable_data { 2019 /** 2020 * PSR control version. 2021 */ 2022 uint8_t cmd_version; 2023 /** 2024 * Panel Instance. 2025 * Panel isntance to identify which psr_state to use 2026 * Currently the support is only for 0 or 1 2027 */ 2028 uint8_t panel_inst; 2029 /** 2030 * Phy state to enter. 2031 * Values to use are defined in dmub_phy_fsm_state 2032 */ 2033 uint8_t phy_fsm_state; 2034 /** 2035 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2036 * Set this using enum phy_link_rate. 2037 * This does not support HDMI/DP2 for now. 2038 */ 2039 uint8_t phy_rate; 2040 }; 2041 2042 /** 2043 * Definition of a DMUB_CMD__PSR_ENABLE command. 2044 * PSR enable/disable is controlled using the sub_type. 2045 */ 2046 struct dmub_rb_cmd_psr_enable { 2047 /** 2048 * Command header. 2049 */ 2050 struct dmub_cmd_header header; 2051 2052 struct dmub_rb_cmd_psr_enable_data data; 2053 }; 2054 2055 /** 2056 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2057 */ 2058 struct dmub_cmd_psr_set_version_data { 2059 /** 2060 * PSR version that FW should implement. 2061 */ 2062 enum psr_version version; 2063 /** 2064 * PSR control version. 2065 */ 2066 uint8_t cmd_version; 2067 /** 2068 * Panel Instance. 2069 * Panel isntance to identify which psr_state to use 2070 * Currently the support is only for 0 or 1 2071 */ 2072 uint8_t panel_inst; 2073 /** 2074 * Explicit padding to 4 byte boundary. 2075 */ 2076 uint8_t pad[2]; 2077 }; 2078 2079 /** 2080 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2081 */ 2082 struct dmub_rb_cmd_psr_set_version { 2083 /** 2084 * Command header. 2085 */ 2086 struct dmub_cmd_header header; 2087 /** 2088 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2089 */ 2090 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2091 }; 2092 2093 struct dmub_cmd_psr_force_static_data { 2094 /** 2095 * PSR control version. 2096 */ 2097 uint8_t cmd_version; 2098 /** 2099 * Panel Instance. 2100 * Panel isntance to identify which psr_state to use 2101 * Currently the support is only for 0 or 1 2102 */ 2103 uint8_t panel_inst; 2104 /** 2105 * Explicit padding to 4 byte boundary. 2106 */ 2107 uint8_t pad[2]; 2108 }; 2109 2110 /** 2111 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2112 */ 2113 struct dmub_rb_cmd_psr_force_static { 2114 /** 2115 * Command header. 2116 */ 2117 struct dmub_cmd_header header; 2118 /** 2119 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2120 */ 2121 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2122 }; 2123 2124 /** 2125 * PSR SU debug flags. 2126 */ 2127 union dmub_psr_su_debug_flags { 2128 /** 2129 * PSR SU debug flags. 2130 */ 2131 struct { 2132 /** 2133 * Update dirty rect in SW only. 2134 */ 2135 uint8_t update_dirty_rect_only : 1; 2136 /** 2137 * Reset the cursor/plane state before processing the call. 2138 */ 2139 uint8_t reset_state : 1; 2140 } bitfields; 2141 2142 /** 2143 * Union for debug flags. 2144 */ 2145 uint32_t u32All; 2146 }; 2147 2148 /** 2149 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2150 * This triggers a selective update for PSR SU. 2151 */ 2152 struct dmub_cmd_update_dirty_rect_data { 2153 /** 2154 * Dirty rects from OS. 2155 */ 2156 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2157 /** 2158 * PSR SU debug flags. 2159 */ 2160 union dmub_psr_su_debug_flags debug_flags; 2161 /** 2162 * OTG HW instance. 2163 */ 2164 uint8_t pipe_idx; 2165 /** 2166 * Number of dirty rects. 2167 */ 2168 uint8_t dirty_rect_count; 2169 /** 2170 * PSR control version. 2171 */ 2172 uint8_t cmd_version; 2173 /** 2174 * Panel Instance. 2175 * Panel isntance to identify which psr_state to use 2176 * Currently the support is only for 0 or 1 2177 */ 2178 uint8_t panel_inst; 2179 }; 2180 2181 /** 2182 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2183 */ 2184 struct dmub_rb_cmd_update_dirty_rect { 2185 /** 2186 * Command header. 2187 */ 2188 struct dmub_cmd_header header; 2189 /** 2190 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2191 */ 2192 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2193 }; 2194 2195 /** 2196 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2197 */ 2198 union dmub_reg_cursor_control_cfg { 2199 struct { 2200 uint32_t cur_enable: 1; 2201 uint32_t reser0: 3; 2202 uint32_t cur_2x_magnify: 1; 2203 uint32_t reser1: 3; 2204 uint32_t mode: 3; 2205 uint32_t reser2: 5; 2206 uint32_t pitch: 2; 2207 uint32_t reser3: 6; 2208 uint32_t line_per_chunk: 5; 2209 uint32_t reser4: 3; 2210 } bits; 2211 uint32_t raw; 2212 }; 2213 struct dmub_cursor_position_cache_hubp { 2214 union dmub_reg_cursor_control_cfg cur_ctl; 2215 union dmub_reg_position_cfg { 2216 struct { 2217 uint32_t cur_x_pos: 16; 2218 uint32_t cur_y_pos: 16; 2219 } bits; 2220 uint32_t raw; 2221 } position; 2222 union dmub_reg_hot_spot_cfg { 2223 struct { 2224 uint32_t hot_x: 16; 2225 uint32_t hot_y: 16; 2226 } bits; 2227 uint32_t raw; 2228 } hot_spot; 2229 union dmub_reg_dst_offset_cfg { 2230 struct { 2231 uint32_t dst_x_offset: 13; 2232 uint32_t reserved: 19; 2233 } bits; 2234 uint32_t raw; 2235 } dst_offset; 2236 }; 2237 2238 union dmub_reg_cur0_control_cfg { 2239 struct { 2240 uint32_t cur0_enable: 1; 2241 uint32_t expansion_mode: 1; 2242 uint32_t reser0: 1; 2243 uint32_t cur0_rom_en: 1; 2244 uint32_t mode: 3; 2245 uint32_t reserved: 25; 2246 } bits; 2247 uint32_t raw; 2248 }; 2249 struct dmub_cursor_position_cache_dpp { 2250 union dmub_reg_cur0_control_cfg cur0_ctl; 2251 }; 2252 struct dmub_cursor_position_cfg { 2253 struct dmub_cursor_position_cache_hubp pHubp; 2254 struct dmub_cursor_position_cache_dpp pDpp; 2255 uint8_t pipe_idx; 2256 /* 2257 * Padding is required. To be 4 Bytes Aligned. 2258 */ 2259 uint8_t padding[3]; 2260 }; 2261 2262 struct dmub_cursor_attribute_cache_hubp { 2263 uint32_t SURFACE_ADDR_HIGH; 2264 uint32_t SURFACE_ADDR; 2265 union dmub_reg_cursor_control_cfg cur_ctl; 2266 union dmub_reg_cursor_size_cfg { 2267 struct { 2268 uint32_t width: 16; 2269 uint32_t height: 16; 2270 } bits; 2271 uint32_t raw; 2272 } size; 2273 union dmub_reg_cursor_settings_cfg { 2274 struct { 2275 uint32_t dst_y_offset: 8; 2276 uint32_t chunk_hdl_adjust: 2; 2277 uint32_t reserved: 22; 2278 } bits; 2279 uint32_t raw; 2280 } settings; 2281 }; 2282 struct dmub_cursor_attribute_cache_dpp { 2283 union dmub_reg_cur0_control_cfg cur0_ctl; 2284 }; 2285 struct dmub_cursor_attributes_cfg { 2286 struct dmub_cursor_attribute_cache_hubp aHubp; 2287 struct dmub_cursor_attribute_cache_dpp aDpp; 2288 }; 2289 2290 struct dmub_cmd_update_cursor_payload0 { 2291 /** 2292 * Cursor dirty rects. 2293 */ 2294 struct dmub_rect cursor_rect; 2295 /** 2296 * PSR SU debug flags. 2297 */ 2298 union dmub_psr_su_debug_flags debug_flags; 2299 /** 2300 * Cursor enable/disable. 2301 */ 2302 uint8_t enable; 2303 /** 2304 * OTG HW instance. 2305 */ 2306 uint8_t pipe_idx; 2307 /** 2308 * PSR control version. 2309 */ 2310 uint8_t cmd_version; 2311 /** 2312 * Panel Instance. 2313 * Panel isntance to identify which psr_state to use 2314 * Currently the support is only for 0 or 1 2315 */ 2316 uint8_t panel_inst; 2317 /** 2318 * Cursor Position Register. 2319 * Registers contains Hubp & Dpp modules 2320 */ 2321 struct dmub_cursor_position_cfg position_cfg; 2322 }; 2323 2324 struct dmub_cmd_update_cursor_payload1 { 2325 struct dmub_cursor_attributes_cfg attribute_cfg; 2326 }; 2327 2328 union dmub_cmd_update_cursor_info_data { 2329 struct dmub_cmd_update_cursor_payload0 payload0; 2330 struct dmub_cmd_update_cursor_payload1 payload1; 2331 }; 2332 /** 2333 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2334 */ 2335 struct dmub_rb_cmd_update_cursor_info { 2336 /** 2337 * Command header. 2338 */ 2339 struct dmub_cmd_header header; 2340 /** 2341 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2342 */ 2343 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2344 }; 2345 2346 /** 2347 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2348 */ 2349 struct dmub_cmd_psr_set_vtotal_data { 2350 /** 2351 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2352 */ 2353 uint16_t psr_vtotal_idle; 2354 /** 2355 * PSR control version. 2356 */ 2357 uint8_t cmd_version; 2358 /** 2359 * Panel Instance. 2360 * Panel isntance to identify which psr_state to use 2361 * Currently the support is only for 0 or 1 2362 */ 2363 uint8_t panel_inst; 2364 /* 2365 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2366 */ 2367 uint16_t psr_vtotal_su; 2368 /** 2369 * Explicit padding to 4 byte boundary. 2370 */ 2371 uint8_t pad2[2]; 2372 }; 2373 2374 /** 2375 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2376 */ 2377 struct dmub_rb_cmd_psr_set_vtotal { 2378 /** 2379 * Command header. 2380 */ 2381 struct dmub_cmd_header header; 2382 /** 2383 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2384 */ 2385 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2386 }; 2387 2388 /** 2389 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2390 */ 2391 struct dmub_cmd_psr_set_power_opt_data { 2392 /** 2393 * PSR control version. 2394 */ 2395 uint8_t cmd_version; 2396 /** 2397 * Panel Instance. 2398 * Panel isntance to identify which psr_state to use 2399 * Currently the support is only for 0 or 1 2400 */ 2401 uint8_t panel_inst; 2402 /** 2403 * Explicit padding to 4 byte boundary. 2404 */ 2405 uint8_t pad[2]; 2406 /** 2407 * PSR power option 2408 */ 2409 uint32_t power_opt; 2410 }; 2411 2412 /** 2413 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2414 */ 2415 struct dmub_rb_cmd_psr_set_power_opt { 2416 /** 2417 * Command header. 2418 */ 2419 struct dmub_cmd_header header; 2420 /** 2421 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2422 */ 2423 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2424 }; 2425 2426 /** 2427 * Set of HW components that can be locked. 2428 * 2429 * Note: If updating with more HW components, fields 2430 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2431 */ 2432 union dmub_hw_lock_flags { 2433 /** 2434 * Set of HW components that can be locked. 2435 */ 2436 struct { 2437 /** 2438 * Lock/unlock OTG master update lock. 2439 */ 2440 uint8_t lock_pipe : 1; 2441 /** 2442 * Lock/unlock cursor. 2443 */ 2444 uint8_t lock_cursor : 1; 2445 /** 2446 * Lock/unlock global update lock. 2447 */ 2448 uint8_t lock_dig : 1; 2449 /** 2450 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2451 */ 2452 uint8_t triple_buffer_lock : 1; 2453 } bits; 2454 2455 /** 2456 * Union for HW Lock flags. 2457 */ 2458 uint8_t u8All; 2459 }; 2460 2461 /** 2462 * Instances of HW to be locked. 2463 * 2464 * Note: If updating with more HW components, fields 2465 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2466 */ 2467 struct dmub_hw_lock_inst_flags { 2468 /** 2469 * OTG HW instance for OTG master update lock. 2470 */ 2471 uint8_t otg_inst; 2472 /** 2473 * OPP instance for cursor lock. 2474 */ 2475 uint8_t opp_inst; 2476 /** 2477 * OTG HW instance for global update lock. 2478 * TODO: Remove, and re-use otg_inst. 2479 */ 2480 uint8_t dig_inst; 2481 /** 2482 * Explicit pad to 4 byte boundary. 2483 */ 2484 uint8_t pad; 2485 }; 2486 2487 /** 2488 * Clients that can acquire the HW Lock Manager. 2489 * 2490 * Note: If updating with more clients, fields in 2491 * dmub_inbox0_cmd_lock_hw must be updated to match. 2492 */ 2493 enum hw_lock_client { 2494 /** 2495 * Driver is the client of HW Lock Manager. 2496 */ 2497 HW_LOCK_CLIENT_DRIVER = 0, 2498 /** 2499 * PSR SU is the client of HW Lock Manager. 2500 */ 2501 HW_LOCK_CLIENT_PSR_SU = 1, 2502 /** 2503 * Invalid client. 2504 */ 2505 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2506 }; 2507 2508 /** 2509 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2510 */ 2511 struct dmub_cmd_lock_hw_data { 2512 /** 2513 * Specifies the client accessing HW Lock Manager. 2514 */ 2515 enum hw_lock_client client; 2516 /** 2517 * HW instances to be locked. 2518 */ 2519 struct dmub_hw_lock_inst_flags inst_flags; 2520 /** 2521 * Which components to be locked. 2522 */ 2523 union dmub_hw_lock_flags hw_locks; 2524 /** 2525 * Specifies lock/unlock. 2526 */ 2527 uint8_t lock; 2528 /** 2529 * HW can be unlocked separately from releasing the HW Lock Mgr. 2530 * This flag is set if the client wishes to release the object. 2531 */ 2532 uint8_t should_release; 2533 /** 2534 * Explicit padding to 4 byte boundary. 2535 */ 2536 uint8_t pad; 2537 }; 2538 2539 /** 2540 * Definition of a DMUB_CMD__HW_LOCK command. 2541 * Command is used by driver and FW. 2542 */ 2543 struct dmub_rb_cmd_lock_hw { 2544 /** 2545 * Command header. 2546 */ 2547 struct dmub_cmd_header header; 2548 /** 2549 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2550 */ 2551 struct dmub_cmd_lock_hw_data lock_hw_data; 2552 }; 2553 2554 /** 2555 * ABM command sub-types. 2556 */ 2557 enum dmub_cmd_abm_type { 2558 /** 2559 * Initialize parameters for ABM algorithm. 2560 * Data is passed through an indirect buffer. 2561 */ 2562 DMUB_CMD__ABM_INIT_CONFIG = 0, 2563 /** 2564 * Set OTG and panel HW instance. 2565 */ 2566 DMUB_CMD__ABM_SET_PIPE = 1, 2567 /** 2568 * Set user requested backklight level. 2569 */ 2570 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2571 /** 2572 * Set ABM operating/aggression level. 2573 */ 2574 DMUB_CMD__ABM_SET_LEVEL = 3, 2575 /** 2576 * Set ambient light level. 2577 */ 2578 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2579 /** 2580 * Enable/disable fractional duty cycle for backlight PWM. 2581 */ 2582 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2583 2584 /** 2585 * unregister vertical interrupt after steady state is reached 2586 */ 2587 DMUB_CMD__ABM_PAUSE = 6, 2588 }; 2589 2590 /** 2591 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2592 * Requirements: 2593 * - Padded explicitly to 32-bit boundary. 2594 * - Must ensure this structure matches the one on driver-side, 2595 * otherwise it won't be aligned. 2596 */ 2597 struct abm_config_table { 2598 /** 2599 * Gamma curve thresholds, used for crgb conversion. 2600 */ 2601 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2602 /** 2603 * Gamma curve offsets, used for crgb conversion. 2604 */ 2605 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2606 /** 2607 * Gamma curve slopes, used for crgb conversion. 2608 */ 2609 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2610 /** 2611 * Custom backlight curve thresholds. 2612 */ 2613 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2614 /** 2615 * Custom backlight curve offsets. 2616 */ 2617 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2618 /** 2619 * Ambient light thresholds. 2620 */ 2621 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2622 /** 2623 * Minimum programmable backlight. 2624 */ 2625 uint16_t min_abm_backlight; // 122B 2626 /** 2627 * Minimum reduction values. 2628 */ 2629 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2630 /** 2631 * Maximum reduction values. 2632 */ 2633 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2634 /** 2635 * Bright positive gain. 2636 */ 2637 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2638 /** 2639 * Dark negative gain. 2640 */ 2641 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2642 /** 2643 * Hybrid factor. 2644 */ 2645 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2646 /** 2647 * Contrast factor. 2648 */ 2649 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2650 /** 2651 * Deviation gain. 2652 */ 2653 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2654 /** 2655 * Minimum knee. 2656 */ 2657 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2658 /** 2659 * Maximum knee. 2660 */ 2661 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2662 /** 2663 * Unused. 2664 */ 2665 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2666 /** 2667 * Explicit padding to 4 byte boundary. 2668 */ 2669 uint8_t pad3[3]; // 229B 2670 /** 2671 * Backlight ramp reduction. 2672 */ 2673 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2674 /** 2675 * Backlight ramp start. 2676 */ 2677 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2678 }; 2679 2680 /** 2681 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2682 */ 2683 struct dmub_cmd_abm_set_pipe_data { 2684 /** 2685 * OTG HW instance. 2686 */ 2687 uint8_t otg_inst; 2688 2689 /** 2690 * Panel Control HW instance. 2691 */ 2692 uint8_t panel_inst; 2693 2694 /** 2695 * Controls how ABM will interpret a set pipe or set level command. 2696 */ 2697 uint8_t set_pipe_option; 2698 2699 /** 2700 * Unused. 2701 * TODO: Remove. 2702 */ 2703 uint8_t ramping_boundary; 2704 }; 2705 2706 /** 2707 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2708 */ 2709 struct dmub_rb_cmd_abm_set_pipe { 2710 /** 2711 * Command header. 2712 */ 2713 struct dmub_cmd_header header; 2714 2715 /** 2716 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2717 */ 2718 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2719 }; 2720 2721 /** 2722 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2723 */ 2724 struct dmub_cmd_abm_set_backlight_data { 2725 /** 2726 * Number of frames to ramp to backlight user level. 2727 */ 2728 uint32_t frame_ramp; 2729 2730 /** 2731 * Requested backlight level from user. 2732 */ 2733 uint32_t backlight_user_level; 2734 2735 /** 2736 * ABM control version. 2737 */ 2738 uint8_t version; 2739 2740 /** 2741 * Panel Control HW instance mask. 2742 * Bit 0 is Panel Control HW instance 0. 2743 * Bit 1 is Panel Control HW instance 1. 2744 */ 2745 uint8_t panel_mask; 2746 2747 /** 2748 * Explicit padding to 4 byte boundary. 2749 */ 2750 uint8_t pad[2]; 2751 }; 2752 2753 /** 2754 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2755 */ 2756 struct dmub_rb_cmd_abm_set_backlight { 2757 /** 2758 * Command header. 2759 */ 2760 struct dmub_cmd_header header; 2761 2762 /** 2763 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2764 */ 2765 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2766 }; 2767 2768 /** 2769 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2770 */ 2771 struct dmub_cmd_abm_set_level_data { 2772 /** 2773 * Set current ABM operating/aggression level. 2774 */ 2775 uint32_t level; 2776 2777 /** 2778 * ABM control version. 2779 */ 2780 uint8_t version; 2781 2782 /** 2783 * Panel Control HW instance mask. 2784 * Bit 0 is Panel Control HW instance 0. 2785 * Bit 1 is Panel Control HW instance 1. 2786 */ 2787 uint8_t panel_mask; 2788 2789 /** 2790 * Explicit padding to 4 byte boundary. 2791 */ 2792 uint8_t pad[2]; 2793 }; 2794 2795 /** 2796 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2797 */ 2798 struct dmub_rb_cmd_abm_set_level { 2799 /** 2800 * Command header. 2801 */ 2802 struct dmub_cmd_header header; 2803 2804 /** 2805 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2806 */ 2807 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2808 }; 2809 2810 /** 2811 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2812 */ 2813 struct dmub_cmd_abm_set_ambient_level_data { 2814 /** 2815 * Ambient light sensor reading from OS. 2816 */ 2817 uint32_t ambient_lux; 2818 2819 /** 2820 * ABM control version. 2821 */ 2822 uint8_t version; 2823 2824 /** 2825 * Panel Control HW instance mask. 2826 * Bit 0 is Panel Control HW instance 0. 2827 * Bit 1 is Panel Control HW instance 1. 2828 */ 2829 uint8_t panel_mask; 2830 2831 /** 2832 * Explicit padding to 4 byte boundary. 2833 */ 2834 uint8_t pad[2]; 2835 }; 2836 2837 /** 2838 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2839 */ 2840 struct dmub_rb_cmd_abm_set_ambient_level { 2841 /** 2842 * Command header. 2843 */ 2844 struct dmub_cmd_header header; 2845 2846 /** 2847 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2848 */ 2849 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2850 }; 2851 2852 /** 2853 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2854 */ 2855 struct dmub_cmd_abm_set_pwm_frac_data { 2856 /** 2857 * Enable/disable fractional duty cycle for backlight PWM. 2858 * TODO: Convert to uint8_t. 2859 */ 2860 uint32_t fractional_pwm; 2861 2862 /** 2863 * ABM control version. 2864 */ 2865 uint8_t version; 2866 2867 /** 2868 * Panel Control HW instance mask. 2869 * Bit 0 is Panel Control HW instance 0. 2870 * Bit 1 is Panel Control HW instance 1. 2871 */ 2872 uint8_t panel_mask; 2873 2874 /** 2875 * Explicit padding to 4 byte boundary. 2876 */ 2877 uint8_t pad[2]; 2878 }; 2879 2880 /** 2881 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2882 */ 2883 struct dmub_rb_cmd_abm_set_pwm_frac { 2884 /** 2885 * Command header. 2886 */ 2887 struct dmub_cmd_header header; 2888 2889 /** 2890 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2891 */ 2892 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2893 }; 2894 2895 /** 2896 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2897 */ 2898 struct dmub_cmd_abm_init_config_data { 2899 /** 2900 * Location of indirect buffer used to pass init data to ABM. 2901 */ 2902 union dmub_addr src; 2903 2904 /** 2905 * Indirect buffer length. 2906 */ 2907 uint16_t bytes; 2908 2909 2910 /** 2911 * ABM control version. 2912 */ 2913 uint8_t version; 2914 2915 /** 2916 * Panel Control HW instance mask. 2917 * Bit 0 is Panel Control HW instance 0. 2918 * Bit 1 is Panel Control HW instance 1. 2919 */ 2920 uint8_t panel_mask; 2921 2922 /** 2923 * Explicit padding to 4 byte boundary. 2924 */ 2925 uint8_t pad[2]; 2926 }; 2927 2928 /** 2929 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2930 */ 2931 struct dmub_rb_cmd_abm_init_config { 2932 /** 2933 * Command header. 2934 */ 2935 struct dmub_cmd_header header; 2936 2937 /** 2938 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2939 */ 2940 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2941 }; 2942 2943 /** 2944 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2945 */ 2946 2947 struct dmub_cmd_abm_pause_data { 2948 2949 /** 2950 * Panel Control HW instance mask. 2951 * Bit 0 is Panel Control HW instance 0. 2952 * Bit 1 is Panel Control HW instance 1. 2953 */ 2954 uint8_t panel_mask; 2955 2956 /** 2957 * OTG hw instance 2958 */ 2959 uint8_t otg_inst; 2960 2961 /** 2962 * Enable or disable ABM pause 2963 */ 2964 uint8_t enable; 2965 2966 /** 2967 * Explicit padding to 4 byte boundary. 2968 */ 2969 uint8_t pad[1]; 2970 }; 2971 2972 /** 2973 * Definition of a DMUB_CMD__ABM_PAUSE command. 2974 */ 2975 struct dmub_rb_cmd_abm_pause { 2976 /** 2977 * Command header. 2978 */ 2979 struct dmub_cmd_header header; 2980 2981 /** 2982 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2983 */ 2984 struct dmub_cmd_abm_pause_data abm_pause_data; 2985 }; 2986 2987 /** 2988 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2989 */ 2990 struct dmub_cmd_query_feature_caps_data { 2991 /** 2992 * DMUB feature capabilities. 2993 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2994 */ 2995 struct dmub_feature_caps feature_caps; 2996 }; 2997 2998 /** 2999 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3000 */ 3001 struct dmub_rb_cmd_query_feature_caps { 3002 /** 3003 * Command header. 3004 */ 3005 struct dmub_cmd_header header; 3006 /** 3007 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3008 */ 3009 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 3010 }; 3011 3012 /** 3013 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3014 */ 3015 struct dmub_cmd_visual_confirm_color_data { 3016 /** 3017 * DMUB feature capabilities. 3018 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3019 */ 3020 struct dmub_visual_confirm_color visual_confirm_color; 3021 }; 3022 3023 /** 3024 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3025 */ 3026 struct dmub_rb_cmd_get_visual_confirm_color { 3027 /** 3028 * Command header. 3029 */ 3030 struct dmub_cmd_header header; 3031 /** 3032 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3033 */ 3034 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3035 }; 3036 3037 struct dmub_optc_state { 3038 uint32_t v_total_max; 3039 uint32_t v_total_min; 3040 uint32_t tg_inst; 3041 }; 3042 3043 struct dmub_rb_cmd_drr_update { 3044 struct dmub_cmd_header header; 3045 struct dmub_optc_state dmub_optc_state_req; 3046 }; 3047 3048 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 3049 uint32_t pix_clk_100hz; 3050 uint8_t max_ramp_step; 3051 uint8_t pipes; 3052 uint8_t min_refresh_in_hz; 3053 uint8_t padding[1]; 3054 }; 3055 3056 struct dmub_cmd_fw_assisted_mclk_switch_config { 3057 uint8_t fams_enabled; 3058 uint8_t visual_confirm_enabled; 3059 uint8_t padding[2]; 3060 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 3061 }; 3062 3063 struct dmub_rb_cmd_fw_assisted_mclk_switch { 3064 struct dmub_cmd_header header; 3065 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 3066 }; 3067 3068 /** 3069 * enum dmub_cmd_panel_cntl_type - Panel control command. 3070 */ 3071 enum dmub_cmd_panel_cntl_type { 3072 /** 3073 * Initializes embedded panel hardware blocks. 3074 */ 3075 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3076 /** 3077 * Queries backlight info for the embedded panel. 3078 */ 3079 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3080 }; 3081 3082 /** 3083 * struct dmub_cmd_panel_cntl_data - Panel control data. 3084 */ 3085 struct dmub_cmd_panel_cntl_data { 3086 uint32_t inst; /**< panel instance */ 3087 uint32_t current_backlight; /* in/out */ 3088 uint32_t bl_pwm_cntl; /* in/out */ 3089 uint32_t bl_pwm_period_cntl; /* in/out */ 3090 uint32_t bl_pwm_ref_div1; /* in/out */ 3091 uint8_t is_backlight_on : 1; /* in/out */ 3092 uint8_t is_powered_on : 1; /* in/out */ 3093 uint8_t padding[3]; 3094 uint32_t bl_pwm_ref_div2; /* in/out */ 3095 uint8_t reserved[4]; 3096 }; 3097 3098 /** 3099 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3100 */ 3101 struct dmub_rb_cmd_panel_cntl { 3102 struct dmub_cmd_header header; /**< header */ 3103 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3104 }; 3105 3106 /** 3107 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3108 */ 3109 struct dmub_cmd_lvtma_control_data { 3110 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3111 uint8_t reserved_0[3]; /**< For future use */ 3112 uint8_t panel_inst; /**< LVTMA control instance */ 3113 uint8_t reserved_1[3]; /**< For future use */ 3114 }; 3115 3116 /** 3117 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3118 */ 3119 struct dmub_rb_cmd_lvtma_control { 3120 /** 3121 * Command header. 3122 */ 3123 struct dmub_cmd_header header; 3124 /** 3125 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3126 */ 3127 struct dmub_cmd_lvtma_control_data data; 3128 }; 3129 3130 /** 3131 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3132 */ 3133 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3134 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3135 uint8_t is_usb; /**< is phy is usb */ 3136 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3137 uint8_t is_dp4; /**< is dp in 4 lane */ 3138 }; 3139 3140 /** 3141 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3142 */ 3143 struct dmub_rb_cmd_transmitter_query_dp_alt { 3144 struct dmub_cmd_header header; /**< header */ 3145 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3146 }; 3147 3148 /** 3149 * Maximum number of bytes a chunk sent to DMUB for parsing 3150 */ 3151 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3152 3153 /** 3154 * Represent a chunk of CEA blocks sent to DMUB for parsing 3155 */ 3156 struct dmub_cmd_send_edid_cea { 3157 uint16_t offset; /**< offset into the CEA block */ 3158 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3159 uint16_t cea_total_length; /**< total length of the CEA block */ 3160 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3161 uint8_t pad[3]; /**< padding and for future expansion */ 3162 }; 3163 3164 /** 3165 * Result of VSDB parsing from CEA block 3166 */ 3167 struct dmub_cmd_edid_cea_amd_vsdb { 3168 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3169 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3170 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3171 uint16_t min_frame_rate; /**< Maximum frame rate */ 3172 uint16_t max_frame_rate; /**< Minimum frame rate */ 3173 }; 3174 3175 /** 3176 * Result of sending a CEA chunk 3177 */ 3178 struct dmub_cmd_edid_cea_ack { 3179 uint16_t offset; /**< offset of the chunk into the CEA block */ 3180 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3181 uint8_t pad; /**< padding and for future expansion */ 3182 }; 3183 3184 /** 3185 * Specify whether the result is an ACK/NACK or the parsing has finished 3186 */ 3187 enum dmub_cmd_edid_cea_reply_type { 3188 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3189 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3190 }; 3191 3192 /** 3193 * Definition of a DMUB_CMD__EDID_CEA command. 3194 */ 3195 struct dmub_rb_cmd_edid_cea { 3196 struct dmub_cmd_header header; /**< Command header */ 3197 union dmub_cmd_edid_cea_data { 3198 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3199 struct dmub_cmd_edid_cea_output { /**< output with results */ 3200 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3201 union { 3202 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3203 struct dmub_cmd_edid_cea_ack ack; 3204 }; 3205 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3206 } data; /**< Command data */ 3207 3208 }; 3209 3210 /** 3211 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3212 */ 3213 struct dmub_cmd_cable_id_input { 3214 uint8_t phy_inst; /**< phy inst for cable id data */ 3215 }; 3216 3217 /** 3218 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3219 */ 3220 struct dmub_cmd_cable_id_output { 3221 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3222 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3223 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3224 uint8_t RESERVED :2; /**< reserved means not defined */ 3225 }; 3226 3227 /** 3228 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3229 */ 3230 struct dmub_rb_cmd_get_usbc_cable_id { 3231 struct dmub_cmd_header header; /**< Command header */ 3232 /** 3233 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3234 */ 3235 union dmub_cmd_cable_id_data { 3236 struct dmub_cmd_cable_id_input input; /**< Input */ 3237 struct dmub_cmd_cable_id_output output; /**< Output */ 3238 uint8_t output_raw; /**< Raw data output */ 3239 } data; 3240 }; 3241 3242 /** 3243 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3244 */ 3245 enum dmub_cmd_secure_display_type { 3246 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3247 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3248 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3249 }; 3250 3251 /** 3252 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3253 */ 3254 struct dmub_rb_cmd_secure_display { 3255 struct dmub_cmd_header header; 3256 /** 3257 * Data passed from driver to dmub firmware. 3258 */ 3259 struct dmub_cmd_roi_info { 3260 uint16_t x_start; 3261 uint16_t x_end; 3262 uint16_t y_start; 3263 uint16_t y_end; 3264 uint8_t otg_id; 3265 uint8_t phy_id; 3266 } roi_info; 3267 }; 3268 3269 /** 3270 * union dmub_rb_cmd - DMUB inbox command. 3271 */ 3272 union dmub_rb_cmd { 3273 /** 3274 * Elements shared with all commands. 3275 */ 3276 struct dmub_rb_cmd_common cmd_common; 3277 /** 3278 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3279 */ 3280 struct dmub_rb_cmd_read_modify_write read_modify_write; 3281 /** 3282 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3283 */ 3284 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3285 /** 3286 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3287 */ 3288 struct dmub_rb_cmd_burst_write burst_write; 3289 /** 3290 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3291 */ 3292 struct dmub_rb_cmd_reg_wait reg_wait; 3293 /** 3294 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3295 */ 3296 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3297 /** 3298 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3299 */ 3300 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3301 /** 3302 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3303 */ 3304 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3305 /** 3306 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3307 */ 3308 struct dmub_rb_cmd_dpphy_init dpphy_init; 3309 /** 3310 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3311 */ 3312 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3313 /** 3314 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3315 */ 3316 struct dmub_rb_cmd_psr_set_version psr_set_version; 3317 /** 3318 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3319 */ 3320 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3321 /** 3322 * Definition of a DMUB_CMD__PSR_ENABLE command. 3323 */ 3324 struct dmub_rb_cmd_psr_enable psr_enable; 3325 /** 3326 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3327 */ 3328 struct dmub_rb_cmd_psr_set_level psr_set_level; 3329 /** 3330 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3331 */ 3332 struct dmub_rb_cmd_psr_force_static psr_force_static; 3333 /** 3334 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3335 */ 3336 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3337 /** 3338 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3339 */ 3340 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3341 /** 3342 * Definition of a DMUB_CMD__HW_LOCK command. 3343 * Command is used by driver and FW. 3344 */ 3345 struct dmub_rb_cmd_lock_hw lock_hw; 3346 /** 3347 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3348 */ 3349 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3350 /** 3351 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3352 */ 3353 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3354 /** 3355 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3356 */ 3357 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3358 /** 3359 * Definition of a DMUB_CMD__MALL command. 3360 */ 3361 struct dmub_rb_cmd_mall mall; 3362 /** 3363 * Definition of a DMUB_CMD__CAB command. 3364 */ 3365 struct dmub_rb_cmd_cab_for_ss cab; 3366 3367 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3368 3369 /** 3370 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3371 */ 3372 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3373 3374 /** 3375 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3376 */ 3377 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3378 3379 /** 3380 * Definition of DMUB_CMD__PANEL_CNTL commands. 3381 */ 3382 struct dmub_rb_cmd_panel_cntl panel_cntl; 3383 /** 3384 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3385 */ 3386 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3387 3388 /** 3389 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3390 */ 3391 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3392 3393 /** 3394 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3395 */ 3396 struct dmub_rb_cmd_abm_set_level abm_set_level; 3397 3398 /** 3399 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3400 */ 3401 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3402 3403 /** 3404 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3405 */ 3406 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3407 3408 /** 3409 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3410 */ 3411 struct dmub_rb_cmd_abm_init_config abm_init_config; 3412 3413 /** 3414 * Definition of a DMUB_CMD__ABM_PAUSE command. 3415 */ 3416 struct dmub_rb_cmd_abm_pause abm_pause; 3417 3418 /** 3419 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3420 */ 3421 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3422 3423 /** 3424 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3425 */ 3426 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3427 3428 /** 3429 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3430 */ 3431 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3432 3433 /** 3434 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3435 */ 3436 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3437 struct dmub_rb_cmd_drr_update drr_update; 3438 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3439 3440 /** 3441 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3442 */ 3443 struct dmub_rb_cmd_lvtma_control lvtma_control; 3444 /** 3445 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3446 */ 3447 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3448 /** 3449 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3450 */ 3451 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3452 /** 3453 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3454 */ 3455 struct dmub_rb_cmd_set_config_access set_config_access; 3456 /** 3457 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3458 */ 3459 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3460 /** 3461 * Definition of a DMUB_CMD__EDID_CEA command. 3462 */ 3463 struct dmub_rb_cmd_edid_cea edid_cea; 3464 /** 3465 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3466 */ 3467 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3468 3469 /** 3470 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3471 */ 3472 struct dmub_rb_cmd_query_hpd_state query_hpd; 3473 /** 3474 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3475 */ 3476 struct dmub_rb_cmd_secure_display secure_display; 3477 3478 /** 3479 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3480 */ 3481 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3482 }; 3483 3484 /** 3485 * union dmub_rb_out_cmd - Outbox command 3486 */ 3487 union dmub_rb_out_cmd { 3488 /** 3489 * Parameters common to every command. 3490 */ 3491 struct dmub_rb_cmd_common cmd_common; 3492 /** 3493 * AUX reply command. 3494 */ 3495 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3496 /** 3497 * HPD notify command. 3498 */ 3499 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3500 /** 3501 * SET_CONFIG reply command. 3502 */ 3503 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3504 /** 3505 * BW ALLOCATION notification command. 3506 */ 3507 struct dmub_rb_cmd_dpia_notification dpia_notify; 3508 }; 3509 #pragma pack(pop) 3510 3511 3512 //============================================================================== 3513 //</DMUB_CMD>=================================================================== 3514 //============================================================================== 3515 //< DMUB_RB>==================================================================== 3516 //============================================================================== 3517 3518 #if defined(__cplusplus) 3519 extern "C" { 3520 #endif 3521 3522 /** 3523 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3524 */ 3525 struct dmub_rb_init_params { 3526 void *ctx; /**< Caller provided context pointer */ 3527 void *base_address; /**< CPU base address for ring's data */ 3528 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3529 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3530 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3531 }; 3532 3533 /** 3534 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3535 */ 3536 struct dmub_rb { 3537 void *base_address; /**< CPU address for the ring's data */ 3538 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3539 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3540 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3541 3542 void *ctx; /**< Caller provided context pointer */ 3543 void *dmub; /**< Pointer to the DMUB interface */ 3544 }; 3545 3546 /** 3547 * @brief Checks if the ringbuffer is empty. 3548 * 3549 * @param rb DMUB Ringbuffer 3550 * @return true if empty 3551 * @return false otherwise 3552 */ 3553 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3554 { 3555 return (rb->wrpt == rb->rptr); 3556 } 3557 3558 /** 3559 * @brief Checks if the ringbuffer is full 3560 * 3561 * @param rb DMUB Ringbuffer 3562 * @return true if full 3563 * @return false otherwise 3564 */ 3565 static inline bool dmub_rb_full(struct dmub_rb *rb) 3566 { 3567 uint32_t data_count; 3568 3569 if (rb->wrpt >= rb->rptr) 3570 data_count = rb->wrpt - rb->rptr; 3571 else 3572 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3573 3574 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3575 } 3576 3577 /** 3578 * @brief Pushes a command into the ringbuffer 3579 * 3580 * @param rb DMUB ringbuffer 3581 * @param cmd The command to push 3582 * @return true if the ringbuffer was not full 3583 * @return false otherwise 3584 */ 3585 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3586 const union dmub_rb_cmd *cmd) 3587 { 3588 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3589 const uint64_t *src = (const uint64_t *)cmd; 3590 uint8_t i; 3591 3592 if (dmub_rb_full(rb)) 3593 return false; 3594 3595 // copying data 3596 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3597 *dst++ = *src++; 3598 3599 rb->wrpt += DMUB_RB_CMD_SIZE; 3600 3601 if (rb->wrpt >= rb->capacity) 3602 rb->wrpt %= rb->capacity; 3603 3604 return true; 3605 } 3606 3607 /** 3608 * @brief Pushes a command into the DMUB outbox ringbuffer 3609 * 3610 * @param rb DMUB outbox ringbuffer 3611 * @param cmd Outbox command 3612 * @return true if not full 3613 * @return false otherwise 3614 */ 3615 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3616 const union dmub_rb_out_cmd *cmd) 3617 { 3618 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3619 const uint8_t *src = (const uint8_t *)cmd; 3620 3621 if (dmub_rb_full(rb)) 3622 return false; 3623 3624 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3625 3626 rb->wrpt += DMUB_RB_CMD_SIZE; 3627 3628 if (rb->wrpt >= rb->capacity) 3629 rb->wrpt %= rb->capacity; 3630 3631 return true; 3632 } 3633 3634 /** 3635 * @brief Returns the next unprocessed command in the ringbuffer. 3636 * 3637 * @param rb DMUB ringbuffer 3638 * @param cmd The command to return 3639 * @return true if not empty 3640 * @return false otherwise 3641 */ 3642 static inline bool dmub_rb_front(struct dmub_rb *rb, 3643 union dmub_rb_cmd **cmd) 3644 { 3645 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3646 3647 if (dmub_rb_empty(rb)) 3648 return false; 3649 3650 *cmd = (union dmub_rb_cmd *)rb_cmd; 3651 3652 return true; 3653 } 3654 3655 /** 3656 * @brief Determines the next ringbuffer offset. 3657 * 3658 * @param rb DMUB inbox ringbuffer 3659 * @param num_cmds Number of commands 3660 * @param next_rptr The next offset in the ringbuffer 3661 */ 3662 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3663 uint32_t num_cmds, 3664 uint32_t *next_rptr) 3665 { 3666 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3667 3668 if (*next_rptr >= rb->capacity) 3669 *next_rptr %= rb->capacity; 3670 } 3671 3672 /** 3673 * @brief Returns a pointer to a command in the inbox. 3674 * 3675 * @param rb DMUB inbox ringbuffer 3676 * @param cmd The inbox command to return 3677 * @param rptr The ringbuffer offset 3678 * @return true if not empty 3679 * @return false otherwise 3680 */ 3681 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3682 union dmub_rb_cmd **cmd, 3683 uint32_t rptr) 3684 { 3685 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3686 3687 if (dmub_rb_empty(rb)) 3688 return false; 3689 3690 *cmd = (union dmub_rb_cmd *)rb_cmd; 3691 3692 return true; 3693 } 3694 3695 /** 3696 * @brief Returns the next unprocessed command in the outbox. 3697 * 3698 * @param rb DMUB outbox ringbuffer 3699 * @param cmd The outbox command to return 3700 * @return true if not empty 3701 * @return false otherwise 3702 */ 3703 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3704 union dmub_rb_out_cmd *cmd) 3705 { 3706 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3707 uint64_t *dst = (uint64_t *)cmd; 3708 uint8_t i; 3709 3710 if (dmub_rb_empty(rb)) 3711 return false; 3712 3713 // copying data 3714 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3715 *dst++ = *src++; 3716 3717 return true; 3718 } 3719 3720 /** 3721 * @brief Removes the front entry in the ringbuffer. 3722 * 3723 * @param rb DMUB ringbuffer 3724 * @return true if the command was removed 3725 * @return false if there were no commands 3726 */ 3727 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3728 { 3729 if (dmub_rb_empty(rb)) 3730 return false; 3731 3732 rb->rptr += DMUB_RB_CMD_SIZE; 3733 3734 if (rb->rptr >= rb->capacity) 3735 rb->rptr %= rb->capacity; 3736 3737 return true; 3738 } 3739 3740 /** 3741 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3742 * 3743 * Avoids a race condition where DMCUB accesses memory while 3744 * there are still writes in flight to framebuffer. 3745 * 3746 * @param rb DMUB ringbuffer 3747 */ 3748 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3749 { 3750 uint32_t rptr = rb->rptr; 3751 uint32_t wptr = rb->wrpt; 3752 3753 while (rptr != wptr) { 3754 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3755 uint8_t i; 3756 3757 /* Don't remove this. 3758 * The contents need to actually be read from the ring buffer 3759 * for this function to be effective. 3760 */ 3761 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3762 (void)READ_ONCE(*data++); 3763 3764 rptr += DMUB_RB_CMD_SIZE; 3765 if (rptr >= rb->capacity) 3766 rptr %= rb->capacity; 3767 } 3768 } 3769 3770 /** 3771 * @brief Initializes a DMCUB ringbuffer 3772 * 3773 * @param rb DMUB ringbuffer 3774 * @param init_params initial configuration for the ringbuffer 3775 */ 3776 static inline void dmub_rb_init(struct dmub_rb *rb, 3777 struct dmub_rb_init_params *init_params) 3778 { 3779 rb->base_address = init_params->base_address; 3780 rb->capacity = init_params->capacity; 3781 rb->rptr = init_params->read_ptr; 3782 rb->wrpt = init_params->write_ptr; 3783 } 3784 3785 /** 3786 * @brief Copies output data from in/out commands into the given command. 3787 * 3788 * @param rb DMUB ringbuffer 3789 * @param cmd Command to copy data into 3790 */ 3791 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3792 union dmub_rb_cmd *cmd) 3793 { 3794 // Copy rb entry back into command 3795 uint8_t *rd_ptr = (rb->rptr == 0) ? 3796 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3797 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3798 3799 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3800 } 3801 3802 #if defined(__cplusplus) 3803 } 3804 #endif 3805 3806 //============================================================================== 3807 //</DMUB_RB>==================================================================== 3808 //============================================================================== 3809 3810 #endif /* _DMUB_CMD_H_ */ 3811