1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 #include <stdarg.h> 43 44 #include "atomfirmware.h" 45 46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 47 48 /* Firmware versioning. */ 49 #ifdef DMUB_EXPOSE_VERSION 50 #define DMUB_FW_VERSION_GIT_HASH 0x992f4893d 51 #define DMUB_FW_VERSION_MAJOR 0 52 #define DMUB_FW_VERSION_MINOR 0 53 #define DMUB_FW_VERSION_REVISION 66 54 #define DMUB_FW_VERSION_TEST 0 55 #define DMUB_FW_VERSION_VBIOS 0 56 #define DMUB_FW_VERSION_HOTFIX 0 57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 62 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 63 64 #endif 65 66 //<DMUB_TYPES>================================================================== 67 /* Basic type definitions. */ 68 69 #define __forceinline inline 70 71 /** 72 * Flag from driver to indicate that ABM should be disabled gradually 73 * by slowly reversing all backlight programming and pixel compensation. 74 */ 75 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 76 77 /** 78 * Flag from driver to indicate that ABM should be disabled immediately 79 * and undo all backlight programming and pixel compensation. 80 */ 81 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 82 83 /** 84 * Flag from driver to indicate that ABM should be disabled immediately 85 * and keep the current backlight programming and pixel compensation. 86 */ 87 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 88 89 /** 90 * Flag from driver to set the current ABM pipe index or ABM operating level. 91 */ 92 #define SET_ABM_PIPE_NORMAL 1 93 94 /** 95 * Number of ambient light levels in ABM algorithm. 96 */ 97 #define NUM_AMBI_LEVEL 5 98 99 /** 100 * Number of operating/aggression levels in ABM algorithm. 101 */ 102 #define NUM_AGGR_LEVEL 4 103 104 /** 105 * Number of segments in the gamma curve. 106 */ 107 #define NUM_POWER_FN_SEGS 8 108 109 /** 110 * Number of segments in the backlight curve. 111 */ 112 #define NUM_BL_CURVE_SEGS 16 113 114 /* Maximum number of streams on any ASIC. */ 115 #define DMUB_MAX_STREAMS 6 116 117 /* Maximum number of planes on any ASIC. */ 118 #define DMUB_MAX_PLANES 6 119 120 #define DMUB_MAX_SUBVP_STREAMS 2 121 122 /* Trace buffer offset for entry */ 123 #define TRACE_BUFFER_ENTRY_OFFSET 16 124 125 /** 126 * 127 * PSR control version legacy 128 */ 129 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 130 /** 131 * PSR control version with multi edp support 132 */ 133 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 134 135 136 /** 137 * ABM control version legacy 138 */ 139 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 140 141 /** 142 * ABM control version with multi edp support 143 */ 144 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 145 146 /** 147 * Physical framebuffer address location, 64-bit. 148 */ 149 #ifndef PHYSICAL_ADDRESS_LOC 150 #define PHYSICAL_ADDRESS_LOC union large_integer 151 #endif 152 153 /** 154 * OS/FW agnostic memcpy 155 */ 156 #ifndef dmub_memcpy 157 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 158 #endif 159 160 /** 161 * OS/FW agnostic memset 162 */ 163 #ifndef dmub_memset 164 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 165 #endif 166 167 #if defined(__cplusplus) 168 extern "C" { 169 #endif 170 171 /** 172 * OS/FW agnostic udelay 173 */ 174 #ifndef dmub_udelay 175 #define dmub_udelay(microseconds) udelay(microseconds) 176 #endif 177 178 /** 179 * Number of nanoseconds per DMUB tick. 180 * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default. 181 * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true. 182 */ 183 #define NS_PER_DMUB_TICK 10 184 185 /** 186 * union dmub_addr - DMUB physical/virtual 64-bit address. 187 */ 188 union dmub_addr { 189 struct { 190 uint32_t low_part; /**< Lower 32 bits */ 191 uint32_t high_part; /**< Upper 32 bits */ 192 } u; /*<< Low/high bit access */ 193 uint64_t quad_part; /*<< 64 bit address */ 194 }; 195 196 /** 197 * Flags that can be set by driver to change some PSR behaviour. 198 */ 199 union dmub_psr_debug_flags { 200 /** 201 * Debug flags. 202 */ 203 struct { 204 /** 205 * Enable visual confirm in FW. 206 */ 207 uint32_t visual_confirm : 1; 208 /** 209 * Use HW Lock Mgr object to do HW locking in FW. 210 */ 211 uint32_t use_hw_lock_mgr : 1; 212 213 /** 214 * Unused. 215 * TODO: Remove. 216 */ 217 uint32_t log_line_nums : 1; 218 } bitfields; 219 220 /** 221 * Union for debug flags. 222 */ 223 uint32_t u32All; 224 }; 225 226 /** 227 * DMUB feature capabilities. 228 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 229 */ 230 struct dmub_feature_caps { 231 /** 232 * Max PSR version supported by FW. 233 */ 234 uint8_t psr; 235 uint8_t reserved[7]; 236 }; 237 238 #if defined(__cplusplus) 239 } 240 #endif 241 242 //============================================================================== 243 //</DMUB_TYPES>================================================================= 244 //============================================================================== 245 //< DMUB_META>================================================================== 246 //============================================================================== 247 #pragma pack(push, 1) 248 249 /* Magic value for identifying dmub_fw_meta_info */ 250 #define DMUB_FW_META_MAGIC 0x444D5542 251 252 /* Offset from the end of the file to the dmub_fw_meta_info */ 253 #define DMUB_FW_META_OFFSET 0x24 254 255 /** 256 * struct dmub_fw_meta_info - metadata associated with fw binary 257 * 258 * NOTE: This should be considered a stable API. Fields should 259 * not be repurposed or reordered. New fields should be 260 * added instead to extend the structure. 261 * 262 * @magic_value: magic value identifying DMUB firmware meta info 263 * @fw_region_size: size of the firmware state region 264 * @trace_buffer_size: size of the tracebuffer region 265 * @fw_version: the firmware version information 266 * @dal_fw: 1 if the firmware is DAL 267 */ 268 struct dmub_fw_meta_info { 269 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 270 uint32_t fw_region_size; /**< size of the firmware state region */ 271 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 272 uint32_t fw_version; /**< the firmware version information */ 273 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 274 uint8_t reserved[3]; /**< padding bits */ 275 }; 276 277 /** 278 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 279 */ 280 union dmub_fw_meta { 281 struct dmub_fw_meta_info info; /**< metadata info */ 282 uint8_t reserved[64]; /**< padding bits */ 283 }; 284 285 #pragma pack(pop) 286 287 //============================================================================== 288 //< DMUB Trace Buffer>================================================================ 289 //============================================================================== 290 /** 291 * dmub_trace_code_t - firmware trace code, 32-bits 292 */ 293 typedef uint32_t dmub_trace_code_t; 294 295 /** 296 * struct dmcub_trace_buf_entry - Firmware trace entry 297 */ 298 struct dmcub_trace_buf_entry { 299 dmub_trace_code_t trace_code; /**< trace code for the event */ 300 uint32_t tick_count; /**< the tick count at time of trace */ 301 uint32_t param0; /**< trace defined parameter 0 */ 302 uint32_t param1; /**< trace defined parameter 1 */ 303 }; 304 305 //============================================================================== 306 //< DMUB_STATUS>================================================================ 307 //============================================================================== 308 309 /** 310 * DMCUB scratch registers can be used to determine firmware status. 311 * Current scratch register usage is as follows: 312 * 313 * SCRATCH0: FW Boot Status register 314 * SCRATCH15: FW Boot Options register 315 */ 316 317 /** 318 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 319 */ 320 union dmub_fw_boot_status { 321 struct { 322 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 323 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 324 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 325 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 326 } bits; /**< status bits */ 327 uint32_t all; /**< 32-bit access to status bits */ 328 }; 329 330 /** 331 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 332 */ 333 enum dmub_fw_boot_status_bit { 334 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 335 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 336 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 337 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 338 }; 339 340 /** 341 * union dmub_fw_boot_options - Boot option definitions for SCRATCH15 342 */ 343 union dmub_fw_boot_options { 344 struct { 345 uint32_t pemu_env : 1; /**< 1 if PEMU */ 346 uint32_t fpga_env : 1; /**< 1 if FPGA */ 347 uint32_t optimized_init : 1; /**< 1 if optimized init */ 348 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 349 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 350 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 351 #ifdef CONFIG_DRM_AMD_DC_DCN3_1 352 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 353 #else 354 uint32_t reserved_unreleased: 1; /**< reserved for an unreleased feature */ 355 #endif 356 uint32_t reserved : 25; /**< reserved */ 357 } bits; /**< boot bits */ 358 uint32_t all; /**< 32-bit access to bits */ 359 }; 360 361 enum dmub_fw_boot_options_bit { 362 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 363 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 364 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 365 }; 366 367 //============================================================================== 368 //</DMUB_STATUS>================================================================ 369 //============================================================================== 370 //< DMUB_VBIOS>================================================================= 371 //============================================================================== 372 373 /* 374 * enum dmub_cmd_vbios_type - VBIOS commands. 375 * 376 * Command IDs should be treated as stable ABI. 377 * Do not reuse or modify IDs. 378 */ 379 enum dmub_cmd_vbios_type { 380 /** 381 * Configures the DIG encoder. 382 */ 383 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 384 /** 385 * Controls the PHY. 386 */ 387 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 388 /** 389 * Sets the pixel clock/symbol clock. 390 */ 391 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 392 /** 393 * Enables or disables power gating. 394 */ 395 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 396 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 397 }; 398 399 //============================================================================== 400 //</DMUB_VBIOS>================================================================= 401 //============================================================================== 402 //< DMUB_GPINT>================================================================= 403 //============================================================================== 404 405 /** 406 * The shifts and masks below may alternatively be used to format and read 407 * the command register bits. 408 */ 409 410 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 411 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 412 413 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 414 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 415 416 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 417 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 418 419 /** 420 * Command responses. 421 */ 422 423 /** 424 * Return response for DMUB_GPINT__STOP_FW command. 425 */ 426 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 427 428 /** 429 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 430 */ 431 union dmub_gpint_data_register { 432 struct { 433 uint32_t param : 16; /**< 16-bit parameter */ 434 uint32_t command_code : 12; /**< GPINT command */ 435 uint32_t status : 4; /**< Command status bit */ 436 } bits; /**< GPINT bit access */ 437 uint32_t all; /**< GPINT 32-bit access */ 438 }; 439 440 /* 441 * enum dmub_gpint_command - GPINT command to DMCUB FW 442 * 443 * Command IDs should be treated as stable ABI. 444 * Do not reuse or modify IDs. 445 */ 446 enum dmub_gpint_command { 447 /** 448 * Invalid command, ignored. 449 */ 450 DMUB_GPINT__INVALID_COMMAND = 0, 451 /** 452 * DESC: Queries the firmware version. 453 * RETURN: Firmware version. 454 */ 455 DMUB_GPINT__GET_FW_VERSION = 1, 456 /** 457 * DESC: Halts the firmware. 458 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 459 */ 460 DMUB_GPINT__STOP_FW = 2, 461 /** 462 * DESC: Get PSR state from FW. 463 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 464 */ 465 DMUB_GPINT__GET_PSR_STATE = 7, 466 /** 467 * DESC: Notifies DMCUB of the currently active streams. 468 * ARGS: Stream mask, 1 bit per active stream index. 469 */ 470 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 471 /** 472 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 473 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 474 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 475 * RETURN: PSR residency in milli-percent. 476 */ 477 DMUB_GPINT__PSR_RESIDENCY = 9, 478 }; 479 480 /** 481 * INBOX0 generic command definition 482 */ 483 union dmub_inbox0_cmd_common { 484 struct { 485 uint32_t command_code: 8; /**< INBOX0 command code */ 486 uint32_t param: 24; /**< 24-bit parameter */ 487 } bits; 488 uint32_t all; 489 }; 490 491 /** 492 * INBOX0 hw_lock command definition 493 */ 494 union dmub_inbox0_cmd_lock_hw { 495 struct { 496 uint32_t command_code: 8; 497 498 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 499 uint32_t hw_lock_client: 1; 500 501 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 502 uint32_t otg_inst: 3; 503 uint32_t opp_inst: 3; 504 uint32_t dig_inst: 3; 505 506 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 507 uint32_t lock_pipe: 1; 508 uint32_t lock_cursor: 1; 509 uint32_t lock_dig: 1; 510 uint32_t triple_buffer_lock: 1; 511 512 uint32_t lock: 1; /**< Lock */ 513 uint32_t should_release: 1; /**< Release */ 514 uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ 515 } bits; 516 uint32_t all; 517 }; 518 519 union dmub_inbox0_data_register { 520 union dmub_inbox0_cmd_common inbox0_cmd_common; 521 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 522 }; 523 524 enum dmub_inbox0_command { 525 /** 526 * DESC: Invalid command, ignored. 527 */ 528 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 529 /** 530 * DESC: Notification to acquire/release HW lock 531 * ARGS: 532 */ 533 DMUB_INBOX0_CMD__HW_LOCK = 1, 534 }; 535 //============================================================================== 536 //</DMUB_GPINT>================================================================= 537 //============================================================================== 538 //< DMUB_CMD>=================================================================== 539 //============================================================================== 540 541 /** 542 * Size in bytes of each DMUB command. 543 */ 544 #define DMUB_RB_CMD_SIZE 64 545 546 /** 547 * Maximum number of items in the DMUB ringbuffer. 548 */ 549 #define DMUB_RB_MAX_ENTRY 128 550 551 /** 552 * Ringbuffer size in bytes. 553 */ 554 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 555 556 /** 557 * REG_SET mask for reg offload. 558 */ 559 #define REG_SET_MASK 0xFFFF 560 561 /* 562 * enum dmub_cmd_type - DMUB inbox command. 563 * 564 * Command IDs should be treated as stable ABI. 565 * Do not reuse or modify IDs. 566 */ 567 enum dmub_cmd_type { 568 /** 569 * Invalid command. 570 */ 571 DMUB_CMD__NULL = 0, 572 /** 573 * Read modify write register sequence offload. 574 */ 575 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 576 /** 577 * Field update register sequence offload. 578 */ 579 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 580 /** 581 * Burst write sequence offload. 582 */ 583 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 584 /** 585 * Reg wait sequence offload. 586 */ 587 DMUB_CMD__REG_REG_WAIT = 4, 588 /** 589 * Workaround to avoid HUBP underflow during NV12 playback. 590 */ 591 DMUB_CMD__PLAT_54186_WA = 5, 592 /** 593 * Command type used to query FW feature caps. 594 */ 595 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 596 /** 597 * Command type used for all PSR commands. 598 */ 599 DMUB_CMD__PSR = 64, 600 /** 601 * Command type used for all MALL commands. 602 */ 603 DMUB_CMD__MALL = 65, 604 /** 605 * Command type used for all ABM commands. 606 */ 607 DMUB_CMD__ABM = 66, 608 /** 609 * Command type used for HW locking in FW. 610 */ 611 DMUB_CMD__HW_LOCK = 69, 612 /** 613 * Command type used to access DP AUX. 614 */ 615 DMUB_CMD__DP_AUX_ACCESS = 70, 616 /** 617 * Command type used for OUTBOX1 notification enable 618 */ 619 DMUB_CMD__OUTBOX1_ENABLE = 71, 620 #ifdef CONFIG_DRM_AMD_DC_DCN3_1 621 /** 622 * Command type used for all idle optimization commands. 623 */ 624 DMUB_CMD__IDLE_OPT = 72, 625 /** 626 * Command type used for all clock manager commands. 627 */ 628 DMUB_CMD__CLK_MGR = 73, 629 /** 630 * Command type used for all panel control commands. 631 */ 632 DMUB_CMD__PANEL_CNTL = 74, 633 #endif 634 /** 635 * Command type used for all VBIOS interface commands. 636 */ 637 DMUB_CMD__VBIOS = 128, 638 }; 639 640 /** 641 * enum dmub_out_cmd_type - DMUB outbox commands. 642 */ 643 enum dmub_out_cmd_type { 644 /** 645 * Invalid outbox command, ignored. 646 */ 647 DMUB_OUT_CMD__NULL = 0, 648 /** 649 * Command type used for DP AUX Reply data notification 650 */ 651 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 652 /** 653 * Command type used for DP HPD event notification 654 */ 655 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 656 }; 657 658 #pragma pack(push, 1) 659 660 /** 661 * struct dmub_cmd_header - Common command header fields. 662 */ 663 struct dmub_cmd_header { 664 unsigned int type : 8; /**< command type */ 665 unsigned int sub_type : 8; /**< command sub type */ 666 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 667 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 668 unsigned int reserved0 : 6; /**< reserved bits */ 669 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 670 unsigned int reserved1 : 2; /**< reserved bits */ 671 }; 672 673 /* 674 * struct dmub_cmd_read_modify_write_sequence - Read modify write 675 * 676 * 60 payload bytes can hold up to 5 sets of read modify writes, 677 * each take 3 dwords. 678 * 679 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 680 * 681 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 682 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 683 */ 684 struct dmub_cmd_read_modify_write_sequence { 685 uint32_t addr; /**< register address */ 686 uint32_t modify_mask; /**< modify mask */ 687 uint32_t modify_value; /**< modify value */ 688 }; 689 690 /** 691 * Maximum number of ops in read modify write sequence. 692 */ 693 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 694 695 /** 696 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 697 */ 698 struct dmub_rb_cmd_read_modify_write { 699 struct dmub_cmd_header header; /**< command header */ 700 /** 701 * Read modify write sequence. 702 */ 703 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 704 }; 705 706 /* 707 * Update a register with specified masks and values sequeunce 708 * 709 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 710 * 711 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 712 * 713 * 714 * USE CASE: 715 * 1. auto-increment register where additional read would update pointer and produce wrong result 716 * 2. toggle a bit without read in the middle 717 */ 718 719 struct dmub_cmd_reg_field_update_sequence { 720 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 721 uint32_t modify_value; /**< value to update with */ 722 }; 723 724 /** 725 * Maximum number of ops in field update sequence. 726 */ 727 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 728 729 /** 730 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 731 */ 732 struct dmub_rb_cmd_reg_field_update_sequence { 733 struct dmub_cmd_header header; /**< command header */ 734 uint32_t addr; /**< register address */ 735 /** 736 * Field update sequence. 737 */ 738 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 739 }; 740 741 742 /** 743 * Maximum number of burst write values. 744 */ 745 #define DMUB_BURST_WRITE_VALUES__MAX 14 746 747 /* 748 * struct dmub_rb_cmd_burst_write - Burst write 749 * 750 * support use case such as writing out LUTs. 751 * 752 * 60 payload bytes can hold up to 14 values to write to given address 753 * 754 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 755 */ 756 struct dmub_rb_cmd_burst_write { 757 struct dmub_cmd_header header; /**< command header */ 758 uint32_t addr; /**< register start address */ 759 /** 760 * Burst write register values. 761 */ 762 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 763 }; 764 765 /** 766 * struct dmub_rb_cmd_common - Common command header 767 */ 768 struct dmub_rb_cmd_common { 769 struct dmub_cmd_header header; /**< command header */ 770 /** 771 * Padding to RB_CMD_SIZE 772 */ 773 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 774 }; 775 776 /** 777 * struct dmub_cmd_reg_wait_data - Register wait data 778 */ 779 struct dmub_cmd_reg_wait_data { 780 uint32_t addr; /**< Register address */ 781 uint32_t mask; /**< Mask for register bits */ 782 uint32_t condition_field_value; /**< Value to wait for */ 783 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 784 }; 785 786 /** 787 * struct dmub_rb_cmd_reg_wait - Register wait command 788 */ 789 struct dmub_rb_cmd_reg_wait { 790 struct dmub_cmd_header header; /**< Command header */ 791 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 792 }; 793 794 /** 795 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 796 * 797 * Reprograms surface parameters to avoid underflow. 798 */ 799 struct dmub_cmd_PLAT_54186_wa { 800 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 801 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 802 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 803 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 804 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 805 struct { 806 uint8_t hubp_inst : 4; /**< HUBP instance */ 807 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 808 uint8_t immediate :1; /**< Immediate flip */ 809 uint8_t vmid : 4; /**< VMID */ 810 uint8_t grph_stereo : 1; /**< 1 if stereo */ 811 uint32_t reserved : 21; /**< Reserved */ 812 } flip_params; /**< Pageflip parameters */ 813 uint32_t reserved[9]; /**< Reserved bits */ 814 }; 815 816 /** 817 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 818 */ 819 struct dmub_rb_cmd_PLAT_54186_wa { 820 struct dmub_cmd_header header; /**< Command header */ 821 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 822 }; 823 824 /** 825 * struct dmub_rb_cmd_mall - MALL command data. 826 */ 827 struct dmub_rb_cmd_mall { 828 struct dmub_cmd_header header; /**< Common command header */ 829 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 830 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 831 uint32_t tmr_delay; /**< Timer delay */ 832 uint32_t tmr_scale; /**< Timer scale */ 833 uint16_t cursor_width; /**< Cursor width in pixels */ 834 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 835 uint16_t cursor_height; /**< Cursor height in pixels */ 836 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 837 uint8_t debug_bits; /**< Debug bits */ 838 839 uint8_t reserved1; /**< Reserved bits */ 840 uint8_t reserved2; /**< Reserved bits */ 841 }; 842 843 #ifdef CONFIG_DRM_AMD_DC_DCN3_1 844 845 /** 846 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 847 */ 848 enum dmub_cmd_idle_opt_type { 849 /** 850 * DCN hardware restore. 851 */ 852 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 853 }; 854 855 /** 856 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 857 */ 858 struct dmub_rb_cmd_idle_opt_dcn_restore { 859 struct dmub_cmd_header header; /**< header */ 860 }; 861 862 /** 863 * struct dmub_clocks - Clock update notification. 864 */ 865 struct dmub_clocks { 866 uint32_t dispclk_khz; /**< dispclk kHz */ 867 uint32_t dppclk_khz; /**< dppclk kHz */ 868 uint32_t dcfclk_khz; /**< dcfclk kHz */ 869 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 870 }; 871 872 /** 873 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 874 */ 875 enum dmub_cmd_clk_mgr_type { 876 /** 877 * Notify DMCUB of clock update. 878 */ 879 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 880 }; 881 882 /** 883 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 884 */ 885 struct dmub_rb_cmd_clk_mgr_notify_clocks { 886 struct dmub_cmd_header header; /**< header */ 887 struct dmub_clocks clocks; /**< clock data */ 888 }; 889 #endif 890 /** 891 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 892 */ 893 struct dmub_cmd_digx_encoder_control_data { 894 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 895 }; 896 897 /** 898 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 899 */ 900 struct dmub_rb_cmd_digx_encoder_control { 901 struct dmub_cmd_header header; /**< header */ 902 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 903 }; 904 905 /** 906 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 907 */ 908 struct dmub_cmd_set_pixel_clock_data { 909 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 910 }; 911 912 /** 913 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 914 */ 915 struct dmub_rb_cmd_set_pixel_clock { 916 struct dmub_cmd_header header; /**< header */ 917 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 918 }; 919 920 /** 921 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 922 */ 923 struct dmub_cmd_enable_disp_power_gating_data { 924 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 925 }; 926 927 /** 928 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 929 */ 930 struct dmub_rb_cmd_enable_disp_power_gating { 931 struct dmub_cmd_header header; /**< header */ 932 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 933 }; 934 935 /** 936 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 937 */ 938 struct dmub_dig_transmitter_control_data_v1_7 { 939 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 940 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 941 union { 942 uint8_t digmode; /**< enum atom_encode_mode_def */ 943 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 944 } mode_laneset; 945 uint8_t lanenum; /**< Number of lanes */ 946 union { 947 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 948 } symclk_units; 949 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 950 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 951 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 952 uint8_t reserved0; /**< For future use */ 953 uint8_t reserved1; /**< For future use */ 954 uint8_t reserved2[3]; /**< For future use */ 955 uint32_t reserved3[11]; /**< For future use */ 956 }; 957 958 /** 959 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 960 */ 961 union dmub_cmd_dig1_transmitter_control_data { 962 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 963 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 964 }; 965 966 /** 967 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 968 */ 969 struct dmub_rb_cmd_dig1_transmitter_control { 970 struct dmub_cmd_header header; /**< header */ 971 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 972 }; 973 974 /** 975 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 976 */ 977 struct dmub_rb_cmd_dpphy_init { 978 struct dmub_cmd_header header; /**< header */ 979 uint8_t reserved[60]; /**< reserved bits */ 980 }; 981 982 /** 983 * enum dp_aux_request_action - DP AUX request command listing. 984 * 985 * 4 AUX request command bits are shifted to high nibble. 986 */ 987 enum dp_aux_request_action { 988 /** I2C-over-AUX write request */ 989 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 990 /** I2C-over-AUX read request */ 991 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 992 /** I2C-over-AUX write status request */ 993 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 994 /** I2C-over-AUX write request with MOT=1 */ 995 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 996 /** I2C-over-AUX read request with MOT=1 */ 997 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 998 /** I2C-over-AUX write status request with MOT=1 */ 999 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1000 /** Native AUX write request */ 1001 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1002 /** Native AUX read request */ 1003 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1004 }; 1005 1006 /** 1007 * enum aux_return_code_type - DP AUX process return code listing. 1008 */ 1009 enum aux_return_code_type { 1010 /** AUX process succeeded */ 1011 AUX_RET_SUCCESS = 0, 1012 /** AUX process failed with unknown reason */ 1013 AUX_RET_ERROR_UNKNOWN, 1014 /** AUX process completed with invalid reply */ 1015 AUX_RET_ERROR_INVALID_REPLY, 1016 /** AUX process timed out */ 1017 AUX_RET_ERROR_TIMEOUT, 1018 /** HPD was low during AUX process */ 1019 AUX_RET_ERROR_HPD_DISCON, 1020 /** Failed to acquire AUX engine */ 1021 AUX_RET_ERROR_ENGINE_ACQUIRE, 1022 /** AUX request not supported */ 1023 AUX_RET_ERROR_INVALID_OPERATION, 1024 /** AUX process not available */ 1025 AUX_RET_ERROR_PROTOCOL_ERROR, 1026 }; 1027 1028 /** 1029 * enum aux_channel_type - DP AUX channel type listing. 1030 */ 1031 enum aux_channel_type { 1032 /** AUX thru Legacy DP AUX */ 1033 AUX_CHANNEL_LEGACY_DDC, 1034 /** AUX thru DPIA DP tunneling */ 1035 AUX_CHANNEL_DPIA 1036 }; 1037 1038 /** 1039 * struct aux_transaction_parameters - DP AUX request transaction data 1040 */ 1041 struct aux_transaction_parameters { 1042 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1043 uint8_t action; /**< enum dp_aux_request_action */ 1044 uint8_t length; /**< DP AUX request data length */ 1045 uint8_t reserved; /**< For future use */ 1046 uint32_t address; /**< DP AUX address */ 1047 uint8_t data[16]; /**< DP AUX write data */ 1048 }; 1049 1050 /** 1051 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1052 */ 1053 struct dmub_cmd_dp_aux_control_data { 1054 uint8_t instance; /**< AUX instance or DPIA instance */ 1055 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1056 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1057 uint8_t reserved0; /**< For future use */ 1058 uint16_t timeout; /**< timeout time in us */ 1059 uint16_t reserved1; /**< For future use */ 1060 enum aux_channel_type type; /**< enum aux_channel_type */ 1061 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1062 }; 1063 1064 /** 1065 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1066 */ 1067 struct dmub_rb_cmd_dp_aux_access { 1068 /** 1069 * Command header. 1070 */ 1071 struct dmub_cmd_header header; 1072 /** 1073 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1074 */ 1075 struct dmub_cmd_dp_aux_control_data aux_control; 1076 }; 1077 1078 /** 1079 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1080 */ 1081 struct dmub_rb_cmd_outbox1_enable { 1082 /** 1083 * Command header. 1084 */ 1085 struct dmub_cmd_header header; 1086 /** 1087 * enable: 0x0 -> disable outbox1 notification (default value) 1088 * 0x1 -> enable outbox1 notification 1089 */ 1090 uint32_t enable; 1091 }; 1092 1093 /* DP AUX Reply command - OutBox Cmd */ 1094 /** 1095 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1096 */ 1097 struct aux_reply_data { 1098 /** 1099 * Aux cmd 1100 */ 1101 uint8_t command; 1102 /** 1103 * Aux reply data length (max: 16 bytes) 1104 */ 1105 uint8_t length; 1106 /** 1107 * Alignment only 1108 */ 1109 uint8_t pad[2]; 1110 /** 1111 * Aux reply data 1112 */ 1113 uint8_t data[16]; 1114 }; 1115 1116 /** 1117 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1118 */ 1119 struct aux_reply_control_data { 1120 /** 1121 * Reserved for future use 1122 */ 1123 uint32_t handle; 1124 /** 1125 * Aux Instance 1126 */ 1127 uint8_t instance; 1128 /** 1129 * Aux transaction result: definition in enum aux_return_code_type 1130 */ 1131 uint8_t result; 1132 /** 1133 * Alignment only 1134 */ 1135 uint16_t pad; 1136 }; 1137 1138 /** 1139 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1140 */ 1141 struct dmub_rb_cmd_dp_aux_reply { 1142 /** 1143 * Command header. 1144 */ 1145 struct dmub_cmd_header header; 1146 /** 1147 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1148 */ 1149 struct aux_reply_control_data control; 1150 /** 1151 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1152 */ 1153 struct aux_reply_data reply_data; 1154 }; 1155 1156 /* DP HPD Notify command - OutBox Cmd */ 1157 /** 1158 * DP HPD Type 1159 */ 1160 enum dp_hpd_type { 1161 /** 1162 * Normal DP HPD 1163 */ 1164 DP_HPD = 0, 1165 /** 1166 * DP HPD short pulse 1167 */ 1168 DP_IRQ 1169 }; 1170 1171 /** 1172 * DP HPD Status 1173 */ 1174 enum dp_hpd_status { 1175 /** 1176 * DP_HPD status low 1177 */ 1178 DP_HPD_UNPLUG = 0, 1179 /** 1180 * DP_HPD status high 1181 */ 1182 DP_HPD_PLUG 1183 }; 1184 1185 /** 1186 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1187 */ 1188 struct dp_hpd_data { 1189 /** 1190 * DP HPD instance 1191 */ 1192 uint8_t instance; 1193 /** 1194 * HPD type 1195 */ 1196 uint8_t hpd_type; 1197 /** 1198 * HPD status: only for type: DP_HPD to indicate status 1199 */ 1200 uint8_t hpd_status; 1201 /** 1202 * Alignment only 1203 */ 1204 uint8_t pad; 1205 }; 1206 1207 /** 1208 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1209 */ 1210 struct dmub_rb_cmd_dp_hpd_notify { 1211 /** 1212 * Command header. 1213 */ 1214 struct dmub_cmd_header header; 1215 /** 1216 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1217 */ 1218 struct dp_hpd_data hpd_data; 1219 }; 1220 1221 /* 1222 * Command IDs should be treated as stable ABI. 1223 * Do not reuse or modify IDs. 1224 */ 1225 1226 /** 1227 * PSR command sub-types. 1228 */ 1229 enum dmub_cmd_psr_type { 1230 /** 1231 * Set PSR version support. 1232 */ 1233 DMUB_CMD__PSR_SET_VERSION = 0, 1234 /** 1235 * Copy driver-calculated parameters to PSR state. 1236 */ 1237 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1238 /** 1239 * Enable PSR. 1240 */ 1241 DMUB_CMD__PSR_ENABLE = 2, 1242 1243 /** 1244 * Disable PSR. 1245 */ 1246 DMUB_CMD__PSR_DISABLE = 3, 1247 1248 /** 1249 * Set PSR level. 1250 * PSR level is a 16-bit value dicated by driver that 1251 * will enable/disable different functionality. 1252 */ 1253 DMUB_CMD__PSR_SET_LEVEL = 4, 1254 1255 /** 1256 * Forces PSR enabled until an explicit PSR disable call. 1257 */ 1258 DMUB_CMD__PSR_FORCE_STATIC = 5, 1259 }; 1260 1261 /** 1262 * PSR versions. 1263 */ 1264 enum psr_version { 1265 /** 1266 * PSR version 1. 1267 */ 1268 PSR_VERSION_1 = 0, 1269 /** 1270 * PSR not supported. 1271 */ 1272 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1273 }; 1274 1275 /** 1276 * enum dmub_cmd_mall_type - MALL commands 1277 */ 1278 enum dmub_cmd_mall_type { 1279 /** 1280 * Allows display refresh from MALL. 1281 */ 1282 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1283 /** 1284 * Disallows display refresh from MALL. 1285 */ 1286 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1287 /** 1288 * Cursor copy for MALL. 1289 */ 1290 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1291 /** 1292 * Controls DF requests. 1293 */ 1294 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1295 }; 1296 1297 1298 /** 1299 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1300 */ 1301 struct dmub_cmd_psr_copy_settings_data { 1302 /** 1303 * Flags that can be set by driver to change some PSR behaviour. 1304 */ 1305 union dmub_psr_debug_flags debug; 1306 /** 1307 * 16-bit value dicated by driver that will enable/disable different functionality. 1308 */ 1309 uint16_t psr_level; 1310 /** 1311 * DPP HW instance. 1312 */ 1313 uint8_t dpp_inst; 1314 /** 1315 * MPCC HW instance. 1316 * Not used in dmub fw, 1317 * dmub fw will get active opp by reading odm registers. 1318 */ 1319 uint8_t mpcc_inst; 1320 /** 1321 * OPP HW instance. 1322 * Not used in dmub fw, 1323 * dmub fw will get active opp by reading odm registers. 1324 */ 1325 uint8_t opp_inst; 1326 /** 1327 * OTG HW instance. 1328 */ 1329 uint8_t otg_inst; 1330 /** 1331 * DIG FE HW instance. 1332 */ 1333 uint8_t digfe_inst; 1334 /** 1335 * DIG BE HW instance. 1336 */ 1337 uint8_t digbe_inst; 1338 /** 1339 * DP PHY HW instance. 1340 */ 1341 uint8_t dpphy_inst; 1342 /** 1343 * AUX HW instance. 1344 */ 1345 uint8_t aux_inst; 1346 /** 1347 * Determines if SMU optimzations are enabled/disabled. 1348 */ 1349 uint8_t smu_optimizations_en; 1350 /** 1351 * Unused. 1352 * TODO: Remove. 1353 */ 1354 uint8_t frame_delay; 1355 /** 1356 * If RFB setup time is greater than the total VBLANK time, 1357 * it is not possible for the sink to capture the video frame 1358 * in the same frame the SDP is sent. In this case, 1359 * the frame capture indication bit should be set and an extra 1360 * static frame should be transmitted to the sink. 1361 */ 1362 uint8_t frame_cap_ind; 1363 /** 1364 * Explicit padding to 4 byte boundary. 1365 */ 1366 uint8_t pad[2]; 1367 /** 1368 * Multi-display optimizations are implemented on certain ASICs. 1369 */ 1370 uint8_t multi_disp_optimizations_en; 1371 /** 1372 * The last possible line SDP may be transmitted without violating 1373 * the RFB setup time or entering the active video frame. 1374 */ 1375 uint16_t init_sdp_deadline; 1376 /** 1377 * Explicit padding to 4 byte boundary. 1378 */ 1379 uint16_t pad2; 1380 /** 1381 * Length of each horizontal line in us. 1382 */ 1383 uint32_t line_time_in_us; 1384 /** 1385 * FEC enable status in driver 1386 */ 1387 uint8_t fec_enable_status; 1388 /** 1389 * FEC re-enable delay when PSR exit. 1390 * unit is 100us, range form 0~255(0xFF). 1391 */ 1392 uint8_t fec_enable_delay_in100us; 1393 /** 1394 * PSR control version. 1395 */ 1396 uint8_t cmd_version; 1397 /** 1398 * Panel Instance. 1399 * Panel isntance to identify which psr_state to use 1400 * Currently the support is only for 0 or 1 1401 */ 1402 uint8_t panel_inst; 1403 }; 1404 1405 /** 1406 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1407 */ 1408 struct dmub_rb_cmd_psr_copy_settings { 1409 /** 1410 * Command header. 1411 */ 1412 struct dmub_cmd_header header; 1413 /** 1414 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1415 */ 1416 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1417 }; 1418 1419 /** 1420 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1421 */ 1422 struct dmub_cmd_psr_set_level_data { 1423 /** 1424 * 16-bit value dicated by driver that will enable/disable different functionality. 1425 */ 1426 uint16_t psr_level; 1427 /** 1428 * PSR control version. 1429 */ 1430 uint8_t cmd_version; 1431 /** 1432 * Panel Instance. 1433 * Panel isntance to identify which psr_state to use 1434 * Currently the support is only for 0 or 1 1435 */ 1436 uint8_t panel_inst; 1437 }; 1438 1439 /** 1440 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1441 */ 1442 struct dmub_rb_cmd_psr_set_level { 1443 /** 1444 * Command header. 1445 */ 1446 struct dmub_cmd_header header; 1447 /** 1448 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1449 */ 1450 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1451 }; 1452 1453 struct dmub_rb_cmd_psr_enable_data { 1454 /** 1455 * PSR control version. 1456 */ 1457 uint8_t cmd_version; 1458 /** 1459 * Panel Instance. 1460 * Panel isntance to identify which psr_state to use 1461 * Currently the support is only for 0 or 1 1462 */ 1463 uint8_t panel_inst; 1464 /** 1465 * Explicit padding to 4 byte boundary. 1466 */ 1467 uint8_t pad[2]; 1468 }; 1469 1470 /** 1471 * Definition of a DMUB_CMD__PSR_ENABLE command. 1472 * PSR enable/disable is controlled using the sub_type. 1473 */ 1474 struct dmub_rb_cmd_psr_enable { 1475 /** 1476 * Command header. 1477 */ 1478 struct dmub_cmd_header header; 1479 1480 struct dmub_rb_cmd_psr_enable_data data; 1481 }; 1482 1483 /** 1484 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1485 */ 1486 struct dmub_cmd_psr_set_version_data { 1487 /** 1488 * PSR version that FW should implement. 1489 */ 1490 enum psr_version version; 1491 /** 1492 * PSR control version. 1493 */ 1494 uint8_t cmd_version; 1495 /** 1496 * Panel Instance. 1497 * Panel isntance to identify which psr_state to use 1498 * Currently the support is only for 0 or 1 1499 */ 1500 uint8_t panel_inst; 1501 /** 1502 * Explicit padding to 4 byte boundary. 1503 */ 1504 uint8_t pad[2]; 1505 }; 1506 1507 /** 1508 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1509 */ 1510 struct dmub_rb_cmd_psr_set_version { 1511 /** 1512 * Command header. 1513 */ 1514 struct dmub_cmd_header header; 1515 /** 1516 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1517 */ 1518 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1519 }; 1520 1521 struct dmub_cmd_psr_force_static_data { 1522 /** 1523 * PSR control version. 1524 */ 1525 uint8_t cmd_version; 1526 /** 1527 * Panel Instance. 1528 * Panel isntance to identify which psr_state to use 1529 * Currently the support is only for 0 or 1 1530 */ 1531 uint8_t panel_inst; 1532 /** 1533 * Explicit padding to 4 byte boundary. 1534 */ 1535 uint8_t pad[2]; 1536 }; 1537 1538 /** 1539 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1540 */ 1541 struct dmub_rb_cmd_psr_force_static { 1542 /** 1543 * Command header. 1544 */ 1545 struct dmub_cmd_header header; 1546 /** 1547 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1548 */ 1549 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1550 }; 1551 1552 /** 1553 * Set of HW components that can be locked. 1554 * 1555 * Note: If updating with more HW components, fields 1556 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1557 */ 1558 union dmub_hw_lock_flags { 1559 /** 1560 * Set of HW components that can be locked. 1561 */ 1562 struct { 1563 /** 1564 * Lock/unlock OTG master update lock. 1565 */ 1566 uint8_t lock_pipe : 1; 1567 /** 1568 * Lock/unlock cursor. 1569 */ 1570 uint8_t lock_cursor : 1; 1571 /** 1572 * Lock/unlock global update lock. 1573 */ 1574 uint8_t lock_dig : 1; 1575 /** 1576 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1577 */ 1578 uint8_t triple_buffer_lock : 1; 1579 } bits; 1580 1581 /** 1582 * Union for HW Lock flags. 1583 */ 1584 uint8_t u8All; 1585 }; 1586 1587 /** 1588 * Instances of HW to be locked. 1589 * 1590 * Note: If updating with more HW components, fields 1591 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1592 */ 1593 struct dmub_hw_lock_inst_flags { 1594 /** 1595 * OTG HW instance for OTG master update lock. 1596 */ 1597 uint8_t otg_inst; 1598 /** 1599 * OPP instance for cursor lock. 1600 */ 1601 uint8_t opp_inst; 1602 /** 1603 * OTG HW instance for global update lock. 1604 * TODO: Remove, and re-use otg_inst. 1605 */ 1606 uint8_t dig_inst; 1607 /** 1608 * Explicit pad to 4 byte boundary. 1609 */ 1610 uint8_t pad; 1611 }; 1612 1613 /** 1614 * Clients that can acquire the HW Lock Manager. 1615 * 1616 * Note: If updating with more clients, fields in 1617 * dmub_inbox0_cmd_lock_hw must be updated to match. 1618 */ 1619 enum hw_lock_client { 1620 /** 1621 * Driver is the client of HW Lock Manager. 1622 */ 1623 HW_LOCK_CLIENT_DRIVER = 0, 1624 HW_LOCK_CLIENT_SUBVP = 3, 1625 /** 1626 * Invalid client. 1627 */ 1628 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1629 }; 1630 1631 /** 1632 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1633 */ 1634 struct dmub_cmd_lock_hw_data { 1635 /** 1636 * Specifies the client accessing HW Lock Manager. 1637 */ 1638 enum hw_lock_client client; 1639 /** 1640 * HW instances to be locked. 1641 */ 1642 struct dmub_hw_lock_inst_flags inst_flags; 1643 /** 1644 * Which components to be locked. 1645 */ 1646 union dmub_hw_lock_flags hw_locks; 1647 /** 1648 * Specifies lock/unlock. 1649 */ 1650 uint8_t lock; 1651 /** 1652 * HW can be unlocked separately from releasing the HW Lock Mgr. 1653 * This flag is set if the client wishes to release the object. 1654 */ 1655 uint8_t should_release; 1656 /** 1657 * Explicit padding to 4 byte boundary. 1658 */ 1659 uint8_t pad; 1660 }; 1661 1662 /** 1663 * Definition of a DMUB_CMD__HW_LOCK command. 1664 * Command is used by driver and FW. 1665 */ 1666 struct dmub_rb_cmd_lock_hw { 1667 /** 1668 * Command header. 1669 */ 1670 struct dmub_cmd_header header; 1671 /** 1672 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1673 */ 1674 struct dmub_cmd_lock_hw_data lock_hw_data; 1675 }; 1676 1677 /** 1678 * ABM command sub-types. 1679 */ 1680 enum dmub_cmd_abm_type { 1681 /** 1682 * Initialize parameters for ABM algorithm. 1683 * Data is passed through an indirect buffer. 1684 */ 1685 DMUB_CMD__ABM_INIT_CONFIG = 0, 1686 /** 1687 * Set OTG and panel HW instance. 1688 */ 1689 DMUB_CMD__ABM_SET_PIPE = 1, 1690 /** 1691 * Set user requested backklight level. 1692 */ 1693 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1694 /** 1695 * Set ABM operating/aggression level. 1696 */ 1697 DMUB_CMD__ABM_SET_LEVEL = 3, 1698 /** 1699 * Set ambient light level. 1700 */ 1701 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1702 /** 1703 * Enable/disable fractional duty cycle for backlight PWM. 1704 */ 1705 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1706 }; 1707 1708 /** 1709 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1710 * Requirements: 1711 * - Padded explicitly to 32-bit boundary. 1712 * - Must ensure this structure matches the one on driver-side, 1713 * otherwise it won't be aligned. 1714 */ 1715 struct abm_config_table { 1716 /** 1717 * Gamma curve thresholds, used for crgb conversion. 1718 */ 1719 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1720 /** 1721 * Gamma curve offsets, used for crgb conversion. 1722 */ 1723 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1724 /** 1725 * Gamma curve slopes, used for crgb conversion. 1726 */ 1727 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1728 /** 1729 * Custom backlight curve thresholds. 1730 */ 1731 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 1732 /** 1733 * Custom backlight curve offsets. 1734 */ 1735 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 1736 /** 1737 * Ambient light thresholds. 1738 */ 1739 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 1740 /** 1741 * Minimum programmable backlight. 1742 */ 1743 uint16_t min_abm_backlight; // 122B 1744 /** 1745 * Minimum reduction values. 1746 */ 1747 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 1748 /** 1749 * Maximum reduction values. 1750 */ 1751 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 1752 /** 1753 * Bright positive gain. 1754 */ 1755 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 1756 /** 1757 * Dark negative gain. 1758 */ 1759 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 1760 /** 1761 * Hybrid factor. 1762 */ 1763 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 1764 /** 1765 * Contrast factor. 1766 */ 1767 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 1768 /** 1769 * Deviation gain. 1770 */ 1771 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 1772 /** 1773 * Minimum knee. 1774 */ 1775 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 1776 /** 1777 * Maximum knee. 1778 */ 1779 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 1780 /** 1781 * Unused. 1782 */ 1783 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 1784 /** 1785 * Explicit padding to 4 byte boundary. 1786 */ 1787 uint8_t pad3[3]; // 229B 1788 /** 1789 * Backlight ramp reduction. 1790 */ 1791 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 1792 /** 1793 * Backlight ramp start. 1794 */ 1795 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 1796 }; 1797 1798 /** 1799 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1800 */ 1801 struct dmub_cmd_abm_set_pipe_data { 1802 /** 1803 * OTG HW instance. 1804 */ 1805 uint8_t otg_inst; 1806 1807 /** 1808 * Panel Control HW instance. 1809 */ 1810 uint8_t panel_inst; 1811 1812 /** 1813 * Controls how ABM will interpret a set pipe or set level command. 1814 */ 1815 uint8_t set_pipe_option; 1816 1817 /** 1818 * Unused. 1819 * TODO: Remove. 1820 */ 1821 uint8_t ramping_boundary; 1822 }; 1823 1824 /** 1825 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1826 */ 1827 struct dmub_rb_cmd_abm_set_pipe { 1828 /** 1829 * Command header. 1830 */ 1831 struct dmub_cmd_header header; 1832 1833 /** 1834 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1835 */ 1836 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 1837 }; 1838 1839 /** 1840 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1841 */ 1842 struct dmub_cmd_abm_set_backlight_data { 1843 /** 1844 * Number of frames to ramp to backlight user level. 1845 */ 1846 uint32_t frame_ramp; 1847 1848 /** 1849 * Requested backlight level from user. 1850 */ 1851 uint32_t backlight_user_level; 1852 1853 /** 1854 * ABM control version. 1855 */ 1856 uint8_t version; 1857 1858 /** 1859 * Panel Control HW instance mask. 1860 * Bit 0 is Panel Control HW instance 0. 1861 * Bit 1 is Panel Control HW instance 1. 1862 */ 1863 uint8_t panel_mask; 1864 1865 /** 1866 * Explicit padding to 4 byte boundary. 1867 */ 1868 uint8_t pad[2]; 1869 }; 1870 1871 /** 1872 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 1873 */ 1874 struct dmub_rb_cmd_abm_set_backlight { 1875 /** 1876 * Command header. 1877 */ 1878 struct dmub_cmd_header header; 1879 1880 /** 1881 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1882 */ 1883 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 1884 }; 1885 1886 /** 1887 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1888 */ 1889 struct dmub_cmd_abm_set_level_data { 1890 /** 1891 * Set current ABM operating/aggression level. 1892 */ 1893 uint32_t level; 1894 1895 /** 1896 * ABM control version. 1897 */ 1898 uint8_t version; 1899 1900 /** 1901 * Panel Control HW instance mask. 1902 * Bit 0 is Panel Control HW instance 0. 1903 * Bit 1 is Panel Control HW instance 1. 1904 */ 1905 uint8_t panel_mask; 1906 1907 /** 1908 * Explicit padding to 4 byte boundary. 1909 */ 1910 uint8_t pad[2]; 1911 }; 1912 1913 /** 1914 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 1915 */ 1916 struct dmub_rb_cmd_abm_set_level { 1917 /** 1918 * Command header. 1919 */ 1920 struct dmub_cmd_header header; 1921 1922 /** 1923 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1924 */ 1925 struct dmub_cmd_abm_set_level_data abm_set_level_data; 1926 }; 1927 1928 /** 1929 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1930 */ 1931 struct dmub_cmd_abm_set_ambient_level_data { 1932 /** 1933 * Ambient light sensor reading from OS. 1934 */ 1935 uint32_t ambient_lux; 1936 1937 /** 1938 * ABM control version. 1939 */ 1940 uint8_t version; 1941 1942 /** 1943 * Panel Control HW instance mask. 1944 * Bit 0 is Panel Control HW instance 0. 1945 * Bit 1 is Panel Control HW instance 1. 1946 */ 1947 uint8_t panel_mask; 1948 1949 /** 1950 * Explicit padding to 4 byte boundary. 1951 */ 1952 uint8_t pad[2]; 1953 }; 1954 1955 /** 1956 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1957 */ 1958 struct dmub_rb_cmd_abm_set_ambient_level { 1959 /** 1960 * Command header. 1961 */ 1962 struct dmub_cmd_header header; 1963 1964 /** 1965 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1966 */ 1967 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 1968 }; 1969 1970 /** 1971 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1972 */ 1973 struct dmub_cmd_abm_set_pwm_frac_data { 1974 /** 1975 * Enable/disable fractional duty cycle for backlight PWM. 1976 * TODO: Convert to uint8_t. 1977 */ 1978 uint32_t fractional_pwm; 1979 1980 /** 1981 * ABM control version. 1982 */ 1983 uint8_t version; 1984 1985 /** 1986 * Panel Control HW instance mask. 1987 * Bit 0 is Panel Control HW instance 0. 1988 * Bit 1 is Panel Control HW instance 1. 1989 */ 1990 uint8_t panel_mask; 1991 1992 /** 1993 * Explicit padding to 4 byte boundary. 1994 */ 1995 uint8_t pad[2]; 1996 }; 1997 1998 /** 1999 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2000 */ 2001 struct dmub_rb_cmd_abm_set_pwm_frac { 2002 /** 2003 * Command header. 2004 */ 2005 struct dmub_cmd_header header; 2006 2007 /** 2008 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2009 */ 2010 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2011 }; 2012 2013 /** 2014 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2015 */ 2016 struct dmub_cmd_abm_init_config_data { 2017 /** 2018 * Location of indirect buffer used to pass init data to ABM. 2019 */ 2020 union dmub_addr src; 2021 2022 /** 2023 * Indirect buffer length. 2024 */ 2025 uint16_t bytes; 2026 2027 2028 /** 2029 * ABM control version. 2030 */ 2031 uint8_t version; 2032 2033 /** 2034 * Panel Control HW instance mask. 2035 * Bit 0 is Panel Control HW instance 0. 2036 * Bit 1 is Panel Control HW instance 1. 2037 */ 2038 uint8_t panel_mask; 2039 2040 /** 2041 * Explicit padding to 4 byte boundary. 2042 */ 2043 uint8_t pad[2]; 2044 }; 2045 2046 /** 2047 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2048 */ 2049 struct dmub_rb_cmd_abm_init_config { 2050 /** 2051 * Command header. 2052 */ 2053 struct dmub_cmd_header header; 2054 2055 /** 2056 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2057 */ 2058 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2059 }; 2060 2061 /** 2062 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2063 */ 2064 struct dmub_cmd_query_feature_caps_data { 2065 /** 2066 * DMUB feature capabilities. 2067 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2068 */ 2069 struct dmub_feature_caps feature_caps; 2070 }; 2071 2072 /** 2073 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2074 */ 2075 struct dmub_rb_cmd_query_feature_caps { 2076 /** 2077 * Command header. 2078 */ 2079 struct dmub_cmd_header header; 2080 /** 2081 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2082 */ 2083 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2084 }; 2085 2086 struct dmub_optc_state { 2087 uint32_t v_total_max; 2088 uint32_t v_total_min; 2089 uint32_t v_total_mid; 2090 uint32_t v_total_mid_frame_num; 2091 uint32_t tg_inst; 2092 uint32_t enable_manual_trigger; 2093 uint32_t clear_force_vsync; 2094 }; 2095 2096 struct dmub_rb_cmd_drr_update { 2097 struct dmub_cmd_header header; 2098 struct dmub_optc_state dmub_optc_state_req; 2099 }; 2100 2101 #ifdef CONFIG_DRM_AMD_DC_DCN3_1 2102 /** 2103 * enum dmub_cmd_panel_cntl_type - Panel control command. 2104 */ 2105 enum dmub_cmd_panel_cntl_type { 2106 /** 2107 * Initializes embedded panel hardware blocks. 2108 */ 2109 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2110 /** 2111 * Queries backlight info for the embedded panel. 2112 */ 2113 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2114 }; 2115 2116 /** 2117 * struct dmub_cmd_panel_cntl_data - Panel control data. 2118 */ 2119 struct dmub_cmd_panel_cntl_data { 2120 uint32_t inst; /**< panel instance */ 2121 uint32_t current_backlight; /* in/out */ 2122 uint32_t bl_pwm_cntl; /* in/out */ 2123 uint32_t bl_pwm_period_cntl; /* in/out */ 2124 uint32_t bl_pwm_ref_div1; /* in/out */ 2125 uint8_t is_backlight_on : 1; /* in/out */ 2126 uint8_t is_powered_on : 1; /* in/out */ 2127 }; 2128 2129 /** 2130 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2131 */ 2132 struct dmub_rb_cmd_panel_cntl { 2133 struct dmub_cmd_header header; /**< header */ 2134 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2135 }; 2136 #endif 2137 2138 /** 2139 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2140 */ 2141 struct dmub_cmd_lvtma_control_data { 2142 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2143 uint8_t reserved_0[3]; /**< For future use */ 2144 uint8_t panel_inst; /**< LVTMA control instance */ 2145 uint8_t reserved_1[3]; /**< For future use */ 2146 }; 2147 2148 /** 2149 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2150 */ 2151 struct dmub_rb_cmd_lvtma_control { 2152 /** 2153 * Command header. 2154 */ 2155 struct dmub_cmd_header header; 2156 /** 2157 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2158 */ 2159 struct dmub_cmd_lvtma_control_data data; 2160 }; 2161 2162 /** 2163 * union dmub_rb_cmd - DMUB inbox command. 2164 */ 2165 union dmub_rb_cmd { 2166 struct dmub_rb_cmd_lock_hw lock_hw; 2167 /** 2168 * Elements shared with all commands. 2169 */ 2170 struct dmub_rb_cmd_common cmd_common; 2171 /** 2172 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2173 */ 2174 struct dmub_rb_cmd_read_modify_write read_modify_write; 2175 /** 2176 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2177 */ 2178 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2179 /** 2180 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2181 */ 2182 struct dmub_rb_cmd_burst_write burst_write; 2183 /** 2184 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2185 */ 2186 struct dmub_rb_cmd_reg_wait reg_wait; 2187 /** 2188 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2189 */ 2190 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2191 /** 2192 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2193 */ 2194 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2195 /** 2196 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2197 */ 2198 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2199 /** 2200 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2201 */ 2202 struct dmub_rb_cmd_dpphy_init dpphy_init; 2203 /** 2204 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2205 */ 2206 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2207 /** 2208 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2209 */ 2210 struct dmub_rb_cmd_psr_set_version psr_set_version; 2211 /** 2212 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2213 */ 2214 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2215 /** 2216 * Definition of a DMUB_CMD__PSR_ENABLE command. 2217 */ 2218 struct dmub_rb_cmd_psr_enable psr_enable; 2219 /** 2220 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2221 */ 2222 struct dmub_rb_cmd_psr_set_level psr_set_level; 2223 /** 2224 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2225 */ 2226 struct dmub_rb_cmd_psr_force_static psr_force_static; 2227 /** 2228 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2229 */ 2230 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2231 /** 2232 * Definition of a DMUB_CMD__MALL command. 2233 */ 2234 struct dmub_rb_cmd_mall mall; 2235 #ifdef CONFIG_DRM_AMD_DC_DCN3_1 2236 /** 2237 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2238 */ 2239 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2240 2241 /** 2242 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2243 */ 2244 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2245 2246 /** 2247 * Definition of DMUB_CMD__PANEL_CNTL commands. 2248 */ 2249 struct dmub_rb_cmd_panel_cntl panel_cntl; 2250 #endif 2251 /** 2252 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2253 */ 2254 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2255 2256 /** 2257 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2258 */ 2259 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2260 2261 /** 2262 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2263 */ 2264 struct dmub_rb_cmd_abm_set_level abm_set_level; 2265 2266 /** 2267 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2268 */ 2269 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2270 2271 /** 2272 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2273 */ 2274 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2275 2276 /** 2277 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2278 */ 2279 struct dmub_rb_cmd_abm_init_config abm_init_config; 2280 2281 /** 2282 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2283 */ 2284 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2285 2286 /** 2287 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2288 */ 2289 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2290 2291 /** 2292 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2293 */ 2294 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2295 struct dmub_rb_cmd_drr_update drr_update; 2296 /** 2297 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2298 */ 2299 struct dmub_rb_cmd_lvtma_control lvtma_control; 2300 }; 2301 2302 /** 2303 * union dmub_rb_out_cmd - Outbox command 2304 */ 2305 union dmub_rb_out_cmd { 2306 /** 2307 * Parameters common to every command. 2308 */ 2309 struct dmub_rb_cmd_common cmd_common; 2310 /** 2311 * AUX reply command. 2312 */ 2313 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2314 /** 2315 * HPD notify command. 2316 */ 2317 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2318 }; 2319 #pragma pack(pop) 2320 2321 2322 //============================================================================== 2323 //</DMUB_CMD>=================================================================== 2324 //============================================================================== 2325 //< DMUB_RB>==================================================================== 2326 //============================================================================== 2327 2328 #if defined(__cplusplus) 2329 extern "C" { 2330 #endif 2331 2332 /** 2333 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2334 */ 2335 struct dmub_rb_init_params { 2336 void *ctx; /**< Caller provided context pointer */ 2337 void *base_address; /**< CPU base address for ring's data */ 2338 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2339 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2340 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2341 }; 2342 2343 /** 2344 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2345 */ 2346 struct dmub_rb { 2347 void *base_address; /**< CPU address for the ring's data */ 2348 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2349 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2350 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2351 2352 void *ctx; /**< Caller provided context pointer */ 2353 void *dmub; /**< Pointer to the DMUB interface */ 2354 }; 2355 2356 /** 2357 * @brief Checks if the ringbuffer is empty. 2358 * 2359 * @param rb DMUB Ringbuffer 2360 * @return true if empty 2361 * @return false otherwise 2362 */ 2363 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2364 { 2365 return (rb->wrpt == rb->rptr); 2366 } 2367 2368 /** 2369 * @brief Checks if the ringbuffer is full 2370 * 2371 * @param rb DMUB Ringbuffer 2372 * @return true if full 2373 * @return false otherwise 2374 */ 2375 static inline bool dmub_rb_full(struct dmub_rb *rb) 2376 { 2377 uint32_t data_count; 2378 2379 if (rb->wrpt >= rb->rptr) 2380 data_count = rb->wrpt - rb->rptr; 2381 else 2382 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2383 2384 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2385 } 2386 2387 /** 2388 * @brief Pushes a command into the ringbuffer 2389 * 2390 * @param rb DMUB ringbuffer 2391 * @param cmd The command to push 2392 * @return true if the ringbuffer was not full 2393 * @return false otherwise 2394 */ 2395 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2396 const union dmub_rb_cmd *cmd) 2397 { 2398 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 2399 const uint64_t *src = (const uint64_t *)cmd; 2400 uint8_t i; 2401 2402 if (dmub_rb_full(rb)) 2403 return false; 2404 2405 // copying data 2406 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2407 *dst++ = *src++; 2408 2409 rb->wrpt += DMUB_RB_CMD_SIZE; 2410 2411 if (rb->wrpt >= rb->capacity) 2412 rb->wrpt %= rb->capacity; 2413 2414 return true; 2415 } 2416 2417 /** 2418 * @brief Pushes a command into the DMUB outbox ringbuffer 2419 * 2420 * @param rb DMUB outbox ringbuffer 2421 * @param cmd Outbox command 2422 * @return true if not full 2423 * @return false otherwise 2424 */ 2425 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2426 const union dmub_rb_out_cmd *cmd) 2427 { 2428 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2429 const uint8_t *src = (uint8_t *)cmd; 2430 2431 if (dmub_rb_full(rb)) 2432 return false; 2433 2434 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2435 2436 rb->wrpt += DMUB_RB_CMD_SIZE; 2437 2438 if (rb->wrpt >= rb->capacity) 2439 rb->wrpt %= rb->capacity; 2440 2441 return true; 2442 } 2443 2444 /** 2445 * @brief Returns the next unprocessed command in the ringbuffer. 2446 * 2447 * @param rb DMUB ringbuffer 2448 * @param cmd The command to return 2449 * @return true if not empty 2450 * @return false otherwise 2451 */ 2452 static inline bool dmub_rb_front(struct dmub_rb *rb, 2453 union dmub_rb_cmd **cmd) 2454 { 2455 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2456 2457 if (dmub_rb_empty(rb)) 2458 return false; 2459 2460 *cmd = (union dmub_rb_cmd *)rb_cmd; 2461 2462 return true; 2463 } 2464 2465 /** 2466 * @brief Determines the next ringbuffer offset. 2467 * 2468 * @param rb DMUB inbox ringbuffer 2469 * @param num_cmds Number of commands 2470 * @param next_rptr The next offset in the ringbuffer 2471 */ 2472 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2473 uint32_t num_cmds, 2474 uint32_t *next_rptr) 2475 { 2476 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2477 2478 if (*next_rptr >= rb->capacity) 2479 *next_rptr %= rb->capacity; 2480 } 2481 2482 /** 2483 * @brief Returns a pointer to a command in the inbox. 2484 * 2485 * @param rb DMUB inbox ringbuffer 2486 * @param cmd The inbox command to return 2487 * @param rptr The ringbuffer offset 2488 * @return true if not empty 2489 * @return false otherwise 2490 */ 2491 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 2492 union dmub_rb_cmd **cmd, 2493 uint32_t rptr) 2494 { 2495 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 2496 2497 if (dmub_rb_empty(rb)) 2498 return false; 2499 2500 *cmd = (union dmub_rb_cmd *)rb_cmd; 2501 2502 return true; 2503 } 2504 2505 /** 2506 * @brief Returns the next unprocessed command in the outbox. 2507 * 2508 * @param rb DMUB outbox ringbuffer 2509 * @param cmd The outbox command to return 2510 * @return true if not empty 2511 * @return false otherwise 2512 */ 2513 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2514 union dmub_rb_out_cmd *cmd) 2515 { 2516 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 2517 uint64_t *dst = (uint64_t *)cmd; 2518 uint8_t i; 2519 2520 if (dmub_rb_empty(rb)) 2521 return false; 2522 2523 // copying data 2524 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2525 *dst++ = *src++; 2526 2527 return true; 2528 } 2529 2530 /** 2531 * @brief Removes the front entry in the ringbuffer. 2532 * 2533 * @param rb DMUB ringbuffer 2534 * @return true if the command was removed 2535 * @return false if there were no commands 2536 */ 2537 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 2538 { 2539 if (dmub_rb_empty(rb)) 2540 return false; 2541 2542 rb->rptr += DMUB_RB_CMD_SIZE; 2543 2544 if (rb->rptr >= rb->capacity) 2545 rb->rptr %= rb->capacity; 2546 2547 return true; 2548 } 2549 2550 /** 2551 * @brief Flushes commands in the ringbuffer to framebuffer memory. 2552 * 2553 * Avoids a race condition where DMCUB accesses memory while 2554 * there are still writes in flight to framebuffer. 2555 * 2556 * @param rb DMUB ringbuffer 2557 */ 2558 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 2559 { 2560 uint32_t rptr = rb->rptr; 2561 uint32_t wptr = rb->wrpt; 2562 2563 while (rptr != wptr) { 2564 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 2565 uint8_t i; 2566 2567 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2568 *data++; 2569 2570 rptr += DMUB_RB_CMD_SIZE; 2571 if (rptr >= rb->capacity) 2572 rptr %= rb->capacity; 2573 } 2574 } 2575 2576 /** 2577 * @brief Initializes a DMCUB ringbuffer 2578 * 2579 * @param rb DMUB ringbuffer 2580 * @param init_params initial configuration for the ringbuffer 2581 */ 2582 static inline void dmub_rb_init(struct dmub_rb *rb, 2583 struct dmub_rb_init_params *init_params) 2584 { 2585 rb->base_address = init_params->base_address; 2586 rb->capacity = init_params->capacity; 2587 rb->rptr = init_params->read_ptr; 2588 rb->wrpt = init_params->write_ptr; 2589 } 2590 2591 /** 2592 * @brief Copies output data from in/out commands into the given command. 2593 * 2594 * @param rb DMUB ringbuffer 2595 * @param cmd Command to copy data into 2596 */ 2597 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 2598 union dmub_rb_cmd *cmd) 2599 { 2600 // Copy rb entry back into command 2601 uint8_t *rd_ptr = (rb->rptr == 0) ? 2602 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 2603 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 2604 2605 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 2606 } 2607 2608 #if defined(__cplusplus) 2609 } 2610 #endif 2611 2612 //============================================================================== 2613 //</DMUB_RB>==================================================================== 2614 //============================================================================== 2615 2616 #endif /* _DMUB_CMD_H_ */ 2617