1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Define max FPO streams as 4 for now. Current implementation today 99 * only supports 1, but could be more in the future. Reduce array 100 * size to ensure the command size remains less than 64 bytes if 101 * adding new fields. 102 */ 103 #define DMUB_MAX_FPO_STREAMS 4 104 105 /* Maximum number of streams on any ASIC. */ 106 #define DMUB_MAX_STREAMS 6 107 108 /* Maximum number of planes on any ASIC. */ 109 #define DMUB_MAX_PLANES 6 110 111 /* Trace buffer offset for entry */ 112 #define TRACE_BUFFER_ENTRY_OFFSET 16 113 114 /** 115 * Maximum number of dirty rects supported by FW. 116 */ 117 #define DMUB_MAX_DIRTY_RECTS 3 118 119 /** 120 * 121 * PSR control version legacy 122 */ 123 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 124 /** 125 * PSR control version with multi edp support 126 */ 127 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 128 129 130 /** 131 * ABM control version legacy 132 */ 133 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 134 135 /** 136 * ABM control version with multi edp support 137 */ 138 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 139 140 /** 141 * Physical framebuffer address location, 64-bit. 142 */ 143 #ifndef PHYSICAL_ADDRESS_LOC 144 #define PHYSICAL_ADDRESS_LOC union large_integer 145 #endif 146 147 #define ABM_NUM_OF_ACE_SEGMENTS 5 148 149 union abm_flags { 150 struct { 151 /** 152 * @abm_enabled: Indicates if ABM is enabled. 153 */ 154 unsigned int abm_enabled : 1; 155 156 /** 157 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 158 */ 159 unsigned int disable_abm_requested : 1; 160 161 /** 162 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled 163 * immediately. 164 */ 165 unsigned int disable_abm_immediately : 1; 166 167 /** 168 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 169 * to be disabled immediately and keep gain. 170 */ 171 unsigned int disable_abm_immediate_keep_gain : 1; 172 173 /** 174 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 175 */ 176 unsigned int fractional_pwm : 1; 177 178 /** 179 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 180 * of user backlight level. 181 */ 182 unsigned int abm_gradual_bl_change : 1; 183 } bitfields; 184 185 unsigned int u32All; 186 }; 187 188 struct abm_save_restore { 189 /** 190 * @flags: Misc. ABM flags. 191 */ 192 union abm_flags flags; 193 194 /** 195 * @pause: true: pause ABM and get state 196 * false: unpause ABM after setting state 197 */ 198 uint32_t pause; 199 200 /** 201 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 202 */ 203 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 204 205 /** 206 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 207 */ 208 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 209 210 /** 211 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 212 */ 213 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 214 215 216 /** 217 * @knee_threshold: Current x-position of ACE knee (u0.16). 218 */ 219 uint32_t knee_threshold; 220 /** 221 * @current_gain: Current backlight reduction (u16.16). 222 */ 223 uint32_t current_gain; 224 /** 225 * @curr_bl_level: Current actual backlight level converging to target backlight level. 226 */ 227 uint16_t curr_bl_level; 228 229 /** 230 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 231 */ 232 uint16_t curr_user_bl_level; 233 234 }; 235 236 237 238 /** 239 * OS/FW agnostic memcpy 240 */ 241 #ifndef dmub_memcpy 242 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 243 #endif 244 245 /** 246 * OS/FW agnostic memset 247 */ 248 #ifndef dmub_memset 249 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 250 #endif 251 252 #if defined(__cplusplus) 253 extern "C" { 254 #endif 255 256 /** 257 * OS/FW agnostic udelay 258 */ 259 #ifndef dmub_udelay 260 #define dmub_udelay(microseconds) udelay(microseconds) 261 #endif 262 263 #pragma pack(push, 1) 264 /** 265 * union dmub_addr - DMUB physical/virtual 64-bit address. 266 */ 267 union dmub_addr { 268 struct { 269 uint32_t low_part; /**< Lower 32 bits */ 270 uint32_t high_part; /**< Upper 32 bits */ 271 } u; /*<< Low/high bit access */ 272 uint64_t quad_part; /*<< 64 bit address */ 273 }; 274 #pragma pack(pop) 275 276 /** 277 * Dirty rect definition. 278 */ 279 struct dmub_rect { 280 /** 281 * Dirty rect x offset. 282 */ 283 uint32_t x; 284 285 /** 286 * Dirty rect y offset. 287 */ 288 uint32_t y; 289 290 /** 291 * Dirty rect width. 292 */ 293 uint32_t width; 294 295 /** 296 * Dirty rect height. 297 */ 298 uint32_t height; 299 }; 300 301 /** 302 * Flags that can be set by driver to change some PSR behaviour. 303 */ 304 union dmub_psr_debug_flags { 305 /** 306 * Debug flags. 307 */ 308 struct { 309 /** 310 * Enable visual confirm in FW. 311 */ 312 uint32_t visual_confirm : 1; 313 314 /** 315 * Force all selective updates to bw full frame updates. 316 */ 317 uint32_t force_full_frame_update : 1; 318 319 /** 320 * Use HW Lock Mgr object to do HW locking in FW. 321 */ 322 uint32_t use_hw_lock_mgr : 1; 323 324 /** 325 * Use TPS3 signal when restore main link. 326 */ 327 uint32_t force_wakeup_by_tps3 : 1; 328 329 /** 330 * Back to back flip, therefore cannot power down PHY 331 */ 332 uint32_t back_to_back_flip : 1; 333 334 } bitfields; 335 336 /** 337 * Union for debug flags. 338 */ 339 uint32_t u32All; 340 }; 341 342 /** 343 * DMUB visual confirm color 344 */ 345 struct dmub_feature_caps { 346 /** 347 * Max PSR version supported by FW. 348 */ 349 uint8_t psr; 350 uint8_t fw_assisted_mclk_switch; 351 uint8_t reserved[4]; 352 uint8_t subvp_psr_support; 353 uint8_t gecc_enable; 354 }; 355 356 struct dmub_visual_confirm_color { 357 /** 358 * Maximum 10 bits color value 359 */ 360 uint16_t color_r_cr; 361 uint16_t color_g_y; 362 uint16_t color_b_cb; 363 uint16_t panel_inst; 364 }; 365 366 #if defined(__cplusplus) 367 } 368 #endif 369 370 //============================================================================== 371 //</DMUB_TYPES>================================================================= 372 //============================================================================== 373 //< DMUB_META>================================================================== 374 //============================================================================== 375 #pragma pack(push, 1) 376 377 /* Magic value for identifying dmub_fw_meta_info */ 378 #define DMUB_FW_META_MAGIC 0x444D5542 379 380 /* Offset from the end of the file to the dmub_fw_meta_info */ 381 #define DMUB_FW_META_OFFSET 0x24 382 383 /** 384 * struct dmub_fw_meta_info - metadata associated with fw binary 385 * 386 * NOTE: This should be considered a stable API. Fields should 387 * not be repurposed or reordered. New fields should be 388 * added instead to extend the structure. 389 * 390 * @magic_value: magic value identifying DMUB firmware meta info 391 * @fw_region_size: size of the firmware state region 392 * @trace_buffer_size: size of the tracebuffer region 393 * @fw_version: the firmware version information 394 * @dal_fw: 1 if the firmware is DAL 395 */ 396 struct dmub_fw_meta_info { 397 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 398 uint32_t fw_region_size; /**< size of the firmware state region */ 399 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 400 uint32_t fw_version; /**< the firmware version information */ 401 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 402 uint8_t reserved[3]; /**< padding bits */ 403 }; 404 405 /** 406 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 407 */ 408 union dmub_fw_meta { 409 struct dmub_fw_meta_info info; /**< metadata info */ 410 uint8_t reserved[64]; /**< padding bits */ 411 }; 412 413 #pragma pack(pop) 414 415 //============================================================================== 416 //< DMUB Trace Buffer>================================================================ 417 //============================================================================== 418 /** 419 * dmub_trace_code_t - firmware trace code, 32-bits 420 */ 421 typedef uint32_t dmub_trace_code_t; 422 423 /** 424 * struct dmcub_trace_buf_entry - Firmware trace entry 425 */ 426 struct dmcub_trace_buf_entry { 427 dmub_trace_code_t trace_code; /**< trace code for the event */ 428 uint32_t tick_count; /**< the tick count at time of trace */ 429 uint32_t param0; /**< trace defined parameter 0 */ 430 uint32_t param1; /**< trace defined parameter 1 */ 431 }; 432 433 //============================================================================== 434 //< DMUB_STATUS>================================================================ 435 //============================================================================== 436 437 /** 438 * DMCUB scratch registers can be used to determine firmware status. 439 * Current scratch register usage is as follows: 440 * 441 * SCRATCH0: FW Boot Status register 442 * SCRATCH5: LVTMA Status Register 443 * SCRATCH15: FW Boot Options register 444 */ 445 446 /** 447 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 448 */ 449 union dmub_fw_boot_status { 450 struct { 451 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 452 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 453 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 454 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 455 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 456 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 457 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 458 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 459 } bits; /**< status bits */ 460 uint32_t all; /**< 32-bit access to status bits */ 461 }; 462 463 /** 464 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 465 */ 466 enum dmub_fw_boot_status_bit { 467 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 468 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 469 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 470 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 471 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 472 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 473 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 474 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 475 }; 476 477 /* Register bit definition for SCRATCH5 */ 478 union dmub_lvtma_status { 479 struct { 480 uint32_t psp_ok : 1; 481 uint32_t edp_on : 1; 482 uint32_t reserved : 30; 483 } bits; 484 uint32_t all; 485 }; 486 487 enum dmub_lvtma_status_bit { 488 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 489 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 490 }; 491 492 enum dmub_ips_disable_type { 493 DMUB_IPS_DISABLE_IPS1 = 1, 494 DMUB_IPS_DISABLE_IPS2 = 2, 495 DMUB_IPS_DISABLE_IPS2_Z10 = 3, 496 }; 497 498 /** 499 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 500 */ 501 union dmub_fw_boot_options { 502 struct { 503 uint32_t pemu_env : 1; /**< 1 if PEMU */ 504 uint32_t fpga_env : 1; /**< 1 if FPGA */ 505 uint32_t optimized_init : 1; /**< 1 if optimized init */ 506 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 507 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 508 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 509 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 510 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 511 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 512 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 513 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 514 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 515 uint32_t power_optimization: 1; 516 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 517 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 518 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 519 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 520 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 521 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 522 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 523 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 524 uint32_t ips_disable: 2; /* options to disable ips support*/ 525 uint32_t reserved : 10; /**< reserved */ 526 } bits; /**< boot bits */ 527 uint32_t all; /**< 32-bit access to bits */ 528 }; 529 530 enum dmub_fw_boot_options_bit { 531 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 532 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 533 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 534 }; 535 536 //============================================================================== 537 //</DMUB_STATUS>================================================================ 538 //============================================================================== 539 //< DMUB_VBIOS>================================================================= 540 //============================================================================== 541 542 /* 543 * enum dmub_cmd_vbios_type - VBIOS commands. 544 * 545 * Command IDs should be treated as stable ABI. 546 * Do not reuse or modify IDs. 547 */ 548 enum dmub_cmd_vbios_type { 549 /** 550 * Configures the DIG encoder. 551 */ 552 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 553 /** 554 * Controls the PHY. 555 */ 556 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 557 /** 558 * Sets the pixel clock/symbol clock. 559 */ 560 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 561 /** 562 * Enables or disables power gating. 563 */ 564 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 565 /** 566 * Controls embedded panels. 567 */ 568 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 569 /** 570 * Query DP alt status on a transmitter. 571 */ 572 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 573 /** 574 * Controls domain power gating 575 */ 576 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 577 }; 578 579 //============================================================================== 580 //</DMUB_VBIOS>================================================================= 581 //============================================================================== 582 //< DMUB_GPINT>================================================================= 583 //============================================================================== 584 585 /** 586 * The shifts and masks below may alternatively be used to format and read 587 * the command register bits. 588 */ 589 590 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 591 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 592 593 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 594 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 595 596 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 597 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 598 599 /** 600 * Command responses. 601 */ 602 603 /** 604 * Return response for DMUB_GPINT__STOP_FW command. 605 */ 606 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 607 608 /** 609 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 610 */ 611 union dmub_gpint_data_register { 612 struct { 613 uint32_t param : 16; /**< 16-bit parameter */ 614 uint32_t command_code : 12; /**< GPINT command */ 615 uint32_t status : 4; /**< Command status bit */ 616 } bits; /**< GPINT bit access */ 617 uint32_t all; /**< GPINT 32-bit access */ 618 }; 619 620 /* 621 * enum dmub_gpint_command - GPINT command to DMCUB FW 622 * 623 * Command IDs should be treated as stable ABI. 624 * Do not reuse or modify IDs. 625 */ 626 enum dmub_gpint_command { 627 /** 628 * Invalid command, ignored. 629 */ 630 DMUB_GPINT__INVALID_COMMAND = 0, 631 /** 632 * DESC: Queries the firmware version. 633 * RETURN: Firmware version. 634 */ 635 DMUB_GPINT__GET_FW_VERSION = 1, 636 /** 637 * DESC: Halts the firmware. 638 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 639 */ 640 DMUB_GPINT__STOP_FW = 2, 641 /** 642 * DESC: Get PSR state from FW. 643 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 644 */ 645 DMUB_GPINT__GET_PSR_STATE = 7, 646 /** 647 * DESC: Notifies DMCUB of the currently active streams. 648 * ARGS: Stream mask, 1 bit per active stream index. 649 */ 650 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 651 /** 652 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 653 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 654 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 655 * RETURN: PSR residency in milli-percent. 656 */ 657 DMUB_GPINT__PSR_RESIDENCY = 9, 658 659 /** 660 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 661 */ 662 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 663 }; 664 665 /** 666 * INBOX0 generic command definition 667 */ 668 union dmub_inbox0_cmd_common { 669 struct { 670 uint32_t command_code: 8; /**< INBOX0 command code */ 671 uint32_t param: 24; /**< 24-bit parameter */ 672 } bits; 673 uint32_t all; 674 }; 675 676 /** 677 * INBOX0 hw_lock command definition 678 */ 679 union dmub_inbox0_cmd_lock_hw { 680 struct { 681 uint32_t command_code: 8; 682 683 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 684 uint32_t hw_lock_client: 2; 685 686 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 687 uint32_t otg_inst: 3; 688 uint32_t opp_inst: 3; 689 uint32_t dig_inst: 3; 690 691 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 692 uint32_t lock_pipe: 1; 693 uint32_t lock_cursor: 1; 694 uint32_t lock_dig: 1; 695 uint32_t triple_buffer_lock: 1; 696 697 uint32_t lock: 1; /**< Lock */ 698 uint32_t should_release: 1; /**< Release */ 699 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 700 } bits; 701 uint32_t all; 702 }; 703 704 union dmub_inbox0_data_register { 705 union dmub_inbox0_cmd_common inbox0_cmd_common; 706 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 707 }; 708 709 enum dmub_inbox0_command { 710 /** 711 * DESC: Invalid command, ignored. 712 */ 713 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 714 /** 715 * DESC: Notification to acquire/release HW lock 716 * ARGS: 717 */ 718 DMUB_INBOX0_CMD__HW_LOCK = 1, 719 }; 720 //============================================================================== 721 //</DMUB_GPINT>================================================================= 722 //============================================================================== 723 //< DMUB_CMD>=================================================================== 724 //============================================================================== 725 726 /** 727 * Size in bytes of each DMUB command. 728 */ 729 #define DMUB_RB_CMD_SIZE 64 730 731 /** 732 * Maximum number of items in the DMUB ringbuffer. 733 */ 734 #define DMUB_RB_MAX_ENTRY 128 735 736 /** 737 * Ringbuffer size in bytes. 738 */ 739 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 740 741 /** 742 * REG_SET mask for reg offload. 743 */ 744 #define REG_SET_MASK 0xFFFF 745 746 /* 747 * enum dmub_cmd_type - DMUB inbox command. 748 * 749 * Command IDs should be treated as stable ABI. 750 * Do not reuse or modify IDs. 751 */ 752 enum dmub_cmd_type { 753 /** 754 * Invalid command. 755 */ 756 DMUB_CMD__NULL = 0, 757 /** 758 * Read modify write register sequence offload. 759 */ 760 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 761 /** 762 * Field update register sequence offload. 763 */ 764 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 765 /** 766 * Burst write sequence offload. 767 */ 768 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 769 /** 770 * Reg wait sequence offload. 771 */ 772 DMUB_CMD__REG_REG_WAIT = 4, 773 /** 774 * Workaround to avoid HUBP underflow during NV12 playback. 775 */ 776 DMUB_CMD__PLAT_54186_WA = 5, 777 /** 778 * Command type used to query FW feature caps. 779 */ 780 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 781 /** 782 * Command type used to get visual confirm color. 783 */ 784 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 785 /** 786 * Command type used for all PSR commands. 787 */ 788 DMUB_CMD__PSR = 64, 789 /** 790 * Command type used for all MALL commands. 791 */ 792 DMUB_CMD__MALL = 65, 793 /** 794 * Command type used for all ABM commands. 795 */ 796 DMUB_CMD__ABM = 66, 797 /** 798 * Command type used to update dirty rects in FW. 799 */ 800 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 801 /** 802 * Command type used to update cursor info in FW. 803 */ 804 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 805 /** 806 * Command type used for HW locking in FW. 807 */ 808 DMUB_CMD__HW_LOCK = 69, 809 /** 810 * Command type used to access DP AUX. 811 */ 812 DMUB_CMD__DP_AUX_ACCESS = 70, 813 /** 814 * Command type used for OUTBOX1 notification enable 815 */ 816 DMUB_CMD__OUTBOX1_ENABLE = 71, 817 818 /** 819 * Command type used for all idle optimization commands. 820 */ 821 DMUB_CMD__IDLE_OPT = 72, 822 /** 823 * Command type used for all clock manager commands. 824 */ 825 DMUB_CMD__CLK_MGR = 73, 826 /** 827 * Command type used for all panel control commands. 828 */ 829 DMUB_CMD__PANEL_CNTL = 74, 830 /** 831 * Command type used for <TODO:description> 832 */ 833 DMUB_CMD__CAB_FOR_SS = 75, 834 835 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 836 837 /** 838 * Command type used for interfacing with DPIA. 839 */ 840 DMUB_CMD__DPIA = 77, 841 /** 842 * Command type used for EDID CEA parsing 843 */ 844 DMUB_CMD__EDID_CEA = 79, 845 /** 846 * Command type used for getting usbc cable ID 847 */ 848 DMUB_CMD_GET_USBC_CABLE_ID = 81, 849 /** 850 * Command type used to query HPD state. 851 */ 852 DMUB_CMD__QUERY_HPD_STATE = 82, 853 /** 854 * Command type used for all VBIOS interface commands. 855 */ 856 857 /** 858 * Command type used for all SECURE_DISPLAY commands. 859 */ 860 DMUB_CMD__SECURE_DISPLAY = 85, 861 862 /** 863 * Command type used to set DPIA HPD interrupt state 864 */ 865 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 866 867 DMUB_CMD__VBIOS = 128, 868 }; 869 870 /** 871 * enum dmub_out_cmd_type - DMUB outbox commands. 872 */ 873 enum dmub_out_cmd_type { 874 /** 875 * Invalid outbox command, ignored. 876 */ 877 DMUB_OUT_CMD__NULL = 0, 878 /** 879 * Command type used for DP AUX Reply data notification 880 */ 881 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 882 /** 883 * Command type used for DP HPD event notification 884 */ 885 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 886 /** 887 * Command type used for SET_CONFIG Reply notification 888 */ 889 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 890 /** 891 * Command type used for USB4 DPIA notification 892 */ 893 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 894 }; 895 896 /* DMUB_CMD__DPIA command sub-types. */ 897 enum dmub_cmd_dpia_type { 898 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 899 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 900 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 901 }; 902 903 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 904 enum dmub_cmd_dpia_notification_type { 905 DPIA_NOTIFY__BW_ALLOCATION = 0, 906 }; 907 908 #pragma pack(push, 1) 909 910 /** 911 * struct dmub_cmd_header - Common command header fields. 912 */ 913 struct dmub_cmd_header { 914 unsigned int type : 8; /**< command type */ 915 unsigned int sub_type : 8; /**< command sub type */ 916 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 917 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 918 unsigned int reserved0 : 6; /**< reserved bits */ 919 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 920 unsigned int reserved1 : 2; /**< reserved bits */ 921 }; 922 923 /* 924 * struct dmub_cmd_read_modify_write_sequence - Read modify write 925 * 926 * 60 payload bytes can hold up to 5 sets of read modify writes, 927 * each take 3 dwords. 928 * 929 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 930 * 931 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 932 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 933 */ 934 struct dmub_cmd_read_modify_write_sequence { 935 uint32_t addr; /**< register address */ 936 uint32_t modify_mask; /**< modify mask */ 937 uint32_t modify_value; /**< modify value */ 938 }; 939 940 /** 941 * Maximum number of ops in read modify write sequence. 942 */ 943 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 944 945 /** 946 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 947 */ 948 struct dmub_rb_cmd_read_modify_write { 949 struct dmub_cmd_header header; /**< command header */ 950 /** 951 * Read modify write sequence. 952 */ 953 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 954 }; 955 956 /* 957 * Update a register with specified masks and values sequeunce 958 * 959 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 960 * 961 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 962 * 963 * 964 * USE CASE: 965 * 1. auto-increment register where additional read would update pointer and produce wrong result 966 * 2. toggle a bit without read in the middle 967 */ 968 969 struct dmub_cmd_reg_field_update_sequence { 970 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 971 uint32_t modify_value; /**< value to update with */ 972 }; 973 974 /** 975 * Maximum number of ops in field update sequence. 976 */ 977 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 978 979 /** 980 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 981 */ 982 struct dmub_rb_cmd_reg_field_update_sequence { 983 struct dmub_cmd_header header; /**< command header */ 984 uint32_t addr; /**< register address */ 985 /** 986 * Field update sequence. 987 */ 988 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 989 }; 990 991 992 /** 993 * Maximum number of burst write values. 994 */ 995 #define DMUB_BURST_WRITE_VALUES__MAX 14 996 997 /* 998 * struct dmub_rb_cmd_burst_write - Burst write 999 * 1000 * support use case such as writing out LUTs. 1001 * 1002 * 60 payload bytes can hold up to 14 values to write to given address 1003 * 1004 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1005 */ 1006 struct dmub_rb_cmd_burst_write { 1007 struct dmub_cmd_header header; /**< command header */ 1008 uint32_t addr; /**< register start address */ 1009 /** 1010 * Burst write register values. 1011 */ 1012 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1013 }; 1014 1015 /** 1016 * struct dmub_rb_cmd_common - Common command header 1017 */ 1018 struct dmub_rb_cmd_common { 1019 struct dmub_cmd_header header; /**< command header */ 1020 /** 1021 * Padding to RB_CMD_SIZE 1022 */ 1023 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1024 }; 1025 1026 /** 1027 * struct dmub_cmd_reg_wait_data - Register wait data 1028 */ 1029 struct dmub_cmd_reg_wait_data { 1030 uint32_t addr; /**< Register address */ 1031 uint32_t mask; /**< Mask for register bits */ 1032 uint32_t condition_field_value; /**< Value to wait for */ 1033 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1034 }; 1035 1036 /** 1037 * struct dmub_rb_cmd_reg_wait - Register wait command 1038 */ 1039 struct dmub_rb_cmd_reg_wait { 1040 struct dmub_cmd_header header; /**< Command header */ 1041 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1042 }; 1043 1044 /** 1045 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1046 * 1047 * Reprograms surface parameters to avoid underflow. 1048 */ 1049 struct dmub_cmd_PLAT_54186_wa { 1050 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1051 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1052 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1053 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1054 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1055 struct { 1056 uint8_t hubp_inst : 4; /**< HUBP instance */ 1057 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 1058 uint8_t immediate :1; /**< Immediate flip */ 1059 uint8_t vmid : 4; /**< VMID */ 1060 uint8_t grph_stereo : 1; /**< 1 if stereo */ 1061 uint32_t reserved : 21; /**< Reserved */ 1062 } flip_params; /**< Pageflip parameters */ 1063 uint32_t reserved[9]; /**< Reserved bits */ 1064 }; 1065 1066 /** 1067 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1068 */ 1069 struct dmub_rb_cmd_PLAT_54186_wa { 1070 struct dmub_cmd_header header; /**< Command header */ 1071 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1072 }; 1073 1074 /** 1075 * struct dmub_rb_cmd_mall - MALL command data. 1076 */ 1077 struct dmub_rb_cmd_mall { 1078 struct dmub_cmd_header header; /**< Common command header */ 1079 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1080 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1081 uint32_t tmr_delay; /**< Timer delay */ 1082 uint32_t tmr_scale; /**< Timer scale */ 1083 uint16_t cursor_width; /**< Cursor width in pixels */ 1084 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1085 uint16_t cursor_height; /**< Cursor height in pixels */ 1086 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1087 uint8_t debug_bits; /**< Debug bits */ 1088 1089 uint8_t reserved1; /**< Reserved bits */ 1090 uint8_t reserved2; /**< Reserved bits */ 1091 }; 1092 1093 /** 1094 * enum dmub_cmd_cab_type - CAB command data. 1095 */ 1096 enum dmub_cmd_cab_type { 1097 /** 1098 * No idle optimizations (i.e. no CAB) 1099 */ 1100 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1101 /** 1102 * No DCN requests for memory 1103 */ 1104 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1105 /** 1106 * Fit surfaces in CAB (i.e. CAB enable) 1107 */ 1108 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1109 }; 1110 1111 /** 1112 * struct dmub_rb_cmd_cab - CAB command data. 1113 */ 1114 struct dmub_rb_cmd_cab_for_ss { 1115 struct dmub_cmd_header header; 1116 uint8_t cab_alloc_ways; /* total number of ways */ 1117 uint8_t debug_bits; /* debug bits */ 1118 }; 1119 1120 /** 1121 * Enum for indicating which MCLK switch mode per pipe 1122 */ 1123 enum mclk_switch_mode { 1124 NONE = 0, 1125 FPO = 1, 1126 SUBVP = 2, 1127 VBLANK = 3, 1128 }; 1129 1130 /* Per pipe struct which stores the MCLK switch mode 1131 * data to be sent to DMUB. 1132 * Named "v2" for now -- once FPO and SUBVP are fully merged 1133 * the type name can be updated 1134 */ 1135 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1136 union { 1137 struct { 1138 uint32_t pix_clk_100hz; 1139 uint16_t main_vblank_start; 1140 uint16_t main_vblank_end; 1141 uint16_t mall_region_lines; 1142 uint16_t prefetch_lines; 1143 uint16_t prefetch_to_mall_start_lines; 1144 uint16_t processing_delay_lines; 1145 uint16_t htotal; // required to calculate line time for multi-display cases 1146 uint16_t vtotal; 1147 uint8_t main_pipe_index; 1148 uint8_t phantom_pipe_index; 1149 /* Since the microschedule is calculated in terms of OTG lines, 1150 * include any scaling factors to make sure when we get accurate 1151 * conversion when programming MALL_START_LINE (which is in terms 1152 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1153 * is 1/2 (numerator = 1, denominator = 2). 1154 */ 1155 uint8_t scale_factor_numerator; 1156 uint8_t scale_factor_denominator; 1157 uint8_t is_drr; 1158 uint8_t main_split_pipe_index; 1159 uint8_t phantom_split_pipe_index; 1160 } subvp_data; 1161 1162 struct { 1163 uint32_t pix_clk_100hz; 1164 uint16_t vblank_start; 1165 uint16_t vblank_end; 1166 uint16_t vstartup_start; 1167 uint16_t vtotal; 1168 uint16_t htotal; 1169 uint8_t vblank_pipe_index; 1170 uint8_t padding[1]; 1171 struct { 1172 uint8_t drr_in_use; 1173 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1174 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1175 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1176 uint8_t use_ramping; // Use ramping or not 1177 uint8_t drr_vblank_start_margin; 1178 } drr_info; // DRR considered as part of SubVP + VBLANK case 1179 } vblank_data; 1180 } pipe_config; 1181 1182 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1183 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1184 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1185 */ 1186 uint8_t mode; // enum mclk_switch_mode 1187 }; 1188 1189 /** 1190 * Config data for Sub-VP and FPO 1191 * Named "v2" for now -- once FPO and SUBVP are fully merged 1192 * the type name can be updated 1193 */ 1194 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1195 uint16_t watermark_a_cache; 1196 uint8_t vertical_int_margin_us; 1197 uint8_t pstate_allow_width_us; 1198 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1199 }; 1200 1201 /** 1202 * DMUB rb command definition for Sub-VP and FPO 1203 * Named "v2" for now -- once FPO and SUBVP are fully merged 1204 * the type name can be updated 1205 */ 1206 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1207 struct dmub_cmd_header header; 1208 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1209 }; 1210 1211 /** 1212 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1213 */ 1214 enum dmub_cmd_idle_opt_type { 1215 /** 1216 * DCN hardware restore. 1217 */ 1218 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1219 1220 /** 1221 * DCN hardware save. 1222 */ 1223 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1224 1225 /** 1226 * DCN hardware notify idle. 1227 */ 1228 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1229 }; 1230 1231 /** 1232 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1233 */ 1234 struct dmub_rb_cmd_idle_opt_dcn_restore { 1235 struct dmub_cmd_header header; /**< header */ 1236 }; 1237 1238 /** 1239 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1240 */ 1241 struct dmub_dcn_notify_idle_cntl_data { 1242 uint8_t driver_idle; 1243 uint8_t pad[1]; 1244 }; 1245 1246 /** 1247 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1248 */ 1249 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1250 struct dmub_cmd_header header; /**< header */ 1251 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1252 }; 1253 1254 /** 1255 * struct dmub_clocks - Clock update notification. 1256 */ 1257 struct dmub_clocks { 1258 uint32_t dispclk_khz; /**< dispclk kHz */ 1259 uint32_t dppclk_khz; /**< dppclk kHz */ 1260 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1261 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1262 }; 1263 1264 /** 1265 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1266 */ 1267 enum dmub_cmd_clk_mgr_type { 1268 /** 1269 * Notify DMCUB of clock update. 1270 */ 1271 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1272 }; 1273 1274 /** 1275 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1276 */ 1277 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1278 struct dmub_cmd_header header; /**< header */ 1279 struct dmub_clocks clocks; /**< clock data */ 1280 }; 1281 1282 /** 1283 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1284 */ 1285 struct dmub_cmd_digx_encoder_control_data { 1286 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1287 }; 1288 1289 /** 1290 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1291 */ 1292 struct dmub_rb_cmd_digx_encoder_control { 1293 struct dmub_cmd_header header; /**< header */ 1294 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1295 }; 1296 1297 /** 1298 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1299 */ 1300 struct dmub_cmd_set_pixel_clock_data { 1301 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1302 }; 1303 1304 /** 1305 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1306 */ 1307 struct dmub_rb_cmd_set_pixel_clock { 1308 struct dmub_cmd_header header; /**< header */ 1309 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1310 }; 1311 1312 /** 1313 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1314 */ 1315 struct dmub_cmd_enable_disp_power_gating_data { 1316 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1317 }; 1318 1319 /** 1320 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1321 */ 1322 struct dmub_rb_cmd_enable_disp_power_gating { 1323 struct dmub_cmd_header header; /**< header */ 1324 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1325 }; 1326 1327 /** 1328 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1329 */ 1330 struct dmub_dig_transmitter_control_data_v1_7 { 1331 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1332 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1333 union { 1334 uint8_t digmode; /**< enum atom_encode_mode_def */ 1335 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1336 } mode_laneset; 1337 uint8_t lanenum; /**< Number of lanes */ 1338 union { 1339 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1340 } symclk_units; 1341 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1342 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1343 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1344 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1345 uint8_t reserved1; /**< For future use */ 1346 uint8_t reserved2[3]; /**< For future use */ 1347 uint32_t reserved3[11]; /**< For future use */ 1348 }; 1349 1350 /** 1351 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1352 */ 1353 union dmub_cmd_dig1_transmitter_control_data { 1354 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1355 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1356 }; 1357 1358 /** 1359 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1360 */ 1361 struct dmub_rb_cmd_dig1_transmitter_control { 1362 struct dmub_cmd_header header; /**< header */ 1363 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1364 }; 1365 1366 /** 1367 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1368 */ 1369 struct dmub_rb_cmd_domain_control_data { 1370 uint8_t inst : 6; /**< DOMAIN instance to control */ 1371 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1372 uint8_t reserved[3]; /**< Reserved for future use */ 1373 }; 1374 1375 /** 1376 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1377 */ 1378 struct dmub_rb_cmd_domain_control { 1379 struct dmub_cmd_header header; /**< header */ 1380 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1381 }; 1382 1383 /** 1384 * DPIA tunnel command parameters. 1385 */ 1386 struct dmub_cmd_dig_dpia_control_data { 1387 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1388 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1389 union { 1390 uint8_t digmode; /** enum atom_encode_mode_def */ 1391 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1392 } mode_laneset; 1393 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1394 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1395 uint8_t hpdsel; /** =0: HPD is not assigned */ 1396 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1397 uint8_t dpia_id; /** Index of DPIA */ 1398 uint8_t fec_rdy : 1; 1399 uint8_t reserved : 7; 1400 uint32_t reserved1; 1401 }; 1402 1403 /** 1404 * DMUB command for DPIA tunnel control. 1405 */ 1406 struct dmub_rb_cmd_dig1_dpia_control { 1407 struct dmub_cmd_header header; 1408 struct dmub_cmd_dig_dpia_control_data dpia_control; 1409 }; 1410 1411 /** 1412 * SET_CONFIG Command Payload 1413 */ 1414 struct set_config_cmd_payload { 1415 uint8_t msg_type; /* set config message type */ 1416 uint8_t msg_data; /* set config message data */ 1417 }; 1418 1419 /** 1420 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1421 */ 1422 struct dmub_cmd_set_config_control_data { 1423 struct set_config_cmd_payload cmd_pkt; 1424 uint8_t instance; /* DPIA instance */ 1425 uint8_t immed_status; /* Immediate status returned in case of error */ 1426 }; 1427 1428 /** 1429 * DMUB command structure for SET_CONFIG command. 1430 */ 1431 struct dmub_rb_cmd_set_config_access { 1432 struct dmub_cmd_header header; /* header */ 1433 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1434 }; 1435 1436 /** 1437 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1438 */ 1439 struct dmub_cmd_mst_alloc_slots_control_data { 1440 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1441 uint8_t instance; /* DPIA instance */ 1442 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1443 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1444 }; 1445 1446 /** 1447 * DMUB command structure for SET_ command. 1448 */ 1449 struct dmub_rb_cmd_set_mst_alloc_slots { 1450 struct dmub_cmd_header header; /* header */ 1451 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1452 }; 1453 1454 /** 1455 * DMUB command structure for DPIA HPD int enable control. 1456 */ 1457 struct dmub_rb_cmd_dpia_hpd_int_enable { 1458 struct dmub_cmd_header header; /* header */ 1459 uint32_t enable; /* dpia hpd interrupt enable */ 1460 }; 1461 1462 /** 1463 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1464 */ 1465 struct dmub_rb_cmd_dpphy_init { 1466 struct dmub_cmd_header header; /**< header */ 1467 uint8_t reserved[60]; /**< reserved bits */ 1468 }; 1469 1470 /** 1471 * enum dp_aux_request_action - DP AUX request command listing. 1472 * 1473 * 4 AUX request command bits are shifted to high nibble. 1474 */ 1475 enum dp_aux_request_action { 1476 /** I2C-over-AUX write request */ 1477 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1478 /** I2C-over-AUX read request */ 1479 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1480 /** I2C-over-AUX write status request */ 1481 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1482 /** I2C-over-AUX write request with MOT=1 */ 1483 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1484 /** I2C-over-AUX read request with MOT=1 */ 1485 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1486 /** I2C-over-AUX write status request with MOT=1 */ 1487 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1488 /** Native AUX write request */ 1489 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1490 /** Native AUX read request */ 1491 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1492 }; 1493 1494 /** 1495 * enum aux_return_code_type - DP AUX process return code listing. 1496 */ 1497 enum aux_return_code_type { 1498 /** AUX process succeeded */ 1499 AUX_RET_SUCCESS = 0, 1500 /** AUX process failed with unknown reason */ 1501 AUX_RET_ERROR_UNKNOWN, 1502 /** AUX process completed with invalid reply */ 1503 AUX_RET_ERROR_INVALID_REPLY, 1504 /** AUX process timed out */ 1505 AUX_RET_ERROR_TIMEOUT, 1506 /** HPD was low during AUX process */ 1507 AUX_RET_ERROR_HPD_DISCON, 1508 /** Failed to acquire AUX engine */ 1509 AUX_RET_ERROR_ENGINE_ACQUIRE, 1510 /** AUX request not supported */ 1511 AUX_RET_ERROR_INVALID_OPERATION, 1512 /** AUX process not available */ 1513 AUX_RET_ERROR_PROTOCOL_ERROR, 1514 }; 1515 1516 /** 1517 * enum aux_channel_type - DP AUX channel type listing. 1518 */ 1519 enum aux_channel_type { 1520 /** AUX thru Legacy DP AUX */ 1521 AUX_CHANNEL_LEGACY_DDC, 1522 /** AUX thru DPIA DP tunneling */ 1523 AUX_CHANNEL_DPIA 1524 }; 1525 1526 /** 1527 * struct aux_transaction_parameters - DP AUX request transaction data 1528 */ 1529 struct aux_transaction_parameters { 1530 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1531 uint8_t action; /**< enum dp_aux_request_action */ 1532 uint8_t length; /**< DP AUX request data length */ 1533 uint8_t reserved; /**< For future use */ 1534 uint32_t address; /**< DP AUX address */ 1535 uint8_t data[16]; /**< DP AUX write data */ 1536 }; 1537 1538 /** 1539 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1540 */ 1541 struct dmub_cmd_dp_aux_control_data { 1542 uint8_t instance; /**< AUX instance or DPIA instance */ 1543 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1544 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1545 uint8_t reserved0; /**< For future use */ 1546 uint16_t timeout; /**< timeout time in us */ 1547 uint16_t reserved1; /**< For future use */ 1548 enum aux_channel_type type; /**< enum aux_channel_type */ 1549 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1550 }; 1551 1552 /** 1553 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1554 */ 1555 struct dmub_rb_cmd_dp_aux_access { 1556 /** 1557 * Command header. 1558 */ 1559 struct dmub_cmd_header header; 1560 /** 1561 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1562 */ 1563 struct dmub_cmd_dp_aux_control_data aux_control; 1564 }; 1565 1566 /** 1567 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1568 */ 1569 struct dmub_rb_cmd_outbox1_enable { 1570 /** 1571 * Command header. 1572 */ 1573 struct dmub_cmd_header header; 1574 /** 1575 * enable: 0x0 -> disable outbox1 notification (default value) 1576 * 0x1 -> enable outbox1 notification 1577 */ 1578 uint32_t enable; 1579 }; 1580 1581 /* DP AUX Reply command - OutBox Cmd */ 1582 /** 1583 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1584 */ 1585 struct aux_reply_data { 1586 /** 1587 * Aux cmd 1588 */ 1589 uint8_t command; 1590 /** 1591 * Aux reply data length (max: 16 bytes) 1592 */ 1593 uint8_t length; 1594 /** 1595 * Alignment only 1596 */ 1597 uint8_t pad[2]; 1598 /** 1599 * Aux reply data 1600 */ 1601 uint8_t data[16]; 1602 }; 1603 1604 /** 1605 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1606 */ 1607 struct aux_reply_control_data { 1608 /** 1609 * Reserved for future use 1610 */ 1611 uint32_t handle; 1612 /** 1613 * Aux Instance 1614 */ 1615 uint8_t instance; 1616 /** 1617 * Aux transaction result: definition in enum aux_return_code_type 1618 */ 1619 uint8_t result; 1620 /** 1621 * Alignment only 1622 */ 1623 uint16_t pad; 1624 }; 1625 1626 /** 1627 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1628 */ 1629 struct dmub_rb_cmd_dp_aux_reply { 1630 /** 1631 * Command header. 1632 */ 1633 struct dmub_cmd_header header; 1634 /** 1635 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1636 */ 1637 struct aux_reply_control_data control; 1638 /** 1639 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1640 */ 1641 struct aux_reply_data reply_data; 1642 }; 1643 1644 /* DP HPD Notify command - OutBox Cmd */ 1645 /** 1646 * DP HPD Type 1647 */ 1648 enum dp_hpd_type { 1649 /** 1650 * Normal DP HPD 1651 */ 1652 DP_HPD = 0, 1653 /** 1654 * DP HPD short pulse 1655 */ 1656 DP_IRQ 1657 }; 1658 1659 /** 1660 * DP HPD Status 1661 */ 1662 enum dp_hpd_status { 1663 /** 1664 * DP_HPD status low 1665 */ 1666 DP_HPD_UNPLUG = 0, 1667 /** 1668 * DP_HPD status high 1669 */ 1670 DP_HPD_PLUG 1671 }; 1672 1673 /** 1674 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1675 */ 1676 struct dp_hpd_data { 1677 /** 1678 * DP HPD instance 1679 */ 1680 uint8_t instance; 1681 /** 1682 * HPD type 1683 */ 1684 uint8_t hpd_type; 1685 /** 1686 * HPD status: only for type: DP_HPD to indicate status 1687 */ 1688 uint8_t hpd_status; 1689 /** 1690 * Alignment only 1691 */ 1692 uint8_t pad; 1693 }; 1694 1695 /** 1696 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1697 */ 1698 struct dmub_rb_cmd_dp_hpd_notify { 1699 /** 1700 * Command header. 1701 */ 1702 struct dmub_cmd_header header; 1703 /** 1704 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1705 */ 1706 struct dp_hpd_data hpd_data; 1707 }; 1708 1709 /** 1710 * Definition of a SET_CONFIG reply from DPOA. 1711 */ 1712 enum set_config_status { 1713 SET_CONFIG_PENDING = 0, 1714 SET_CONFIG_ACK_RECEIVED, 1715 SET_CONFIG_RX_TIMEOUT, 1716 SET_CONFIG_UNKNOWN_ERROR, 1717 }; 1718 1719 /** 1720 * Definition of a set_config reply 1721 */ 1722 struct set_config_reply_control_data { 1723 uint8_t instance; /* DPIA Instance */ 1724 uint8_t status; /* Set Config reply */ 1725 uint16_t pad; /* Alignment */ 1726 }; 1727 1728 /** 1729 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1730 */ 1731 struct dmub_rb_cmd_dp_set_config_reply { 1732 struct dmub_cmd_header header; 1733 struct set_config_reply_control_data set_config_reply_control; 1734 }; 1735 1736 /** 1737 * Definition of a DPIA notification header 1738 */ 1739 struct dpia_notification_header { 1740 uint8_t instance; /**< DPIA Instance */ 1741 uint8_t reserved[3]; 1742 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 1743 }; 1744 1745 /** 1746 * Definition of the common data struct of DPIA notification 1747 */ 1748 struct dpia_notification_common { 1749 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 1750 - sizeof(struct dpia_notification_header)]; 1751 }; 1752 1753 /** 1754 * Definition of a DPIA notification data 1755 */ 1756 struct dpia_bw_allocation_notify_data { 1757 union { 1758 struct { 1759 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 1760 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 1761 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 1762 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 1763 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 1764 uint16_t reserved: 11; /**< Reserved */ 1765 } bits; 1766 1767 uint16_t flags; 1768 }; 1769 1770 uint8_t cm_id; /**< CM ID */ 1771 uint8_t group_id; /**< Group ID */ 1772 uint8_t granularity; /**< BW Allocation Granularity */ 1773 uint8_t estimated_bw; /**< Estimated_BW */ 1774 uint8_t allocated_bw; /**< Allocated_BW */ 1775 uint8_t reserved; 1776 }; 1777 1778 /** 1779 * union dpia_notify_data_type - DPIA Notification in Outbox command 1780 */ 1781 union dpia_notification_data { 1782 /** 1783 * DPIA Notification for common data struct 1784 */ 1785 struct dpia_notification_common common_data; 1786 1787 /** 1788 * DPIA Notification for DP BW Allocation support 1789 */ 1790 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 1791 }; 1792 1793 /** 1794 * Definition of a DPIA notification payload 1795 */ 1796 struct dpia_notification_payload { 1797 struct dpia_notification_header header; 1798 union dpia_notification_data data; /**< DPIA notification payload data */ 1799 }; 1800 1801 /** 1802 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 1803 */ 1804 struct dmub_rb_cmd_dpia_notification { 1805 struct dmub_cmd_header header; /**< DPIA notification header */ 1806 struct dpia_notification_payload payload; /**< DPIA notification payload */ 1807 }; 1808 1809 /** 1810 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1811 */ 1812 struct dmub_cmd_hpd_state_query_data { 1813 uint8_t instance; /**< HPD instance or DPIA instance */ 1814 uint8_t result; /**< For returning HPD state */ 1815 uint16_t pad; /** < Alignment */ 1816 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1817 enum aux_return_code_type status; /**< for returning the status of command */ 1818 }; 1819 1820 /** 1821 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1822 */ 1823 struct dmub_rb_cmd_query_hpd_state { 1824 /** 1825 * Command header. 1826 */ 1827 struct dmub_cmd_header header; 1828 /** 1829 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1830 */ 1831 struct dmub_cmd_hpd_state_query_data data; 1832 }; 1833 1834 /* 1835 * Command IDs should be treated as stable ABI. 1836 * Do not reuse or modify IDs. 1837 */ 1838 1839 /** 1840 * PSR command sub-types. 1841 */ 1842 enum dmub_cmd_psr_type { 1843 /** 1844 * Set PSR version support. 1845 */ 1846 DMUB_CMD__PSR_SET_VERSION = 0, 1847 /** 1848 * Copy driver-calculated parameters to PSR state. 1849 */ 1850 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1851 /** 1852 * Enable PSR. 1853 */ 1854 DMUB_CMD__PSR_ENABLE = 2, 1855 1856 /** 1857 * Disable PSR. 1858 */ 1859 DMUB_CMD__PSR_DISABLE = 3, 1860 1861 /** 1862 * Set PSR level. 1863 * PSR level is a 16-bit value dicated by driver that 1864 * will enable/disable different functionality. 1865 */ 1866 DMUB_CMD__PSR_SET_LEVEL = 4, 1867 1868 /** 1869 * Forces PSR enabled until an explicit PSR disable call. 1870 */ 1871 DMUB_CMD__PSR_FORCE_STATIC = 5, 1872 /** 1873 * Set vtotal in psr active for FreeSync PSR. 1874 */ 1875 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1876 /** 1877 * Set PSR power option 1878 */ 1879 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1880 }; 1881 1882 enum dmub_cmd_fams_type { 1883 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1884 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1885 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1886 /** 1887 * For SubVP set manual trigger in FW because it 1888 * triggers DRR_UPDATE_PENDING which SubVP relies 1889 * on (for any SubVP cases that use a DRR display) 1890 */ 1891 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1892 }; 1893 1894 /** 1895 * PSR versions. 1896 */ 1897 enum psr_version { 1898 /** 1899 * PSR version 1. 1900 */ 1901 PSR_VERSION_1 = 0, 1902 /** 1903 * Freesync PSR SU. 1904 */ 1905 PSR_VERSION_SU_1 = 1, 1906 /** 1907 * PSR not supported. 1908 */ 1909 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1910 }; 1911 1912 /** 1913 * enum dmub_cmd_mall_type - MALL commands 1914 */ 1915 enum dmub_cmd_mall_type { 1916 /** 1917 * Allows display refresh from MALL. 1918 */ 1919 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1920 /** 1921 * Disallows display refresh from MALL. 1922 */ 1923 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1924 /** 1925 * Cursor copy for MALL. 1926 */ 1927 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1928 /** 1929 * Controls DF requests. 1930 */ 1931 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1932 }; 1933 1934 /** 1935 * PHY Link rate for DP. 1936 */ 1937 enum phy_link_rate { 1938 /** 1939 * not supported. 1940 */ 1941 PHY_RATE_UNKNOWN = 0, 1942 /** 1943 * Rate_1 (RBR) - 1.62 Gbps/Lane 1944 */ 1945 PHY_RATE_162 = 1, 1946 /** 1947 * Rate_2 - 2.16 Gbps/Lane 1948 */ 1949 PHY_RATE_216 = 2, 1950 /** 1951 * Rate_3 - 2.43 Gbps/Lane 1952 */ 1953 PHY_RATE_243 = 3, 1954 /** 1955 * Rate_4 (HBR) - 2.70 Gbps/Lane 1956 */ 1957 PHY_RATE_270 = 4, 1958 /** 1959 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1960 */ 1961 PHY_RATE_324 = 5, 1962 /** 1963 * Rate_6 - 4.32 Gbps/Lane 1964 */ 1965 PHY_RATE_432 = 6, 1966 /** 1967 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1968 */ 1969 PHY_RATE_540 = 7, 1970 /** 1971 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1972 */ 1973 PHY_RATE_810 = 8, 1974 /** 1975 * UHBR10 - 10.0 Gbps/Lane 1976 */ 1977 PHY_RATE_1000 = 9, 1978 /** 1979 * UHBR13.5 - 13.5 Gbps/Lane 1980 */ 1981 PHY_RATE_1350 = 10, 1982 /** 1983 * UHBR10 - 20.0 Gbps/Lane 1984 */ 1985 PHY_RATE_2000 = 11, 1986 }; 1987 1988 /** 1989 * enum dmub_phy_fsm_state - PHY FSM states. 1990 * PHY FSM state to transit to during PSR enable/disable. 1991 */ 1992 enum dmub_phy_fsm_state { 1993 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1994 DMUB_PHY_FSM_RESET, 1995 DMUB_PHY_FSM_RESET_RELEASED, 1996 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1997 DMUB_PHY_FSM_INITIALIZED, 1998 DMUB_PHY_FSM_CALIBRATED, 1999 DMUB_PHY_FSM_CALIBRATED_LP, 2000 DMUB_PHY_FSM_CALIBRATED_PG, 2001 DMUB_PHY_FSM_POWER_DOWN, 2002 DMUB_PHY_FSM_PLL_EN, 2003 DMUB_PHY_FSM_TX_EN, 2004 DMUB_PHY_FSM_FAST_LP, 2005 }; 2006 2007 /** 2008 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2009 */ 2010 struct dmub_cmd_psr_copy_settings_data { 2011 /** 2012 * Flags that can be set by driver to change some PSR behaviour. 2013 */ 2014 union dmub_psr_debug_flags debug; 2015 /** 2016 * 16-bit value dicated by driver that will enable/disable different functionality. 2017 */ 2018 uint16_t psr_level; 2019 /** 2020 * DPP HW instance. 2021 */ 2022 uint8_t dpp_inst; 2023 /** 2024 * MPCC HW instance. 2025 * Not used in dmub fw, 2026 * dmub fw will get active opp by reading odm registers. 2027 */ 2028 uint8_t mpcc_inst; 2029 /** 2030 * OPP HW instance. 2031 * Not used in dmub fw, 2032 * dmub fw will get active opp by reading odm registers. 2033 */ 2034 uint8_t opp_inst; 2035 /** 2036 * OTG HW instance. 2037 */ 2038 uint8_t otg_inst; 2039 /** 2040 * DIG FE HW instance. 2041 */ 2042 uint8_t digfe_inst; 2043 /** 2044 * DIG BE HW instance. 2045 */ 2046 uint8_t digbe_inst; 2047 /** 2048 * DP PHY HW instance. 2049 */ 2050 uint8_t dpphy_inst; 2051 /** 2052 * AUX HW instance. 2053 */ 2054 uint8_t aux_inst; 2055 /** 2056 * Determines if SMU optimzations are enabled/disabled. 2057 */ 2058 uint8_t smu_optimizations_en; 2059 /** 2060 * Unused. 2061 * TODO: Remove. 2062 */ 2063 uint8_t frame_delay; 2064 /** 2065 * If RFB setup time is greater than the total VBLANK time, 2066 * it is not possible for the sink to capture the video frame 2067 * in the same frame the SDP is sent. In this case, 2068 * the frame capture indication bit should be set and an extra 2069 * static frame should be transmitted to the sink. 2070 */ 2071 uint8_t frame_cap_ind; 2072 /** 2073 * Granularity of Y offset supported by sink. 2074 */ 2075 uint8_t su_y_granularity; 2076 /** 2077 * Indicates whether sink should start capturing 2078 * immediately following active scan line, 2079 * or starting with the 2nd active scan line. 2080 */ 2081 uint8_t line_capture_indication; 2082 /** 2083 * Multi-display optimizations are implemented on certain ASICs. 2084 */ 2085 uint8_t multi_disp_optimizations_en; 2086 /** 2087 * The last possible line SDP may be transmitted without violating 2088 * the RFB setup time or entering the active video frame. 2089 */ 2090 uint16_t init_sdp_deadline; 2091 /** 2092 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2093 */ 2094 uint8_t rate_control_caps ; 2095 /* 2096 * Force PSRSU always doing full frame update 2097 */ 2098 uint8_t force_ffu_mode; 2099 /** 2100 * Length of each horizontal line in us. 2101 */ 2102 uint32_t line_time_in_us; 2103 /** 2104 * FEC enable status in driver 2105 */ 2106 uint8_t fec_enable_status; 2107 /** 2108 * FEC re-enable delay when PSR exit. 2109 * unit is 100us, range form 0~255(0xFF). 2110 */ 2111 uint8_t fec_enable_delay_in100us; 2112 /** 2113 * PSR control version. 2114 */ 2115 uint8_t cmd_version; 2116 /** 2117 * Panel Instance. 2118 * Panel instance to identify which psr_state to use 2119 * Currently the support is only for 0 or 1 2120 */ 2121 uint8_t panel_inst; 2122 /* 2123 * DSC enable status in driver 2124 */ 2125 uint8_t dsc_enable_status; 2126 /* 2127 * Use FSM state for PSR power up/down 2128 */ 2129 uint8_t use_phy_fsm; 2130 /** 2131 * frame delay for frame re-lock 2132 */ 2133 uint8_t relock_delay_frame_cnt; 2134 /** 2135 * Explicit padding to 2 byte boundary. 2136 */ 2137 uint8_t pad3; 2138 /** 2139 * DSC Slice height. 2140 */ 2141 uint16_t dsc_slice_height; 2142 /** 2143 * Explicit padding to 4 byte boundary. 2144 */ 2145 uint16_t pad; 2146 }; 2147 2148 /** 2149 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2150 */ 2151 struct dmub_rb_cmd_psr_copy_settings { 2152 /** 2153 * Command header. 2154 */ 2155 struct dmub_cmd_header header; 2156 /** 2157 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2158 */ 2159 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2160 }; 2161 2162 /** 2163 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2164 */ 2165 struct dmub_cmd_psr_set_level_data { 2166 /** 2167 * 16-bit value dicated by driver that will enable/disable different functionality. 2168 */ 2169 uint16_t psr_level; 2170 /** 2171 * PSR control version. 2172 */ 2173 uint8_t cmd_version; 2174 /** 2175 * Panel Instance. 2176 * Panel instance to identify which psr_state to use 2177 * Currently the support is only for 0 or 1 2178 */ 2179 uint8_t panel_inst; 2180 }; 2181 2182 /** 2183 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2184 */ 2185 struct dmub_rb_cmd_psr_set_level { 2186 /** 2187 * Command header. 2188 */ 2189 struct dmub_cmd_header header; 2190 /** 2191 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2192 */ 2193 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2194 }; 2195 2196 struct dmub_rb_cmd_psr_enable_data { 2197 /** 2198 * PSR control version. 2199 */ 2200 uint8_t cmd_version; 2201 /** 2202 * Panel Instance. 2203 * Panel instance to identify which psr_state to use 2204 * Currently the support is only for 0 or 1 2205 */ 2206 uint8_t panel_inst; 2207 /** 2208 * Phy state to enter. 2209 * Values to use are defined in dmub_phy_fsm_state 2210 */ 2211 uint8_t phy_fsm_state; 2212 /** 2213 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2214 * Set this using enum phy_link_rate. 2215 * This does not support HDMI/DP2 for now. 2216 */ 2217 uint8_t phy_rate; 2218 }; 2219 2220 /** 2221 * Definition of a DMUB_CMD__PSR_ENABLE command. 2222 * PSR enable/disable is controlled using the sub_type. 2223 */ 2224 struct dmub_rb_cmd_psr_enable { 2225 /** 2226 * Command header. 2227 */ 2228 struct dmub_cmd_header header; 2229 2230 struct dmub_rb_cmd_psr_enable_data data; 2231 }; 2232 2233 /** 2234 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2235 */ 2236 struct dmub_cmd_psr_set_version_data { 2237 /** 2238 * PSR version that FW should implement. 2239 */ 2240 enum psr_version version; 2241 /** 2242 * PSR control version. 2243 */ 2244 uint8_t cmd_version; 2245 /** 2246 * Panel Instance. 2247 * Panel instance to identify which psr_state to use 2248 * Currently the support is only for 0 or 1 2249 */ 2250 uint8_t panel_inst; 2251 /** 2252 * Explicit padding to 4 byte boundary. 2253 */ 2254 uint8_t pad[2]; 2255 }; 2256 2257 /** 2258 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2259 */ 2260 struct dmub_rb_cmd_psr_set_version { 2261 /** 2262 * Command header. 2263 */ 2264 struct dmub_cmd_header header; 2265 /** 2266 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2267 */ 2268 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2269 }; 2270 2271 struct dmub_cmd_psr_force_static_data { 2272 /** 2273 * PSR control version. 2274 */ 2275 uint8_t cmd_version; 2276 /** 2277 * Panel Instance. 2278 * Panel instance to identify which psr_state to use 2279 * Currently the support is only for 0 or 1 2280 */ 2281 uint8_t panel_inst; 2282 /** 2283 * Explicit padding to 4 byte boundary. 2284 */ 2285 uint8_t pad[2]; 2286 }; 2287 2288 /** 2289 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2290 */ 2291 struct dmub_rb_cmd_psr_force_static { 2292 /** 2293 * Command header. 2294 */ 2295 struct dmub_cmd_header header; 2296 /** 2297 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2298 */ 2299 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2300 }; 2301 2302 /** 2303 * PSR SU debug flags. 2304 */ 2305 union dmub_psr_su_debug_flags { 2306 /** 2307 * PSR SU debug flags. 2308 */ 2309 struct { 2310 /** 2311 * Update dirty rect in SW only. 2312 */ 2313 uint8_t update_dirty_rect_only : 1; 2314 /** 2315 * Reset the cursor/plane state before processing the call. 2316 */ 2317 uint8_t reset_state : 1; 2318 } bitfields; 2319 2320 /** 2321 * Union for debug flags. 2322 */ 2323 uint32_t u32All; 2324 }; 2325 2326 /** 2327 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2328 * This triggers a selective update for PSR SU. 2329 */ 2330 struct dmub_cmd_update_dirty_rect_data { 2331 /** 2332 * Dirty rects from OS. 2333 */ 2334 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2335 /** 2336 * PSR SU debug flags. 2337 */ 2338 union dmub_psr_su_debug_flags debug_flags; 2339 /** 2340 * OTG HW instance. 2341 */ 2342 uint8_t pipe_idx; 2343 /** 2344 * Number of dirty rects. 2345 */ 2346 uint8_t dirty_rect_count; 2347 /** 2348 * PSR control version. 2349 */ 2350 uint8_t cmd_version; 2351 /** 2352 * Panel Instance. 2353 * Panel instance to identify which psr_state to use 2354 * Currently the support is only for 0 or 1 2355 */ 2356 uint8_t panel_inst; 2357 }; 2358 2359 /** 2360 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2361 */ 2362 struct dmub_rb_cmd_update_dirty_rect { 2363 /** 2364 * Command header. 2365 */ 2366 struct dmub_cmd_header header; 2367 /** 2368 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2369 */ 2370 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2371 }; 2372 2373 /** 2374 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2375 */ 2376 union dmub_reg_cursor_control_cfg { 2377 struct { 2378 uint32_t cur_enable: 1; 2379 uint32_t reser0: 3; 2380 uint32_t cur_2x_magnify: 1; 2381 uint32_t reser1: 3; 2382 uint32_t mode: 3; 2383 uint32_t reser2: 5; 2384 uint32_t pitch: 2; 2385 uint32_t reser3: 6; 2386 uint32_t line_per_chunk: 5; 2387 uint32_t reser4: 3; 2388 } bits; 2389 uint32_t raw; 2390 }; 2391 struct dmub_cursor_position_cache_hubp { 2392 union dmub_reg_cursor_control_cfg cur_ctl; 2393 union dmub_reg_position_cfg { 2394 struct { 2395 uint32_t cur_x_pos: 16; 2396 uint32_t cur_y_pos: 16; 2397 } bits; 2398 uint32_t raw; 2399 } position; 2400 union dmub_reg_hot_spot_cfg { 2401 struct { 2402 uint32_t hot_x: 16; 2403 uint32_t hot_y: 16; 2404 } bits; 2405 uint32_t raw; 2406 } hot_spot; 2407 union dmub_reg_dst_offset_cfg { 2408 struct { 2409 uint32_t dst_x_offset: 13; 2410 uint32_t reserved: 19; 2411 } bits; 2412 uint32_t raw; 2413 } dst_offset; 2414 }; 2415 2416 union dmub_reg_cur0_control_cfg { 2417 struct { 2418 uint32_t cur0_enable: 1; 2419 uint32_t expansion_mode: 1; 2420 uint32_t reser0: 1; 2421 uint32_t cur0_rom_en: 1; 2422 uint32_t mode: 3; 2423 uint32_t reserved: 25; 2424 } bits; 2425 uint32_t raw; 2426 }; 2427 struct dmub_cursor_position_cache_dpp { 2428 union dmub_reg_cur0_control_cfg cur0_ctl; 2429 }; 2430 struct dmub_cursor_position_cfg { 2431 struct dmub_cursor_position_cache_hubp pHubp; 2432 struct dmub_cursor_position_cache_dpp pDpp; 2433 uint8_t pipe_idx; 2434 /* 2435 * Padding is required. To be 4 Bytes Aligned. 2436 */ 2437 uint8_t padding[3]; 2438 }; 2439 2440 struct dmub_cursor_attribute_cache_hubp { 2441 uint32_t SURFACE_ADDR_HIGH; 2442 uint32_t SURFACE_ADDR; 2443 union dmub_reg_cursor_control_cfg cur_ctl; 2444 union dmub_reg_cursor_size_cfg { 2445 struct { 2446 uint32_t width: 16; 2447 uint32_t height: 16; 2448 } bits; 2449 uint32_t raw; 2450 } size; 2451 union dmub_reg_cursor_settings_cfg { 2452 struct { 2453 uint32_t dst_y_offset: 8; 2454 uint32_t chunk_hdl_adjust: 2; 2455 uint32_t reserved: 22; 2456 } bits; 2457 uint32_t raw; 2458 } settings; 2459 }; 2460 struct dmub_cursor_attribute_cache_dpp { 2461 union dmub_reg_cur0_control_cfg cur0_ctl; 2462 }; 2463 struct dmub_cursor_attributes_cfg { 2464 struct dmub_cursor_attribute_cache_hubp aHubp; 2465 struct dmub_cursor_attribute_cache_dpp aDpp; 2466 }; 2467 2468 struct dmub_cmd_update_cursor_payload0 { 2469 /** 2470 * Cursor dirty rects. 2471 */ 2472 struct dmub_rect cursor_rect; 2473 /** 2474 * PSR SU debug flags. 2475 */ 2476 union dmub_psr_su_debug_flags debug_flags; 2477 /** 2478 * Cursor enable/disable. 2479 */ 2480 uint8_t enable; 2481 /** 2482 * OTG HW instance. 2483 */ 2484 uint8_t pipe_idx; 2485 /** 2486 * PSR control version. 2487 */ 2488 uint8_t cmd_version; 2489 /** 2490 * Panel Instance. 2491 * Panel instance to identify which psr_state to use 2492 * Currently the support is only for 0 or 1 2493 */ 2494 uint8_t panel_inst; 2495 /** 2496 * Cursor Position Register. 2497 * Registers contains Hubp & Dpp modules 2498 */ 2499 struct dmub_cursor_position_cfg position_cfg; 2500 }; 2501 2502 struct dmub_cmd_update_cursor_payload1 { 2503 struct dmub_cursor_attributes_cfg attribute_cfg; 2504 }; 2505 2506 union dmub_cmd_update_cursor_info_data { 2507 struct dmub_cmd_update_cursor_payload0 payload0; 2508 struct dmub_cmd_update_cursor_payload1 payload1; 2509 }; 2510 /** 2511 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2512 */ 2513 struct dmub_rb_cmd_update_cursor_info { 2514 /** 2515 * Command header. 2516 */ 2517 struct dmub_cmd_header header; 2518 /** 2519 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2520 */ 2521 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2522 }; 2523 2524 /** 2525 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2526 */ 2527 struct dmub_cmd_psr_set_vtotal_data { 2528 /** 2529 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2530 */ 2531 uint16_t psr_vtotal_idle; 2532 /** 2533 * PSR control version. 2534 */ 2535 uint8_t cmd_version; 2536 /** 2537 * Panel Instance. 2538 * Panel instance to identify which psr_state to use 2539 * Currently the support is only for 0 or 1 2540 */ 2541 uint8_t panel_inst; 2542 /* 2543 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2544 */ 2545 uint16_t psr_vtotal_su; 2546 /** 2547 * Explicit padding to 4 byte boundary. 2548 */ 2549 uint8_t pad2[2]; 2550 }; 2551 2552 /** 2553 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2554 */ 2555 struct dmub_rb_cmd_psr_set_vtotal { 2556 /** 2557 * Command header. 2558 */ 2559 struct dmub_cmd_header header; 2560 /** 2561 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2562 */ 2563 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2564 }; 2565 2566 /** 2567 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2568 */ 2569 struct dmub_cmd_psr_set_power_opt_data { 2570 /** 2571 * PSR control version. 2572 */ 2573 uint8_t cmd_version; 2574 /** 2575 * Panel Instance. 2576 * Panel instance to identify which psr_state to use 2577 * Currently the support is only for 0 or 1 2578 */ 2579 uint8_t panel_inst; 2580 /** 2581 * Explicit padding to 4 byte boundary. 2582 */ 2583 uint8_t pad[2]; 2584 /** 2585 * PSR power option 2586 */ 2587 uint32_t power_opt; 2588 }; 2589 2590 /** 2591 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2592 */ 2593 struct dmub_rb_cmd_psr_set_power_opt { 2594 /** 2595 * Command header. 2596 */ 2597 struct dmub_cmd_header header; 2598 /** 2599 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2600 */ 2601 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2602 }; 2603 2604 /** 2605 * Set of HW components that can be locked. 2606 * 2607 * Note: If updating with more HW components, fields 2608 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2609 */ 2610 union dmub_hw_lock_flags { 2611 /** 2612 * Set of HW components that can be locked. 2613 */ 2614 struct { 2615 /** 2616 * Lock/unlock OTG master update lock. 2617 */ 2618 uint8_t lock_pipe : 1; 2619 /** 2620 * Lock/unlock cursor. 2621 */ 2622 uint8_t lock_cursor : 1; 2623 /** 2624 * Lock/unlock global update lock. 2625 */ 2626 uint8_t lock_dig : 1; 2627 /** 2628 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2629 */ 2630 uint8_t triple_buffer_lock : 1; 2631 } bits; 2632 2633 /** 2634 * Union for HW Lock flags. 2635 */ 2636 uint8_t u8All; 2637 }; 2638 2639 /** 2640 * Instances of HW to be locked. 2641 * 2642 * Note: If updating with more HW components, fields 2643 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2644 */ 2645 struct dmub_hw_lock_inst_flags { 2646 /** 2647 * OTG HW instance for OTG master update lock. 2648 */ 2649 uint8_t otg_inst; 2650 /** 2651 * OPP instance for cursor lock. 2652 */ 2653 uint8_t opp_inst; 2654 /** 2655 * OTG HW instance for global update lock. 2656 * TODO: Remove, and re-use otg_inst. 2657 */ 2658 uint8_t dig_inst; 2659 /** 2660 * Explicit pad to 4 byte boundary. 2661 */ 2662 uint8_t pad; 2663 }; 2664 2665 /** 2666 * Clients that can acquire the HW Lock Manager. 2667 * 2668 * Note: If updating with more clients, fields in 2669 * dmub_inbox0_cmd_lock_hw must be updated to match. 2670 */ 2671 enum hw_lock_client { 2672 /** 2673 * Driver is the client of HW Lock Manager. 2674 */ 2675 HW_LOCK_CLIENT_DRIVER = 0, 2676 /** 2677 * PSR SU is the client of HW Lock Manager. 2678 */ 2679 HW_LOCK_CLIENT_PSR_SU = 1, 2680 /** 2681 * Invalid client. 2682 */ 2683 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2684 }; 2685 2686 /** 2687 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2688 */ 2689 struct dmub_cmd_lock_hw_data { 2690 /** 2691 * Specifies the client accessing HW Lock Manager. 2692 */ 2693 enum hw_lock_client client; 2694 /** 2695 * HW instances to be locked. 2696 */ 2697 struct dmub_hw_lock_inst_flags inst_flags; 2698 /** 2699 * Which components to be locked. 2700 */ 2701 union dmub_hw_lock_flags hw_locks; 2702 /** 2703 * Specifies lock/unlock. 2704 */ 2705 uint8_t lock; 2706 /** 2707 * HW can be unlocked separately from releasing the HW Lock Mgr. 2708 * This flag is set if the client wishes to release the object. 2709 */ 2710 uint8_t should_release; 2711 /** 2712 * Explicit padding to 4 byte boundary. 2713 */ 2714 uint8_t pad; 2715 }; 2716 2717 /** 2718 * Definition of a DMUB_CMD__HW_LOCK command. 2719 * Command is used by driver and FW. 2720 */ 2721 struct dmub_rb_cmd_lock_hw { 2722 /** 2723 * Command header. 2724 */ 2725 struct dmub_cmd_header header; 2726 /** 2727 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2728 */ 2729 struct dmub_cmd_lock_hw_data lock_hw_data; 2730 }; 2731 2732 /** 2733 * ABM command sub-types. 2734 */ 2735 enum dmub_cmd_abm_type { 2736 /** 2737 * Initialize parameters for ABM algorithm. 2738 * Data is passed through an indirect buffer. 2739 */ 2740 DMUB_CMD__ABM_INIT_CONFIG = 0, 2741 /** 2742 * Set OTG and panel HW instance. 2743 */ 2744 DMUB_CMD__ABM_SET_PIPE = 1, 2745 /** 2746 * Set user requested backklight level. 2747 */ 2748 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2749 /** 2750 * Set ABM operating/aggression level. 2751 */ 2752 DMUB_CMD__ABM_SET_LEVEL = 3, 2753 /** 2754 * Set ambient light level. 2755 */ 2756 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2757 /** 2758 * Enable/disable fractional duty cycle for backlight PWM. 2759 */ 2760 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2761 2762 /** 2763 * unregister vertical interrupt after steady state is reached 2764 */ 2765 DMUB_CMD__ABM_PAUSE = 6, 2766 2767 /** 2768 * Save and Restore ABM state. On save we save parameters, and 2769 * on restore we update state with passed in data. 2770 */ 2771 DMUB_CMD__ABM_SAVE_RESTORE = 7, 2772 }; 2773 2774 /** 2775 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2776 * Requirements: 2777 * - Padded explicitly to 32-bit boundary. 2778 * - Must ensure this structure matches the one on driver-side, 2779 * otherwise it won't be aligned. 2780 */ 2781 struct abm_config_table { 2782 /** 2783 * Gamma curve thresholds, used for crgb conversion. 2784 */ 2785 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2786 /** 2787 * Gamma curve offsets, used for crgb conversion. 2788 */ 2789 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2790 /** 2791 * Gamma curve slopes, used for crgb conversion. 2792 */ 2793 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2794 /** 2795 * Custom backlight curve thresholds. 2796 */ 2797 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2798 /** 2799 * Custom backlight curve offsets. 2800 */ 2801 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2802 /** 2803 * Ambient light thresholds. 2804 */ 2805 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2806 /** 2807 * Minimum programmable backlight. 2808 */ 2809 uint16_t min_abm_backlight; // 122B 2810 /** 2811 * Minimum reduction values. 2812 */ 2813 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2814 /** 2815 * Maximum reduction values. 2816 */ 2817 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2818 /** 2819 * Bright positive gain. 2820 */ 2821 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2822 /** 2823 * Dark negative gain. 2824 */ 2825 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2826 /** 2827 * Hybrid factor. 2828 */ 2829 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2830 /** 2831 * Contrast factor. 2832 */ 2833 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2834 /** 2835 * Deviation gain. 2836 */ 2837 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2838 /** 2839 * Minimum knee. 2840 */ 2841 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2842 /** 2843 * Maximum knee. 2844 */ 2845 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2846 /** 2847 * Unused. 2848 */ 2849 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2850 /** 2851 * Explicit padding to 4 byte boundary. 2852 */ 2853 uint8_t pad3[3]; // 229B 2854 /** 2855 * Backlight ramp reduction. 2856 */ 2857 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2858 /** 2859 * Backlight ramp start. 2860 */ 2861 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2862 }; 2863 2864 /** 2865 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2866 */ 2867 struct dmub_cmd_abm_set_pipe_data { 2868 /** 2869 * OTG HW instance. 2870 */ 2871 uint8_t otg_inst; 2872 2873 /** 2874 * Panel Control HW instance. 2875 */ 2876 uint8_t panel_inst; 2877 2878 /** 2879 * Controls how ABM will interpret a set pipe or set level command. 2880 */ 2881 uint8_t set_pipe_option; 2882 2883 /** 2884 * Unused. 2885 * TODO: Remove. 2886 */ 2887 uint8_t ramping_boundary; 2888 }; 2889 2890 /** 2891 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2892 */ 2893 struct dmub_rb_cmd_abm_set_pipe { 2894 /** 2895 * Command header. 2896 */ 2897 struct dmub_cmd_header header; 2898 2899 /** 2900 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2901 */ 2902 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2903 }; 2904 2905 /** 2906 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2907 */ 2908 struct dmub_cmd_abm_set_backlight_data { 2909 /** 2910 * Number of frames to ramp to backlight user level. 2911 */ 2912 uint32_t frame_ramp; 2913 2914 /** 2915 * Requested backlight level from user. 2916 */ 2917 uint32_t backlight_user_level; 2918 2919 /** 2920 * ABM control version. 2921 */ 2922 uint8_t version; 2923 2924 /** 2925 * Panel Control HW instance mask. 2926 * Bit 0 is Panel Control HW instance 0. 2927 * Bit 1 is Panel Control HW instance 1. 2928 */ 2929 uint8_t panel_mask; 2930 2931 /** 2932 * Explicit padding to 4 byte boundary. 2933 */ 2934 uint8_t pad[2]; 2935 }; 2936 2937 /** 2938 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2939 */ 2940 struct dmub_rb_cmd_abm_set_backlight { 2941 /** 2942 * Command header. 2943 */ 2944 struct dmub_cmd_header header; 2945 2946 /** 2947 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2948 */ 2949 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2950 }; 2951 2952 /** 2953 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2954 */ 2955 struct dmub_cmd_abm_set_level_data { 2956 /** 2957 * Set current ABM operating/aggression level. 2958 */ 2959 uint32_t level; 2960 2961 /** 2962 * ABM control version. 2963 */ 2964 uint8_t version; 2965 2966 /** 2967 * Panel Control HW instance mask. 2968 * Bit 0 is Panel Control HW instance 0. 2969 * Bit 1 is Panel Control HW instance 1. 2970 */ 2971 uint8_t panel_mask; 2972 2973 /** 2974 * Explicit padding to 4 byte boundary. 2975 */ 2976 uint8_t pad[2]; 2977 }; 2978 2979 /** 2980 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2981 */ 2982 struct dmub_rb_cmd_abm_set_level { 2983 /** 2984 * Command header. 2985 */ 2986 struct dmub_cmd_header header; 2987 2988 /** 2989 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2990 */ 2991 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2992 }; 2993 2994 /** 2995 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2996 */ 2997 struct dmub_cmd_abm_set_ambient_level_data { 2998 /** 2999 * Ambient light sensor reading from OS. 3000 */ 3001 uint32_t ambient_lux; 3002 3003 /** 3004 * ABM control version. 3005 */ 3006 uint8_t version; 3007 3008 /** 3009 * Panel Control HW instance mask. 3010 * Bit 0 is Panel Control HW instance 0. 3011 * Bit 1 is Panel Control HW instance 1. 3012 */ 3013 uint8_t panel_mask; 3014 3015 /** 3016 * Explicit padding to 4 byte boundary. 3017 */ 3018 uint8_t pad[2]; 3019 }; 3020 3021 /** 3022 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3023 */ 3024 struct dmub_rb_cmd_abm_set_ambient_level { 3025 /** 3026 * Command header. 3027 */ 3028 struct dmub_cmd_header header; 3029 3030 /** 3031 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3032 */ 3033 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 3034 }; 3035 3036 /** 3037 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 3038 */ 3039 struct dmub_cmd_abm_set_pwm_frac_data { 3040 /** 3041 * Enable/disable fractional duty cycle for backlight PWM. 3042 * TODO: Convert to uint8_t. 3043 */ 3044 uint32_t fractional_pwm; 3045 3046 /** 3047 * ABM control version. 3048 */ 3049 uint8_t version; 3050 3051 /** 3052 * Panel Control HW instance mask. 3053 * Bit 0 is Panel Control HW instance 0. 3054 * Bit 1 is Panel Control HW instance 1. 3055 */ 3056 uint8_t panel_mask; 3057 3058 /** 3059 * Explicit padding to 4 byte boundary. 3060 */ 3061 uint8_t pad[2]; 3062 }; 3063 3064 /** 3065 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3066 */ 3067 struct dmub_rb_cmd_abm_set_pwm_frac { 3068 /** 3069 * Command header. 3070 */ 3071 struct dmub_cmd_header header; 3072 3073 /** 3074 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 3075 */ 3076 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 3077 }; 3078 3079 /** 3080 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3081 */ 3082 struct dmub_cmd_abm_init_config_data { 3083 /** 3084 * Location of indirect buffer used to pass init data to ABM. 3085 */ 3086 union dmub_addr src; 3087 3088 /** 3089 * Indirect buffer length. 3090 */ 3091 uint16_t bytes; 3092 3093 3094 /** 3095 * ABM control version. 3096 */ 3097 uint8_t version; 3098 3099 /** 3100 * Panel Control HW instance mask. 3101 * Bit 0 is Panel Control HW instance 0. 3102 * Bit 1 is Panel Control HW instance 1. 3103 */ 3104 uint8_t panel_mask; 3105 3106 /** 3107 * Explicit padding to 4 byte boundary. 3108 */ 3109 uint8_t pad[2]; 3110 }; 3111 3112 /** 3113 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3114 */ 3115 struct dmub_rb_cmd_abm_init_config { 3116 /** 3117 * Command header. 3118 */ 3119 struct dmub_cmd_header header; 3120 3121 /** 3122 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3123 */ 3124 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3125 }; 3126 3127 /** 3128 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3129 */ 3130 3131 struct dmub_cmd_abm_pause_data { 3132 3133 /** 3134 * Panel Control HW instance mask. 3135 * Bit 0 is Panel Control HW instance 0. 3136 * Bit 1 is Panel Control HW instance 1. 3137 */ 3138 uint8_t panel_mask; 3139 3140 /** 3141 * OTG hw instance 3142 */ 3143 uint8_t otg_inst; 3144 3145 /** 3146 * Enable or disable ABM pause 3147 */ 3148 uint8_t enable; 3149 3150 /** 3151 * Explicit padding to 4 byte boundary. 3152 */ 3153 uint8_t pad[1]; 3154 }; 3155 3156 3157 /** 3158 * Definition of a DMUB_CMD__ABM_PAUSE command. 3159 */ 3160 struct dmub_rb_cmd_abm_pause { 3161 /** 3162 * Command header. 3163 */ 3164 struct dmub_cmd_header header; 3165 3166 /** 3167 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3168 */ 3169 struct dmub_cmd_abm_pause_data abm_pause_data; 3170 }; 3171 3172 /** 3173 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 3174 */ 3175 struct dmub_rb_cmd_abm_save_restore { 3176 /** 3177 * Command header. 3178 */ 3179 struct dmub_cmd_header header; 3180 3181 /** 3182 * OTG hw instance 3183 */ 3184 uint8_t otg_inst; 3185 3186 /** 3187 * Enable or disable ABM pause 3188 */ 3189 uint8_t freeze; 3190 3191 /** 3192 * Explicit padding to 4 byte boundary. 3193 */ 3194 uint8_t debug; 3195 3196 /** 3197 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3198 */ 3199 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3200 }; 3201 3202 /** 3203 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3204 */ 3205 struct dmub_cmd_query_feature_caps_data { 3206 /** 3207 * DMUB feature capabilities. 3208 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3209 */ 3210 struct dmub_feature_caps feature_caps; 3211 }; 3212 3213 /** 3214 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3215 */ 3216 struct dmub_rb_cmd_query_feature_caps { 3217 /** 3218 * Command header. 3219 */ 3220 struct dmub_cmd_header header; 3221 /** 3222 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3223 */ 3224 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 3225 }; 3226 3227 /** 3228 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3229 */ 3230 struct dmub_cmd_visual_confirm_color_data { 3231 /** 3232 * DMUB feature capabilities. 3233 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3234 */ 3235 struct dmub_visual_confirm_color visual_confirm_color; 3236 }; 3237 3238 /** 3239 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3240 */ 3241 struct dmub_rb_cmd_get_visual_confirm_color { 3242 /** 3243 * Command header. 3244 */ 3245 struct dmub_cmd_header header; 3246 /** 3247 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3248 */ 3249 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3250 }; 3251 3252 struct dmub_optc_state { 3253 uint32_t v_total_max; 3254 uint32_t v_total_min; 3255 uint32_t tg_inst; 3256 }; 3257 3258 struct dmub_rb_cmd_drr_update { 3259 struct dmub_cmd_header header; 3260 struct dmub_optc_state dmub_optc_state_req; 3261 }; 3262 3263 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 3264 uint32_t pix_clk_100hz; 3265 uint8_t max_ramp_step; 3266 uint8_t pipes; 3267 uint8_t min_refresh_in_hz; 3268 uint8_t pipe_count; 3269 uint8_t pipe_index[4]; 3270 }; 3271 3272 struct dmub_cmd_fw_assisted_mclk_switch_config { 3273 uint8_t fams_enabled; 3274 uint8_t visual_confirm_enabled; 3275 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 3276 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 3277 }; 3278 3279 struct dmub_rb_cmd_fw_assisted_mclk_switch { 3280 struct dmub_cmd_header header; 3281 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 3282 }; 3283 3284 /** 3285 * enum dmub_cmd_panel_cntl_type - Panel control command. 3286 */ 3287 enum dmub_cmd_panel_cntl_type { 3288 /** 3289 * Initializes embedded panel hardware blocks. 3290 */ 3291 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3292 /** 3293 * Queries backlight info for the embedded panel. 3294 */ 3295 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3296 }; 3297 3298 /** 3299 * struct dmub_cmd_panel_cntl_data - Panel control data. 3300 */ 3301 struct dmub_cmd_panel_cntl_data { 3302 uint32_t inst; /**< panel instance */ 3303 uint32_t current_backlight; /* in/out */ 3304 uint32_t bl_pwm_cntl; /* in/out */ 3305 uint32_t bl_pwm_period_cntl; /* in/out */ 3306 uint32_t bl_pwm_ref_div1; /* in/out */ 3307 uint8_t is_backlight_on : 1; /* in/out */ 3308 uint8_t is_powered_on : 1; /* in/out */ 3309 uint8_t padding[3]; 3310 uint32_t bl_pwm_ref_div2; /* in/out */ 3311 uint8_t reserved[4]; 3312 }; 3313 3314 /** 3315 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3316 */ 3317 struct dmub_rb_cmd_panel_cntl { 3318 struct dmub_cmd_header header; /**< header */ 3319 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3320 }; 3321 3322 /** 3323 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3324 */ 3325 struct dmub_cmd_lvtma_control_data { 3326 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3327 uint8_t bypass_panel_control_wait; 3328 uint8_t reserved_0[2]; /**< For future use */ 3329 uint8_t panel_inst; /**< LVTMA control instance */ 3330 uint8_t reserved_1[3]; /**< For future use */ 3331 }; 3332 3333 /** 3334 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3335 */ 3336 struct dmub_rb_cmd_lvtma_control { 3337 /** 3338 * Command header. 3339 */ 3340 struct dmub_cmd_header header; 3341 /** 3342 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3343 */ 3344 struct dmub_cmd_lvtma_control_data data; 3345 }; 3346 3347 /** 3348 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3349 */ 3350 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3351 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3352 uint8_t is_usb; /**< is phy is usb */ 3353 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3354 uint8_t is_dp4; /**< is dp in 4 lane */ 3355 }; 3356 3357 /** 3358 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3359 */ 3360 struct dmub_rb_cmd_transmitter_query_dp_alt { 3361 struct dmub_cmd_header header; /**< header */ 3362 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3363 }; 3364 3365 /** 3366 * Maximum number of bytes a chunk sent to DMUB for parsing 3367 */ 3368 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3369 3370 /** 3371 * Represent a chunk of CEA blocks sent to DMUB for parsing 3372 */ 3373 struct dmub_cmd_send_edid_cea { 3374 uint16_t offset; /**< offset into the CEA block */ 3375 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3376 uint16_t cea_total_length; /**< total length of the CEA block */ 3377 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3378 uint8_t pad[3]; /**< padding and for future expansion */ 3379 }; 3380 3381 /** 3382 * Result of VSDB parsing from CEA block 3383 */ 3384 struct dmub_cmd_edid_cea_amd_vsdb { 3385 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3386 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3387 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3388 uint16_t min_frame_rate; /**< Maximum frame rate */ 3389 uint16_t max_frame_rate; /**< Minimum frame rate */ 3390 }; 3391 3392 /** 3393 * Result of sending a CEA chunk 3394 */ 3395 struct dmub_cmd_edid_cea_ack { 3396 uint16_t offset; /**< offset of the chunk into the CEA block */ 3397 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3398 uint8_t pad; /**< padding and for future expansion */ 3399 }; 3400 3401 /** 3402 * Specify whether the result is an ACK/NACK or the parsing has finished 3403 */ 3404 enum dmub_cmd_edid_cea_reply_type { 3405 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3406 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3407 }; 3408 3409 /** 3410 * Definition of a DMUB_CMD__EDID_CEA command. 3411 */ 3412 struct dmub_rb_cmd_edid_cea { 3413 struct dmub_cmd_header header; /**< Command header */ 3414 union dmub_cmd_edid_cea_data { 3415 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3416 struct dmub_cmd_edid_cea_output { /**< output with results */ 3417 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3418 union { 3419 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3420 struct dmub_cmd_edid_cea_ack ack; 3421 }; 3422 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3423 } data; /**< Command data */ 3424 3425 }; 3426 3427 /** 3428 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3429 */ 3430 struct dmub_cmd_cable_id_input { 3431 uint8_t phy_inst; /**< phy inst for cable id data */ 3432 }; 3433 3434 /** 3435 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3436 */ 3437 struct dmub_cmd_cable_id_output { 3438 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3439 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3440 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3441 uint8_t RESERVED :2; /**< reserved means not defined */ 3442 }; 3443 3444 /** 3445 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3446 */ 3447 struct dmub_rb_cmd_get_usbc_cable_id { 3448 struct dmub_cmd_header header; /**< Command header */ 3449 /** 3450 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3451 */ 3452 union dmub_cmd_cable_id_data { 3453 struct dmub_cmd_cable_id_input input; /**< Input */ 3454 struct dmub_cmd_cable_id_output output; /**< Output */ 3455 uint8_t output_raw; /**< Raw data output */ 3456 } data; 3457 }; 3458 3459 /** 3460 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3461 */ 3462 enum dmub_cmd_secure_display_type { 3463 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3464 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3465 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3466 }; 3467 3468 /** 3469 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3470 */ 3471 struct dmub_rb_cmd_secure_display { 3472 struct dmub_cmd_header header; 3473 /** 3474 * Data passed from driver to dmub firmware. 3475 */ 3476 struct dmub_cmd_roi_info { 3477 uint16_t x_start; 3478 uint16_t x_end; 3479 uint16_t y_start; 3480 uint16_t y_end; 3481 uint8_t otg_id; 3482 uint8_t phy_id; 3483 } roi_info; 3484 }; 3485 3486 /** 3487 * union dmub_rb_cmd - DMUB inbox command. 3488 */ 3489 union dmub_rb_cmd { 3490 /** 3491 * Elements shared with all commands. 3492 */ 3493 struct dmub_rb_cmd_common cmd_common; 3494 /** 3495 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3496 */ 3497 struct dmub_rb_cmd_read_modify_write read_modify_write; 3498 /** 3499 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3500 */ 3501 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3502 /** 3503 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3504 */ 3505 struct dmub_rb_cmd_burst_write burst_write; 3506 /** 3507 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3508 */ 3509 struct dmub_rb_cmd_reg_wait reg_wait; 3510 /** 3511 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3512 */ 3513 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3514 /** 3515 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3516 */ 3517 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3518 /** 3519 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3520 */ 3521 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3522 /** 3523 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3524 */ 3525 struct dmub_rb_cmd_dpphy_init dpphy_init; 3526 /** 3527 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3528 */ 3529 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3530 /** 3531 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3532 */ 3533 struct dmub_rb_cmd_domain_control domain_control; 3534 /** 3535 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3536 */ 3537 struct dmub_rb_cmd_psr_set_version psr_set_version; 3538 /** 3539 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3540 */ 3541 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3542 /** 3543 * Definition of a DMUB_CMD__PSR_ENABLE command. 3544 */ 3545 struct dmub_rb_cmd_psr_enable psr_enable; 3546 /** 3547 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3548 */ 3549 struct dmub_rb_cmd_psr_set_level psr_set_level; 3550 /** 3551 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3552 */ 3553 struct dmub_rb_cmd_psr_force_static psr_force_static; 3554 /** 3555 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3556 */ 3557 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3558 /** 3559 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3560 */ 3561 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3562 /** 3563 * Definition of a DMUB_CMD__HW_LOCK command. 3564 * Command is used by driver and FW. 3565 */ 3566 struct dmub_rb_cmd_lock_hw lock_hw; 3567 /** 3568 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3569 */ 3570 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3571 /** 3572 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3573 */ 3574 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3575 /** 3576 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3577 */ 3578 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3579 /** 3580 * Definition of a DMUB_CMD__MALL command. 3581 */ 3582 struct dmub_rb_cmd_mall mall; 3583 /** 3584 * Definition of a DMUB_CMD__CAB command. 3585 */ 3586 struct dmub_rb_cmd_cab_for_ss cab; 3587 3588 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3589 3590 /** 3591 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3592 */ 3593 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3594 3595 /** 3596 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3597 */ 3598 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3599 3600 /** 3601 * Definition of DMUB_CMD__PANEL_CNTL commands. 3602 */ 3603 struct dmub_rb_cmd_panel_cntl panel_cntl; 3604 /** 3605 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3606 */ 3607 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3608 3609 /** 3610 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3611 */ 3612 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3613 3614 /** 3615 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3616 */ 3617 struct dmub_rb_cmd_abm_set_level abm_set_level; 3618 3619 /** 3620 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3621 */ 3622 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3623 3624 /** 3625 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3626 */ 3627 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3628 3629 /** 3630 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3631 */ 3632 struct dmub_rb_cmd_abm_init_config abm_init_config; 3633 3634 /** 3635 * Definition of a DMUB_CMD__ABM_PAUSE command. 3636 */ 3637 struct dmub_rb_cmd_abm_pause abm_pause; 3638 3639 /** 3640 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 3641 */ 3642 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 3643 3644 /** 3645 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3646 */ 3647 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3648 3649 /** 3650 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3651 */ 3652 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3653 3654 /** 3655 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3656 */ 3657 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3658 3659 /** 3660 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3661 */ 3662 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3663 struct dmub_rb_cmd_drr_update drr_update; 3664 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3665 3666 /** 3667 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3668 */ 3669 struct dmub_rb_cmd_lvtma_control lvtma_control; 3670 /** 3671 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3672 */ 3673 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3674 /** 3675 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3676 */ 3677 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3678 /** 3679 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3680 */ 3681 struct dmub_rb_cmd_set_config_access set_config_access; 3682 /** 3683 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3684 */ 3685 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3686 /** 3687 * Definition of a DMUB_CMD__EDID_CEA command. 3688 */ 3689 struct dmub_rb_cmd_edid_cea edid_cea; 3690 /** 3691 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3692 */ 3693 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3694 3695 /** 3696 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3697 */ 3698 struct dmub_rb_cmd_query_hpd_state query_hpd; 3699 /** 3700 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3701 */ 3702 struct dmub_rb_cmd_secure_display secure_display; 3703 3704 /** 3705 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3706 */ 3707 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3708 /** 3709 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 3710 */ 3711 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 3712 }; 3713 3714 /** 3715 * union dmub_rb_out_cmd - Outbox command 3716 */ 3717 union dmub_rb_out_cmd { 3718 /** 3719 * Parameters common to every command. 3720 */ 3721 struct dmub_rb_cmd_common cmd_common; 3722 /** 3723 * AUX reply command. 3724 */ 3725 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3726 /** 3727 * HPD notify command. 3728 */ 3729 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3730 /** 3731 * SET_CONFIG reply command. 3732 */ 3733 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3734 /** 3735 * DPIA notification command. 3736 */ 3737 struct dmub_rb_cmd_dpia_notification dpia_notification; 3738 }; 3739 #pragma pack(pop) 3740 3741 3742 //============================================================================== 3743 //</DMUB_CMD>=================================================================== 3744 //============================================================================== 3745 //< DMUB_RB>==================================================================== 3746 //============================================================================== 3747 3748 #if defined(__cplusplus) 3749 extern "C" { 3750 #endif 3751 3752 /** 3753 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3754 */ 3755 struct dmub_rb_init_params { 3756 void *ctx; /**< Caller provided context pointer */ 3757 void *base_address; /**< CPU base address for ring's data */ 3758 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3759 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3760 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3761 }; 3762 3763 /** 3764 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3765 */ 3766 struct dmub_rb { 3767 void *base_address; /**< CPU address for the ring's data */ 3768 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3769 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3770 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3771 3772 void *ctx; /**< Caller provided context pointer */ 3773 void *dmub; /**< Pointer to the DMUB interface */ 3774 }; 3775 3776 /** 3777 * @brief Checks if the ringbuffer is empty. 3778 * 3779 * @param rb DMUB Ringbuffer 3780 * @return true if empty 3781 * @return false otherwise 3782 */ 3783 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3784 { 3785 return (rb->wrpt == rb->rptr); 3786 } 3787 3788 /** 3789 * @brief Checks if the ringbuffer is full 3790 * 3791 * @param rb DMUB Ringbuffer 3792 * @return true if full 3793 * @return false otherwise 3794 */ 3795 static inline bool dmub_rb_full(struct dmub_rb *rb) 3796 { 3797 uint32_t data_count; 3798 3799 if (rb->wrpt >= rb->rptr) 3800 data_count = rb->wrpt - rb->rptr; 3801 else 3802 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3803 3804 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3805 } 3806 3807 /** 3808 * @brief Pushes a command into the ringbuffer 3809 * 3810 * @param rb DMUB ringbuffer 3811 * @param cmd The command to push 3812 * @return true if the ringbuffer was not full 3813 * @return false otherwise 3814 */ 3815 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3816 const union dmub_rb_cmd *cmd) 3817 { 3818 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3819 const uint64_t *src = (const uint64_t *)cmd; 3820 uint8_t i; 3821 3822 if (dmub_rb_full(rb)) 3823 return false; 3824 3825 // copying data 3826 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3827 *dst++ = *src++; 3828 3829 rb->wrpt += DMUB_RB_CMD_SIZE; 3830 3831 if (rb->wrpt >= rb->capacity) 3832 rb->wrpt %= rb->capacity; 3833 3834 return true; 3835 } 3836 3837 /** 3838 * @brief Pushes a command into the DMUB outbox ringbuffer 3839 * 3840 * @param rb DMUB outbox ringbuffer 3841 * @param cmd Outbox command 3842 * @return true if not full 3843 * @return false otherwise 3844 */ 3845 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3846 const union dmub_rb_out_cmd *cmd) 3847 { 3848 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3849 const uint8_t *src = (const uint8_t *)cmd; 3850 3851 if (dmub_rb_full(rb)) 3852 return false; 3853 3854 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3855 3856 rb->wrpt += DMUB_RB_CMD_SIZE; 3857 3858 if (rb->wrpt >= rb->capacity) 3859 rb->wrpt %= rb->capacity; 3860 3861 return true; 3862 } 3863 3864 /** 3865 * @brief Returns the next unprocessed command in the ringbuffer. 3866 * 3867 * @param rb DMUB ringbuffer 3868 * @param cmd The command to return 3869 * @return true if not empty 3870 * @return false otherwise 3871 */ 3872 static inline bool dmub_rb_front(struct dmub_rb *rb, 3873 union dmub_rb_cmd **cmd) 3874 { 3875 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3876 3877 if (dmub_rb_empty(rb)) 3878 return false; 3879 3880 *cmd = (union dmub_rb_cmd *)rb_cmd; 3881 3882 return true; 3883 } 3884 3885 /** 3886 * @brief Determines the next ringbuffer offset. 3887 * 3888 * @param rb DMUB inbox ringbuffer 3889 * @param num_cmds Number of commands 3890 * @param next_rptr The next offset in the ringbuffer 3891 */ 3892 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3893 uint32_t num_cmds, 3894 uint32_t *next_rptr) 3895 { 3896 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3897 3898 if (*next_rptr >= rb->capacity) 3899 *next_rptr %= rb->capacity; 3900 } 3901 3902 /** 3903 * @brief Returns a pointer to a command in the inbox. 3904 * 3905 * @param rb DMUB inbox ringbuffer 3906 * @param cmd The inbox command to return 3907 * @param rptr The ringbuffer offset 3908 * @return true if not empty 3909 * @return false otherwise 3910 */ 3911 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3912 union dmub_rb_cmd **cmd, 3913 uint32_t rptr) 3914 { 3915 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3916 3917 if (dmub_rb_empty(rb)) 3918 return false; 3919 3920 *cmd = (union dmub_rb_cmd *)rb_cmd; 3921 3922 return true; 3923 } 3924 3925 /** 3926 * @brief Returns the next unprocessed command in the outbox. 3927 * 3928 * @param rb DMUB outbox ringbuffer 3929 * @param cmd The outbox command to return 3930 * @return true if not empty 3931 * @return false otherwise 3932 */ 3933 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3934 union dmub_rb_out_cmd *cmd) 3935 { 3936 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3937 uint64_t *dst = (uint64_t *)cmd; 3938 uint8_t i; 3939 3940 if (dmub_rb_empty(rb)) 3941 return false; 3942 3943 // copying data 3944 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3945 *dst++ = *src++; 3946 3947 return true; 3948 } 3949 3950 /** 3951 * @brief Removes the front entry in the ringbuffer. 3952 * 3953 * @param rb DMUB ringbuffer 3954 * @return true if the command was removed 3955 * @return false if there were no commands 3956 */ 3957 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3958 { 3959 if (dmub_rb_empty(rb)) 3960 return false; 3961 3962 rb->rptr += DMUB_RB_CMD_SIZE; 3963 3964 if (rb->rptr >= rb->capacity) 3965 rb->rptr %= rb->capacity; 3966 3967 return true; 3968 } 3969 3970 /** 3971 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3972 * 3973 * Avoids a race condition where DMCUB accesses memory while 3974 * there are still writes in flight to framebuffer. 3975 * 3976 * @param rb DMUB ringbuffer 3977 */ 3978 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3979 { 3980 uint32_t rptr = rb->rptr; 3981 uint32_t wptr = rb->wrpt; 3982 3983 while (rptr != wptr) { 3984 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3985 uint8_t i; 3986 3987 /* Don't remove this. 3988 * The contents need to actually be read from the ring buffer 3989 * for this function to be effective. 3990 */ 3991 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3992 (void)READ_ONCE(*data++); 3993 3994 rptr += DMUB_RB_CMD_SIZE; 3995 if (rptr >= rb->capacity) 3996 rptr %= rb->capacity; 3997 } 3998 } 3999 4000 /** 4001 * @brief Initializes a DMCUB ringbuffer 4002 * 4003 * @param rb DMUB ringbuffer 4004 * @param init_params initial configuration for the ringbuffer 4005 */ 4006 static inline void dmub_rb_init(struct dmub_rb *rb, 4007 struct dmub_rb_init_params *init_params) 4008 { 4009 rb->base_address = init_params->base_address; 4010 rb->capacity = init_params->capacity; 4011 rb->rptr = init_params->read_ptr; 4012 rb->wrpt = init_params->write_ptr; 4013 } 4014 4015 /** 4016 * @brief Copies output data from in/out commands into the given command. 4017 * 4018 * @param rb DMUB ringbuffer 4019 * @param cmd Command to copy data into 4020 */ 4021 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 4022 union dmub_rb_cmd *cmd) 4023 { 4024 // Copy rb entry back into command 4025 uint8_t *rd_ptr = (rb->rptr == 0) ? 4026 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 4027 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 4028 4029 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 4030 } 4031 4032 #if defined(__cplusplus) 4033 } 4034 #endif 4035 4036 //============================================================================== 4037 //</DMUB_RB>==================================================================== 4038 //============================================================================== 4039 4040 #endif /* _DMUB_CMD_H_ */ 4041