1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Maximum number of streams on any ASIC. */ 99 #define DMUB_MAX_STREAMS 6 100 101 /* Maximum number of planes on any ASIC. */ 102 #define DMUB_MAX_PLANES 6 103 104 /* Trace buffer offset for entry */ 105 #define TRACE_BUFFER_ENTRY_OFFSET 16 106 107 /** 108 * Maximum number of dirty rects supported by FW. 109 */ 110 #define DMUB_MAX_DIRTY_RECTS 3 111 112 /** 113 * 114 * PSR control version legacy 115 */ 116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117 /** 118 * PSR control version with multi edp support 119 */ 120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121 122 123 /** 124 * ABM control version legacy 125 */ 126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127 128 /** 129 * ABM control version with multi edp support 130 */ 131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132 133 /** 134 * Physical framebuffer address location, 64-bit. 135 */ 136 #ifndef PHYSICAL_ADDRESS_LOC 137 #define PHYSICAL_ADDRESS_LOC union large_integer 138 #endif 139 140 /** 141 * OS/FW agnostic memcpy 142 */ 143 #ifndef dmub_memcpy 144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 145 #endif 146 147 /** 148 * OS/FW agnostic memset 149 */ 150 #ifndef dmub_memset 151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 152 #endif 153 154 #if defined(__cplusplus) 155 extern "C" { 156 #endif 157 158 /** 159 * OS/FW agnostic udelay 160 */ 161 #ifndef dmub_udelay 162 #define dmub_udelay(microseconds) udelay(microseconds) 163 #endif 164 165 /** 166 * union dmub_addr - DMUB physical/virtual 64-bit address. 167 */ 168 union dmub_addr { 169 struct { 170 uint32_t low_part; /**< Lower 32 bits */ 171 uint32_t high_part; /**< Upper 32 bits */ 172 } u; /*<< Low/high bit access */ 173 uint64_t quad_part; /*<< 64 bit address */ 174 }; 175 176 /** 177 * Dirty rect definition. 178 */ 179 struct dmub_rect { 180 /** 181 * Dirty rect x offset. 182 */ 183 uint32_t x; 184 185 /** 186 * Dirty rect y offset. 187 */ 188 uint32_t y; 189 190 /** 191 * Dirty rect width. 192 */ 193 uint32_t width; 194 195 /** 196 * Dirty rect height. 197 */ 198 uint32_t height; 199 }; 200 201 /** 202 * Flags that can be set by driver to change some PSR behaviour. 203 */ 204 union dmub_psr_debug_flags { 205 /** 206 * Debug flags. 207 */ 208 struct { 209 /** 210 * Enable visual confirm in FW. 211 */ 212 uint32_t visual_confirm : 1; 213 214 /** 215 * Force all selective updates to bw full frame updates. 216 */ 217 uint32_t force_full_frame_update : 1; 218 219 /** 220 * Use HW Lock Mgr object to do HW locking in FW. 221 */ 222 uint32_t use_hw_lock_mgr : 1; 223 224 /** 225 * Use TPS3 signal when restore main link. 226 */ 227 uint32_t force_wakeup_by_tps3 : 1; 228 229 /** 230 * Back to back flip, therefore cannot power down PHY 231 */ 232 uint32_t back_to_back_flip : 1; 233 234 } bitfields; 235 236 /** 237 * Union for debug flags. 238 */ 239 uint32_t u32All; 240 }; 241 242 /** 243 * DMUB visual confirm color 244 */ 245 struct dmub_feature_caps { 246 /** 247 * Max PSR version supported by FW. 248 */ 249 uint8_t psr; 250 uint8_t fw_assisted_mclk_switch; 251 uint8_t reserved[6]; 252 }; 253 254 struct dmub_visual_confirm_color { 255 /** 256 * Maximum 10 bits color value 257 */ 258 uint16_t color_r_cr; 259 uint16_t color_g_y; 260 uint16_t color_b_cb; 261 uint16_t panel_inst; 262 }; 263 264 #if defined(__cplusplus) 265 } 266 #endif 267 268 //============================================================================== 269 //</DMUB_TYPES>================================================================= 270 //============================================================================== 271 //< DMUB_META>================================================================== 272 //============================================================================== 273 #pragma pack(push, 1) 274 275 /* Magic value for identifying dmub_fw_meta_info */ 276 #define DMUB_FW_META_MAGIC 0x444D5542 277 278 /* Offset from the end of the file to the dmub_fw_meta_info */ 279 #define DMUB_FW_META_OFFSET 0x24 280 281 /** 282 * struct dmub_fw_meta_info - metadata associated with fw binary 283 * 284 * NOTE: This should be considered a stable API. Fields should 285 * not be repurposed or reordered. New fields should be 286 * added instead to extend the structure. 287 * 288 * @magic_value: magic value identifying DMUB firmware meta info 289 * @fw_region_size: size of the firmware state region 290 * @trace_buffer_size: size of the tracebuffer region 291 * @fw_version: the firmware version information 292 * @dal_fw: 1 if the firmware is DAL 293 */ 294 struct dmub_fw_meta_info { 295 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 296 uint32_t fw_region_size; /**< size of the firmware state region */ 297 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 298 uint32_t fw_version; /**< the firmware version information */ 299 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 300 uint8_t reserved[3]; /**< padding bits */ 301 }; 302 303 /** 304 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 305 */ 306 union dmub_fw_meta { 307 struct dmub_fw_meta_info info; /**< metadata info */ 308 uint8_t reserved[64]; /**< padding bits */ 309 }; 310 311 #pragma pack(pop) 312 313 //============================================================================== 314 //< DMUB Trace Buffer>================================================================ 315 //============================================================================== 316 /** 317 * dmub_trace_code_t - firmware trace code, 32-bits 318 */ 319 typedef uint32_t dmub_trace_code_t; 320 321 /** 322 * struct dmcub_trace_buf_entry - Firmware trace entry 323 */ 324 struct dmcub_trace_buf_entry { 325 dmub_trace_code_t trace_code; /**< trace code for the event */ 326 uint32_t tick_count; /**< the tick count at time of trace */ 327 uint32_t param0; /**< trace defined parameter 0 */ 328 uint32_t param1; /**< trace defined parameter 1 */ 329 }; 330 331 //============================================================================== 332 //< DMUB_STATUS>================================================================ 333 //============================================================================== 334 335 /** 336 * DMCUB scratch registers can be used to determine firmware status. 337 * Current scratch register usage is as follows: 338 * 339 * SCRATCH0: FW Boot Status register 340 * SCRATCH5: LVTMA Status Register 341 * SCRATCH15: FW Boot Options register 342 */ 343 344 /** 345 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 346 */ 347 union dmub_fw_boot_status { 348 struct { 349 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 350 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 351 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 352 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 353 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 354 uint32_t reserved : 1; 355 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 356 357 } bits; /**< status bits */ 358 uint32_t all; /**< 32-bit access to status bits */ 359 }; 360 361 /** 362 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 363 */ 364 enum dmub_fw_boot_status_bit { 365 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 366 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 367 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 368 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 369 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 370 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 371 }; 372 373 /* Register bit definition for SCRATCH5 */ 374 union dmub_lvtma_status { 375 struct { 376 uint32_t psp_ok : 1; 377 uint32_t edp_on : 1; 378 uint32_t reserved : 30; 379 } bits; 380 uint32_t all; 381 }; 382 383 enum dmub_lvtma_status_bit { 384 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 385 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 386 }; 387 388 /** 389 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 390 */ 391 union dmub_fw_boot_options { 392 struct { 393 uint32_t pemu_env : 1; /**< 1 if PEMU */ 394 uint32_t fpga_env : 1; /**< 1 if FPGA */ 395 uint32_t optimized_init : 1; /**< 1 if optimized init */ 396 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 397 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 398 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 399 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 400 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 401 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 402 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 403 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 404 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 405 uint32_t power_optimization: 1; 406 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 407 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 408 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 409 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 410 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 411 412 uint32_t reserved : 15; /**< reserved */ 413 } bits; /**< boot bits */ 414 uint32_t all; /**< 32-bit access to bits */ 415 }; 416 417 enum dmub_fw_boot_options_bit { 418 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 419 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 420 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 421 }; 422 423 //============================================================================== 424 //</DMUB_STATUS>================================================================ 425 //============================================================================== 426 //< DMUB_VBIOS>================================================================= 427 //============================================================================== 428 429 /* 430 * enum dmub_cmd_vbios_type - VBIOS commands. 431 * 432 * Command IDs should be treated as stable ABI. 433 * Do not reuse or modify IDs. 434 */ 435 enum dmub_cmd_vbios_type { 436 /** 437 * Configures the DIG encoder. 438 */ 439 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 440 /** 441 * Controls the PHY. 442 */ 443 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 444 /** 445 * Sets the pixel clock/symbol clock. 446 */ 447 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 448 /** 449 * Enables or disables power gating. 450 */ 451 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 452 /** 453 * Controls embedded panels. 454 */ 455 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 456 /** 457 * Query DP alt status on a transmitter. 458 */ 459 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 460 }; 461 462 //============================================================================== 463 //</DMUB_VBIOS>================================================================= 464 //============================================================================== 465 //< DMUB_GPINT>================================================================= 466 //============================================================================== 467 468 /** 469 * The shifts and masks below may alternatively be used to format and read 470 * the command register bits. 471 */ 472 473 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 474 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 475 476 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 477 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 478 479 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 480 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 481 482 /** 483 * Command responses. 484 */ 485 486 /** 487 * Return response for DMUB_GPINT__STOP_FW command. 488 */ 489 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 490 491 /** 492 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 493 */ 494 union dmub_gpint_data_register { 495 struct { 496 uint32_t param : 16; /**< 16-bit parameter */ 497 uint32_t command_code : 12; /**< GPINT command */ 498 uint32_t status : 4; /**< Command status bit */ 499 } bits; /**< GPINT bit access */ 500 uint32_t all; /**< GPINT 32-bit access */ 501 }; 502 503 /* 504 * enum dmub_gpint_command - GPINT command to DMCUB FW 505 * 506 * Command IDs should be treated as stable ABI. 507 * Do not reuse or modify IDs. 508 */ 509 enum dmub_gpint_command { 510 /** 511 * Invalid command, ignored. 512 */ 513 DMUB_GPINT__INVALID_COMMAND = 0, 514 /** 515 * DESC: Queries the firmware version. 516 * RETURN: Firmware version. 517 */ 518 DMUB_GPINT__GET_FW_VERSION = 1, 519 /** 520 * DESC: Halts the firmware. 521 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 522 */ 523 DMUB_GPINT__STOP_FW = 2, 524 /** 525 * DESC: Get PSR state from FW. 526 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 527 */ 528 DMUB_GPINT__GET_PSR_STATE = 7, 529 /** 530 * DESC: Notifies DMCUB of the currently active streams. 531 * ARGS: Stream mask, 1 bit per active stream index. 532 */ 533 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 534 /** 535 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 536 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 537 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 538 * RETURN: PSR residency in milli-percent. 539 */ 540 DMUB_GPINT__PSR_RESIDENCY = 9, 541 542 /** 543 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 544 */ 545 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 546 }; 547 548 /** 549 * INBOX0 generic command definition 550 */ 551 union dmub_inbox0_cmd_common { 552 struct { 553 uint32_t command_code: 8; /**< INBOX0 command code */ 554 uint32_t param: 24; /**< 24-bit parameter */ 555 } bits; 556 uint32_t all; 557 }; 558 559 /** 560 * INBOX0 hw_lock command definition 561 */ 562 union dmub_inbox0_cmd_lock_hw { 563 struct { 564 uint32_t command_code: 8; 565 566 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 567 uint32_t hw_lock_client: 2; 568 569 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 570 uint32_t otg_inst: 3; 571 uint32_t opp_inst: 3; 572 uint32_t dig_inst: 3; 573 574 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 575 uint32_t lock_pipe: 1; 576 uint32_t lock_cursor: 1; 577 uint32_t lock_dig: 1; 578 uint32_t triple_buffer_lock: 1; 579 580 uint32_t lock: 1; /**< Lock */ 581 uint32_t should_release: 1; /**< Release */ 582 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 583 } bits; 584 uint32_t all; 585 }; 586 587 union dmub_inbox0_data_register { 588 union dmub_inbox0_cmd_common inbox0_cmd_common; 589 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 590 }; 591 592 enum dmub_inbox0_command { 593 /** 594 * DESC: Invalid command, ignored. 595 */ 596 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 597 /** 598 * DESC: Notification to acquire/release HW lock 599 * ARGS: 600 */ 601 DMUB_INBOX0_CMD__HW_LOCK = 1, 602 }; 603 //============================================================================== 604 //</DMUB_GPINT>================================================================= 605 //============================================================================== 606 //< DMUB_CMD>=================================================================== 607 //============================================================================== 608 609 /** 610 * Size in bytes of each DMUB command. 611 */ 612 #define DMUB_RB_CMD_SIZE 64 613 614 /** 615 * Maximum number of items in the DMUB ringbuffer. 616 */ 617 #define DMUB_RB_MAX_ENTRY 128 618 619 /** 620 * Ringbuffer size in bytes. 621 */ 622 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 623 624 /** 625 * REG_SET mask for reg offload. 626 */ 627 #define REG_SET_MASK 0xFFFF 628 629 /* 630 * enum dmub_cmd_type - DMUB inbox command. 631 * 632 * Command IDs should be treated as stable ABI. 633 * Do not reuse or modify IDs. 634 */ 635 enum dmub_cmd_type { 636 /** 637 * Invalid command. 638 */ 639 DMUB_CMD__NULL = 0, 640 /** 641 * Read modify write register sequence offload. 642 */ 643 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 644 /** 645 * Field update register sequence offload. 646 */ 647 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 648 /** 649 * Burst write sequence offload. 650 */ 651 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 652 /** 653 * Reg wait sequence offload. 654 */ 655 DMUB_CMD__REG_REG_WAIT = 4, 656 /** 657 * Workaround to avoid HUBP underflow during NV12 playback. 658 */ 659 DMUB_CMD__PLAT_54186_WA = 5, 660 /** 661 * Command type used to query FW feature caps. 662 */ 663 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 664 /** 665 * Command type used to get visual confirm color. 666 */ 667 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 668 /** 669 * Command type used for all PSR commands. 670 */ 671 DMUB_CMD__PSR = 64, 672 /** 673 * Command type used for all MALL commands. 674 */ 675 DMUB_CMD__MALL = 65, 676 /** 677 * Command type used for all ABM commands. 678 */ 679 DMUB_CMD__ABM = 66, 680 /** 681 * Command type used to update dirty rects in FW. 682 */ 683 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 684 /** 685 * Command type used to update cursor info in FW. 686 */ 687 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 688 /** 689 * Command type used for HW locking in FW. 690 */ 691 DMUB_CMD__HW_LOCK = 69, 692 /** 693 * Command type used to access DP AUX. 694 */ 695 DMUB_CMD__DP_AUX_ACCESS = 70, 696 /** 697 * Command type used for OUTBOX1 notification enable 698 */ 699 DMUB_CMD__OUTBOX1_ENABLE = 71, 700 701 /** 702 * Command type used for all idle optimization commands. 703 */ 704 DMUB_CMD__IDLE_OPT = 72, 705 /** 706 * Command type used for all clock manager commands. 707 */ 708 DMUB_CMD__CLK_MGR = 73, 709 /** 710 * Command type used for all panel control commands. 711 */ 712 DMUB_CMD__PANEL_CNTL = 74, 713 /** 714 * Command type used for <TODO:description> 715 */ 716 DMUB_CMD__CAB_FOR_SS = 75, 717 718 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 719 720 /** 721 * Command type used for interfacing with DPIA. 722 */ 723 DMUB_CMD__DPIA = 77, 724 /** 725 * Command type used for EDID CEA parsing 726 */ 727 DMUB_CMD__EDID_CEA = 79, 728 /** 729 * Command type used for getting usbc cable ID 730 */ 731 DMUB_CMD_GET_USBC_CABLE_ID = 81, 732 /** 733 * Command type used to query HPD state. 734 */ 735 DMUB_CMD__QUERY_HPD_STATE = 82, 736 /** 737 * Command type used for all VBIOS interface commands. 738 */ 739 740 /** 741 * Command type used for all SECURE_DISPLAY commands. 742 */ 743 DMUB_CMD__SECURE_DISPLAY = 85, 744 745 /** 746 * Command type used to set DPIA HPD interrupt state 747 */ 748 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 749 750 DMUB_CMD__VBIOS = 128, 751 }; 752 753 /** 754 * enum dmub_out_cmd_type - DMUB outbox commands. 755 */ 756 enum dmub_out_cmd_type { 757 /** 758 * Invalid outbox command, ignored. 759 */ 760 DMUB_OUT_CMD__NULL = 0, 761 /** 762 * Command type used for DP AUX Reply data notification 763 */ 764 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 765 /** 766 * Command type used for DP HPD event notification 767 */ 768 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 769 /** 770 * Command type used for SET_CONFIG Reply notification 771 */ 772 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 773 /** 774 * Command type used for USB4 DPIA notification 775 */ 776 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 777 }; 778 779 /* DMUB_CMD__DPIA command sub-types. */ 780 enum dmub_cmd_dpia_type { 781 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 782 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 783 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 784 }; 785 786 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 787 enum dmub_cmd_dpia_notification_type { 788 DPIA_NOTIFY__BW_ALLOCATION = 0, 789 }; 790 791 #pragma pack(push, 1) 792 793 /** 794 * struct dmub_cmd_header - Common command header fields. 795 */ 796 struct dmub_cmd_header { 797 unsigned int type : 8; /**< command type */ 798 unsigned int sub_type : 8; /**< command sub type */ 799 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 800 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 801 unsigned int reserved0 : 6; /**< reserved bits */ 802 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 803 unsigned int reserved1 : 2; /**< reserved bits */ 804 }; 805 806 /* 807 * struct dmub_cmd_read_modify_write_sequence - Read modify write 808 * 809 * 60 payload bytes can hold up to 5 sets of read modify writes, 810 * each take 3 dwords. 811 * 812 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 813 * 814 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 815 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 816 */ 817 struct dmub_cmd_read_modify_write_sequence { 818 uint32_t addr; /**< register address */ 819 uint32_t modify_mask; /**< modify mask */ 820 uint32_t modify_value; /**< modify value */ 821 }; 822 823 /** 824 * Maximum number of ops in read modify write sequence. 825 */ 826 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 827 828 /** 829 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 830 */ 831 struct dmub_rb_cmd_read_modify_write { 832 struct dmub_cmd_header header; /**< command header */ 833 /** 834 * Read modify write sequence. 835 */ 836 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 837 }; 838 839 /* 840 * Update a register with specified masks and values sequeunce 841 * 842 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 843 * 844 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 845 * 846 * 847 * USE CASE: 848 * 1. auto-increment register where additional read would update pointer and produce wrong result 849 * 2. toggle a bit without read in the middle 850 */ 851 852 struct dmub_cmd_reg_field_update_sequence { 853 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 854 uint32_t modify_value; /**< value to update with */ 855 }; 856 857 /** 858 * Maximum number of ops in field update sequence. 859 */ 860 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 861 862 /** 863 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 864 */ 865 struct dmub_rb_cmd_reg_field_update_sequence { 866 struct dmub_cmd_header header; /**< command header */ 867 uint32_t addr; /**< register address */ 868 /** 869 * Field update sequence. 870 */ 871 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 872 }; 873 874 875 /** 876 * Maximum number of burst write values. 877 */ 878 #define DMUB_BURST_WRITE_VALUES__MAX 14 879 880 /* 881 * struct dmub_rb_cmd_burst_write - Burst write 882 * 883 * support use case such as writing out LUTs. 884 * 885 * 60 payload bytes can hold up to 14 values to write to given address 886 * 887 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 888 */ 889 struct dmub_rb_cmd_burst_write { 890 struct dmub_cmd_header header; /**< command header */ 891 uint32_t addr; /**< register start address */ 892 /** 893 * Burst write register values. 894 */ 895 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 896 }; 897 898 /** 899 * struct dmub_rb_cmd_common - Common command header 900 */ 901 struct dmub_rb_cmd_common { 902 struct dmub_cmd_header header; /**< command header */ 903 /** 904 * Padding to RB_CMD_SIZE 905 */ 906 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 907 }; 908 909 /** 910 * struct dmub_cmd_reg_wait_data - Register wait data 911 */ 912 struct dmub_cmd_reg_wait_data { 913 uint32_t addr; /**< Register address */ 914 uint32_t mask; /**< Mask for register bits */ 915 uint32_t condition_field_value; /**< Value to wait for */ 916 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 917 }; 918 919 /** 920 * struct dmub_rb_cmd_reg_wait - Register wait command 921 */ 922 struct dmub_rb_cmd_reg_wait { 923 struct dmub_cmd_header header; /**< Command header */ 924 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 925 }; 926 927 /** 928 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 929 * 930 * Reprograms surface parameters to avoid underflow. 931 */ 932 struct dmub_cmd_PLAT_54186_wa { 933 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 934 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 935 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 936 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 937 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 938 struct { 939 uint8_t hubp_inst : 4; /**< HUBP instance */ 940 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 941 uint8_t immediate :1; /**< Immediate flip */ 942 uint8_t vmid : 4; /**< VMID */ 943 uint8_t grph_stereo : 1; /**< 1 if stereo */ 944 uint32_t reserved : 21; /**< Reserved */ 945 } flip_params; /**< Pageflip parameters */ 946 uint32_t reserved[9]; /**< Reserved bits */ 947 }; 948 949 /** 950 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 951 */ 952 struct dmub_rb_cmd_PLAT_54186_wa { 953 struct dmub_cmd_header header; /**< Command header */ 954 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 955 }; 956 957 /** 958 * struct dmub_rb_cmd_mall - MALL command data. 959 */ 960 struct dmub_rb_cmd_mall { 961 struct dmub_cmd_header header; /**< Common command header */ 962 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 963 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 964 uint32_t tmr_delay; /**< Timer delay */ 965 uint32_t tmr_scale; /**< Timer scale */ 966 uint16_t cursor_width; /**< Cursor width in pixels */ 967 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 968 uint16_t cursor_height; /**< Cursor height in pixels */ 969 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 970 uint8_t debug_bits; /**< Debug bits */ 971 972 uint8_t reserved1; /**< Reserved bits */ 973 uint8_t reserved2; /**< Reserved bits */ 974 }; 975 976 /** 977 * enum dmub_cmd_cab_type - TODO: 978 */ 979 enum dmub_cmd_cab_type { 980 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 981 DMUB_CMD__CAB_NO_DCN_REQ = 1, 982 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 983 }; 984 985 /** 986 * struct dmub_rb_cmd_cab_for_ss - TODO: 987 */ 988 struct dmub_rb_cmd_cab_for_ss { 989 struct dmub_cmd_header header; 990 uint8_t cab_alloc_ways; /* total number of ways */ 991 uint8_t debug_bits; /* debug bits */ 992 }; 993 994 enum mclk_switch_mode { 995 NONE = 0, 996 FPO = 1, 997 SUBVP = 2, 998 VBLANK = 3, 999 }; 1000 1001 /* Per pipe struct which stores the MCLK switch mode 1002 * data to be sent to DMUB. 1003 * Named "v2" for now -- once FPO and SUBVP are fully merged 1004 * the type name can be updated 1005 */ 1006 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1007 union { 1008 struct { 1009 uint32_t pix_clk_100hz; 1010 uint16_t main_vblank_start; 1011 uint16_t main_vblank_end; 1012 uint16_t mall_region_lines; 1013 uint16_t prefetch_lines; 1014 uint16_t prefetch_to_mall_start_lines; 1015 uint16_t processing_delay_lines; 1016 uint16_t htotal; // required to calculate line time for multi-display cases 1017 uint16_t vtotal; 1018 uint8_t main_pipe_index; 1019 uint8_t phantom_pipe_index; 1020 /* Since the microschedule is calculated in terms of OTG lines, 1021 * include any scaling factors to make sure when we get accurate 1022 * conversion when programming MALL_START_LINE (which is in terms 1023 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1024 * is 1/2 (numerator = 1, denominator = 2). 1025 */ 1026 uint8_t scale_factor_numerator; 1027 uint8_t scale_factor_denominator; 1028 uint8_t is_drr; 1029 uint8_t main_split_pipe_index; 1030 uint8_t phantom_split_pipe_index; 1031 } subvp_data; 1032 1033 struct { 1034 uint32_t pix_clk_100hz; 1035 uint16_t vblank_start; 1036 uint16_t vblank_end; 1037 uint16_t vstartup_start; 1038 uint16_t vtotal; 1039 uint16_t htotal; 1040 uint8_t vblank_pipe_index; 1041 uint8_t padding[1]; 1042 struct { 1043 uint8_t drr_in_use; 1044 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1045 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1046 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1047 uint8_t use_ramping; // Use ramping or not 1048 uint8_t drr_vblank_start_margin; 1049 } drr_info; // DRR considered as part of SubVP + VBLANK case 1050 } vblank_data; 1051 } pipe_config; 1052 1053 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1054 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1055 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1056 */ 1057 uint8_t mode; // enum mclk_switch_mode 1058 }; 1059 1060 /** 1061 * Config data for Sub-VP and FPO 1062 * Named "v2" for now -- once FPO and SUBVP are fully merged 1063 * the type name can be updated 1064 */ 1065 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1066 uint16_t watermark_a_cache; 1067 uint8_t vertical_int_margin_us; 1068 uint8_t pstate_allow_width_us; 1069 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1070 }; 1071 1072 /** 1073 * DMUB rb command definition for Sub-VP and FPO 1074 * Named "v2" for now -- once FPO and SUBVP are fully merged 1075 * the type name can be updated 1076 */ 1077 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1078 struct dmub_cmd_header header; 1079 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1080 }; 1081 1082 /** 1083 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1084 */ 1085 enum dmub_cmd_idle_opt_type { 1086 /** 1087 * DCN hardware restore. 1088 */ 1089 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1090 1091 /** 1092 * DCN hardware save. 1093 */ 1094 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1095 }; 1096 1097 /** 1098 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1099 */ 1100 struct dmub_rb_cmd_idle_opt_dcn_restore { 1101 struct dmub_cmd_header header; /**< header */ 1102 }; 1103 1104 /** 1105 * struct dmub_clocks - Clock update notification. 1106 */ 1107 struct dmub_clocks { 1108 uint32_t dispclk_khz; /**< dispclk kHz */ 1109 uint32_t dppclk_khz; /**< dppclk kHz */ 1110 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1111 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1112 }; 1113 1114 /** 1115 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1116 */ 1117 enum dmub_cmd_clk_mgr_type { 1118 /** 1119 * Notify DMCUB of clock update. 1120 */ 1121 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1122 }; 1123 1124 /** 1125 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1126 */ 1127 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1128 struct dmub_cmd_header header; /**< header */ 1129 struct dmub_clocks clocks; /**< clock data */ 1130 }; 1131 1132 /** 1133 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1134 */ 1135 struct dmub_cmd_digx_encoder_control_data { 1136 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1137 }; 1138 1139 /** 1140 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1141 */ 1142 struct dmub_rb_cmd_digx_encoder_control { 1143 struct dmub_cmd_header header; /**< header */ 1144 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1145 }; 1146 1147 /** 1148 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1149 */ 1150 struct dmub_cmd_set_pixel_clock_data { 1151 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1152 }; 1153 1154 /** 1155 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1156 */ 1157 struct dmub_rb_cmd_set_pixel_clock { 1158 struct dmub_cmd_header header; /**< header */ 1159 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1160 }; 1161 1162 /** 1163 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1164 */ 1165 struct dmub_cmd_enable_disp_power_gating_data { 1166 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1167 }; 1168 1169 /** 1170 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1171 */ 1172 struct dmub_rb_cmd_enable_disp_power_gating { 1173 struct dmub_cmd_header header; /**< header */ 1174 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1175 }; 1176 1177 /** 1178 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1179 */ 1180 struct dmub_dig_transmitter_control_data_v1_7 { 1181 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1182 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1183 union { 1184 uint8_t digmode; /**< enum atom_encode_mode_def */ 1185 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1186 } mode_laneset; 1187 uint8_t lanenum; /**< Number of lanes */ 1188 union { 1189 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1190 } symclk_units; 1191 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1192 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1193 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1194 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1195 uint8_t reserved1; /**< For future use */ 1196 uint8_t reserved2[3]; /**< For future use */ 1197 uint32_t reserved3[11]; /**< For future use */ 1198 }; 1199 1200 /** 1201 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1202 */ 1203 union dmub_cmd_dig1_transmitter_control_data { 1204 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1205 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1206 }; 1207 1208 /** 1209 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1210 */ 1211 struct dmub_rb_cmd_dig1_transmitter_control { 1212 struct dmub_cmd_header header; /**< header */ 1213 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1214 }; 1215 1216 /** 1217 * DPIA tunnel command parameters. 1218 */ 1219 struct dmub_cmd_dig_dpia_control_data { 1220 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1221 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1222 union { 1223 uint8_t digmode; /** enum atom_encode_mode_def */ 1224 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1225 } mode_laneset; 1226 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1227 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1228 uint8_t hpdsel; /** =0: HPD is not assigned */ 1229 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1230 uint8_t dpia_id; /** Index of DPIA */ 1231 uint8_t fec_rdy : 1; 1232 uint8_t reserved : 7; 1233 uint32_t reserved1; 1234 }; 1235 1236 /** 1237 * DMUB command for DPIA tunnel control. 1238 */ 1239 struct dmub_rb_cmd_dig1_dpia_control { 1240 struct dmub_cmd_header header; 1241 struct dmub_cmd_dig_dpia_control_data dpia_control; 1242 }; 1243 1244 /** 1245 * SET_CONFIG Command Payload 1246 */ 1247 struct set_config_cmd_payload { 1248 uint8_t msg_type; /* set config message type */ 1249 uint8_t msg_data; /* set config message data */ 1250 }; 1251 1252 /** 1253 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1254 */ 1255 struct dmub_cmd_set_config_control_data { 1256 struct set_config_cmd_payload cmd_pkt; 1257 uint8_t instance; /* DPIA instance */ 1258 uint8_t immed_status; /* Immediate status returned in case of error */ 1259 }; 1260 1261 /** 1262 * DMUB command structure for SET_CONFIG command. 1263 */ 1264 struct dmub_rb_cmd_set_config_access { 1265 struct dmub_cmd_header header; /* header */ 1266 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1267 }; 1268 1269 /** 1270 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1271 */ 1272 struct dmub_cmd_mst_alloc_slots_control_data { 1273 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1274 uint8_t instance; /* DPIA instance */ 1275 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1276 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1277 }; 1278 1279 /** 1280 * DMUB command structure for SET_ command. 1281 */ 1282 struct dmub_rb_cmd_set_mst_alloc_slots { 1283 struct dmub_cmd_header header; /* header */ 1284 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1285 }; 1286 1287 /** 1288 * DMUB command structure for DPIA HPD int enable control. 1289 */ 1290 struct dmub_rb_cmd_dpia_hpd_int_enable { 1291 struct dmub_cmd_header header; /* header */ 1292 uint32_t enable; /* dpia hpd interrupt enable */ 1293 }; 1294 1295 /** 1296 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1297 */ 1298 struct dmub_rb_cmd_dpphy_init { 1299 struct dmub_cmd_header header; /**< header */ 1300 uint8_t reserved[60]; /**< reserved bits */ 1301 }; 1302 1303 /** 1304 * enum dp_aux_request_action - DP AUX request command listing. 1305 * 1306 * 4 AUX request command bits are shifted to high nibble. 1307 */ 1308 enum dp_aux_request_action { 1309 /** I2C-over-AUX write request */ 1310 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1311 /** I2C-over-AUX read request */ 1312 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1313 /** I2C-over-AUX write status request */ 1314 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1315 /** I2C-over-AUX write request with MOT=1 */ 1316 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1317 /** I2C-over-AUX read request with MOT=1 */ 1318 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1319 /** I2C-over-AUX write status request with MOT=1 */ 1320 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1321 /** Native AUX write request */ 1322 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1323 /** Native AUX read request */ 1324 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1325 }; 1326 1327 /** 1328 * enum aux_return_code_type - DP AUX process return code listing. 1329 */ 1330 enum aux_return_code_type { 1331 /** AUX process succeeded */ 1332 AUX_RET_SUCCESS = 0, 1333 /** AUX process failed with unknown reason */ 1334 AUX_RET_ERROR_UNKNOWN, 1335 /** AUX process completed with invalid reply */ 1336 AUX_RET_ERROR_INVALID_REPLY, 1337 /** AUX process timed out */ 1338 AUX_RET_ERROR_TIMEOUT, 1339 /** HPD was low during AUX process */ 1340 AUX_RET_ERROR_HPD_DISCON, 1341 /** Failed to acquire AUX engine */ 1342 AUX_RET_ERROR_ENGINE_ACQUIRE, 1343 /** AUX request not supported */ 1344 AUX_RET_ERROR_INVALID_OPERATION, 1345 /** AUX process not available */ 1346 AUX_RET_ERROR_PROTOCOL_ERROR, 1347 }; 1348 1349 /** 1350 * enum aux_channel_type - DP AUX channel type listing. 1351 */ 1352 enum aux_channel_type { 1353 /** AUX thru Legacy DP AUX */ 1354 AUX_CHANNEL_LEGACY_DDC, 1355 /** AUX thru DPIA DP tunneling */ 1356 AUX_CHANNEL_DPIA 1357 }; 1358 1359 /** 1360 * struct aux_transaction_parameters - DP AUX request transaction data 1361 */ 1362 struct aux_transaction_parameters { 1363 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1364 uint8_t action; /**< enum dp_aux_request_action */ 1365 uint8_t length; /**< DP AUX request data length */ 1366 uint8_t reserved; /**< For future use */ 1367 uint32_t address; /**< DP AUX address */ 1368 uint8_t data[16]; /**< DP AUX write data */ 1369 }; 1370 1371 /** 1372 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1373 */ 1374 struct dmub_cmd_dp_aux_control_data { 1375 uint8_t instance; /**< AUX instance or DPIA instance */ 1376 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1377 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1378 uint8_t reserved0; /**< For future use */ 1379 uint16_t timeout; /**< timeout time in us */ 1380 uint16_t reserved1; /**< For future use */ 1381 enum aux_channel_type type; /**< enum aux_channel_type */ 1382 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1383 }; 1384 1385 /** 1386 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1387 */ 1388 struct dmub_rb_cmd_dp_aux_access { 1389 /** 1390 * Command header. 1391 */ 1392 struct dmub_cmd_header header; 1393 /** 1394 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1395 */ 1396 struct dmub_cmd_dp_aux_control_data aux_control; 1397 }; 1398 1399 /** 1400 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1401 */ 1402 struct dmub_rb_cmd_outbox1_enable { 1403 /** 1404 * Command header. 1405 */ 1406 struct dmub_cmd_header header; 1407 /** 1408 * enable: 0x0 -> disable outbox1 notification (default value) 1409 * 0x1 -> enable outbox1 notification 1410 */ 1411 uint32_t enable; 1412 }; 1413 1414 /* DP AUX Reply command - OutBox Cmd */ 1415 /** 1416 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1417 */ 1418 struct aux_reply_data { 1419 /** 1420 * Aux cmd 1421 */ 1422 uint8_t command; 1423 /** 1424 * Aux reply data length (max: 16 bytes) 1425 */ 1426 uint8_t length; 1427 /** 1428 * Alignment only 1429 */ 1430 uint8_t pad[2]; 1431 /** 1432 * Aux reply data 1433 */ 1434 uint8_t data[16]; 1435 }; 1436 1437 /** 1438 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1439 */ 1440 struct aux_reply_control_data { 1441 /** 1442 * Reserved for future use 1443 */ 1444 uint32_t handle; 1445 /** 1446 * Aux Instance 1447 */ 1448 uint8_t instance; 1449 /** 1450 * Aux transaction result: definition in enum aux_return_code_type 1451 */ 1452 uint8_t result; 1453 /** 1454 * Alignment only 1455 */ 1456 uint16_t pad; 1457 }; 1458 1459 /** 1460 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1461 */ 1462 struct dmub_rb_cmd_dp_aux_reply { 1463 /** 1464 * Command header. 1465 */ 1466 struct dmub_cmd_header header; 1467 /** 1468 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1469 */ 1470 struct aux_reply_control_data control; 1471 /** 1472 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1473 */ 1474 struct aux_reply_data reply_data; 1475 }; 1476 1477 /* DP HPD Notify command - OutBox Cmd */ 1478 /** 1479 * DP HPD Type 1480 */ 1481 enum dp_hpd_type { 1482 /** 1483 * Normal DP HPD 1484 */ 1485 DP_HPD = 0, 1486 /** 1487 * DP HPD short pulse 1488 */ 1489 DP_IRQ 1490 }; 1491 1492 /** 1493 * DP HPD Status 1494 */ 1495 enum dp_hpd_status { 1496 /** 1497 * DP_HPD status low 1498 */ 1499 DP_HPD_UNPLUG = 0, 1500 /** 1501 * DP_HPD status high 1502 */ 1503 DP_HPD_PLUG 1504 }; 1505 1506 /** 1507 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1508 */ 1509 struct dp_hpd_data { 1510 /** 1511 * DP HPD instance 1512 */ 1513 uint8_t instance; 1514 /** 1515 * HPD type 1516 */ 1517 uint8_t hpd_type; 1518 /** 1519 * HPD status: only for type: DP_HPD to indicate status 1520 */ 1521 uint8_t hpd_status; 1522 /** 1523 * Alignment only 1524 */ 1525 uint8_t pad; 1526 }; 1527 1528 /** 1529 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1530 */ 1531 struct dmub_rb_cmd_dp_hpd_notify { 1532 /** 1533 * Command header. 1534 */ 1535 struct dmub_cmd_header header; 1536 /** 1537 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1538 */ 1539 struct dp_hpd_data hpd_data; 1540 }; 1541 1542 /** 1543 * Definition of a SET_CONFIG reply from DPOA. 1544 */ 1545 enum set_config_status { 1546 SET_CONFIG_PENDING = 0, 1547 SET_CONFIG_ACK_RECEIVED, 1548 SET_CONFIG_RX_TIMEOUT, 1549 SET_CONFIG_UNKNOWN_ERROR, 1550 }; 1551 1552 /** 1553 * Definition of a set_config reply 1554 */ 1555 struct set_config_reply_control_data { 1556 uint8_t instance; /* DPIA Instance */ 1557 uint8_t status; /* Set Config reply */ 1558 uint16_t pad; /* Alignment */ 1559 }; 1560 1561 /** 1562 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1563 */ 1564 struct dmub_rb_cmd_dp_set_config_reply { 1565 struct dmub_cmd_header header; 1566 struct set_config_reply_control_data set_config_reply_control; 1567 }; 1568 1569 /** 1570 * Definition of a DPIA notification header 1571 */ 1572 struct dpia_notification_header { 1573 uint8_t instance; /**< DPIA Instance */ 1574 uint8_t reserved[3]; 1575 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 1576 }; 1577 1578 /** 1579 * Definition of the common data struct of DPIA notification 1580 */ 1581 struct dpia_notification_common { 1582 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 1583 - sizeof(struct dpia_notification_header)]; 1584 }; 1585 1586 /** 1587 * Definition of a DPIA notification data 1588 */ 1589 struct dpia_bw_allocation_notify_data { 1590 union { 1591 struct { 1592 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 1593 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 1594 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 1595 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 1596 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 1597 uint16_t reserved: 11; /**< Reserved */ 1598 } bits; 1599 1600 uint16_t flags; 1601 }; 1602 1603 uint8_t cm_id; /**< CM ID */ 1604 uint8_t group_id; /**< Group ID */ 1605 uint8_t granularity; /**< BW Allocation Granularity */ 1606 uint8_t estimated_bw; /**< Estimated_BW */ 1607 uint8_t allocated_bw; /**< Allocated_BW */ 1608 uint8_t reserved; 1609 }; 1610 1611 /** 1612 * union dpia_notify_data_type - DPIA Notification in Outbox command 1613 */ 1614 union dpia_notification_data { 1615 /** 1616 * DPIA Notification for common data struct 1617 */ 1618 struct dpia_notification_common common_data; 1619 1620 /** 1621 * DPIA Notification for DP BW Allocation support 1622 */ 1623 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 1624 }; 1625 1626 /** 1627 * Definition of a DPIA notification payload 1628 */ 1629 struct dpia_notification_payload { 1630 struct dpia_notification_header header; 1631 union dpia_notification_data data; /**< DPIA notification payload data */ 1632 }; 1633 1634 /** 1635 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 1636 */ 1637 struct dmub_rb_cmd_dpia_notification { 1638 struct dmub_cmd_header header; /**< DPIA notification header */ 1639 struct dpia_notification_payload payload; /**< DPIA notification payload */ 1640 }; 1641 1642 /** 1643 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1644 */ 1645 struct dmub_cmd_hpd_state_query_data { 1646 uint8_t instance; /**< HPD instance or DPIA instance */ 1647 uint8_t result; /**< For returning HPD state */ 1648 uint16_t pad; /** < Alignment */ 1649 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1650 enum aux_return_code_type status; /**< for returning the status of command */ 1651 }; 1652 1653 /** 1654 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1655 */ 1656 struct dmub_rb_cmd_query_hpd_state { 1657 /** 1658 * Command header. 1659 */ 1660 struct dmub_cmd_header header; 1661 /** 1662 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1663 */ 1664 struct dmub_cmd_hpd_state_query_data data; 1665 }; 1666 1667 /* 1668 * Command IDs should be treated as stable ABI. 1669 * Do not reuse or modify IDs. 1670 */ 1671 1672 /** 1673 * PSR command sub-types. 1674 */ 1675 enum dmub_cmd_psr_type { 1676 /** 1677 * Set PSR version support. 1678 */ 1679 DMUB_CMD__PSR_SET_VERSION = 0, 1680 /** 1681 * Copy driver-calculated parameters to PSR state. 1682 */ 1683 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1684 /** 1685 * Enable PSR. 1686 */ 1687 DMUB_CMD__PSR_ENABLE = 2, 1688 1689 /** 1690 * Disable PSR. 1691 */ 1692 DMUB_CMD__PSR_DISABLE = 3, 1693 1694 /** 1695 * Set PSR level. 1696 * PSR level is a 16-bit value dicated by driver that 1697 * will enable/disable different functionality. 1698 */ 1699 DMUB_CMD__PSR_SET_LEVEL = 4, 1700 1701 /** 1702 * Forces PSR enabled until an explicit PSR disable call. 1703 */ 1704 DMUB_CMD__PSR_FORCE_STATIC = 5, 1705 /** 1706 * Set vtotal in psr active for FreeSync PSR. 1707 */ 1708 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1709 /** 1710 * Set PSR power option 1711 */ 1712 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1713 }; 1714 1715 enum dmub_cmd_fams_type { 1716 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1717 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1718 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1719 /** 1720 * For SubVP set manual trigger in FW because it 1721 * triggers DRR_UPDATE_PENDING which SubVP relies 1722 * on (for any SubVP cases that use a DRR display) 1723 */ 1724 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1725 }; 1726 1727 /** 1728 * PSR versions. 1729 */ 1730 enum psr_version { 1731 /** 1732 * PSR version 1. 1733 */ 1734 PSR_VERSION_1 = 0, 1735 /** 1736 * Freesync PSR SU. 1737 */ 1738 PSR_VERSION_SU_1 = 1, 1739 /** 1740 * PSR not supported. 1741 */ 1742 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1743 }; 1744 1745 /** 1746 * enum dmub_cmd_mall_type - MALL commands 1747 */ 1748 enum dmub_cmd_mall_type { 1749 /** 1750 * Allows display refresh from MALL. 1751 */ 1752 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1753 /** 1754 * Disallows display refresh from MALL. 1755 */ 1756 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1757 /** 1758 * Cursor copy for MALL. 1759 */ 1760 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1761 /** 1762 * Controls DF requests. 1763 */ 1764 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1765 }; 1766 1767 /** 1768 * PHY Link rate for DP. 1769 */ 1770 enum phy_link_rate { 1771 /** 1772 * not supported. 1773 */ 1774 PHY_RATE_UNKNOWN = 0, 1775 /** 1776 * Rate_1 (RBR) - 1.62 Gbps/Lane 1777 */ 1778 PHY_RATE_162 = 1, 1779 /** 1780 * Rate_2 - 2.16 Gbps/Lane 1781 */ 1782 PHY_RATE_216 = 2, 1783 /** 1784 * Rate_3 - 2.43 Gbps/Lane 1785 */ 1786 PHY_RATE_243 = 3, 1787 /** 1788 * Rate_4 (HBR) - 2.70 Gbps/Lane 1789 */ 1790 PHY_RATE_270 = 4, 1791 /** 1792 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1793 */ 1794 PHY_RATE_324 = 5, 1795 /** 1796 * Rate_6 - 4.32 Gbps/Lane 1797 */ 1798 PHY_RATE_432 = 6, 1799 /** 1800 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1801 */ 1802 PHY_RATE_540 = 7, 1803 /** 1804 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1805 */ 1806 PHY_RATE_810 = 8, 1807 /** 1808 * UHBR10 - 10.0 Gbps/Lane 1809 */ 1810 PHY_RATE_1000 = 9, 1811 /** 1812 * UHBR13.5 - 13.5 Gbps/Lane 1813 */ 1814 PHY_RATE_1350 = 10, 1815 /** 1816 * UHBR10 - 20.0 Gbps/Lane 1817 */ 1818 PHY_RATE_2000 = 11, 1819 }; 1820 1821 /** 1822 * enum dmub_phy_fsm_state - PHY FSM states. 1823 * PHY FSM state to transit to during PSR enable/disable. 1824 */ 1825 enum dmub_phy_fsm_state { 1826 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1827 DMUB_PHY_FSM_RESET, 1828 DMUB_PHY_FSM_RESET_RELEASED, 1829 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1830 DMUB_PHY_FSM_INITIALIZED, 1831 DMUB_PHY_FSM_CALIBRATED, 1832 DMUB_PHY_FSM_CALIBRATED_LP, 1833 DMUB_PHY_FSM_CALIBRATED_PG, 1834 DMUB_PHY_FSM_POWER_DOWN, 1835 DMUB_PHY_FSM_PLL_EN, 1836 DMUB_PHY_FSM_TX_EN, 1837 DMUB_PHY_FSM_FAST_LP, 1838 }; 1839 1840 /** 1841 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1842 */ 1843 struct dmub_cmd_psr_copy_settings_data { 1844 /** 1845 * Flags that can be set by driver to change some PSR behaviour. 1846 */ 1847 union dmub_psr_debug_flags debug; 1848 /** 1849 * 16-bit value dicated by driver that will enable/disable different functionality. 1850 */ 1851 uint16_t psr_level; 1852 /** 1853 * DPP HW instance. 1854 */ 1855 uint8_t dpp_inst; 1856 /** 1857 * MPCC HW instance. 1858 * Not used in dmub fw, 1859 * dmub fw will get active opp by reading odm registers. 1860 */ 1861 uint8_t mpcc_inst; 1862 /** 1863 * OPP HW instance. 1864 * Not used in dmub fw, 1865 * dmub fw will get active opp by reading odm registers. 1866 */ 1867 uint8_t opp_inst; 1868 /** 1869 * OTG HW instance. 1870 */ 1871 uint8_t otg_inst; 1872 /** 1873 * DIG FE HW instance. 1874 */ 1875 uint8_t digfe_inst; 1876 /** 1877 * DIG BE HW instance. 1878 */ 1879 uint8_t digbe_inst; 1880 /** 1881 * DP PHY HW instance. 1882 */ 1883 uint8_t dpphy_inst; 1884 /** 1885 * AUX HW instance. 1886 */ 1887 uint8_t aux_inst; 1888 /** 1889 * Determines if SMU optimzations are enabled/disabled. 1890 */ 1891 uint8_t smu_optimizations_en; 1892 /** 1893 * Unused. 1894 * TODO: Remove. 1895 */ 1896 uint8_t frame_delay; 1897 /** 1898 * If RFB setup time is greater than the total VBLANK time, 1899 * it is not possible for the sink to capture the video frame 1900 * in the same frame the SDP is sent. In this case, 1901 * the frame capture indication bit should be set and an extra 1902 * static frame should be transmitted to the sink. 1903 */ 1904 uint8_t frame_cap_ind; 1905 /** 1906 * Granularity of Y offset supported by sink. 1907 */ 1908 uint8_t su_y_granularity; 1909 /** 1910 * Indicates whether sink should start capturing 1911 * immediately following active scan line, 1912 * or starting with the 2nd active scan line. 1913 */ 1914 uint8_t line_capture_indication; 1915 /** 1916 * Multi-display optimizations are implemented on certain ASICs. 1917 */ 1918 uint8_t multi_disp_optimizations_en; 1919 /** 1920 * The last possible line SDP may be transmitted without violating 1921 * the RFB setup time or entering the active video frame. 1922 */ 1923 uint16_t init_sdp_deadline; 1924 /** 1925 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1926 */ 1927 uint8_t rate_control_caps ; 1928 /* 1929 * Force PSRSU always doing full frame update 1930 */ 1931 uint8_t force_ffu_mode; 1932 /** 1933 * Length of each horizontal line in us. 1934 */ 1935 uint32_t line_time_in_us; 1936 /** 1937 * FEC enable status in driver 1938 */ 1939 uint8_t fec_enable_status; 1940 /** 1941 * FEC re-enable delay when PSR exit. 1942 * unit is 100us, range form 0~255(0xFF). 1943 */ 1944 uint8_t fec_enable_delay_in100us; 1945 /** 1946 * PSR control version. 1947 */ 1948 uint8_t cmd_version; 1949 /** 1950 * Panel Instance. 1951 * Panel isntance to identify which psr_state to use 1952 * Currently the support is only for 0 or 1 1953 */ 1954 uint8_t panel_inst; 1955 /* 1956 * DSC enable status in driver 1957 */ 1958 uint8_t dsc_enable_status; 1959 /* 1960 * Use FSM state for PSR power up/down 1961 */ 1962 uint8_t use_phy_fsm; 1963 /** 1964 * frame delay for frame re-lock 1965 */ 1966 uint8_t relock_delay_frame_cnt; 1967 /** 1968 * Explicit padding to 2 byte boundary. 1969 */ 1970 uint8_t pad3; 1971 /** 1972 * DSC Slice height. 1973 */ 1974 uint16_t dsc_slice_height; 1975 /** 1976 * Explicit padding to 4 byte boundary. 1977 */ 1978 uint16_t pad; 1979 }; 1980 1981 /** 1982 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1983 */ 1984 struct dmub_rb_cmd_psr_copy_settings { 1985 /** 1986 * Command header. 1987 */ 1988 struct dmub_cmd_header header; 1989 /** 1990 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1991 */ 1992 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1993 }; 1994 1995 /** 1996 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1997 */ 1998 struct dmub_cmd_psr_set_level_data { 1999 /** 2000 * 16-bit value dicated by driver that will enable/disable different functionality. 2001 */ 2002 uint16_t psr_level; 2003 /** 2004 * PSR control version. 2005 */ 2006 uint8_t cmd_version; 2007 /** 2008 * Panel Instance. 2009 * Panel isntance to identify which psr_state to use 2010 * Currently the support is only for 0 or 1 2011 */ 2012 uint8_t panel_inst; 2013 }; 2014 2015 /** 2016 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2017 */ 2018 struct dmub_rb_cmd_psr_set_level { 2019 /** 2020 * Command header. 2021 */ 2022 struct dmub_cmd_header header; 2023 /** 2024 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2025 */ 2026 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2027 }; 2028 2029 struct dmub_rb_cmd_psr_enable_data { 2030 /** 2031 * PSR control version. 2032 */ 2033 uint8_t cmd_version; 2034 /** 2035 * Panel Instance. 2036 * Panel isntance to identify which psr_state to use 2037 * Currently the support is only for 0 or 1 2038 */ 2039 uint8_t panel_inst; 2040 /** 2041 * Phy state to enter. 2042 * Values to use are defined in dmub_phy_fsm_state 2043 */ 2044 uint8_t phy_fsm_state; 2045 /** 2046 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2047 * Set this using enum phy_link_rate. 2048 * This does not support HDMI/DP2 for now. 2049 */ 2050 uint8_t phy_rate; 2051 }; 2052 2053 /** 2054 * Definition of a DMUB_CMD__PSR_ENABLE command. 2055 * PSR enable/disable is controlled using the sub_type. 2056 */ 2057 struct dmub_rb_cmd_psr_enable { 2058 /** 2059 * Command header. 2060 */ 2061 struct dmub_cmd_header header; 2062 2063 struct dmub_rb_cmd_psr_enable_data data; 2064 }; 2065 2066 /** 2067 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2068 */ 2069 struct dmub_cmd_psr_set_version_data { 2070 /** 2071 * PSR version that FW should implement. 2072 */ 2073 enum psr_version version; 2074 /** 2075 * PSR control version. 2076 */ 2077 uint8_t cmd_version; 2078 /** 2079 * Panel Instance. 2080 * Panel isntance to identify which psr_state to use 2081 * Currently the support is only for 0 or 1 2082 */ 2083 uint8_t panel_inst; 2084 /** 2085 * Explicit padding to 4 byte boundary. 2086 */ 2087 uint8_t pad[2]; 2088 }; 2089 2090 /** 2091 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2092 */ 2093 struct dmub_rb_cmd_psr_set_version { 2094 /** 2095 * Command header. 2096 */ 2097 struct dmub_cmd_header header; 2098 /** 2099 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2100 */ 2101 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2102 }; 2103 2104 struct dmub_cmd_psr_force_static_data { 2105 /** 2106 * PSR control version. 2107 */ 2108 uint8_t cmd_version; 2109 /** 2110 * Panel Instance. 2111 * Panel isntance to identify which psr_state to use 2112 * Currently the support is only for 0 or 1 2113 */ 2114 uint8_t panel_inst; 2115 /** 2116 * Explicit padding to 4 byte boundary. 2117 */ 2118 uint8_t pad[2]; 2119 }; 2120 2121 /** 2122 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2123 */ 2124 struct dmub_rb_cmd_psr_force_static { 2125 /** 2126 * Command header. 2127 */ 2128 struct dmub_cmd_header header; 2129 /** 2130 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2131 */ 2132 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2133 }; 2134 2135 /** 2136 * PSR SU debug flags. 2137 */ 2138 union dmub_psr_su_debug_flags { 2139 /** 2140 * PSR SU debug flags. 2141 */ 2142 struct { 2143 /** 2144 * Update dirty rect in SW only. 2145 */ 2146 uint8_t update_dirty_rect_only : 1; 2147 /** 2148 * Reset the cursor/plane state before processing the call. 2149 */ 2150 uint8_t reset_state : 1; 2151 } bitfields; 2152 2153 /** 2154 * Union for debug flags. 2155 */ 2156 uint32_t u32All; 2157 }; 2158 2159 /** 2160 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2161 * This triggers a selective update for PSR SU. 2162 */ 2163 struct dmub_cmd_update_dirty_rect_data { 2164 /** 2165 * Dirty rects from OS. 2166 */ 2167 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2168 /** 2169 * PSR SU debug flags. 2170 */ 2171 union dmub_psr_su_debug_flags debug_flags; 2172 /** 2173 * OTG HW instance. 2174 */ 2175 uint8_t pipe_idx; 2176 /** 2177 * Number of dirty rects. 2178 */ 2179 uint8_t dirty_rect_count; 2180 /** 2181 * PSR control version. 2182 */ 2183 uint8_t cmd_version; 2184 /** 2185 * Panel Instance. 2186 * Panel isntance to identify which psr_state to use 2187 * Currently the support is only for 0 or 1 2188 */ 2189 uint8_t panel_inst; 2190 }; 2191 2192 /** 2193 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2194 */ 2195 struct dmub_rb_cmd_update_dirty_rect { 2196 /** 2197 * Command header. 2198 */ 2199 struct dmub_cmd_header header; 2200 /** 2201 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2202 */ 2203 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2204 }; 2205 2206 /** 2207 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2208 */ 2209 union dmub_reg_cursor_control_cfg { 2210 struct { 2211 uint32_t cur_enable: 1; 2212 uint32_t reser0: 3; 2213 uint32_t cur_2x_magnify: 1; 2214 uint32_t reser1: 3; 2215 uint32_t mode: 3; 2216 uint32_t reser2: 5; 2217 uint32_t pitch: 2; 2218 uint32_t reser3: 6; 2219 uint32_t line_per_chunk: 5; 2220 uint32_t reser4: 3; 2221 } bits; 2222 uint32_t raw; 2223 }; 2224 struct dmub_cursor_position_cache_hubp { 2225 union dmub_reg_cursor_control_cfg cur_ctl; 2226 union dmub_reg_position_cfg { 2227 struct { 2228 uint32_t cur_x_pos: 16; 2229 uint32_t cur_y_pos: 16; 2230 } bits; 2231 uint32_t raw; 2232 } position; 2233 union dmub_reg_hot_spot_cfg { 2234 struct { 2235 uint32_t hot_x: 16; 2236 uint32_t hot_y: 16; 2237 } bits; 2238 uint32_t raw; 2239 } hot_spot; 2240 union dmub_reg_dst_offset_cfg { 2241 struct { 2242 uint32_t dst_x_offset: 13; 2243 uint32_t reserved: 19; 2244 } bits; 2245 uint32_t raw; 2246 } dst_offset; 2247 }; 2248 2249 union dmub_reg_cur0_control_cfg { 2250 struct { 2251 uint32_t cur0_enable: 1; 2252 uint32_t expansion_mode: 1; 2253 uint32_t reser0: 1; 2254 uint32_t cur0_rom_en: 1; 2255 uint32_t mode: 3; 2256 uint32_t reserved: 25; 2257 } bits; 2258 uint32_t raw; 2259 }; 2260 struct dmub_cursor_position_cache_dpp { 2261 union dmub_reg_cur0_control_cfg cur0_ctl; 2262 }; 2263 struct dmub_cursor_position_cfg { 2264 struct dmub_cursor_position_cache_hubp pHubp; 2265 struct dmub_cursor_position_cache_dpp pDpp; 2266 uint8_t pipe_idx; 2267 /* 2268 * Padding is required. To be 4 Bytes Aligned. 2269 */ 2270 uint8_t padding[3]; 2271 }; 2272 2273 struct dmub_cursor_attribute_cache_hubp { 2274 uint32_t SURFACE_ADDR_HIGH; 2275 uint32_t SURFACE_ADDR; 2276 union dmub_reg_cursor_control_cfg cur_ctl; 2277 union dmub_reg_cursor_size_cfg { 2278 struct { 2279 uint32_t width: 16; 2280 uint32_t height: 16; 2281 } bits; 2282 uint32_t raw; 2283 } size; 2284 union dmub_reg_cursor_settings_cfg { 2285 struct { 2286 uint32_t dst_y_offset: 8; 2287 uint32_t chunk_hdl_adjust: 2; 2288 uint32_t reserved: 22; 2289 } bits; 2290 uint32_t raw; 2291 } settings; 2292 }; 2293 struct dmub_cursor_attribute_cache_dpp { 2294 union dmub_reg_cur0_control_cfg cur0_ctl; 2295 }; 2296 struct dmub_cursor_attributes_cfg { 2297 struct dmub_cursor_attribute_cache_hubp aHubp; 2298 struct dmub_cursor_attribute_cache_dpp aDpp; 2299 }; 2300 2301 struct dmub_cmd_update_cursor_payload0 { 2302 /** 2303 * Cursor dirty rects. 2304 */ 2305 struct dmub_rect cursor_rect; 2306 /** 2307 * PSR SU debug flags. 2308 */ 2309 union dmub_psr_su_debug_flags debug_flags; 2310 /** 2311 * Cursor enable/disable. 2312 */ 2313 uint8_t enable; 2314 /** 2315 * OTG HW instance. 2316 */ 2317 uint8_t pipe_idx; 2318 /** 2319 * PSR control version. 2320 */ 2321 uint8_t cmd_version; 2322 /** 2323 * Panel Instance. 2324 * Panel isntance to identify which psr_state to use 2325 * Currently the support is only for 0 or 1 2326 */ 2327 uint8_t panel_inst; 2328 /** 2329 * Cursor Position Register. 2330 * Registers contains Hubp & Dpp modules 2331 */ 2332 struct dmub_cursor_position_cfg position_cfg; 2333 }; 2334 2335 struct dmub_cmd_update_cursor_payload1 { 2336 struct dmub_cursor_attributes_cfg attribute_cfg; 2337 }; 2338 2339 union dmub_cmd_update_cursor_info_data { 2340 struct dmub_cmd_update_cursor_payload0 payload0; 2341 struct dmub_cmd_update_cursor_payload1 payload1; 2342 }; 2343 /** 2344 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2345 */ 2346 struct dmub_rb_cmd_update_cursor_info { 2347 /** 2348 * Command header. 2349 */ 2350 struct dmub_cmd_header header; 2351 /** 2352 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2353 */ 2354 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2355 }; 2356 2357 /** 2358 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2359 */ 2360 struct dmub_cmd_psr_set_vtotal_data { 2361 /** 2362 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2363 */ 2364 uint16_t psr_vtotal_idle; 2365 /** 2366 * PSR control version. 2367 */ 2368 uint8_t cmd_version; 2369 /** 2370 * Panel Instance. 2371 * Panel isntance to identify which psr_state to use 2372 * Currently the support is only for 0 or 1 2373 */ 2374 uint8_t panel_inst; 2375 /* 2376 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2377 */ 2378 uint16_t psr_vtotal_su; 2379 /** 2380 * Explicit padding to 4 byte boundary. 2381 */ 2382 uint8_t pad2[2]; 2383 }; 2384 2385 /** 2386 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2387 */ 2388 struct dmub_rb_cmd_psr_set_vtotal { 2389 /** 2390 * Command header. 2391 */ 2392 struct dmub_cmd_header header; 2393 /** 2394 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2395 */ 2396 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2397 }; 2398 2399 /** 2400 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2401 */ 2402 struct dmub_cmd_psr_set_power_opt_data { 2403 /** 2404 * PSR control version. 2405 */ 2406 uint8_t cmd_version; 2407 /** 2408 * Panel Instance. 2409 * Panel isntance to identify which psr_state to use 2410 * Currently the support is only for 0 or 1 2411 */ 2412 uint8_t panel_inst; 2413 /** 2414 * Explicit padding to 4 byte boundary. 2415 */ 2416 uint8_t pad[2]; 2417 /** 2418 * PSR power option 2419 */ 2420 uint32_t power_opt; 2421 }; 2422 2423 /** 2424 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2425 */ 2426 struct dmub_rb_cmd_psr_set_power_opt { 2427 /** 2428 * Command header. 2429 */ 2430 struct dmub_cmd_header header; 2431 /** 2432 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2433 */ 2434 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2435 }; 2436 2437 /** 2438 * Set of HW components that can be locked. 2439 * 2440 * Note: If updating with more HW components, fields 2441 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2442 */ 2443 union dmub_hw_lock_flags { 2444 /** 2445 * Set of HW components that can be locked. 2446 */ 2447 struct { 2448 /** 2449 * Lock/unlock OTG master update lock. 2450 */ 2451 uint8_t lock_pipe : 1; 2452 /** 2453 * Lock/unlock cursor. 2454 */ 2455 uint8_t lock_cursor : 1; 2456 /** 2457 * Lock/unlock global update lock. 2458 */ 2459 uint8_t lock_dig : 1; 2460 /** 2461 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2462 */ 2463 uint8_t triple_buffer_lock : 1; 2464 } bits; 2465 2466 /** 2467 * Union for HW Lock flags. 2468 */ 2469 uint8_t u8All; 2470 }; 2471 2472 /** 2473 * Instances of HW to be locked. 2474 * 2475 * Note: If updating with more HW components, fields 2476 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2477 */ 2478 struct dmub_hw_lock_inst_flags { 2479 /** 2480 * OTG HW instance for OTG master update lock. 2481 */ 2482 uint8_t otg_inst; 2483 /** 2484 * OPP instance for cursor lock. 2485 */ 2486 uint8_t opp_inst; 2487 /** 2488 * OTG HW instance for global update lock. 2489 * TODO: Remove, and re-use otg_inst. 2490 */ 2491 uint8_t dig_inst; 2492 /** 2493 * Explicit pad to 4 byte boundary. 2494 */ 2495 uint8_t pad; 2496 }; 2497 2498 /** 2499 * Clients that can acquire the HW Lock Manager. 2500 * 2501 * Note: If updating with more clients, fields in 2502 * dmub_inbox0_cmd_lock_hw must be updated to match. 2503 */ 2504 enum hw_lock_client { 2505 /** 2506 * Driver is the client of HW Lock Manager. 2507 */ 2508 HW_LOCK_CLIENT_DRIVER = 0, 2509 /** 2510 * PSR SU is the client of HW Lock Manager. 2511 */ 2512 HW_LOCK_CLIENT_PSR_SU = 1, 2513 /** 2514 * Invalid client. 2515 */ 2516 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2517 }; 2518 2519 /** 2520 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2521 */ 2522 struct dmub_cmd_lock_hw_data { 2523 /** 2524 * Specifies the client accessing HW Lock Manager. 2525 */ 2526 enum hw_lock_client client; 2527 /** 2528 * HW instances to be locked. 2529 */ 2530 struct dmub_hw_lock_inst_flags inst_flags; 2531 /** 2532 * Which components to be locked. 2533 */ 2534 union dmub_hw_lock_flags hw_locks; 2535 /** 2536 * Specifies lock/unlock. 2537 */ 2538 uint8_t lock; 2539 /** 2540 * HW can be unlocked separately from releasing the HW Lock Mgr. 2541 * This flag is set if the client wishes to release the object. 2542 */ 2543 uint8_t should_release; 2544 /** 2545 * Explicit padding to 4 byte boundary. 2546 */ 2547 uint8_t pad; 2548 }; 2549 2550 /** 2551 * Definition of a DMUB_CMD__HW_LOCK command. 2552 * Command is used by driver and FW. 2553 */ 2554 struct dmub_rb_cmd_lock_hw { 2555 /** 2556 * Command header. 2557 */ 2558 struct dmub_cmd_header header; 2559 /** 2560 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2561 */ 2562 struct dmub_cmd_lock_hw_data lock_hw_data; 2563 }; 2564 2565 /** 2566 * ABM command sub-types. 2567 */ 2568 enum dmub_cmd_abm_type { 2569 /** 2570 * Initialize parameters for ABM algorithm. 2571 * Data is passed through an indirect buffer. 2572 */ 2573 DMUB_CMD__ABM_INIT_CONFIG = 0, 2574 /** 2575 * Set OTG and panel HW instance. 2576 */ 2577 DMUB_CMD__ABM_SET_PIPE = 1, 2578 /** 2579 * Set user requested backklight level. 2580 */ 2581 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2582 /** 2583 * Set ABM operating/aggression level. 2584 */ 2585 DMUB_CMD__ABM_SET_LEVEL = 3, 2586 /** 2587 * Set ambient light level. 2588 */ 2589 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2590 /** 2591 * Enable/disable fractional duty cycle for backlight PWM. 2592 */ 2593 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2594 2595 /** 2596 * unregister vertical interrupt after steady state is reached 2597 */ 2598 DMUB_CMD__ABM_PAUSE = 6, 2599 }; 2600 2601 /** 2602 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2603 * Requirements: 2604 * - Padded explicitly to 32-bit boundary. 2605 * - Must ensure this structure matches the one on driver-side, 2606 * otherwise it won't be aligned. 2607 */ 2608 struct abm_config_table { 2609 /** 2610 * Gamma curve thresholds, used for crgb conversion. 2611 */ 2612 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2613 /** 2614 * Gamma curve offsets, used for crgb conversion. 2615 */ 2616 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2617 /** 2618 * Gamma curve slopes, used for crgb conversion. 2619 */ 2620 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2621 /** 2622 * Custom backlight curve thresholds. 2623 */ 2624 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2625 /** 2626 * Custom backlight curve offsets. 2627 */ 2628 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2629 /** 2630 * Ambient light thresholds. 2631 */ 2632 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2633 /** 2634 * Minimum programmable backlight. 2635 */ 2636 uint16_t min_abm_backlight; // 122B 2637 /** 2638 * Minimum reduction values. 2639 */ 2640 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2641 /** 2642 * Maximum reduction values. 2643 */ 2644 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2645 /** 2646 * Bright positive gain. 2647 */ 2648 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2649 /** 2650 * Dark negative gain. 2651 */ 2652 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2653 /** 2654 * Hybrid factor. 2655 */ 2656 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2657 /** 2658 * Contrast factor. 2659 */ 2660 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2661 /** 2662 * Deviation gain. 2663 */ 2664 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2665 /** 2666 * Minimum knee. 2667 */ 2668 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2669 /** 2670 * Maximum knee. 2671 */ 2672 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2673 /** 2674 * Unused. 2675 */ 2676 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2677 /** 2678 * Explicit padding to 4 byte boundary. 2679 */ 2680 uint8_t pad3[3]; // 229B 2681 /** 2682 * Backlight ramp reduction. 2683 */ 2684 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2685 /** 2686 * Backlight ramp start. 2687 */ 2688 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2689 }; 2690 2691 /** 2692 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2693 */ 2694 struct dmub_cmd_abm_set_pipe_data { 2695 /** 2696 * OTG HW instance. 2697 */ 2698 uint8_t otg_inst; 2699 2700 /** 2701 * Panel Control HW instance. 2702 */ 2703 uint8_t panel_inst; 2704 2705 /** 2706 * Controls how ABM will interpret a set pipe or set level command. 2707 */ 2708 uint8_t set_pipe_option; 2709 2710 /** 2711 * Unused. 2712 * TODO: Remove. 2713 */ 2714 uint8_t ramping_boundary; 2715 }; 2716 2717 /** 2718 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2719 */ 2720 struct dmub_rb_cmd_abm_set_pipe { 2721 /** 2722 * Command header. 2723 */ 2724 struct dmub_cmd_header header; 2725 2726 /** 2727 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2728 */ 2729 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2730 }; 2731 2732 /** 2733 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2734 */ 2735 struct dmub_cmd_abm_set_backlight_data { 2736 /** 2737 * Number of frames to ramp to backlight user level. 2738 */ 2739 uint32_t frame_ramp; 2740 2741 /** 2742 * Requested backlight level from user. 2743 */ 2744 uint32_t backlight_user_level; 2745 2746 /** 2747 * ABM control version. 2748 */ 2749 uint8_t version; 2750 2751 /** 2752 * Panel Control HW instance mask. 2753 * Bit 0 is Panel Control HW instance 0. 2754 * Bit 1 is Panel Control HW instance 1. 2755 */ 2756 uint8_t panel_mask; 2757 2758 /** 2759 * Explicit padding to 4 byte boundary. 2760 */ 2761 uint8_t pad[2]; 2762 }; 2763 2764 /** 2765 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2766 */ 2767 struct dmub_rb_cmd_abm_set_backlight { 2768 /** 2769 * Command header. 2770 */ 2771 struct dmub_cmd_header header; 2772 2773 /** 2774 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2775 */ 2776 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2777 }; 2778 2779 /** 2780 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2781 */ 2782 struct dmub_cmd_abm_set_level_data { 2783 /** 2784 * Set current ABM operating/aggression level. 2785 */ 2786 uint32_t level; 2787 2788 /** 2789 * ABM control version. 2790 */ 2791 uint8_t version; 2792 2793 /** 2794 * Panel Control HW instance mask. 2795 * Bit 0 is Panel Control HW instance 0. 2796 * Bit 1 is Panel Control HW instance 1. 2797 */ 2798 uint8_t panel_mask; 2799 2800 /** 2801 * Explicit padding to 4 byte boundary. 2802 */ 2803 uint8_t pad[2]; 2804 }; 2805 2806 /** 2807 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2808 */ 2809 struct dmub_rb_cmd_abm_set_level { 2810 /** 2811 * Command header. 2812 */ 2813 struct dmub_cmd_header header; 2814 2815 /** 2816 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2817 */ 2818 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2819 }; 2820 2821 /** 2822 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2823 */ 2824 struct dmub_cmd_abm_set_ambient_level_data { 2825 /** 2826 * Ambient light sensor reading from OS. 2827 */ 2828 uint32_t ambient_lux; 2829 2830 /** 2831 * ABM control version. 2832 */ 2833 uint8_t version; 2834 2835 /** 2836 * Panel Control HW instance mask. 2837 * Bit 0 is Panel Control HW instance 0. 2838 * Bit 1 is Panel Control HW instance 1. 2839 */ 2840 uint8_t panel_mask; 2841 2842 /** 2843 * Explicit padding to 4 byte boundary. 2844 */ 2845 uint8_t pad[2]; 2846 }; 2847 2848 /** 2849 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2850 */ 2851 struct dmub_rb_cmd_abm_set_ambient_level { 2852 /** 2853 * Command header. 2854 */ 2855 struct dmub_cmd_header header; 2856 2857 /** 2858 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2859 */ 2860 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2861 }; 2862 2863 /** 2864 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2865 */ 2866 struct dmub_cmd_abm_set_pwm_frac_data { 2867 /** 2868 * Enable/disable fractional duty cycle for backlight PWM. 2869 * TODO: Convert to uint8_t. 2870 */ 2871 uint32_t fractional_pwm; 2872 2873 /** 2874 * ABM control version. 2875 */ 2876 uint8_t version; 2877 2878 /** 2879 * Panel Control HW instance mask. 2880 * Bit 0 is Panel Control HW instance 0. 2881 * Bit 1 is Panel Control HW instance 1. 2882 */ 2883 uint8_t panel_mask; 2884 2885 /** 2886 * Explicit padding to 4 byte boundary. 2887 */ 2888 uint8_t pad[2]; 2889 }; 2890 2891 /** 2892 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2893 */ 2894 struct dmub_rb_cmd_abm_set_pwm_frac { 2895 /** 2896 * Command header. 2897 */ 2898 struct dmub_cmd_header header; 2899 2900 /** 2901 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2902 */ 2903 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2904 }; 2905 2906 /** 2907 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2908 */ 2909 struct dmub_cmd_abm_init_config_data { 2910 /** 2911 * Location of indirect buffer used to pass init data to ABM. 2912 */ 2913 union dmub_addr src; 2914 2915 /** 2916 * Indirect buffer length. 2917 */ 2918 uint16_t bytes; 2919 2920 2921 /** 2922 * ABM control version. 2923 */ 2924 uint8_t version; 2925 2926 /** 2927 * Panel Control HW instance mask. 2928 * Bit 0 is Panel Control HW instance 0. 2929 * Bit 1 is Panel Control HW instance 1. 2930 */ 2931 uint8_t panel_mask; 2932 2933 /** 2934 * Explicit padding to 4 byte boundary. 2935 */ 2936 uint8_t pad[2]; 2937 }; 2938 2939 /** 2940 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2941 */ 2942 struct dmub_rb_cmd_abm_init_config { 2943 /** 2944 * Command header. 2945 */ 2946 struct dmub_cmd_header header; 2947 2948 /** 2949 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2950 */ 2951 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2952 }; 2953 2954 /** 2955 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2956 */ 2957 2958 struct dmub_cmd_abm_pause_data { 2959 2960 /** 2961 * Panel Control HW instance mask. 2962 * Bit 0 is Panel Control HW instance 0. 2963 * Bit 1 is Panel Control HW instance 1. 2964 */ 2965 uint8_t panel_mask; 2966 2967 /** 2968 * OTG hw instance 2969 */ 2970 uint8_t otg_inst; 2971 2972 /** 2973 * Enable or disable ABM pause 2974 */ 2975 uint8_t enable; 2976 2977 /** 2978 * Explicit padding to 4 byte boundary. 2979 */ 2980 uint8_t pad[1]; 2981 }; 2982 2983 /** 2984 * Definition of a DMUB_CMD__ABM_PAUSE command. 2985 */ 2986 struct dmub_rb_cmd_abm_pause { 2987 /** 2988 * Command header. 2989 */ 2990 struct dmub_cmd_header header; 2991 2992 /** 2993 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2994 */ 2995 struct dmub_cmd_abm_pause_data abm_pause_data; 2996 }; 2997 2998 /** 2999 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3000 */ 3001 struct dmub_cmd_query_feature_caps_data { 3002 /** 3003 * DMUB feature capabilities. 3004 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3005 */ 3006 struct dmub_feature_caps feature_caps; 3007 }; 3008 3009 /** 3010 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3011 */ 3012 struct dmub_rb_cmd_query_feature_caps { 3013 /** 3014 * Command header. 3015 */ 3016 struct dmub_cmd_header header; 3017 /** 3018 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3019 */ 3020 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 3021 }; 3022 3023 /** 3024 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3025 */ 3026 struct dmub_cmd_visual_confirm_color_data { 3027 /** 3028 * DMUB feature capabilities. 3029 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3030 */ 3031 struct dmub_visual_confirm_color visual_confirm_color; 3032 }; 3033 3034 /** 3035 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3036 */ 3037 struct dmub_rb_cmd_get_visual_confirm_color { 3038 /** 3039 * Command header. 3040 */ 3041 struct dmub_cmd_header header; 3042 /** 3043 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3044 */ 3045 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3046 }; 3047 3048 struct dmub_optc_state { 3049 uint32_t v_total_max; 3050 uint32_t v_total_min; 3051 uint32_t tg_inst; 3052 }; 3053 3054 struct dmub_rb_cmd_drr_update { 3055 struct dmub_cmd_header header; 3056 struct dmub_optc_state dmub_optc_state_req; 3057 }; 3058 3059 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 3060 uint32_t pix_clk_100hz; 3061 uint8_t max_ramp_step; 3062 uint8_t pipes; 3063 uint8_t min_refresh_in_hz; 3064 uint8_t padding[1]; 3065 }; 3066 3067 struct dmub_cmd_fw_assisted_mclk_switch_config { 3068 uint8_t fams_enabled; 3069 uint8_t visual_confirm_enabled; 3070 uint8_t padding[2]; 3071 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 3072 }; 3073 3074 struct dmub_rb_cmd_fw_assisted_mclk_switch { 3075 struct dmub_cmd_header header; 3076 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 3077 }; 3078 3079 /** 3080 * enum dmub_cmd_panel_cntl_type - Panel control command. 3081 */ 3082 enum dmub_cmd_panel_cntl_type { 3083 /** 3084 * Initializes embedded panel hardware blocks. 3085 */ 3086 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3087 /** 3088 * Queries backlight info for the embedded panel. 3089 */ 3090 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3091 }; 3092 3093 /** 3094 * struct dmub_cmd_panel_cntl_data - Panel control data. 3095 */ 3096 struct dmub_cmd_panel_cntl_data { 3097 uint32_t inst; /**< panel instance */ 3098 uint32_t current_backlight; /* in/out */ 3099 uint32_t bl_pwm_cntl; /* in/out */ 3100 uint32_t bl_pwm_period_cntl; /* in/out */ 3101 uint32_t bl_pwm_ref_div1; /* in/out */ 3102 uint8_t is_backlight_on : 1; /* in/out */ 3103 uint8_t is_powered_on : 1; /* in/out */ 3104 uint8_t padding[3]; 3105 uint32_t bl_pwm_ref_div2; /* in/out */ 3106 uint8_t reserved[4]; 3107 }; 3108 3109 /** 3110 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3111 */ 3112 struct dmub_rb_cmd_panel_cntl { 3113 struct dmub_cmd_header header; /**< header */ 3114 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3115 }; 3116 3117 /** 3118 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3119 */ 3120 struct dmub_cmd_lvtma_control_data { 3121 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3122 uint8_t bypass_panel_control_wait; 3123 uint8_t reserved_0[2]; /**< For future use */ 3124 uint8_t panel_inst; /**< LVTMA control instance */ 3125 uint8_t reserved_1[3]; /**< For future use */ 3126 }; 3127 3128 /** 3129 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3130 */ 3131 struct dmub_rb_cmd_lvtma_control { 3132 /** 3133 * Command header. 3134 */ 3135 struct dmub_cmd_header header; 3136 /** 3137 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3138 */ 3139 struct dmub_cmd_lvtma_control_data data; 3140 }; 3141 3142 /** 3143 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3144 */ 3145 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3146 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3147 uint8_t is_usb; /**< is phy is usb */ 3148 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3149 uint8_t is_dp4; /**< is dp in 4 lane */ 3150 }; 3151 3152 /** 3153 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3154 */ 3155 struct dmub_rb_cmd_transmitter_query_dp_alt { 3156 struct dmub_cmd_header header; /**< header */ 3157 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3158 }; 3159 3160 /** 3161 * Maximum number of bytes a chunk sent to DMUB for parsing 3162 */ 3163 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3164 3165 /** 3166 * Represent a chunk of CEA blocks sent to DMUB for parsing 3167 */ 3168 struct dmub_cmd_send_edid_cea { 3169 uint16_t offset; /**< offset into the CEA block */ 3170 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3171 uint16_t cea_total_length; /**< total length of the CEA block */ 3172 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3173 uint8_t pad[3]; /**< padding and for future expansion */ 3174 }; 3175 3176 /** 3177 * Result of VSDB parsing from CEA block 3178 */ 3179 struct dmub_cmd_edid_cea_amd_vsdb { 3180 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3181 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3182 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3183 uint16_t min_frame_rate; /**< Maximum frame rate */ 3184 uint16_t max_frame_rate; /**< Minimum frame rate */ 3185 }; 3186 3187 /** 3188 * Result of sending a CEA chunk 3189 */ 3190 struct dmub_cmd_edid_cea_ack { 3191 uint16_t offset; /**< offset of the chunk into the CEA block */ 3192 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3193 uint8_t pad; /**< padding and for future expansion */ 3194 }; 3195 3196 /** 3197 * Specify whether the result is an ACK/NACK or the parsing has finished 3198 */ 3199 enum dmub_cmd_edid_cea_reply_type { 3200 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3201 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3202 }; 3203 3204 /** 3205 * Definition of a DMUB_CMD__EDID_CEA command. 3206 */ 3207 struct dmub_rb_cmd_edid_cea { 3208 struct dmub_cmd_header header; /**< Command header */ 3209 union dmub_cmd_edid_cea_data { 3210 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3211 struct dmub_cmd_edid_cea_output { /**< output with results */ 3212 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3213 union { 3214 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3215 struct dmub_cmd_edid_cea_ack ack; 3216 }; 3217 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3218 } data; /**< Command data */ 3219 3220 }; 3221 3222 /** 3223 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3224 */ 3225 struct dmub_cmd_cable_id_input { 3226 uint8_t phy_inst; /**< phy inst for cable id data */ 3227 }; 3228 3229 /** 3230 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3231 */ 3232 struct dmub_cmd_cable_id_output { 3233 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3234 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3235 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3236 uint8_t RESERVED :2; /**< reserved means not defined */ 3237 }; 3238 3239 /** 3240 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3241 */ 3242 struct dmub_rb_cmd_get_usbc_cable_id { 3243 struct dmub_cmd_header header; /**< Command header */ 3244 /** 3245 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3246 */ 3247 union dmub_cmd_cable_id_data { 3248 struct dmub_cmd_cable_id_input input; /**< Input */ 3249 struct dmub_cmd_cable_id_output output; /**< Output */ 3250 uint8_t output_raw; /**< Raw data output */ 3251 } data; 3252 }; 3253 3254 /** 3255 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3256 */ 3257 enum dmub_cmd_secure_display_type { 3258 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3259 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3260 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3261 }; 3262 3263 /** 3264 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3265 */ 3266 struct dmub_rb_cmd_secure_display { 3267 struct dmub_cmd_header header; 3268 /** 3269 * Data passed from driver to dmub firmware. 3270 */ 3271 struct dmub_cmd_roi_info { 3272 uint16_t x_start; 3273 uint16_t x_end; 3274 uint16_t y_start; 3275 uint16_t y_end; 3276 uint8_t otg_id; 3277 uint8_t phy_id; 3278 } roi_info; 3279 }; 3280 3281 /** 3282 * union dmub_rb_cmd - DMUB inbox command. 3283 */ 3284 union dmub_rb_cmd { 3285 /** 3286 * Elements shared with all commands. 3287 */ 3288 struct dmub_rb_cmd_common cmd_common; 3289 /** 3290 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3291 */ 3292 struct dmub_rb_cmd_read_modify_write read_modify_write; 3293 /** 3294 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3295 */ 3296 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3297 /** 3298 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3299 */ 3300 struct dmub_rb_cmd_burst_write burst_write; 3301 /** 3302 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3303 */ 3304 struct dmub_rb_cmd_reg_wait reg_wait; 3305 /** 3306 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3307 */ 3308 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3309 /** 3310 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3311 */ 3312 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3313 /** 3314 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3315 */ 3316 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3317 /** 3318 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3319 */ 3320 struct dmub_rb_cmd_dpphy_init dpphy_init; 3321 /** 3322 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3323 */ 3324 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3325 /** 3326 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3327 */ 3328 struct dmub_rb_cmd_psr_set_version psr_set_version; 3329 /** 3330 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3331 */ 3332 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3333 /** 3334 * Definition of a DMUB_CMD__PSR_ENABLE command. 3335 */ 3336 struct dmub_rb_cmd_psr_enable psr_enable; 3337 /** 3338 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3339 */ 3340 struct dmub_rb_cmd_psr_set_level psr_set_level; 3341 /** 3342 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3343 */ 3344 struct dmub_rb_cmd_psr_force_static psr_force_static; 3345 /** 3346 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3347 */ 3348 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3349 /** 3350 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3351 */ 3352 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3353 /** 3354 * Definition of a DMUB_CMD__HW_LOCK command. 3355 * Command is used by driver and FW. 3356 */ 3357 struct dmub_rb_cmd_lock_hw lock_hw; 3358 /** 3359 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3360 */ 3361 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3362 /** 3363 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3364 */ 3365 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3366 /** 3367 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3368 */ 3369 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3370 /** 3371 * Definition of a DMUB_CMD__MALL command. 3372 */ 3373 struct dmub_rb_cmd_mall mall; 3374 /** 3375 * Definition of a DMUB_CMD__CAB command. 3376 */ 3377 struct dmub_rb_cmd_cab_for_ss cab; 3378 3379 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3380 3381 /** 3382 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3383 */ 3384 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3385 3386 /** 3387 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3388 */ 3389 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3390 3391 /** 3392 * Definition of DMUB_CMD__PANEL_CNTL commands. 3393 */ 3394 struct dmub_rb_cmd_panel_cntl panel_cntl; 3395 /** 3396 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3397 */ 3398 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3399 3400 /** 3401 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3402 */ 3403 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3404 3405 /** 3406 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3407 */ 3408 struct dmub_rb_cmd_abm_set_level abm_set_level; 3409 3410 /** 3411 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3412 */ 3413 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3414 3415 /** 3416 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3417 */ 3418 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3419 3420 /** 3421 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3422 */ 3423 struct dmub_rb_cmd_abm_init_config abm_init_config; 3424 3425 /** 3426 * Definition of a DMUB_CMD__ABM_PAUSE command. 3427 */ 3428 struct dmub_rb_cmd_abm_pause abm_pause; 3429 3430 /** 3431 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3432 */ 3433 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3434 3435 /** 3436 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3437 */ 3438 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3439 3440 /** 3441 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3442 */ 3443 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3444 3445 /** 3446 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3447 */ 3448 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3449 struct dmub_rb_cmd_drr_update drr_update; 3450 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3451 3452 /** 3453 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3454 */ 3455 struct dmub_rb_cmd_lvtma_control lvtma_control; 3456 /** 3457 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3458 */ 3459 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3460 /** 3461 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3462 */ 3463 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3464 /** 3465 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3466 */ 3467 struct dmub_rb_cmd_set_config_access set_config_access; 3468 /** 3469 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3470 */ 3471 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3472 /** 3473 * Definition of a DMUB_CMD__EDID_CEA command. 3474 */ 3475 struct dmub_rb_cmd_edid_cea edid_cea; 3476 /** 3477 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3478 */ 3479 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3480 3481 /** 3482 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3483 */ 3484 struct dmub_rb_cmd_query_hpd_state query_hpd; 3485 /** 3486 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3487 */ 3488 struct dmub_rb_cmd_secure_display secure_display; 3489 3490 /** 3491 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3492 */ 3493 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3494 }; 3495 3496 /** 3497 * union dmub_rb_out_cmd - Outbox command 3498 */ 3499 union dmub_rb_out_cmd { 3500 /** 3501 * Parameters common to every command. 3502 */ 3503 struct dmub_rb_cmd_common cmd_common; 3504 /** 3505 * AUX reply command. 3506 */ 3507 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3508 /** 3509 * HPD notify command. 3510 */ 3511 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3512 /** 3513 * SET_CONFIG reply command. 3514 */ 3515 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3516 /** 3517 * DPIA notification command. 3518 */ 3519 struct dmub_rb_cmd_dpia_notification dpia_notification; 3520 }; 3521 #pragma pack(pop) 3522 3523 3524 //============================================================================== 3525 //</DMUB_CMD>=================================================================== 3526 //============================================================================== 3527 //< DMUB_RB>==================================================================== 3528 //============================================================================== 3529 3530 #if defined(__cplusplus) 3531 extern "C" { 3532 #endif 3533 3534 /** 3535 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3536 */ 3537 struct dmub_rb_init_params { 3538 void *ctx; /**< Caller provided context pointer */ 3539 void *base_address; /**< CPU base address for ring's data */ 3540 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3541 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3542 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3543 }; 3544 3545 /** 3546 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3547 */ 3548 struct dmub_rb { 3549 void *base_address; /**< CPU address for the ring's data */ 3550 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3551 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3552 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3553 3554 void *ctx; /**< Caller provided context pointer */ 3555 void *dmub; /**< Pointer to the DMUB interface */ 3556 }; 3557 3558 /** 3559 * @brief Checks if the ringbuffer is empty. 3560 * 3561 * @param rb DMUB Ringbuffer 3562 * @return true if empty 3563 * @return false otherwise 3564 */ 3565 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3566 { 3567 return (rb->wrpt == rb->rptr); 3568 } 3569 3570 /** 3571 * @brief Checks if the ringbuffer is full 3572 * 3573 * @param rb DMUB Ringbuffer 3574 * @return true if full 3575 * @return false otherwise 3576 */ 3577 static inline bool dmub_rb_full(struct dmub_rb *rb) 3578 { 3579 uint32_t data_count; 3580 3581 if (rb->wrpt >= rb->rptr) 3582 data_count = rb->wrpt - rb->rptr; 3583 else 3584 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3585 3586 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3587 } 3588 3589 /** 3590 * @brief Pushes a command into the ringbuffer 3591 * 3592 * @param rb DMUB ringbuffer 3593 * @param cmd The command to push 3594 * @return true if the ringbuffer was not full 3595 * @return false otherwise 3596 */ 3597 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3598 const union dmub_rb_cmd *cmd) 3599 { 3600 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3601 const uint64_t *src = (const uint64_t *)cmd; 3602 uint8_t i; 3603 3604 if (dmub_rb_full(rb)) 3605 return false; 3606 3607 // copying data 3608 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3609 *dst++ = *src++; 3610 3611 rb->wrpt += DMUB_RB_CMD_SIZE; 3612 3613 if (rb->wrpt >= rb->capacity) 3614 rb->wrpt %= rb->capacity; 3615 3616 return true; 3617 } 3618 3619 /** 3620 * @brief Pushes a command into the DMUB outbox ringbuffer 3621 * 3622 * @param rb DMUB outbox ringbuffer 3623 * @param cmd Outbox command 3624 * @return true if not full 3625 * @return false otherwise 3626 */ 3627 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3628 const union dmub_rb_out_cmd *cmd) 3629 { 3630 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3631 const uint8_t *src = (const uint8_t *)cmd; 3632 3633 if (dmub_rb_full(rb)) 3634 return false; 3635 3636 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3637 3638 rb->wrpt += DMUB_RB_CMD_SIZE; 3639 3640 if (rb->wrpt >= rb->capacity) 3641 rb->wrpt %= rb->capacity; 3642 3643 return true; 3644 } 3645 3646 /** 3647 * @brief Returns the next unprocessed command in the ringbuffer. 3648 * 3649 * @param rb DMUB ringbuffer 3650 * @param cmd The command to return 3651 * @return true if not empty 3652 * @return false otherwise 3653 */ 3654 static inline bool dmub_rb_front(struct dmub_rb *rb, 3655 union dmub_rb_cmd **cmd) 3656 { 3657 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3658 3659 if (dmub_rb_empty(rb)) 3660 return false; 3661 3662 *cmd = (union dmub_rb_cmd *)rb_cmd; 3663 3664 return true; 3665 } 3666 3667 /** 3668 * @brief Determines the next ringbuffer offset. 3669 * 3670 * @param rb DMUB inbox ringbuffer 3671 * @param num_cmds Number of commands 3672 * @param next_rptr The next offset in the ringbuffer 3673 */ 3674 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3675 uint32_t num_cmds, 3676 uint32_t *next_rptr) 3677 { 3678 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3679 3680 if (*next_rptr >= rb->capacity) 3681 *next_rptr %= rb->capacity; 3682 } 3683 3684 /** 3685 * @brief Returns a pointer to a command in the inbox. 3686 * 3687 * @param rb DMUB inbox ringbuffer 3688 * @param cmd The inbox command to return 3689 * @param rptr The ringbuffer offset 3690 * @return true if not empty 3691 * @return false otherwise 3692 */ 3693 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3694 union dmub_rb_cmd **cmd, 3695 uint32_t rptr) 3696 { 3697 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3698 3699 if (dmub_rb_empty(rb)) 3700 return false; 3701 3702 *cmd = (union dmub_rb_cmd *)rb_cmd; 3703 3704 return true; 3705 } 3706 3707 /** 3708 * @brief Returns the next unprocessed command in the outbox. 3709 * 3710 * @param rb DMUB outbox ringbuffer 3711 * @param cmd The outbox command to return 3712 * @return true if not empty 3713 * @return false otherwise 3714 */ 3715 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3716 union dmub_rb_out_cmd *cmd) 3717 { 3718 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3719 uint64_t *dst = (uint64_t *)cmd; 3720 uint8_t i; 3721 3722 if (dmub_rb_empty(rb)) 3723 return false; 3724 3725 // copying data 3726 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3727 *dst++ = *src++; 3728 3729 return true; 3730 } 3731 3732 /** 3733 * @brief Removes the front entry in the ringbuffer. 3734 * 3735 * @param rb DMUB ringbuffer 3736 * @return true if the command was removed 3737 * @return false if there were no commands 3738 */ 3739 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3740 { 3741 if (dmub_rb_empty(rb)) 3742 return false; 3743 3744 rb->rptr += DMUB_RB_CMD_SIZE; 3745 3746 if (rb->rptr >= rb->capacity) 3747 rb->rptr %= rb->capacity; 3748 3749 return true; 3750 } 3751 3752 /** 3753 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3754 * 3755 * Avoids a race condition where DMCUB accesses memory while 3756 * there are still writes in flight to framebuffer. 3757 * 3758 * @param rb DMUB ringbuffer 3759 */ 3760 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3761 { 3762 uint32_t rptr = rb->rptr; 3763 uint32_t wptr = rb->wrpt; 3764 3765 while (rptr != wptr) { 3766 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3767 uint8_t i; 3768 3769 /* Don't remove this. 3770 * The contents need to actually be read from the ring buffer 3771 * for this function to be effective. 3772 */ 3773 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3774 (void)READ_ONCE(*data++); 3775 3776 rptr += DMUB_RB_CMD_SIZE; 3777 if (rptr >= rb->capacity) 3778 rptr %= rb->capacity; 3779 } 3780 } 3781 3782 /** 3783 * @brief Initializes a DMCUB ringbuffer 3784 * 3785 * @param rb DMUB ringbuffer 3786 * @param init_params initial configuration for the ringbuffer 3787 */ 3788 static inline void dmub_rb_init(struct dmub_rb *rb, 3789 struct dmub_rb_init_params *init_params) 3790 { 3791 rb->base_address = init_params->base_address; 3792 rb->capacity = init_params->capacity; 3793 rb->rptr = init_params->read_ptr; 3794 rb->wrpt = init_params->write_ptr; 3795 } 3796 3797 /** 3798 * @brief Copies output data from in/out commands into the given command. 3799 * 3800 * @param rb DMUB ringbuffer 3801 * @param cmd Command to copy data into 3802 */ 3803 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3804 union dmub_rb_cmd *cmd) 3805 { 3806 // Copy rb entry back into command 3807 uint8_t *rd_ptr = (rb->rptr == 0) ? 3808 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3809 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3810 3811 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3812 } 3813 3814 #if defined(__cplusplus) 3815 } 3816 #endif 3817 3818 //============================================================================== 3819 //</DMUB_RB>==================================================================== 3820 //============================================================================== 3821 3822 #endif /* _DMUB_CMD_H_ */ 3823