1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Define max FPO streams as 4 for now. Current implementation today 99 * only supports 1, but could be more in the future. Reduce array 100 * size to ensure the command size remains less than 64 bytes if 101 * adding new fields. 102 */ 103 #define DMUB_MAX_FPO_STREAMS 4 104 105 /* Maximum number of streams on any ASIC. */ 106 #define DMUB_MAX_STREAMS 6 107 108 /* Maximum number of planes on any ASIC. */ 109 #define DMUB_MAX_PLANES 6 110 111 /* Trace buffer offset for entry */ 112 #define TRACE_BUFFER_ENTRY_OFFSET 16 113 114 /** 115 * Maximum number of dirty rects supported by FW. 116 */ 117 #define DMUB_MAX_DIRTY_RECTS 3 118 119 /** 120 * 121 * PSR control version legacy 122 */ 123 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 124 /** 125 * PSR control version with multi edp support 126 */ 127 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 128 129 130 /** 131 * ABM control version legacy 132 */ 133 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 134 135 /** 136 * ABM control version with multi edp support 137 */ 138 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 139 140 /** 141 * Physical framebuffer address location, 64-bit. 142 */ 143 #ifndef PHYSICAL_ADDRESS_LOC 144 #define PHYSICAL_ADDRESS_LOC union large_integer 145 #endif 146 147 /** 148 * OS/FW agnostic memcpy 149 */ 150 #ifndef dmub_memcpy 151 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 152 #endif 153 154 /** 155 * OS/FW agnostic memset 156 */ 157 #ifndef dmub_memset 158 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 159 #endif 160 161 #if defined(__cplusplus) 162 extern "C" { 163 #endif 164 165 /** 166 * OS/FW agnostic udelay 167 */ 168 #ifndef dmub_udelay 169 #define dmub_udelay(microseconds) udelay(microseconds) 170 #endif 171 172 #pragma pack(push, 1) 173 /** 174 * union dmub_addr - DMUB physical/virtual 64-bit address. 175 */ 176 union dmub_addr { 177 struct { 178 uint32_t low_part; /**< Lower 32 bits */ 179 uint32_t high_part; /**< Upper 32 bits */ 180 } u; /*<< Low/high bit access */ 181 uint64_t quad_part; /*<< 64 bit address */ 182 }; 183 #pragma pack(pop) 184 185 /** 186 * Dirty rect definition. 187 */ 188 struct dmub_rect { 189 /** 190 * Dirty rect x offset. 191 */ 192 uint32_t x; 193 194 /** 195 * Dirty rect y offset. 196 */ 197 uint32_t y; 198 199 /** 200 * Dirty rect width. 201 */ 202 uint32_t width; 203 204 /** 205 * Dirty rect height. 206 */ 207 uint32_t height; 208 }; 209 210 /** 211 * Flags that can be set by driver to change some PSR behaviour. 212 */ 213 union dmub_psr_debug_flags { 214 /** 215 * Debug flags. 216 */ 217 struct { 218 /** 219 * Enable visual confirm in FW. 220 */ 221 uint32_t visual_confirm : 1; 222 223 /** 224 * Force all selective updates to bw full frame updates. 225 */ 226 uint32_t force_full_frame_update : 1; 227 228 /** 229 * Use HW Lock Mgr object to do HW locking in FW. 230 */ 231 uint32_t use_hw_lock_mgr : 1; 232 233 /** 234 * Use TPS3 signal when restore main link. 235 */ 236 uint32_t force_wakeup_by_tps3 : 1; 237 238 /** 239 * Back to back flip, therefore cannot power down PHY 240 */ 241 uint32_t back_to_back_flip : 1; 242 243 } bitfields; 244 245 /** 246 * Union for debug flags. 247 */ 248 uint32_t u32All; 249 }; 250 251 /** 252 * DMUB visual confirm color 253 */ 254 struct dmub_feature_caps { 255 /** 256 * Max PSR version supported by FW. 257 */ 258 uint8_t psr; 259 uint8_t fw_assisted_mclk_switch; 260 uint8_t reserved[6]; 261 }; 262 263 struct dmub_visual_confirm_color { 264 /** 265 * Maximum 10 bits color value 266 */ 267 uint16_t color_r_cr; 268 uint16_t color_g_y; 269 uint16_t color_b_cb; 270 uint16_t panel_inst; 271 }; 272 273 #if defined(__cplusplus) 274 } 275 #endif 276 277 //============================================================================== 278 //</DMUB_TYPES>================================================================= 279 //============================================================================== 280 //< DMUB_META>================================================================== 281 //============================================================================== 282 #pragma pack(push, 1) 283 284 /* Magic value for identifying dmub_fw_meta_info */ 285 #define DMUB_FW_META_MAGIC 0x444D5542 286 287 /* Offset from the end of the file to the dmub_fw_meta_info */ 288 #define DMUB_FW_META_OFFSET 0x24 289 290 /** 291 * struct dmub_fw_meta_info - metadata associated with fw binary 292 * 293 * NOTE: This should be considered a stable API. Fields should 294 * not be repurposed or reordered. New fields should be 295 * added instead to extend the structure. 296 * 297 * @magic_value: magic value identifying DMUB firmware meta info 298 * @fw_region_size: size of the firmware state region 299 * @trace_buffer_size: size of the tracebuffer region 300 * @fw_version: the firmware version information 301 * @dal_fw: 1 if the firmware is DAL 302 */ 303 struct dmub_fw_meta_info { 304 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 305 uint32_t fw_region_size; /**< size of the firmware state region */ 306 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 307 uint32_t fw_version; /**< the firmware version information */ 308 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 309 uint8_t reserved[3]; /**< padding bits */ 310 }; 311 312 /** 313 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 314 */ 315 union dmub_fw_meta { 316 struct dmub_fw_meta_info info; /**< metadata info */ 317 uint8_t reserved[64]; /**< padding bits */ 318 }; 319 320 #pragma pack(pop) 321 322 //============================================================================== 323 //< DMUB Trace Buffer>================================================================ 324 //============================================================================== 325 /** 326 * dmub_trace_code_t - firmware trace code, 32-bits 327 */ 328 typedef uint32_t dmub_trace_code_t; 329 330 /** 331 * struct dmcub_trace_buf_entry - Firmware trace entry 332 */ 333 struct dmcub_trace_buf_entry { 334 dmub_trace_code_t trace_code; /**< trace code for the event */ 335 uint32_t tick_count; /**< the tick count at time of trace */ 336 uint32_t param0; /**< trace defined parameter 0 */ 337 uint32_t param1; /**< trace defined parameter 1 */ 338 }; 339 340 //============================================================================== 341 //< DMUB_STATUS>================================================================ 342 //============================================================================== 343 344 /** 345 * DMCUB scratch registers can be used to determine firmware status. 346 * Current scratch register usage is as follows: 347 * 348 * SCRATCH0: FW Boot Status register 349 * SCRATCH5: LVTMA Status Register 350 * SCRATCH15: FW Boot Options register 351 */ 352 353 /** 354 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 355 */ 356 union dmub_fw_boot_status { 357 struct { 358 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 359 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 360 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 361 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 362 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 363 uint32_t reserved : 1; 364 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 365 366 } bits; /**< status bits */ 367 uint32_t all; /**< 32-bit access to status bits */ 368 }; 369 370 /** 371 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 372 */ 373 enum dmub_fw_boot_status_bit { 374 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 375 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 376 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 377 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 378 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 379 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 380 }; 381 382 /* Register bit definition for SCRATCH5 */ 383 union dmub_lvtma_status { 384 struct { 385 uint32_t psp_ok : 1; 386 uint32_t edp_on : 1; 387 uint32_t reserved : 30; 388 } bits; 389 uint32_t all; 390 }; 391 392 enum dmub_lvtma_status_bit { 393 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 394 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 395 }; 396 397 /** 398 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 399 */ 400 union dmub_fw_boot_options { 401 struct { 402 uint32_t pemu_env : 1; /**< 1 if PEMU */ 403 uint32_t fpga_env : 1; /**< 1 if FPGA */ 404 uint32_t optimized_init : 1; /**< 1 if optimized init */ 405 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 406 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 407 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 408 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 409 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 410 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 411 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 412 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 413 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 414 uint32_t power_optimization: 1; 415 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 416 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 417 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 418 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 419 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 420 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 421 uint32_t reserved : 14; /**< reserved */ 422 } bits; /**< boot bits */ 423 uint32_t all; /**< 32-bit access to bits */ 424 }; 425 426 enum dmub_fw_boot_options_bit { 427 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 428 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 429 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 430 }; 431 432 //============================================================================== 433 //</DMUB_STATUS>================================================================ 434 //============================================================================== 435 //< DMUB_VBIOS>================================================================= 436 //============================================================================== 437 438 /* 439 * enum dmub_cmd_vbios_type - VBIOS commands. 440 * 441 * Command IDs should be treated as stable ABI. 442 * Do not reuse or modify IDs. 443 */ 444 enum dmub_cmd_vbios_type { 445 /** 446 * Configures the DIG encoder. 447 */ 448 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 449 /** 450 * Controls the PHY. 451 */ 452 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 453 /** 454 * Sets the pixel clock/symbol clock. 455 */ 456 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 457 /** 458 * Enables or disables power gating. 459 */ 460 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 461 /** 462 * Controls embedded panels. 463 */ 464 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 465 /** 466 * Query DP alt status on a transmitter. 467 */ 468 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 469 /** 470 * Controls domain power gating 471 */ 472 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 473 }; 474 475 //============================================================================== 476 //</DMUB_VBIOS>================================================================= 477 //============================================================================== 478 //< DMUB_GPINT>================================================================= 479 //============================================================================== 480 481 /** 482 * The shifts and masks below may alternatively be used to format and read 483 * the command register bits. 484 */ 485 486 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 487 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 488 489 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 490 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 491 492 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 493 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 494 495 /** 496 * Command responses. 497 */ 498 499 /** 500 * Return response for DMUB_GPINT__STOP_FW command. 501 */ 502 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 503 504 /** 505 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 506 */ 507 union dmub_gpint_data_register { 508 struct { 509 uint32_t param : 16; /**< 16-bit parameter */ 510 uint32_t command_code : 12; /**< GPINT command */ 511 uint32_t status : 4; /**< Command status bit */ 512 } bits; /**< GPINT bit access */ 513 uint32_t all; /**< GPINT 32-bit access */ 514 }; 515 516 /* 517 * enum dmub_gpint_command - GPINT command to DMCUB FW 518 * 519 * Command IDs should be treated as stable ABI. 520 * Do not reuse or modify IDs. 521 */ 522 enum dmub_gpint_command { 523 /** 524 * Invalid command, ignored. 525 */ 526 DMUB_GPINT__INVALID_COMMAND = 0, 527 /** 528 * DESC: Queries the firmware version. 529 * RETURN: Firmware version. 530 */ 531 DMUB_GPINT__GET_FW_VERSION = 1, 532 /** 533 * DESC: Halts the firmware. 534 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 535 */ 536 DMUB_GPINT__STOP_FW = 2, 537 /** 538 * DESC: Get PSR state from FW. 539 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 540 */ 541 DMUB_GPINT__GET_PSR_STATE = 7, 542 /** 543 * DESC: Notifies DMCUB of the currently active streams. 544 * ARGS: Stream mask, 1 bit per active stream index. 545 */ 546 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 547 /** 548 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 549 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 550 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 551 * RETURN: PSR residency in milli-percent. 552 */ 553 DMUB_GPINT__PSR_RESIDENCY = 9, 554 555 /** 556 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 557 */ 558 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 559 }; 560 561 /** 562 * INBOX0 generic command definition 563 */ 564 union dmub_inbox0_cmd_common { 565 struct { 566 uint32_t command_code: 8; /**< INBOX0 command code */ 567 uint32_t param: 24; /**< 24-bit parameter */ 568 } bits; 569 uint32_t all; 570 }; 571 572 /** 573 * INBOX0 hw_lock command definition 574 */ 575 union dmub_inbox0_cmd_lock_hw { 576 struct { 577 uint32_t command_code: 8; 578 579 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 580 uint32_t hw_lock_client: 2; 581 582 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 583 uint32_t otg_inst: 3; 584 uint32_t opp_inst: 3; 585 uint32_t dig_inst: 3; 586 587 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 588 uint32_t lock_pipe: 1; 589 uint32_t lock_cursor: 1; 590 uint32_t lock_dig: 1; 591 uint32_t triple_buffer_lock: 1; 592 593 uint32_t lock: 1; /**< Lock */ 594 uint32_t should_release: 1; /**< Release */ 595 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 596 } bits; 597 uint32_t all; 598 }; 599 600 union dmub_inbox0_data_register { 601 union dmub_inbox0_cmd_common inbox0_cmd_common; 602 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 603 }; 604 605 enum dmub_inbox0_command { 606 /** 607 * DESC: Invalid command, ignored. 608 */ 609 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 610 /** 611 * DESC: Notification to acquire/release HW lock 612 * ARGS: 613 */ 614 DMUB_INBOX0_CMD__HW_LOCK = 1, 615 }; 616 //============================================================================== 617 //</DMUB_GPINT>================================================================= 618 //============================================================================== 619 //< DMUB_CMD>=================================================================== 620 //============================================================================== 621 622 /** 623 * Size in bytes of each DMUB command. 624 */ 625 #define DMUB_RB_CMD_SIZE 64 626 627 /** 628 * Maximum number of items in the DMUB ringbuffer. 629 */ 630 #define DMUB_RB_MAX_ENTRY 128 631 632 /** 633 * Ringbuffer size in bytes. 634 */ 635 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 636 637 /** 638 * REG_SET mask for reg offload. 639 */ 640 #define REG_SET_MASK 0xFFFF 641 642 /* 643 * enum dmub_cmd_type - DMUB inbox command. 644 * 645 * Command IDs should be treated as stable ABI. 646 * Do not reuse or modify IDs. 647 */ 648 enum dmub_cmd_type { 649 /** 650 * Invalid command. 651 */ 652 DMUB_CMD__NULL = 0, 653 /** 654 * Read modify write register sequence offload. 655 */ 656 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 657 /** 658 * Field update register sequence offload. 659 */ 660 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 661 /** 662 * Burst write sequence offload. 663 */ 664 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 665 /** 666 * Reg wait sequence offload. 667 */ 668 DMUB_CMD__REG_REG_WAIT = 4, 669 /** 670 * Workaround to avoid HUBP underflow during NV12 playback. 671 */ 672 DMUB_CMD__PLAT_54186_WA = 5, 673 /** 674 * Command type used to query FW feature caps. 675 */ 676 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 677 /** 678 * Command type used to get visual confirm color. 679 */ 680 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 681 /** 682 * Command type used for all PSR commands. 683 */ 684 DMUB_CMD__PSR = 64, 685 /** 686 * Command type used for all MALL commands. 687 */ 688 DMUB_CMD__MALL = 65, 689 /** 690 * Command type used for all ABM commands. 691 */ 692 DMUB_CMD__ABM = 66, 693 /** 694 * Command type used to update dirty rects in FW. 695 */ 696 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 697 /** 698 * Command type used to update cursor info in FW. 699 */ 700 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 701 /** 702 * Command type used for HW locking in FW. 703 */ 704 DMUB_CMD__HW_LOCK = 69, 705 /** 706 * Command type used to access DP AUX. 707 */ 708 DMUB_CMD__DP_AUX_ACCESS = 70, 709 /** 710 * Command type used for OUTBOX1 notification enable 711 */ 712 DMUB_CMD__OUTBOX1_ENABLE = 71, 713 714 /** 715 * Command type used for all idle optimization commands. 716 */ 717 DMUB_CMD__IDLE_OPT = 72, 718 /** 719 * Command type used for all clock manager commands. 720 */ 721 DMUB_CMD__CLK_MGR = 73, 722 /** 723 * Command type used for all panel control commands. 724 */ 725 DMUB_CMD__PANEL_CNTL = 74, 726 /** 727 * Command type used for <TODO:description> 728 */ 729 DMUB_CMD__CAB_FOR_SS = 75, 730 731 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 732 733 /** 734 * Command type used for interfacing with DPIA. 735 */ 736 DMUB_CMD__DPIA = 77, 737 /** 738 * Command type used for EDID CEA parsing 739 */ 740 DMUB_CMD__EDID_CEA = 79, 741 /** 742 * Command type used for getting usbc cable ID 743 */ 744 DMUB_CMD_GET_USBC_CABLE_ID = 81, 745 /** 746 * Command type used to query HPD state. 747 */ 748 DMUB_CMD__QUERY_HPD_STATE = 82, 749 /** 750 * Command type used for all VBIOS interface commands. 751 */ 752 753 /** 754 * Command type used for all SECURE_DISPLAY commands. 755 */ 756 DMUB_CMD__SECURE_DISPLAY = 85, 757 758 /** 759 * Command type used to set DPIA HPD interrupt state 760 */ 761 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 762 763 DMUB_CMD__VBIOS = 128, 764 }; 765 766 /** 767 * enum dmub_out_cmd_type - DMUB outbox commands. 768 */ 769 enum dmub_out_cmd_type { 770 /** 771 * Invalid outbox command, ignored. 772 */ 773 DMUB_OUT_CMD__NULL = 0, 774 /** 775 * Command type used for DP AUX Reply data notification 776 */ 777 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 778 /** 779 * Command type used for DP HPD event notification 780 */ 781 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 782 /** 783 * Command type used for SET_CONFIG Reply notification 784 */ 785 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 786 /** 787 * Command type used for USB4 DPIA notification 788 */ 789 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 790 }; 791 792 /* DMUB_CMD__DPIA command sub-types. */ 793 enum dmub_cmd_dpia_type { 794 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 795 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 796 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 797 }; 798 799 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 800 enum dmub_cmd_dpia_notification_type { 801 DPIA_NOTIFY__BW_ALLOCATION = 0, 802 }; 803 804 #pragma pack(push, 1) 805 806 /** 807 * struct dmub_cmd_header - Common command header fields. 808 */ 809 struct dmub_cmd_header { 810 unsigned int type : 8; /**< command type */ 811 unsigned int sub_type : 8; /**< command sub type */ 812 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 813 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 814 unsigned int reserved0 : 6; /**< reserved bits */ 815 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 816 unsigned int reserved1 : 2; /**< reserved bits */ 817 }; 818 819 /* 820 * struct dmub_cmd_read_modify_write_sequence - Read modify write 821 * 822 * 60 payload bytes can hold up to 5 sets of read modify writes, 823 * each take 3 dwords. 824 * 825 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 826 * 827 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 828 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 829 */ 830 struct dmub_cmd_read_modify_write_sequence { 831 uint32_t addr; /**< register address */ 832 uint32_t modify_mask; /**< modify mask */ 833 uint32_t modify_value; /**< modify value */ 834 }; 835 836 /** 837 * Maximum number of ops in read modify write sequence. 838 */ 839 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 840 841 /** 842 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 843 */ 844 struct dmub_rb_cmd_read_modify_write { 845 struct dmub_cmd_header header; /**< command header */ 846 /** 847 * Read modify write sequence. 848 */ 849 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 850 }; 851 852 /* 853 * Update a register with specified masks and values sequeunce 854 * 855 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 856 * 857 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 858 * 859 * 860 * USE CASE: 861 * 1. auto-increment register where additional read would update pointer and produce wrong result 862 * 2. toggle a bit without read in the middle 863 */ 864 865 struct dmub_cmd_reg_field_update_sequence { 866 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 867 uint32_t modify_value; /**< value to update with */ 868 }; 869 870 /** 871 * Maximum number of ops in field update sequence. 872 */ 873 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 874 875 /** 876 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 877 */ 878 struct dmub_rb_cmd_reg_field_update_sequence { 879 struct dmub_cmd_header header; /**< command header */ 880 uint32_t addr; /**< register address */ 881 /** 882 * Field update sequence. 883 */ 884 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 885 }; 886 887 888 /** 889 * Maximum number of burst write values. 890 */ 891 #define DMUB_BURST_WRITE_VALUES__MAX 14 892 893 /* 894 * struct dmub_rb_cmd_burst_write - Burst write 895 * 896 * support use case such as writing out LUTs. 897 * 898 * 60 payload bytes can hold up to 14 values to write to given address 899 * 900 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 901 */ 902 struct dmub_rb_cmd_burst_write { 903 struct dmub_cmd_header header; /**< command header */ 904 uint32_t addr; /**< register start address */ 905 /** 906 * Burst write register values. 907 */ 908 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 909 }; 910 911 /** 912 * struct dmub_rb_cmd_common - Common command header 913 */ 914 struct dmub_rb_cmd_common { 915 struct dmub_cmd_header header; /**< command header */ 916 /** 917 * Padding to RB_CMD_SIZE 918 */ 919 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 920 }; 921 922 /** 923 * struct dmub_cmd_reg_wait_data - Register wait data 924 */ 925 struct dmub_cmd_reg_wait_data { 926 uint32_t addr; /**< Register address */ 927 uint32_t mask; /**< Mask for register bits */ 928 uint32_t condition_field_value; /**< Value to wait for */ 929 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 930 }; 931 932 /** 933 * struct dmub_rb_cmd_reg_wait - Register wait command 934 */ 935 struct dmub_rb_cmd_reg_wait { 936 struct dmub_cmd_header header; /**< Command header */ 937 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 938 }; 939 940 /** 941 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 942 * 943 * Reprograms surface parameters to avoid underflow. 944 */ 945 struct dmub_cmd_PLAT_54186_wa { 946 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 947 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 948 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 949 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 950 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 951 struct { 952 uint8_t hubp_inst : 4; /**< HUBP instance */ 953 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 954 uint8_t immediate :1; /**< Immediate flip */ 955 uint8_t vmid : 4; /**< VMID */ 956 uint8_t grph_stereo : 1; /**< 1 if stereo */ 957 uint32_t reserved : 21; /**< Reserved */ 958 } flip_params; /**< Pageflip parameters */ 959 uint32_t reserved[9]; /**< Reserved bits */ 960 }; 961 962 /** 963 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 964 */ 965 struct dmub_rb_cmd_PLAT_54186_wa { 966 struct dmub_cmd_header header; /**< Command header */ 967 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 968 }; 969 970 /** 971 * struct dmub_rb_cmd_mall - MALL command data. 972 */ 973 struct dmub_rb_cmd_mall { 974 struct dmub_cmd_header header; /**< Common command header */ 975 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 976 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 977 uint32_t tmr_delay; /**< Timer delay */ 978 uint32_t tmr_scale; /**< Timer scale */ 979 uint16_t cursor_width; /**< Cursor width in pixels */ 980 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 981 uint16_t cursor_height; /**< Cursor height in pixels */ 982 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 983 uint8_t debug_bits; /**< Debug bits */ 984 985 uint8_t reserved1; /**< Reserved bits */ 986 uint8_t reserved2; /**< Reserved bits */ 987 }; 988 989 /** 990 * enum dmub_cmd_cab_type - TODO: 991 */ 992 enum dmub_cmd_cab_type { 993 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 994 DMUB_CMD__CAB_NO_DCN_REQ = 1, 995 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 996 }; 997 998 /** 999 * struct dmub_rb_cmd_cab_for_ss - TODO: 1000 */ 1001 struct dmub_rb_cmd_cab_for_ss { 1002 struct dmub_cmd_header header; 1003 uint8_t cab_alloc_ways; /* total number of ways */ 1004 uint8_t debug_bits; /* debug bits */ 1005 }; 1006 1007 enum mclk_switch_mode { 1008 NONE = 0, 1009 FPO = 1, 1010 SUBVP = 2, 1011 VBLANK = 3, 1012 }; 1013 1014 /* Per pipe struct which stores the MCLK switch mode 1015 * data to be sent to DMUB. 1016 * Named "v2" for now -- once FPO and SUBVP are fully merged 1017 * the type name can be updated 1018 */ 1019 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1020 union { 1021 struct { 1022 uint32_t pix_clk_100hz; 1023 uint16_t main_vblank_start; 1024 uint16_t main_vblank_end; 1025 uint16_t mall_region_lines; 1026 uint16_t prefetch_lines; 1027 uint16_t prefetch_to_mall_start_lines; 1028 uint16_t processing_delay_lines; 1029 uint16_t htotal; // required to calculate line time for multi-display cases 1030 uint16_t vtotal; 1031 uint8_t main_pipe_index; 1032 uint8_t phantom_pipe_index; 1033 /* Since the microschedule is calculated in terms of OTG lines, 1034 * include any scaling factors to make sure when we get accurate 1035 * conversion when programming MALL_START_LINE (which is in terms 1036 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1037 * is 1/2 (numerator = 1, denominator = 2). 1038 */ 1039 uint8_t scale_factor_numerator; 1040 uint8_t scale_factor_denominator; 1041 uint8_t is_drr; 1042 uint8_t main_split_pipe_index; 1043 uint8_t phantom_split_pipe_index; 1044 } subvp_data; 1045 1046 struct { 1047 uint32_t pix_clk_100hz; 1048 uint16_t vblank_start; 1049 uint16_t vblank_end; 1050 uint16_t vstartup_start; 1051 uint16_t vtotal; 1052 uint16_t htotal; 1053 uint8_t vblank_pipe_index; 1054 uint8_t padding[1]; 1055 struct { 1056 uint8_t drr_in_use; 1057 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1058 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1059 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1060 uint8_t use_ramping; // Use ramping or not 1061 uint8_t drr_vblank_start_margin; 1062 } drr_info; // DRR considered as part of SubVP + VBLANK case 1063 } vblank_data; 1064 } pipe_config; 1065 1066 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1067 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1068 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1069 */ 1070 uint8_t mode; // enum mclk_switch_mode 1071 }; 1072 1073 /** 1074 * Config data for Sub-VP and FPO 1075 * Named "v2" for now -- once FPO and SUBVP are fully merged 1076 * the type name can be updated 1077 */ 1078 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1079 uint16_t watermark_a_cache; 1080 uint8_t vertical_int_margin_us; 1081 uint8_t pstate_allow_width_us; 1082 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1083 }; 1084 1085 /** 1086 * DMUB rb command definition for Sub-VP and FPO 1087 * Named "v2" for now -- once FPO and SUBVP are fully merged 1088 * the type name can be updated 1089 */ 1090 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1091 struct dmub_cmd_header header; 1092 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1093 }; 1094 1095 /** 1096 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1097 */ 1098 enum dmub_cmd_idle_opt_type { 1099 /** 1100 * DCN hardware restore. 1101 */ 1102 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1103 1104 /** 1105 * DCN hardware save. 1106 */ 1107 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1108 }; 1109 1110 /** 1111 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1112 */ 1113 struct dmub_rb_cmd_idle_opt_dcn_restore { 1114 struct dmub_cmd_header header; /**< header */ 1115 }; 1116 1117 /** 1118 * struct dmub_clocks - Clock update notification. 1119 */ 1120 struct dmub_clocks { 1121 uint32_t dispclk_khz; /**< dispclk kHz */ 1122 uint32_t dppclk_khz; /**< dppclk kHz */ 1123 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1124 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1125 }; 1126 1127 /** 1128 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1129 */ 1130 enum dmub_cmd_clk_mgr_type { 1131 /** 1132 * Notify DMCUB of clock update. 1133 */ 1134 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1135 }; 1136 1137 /** 1138 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1139 */ 1140 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1141 struct dmub_cmd_header header; /**< header */ 1142 struct dmub_clocks clocks; /**< clock data */ 1143 }; 1144 1145 /** 1146 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1147 */ 1148 struct dmub_cmd_digx_encoder_control_data { 1149 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1150 }; 1151 1152 /** 1153 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1154 */ 1155 struct dmub_rb_cmd_digx_encoder_control { 1156 struct dmub_cmd_header header; /**< header */ 1157 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1158 }; 1159 1160 /** 1161 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1162 */ 1163 struct dmub_cmd_set_pixel_clock_data { 1164 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1165 }; 1166 1167 /** 1168 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1169 */ 1170 struct dmub_rb_cmd_set_pixel_clock { 1171 struct dmub_cmd_header header; /**< header */ 1172 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1173 }; 1174 1175 /** 1176 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1177 */ 1178 struct dmub_cmd_enable_disp_power_gating_data { 1179 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1180 }; 1181 1182 /** 1183 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1184 */ 1185 struct dmub_rb_cmd_enable_disp_power_gating { 1186 struct dmub_cmd_header header; /**< header */ 1187 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1188 }; 1189 1190 /** 1191 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1192 */ 1193 struct dmub_dig_transmitter_control_data_v1_7 { 1194 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1195 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1196 union { 1197 uint8_t digmode; /**< enum atom_encode_mode_def */ 1198 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1199 } mode_laneset; 1200 uint8_t lanenum; /**< Number of lanes */ 1201 union { 1202 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1203 } symclk_units; 1204 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1205 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1206 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1207 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1208 uint8_t reserved1; /**< For future use */ 1209 uint8_t reserved2[3]; /**< For future use */ 1210 uint32_t reserved3[11]; /**< For future use */ 1211 }; 1212 1213 /** 1214 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1215 */ 1216 union dmub_cmd_dig1_transmitter_control_data { 1217 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1218 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1219 }; 1220 1221 /** 1222 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1223 */ 1224 struct dmub_rb_cmd_dig1_transmitter_control { 1225 struct dmub_cmd_header header; /**< header */ 1226 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1227 }; 1228 1229 /** 1230 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1231 */ 1232 struct dmub_rb_cmd_domain_control_data { 1233 uint8_t inst : 6; /**< DOMAIN instance to control */ 1234 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1235 uint8_t reserved[3]; /**< Reserved for future use */ 1236 }; 1237 1238 /** 1239 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1240 */ 1241 struct dmub_rb_cmd_domain_control { 1242 struct dmub_cmd_header header; /**< header */ 1243 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1244 }; 1245 1246 /** 1247 * DPIA tunnel command parameters. 1248 */ 1249 struct dmub_cmd_dig_dpia_control_data { 1250 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1251 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1252 union { 1253 uint8_t digmode; /** enum atom_encode_mode_def */ 1254 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1255 } mode_laneset; 1256 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1257 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1258 uint8_t hpdsel; /** =0: HPD is not assigned */ 1259 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1260 uint8_t dpia_id; /** Index of DPIA */ 1261 uint8_t fec_rdy : 1; 1262 uint8_t reserved : 7; 1263 uint32_t reserved1; 1264 }; 1265 1266 /** 1267 * DMUB command for DPIA tunnel control. 1268 */ 1269 struct dmub_rb_cmd_dig1_dpia_control { 1270 struct dmub_cmd_header header; 1271 struct dmub_cmd_dig_dpia_control_data dpia_control; 1272 }; 1273 1274 /** 1275 * SET_CONFIG Command Payload 1276 */ 1277 struct set_config_cmd_payload { 1278 uint8_t msg_type; /* set config message type */ 1279 uint8_t msg_data; /* set config message data */ 1280 }; 1281 1282 /** 1283 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1284 */ 1285 struct dmub_cmd_set_config_control_data { 1286 struct set_config_cmd_payload cmd_pkt; 1287 uint8_t instance; /* DPIA instance */ 1288 uint8_t immed_status; /* Immediate status returned in case of error */ 1289 }; 1290 1291 /** 1292 * DMUB command structure for SET_CONFIG command. 1293 */ 1294 struct dmub_rb_cmd_set_config_access { 1295 struct dmub_cmd_header header; /* header */ 1296 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1297 }; 1298 1299 /** 1300 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1301 */ 1302 struct dmub_cmd_mst_alloc_slots_control_data { 1303 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1304 uint8_t instance; /* DPIA instance */ 1305 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1306 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1307 }; 1308 1309 /** 1310 * DMUB command structure for SET_ command. 1311 */ 1312 struct dmub_rb_cmd_set_mst_alloc_slots { 1313 struct dmub_cmd_header header; /* header */ 1314 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1315 }; 1316 1317 /** 1318 * DMUB command structure for DPIA HPD int enable control. 1319 */ 1320 struct dmub_rb_cmd_dpia_hpd_int_enable { 1321 struct dmub_cmd_header header; /* header */ 1322 uint32_t enable; /* dpia hpd interrupt enable */ 1323 }; 1324 1325 /** 1326 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1327 */ 1328 struct dmub_rb_cmd_dpphy_init { 1329 struct dmub_cmd_header header; /**< header */ 1330 uint8_t reserved[60]; /**< reserved bits */ 1331 }; 1332 1333 /** 1334 * enum dp_aux_request_action - DP AUX request command listing. 1335 * 1336 * 4 AUX request command bits are shifted to high nibble. 1337 */ 1338 enum dp_aux_request_action { 1339 /** I2C-over-AUX write request */ 1340 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1341 /** I2C-over-AUX read request */ 1342 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1343 /** I2C-over-AUX write status request */ 1344 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1345 /** I2C-over-AUX write request with MOT=1 */ 1346 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1347 /** I2C-over-AUX read request with MOT=1 */ 1348 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1349 /** I2C-over-AUX write status request with MOT=1 */ 1350 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1351 /** Native AUX write request */ 1352 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1353 /** Native AUX read request */ 1354 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1355 }; 1356 1357 /** 1358 * enum aux_return_code_type - DP AUX process return code listing. 1359 */ 1360 enum aux_return_code_type { 1361 /** AUX process succeeded */ 1362 AUX_RET_SUCCESS = 0, 1363 /** AUX process failed with unknown reason */ 1364 AUX_RET_ERROR_UNKNOWN, 1365 /** AUX process completed with invalid reply */ 1366 AUX_RET_ERROR_INVALID_REPLY, 1367 /** AUX process timed out */ 1368 AUX_RET_ERROR_TIMEOUT, 1369 /** HPD was low during AUX process */ 1370 AUX_RET_ERROR_HPD_DISCON, 1371 /** Failed to acquire AUX engine */ 1372 AUX_RET_ERROR_ENGINE_ACQUIRE, 1373 /** AUX request not supported */ 1374 AUX_RET_ERROR_INVALID_OPERATION, 1375 /** AUX process not available */ 1376 AUX_RET_ERROR_PROTOCOL_ERROR, 1377 }; 1378 1379 /** 1380 * enum aux_channel_type - DP AUX channel type listing. 1381 */ 1382 enum aux_channel_type { 1383 /** AUX thru Legacy DP AUX */ 1384 AUX_CHANNEL_LEGACY_DDC, 1385 /** AUX thru DPIA DP tunneling */ 1386 AUX_CHANNEL_DPIA 1387 }; 1388 1389 /** 1390 * struct aux_transaction_parameters - DP AUX request transaction data 1391 */ 1392 struct aux_transaction_parameters { 1393 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1394 uint8_t action; /**< enum dp_aux_request_action */ 1395 uint8_t length; /**< DP AUX request data length */ 1396 uint8_t reserved; /**< For future use */ 1397 uint32_t address; /**< DP AUX address */ 1398 uint8_t data[16]; /**< DP AUX write data */ 1399 }; 1400 1401 /** 1402 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1403 */ 1404 struct dmub_cmd_dp_aux_control_data { 1405 uint8_t instance; /**< AUX instance or DPIA instance */ 1406 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1407 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1408 uint8_t reserved0; /**< For future use */ 1409 uint16_t timeout; /**< timeout time in us */ 1410 uint16_t reserved1; /**< For future use */ 1411 enum aux_channel_type type; /**< enum aux_channel_type */ 1412 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1413 }; 1414 1415 /** 1416 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1417 */ 1418 struct dmub_rb_cmd_dp_aux_access { 1419 /** 1420 * Command header. 1421 */ 1422 struct dmub_cmd_header header; 1423 /** 1424 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1425 */ 1426 struct dmub_cmd_dp_aux_control_data aux_control; 1427 }; 1428 1429 /** 1430 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1431 */ 1432 struct dmub_rb_cmd_outbox1_enable { 1433 /** 1434 * Command header. 1435 */ 1436 struct dmub_cmd_header header; 1437 /** 1438 * enable: 0x0 -> disable outbox1 notification (default value) 1439 * 0x1 -> enable outbox1 notification 1440 */ 1441 uint32_t enable; 1442 }; 1443 1444 /* DP AUX Reply command - OutBox Cmd */ 1445 /** 1446 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1447 */ 1448 struct aux_reply_data { 1449 /** 1450 * Aux cmd 1451 */ 1452 uint8_t command; 1453 /** 1454 * Aux reply data length (max: 16 bytes) 1455 */ 1456 uint8_t length; 1457 /** 1458 * Alignment only 1459 */ 1460 uint8_t pad[2]; 1461 /** 1462 * Aux reply data 1463 */ 1464 uint8_t data[16]; 1465 }; 1466 1467 /** 1468 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1469 */ 1470 struct aux_reply_control_data { 1471 /** 1472 * Reserved for future use 1473 */ 1474 uint32_t handle; 1475 /** 1476 * Aux Instance 1477 */ 1478 uint8_t instance; 1479 /** 1480 * Aux transaction result: definition in enum aux_return_code_type 1481 */ 1482 uint8_t result; 1483 /** 1484 * Alignment only 1485 */ 1486 uint16_t pad; 1487 }; 1488 1489 /** 1490 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1491 */ 1492 struct dmub_rb_cmd_dp_aux_reply { 1493 /** 1494 * Command header. 1495 */ 1496 struct dmub_cmd_header header; 1497 /** 1498 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1499 */ 1500 struct aux_reply_control_data control; 1501 /** 1502 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1503 */ 1504 struct aux_reply_data reply_data; 1505 }; 1506 1507 /* DP HPD Notify command - OutBox Cmd */ 1508 /** 1509 * DP HPD Type 1510 */ 1511 enum dp_hpd_type { 1512 /** 1513 * Normal DP HPD 1514 */ 1515 DP_HPD = 0, 1516 /** 1517 * DP HPD short pulse 1518 */ 1519 DP_IRQ 1520 }; 1521 1522 /** 1523 * DP HPD Status 1524 */ 1525 enum dp_hpd_status { 1526 /** 1527 * DP_HPD status low 1528 */ 1529 DP_HPD_UNPLUG = 0, 1530 /** 1531 * DP_HPD status high 1532 */ 1533 DP_HPD_PLUG 1534 }; 1535 1536 /** 1537 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1538 */ 1539 struct dp_hpd_data { 1540 /** 1541 * DP HPD instance 1542 */ 1543 uint8_t instance; 1544 /** 1545 * HPD type 1546 */ 1547 uint8_t hpd_type; 1548 /** 1549 * HPD status: only for type: DP_HPD to indicate status 1550 */ 1551 uint8_t hpd_status; 1552 /** 1553 * Alignment only 1554 */ 1555 uint8_t pad; 1556 }; 1557 1558 /** 1559 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1560 */ 1561 struct dmub_rb_cmd_dp_hpd_notify { 1562 /** 1563 * Command header. 1564 */ 1565 struct dmub_cmd_header header; 1566 /** 1567 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1568 */ 1569 struct dp_hpd_data hpd_data; 1570 }; 1571 1572 /** 1573 * Definition of a SET_CONFIG reply from DPOA. 1574 */ 1575 enum set_config_status { 1576 SET_CONFIG_PENDING = 0, 1577 SET_CONFIG_ACK_RECEIVED, 1578 SET_CONFIG_RX_TIMEOUT, 1579 SET_CONFIG_UNKNOWN_ERROR, 1580 }; 1581 1582 /** 1583 * Definition of a set_config reply 1584 */ 1585 struct set_config_reply_control_data { 1586 uint8_t instance; /* DPIA Instance */ 1587 uint8_t status; /* Set Config reply */ 1588 uint16_t pad; /* Alignment */ 1589 }; 1590 1591 /** 1592 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1593 */ 1594 struct dmub_rb_cmd_dp_set_config_reply { 1595 struct dmub_cmd_header header; 1596 struct set_config_reply_control_data set_config_reply_control; 1597 }; 1598 1599 /** 1600 * Definition of a DPIA notification header 1601 */ 1602 struct dpia_notification_header { 1603 uint8_t instance; /**< DPIA Instance */ 1604 uint8_t reserved[3]; 1605 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 1606 }; 1607 1608 /** 1609 * Definition of the common data struct of DPIA notification 1610 */ 1611 struct dpia_notification_common { 1612 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 1613 - sizeof(struct dpia_notification_header)]; 1614 }; 1615 1616 /** 1617 * Definition of a DPIA notification data 1618 */ 1619 struct dpia_bw_allocation_notify_data { 1620 union { 1621 struct { 1622 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 1623 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 1624 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 1625 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 1626 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 1627 uint16_t reserved: 11; /**< Reserved */ 1628 } bits; 1629 1630 uint16_t flags; 1631 }; 1632 1633 uint8_t cm_id; /**< CM ID */ 1634 uint8_t group_id; /**< Group ID */ 1635 uint8_t granularity; /**< BW Allocation Granularity */ 1636 uint8_t estimated_bw; /**< Estimated_BW */ 1637 uint8_t allocated_bw; /**< Allocated_BW */ 1638 uint8_t reserved; 1639 }; 1640 1641 /** 1642 * union dpia_notify_data_type - DPIA Notification in Outbox command 1643 */ 1644 union dpia_notification_data { 1645 /** 1646 * DPIA Notification for common data struct 1647 */ 1648 struct dpia_notification_common common_data; 1649 1650 /** 1651 * DPIA Notification for DP BW Allocation support 1652 */ 1653 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 1654 }; 1655 1656 /** 1657 * Definition of a DPIA notification payload 1658 */ 1659 struct dpia_notification_payload { 1660 struct dpia_notification_header header; 1661 union dpia_notification_data data; /**< DPIA notification payload data */ 1662 }; 1663 1664 /** 1665 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 1666 */ 1667 struct dmub_rb_cmd_dpia_notification { 1668 struct dmub_cmd_header header; /**< DPIA notification header */ 1669 struct dpia_notification_payload payload; /**< DPIA notification payload */ 1670 }; 1671 1672 /** 1673 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1674 */ 1675 struct dmub_cmd_hpd_state_query_data { 1676 uint8_t instance; /**< HPD instance or DPIA instance */ 1677 uint8_t result; /**< For returning HPD state */ 1678 uint16_t pad; /** < Alignment */ 1679 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1680 enum aux_return_code_type status; /**< for returning the status of command */ 1681 }; 1682 1683 /** 1684 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1685 */ 1686 struct dmub_rb_cmd_query_hpd_state { 1687 /** 1688 * Command header. 1689 */ 1690 struct dmub_cmd_header header; 1691 /** 1692 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1693 */ 1694 struct dmub_cmd_hpd_state_query_data data; 1695 }; 1696 1697 /* 1698 * Command IDs should be treated as stable ABI. 1699 * Do not reuse or modify IDs. 1700 */ 1701 1702 /** 1703 * PSR command sub-types. 1704 */ 1705 enum dmub_cmd_psr_type { 1706 /** 1707 * Set PSR version support. 1708 */ 1709 DMUB_CMD__PSR_SET_VERSION = 0, 1710 /** 1711 * Copy driver-calculated parameters to PSR state. 1712 */ 1713 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1714 /** 1715 * Enable PSR. 1716 */ 1717 DMUB_CMD__PSR_ENABLE = 2, 1718 1719 /** 1720 * Disable PSR. 1721 */ 1722 DMUB_CMD__PSR_DISABLE = 3, 1723 1724 /** 1725 * Set PSR level. 1726 * PSR level is a 16-bit value dicated by driver that 1727 * will enable/disable different functionality. 1728 */ 1729 DMUB_CMD__PSR_SET_LEVEL = 4, 1730 1731 /** 1732 * Forces PSR enabled until an explicit PSR disable call. 1733 */ 1734 DMUB_CMD__PSR_FORCE_STATIC = 5, 1735 /** 1736 * Set vtotal in psr active for FreeSync PSR. 1737 */ 1738 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1739 /** 1740 * Set PSR power option 1741 */ 1742 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1743 }; 1744 1745 enum dmub_cmd_fams_type { 1746 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1747 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1748 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1749 /** 1750 * For SubVP set manual trigger in FW because it 1751 * triggers DRR_UPDATE_PENDING which SubVP relies 1752 * on (for any SubVP cases that use a DRR display) 1753 */ 1754 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1755 }; 1756 1757 /** 1758 * PSR versions. 1759 */ 1760 enum psr_version { 1761 /** 1762 * PSR version 1. 1763 */ 1764 PSR_VERSION_1 = 0, 1765 /** 1766 * Freesync PSR SU. 1767 */ 1768 PSR_VERSION_SU_1 = 1, 1769 /** 1770 * PSR not supported. 1771 */ 1772 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1773 }; 1774 1775 /** 1776 * enum dmub_cmd_mall_type - MALL commands 1777 */ 1778 enum dmub_cmd_mall_type { 1779 /** 1780 * Allows display refresh from MALL. 1781 */ 1782 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1783 /** 1784 * Disallows display refresh from MALL. 1785 */ 1786 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1787 /** 1788 * Cursor copy for MALL. 1789 */ 1790 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1791 /** 1792 * Controls DF requests. 1793 */ 1794 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1795 }; 1796 1797 /** 1798 * PHY Link rate for DP. 1799 */ 1800 enum phy_link_rate { 1801 /** 1802 * not supported. 1803 */ 1804 PHY_RATE_UNKNOWN = 0, 1805 /** 1806 * Rate_1 (RBR) - 1.62 Gbps/Lane 1807 */ 1808 PHY_RATE_162 = 1, 1809 /** 1810 * Rate_2 - 2.16 Gbps/Lane 1811 */ 1812 PHY_RATE_216 = 2, 1813 /** 1814 * Rate_3 - 2.43 Gbps/Lane 1815 */ 1816 PHY_RATE_243 = 3, 1817 /** 1818 * Rate_4 (HBR) - 2.70 Gbps/Lane 1819 */ 1820 PHY_RATE_270 = 4, 1821 /** 1822 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1823 */ 1824 PHY_RATE_324 = 5, 1825 /** 1826 * Rate_6 - 4.32 Gbps/Lane 1827 */ 1828 PHY_RATE_432 = 6, 1829 /** 1830 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1831 */ 1832 PHY_RATE_540 = 7, 1833 /** 1834 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1835 */ 1836 PHY_RATE_810 = 8, 1837 /** 1838 * UHBR10 - 10.0 Gbps/Lane 1839 */ 1840 PHY_RATE_1000 = 9, 1841 /** 1842 * UHBR13.5 - 13.5 Gbps/Lane 1843 */ 1844 PHY_RATE_1350 = 10, 1845 /** 1846 * UHBR10 - 20.0 Gbps/Lane 1847 */ 1848 PHY_RATE_2000 = 11, 1849 }; 1850 1851 /** 1852 * enum dmub_phy_fsm_state - PHY FSM states. 1853 * PHY FSM state to transit to during PSR enable/disable. 1854 */ 1855 enum dmub_phy_fsm_state { 1856 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1857 DMUB_PHY_FSM_RESET, 1858 DMUB_PHY_FSM_RESET_RELEASED, 1859 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1860 DMUB_PHY_FSM_INITIALIZED, 1861 DMUB_PHY_FSM_CALIBRATED, 1862 DMUB_PHY_FSM_CALIBRATED_LP, 1863 DMUB_PHY_FSM_CALIBRATED_PG, 1864 DMUB_PHY_FSM_POWER_DOWN, 1865 DMUB_PHY_FSM_PLL_EN, 1866 DMUB_PHY_FSM_TX_EN, 1867 DMUB_PHY_FSM_FAST_LP, 1868 }; 1869 1870 /** 1871 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1872 */ 1873 struct dmub_cmd_psr_copy_settings_data { 1874 /** 1875 * Flags that can be set by driver to change some PSR behaviour. 1876 */ 1877 union dmub_psr_debug_flags debug; 1878 /** 1879 * 16-bit value dicated by driver that will enable/disable different functionality. 1880 */ 1881 uint16_t psr_level; 1882 /** 1883 * DPP HW instance. 1884 */ 1885 uint8_t dpp_inst; 1886 /** 1887 * MPCC HW instance. 1888 * Not used in dmub fw, 1889 * dmub fw will get active opp by reading odm registers. 1890 */ 1891 uint8_t mpcc_inst; 1892 /** 1893 * OPP HW instance. 1894 * Not used in dmub fw, 1895 * dmub fw will get active opp by reading odm registers. 1896 */ 1897 uint8_t opp_inst; 1898 /** 1899 * OTG HW instance. 1900 */ 1901 uint8_t otg_inst; 1902 /** 1903 * DIG FE HW instance. 1904 */ 1905 uint8_t digfe_inst; 1906 /** 1907 * DIG BE HW instance. 1908 */ 1909 uint8_t digbe_inst; 1910 /** 1911 * DP PHY HW instance. 1912 */ 1913 uint8_t dpphy_inst; 1914 /** 1915 * AUX HW instance. 1916 */ 1917 uint8_t aux_inst; 1918 /** 1919 * Determines if SMU optimzations are enabled/disabled. 1920 */ 1921 uint8_t smu_optimizations_en; 1922 /** 1923 * Unused. 1924 * TODO: Remove. 1925 */ 1926 uint8_t frame_delay; 1927 /** 1928 * If RFB setup time is greater than the total VBLANK time, 1929 * it is not possible for the sink to capture the video frame 1930 * in the same frame the SDP is sent. In this case, 1931 * the frame capture indication bit should be set and an extra 1932 * static frame should be transmitted to the sink. 1933 */ 1934 uint8_t frame_cap_ind; 1935 /** 1936 * Granularity of Y offset supported by sink. 1937 */ 1938 uint8_t su_y_granularity; 1939 /** 1940 * Indicates whether sink should start capturing 1941 * immediately following active scan line, 1942 * or starting with the 2nd active scan line. 1943 */ 1944 uint8_t line_capture_indication; 1945 /** 1946 * Multi-display optimizations are implemented on certain ASICs. 1947 */ 1948 uint8_t multi_disp_optimizations_en; 1949 /** 1950 * The last possible line SDP may be transmitted without violating 1951 * the RFB setup time or entering the active video frame. 1952 */ 1953 uint16_t init_sdp_deadline; 1954 /** 1955 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1956 */ 1957 uint8_t rate_control_caps ; 1958 /* 1959 * Force PSRSU always doing full frame update 1960 */ 1961 uint8_t force_ffu_mode; 1962 /** 1963 * Length of each horizontal line in us. 1964 */ 1965 uint32_t line_time_in_us; 1966 /** 1967 * FEC enable status in driver 1968 */ 1969 uint8_t fec_enable_status; 1970 /** 1971 * FEC re-enable delay when PSR exit. 1972 * unit is 100us, range form 0~255(0xFF). 1973 */ 1974 uint8_t fec_enable_delay_in100us; 1975 /** 1976 * PSR control version. 1977 */ 1978 uint8_t cmd_version; 1979 /** 1980 * Panel Instance. 1981 * Panel instance to identify which psr_state to use 1982 * Currently the support is only for 0 or 1 1983 */ 1984 uint8_t panel_inst; 1985 /* 1986 * DSC enable status in driver 1987 */ 1988 uint8_t dsc_enable_status; 1989 /* 1990 * Use FSM state for PSR power up/down 1991 */ 1992 uint8_t use_phy_fsm; 1993 /** 1994 * frame delay for frame re-lock 1995 */ 1996 uint8_t relock_delay_frame_cnt; 1997 /** 1998 * Explicit padding to 2 byte boundary. 1999 */ 2000 uint8_t pad3; 2001 /** 2002 * DSC Slice height. 2003 */ 2004 uint16_t dsc_slice_height; 2005 /** 2006 * Explicit padding to 4 byte boundary. 2007 */ 2008 uint16_t pad; 2009 }; 2010 2011 /** 2012 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2013 */ 2014 struct dmub_rb_cmd_psr_copy_settings { 2015 /** 2016 * Command header. 2017 */ 2018 struct dmub_cmd_header header; 2019 /** 2020 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2021 */ 2022 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2023 }; 2024 2025 /** 2026 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2027 */ 2028 struct dmub_cmd_psr_set_level_data { 2029 /** 2030 * 16-bit value dicated by driver that will enable/disable different functionality. 2031 */ 2032 uint16_t psr_level; 2033 /** 2034 * PSR control version. 2035 */ 2036 uint8_t cmd_version; 2037 /** 2038 * Panel Instance. 2039 * Panel instance to identify which psr_state to use 2040 * Currently the support is only for 0 or 1 2041 */ 2042 uint8_t panel_inst; 2043 }; 2044 2045 /** 2046 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2047 */ 2048 struct dmub_rb_cmd_psr_set_level { 2049 /** 2050 * Command header. 2051 */ 2052 struct dmub_cmd_header header; 2053 /** 2054 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2055 */ 2056 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2057 }; 2058 2059 struct dmub_rb_cmd_psr_enable_data { 2060 /** 2061 * PSR control version. 2062 */ 2063 uint8_t cmd_version; 2064 /** 2065 * Panel Instance. 2066 * Panel instance to identify which psr_state to use 2067 * Currently the support is only for 0 or 1 2068 */ 2069 uint8_t panel_inst; 2070 /** 2071 * Phy state to enter. 2072 * Values to use are defined in dmub_phy_fsm_state 2073 */ 2074 uint8_t phy_fsm_state; 2075 /** 2076 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2077 * Set this using enum phy_link_rate. 2078 * This does not support HDMI/DP2 for now. 2079 */ 2080 uint8_t phy_rate; 2081 }; 2082 2083 /** 2084 * Definition of a DMUB_CMD__PSR_ENABLE command. 2085 * PSR enable/disable is controlled using the sub_type. 2086 */ 2087 struct dmub_rb_cmd_psr_enable { 2088 /** 2089 * Command header. 2090 */ 2091 struct dmub_cmd_header header; 2092 2093 struct dmub_rb_cmd_psr_enable_data data; 2094 }; 2095 2096 /** 2097 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2098 */ 2099 struct dmub_cmd_psr_set_version_data { 2100 /** 2101 * PSR version that FW should implement. 2102 */ 2103 enum psr_version version; 2104 /** 2105 * PSR control version. 2106 */ 2107 uint8_t cmd_version; 2108 /** 2109 * Panel Instance. 2110 * Panel instance to identify which psr_state to use 2111 * Currently the support is only for 0 or 1 2112 */ 2113 uint8_t panel_inst; 2114 /** 2115 * Explicit padding to 4 byte boundary. 2116 */ 2117 uint8_t pad[2]; 2118 }; 2119 2120 /** 2121 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2122 */ 2123 struct dmub_rb_cmd_psr_set_version { 2124 /** 2125 * Command header. 2126 */ 2127 struct dmub_cmd_header header; 2128 /** 2129 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2130 */ 2131 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2132 }; 2133 2134 struct dmub_cmd_psr_force_static_data { 2135 /** 2136 * PSR control version. 2137 */ 2138 uint8_t cmd_version; 2139 /** 2140 * Panel Instance. 2141 * Panel instance to identify which psr_state to use 2142 * Currently the support is only for 0 or 1 2143 */ 2144 uint8_t panel_inst; 2145 /** 2146 * Explicit padding to 4 byte boundary. 2147 */ 2148 uint8_t pad[2]; 2149 }; 2150 2151 /** 2152 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2153 */ 2154 struct dmub_rb_cmd_psr_force_static { 2155 /** 2156 * Command header. 2157 */ 2158 struct dmub_cmd_header header; 2159 /** 2160 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2161 */ 2162 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2163 }; 2164 2165 /** 2166 * PSR SU debug flags. 2167 */ 2168 union dmub_psr_su_debug_flags { 2169 /** 2170 * PSR SU debug flags. 2171 */ 2172 struct { 2173 /** 2174 * Update dirty rect in SW only. 2175 */ 2176 uint8_t update_dirty_rect_only : 1; 2177 /** 2178 * Reset the cursor/plane state before processing the call. 2179 */ 2180 uint8_t reset_state : 1; 2181 } bitfields; 2182 2183 /** 2184 * Union for debug flags. 2185 */ 2186 uint32_t u32All; 2187 }; 2188 2189 /** 2190 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2191 * This triggers a selective update for PSR SU. 2192 */ 2193 struct dmub_cmd_update_dirty_rect_data { 2194 /** 2195 * Dirty rects from OS. 2196 */ 2197 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2198 /** 2199 * PSR SU debug flags. 2200 */ 2201 union dmub_psr_su_debug_flags debug_flags; 2202 /** 2203 * OTG HW instance. 2204 */ 2205 uint8_t pipe_idx; 2206 /** 2207 * Number of dirty rects. 2208 */ 2209 uint8_t dirty_rect_count; 2210 /** 2211 * PSR control version. 2212 */ 2213 uint8_t cmd_version; 2214 /** 2215 * Panel Instance. 2216 * Panel instance to identify which psr_state to use 2217 * Currently the support is only for 0 or 1 2218 */ 2219 uint8_t panel_inst; 2220 }; 2221 2222 /** 2223 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2224 */ 2225 struct dmub_rb_cmd_update_dirty_rect { 2226 /** 2227 * Command header. 2228 */ 2229 struct dmub_cmd_header header; 2230 /** 2231 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2232 */ 2233 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2234 }; 2235 2236 /** 2237 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2238 */ 2239 union dmub_reg_cursor_control_cfg { 2240 struct { 2241 uint32_t cur_enable: 1; 2242 uint32_t reser0: 3; 2243 uint32_t cur_2x_magnify: 1; 2244 uint32_t reser1: 3; 2245 uint32_t mode: 3; 2246 uint32_t reser2: 5; 2247 uint32_t pitch: 2; 2248 uint32_t reser3: 6; 2249 uint32_t line_per_chunk: 5; 2250 uint32_t reser4: 3; 2251 } bits; 2252 uint32_t raw; 2253 }; 2254 struct dmub_cursor_position_cache_hubp { 2255 union dmub_reg_cursor_control_cfg cur_ctl; 2256 union dmub_reg_position_cfg { 2257 struct { 2258 uint32_t cur_x_pos: 16; 2259 uint32_t cur_y_pos: 16; 2260 } bits; 2261 uint32_t raw; 2262 } position; 2263 union dmub_reg_hot_spot_cfg { 2264 struct { 2265 uint32_t hot_x: 16; 2266 uint32_t hot_y: 16; 2267 } bits; 2268 uint32_t raw; 2269 } hot_spot; 2270 union dmub_reg_dst_offset_cfg { 2271 struct { 2272 uint32_t dst_x_offset: 13; 2273 uint32_t reserved: 19; 2274 } bits; 2275 uint32_t raw; 2276 } dst_offset; 2277 }; 2278 2279 union dmub_reg_cur0_control_cfg { 2280 struct { 2281 uint32_t cur0_enable: 1; 2282 uint32_t expansion_mode: 1; 2283 uint32_t reser0: 1; 2284 uint32_t cur0_rom_en: 1; 2285 uint32_t mode: 3; 2286 uint32_t reserved: 25; 2287 } bits; 2288 uint32_t raw; 2289 }; 2290 struct dmub_cursor_position_cache_dpp { 2291 union dmub_reg_cur0_control_cfg cur0_ctl; 2292 }; 2293 struct dmub_cursor_position_cfg { 2294 struct dmub_cursor_position_cache_hubp pHubp; 2295 struct dmub_cursor_position_cache_dpp pDpp; 2296 uint8_t pipe_idx; 2297 /* 2298 * Padding is required. To be 4 Bytes Aligned. 2299 */ 2300 uint8_t padding[3]; 2301 }; 2302 2303 struct dmub_cursor_attribute_cache_hubp { 2304 uint32_t SURFACE_ADDR_HIGH; 2305 uint32_t SURFACE_ADDR; 2306 union dmub_reg_cursor_control_cfg cur_ctl; 2307 union dmub_reg_cursor_size_cfg { 2308 struct { 2309 uint32_t width: 16; 2310 uint32_t height: 16; 2311 } bits; 2312 uint32_t raw; 2313 } size; 2314 union dmub_reg_cursor_settings_cfg { 2315 struct { 2316 uint32_t dst_y_offset: 8; 2317 uint32_t chunk_hdl_adjust: 2; 2318 uint32_t reserved: 22; 2319 } bits; 2320 uint32_t raw; 2321 } settings; 2322 }; 2323 struct dmub_cursor_attribute_cache_dpp { 2324 union dmub_reg_cur0_control_cfg cur0_ctl; 2325 }; 2326 struct dmub_cursor_attributes_cfg { 2327 struct dmub_cursor_attribute_cache_hubp aHubp; 2328 struct dmub_cursor_attribute_cache_dpp aDpp; 2329 }; 2330 2331 struct dmub_cmd_update_cursor_payload0 { 2332 /** 2333 * Cursor dirty rects. 2334 */ 2335 struct dmub_rect cursor_rect; 2336 /** 2337 * PSR SU debug flags. 2338 */ 2339 union dmub_psr_su_debug_flags debug_flags; 2340 /** 2341 * Cursor enable/disable. 2342 */ 2343 uint8_t enable; 2344 /** 2345 * OTG HW instance. 2346 */ 2347 uint8_t pipe_idx; 2348 /** 2349 * PSR control version. 2350 */ 2351 uint8_t cmd_version; 2352 /** 2353 * Panel Instance. 2354 * Panel instance to identify which psr_state to use 2355 * Currently the support is only for 0 or 1 2356 */ 2357 uint8_t panel_inst; 2358 /** 2359 * Cursor Position Register. 2360 * Registers contains Hubp & Dpp modules 2361 */ 2362 struct dmub_cursor_position_cfg position_cfg; 2363 }; 2364 2365 struct dmub_cmd_update_cursor_payload1 { 2366 struct dmub_cursor_attributes_cfg attribute_cfg; 2367 }; 2368 2369 union dmub_cmd_update_cursor_info_data { 2370 struct dmub_cmd_update_cursor_payload0 payload0; 2371 struct dmub_cmd_update_cursor_payload1 payload1; 2372 }; 2373 /** 2374 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2375 */ 2376 struct dmub_rb_cmd_update_cursor_info { 2377 /** 2378 * Command header. 2379 */ 2380 struct dmub_cmd_header header; 2381 /** 2382 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2383 */ 2384 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2385 }; 2386 2387 /** 2388 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2389 */ 2390 struct dmub_cmd_psr_set_vtotal_data { 2391 /** 2392 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2393 */ 2394 uint16_t psr_vtotal_idle; 2395 /** 2396 * PSR control version. 2397 */ 2398 uint8_t cmd_version; 2399 /** 2400 * Panel Instance. 2401 * Panel instance to identify which psr_state to use 2402 * Currently the support is only for 0 or 1 2403 */ 2404 uint8_t panel_inst; 2405 /* 2406 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2407 */ 2408 uint16_t psr_vtotal_su; 2409 /** 2410 * Explicit padding to 4 byte boundary. 2411 */ 2412 uint8_t pad2[2]; 2413 }; 2414 2415 /** 2416 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2417 */ 2418 struct dmub_rb_cmd_psr_set_vtotal { 2419 /** 2420 * Command header. 2421 */ 2422 struct dmub_cmd_header header; 2423 /** 2424 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2425 */ 2426 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2427 }; 2428 2429 /** 2430 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2431 */ 2432 struct dmub_cmd_psr_set_power_opt_data { 2433 /** 2434 * PSR control version. 2435 */ 2436 uint8_t cmd_version; 2437 /** 2438 * Panel Instance. 2439 * Panel instance to identify which psr_state to use 2440 * Currently the support is only for 0 or 1 2441 */ 2442 uint8_t panel_inst; 2443 /** 2444 * Explicit padding to 4 byte boundary. 2445 */ 2446 uint8_t pad[2]; 2447 /** 2448 * PSR power option 2449 */ 2450 uint32_t power_opt; 2451 }; 2452 2453 /** 2454 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2455 */ 2456 struct dmub_rb_cmd_psr_set_power_opt { 2457 /** 2458 * Command header. 2459 */ 2460 struct dmub_cmd_header header; 2461 /** 2462 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2463 */ 2464 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2465 }; 2466 2467 /** 2468 * Set of HW components that can be locked. 2469 * 2470 * Note: If updating with more HW components, fields 2471 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2472 */ 2473 union dmub_hw_lock_flags { 2474 /** 2475 * Set of HW components that can be locked. 2476 */ 2477 struct { 2478 /** 2479 * Lock/unlock OTG master update lock. 2480 */ 2481 uint8_t lock_pipe : 1; 2482 /** 2483 * Lock/unlock cursor. 2484 */ 2485 uint8_t lock_cursor : 1; 2486 /** 2487 * Lock/unlock global update lock. 2488 */ 2489 uint8_t lock_dig : 1; 2490 /** 2491 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2492 */ 2493 uint8_t triple_buffer_lock : 1; 2494 } bits; 2495 2496 /** 2497 * Union for HW Lock flags. 2498 */ 2499 uint8_t u8All; 2500 }; 2501 2502 /** 2503 * Instances of HW to be locked. 2504 * 2505 * Note: If updating with more HW components, fields 2506 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2507 */ 2508 struct dmub_hw_lock_inst_flags { 2509 /** 2510 * OTG HW instance for OTG master update lock. 2511 */ 2512 uint8_t otg_inst; 2513 /** 2514 * OPP instance for cursor lock. 2515 */ 2516 uint8_t opp_inst; 2517 /** 2518 * OTG HW instance for global update lock. 2519 * TODO: Remove, and re-use otg_inst. 2520 */ 2521 uint8_t dig_inst; 2522 /** 2523 * Explicit pad to 4 byte boundary. 2524 */ 2525 uint8_t pad; 2526 }; 2527 2528 /** 2529 * Clients that can acquire the HW Lock Manager. 2530 * 2531 * Note: If updating with more clients, fields in 2532 * dmub_inbox0_cmd_lock_hw must be updated to match. 2533 */ 2534 enum hw_lock_client { 2535 /** 2536 * Driver is the client of HW Lock Manager. 2537 */ 2538 HW_LOCK_CLIENT_DRIVER = 0, 2539 /** 2540 * PSR SU is the client of HW Lock Manager. 2541 */ 2542 HW_LOCK_CLIENT_PSR_SU = 1, 2543 /** 2544 * Invalid client. 2545 */ 2546 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2547 }; 2548 2549 /** 2550 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2551 */ 2552 struct dmub_cmd_lock_hw_data { 2553 /** 2554 * Specifies the client accessing HW Lock Manager. 2555 */ 2556 enum hw_lock_client client; 2557 /** 2558 * HW instances to be locked. 2559 */ 2560 struct dmub_hw_lock_inst_flags inst_flags; 2561 /** 2562 * Which components to be locked. 2563 */ 2564 union dmub_hw_lock_flags hw_locks; 2565 /** 2566 * Specifies lock/unlock. 2567 */ 2568 uint8_t lock; 2569 /** 2570 * HW can be unlocked separately from releasing the HW Lock Mgr. 2571 * This flag is set if the client wishes to release the object. 2572 */ 2573 uint8_t should_release; 2574 /** 2575 * Explicit padding to 4 byte boundary. 2576 */ 2577 uint8_t pad; 2578 }; 2579 2580 /** 2581 * Definition of a DMUB_CMD__HW_LOCK command. 2582 * Command is used by driver and FW. 2583 */ 2584 struct dmub_rb_cmd_lock_hw { 2585 /** 2586 * Command header. 2587 */ 2588 struct dmub_cmd_header header; 2589 /** 2590 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2591 */ 2592 struct dmub_cmd_lock_hw_data lock_hw_data; 2593 }; 2594 2595 /** 2596 * ABM command sub-types. 2597 */ 2598 enum dmub_cmd_abm_type { 2599 /** 2600 * Initialize parameters for ABM algorithm. 2601 * Data is passed through an indirect buffer. 2602 */ 2603 DMUB_CMD__ABM_INIT_CONFIG = 0, 2604 /** 2605 * Set OTG and panel HW instance. 2606 */ 2607 DMUB_CMD__ABM_SET_PIPE = 1, 2608 /** 2609 * Set user requested backklight level. 2610 */ 2611 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2612 /** 2613 * Set ABM operating/aggression level. 2614 */ 2615 DMUB_CMD__ABM_SET_LEVEL = 3, 2616 /** 2617 * Set ambient light level. 2618 */ 2619 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2620 /** 2621 * Enable/disable fractional duty cycle for backlight PWM. 2622 */ 2623 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2624 2625 /** 2626 * unregister vertical interrupt after steady state is reached 2627 */ 2628 DMUB_CMD__ABM_PAUSE = 6, 2629 }; 2630 2631 /** 2632 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2633 * Requirements: 2634 * - Padded explicitly to 32-bit boundary. 2635 * - Must ensure this structure matches the one on driver-side, 2636 * otherwise it won't be aligned. 2637 */ 2638 struct abm_config_table { 2639 /** 2640 * Gamma curve thresholds, used for crgb conversion. 2641 */ 2642 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2643 /** 2644 * Gamma curve offsets, used for crgb conversion. 2645 */ 2646 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2647 /** 2648 * Gamma curve slopes, used for crgb conversion. 2649 */ 2650 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2651 /** 2652 * Custom backlight curve thresholds. 2653 */ 2654 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2655 /** 2656 * Custom backlight curve offsets. 2657 */ 2658 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2659 /** 2660 * Ambient light thresholds. 2661 */ 2662 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2663 /** 2664 * Minimum programmable backlight. 2665 */ 2666 uint16_t min_abm_backlight; // 122B 2667 /** 2668 * Minimum reduction values. 2669 */ 2670 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2671 /** 2672 * Maximum reduction values. 2673 */ 2674 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2675 /** 2676 * Bright positive gain. 2677 */ 2678 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2679 /** 2680 * Dark negative gain. 2681 */ 2682 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2683 /** 2684 * Hybrid factor. 2685 */ 2686 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2687 /** 2688 * Contrast factor. 2689 */ 2690 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2691 /** 2692 * Deviation gain. 2693 */ 2694 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2695 /** 2696 * Minimum knee. 2697 */ 2698 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2699 /** 2700 * Maximum knee. 2701 */ 2702 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2703 /** 2704 * Unused. 2705 */ 2706 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2707 /** 2708 * Explicit padding to 4 byte boundary. 2709 */ 2710 uint8_t pad3[3]; // 229B 2711 /** 2712 * Backlight ramp reduction. 2713 */ 2714 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2715 /** 2716 * Backlight ramp start. 2717 */ 2718 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2719 }; 2720 2721 /** 2722 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2723 */ 2724 struct dmub_cmd_abm_set_pipe_data { 2725 /** 2726 * OTG HW instance. 2727 */ 2728 uint8_t otg_inst; 2729 2730 /** 2731 * Panel Control HW instance. 2732 */ 2733 uint8_t panel_inst; 2734 2735 /** 2736 * Controls how ABM will interpret a set pipe or set level command. 2737 */ 2738 uint8_t set_pipe_option; 2739 2740 /** 2741 * Unused. 2742 * TODO: Remove. 2743 */ 2744 uint8_t ramping_boundary; 2745 }; 2746 2747 /** 2748 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2749 */ 2750 struct dmub_rb_cmd_abm_set_pipe { 2751 /** 2752 * Command header. 2753 */ 2754 struct dmub_cmd_header header; 2755 2756 /** 2757 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2758 */ 2759 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2760 }; 2761 2762 /** 2763 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2764 */ 2765 struct dmub_cmd_abm_set_backlight_data { 2766 /** 2767 * Number of frames to ramp to backlight user level. 2768 */ 2769 uint32_t frame_ramp; 2770 2771 /** 2772 * Requested backlight level from user. 2773 */ 2774 uint32_t backlight_user_level; 2775 2776 /** 2777 * ABM control version. 2778 */ 2779 uint8_t version; 2780 2781 /** 2782 * Panel Control HW instance mask. 2783 * Bit 0 is Panel Control HW instance 0. 2784 * Bit 1 is Panel Control HW instance 1. 2785 */ 2786 uint8_t panel_mask; 2787 2788 /** 2789 * Explicit padding to 4 byte boundary. 2790 */ 2791 uint8_t pad[2]; 2792 }; 2793 2794 /** 2795 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2796 */ 2797 struct dmub_rb_cmd_abm_set_backlight { 2798 /** 2799 * Command header. 2800 */ 2801 struct dmub_cmd_header header; 2802 2803 /** 2804 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2805 */ 2806 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2807 }; 2808 2809 /** 2810 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2811 */ 2812 struct dmub_cmd_abm_set_level_data { 2813 /** 2814 * Set current ABM operating/aggression level. 2815 */ 2816 uint32_t level; 2817 2818 /** 2819 * ABM control version. 2820 */ 2821 uint8_t version; 2822 2823 /** 2824 * Panel Control HW instance mask. 2825 * Bit 0 is Panel Control HW instance 0. 2826 * Bit 1 is Panel Control HW instance 1. 2827 */ 2828 uint8_t panel_mask; 2829 2830 /** 2831 * Explicit padding to 4 byte boundary. 2832 */ 2833 uint8_t pad[2]; 2834 }; 2835 2836 /** 2837 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2838 */ 2839 struct dmub_rb_cmd_abm_set_level { 2840 /** 2841 * Command header. 2842 */ 2843 struct dmub_cmd_header header; 2844 2845 /** 2846 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2847 */ 2848 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2849 }; 2850 2851 /** 2852 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2853 */ 2854 struct dmub_cmd_abm_set_ambient_level_data { 2855 /** 2856 * Ambient light sensor reading from OS. 2857 */ 2858 uint32_t ambient_lux; 2859 2860 /** 2861 * ABM control version. 2862 */ 2863 uint8_t version; 2864 2865 /** 2866 * Panel Control HW instance mask. 2867 * Bit 0 is Panel Control HW instance 0. 2868 * Bit 1 is Panel Control HW instance 1. 2869 */ 2870 uint8_t panel_mask; 2871 2872 /** 2873 * Explicit padding to 4 byte boundary. 2874 */ 2875 uint8_t pad[2]; 2876 }; 2877 2878 /** 2879 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2880 */ 2881 struct dmub_rb_cmd_abm_set_ambient_level { 2882 /** 2883 * Command header. 2884 */ 2885 struct dmub_cmd_header header; 2886 2887 /** 2888 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2889 */ 2890 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2891 }; 2892 2893 /** 2894 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2895 */ 2896 struct dmub_cmd_abm_set_pwm_frac_data { 2897 /** 2898 * Enable/disable fractional duty cycle for backlight PWM. 2899 * TODO: Convert to uint8_t. 2900 */ 2901 uint32_t fractional_pwm; 2902 2903 /** 2904 * ABM control version. 2905 */ 2906 uint8_t version; 2907 2908 /** 2909 * Panel Control HW instance mask. 2910 * Bit 0 is Panel Control HW instance 0. 2911 * Bit 1 is Panel Control HW instance 1. 2912 */ 2913 uint8_t panel_mask; 2914 2915 /** 2916 * Explicit padding to 4 byte boundary. 2917 */ 2918 uint8_t pad[2]; 2919 }; 2920 2921 /** 2922 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2923 */ 2924 struct dmub_rb_cmd_abm_set_pwm_frac { 2925 /** 2926 * Command header. 2927 */ 2928 struct dmub_cmd_header header; 2929 2930 /** 2931 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2932 */ 2933 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2934 }; 2935 2936 /** 2937 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2938 */ 2939 struct dmub_cmd_abm_init_config_data { 2940 /** 2941 * Location of indirect buffer used to pass init data to ABM. 2942 */ 2943 union dmub_addr src; 2944 2945 /** 2946 * Indirect buffer length. 2947 */ 2948 uint16_t bytes; 2949 2950 2951 /** 2952 * ABM control version. 2953 */ 2954 uint8_t version; 2955 2956 /** 2957 * Panel Control HW instance mask. 2958 * Bit 0 is Panel Control HW instance 0. 2959 * Bit 1 is Panel Control HW instance 1. 2960 */ 2961 uint8_t panel_mask; 2962 2963 /** 2964 * Explicit padding to 4 byte boundary. 2965 */ 2966 uint8_t pad[2]; 2967 }; 2968 2969 /** 2970 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2971 */ 2972 struct dmub_rb_cmd_abm_init_config { 2973 /** 2974 * Command header. 2975 */ 2976 struct dmub_cmd_header header; 2977 2978 /** 2979 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2980 */ 2981 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2982 }; 2983 2984 /** 2985 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2986 */ 2987 2988 struct dmub_cmd_abm_pause_data { 2989 2990 /** 2991 * Panel Control HW instance mask. 2992 * Bit 0 is Panel Control HW instance 0. 2993 * Bit 1 is Panel Control HW instance 1. 2994 */ 2995 uint8_t panel_mask; 2996 2997 /** 2998 * OTG hw instance 2999 */ 3000 uint8_t otg_inst; 3001 3002 /** 3003 * Enable or disable ABM pause 3004 */ 3005 uint8_t enable; 3006 3007 /** 3008 * Explicit padding to 4 byte boundary. 3009 */ 3010 uint8_t pad[1]; 3011 }; 3012 3013 /** 3014 * Definition of a DMUB_CMD__ABM_PAUSE command. 3015 */ 3016 struct dmub_rb_cmd_abm_pause { 3017 /** 3018 * Command header. 3019 */ 3020 struct dmub_cmd_header header; 3021 3022 /** 3023 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3024 */ 3025 struct dmub_cmd_abm_pause_data abm_pause_data; 3026 }; 3027 3028 /** 3029 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3030 */ 3031 struct dmub_cmd_query_feature_caps_data { 3032 /** 3033 * DMUB feature capabilities. 3034 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3035 */ 3036 struct dmub_feature_caps feature_caps; 3037 }; 3038 3039 /** 3040 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3041 */ 3042 struct dmub_rb_cmd_query_feature_caps { 3043 /** 3044 * Command header. 3045 */ 3046 struct dmub_cmd_header header; 3047 /** 3048 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3049 */ 3050 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 3051 }; 3052 3053 /** 3054 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3055 */ 3056 struct dmub_cmd_visual_confirm_color_data { 3057 /** 3058 * DMUB feature capabilities. 3059 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3060 */ 3061 struct dmub_visual_confirm_color visual_confirm_color; 3062 }; 3063 3064 /** 3065 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3066 */ 3067 struct dmub_rb_cmd_get_visual_confirm_color { 3068 /** 3069 * Command header. 3070 */ 3071 struct dmub_cmd_header header; 3072 /** 3073 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3074 */ 3075 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3076 }; 3077 3078 struct dmub_optc_state { 3079 uint32_t v_total_max; 3080 uint32_t v_total_min; 3081 uint32_t tg_inst; 3082 }; 3083 3084 struct dmub_rb_cmd_drr_update { 3085 struct dmub_cmd_header header; 3086 struct dmub_optc_state dmub_optc_state_req; 3087 }; 3088 3089 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 3090 uint32_t pix_clk_100hz; 3091 uint8_t max_ramp_step; 3092 uint8_t pipes; 3093 uint8_t min_refresh_in_hz; 3094 uint8_t pipe_count; 3095 uint8_t pipe_index[4]; 3096 }; 3097 3098 struct dmub_cmd_fw_assisted_mclk_switch_config { 3099 uint8_t fams_enabled; 3100 uint8_t visual_confirm_enabled; 3101 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 3102 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 3103 }; 3104 3105 struct dmub_rb_cmd_fw_assisted_mclk_switch { 3106 struct dmub_cmd_header header; 3107 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 3108 }; 3109 3110 /** 3111 * enum dmub_cmd_panel_cntl_type - Panel control command. 3112 */ 3113 enum dmub_cmd_panel_cntl_type { 3114 /** 3115 * Initializes embedded panel hardware blocks. 3116 */ 3117 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3118 /** 3119 * Queries backlight info for the embedded panel. 3120 */ 3121 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3122 }; 3123 3124 /** 3125 * struct dmub_cmd_panel_cntl_data - Panel control data. 3126 */ 3127 struct dmub_cmd_panel_cntl_data { 3128 uint32_t inst; /**< panel instance */ 3129 uint32_t current_backlight; /* in/out */ 3130 uint32_t bl_pwm_cntl; /* in/out */ 3131 uint32_t bl_pwm_period_cntl; /* in/out */ 3132 uint32_t bl_pwm_ref_div1; /* in/out */ 3133 uint8_t is_backlight_on : 1; /* in/out */ 3134 uint8_t is_powered_on : 1; /* in/out */ 3135 uint8_t padding[3]; 3136 uint32_t bl_pwm_ref_div2; /* in/out */ 3137 uint8_t reserved[4]; 3138 }; 3139 3140 /** 3141 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3142 */ 3143 struct dmub_rb_cmd_panel_cntl { 3144 struct dmub_cmd_header header; /**< header */ 3145 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3146 }; 3147 3148 /** 3149 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3150 */ 3151 struct dmub_cmd_lvtma_control_data { 3152 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3153 uint8_t bypass_panel_control_wait; 3154 uint8_t reserved_0[2]; /**< For future use */ 3155 uint8_t panel_inst; /**< LVTMA control instance */ 3156 uint8_t reserved_1[3]; /**< For future use */ 3157 }; 3158 3159 /** 3160 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3161 */ 3162 struct dmub_rb_cmd_lvtma_control { 3163 /** 3164 * Command header. 3165 */ 3166 struct dmub_cmd_header header; 3167 /** 3168 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3169 */ 3170 struct dmub_cmd_lvtma_control_data data; 3171 }; 3172 3173 /** 3174 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3175 */ 3176 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3177 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3178 uint8_t is_usb; /**< is phy is usb */ 3179 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3180 uint8_t is_dp4; /**< is dp in 4 lane */ 3181 }; 3182 3183 /** 3184 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3185 */ 3186 struct dmub_rb_cmd_transmitter_query_dp_alt { 3187 struct dmub_cmd_header header; /**< header */ 3188 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3189 }; 3190 3191 /** 3192 * Maximum number of bytes a chunk sent to DMUB for parsing 3193 */ 3194 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3195 3196 /** 3197 * Represent a chunk of CEA blocks sent to DMUB for parsing 3198 */ 3199 struct dmub_cmd_send_edid_cea { 3200 uint16_t offset; /**< offset into the CEA block */ 3201 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3202 uint16_t cea_total_length; /**< total length of the CEA block */ 3203 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3204 uint8_t pad[3]; /**< padding and for future expansion */ 3205 }; 3206 3207 /** 3208 * Result of VSDB parsing from CEA block 3209 */ 3210 struct dmub_cmd_edid_cea_amd_vsdb { 3211 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3212 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3213 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3214 uint16_t min_frame_rate; /**< Maximum frame rate */ 3215 uint16_t max_frame_rate; /**< Minimum frame rate */ 3216 }; 3217 3218 /** 3219 * Result of sending a CEA chunk 3220 */ 3221 struct dmub_cmd_edid_cea_ack { 3222 uint16_t offset; /**< offset of the chunk into the CEA block */ 3223 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3224 uint8_t pad; /**< padding and for future expansion */ 3225 }; 3226 3227 /** 3228 * Specify whether the result is an ACK/NACK or the parsing has finished 3229 */ 3230 enum dmub_cmd_edid_cea_reply_type { 3231 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3232 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3233 }; 3234 3235 /** 3236 * Definition of a DMUB_CMD__EDID_CEA command. 3237 */ 3238 struct dmub_rb_cmd_edid_cea { 3239 struct dmub_cmd_header header; /**< Command header */ 3240 union dmub_cmd_edid_cea_data { 3241 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3242 struct dmub_cmd_edid_cea_output { /**< output with results */ 3243 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3244 union { 3245 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3246 struct dmub_cmd_edid_cea_ack ack; 3247 }; 3248 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3249 } data; /**< Command data */ 3250 3251 }; 3252 3253 /** 3254 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3255 */ 3256 struct dmub_cmd_cable_id_input { 3257 uint8_t phy_inst; /**< phy inst for cable id data */ 3258 }; 3259 3260 /** 3261 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3262 */ 3263 struct dmub_cmd_cable_id_output { 3264 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3265 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3266 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3267 uint8_t RESERVED :2; /**< reserved means not defined */ 3268 }; 3269 3270 /** 3271 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3272 */ 3273 struct dmub_rb_cmd_get_usbc_cable_id { 3274 struct dmub_cmd_header header; /**< Command header */ 3275 /** 3276 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3277 */ 3278 union dmub_cmd_cable_id_data { 3279 struct dmub_cmd_cable_id_input input; /**< Input */ 3280 struct dmub_cmd_cable_id_output output; /**< Output */ 3281 uint8_t output_raw; /**< Raw data output */ 3282 } data; 3283 }; 3284 3285 /** 3286 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3287 */ 3288 enum dmub_cmd_secure_display_type { 3289 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3290 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3291 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3292 }; 3293 3294 /** 3295 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3296 */ 3297 struct dmub_rb_cmd_secure_display { 3298 struct dmub_cmd_header header; 3299 /** 3300 * Data passed from driver to dmub firmware. 3301 */ 3302 struct dmub_cmd_roi_info { 3303 uint16_t x_start; 3304 uint16_t x_end; 3305 uint16_t y_start; 3306 uint16_t y_end; 3307 uint8_t otg_id; 3308 uint8_t phy_id; 3309 } roi_info; 3310 }; 3311 3312 /** 3313 * union dmub_rb_cmd - DMUB inbox command. 3314 */ 3315 union dmub_rb_cmd { 3316 /** 3317 * Elements shared with all commands. 3318 */ 3319 struct dmub_rb_cmd_common cmd_common; 3320 /** 3321 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3322 */ 3323 struct dmub_rb_cmd_read_modify_write read_modify_write; 3324 /** 3325 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3326 */ 3327 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3328 /** 3329 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3330 */ 3331 struct dmub_rb_cmd_burst_write burst_write; 3332 /** 3333 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3334 */ 3335 struct dmub_rb_cmd_reg_wait reg_wait; 3336 /** 3337 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3338 */ 3339 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3340 /** 3341 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3342 */ 3343 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3344 /** 3345 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3346 */ 3347 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3348 /** 3349 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3350 */ 3351 struct dmub_rb_cmd_dpphy_init dpphy_init; 3352 /** 3353 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3354 */ 3355 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3356 /** 3357 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3358 */ 3359 struct dmub_rb_cmd_domain_control domain_control; 3360 /** 3361 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3362 */ 3363 struct dmub_rb_cmd_psr_set_version psr_set_version; 3364 /** 3365 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3366 */ 3367 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3368 /** 3369 * Definition of a DMUB_CMD__PSR_ENABLE command. 3370 */ 3371 struct dmub_rb_cmd_psr_enable psr_enable; 3372 /** 3373 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3374 */ 3375 struct dmub_rb_cmd_psr_set_level psr_set_level; 3376 /** 3377 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3378 */ 3379 struct dmub_rb_cmd_psr_force_static psr_force_static; 3380 /** 3381 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3382 */ 3383 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3384 /** 3385 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3386 */ 3387 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3388 /** 3389 * Definition of a DMUB_CMD__HW_LOCK command. 3390 * Command is used by driver and FW. 3391 */ 3392 struct dmub_rb_cmd_lock_hw lock_hw; 3393 /** 3394 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3395 */ 3396 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3397 /** 3398 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3399 */ 3400 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3401 /** 3402 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3403 */ 3404 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3405 /** 3406 * Definition of a DMUB_CMD__MALL command. 3407 */ 3408 struct dmub_rb_cmd_mall mall; 3409 /** 3410 * Definition of a DMUB_CMD__CAB command. 3411 */ 3412 struct dmub_rb_cmd_cab_for_ss cab; 3413 3414 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3415 3416 /** 3417 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3418 */ 3419 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3420 3421 /** 3422 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3423 */ 3424 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3425 3426 /** 3427 * Definition of DMUB_CMD__PANEL_CNTL commands. 3428 */ 3429 struct dmub_rb_cmd_panel_cntl panel_cntl; 3430 /** 3431 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3432 */ 3433 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3434 3435 /** 3436 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3437 */ 3438 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3439 3440 /** 3441 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3442 */ 3443 struct dmub_rb_cmd_abm_set_level abm_set_level; 3444 3445 /** 3446 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3447 */ 3448 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3449 3450 /** 3451 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3452 */ 3453 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3454 3455 /** 3456 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3457 */ 3458 struct dmub_rb_cmd_abm_init_config abm_init_config; 3459 3460 /** 3461 * Definition of a DMUB_CMD__ABM_PAUSE command. 3462 */ 3463 struct dmub_rb_cmd_abm_pause abm_pause; 3464 3465 /** 3466 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3467 */ 3468 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3469 3470 /** 3471 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3472 */ 3473 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3474 3475 /** 3476 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3477 */ 3478 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3479 3480 /** 3481 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3482 */ 3483 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3484 struct dmub_rb_cmd_drr_update drr_update; 3485 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3486 3487 /** 3488 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3489 */ 3490 struct dmub_rb_cmd_lvtma_control lvtma_control; 3491 /** 3492 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3493 */ 3494 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3495 /** 3496 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3497 */ 3498 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3499 /** 3500 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3501 */ 3502 struct dmub_rb_cmd_set_config_access set_config_access; 3503 /** 3504 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3505 */ 3506 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3507 /** 3508 * Definition of a DMUB_CMD__EDID_CEA command. 3509 */ 3510 struct dmub_rb_cmd_edid_cea edid_cea; 3511 /** 3512 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3513 */ 3514 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3515 3516 /** 3517 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3518 */ 3519 struct dmub_rb_cmd_query_hpd_state query_hpd; 3520 /** 3521 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3522 */ 3523 struct dmub_rb_cmd_secure_display secure_display; 3524 3525 /** 3526 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3527 */ 3528 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3529 }; 3530 3531 /** 3532 * union dmub_rb_out_cmd - Outbox command 3533 */ 3534 union dmub_rb_out_cmd { 3535 /** 3536 * Parameters common to every command. 3537 */ 3538 struct dmub_rb_cmd_common cmd_common; 3539 /** 3540 * AUX reply command. 3541 */ 3542 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3543 /** 3544 * HPD notify command. 3545 */ 3546 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3547 /** 3548 * SET_CONFIG reply command. 3549 */ 3550 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3551 /** 3552 * DPIA notification command. 3553 */ 3554 struct dmub_rb_cmd_dpia_notification dpia_notification; 3555 }; 3556 #pragma pack(pop) 3557 3558 3559 //============================================================================== 3560 //</DMUB_CMD>=================================================================== 3561 //============================================================================== 3562 //< DMUB_RB>==================================================================== 3563 //============================================================================== 3564 3565 #if defined(__cplusplus) 3566 extern "C" { 3567 #endif 3568 3569 /** 3570 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3571 */ 3572 struct dmub_rb_init_params { 3573 void *ctx; /**< Caller provided context pointer */ 3574 void *base_address; /**< CPU base address for ring's data */ 3575 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3576 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3577 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3578 }; 3579 3580 /** 3581 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3582 */ 3583 struct dmub_rb { 3584 void *base_address; /**< CPU address for the ring's data */ 3585 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3586 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3587 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3588 3589 void *ctx; /**< Caller provided context pointer */ 3590 void *dmub; /**< Pointer to the DMUB interface */ 3591 }; 3592 3593 /** 3594 * @brief Checks if the ringbuffer is empty. 3595 * 3596 * @param rb DMUB Ringbuffer 3597 * @return true if empty 3598 * @return false otherwise 3599 */ 3600 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3601 { 3602 return (rb->wrpt == rb->rptr); 3603 } 3604 3605 /** 3606 * @brief Checks if the ringbuffer is full 3607 * 3608 * @param rb DMUB Ringbuffer 3609 * @return true if full 3610 * @return false otherwise 3611 */ 3612 static inline bool dmub_rb_full(struct dmub_rb *rb) 3613 { 3614 uint32_t data_count; 3615 3616 if (rb->wrpt >= rb->rptr) 3617 data_count = rb->wrpt - rb->rptr; 3618 else 3619 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3620 3621 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3622 } 3623 3624 /** 3625 * @brief Pushes a command into the ringbuffer 3626 * 3627 * @param rb DMUB ringbuffer 3628 * @param cmd The command to push 3629 * @return true if the ringbuffer was not full 3630 * @return false otherwise 3631 */ 3632 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3633 const union dmub_rb_cmd *cmd) 3634 { 3635 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3636 const uint64_t *src = (const uint64_t *)cmd; 3637 uint8_t i; 3638 3639 if (dmub_rb_full(rb)) 3640 return false; 3641 3642 // copying data 3643 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3644 *dst++ = *src++; 3645 3646 rb->wrpt += DMUB_RB_CMD_SIZE; 3647 3648 if (rb->wrpt >= rb->capacity) 3649 rb->wrpt %= rb->capacity; 3650 3651 return true; 3652 } 3653 3654 /** 3655 * @brief Pushes a command into the DMUB outbox ringbuffer 3656 * 3657 * @param rb DMUB outbox ringbuffer 3658 * @param cmd Outbox command 3659 * @return true if not full 3660 * @return false otherwise 3661 */ 3662 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3663 const union dmub_rb_out_cmd *cmd) 3664 { 3665 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3666 const uint8_t *src = (const uint8_t *)cmd; 3667 3668 if (dmub_rb_full(rb)) 3669 return false; 3670 3671 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3672 3673 rb->wrpt += DMUB_RB_CMD_SIZE; 3674 3675 if (rb->wrpt >= rb->capacity) 3676 rb->wrpt %= rb->capacity; 3677 3678 return true; 3679 } 3680 3681 /** 3682 * @brief Returns the next unprocessed command in the ringbuffer. 3683 * 3684 * @param rb DMUB ringbuffer 3685 * @param cmd The command to return 3686 * @return true if not empty 3687 * @return false otherwise 3688 */ 3689 static inline bool dmub_rb_front(struct dmub_rb *rb, 3690 union dmub_rb_cmd **cmd) 3691 { 3692 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3693 3694 if (dmub_rb_empty(rb)) 3695 return false; 3696 3697 *cmd = (union dmub_rb_cmd *)rb_cmd; 3698 3699 return true; 3700 } 3701 3702 /** 3703 * @brief Determines the next ringbuffer offset. 3704 * 3705 * @param rb DMUB inbox ringbuffer 3706 * @param num_cmds Number of commands 3707 * @param next_rptr The next offset in the ringbuffer 3708 */ 3709 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3710 uint32_t num_cmds, 3711 uint32_t *next_rptr) 3712 { 3713 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3714 3715 if (*next_rptr >= rb->capacity) 3716 *next_rptr %= rb->capacity; 3717 } 3718 3719 /** 3720 * @brief Returns a pointer to a command in the inbox. 3721 * 3722 * @param rb DMUB inbox ringbuffer 3723 * @param cmd The inbox command to return 3724 * @param rptr The ringbuffer offset 3725 * @return true if not empty 3726 * @return false otherwise 3727 */ 3728 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3729 union dmub_rb_cmd **cmd, 3730 uint32_t rptr) 3731 { 3732 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3733 3734 if (dmub_rb_empty(rb)) 3735 return false; 3736 3737 *cmd = (union dmub_rb_cmd *)rb_cmd; 3738 3739 return true; 3740 } 3741 3742 /** 3743 * @brief Returns the next unprocessed command in the outbox. 3744 * 3745 * @param rb DMUB outbox ringbuffer 3746 * @param cmd The outbox command to return 3747 * @return true if not empty 3748 * @return false otherwise 3749 */ 3750 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3751 union dmub_rb_out_cmd *cmd) 3752 { 3753 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3754 uint64_t *dst = (uint64_t *)cmd; 3755 uint8_t i; 3756 3757 if (dmub_rb_empty(rb)) 3758 return false; 3759 3760 // copying data 3761 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3762 *dst++ = *src++; 3763 3764 return true; 3765 } 3766 3767 /** 3768 * @brief Removes the front entry in the ringbuffer. 3769 * 3770 * @param rb DMUB ringbuffer 3771 * @return true if the command was removed 3772 * @return false if there were no commands 3773 */ 3774 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3775 { 3776 if (dmub_rb_empty(rb)) 3777 return false; 3778 3779 rb->rptr += DMUB_RB_CMD_SIZE; 3780 3781 if (rb->rptr >= rb->capacity) 3782 rb->rptr %= rb->capacity; 3783 3784 return true; 3785 } 3786 3787 /** 3788 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3789 * 3790 * Avoids a race condition where DMCUB accesses memory while 3791 * there are still writes in flight to framebuffer. 3792 * 3793 * @param rb DMUB ringbuffer 3794 */ 3795 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3796 { 3797 uint32_t rptr = rb->rptr; 3798 uint32_t wptr = rb->wrpt; 3799 3800 while (rptr != wptr) { 3801 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3802 uint8_t i; 3803 3804 /* Don't remove this. 3805 * The contents need to actually be read from the ring buffer 3806 * for this function to be effective. 3807 */ 3808 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3809 (void)READ_ONCE(*data++); 3810 3811 rptr += DMUB_RB_CMD_SIZE; 3812 if (rptr >= rb->capacity) 3813 rptr %= rb->capacity; 3814 } 3815 } 3816 3817 /** 3818 * @brief Initializes a DMCUB ringbuffer 3819 * 3820 * @param rb DMUB ringbuffer 3821 * @param init_params initial configuration for the ringbuffer 3822 */ 3823 static inline void dmub_rb_init(struct dmub_rb *rb, 3824 struct dmub_rb_init_params *init_params) 3825 { 3826 rb->base_address = init_params->base_address; 3827 rb->capacity = init_params->capacity; 3828 rb->rptr = init_params->read_ptr; 3829 rb->wrpt = init_params->write_ptr; 3830 } 3831 3832 /** 3833 * @brief Copies output data from in/out commands into the given command. 3834 * 3835 * @param rb DMUB ringbuffer 3836 * @param cmd Command to copy data into 3837 */ 3838 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3839 union dmub_rb_cmd *cmd) 3840 { 3841 // Copy rb entry back into command 3842 uint8_t *rd_ptr = (rb->rptr == 0) ? 3843 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3844 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3845 3846 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3847 } 3848 3849 #if defined(__cplusplus) 3850 } 3851 #endif 3852 3853 //============================================================================== 3854 //</DMUB_RB>==================================================================== 3855 //============================================================================== 3856 3857 #endif /* _DMUB_CMD_H_ */ 3858