1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 #include <stdarg.h> 34 35 #include "atomfirmware.h" 36 37 /* Firmware versioning. */ 38 #ifdef DMUB_EXPOSE_VERSION 39 #define DMUB_FW_VERSION_GIT_HASH 0x8aafc9acc 40 #define DMUB_FW_VERSION_MAJOR 0 41 #define DMUB_FW_VERSION_MINOR 0 42 #define DMUB_FW_VERSION_REVISION 38 43 #define DMUB_FW_VERSION_TEST 0 44 #define DMUB_FW_VERSION_VBIOS 0 45 #define DMUB_FW_VERSION_HOTFIX 0 46 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 47 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 48 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 49 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 50 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 51 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 52 53 #endif 54 55 //<DMUB_TYPES>================================================================== 56 /* Basic type definitions. */ 57 58 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 59 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 #define SET_ABM_PIPE_NORMAL 1 62 63 /* Maximum number of streams on any ASIC. */ 64 #define DMUB_MAX_STREAMS 6 65 66 /* Maximum number of planes on any ASIC. */ 67 #define DMUB_MAX_PLANES 6 68 69 #ifndef PHYSICAL_ADDRESS_LOC 70 #define PHYSICAL_ADDRESS_LOC union large_integer 71 #endif 72 73 #ifndef dmub_memcpy 74 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 75 #endif 76 77 #ifndef dmub_memset 78 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 79 #endif 80 81 #if defined(__cplusplus) 82 extern "C" { 83 #endif 84 85 #ifndef dmub_udelay 86 #define dmub_udelay(microseconds) udelay(microseconds) 87 #endif 88 89 union dmub_addr { 90 struct { 91 uint32_t low_part; 92 uint32_t high_part; 93 } u; 94 uint64_t quad_part; 95 }; 96 97 union dmub_psr_debug_flags { 98 struct { 99 uint32_t visual_confirm : 1; 100 uint32_t use_hw_lock_mgr : 1; 101 uint32_t log_line_nums : 1; 102 } bitfields; 103 104 uint32_t u32All; 105 }; 106 107 #if defined(__cplusplus) 108 } 109 #endif 110 111 112 113 //============================================================================== 114 //</DMUB_TYPES>================================================================= 115 //============================================================================== 116 //< DMUB_META>================================================================== 117 //============================================================================== 118 #pragma pack(push, 1) 119 120 /* Magic value for identifying dmub_fw_meta_info */ 121 #define DMUB_FW_META_MAGIC 0x444D5542 122 123 /* Offset from the end of the file to the dmub_fw_meta_info */ 124 #define DMUB_FW_META_OFFSET 0x24 125 126 /** 127 * struct dmub_fw_meta_info - metadata associated with fw binary 128 * 129 * NOTE: This should be considered a stable API. Fields should 130 * not be repurposed or reordered. New fields should be 131 * added instead to extend the structure. 132 * 133 * @magic_value: magic value identifying DMUB firmware meta info 134 * @fw_region_size: size of the firmware state region 135 * @trace_buffer_size: size of the tracebuffer region 136 * @fw_version: the firmware version information 137 * @dal_fw: 1 if the firmware is DAL 138 */ 139 struct dmub_fw_meta_info { 140 uint32_t magic_value; 141 uint32_t fw_region_size; 142 uint32_t trace_buffer_size; 143 uint32_t fw_version; 144 uint8_t dal_fw; 145 uint8_t reserved[3]; 146 }; 147 148 /* Ensure that the structure remains 64 bytes. */ 149 union dmub_fw_meta { 150 struct dmub_fw_meta_info info; 151 uint8_t reserved[64]; 152 }; 153 154 #pragma pack(pop) 155 156 //============================================================================== 157 //< DMUB_STATUS>================================================================ 158 //============================================================================== 159 160 /** 161 * DMCUB scratch registers can be used to determine firmware status. 162 * Current scratch register usage is as follows: 163 * 164 * SCRATCH0: FW Boot Status register 165 * SCRATCH15: FW Boot Options register 166 */ 167 168 /* Register bit definition for SCRATCH0 */ 169 union dmub_fw_boot_status { 170 struct { 171 uint32_t dal_fw : 1; 172 uint32_t mailbox_rdy : 1; 173 uint32_t optimized_init_done : 1; 174 uint32_t restore_required : 1; 175 } bits; 176 uint32_t all; 177 }; 178 179 enum dmub_fw_boot_status_bit { 180 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), 181 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), 182 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 183 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), 184 }; 185 186 /* Register bit definition for SCRATCH15 */ 187 union dmub_fw_boot_options { 188 struct { 189 uint32_t pemu_env : 1; 190 uint32_t fpga_env : 1; 191 uint32_t optimized_init : 1; 192 uint32_t skip_phy_access : 1; 193 uint32_t disable_clk_gate: 1; 194 uint32_t reserved : 27; 195 } bits; 196 uint32_t all; 197 }; 198 199 enum dmub_fw_boot_options_bit { 200 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), 201 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), 202 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 203 }; 204 205 //============================================================================== 206 //</DMUB_STATUS>================================================================ 207 //============================================================================== 208 //< DMUB_VBIOS>================================================================= 209 //============================================================================== 210 211 /* 212 * Command IDs should be treated as stable ABI. 213 * Do not reuse or modify IDs. 214 */ 215 216 enum dmub_cmd_vbios_type { 217 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 218 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 219 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 220 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 221 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 222 }; 223 224 //============================================================================== 225 //</DMUB_VBIOS>================================================================= 226 //============================================================================== 227 //< DMUB_GPINT>================================================================= 228 //============================================================================== 229 230 /** 231 * The shifts and masks below may alternatively be used to format and read 232 * the command register bits. 233 */ 234 235 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 236 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 237 238 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 239 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 240 241 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 242 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 243 244 /** 245 * Command responses. 246 */ 247 248 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 249 250 /** 251 * The register format for sending a command via the GPINT. 252 */ 253 union dmub_gpint_data_register { 254 struct { 255 uint32_t param : 16; 256 uint32_t command_code : 12; 257 uint32_t status : 4; 258 } bits; 259 uint32_t all; 260 }; 261 262 /* 263 * Command IDs should be treated as stable ABI. 264 * Do not reuse or modify IDs. 265 */ 266 267 enum dmub_gpint_command { 268 DMUB_GPINT__INVALID_COMMAND = 0, 269 DMUB_GPINT__GET_FW_VERSION = 1, 270 DMUB_GPINT__STOP_FW = 2, 271 DMUB_GPINT__GET_PSR_STATE = 7, 272 /** 273 * DESC: Notifies DMCUB of the currently active streams. 274 * ARGS: Stream mask, 1 bit per active stream index. 275 */ 276 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 277 }; 278 279 //============================================================================== 280 //</DMUB_GPINT>================================================================= 281 //============================================================================== 282 //< DMUB_CMD>=================================================================== 283 //============================================================================== 284 285 #define DMUB_RB_CMD_SIZE 64 286 #define DMUB_RB_MAX_ENTRY 128 287 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 288 #define REG_SET_MASK 0xFFFF 289 290 /* 291 * Command IDs should be treated as stable ABI. 292 * Do not reuse or modify IDs. 293 */ 294 295 enum dmub_cmd_type { 296 DMUB_CMD__NULL = 0, 297 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 298 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 299 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 300 DMUB_CMD__REG_REG_WAIT = 4, 301 DMUB_CMD__PLAT_54186_WA = 5, 302 DMUB_CMD__PSR = 64, 303 DMUB_CMD__MALL = 65, 304 DMUB_CMD__ABM = 66, 305 DMUB_CMD__HW_LOCK = 69, 306 DMUB_CMD__DP_AUX_ACCESS = 70, 307 DMUB_CMD__OUTBOX1_ENABLE = 71, 308 DMUB_CMD__VBIOS = 128, 309 }; 310 311 enum dmub_out_cmd_type { 312 DMUB_OUT_CMD__NULL = 0, 313 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 314 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 315 }; 316 317 #pragma pack(push, 1) 318 319 struct dmub_cmd_header { 320 unsigned int type : 8; 321 unsigned int sub_type : 8; 322 unsigned int reserved0 : 8; 323 unsigned int payload_bytes : 6; /* up to 60 bytes */ 324 unsigned int reserved1 : 2; 325 }; 326 327 /* 328 * Read modify write 329 * 330 * 60 payload bytes can hold up to 5 sets of read modify writes, 331 * each take 3 dwords. 332 * 333 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 334 * 335 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 336 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 337 */ 338 struct dmub_cmd_read_modify_write_sequence { 339 uint32_t addr; 340 uint32_t modify_mask; 341 uint32_t modify_value; 342 }; 343 344 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 345 struct dmub_rb_cmd_read_modify_write { 346 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 347 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 348 }; 349 350 /* 351 * Update a register with specified masks and values sequeunce 352 * 353 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 354 * 355 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 356 * 357 * 358 * USE CASE: 359 * 1. auto-increment register where additional read would update pointer and produce wrong result 360 * 2. toggle a bit without read in the middle 361 */ 362 363 struct dmub_cmd_reg_field_update_sequence { 364 uint32_t modify_mask; // 0xffff'ffff to skip initial read 365 uint32_t modify_value; 366 }; 367 368 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 369 struct dmub_rb_cmd_reg_field_update_sequence { 370 struct dmub_cmd_header header; 371 uint32_t addr; 372 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 373 }; 374 375 /* 376 * Burst write 377 * 378 * support use case such as writing out LUTs. 379 * 380 * 60 payload bytes can hold up to 14 values to write to given address 381 * 382 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 383 */ 384 #define DMUB_BURST_WRITE_VALUES__MAX 14 385 struct dmub_rb_cmd_burst_write { 386 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 387 uint32_t addr; 388 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 389 }; 390 391 392 struct dmub_rb_cmd_common { 393 struct dmub_cmd_header header; 394 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 395 }; 396 397 struct dmub_cmd_reg_wait_data { 398 uint32_t addr; 399 uint32_t mask; 400 uint32_t condition_field_value; 401 uint32_t time_out_us; 402 }; 403 404 struct dmub_rb_cmd_reg_wait { 405 struct dmub_cmd_header header; 406 struct dmub_cmd_reg_wait_data reg_wait; 407 }; 408 409 struct dmub_cmd_PLAT_54186_wa { 410 uint32_t DCSURF_SURFACE_CONTROL; 411 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 412 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 413 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 414 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 415 struct { 416 uint8_t hubp_inst : 4; 417 uint8_t tmz_surface : 1; 418 uint8_t immediate :1; 419 uint8_t vmid : 4; 420 uint8_t grph_stereo : 1; 421 uint32_t reserved : 21; 422 } flip_params; 423 uint32_t reserved[9]; 424 }; 425 426 struct dmub_rb_cmd_PLAT_54186_wa { 427 struct dmub_cmd_header header; 428 struct dmub_cmd_PLAT_54186_wa flip; 429 }; 430 431 struct dmub_rb_cmd_mall { 432 struct dmub_cmd_header header; 433 union dmub_addr cursor_copy_src; 434 union dmub_addr cursor_copy_dst; 435 uint32_t tmr_delay; 436 uint32_t tmr_scale; 437 uint16_t cursor_width; 438 uint16_t cursor_pitch; 439 uint16_t cursor_height; 440 uint8_t cursor_bpp; 441 }; 442 443 struct dmub_cmd_digx_encoder_control_data { 444 union dig_encoder_control_parameters_v1_5 dig; 445 }; 446 447 struct dmub_rb_cmd_digx_encoder_control { 448 struct dmub_cmd_header header; 449 struct dmub_cmd_digx_encoder_control_data encoder_control; 450 }; 451 452 struct dmub_cmd_set_pixel_clock_data { 453 struct set_pixel_clock_parameter_v1_7 clk; 454 }; 455 456 struct dmub_rb_cmd_set_pixel_clock { 457 struct dmub_cmd_header header; 458 struct dmub_cmd_set_pixel_clock_data pixel_clock; 459 }; 460 461 struct dmub_cmd_enable_disp_power_gating_data { 462 struct enable_disp_power_gating_parameters_v2_1 pwr; 463 }; 464 465 struct dmub_rb_cmd_enable_disp_power_gating { 466 struct dmub_cmd_header header; 467 struct dmub_cmd_enable_disp_power_gating_data power_gating; 468 }; 469 470 struct dmub_cmd_dig1_transmitter_control_data { 471 struct dig_transmitter_control_parameters_v1_6 dig; 472 }; 473 474 struct dmub_rb_cmd_dig1_transmitter_control { 475 struct dmub_cmd_header header; 476 struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 477 }; 478 479 struct dmub_rb_cmd_dpphy_init { 480 struct dmub_cmd_header header; 481 uint8_t reserved[60]; 482 }; 483 484 enum dp_aux_request_action { 485 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 486 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 487 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 488 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 489 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 490 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 491 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 492 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 493 }; 494 495 enum aux_return_code_type { 496 AUX_RET_SUCCESS = 0, 497 AUX_RET_ERROR_TIMEOUT, 498 AUX_RET_ERROR_NO_DATA, 499 AUX_RET_ERROR_INVALID_OPERATION, 500 AUX_RET_ERROR_PROTOCOL_ERROR, 501 }; 502 503 /* DP AUX command */ 504 struct aux_transaction_parameters { 505 uint8_t is_i2c_over_aux; 506 uint8_t action; 507 uint8_t length; 508 uint8_t pad; 509 uint32_t address; 510 uint8_t data[16]; 511 }; 512 513 struct dmub_cmd_dp_aux_control_data { 514 uint32_t handle; 515 uint8_t port_index; 516 uint8_t sw_crc_enabled; 517 uint16_t timeout; 518 struct aux_transaction_parameters dpaux; 519 }; 520 521 struct dmub_rb_cmd_dp_aux_access { 522 struct dmub_cmd_header header; 523 struct dmub_cmd_dp_aux_control_data aux_control; 524 }; 525 526 struct dmub_rb_cmd_outbox1_enable { 527 struct dmub_cmd_header header; 528 uint32_t enable; 529 }; 530 531 /* DP AUX Reply command - OutBox Cmd */ 532 struct aux_reply_data { 533 uint8_t command; 534 uint8_t length; 535 uint8_t pad[2]; 536 uint8_t data[16]; 537 }; 538 539 struct aux_reply_control_data { 540 uint32_t handle; 541 uint8_t phy_port_index; 542 uint8_t result; 543 uint16_t pad; 544 }; 545 546 struct dmub_rb_cmd_dp_aux_reply { 547 struct dmub_cmd_header header; 548 struct aux_reply_control_data control; 549 struct aux_reply_data reply_data; 550 }; 551 552 /* DP HPD Notify command - OutBox Cmd */ 553 enum dp_hpd_type { 554 DP_HPD = 0, 555 DP_IRQ 556 }; 557 558 enum dp_hpd_status { 559 DP_HPD_UNPLUG = 0, 560 DP_HPD_PLUG 561 }; 562 563 struct dp_hpd_data { 564 uint8_t phy_port_index; 565 uint8_t hpd_type; 566 uint8_t hpd_status; 567 uint8_t pad; 568 }; 569 570 struct dmub_rb_cmd_dp_hpd_notify { 571 struct dmub_cmd_header header; 572 struct dp_hpd_data hpd_data; 573 }; 574 575 /* 576 * Command IDs should be treated as stable ABI. 577 * Do not reuse or modify IDs. 578 */ 579 580 enum dmub_cmd_psr_type { 581 DMUB_CMD__PSR_SET_VERSION = 0, 582 DMUB_CMD__PSR_COPY_SETTINGS = 1, 583 DMUB_CMD__PSR_ENABLE = 2, 584 DMUB_CMD__PSR_DISABLE = 3, 585 DMUB_CMD__PSR_SET_LEVEL = 4, 586 }; 587 588 enum psr_version { 589 PSR_VERSION_1 = 0, 590 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 591 }; 592 593 enum dmub_cmd_mall_type { 594 DMUB_CMD__MALL_ACTION_ALLOW = 0, 595 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 596 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 597 }; 598 599 struct dmub_cmd_psr_copy_settings_data { 600 union dmub_psr_debug_flags debug; 601 uint16_t psr_level; 602 uint8_t dpp_inst; 603 uint8_t mpcc_inst; 604 uint8_t opp_inst; 605 uint8_t otg_inst; 606 uint8_t digfe_inst; 607 uint8_t digbe_inst; 608 uint8_t dpphy_inst; 609 uint8_t aux_inst; 610 uint8_t smu_optimizations_en; 611 uint8_t frame_delay; 612 uint8_t frame_cap_ind; 613 uint8_t pad[3]; 614 uint16_t init_sdp_deadline; 615 uint16_t pad2; 616 }; 617 618 struct dmub_rb_cmd_psr_copy_settings { 619 struct dmub_cmd_header header; 620 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 621 }; 622 623 struct dmub_cmd_psr_set_level_data { 624 uint16_t psr_level; 625 uint8_t pad[2]; 626 }; 627 628 struct dmub_rb_cmd_psr_set_level { 629 struct dmub_cmd_header header; 630 struct dmub_cmd_psr_set_level_data psr_set_level_data; 631 }; 632 633 struct dmub_rb_cmd_psr_enable { 634 struct dmub_cmd_header header; 635 }; 636 637 struct dmub_cmd_psr_set_version_data { 638 enum psr_version version; // PSR version 1 or 2 639 }; 640 641 struct dmub_rb_cmd_psr_set_version { 642 struct dmub_cmd_header header; 643 struct dmub_cmd_psr_set_version_data psr_set_version_data; 644 }; 645 646 union dmub_hw_lock_flags { 647 struct { 648 uint8_t lock_pipe : 1; 649 uint8_t lock_cursor : 1; 650 uint8_t lock_dig : 1; 651 uint8_t triple_buffer_lock : 1; 652 } bits; 653 654 uint8_t u8All; 655 }; 656 657 struct dmub_hw_lock_inst_flags { 658 uint8_t otg_inst; 659 uint8_t opp_inst; 660 uint8_t dig_inst; 661 uint8_t pad; 662 }; 663 664 enum hw_lock_client { 665 HW_LOCK_CLIENT_DRIVER = 0, 666 HW_LOCK_CLIENT_FW, 667 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 668 }; 669 670 struct dmub_cmd_lock_hw_data { 671 enum hw_lock_client client; 672 struct dmub_hw_lock_inst_flags inst_flags; 673 union dmub_hw_lock_flags hw_locks; 674 uint8_t lock; 675 uint8_t should_release; 676 uint8_t pad; 677 }; 678 679 struct dmub_rb_cmd_lock_hw { 680 struct dmub_cmd_header header; 681 struct dmub_cmd_lock_hw_data lock_hw_data; 682 }; 683 684 enum dmub_cmd_abm_type { 685 DMUB_CMD__ABM_INIT_CONFIG = 0, 686 DMUB_CMD__ABM_SET_PIPE = 1, 687 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 688 DMUB_CMD__ABM_SET_LEVEL = 3, 689 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 690 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 691 }; 692 693 #define NUM_AMBI_LEVEL 5 694 #define NUM_AGGR_LEVEL 4 695 #define NUM_POWER_FN_SEGS 8 696 #define NUM_BL_CURVE_SEGS 16 697 698 /* 699 * Parameters for ABM2.4 algorithm. 700 * Padded explicitly to 32-bit boundary. 701 */ 702 struct abm_config_table { 703 /* Parameters for crgb conversion */ 704 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 705 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 15B 706 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 31B 707 708 /* Parameters for custom curve */ 709 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 47B 710 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 79B 711 712 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 111B 713 uint16_t min_abm_backlight; // 121B 714 715 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 123B 716 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 143B 717 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 163B 718 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 183B 719 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 203B 720 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 207B 721 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 211B 722 uint8_t min_knee[NUM_AGGR_LEVEL]; // 215B 723 uint8_t max_knee[NUM_AGGR_LEVEL]; // 219B 724 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 223B 725 uint8_t pad3[3]; // 228B 726 }; 727 728 struct dmub_cmd_abm_set_pipe_data { 729 uint8_t otg_inst; 730 uint8_t panel_inst; 731 uint8_t set_pipe_option; 732 uint8_t ramping_boundary; // TODO: Remove this 733 }; 734 735 struct dmub_rb_cmd_abm_set_pipe { 736 struct dmub_cmd_header header; 737 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 738 }; 739 740 struct dmub_cmd_abm_set_backlight_data { 741 uint32_t frame_ramp; 742 uint32_t backlight_user_level; 743 }; 744 745 struct dmub_rb_cmd_abm_set_backlight { 746 struct dmub_cmd_header header; 747 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 748 }; 749 750 struct dmub_cmd_abm_set_level_data { 751 uint32_t level; 752 }; 753 754 struct dmub_rb_cmd_abm_set_level { 755 struct dmub_cmd_header header; 756 struct dmub_cmd_abm_set_level_data abm_set_level_data; 757 }; 758 759 struct dmub_cmd_abm_set_ambient_level_data { 760 uint32_t ambient_lux; 761 }; 762 763 struct dmub_rb_cmd_abm_set_ambient_level { 764 struct dmub_cmd_header header; 765 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 766 }; 767 768 struct dmub_cmd_abm_set_pwm_frac_data { 769 uint32_t fractional_pwm; 770 }; 771 772 struct dmub_rb_cmd_abm_set_pwm_frac { 773 struct dmub_cmd_header header; 774 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 775 }; 776 777 struct dmub_cmd_abm_init_config_data { 778 union dmub_addr src; 779 uint16_t bytes; 780 }; 781 782 struct dmub_rb_cmd_abm_init_config { 783 struct dmub_cmd_header header; 784 struct dmub_cmd_abm_init_config_data abm_init_config_data; 785 }; 786 787 union dmub_rb_cmd { 788 struct dmub_rb_cmd_lock_hw lock_hw; 789 struct dmub_rb_cmd_read_modify_write read_modify_write; 790 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 791 struct dmub_rb_cmd_burst_write burst_write; 792 struct dmub_rb_cmd_reg_wait reg_wait; 793 struct dmub_rb_cmd_common cmd_common; 794 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 795 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 796 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 797 struct dmub_rb_cmd_dpphy_init dpphy_init; 798 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 799 struct dmub_rb_cmd_psr_set_version psr_set_version; 800 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 801 struct dmub_rb_cmd_psr_enable psr_enable; 802 struct dmub_rb_cmd_psr_set_level psr_set_level; 803 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 804 struct dmub_rb_cmd_mall mall; 805 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 806 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 807 struct dmub_rb_cmd_abm_set_level abm_set_level; 808 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 809 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 810 struct dmub_rb_cmd_abm_init_config abm_init_config; 811 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 812 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 813 }; 814 815 union dmub_rb_out_cmd { 816 struct dmub_rb_cmd_common cmd_common; 817 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 818 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 819 }; 820 #pragma pack(pop) 821 822 823 //============================================================================== 824 //</DMUB_CMD>=================================================================== 825 //============================================================================== 826 //< DMUB_RB>==================================================================== 827 //============================================================================== 828 829 #if defined(__cplusplus) 830 extern "C" { 831 #endif 832 833 struct dmub_rb_init_params { 834 void *ctx; 835 void *base_address; 836 uint32_t capacity; 837 uint32_t read_ptr; 838 uint32_t write_ptr; 839 }; 840 841 struct dmub_rb { 842 void *base_address; 843 uint32_t data_count; 844 uint32_t rptr; 845 uint32_t wrpt; 846 uint32_t capacity; 847 848 void *ctx; 849 void *dmub; 850 }; 851 852 853 static inline bool dmub_rb_empty(struct dmub_rb *rb) 854 { 855 return (rb->wrpt == rb->rptr); 856 } 857 858 static inline bool dmub_rb_full(struct dmub_rb *rb) 859 { 860 uint32_t data_count; 861 862 if (rb->wrpt >= rb->rptr) 863 data_count = rb->wrpt - rb->rptr; 864 else 865 data_count = rb->capacity - (rb->rptr - rb->wrpt); 866 867 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 868 } 869 870 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 871 const union dmub_rb_cmd *cmd) 872 { 873 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 874 const uint64_t *src = (const uint64_t *)cmd; 875 int i; 876 877 if (dmub_rb_full(rb)) 878 return false; 879 880 // copying data 881 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 882 *dst++ = *src++; 883 884 rb->wrpt += DMUB_RB_CMD_SIZE; 885 886 if (rb->wrpt >= rb->capacity) 887 rb->wrpt %= rb->capacity; 888 889 return true; 890 } 891 892 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 893 const union dmub_rb_out_cmd *cmd) 894 { 895 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 896 const uint8_t *src = (uint8_t *)cmd; 897 898 if (dmub_rb_full(rb)) 899 return false; 900 901 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 902 903 rb->wrpt += DMUB_RB_CMD_SIZE; 904 905 if (rb->wrpt >= rb->capacity) 906 rb->wrpt %= rb->capacity; 907 908 return true; 909 } 910 911 static inline bool dmub_rb_front(struct dmub_rb *rb, 912 union dmub_rb_cmd *cmd) 913 { 914 uint8_t *rd_ptr = (uint8_t *)rb->base_address + rb->rptr; 915 916 if (dmub_rb_empty(rb)) 917 return false; 918 919 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 920 921 return true; 922 } 923 924 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 925 union dmub_rb_out_cmd *cmd) 926 { 927 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 928 uint64_t *dst = (uint64_t *)cmd; 929 int i; 930 931 if (dmub_rb_empty(rb)) 932 return false; 933 934 // copying data 935 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 936 *dst++ = *src++; 937 938 return true; 939 } 940 941 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 942 { 943 if (dmub_rb_empty(rb)) 944 return false; 945 946 rb->rptr += DMUB_RB_CMD_SIZE; 947 948 if (rb->rptr >= rb->capacity) 949 rb->rptr %= rb->capacity; 950 951 return true; 952 } 953 954 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 955 { 956 uint32_t rptr = rb->rptr; 957 uint32_t wptr = rb->wrpt; 958 959 while (rptr != wptr) { 960 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 961 int i; 962 963 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 964 *data++; 965 966 rptr += DMUB_RB_CMD_SIZE; 967 if (rptr >= rb->capacity) 968 rptr %= rb->capacity; 969 } 970 } 971 972 static inline void dmub_rb_init(struct dmub_rb *rb, 973 struct dmub_rb_init_params *init_params) 974 { 975 rb->base_address = init_params->base_address; 976 rb->capacity = init_params->capacity; 977 rb->rptr = init_params->read_ptr; 978 rb->wrpt = init_params->write_ptr; 979 } 980 981 #if defined(__cplusplus) 982 } 983 #endif 984 985 //============================================================================== 986 //</DMUB_RB>==================================================================== 987 //============================================================================== 988 989 #endif /* _DMUB_CMD_H_ */ 990