1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 #include <stdarg.h> 34 35 #include "atomfirmware.h" 36 37 /* Firmware versioning. */ 38 #ifdef DMUB_EXPOSE_VERSION 39 #define DMUB_FW_VERSION_GIT_HASH 0x4e5b2f46f 40 #define DMUB_FW_VERSION_MAJOR 0 41 #define DMUB_FW_VERSION_MINOR 0 42 #define DMUB_FW_VERSION_REVISION 29 43 #define DMUB_FW_VERSION_TEST 0 44 #define DMUB_FW_VERSION_VBIOS 0 45 #define DMUB_FW_VERSION_HOTFIX 0 46 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 47 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 48 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 49 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 50 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 51 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 52 53 #endif 54 55 //<DMUB_TYPES>================================================================== 56 /* Basic type definitions. */ 57 58 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 59 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 60 #define SET_ABM_PIPE_NORMAL 1 61 62 /* Maximum number of streams on any ASIC. */ 63 #define DMUB_MAX_STREAMS 6 64 65 /* Maximum number of planes on any ASIC. */ 66 #define DMUB_MAX_PLANES 6 67 68 #ifndef PHYSICAL_ADDRESS_LOC 69 #define PHYSICAL_ADDRESS_LOC union large_integer 70 #endif 71 72 #if defined(__cplusplus) 73 extern "C" { 74 #endif 75 76 #ifndef dmub_memcpy 77 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 78 #endif 79 80 #ifndef dmub_memset 81 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 82 #endif 83 84 #ifndef dmub_udelay 85 #define dmub_udelay(microseconds) udelay(microseconds) 86 #endif 87 88 union dmub_addr { 89 struct { 90 uint32_t low_part; 91 uint32_t high_part; 92 } u; 93 uint64_t quad_part; 94 }; 95 96 union dmub_psr_debug_flags { 97 struct { 98 uint32_t visual_confirm : 1; 99 uint32_t use_hw_lock_mgr : 1; 100 } bitfields; 101 102 uint32_t u32All; 103 }; 104 105 #if defined(__cplusplus) 106 } 107 #endif 108 109 110 111 //============================================================================== 112 //</DMUB_TYPES>================================================================= 113 //============================================================================== 114 //< DMUB_META>================================================================== 115 //============================================================================== 116 #pragma pack(push, 1) 117 118 /* Magic value for identifying dmub_fw_meta_info */ 119 #define DMUB_FW_META_MAGIC 0x444D5542 120 121 /* Offset from the end of the file to the dmub_fw_meta_info */ 122 #define DMUB_FW_META_OFFSET 0x24 123 124 /** 125 * struct dmub_fw_meta_info - metadata associated with fw binary 126 * 127 * NOTE: This should be considered a stable API. Fields should 128 * not be repurposed or reordered. New fields should be 129 * added instead to extend the structure. 130 * 131 * @magic_value: magic value identifying DMUB firmware meta info 132 * @fw_region_size: size of the firmware state region 133 * @trace_buffer_size: size of the tracebuffer region 134 * @fw_version: the firmware version information 135 * @dal_fw: 1 if the firmware is DAL 136 */ 137 struct dmub_fw_meta_info { 138 uint32_t magic_value; 139 uint32_t fw_region_size; 140 uint32_t trace_buffer_size; 141 uint32_t fw_version; 142 uint8_t dal_fw; 143 uint8_t reserved[3]; 144 }; 145 146 /* Ensure that the structure remains 64 bytes. */ 147 union dmub_fw_meta { 148 struct dmub_fw_meta_info info; 149 uint8_t reserved[64]; 150 }; 151 152 #pragma pack(pop) 153 154 //============================================================================== 155 //< DMUB_STATUS>================================================================ 156 //============================================================================== 157 158 /** 159 * DMCUB scratch registers can be used to determine firmware status. 160 * Current scratch register usage is as follows: 161 * 162 * SCRATCH0: FW Boot Status register 163 * SCRATCH15: FW Boot Options register 164 */ 165 166 /* Register bit definition for SCRATCH0 */ 167 union dmub_fw_boot_status { 168 struct { 169 uint32_t dal_fw : 1; 170 uint32_t mailbox_rdy : 1; 171 uint32_t optimized_init_done : 1; 172 uint32_t reserved : 29; 173 } bits; 174 uint32_t all; 175 }; 176 177 enum dmub_fw_boot_status_bit { 178 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), 179 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), 180 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 181 }; 182 183 /* Register bit definition for SCRATCH15 */ 184 union dmub_fw_boot_options { 185 struct { 186 uint32_t pemu_env : 1; 187 uint32_t fpga_env : 1; 188 uint32_t optimized_init : 1; 189 uint32_t reserved : 29; 190 } bits; 191 uint32_t all; 192 }; 193 194 enum dmub_fw_boot_options_bit { 195 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), 196 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), 197 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 198 }; 199 200 //============================================================================== 201 //</DMUB_STATUS>================================================================ 202 //============================================================================== 203 //< DMUB_VBIOS>================================================================= 204 //============================================================================== 205 206 /* 207 * Command IDs should be treated as stable ABI. 208 * Do not reuse or modify IDs. 209 */ 210 211 enum dmub_cmd_vbios_type { 212 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 213 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 214 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 215 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 216 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 217 }; 218 219 //============================================================================== 220 //</DMUB_VBIOS>================================================================= 221 //============================================================================== 222 //< DMUB_GPINT>================================================================= 223 //============================================================================== 224 225 /** 226 * The shifts and masks below may alternatively be used to format and read 227 * the command register bits. 228 */ 229 230 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 231 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 232 233 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 234 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 235 236 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 237 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 238 239 /** 240 * Command responses. 241 */ 242 243 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 244 245 /** 246 * The register format for sending a command via the GPINT. 247 */ 248 union dmub_gpint_data_register { 249 struct { 250 uint32_t param : 16; 251 uint32_t command_code : 12; 252 uint32_t status : 4; 253 } bits; 254 uint32_t all; 255 }; 256 257 /* 258 * Command IDs should be treated as stable ABI. 259 * Do not reuse or modify IDs. 260 */ 261 262 enum dmub_gpint_command { 263 DMUB_GPINT__INVALID_COMMAND = 0, 264 DMUB_GPINT__GET_FW_VERSION = 1, 265 DMUB_GPINT__STOP_FW = 2, 266 DMUB_GPINT__GET_PSR_STATE = 7, 267 /** 268 * DESC: Notifies DMCUB of the currently active streams. 269 * ARGS: Stream mask, 1 bit per active stream index. 270 */ 271 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 272 }; 273 274 //============================================================================== 275 //</DMUB_GPINT>================================================================= 276 //============================================================================== 277 //< DMUB_CMD>=================================================================== 278 //============================================================================== 279 280 #define DMUB_RB_CMD_SIZE 64 281 #define DMUB_RB_MAX_ENTRY 128 282 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 283 #define REG_SET_MASK 0xFFFF 284 285 /* 286 * Command IDs should be treated as stable ABI. 287 * Do not reuse or modify IDs. 288 */ 289 290 enum dmub_cmd_type { 291 DMUB_CMD__NULL = 0, 292 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 293 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 294 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 295 DMUB_CMD__REG_REG_WAIT = 4, 296 DMUB_CMD__PLAT_54186_WA = 5, 297 DMUB_CMD__PSR = 64, 298 DMUB_CMD__ABM = 66, 299 DMUB_CMD__HW_LOCK = 69, 300 DMUB_CMD__VBIOS = 128, 301 }; 302 303 #pragma pack(push, 1) 304 305 struct dmub_cmd_header { 306 unsigned int type : 8; 307 unsigned int sub_type : 8; 308 unsigned int reserved0 : 8; 309 unsigned int payload_bytes : 6; /* up to 60 bytes */ 310 unsigned int reserved1 : 2; 311 }; 312 313 /* 314 * Read modify write 315 * 316 * 60 payload bytes can hold up to 5 sets of read modify writes, 317 * each take 3 dwords. 318 * 319 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 320 * 321 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 322 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 323 */ 324 struct dmub_cmd_read_modify_write_sequence { 325 uint32_t addr; 326 uint32_t modify_mask; 327 uint32_t modify_value; 328 }; 329 330 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 331 struct dmub_rb_cmd_read_modify_write { 332 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 333 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 334 }; 335 336 /* 337 * Update a register with specified masks and values sequeunce 338 * 339 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 340 * 341 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 342 * 343 * 344 * USE CASE: 345 * 1. auto-increment register where additional read would update pointer and produce wrong result 346 * 2. toggle a bit without read in the middle 347 */ 348 349 struct dmub_cmd_reg_field_update_sequence { 350 uint32_t modify_mask; // 0xffff'ffff to skip initial read 351 uint32_t modify_value; 352 }; 353 354 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 355 struct dmub_rb_cmd_reg_field_update_sequence { 356 struct dmub_cmd_header header; 357 uint32_t addr; 358 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 359 }; 360 361 /* 362 * Burst write 363 * 364 * support use case such as writing out LUTs. 365 * 366 * 60 payload bytes can hold up to 14 values to write to given address 367 * 368 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 369 */ 370 #define DMUB_BURST_WRITE_VALUES__MAX 14 371 struct dmub_rb_cmd_burst_write { 372 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 373 uint32_t addr; 374 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 375 }; 376 377 378 struct dmub_rb_cmd_common { 379 struct dmub_cmd_header header; 380 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 381 }; 382 383 struct dmub_cmd_reg_wait_data { 384 uint32_t addr; 385 uint32_t mask; 386 uint32_t condition_field_value; 387 uint32_t time_out_us; 388 }; 389 390 struct dmub_rb_cmd_reg_wait { 391 struct dmub_cmd_header header; 392 struct dmub_cmd_reg_wait_data reg_wait; 393 }; 394 395 struct dmub_cmd_PLAT_54186_wa { 396 uint32_t DCSURF_SURFACE_CONTROL; 397 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 398 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 399 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 400 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 401 struct { 402 uint8_t hubp_inst : 4; 403 uint8_t tmz_surface : 1; 404 uint8_t immediate :1; 405 uint8_t vmid : 4; 406 uint8_t grph_stereo : 1; 407 uint32_t reserved : 21; 408 } flip_params; 409 uint32_t reserved[9]; 410 }; 411 412 struct dmub_rb_cmd_PLAT_54186_wa { 413 struct dmub_cmd_header header; 414 struct dmub_cmd_PLAT_54186_wa flip; 415 }; 416 417 struct dmub_cmd_digx_encoder_control_data { 418 union dig_encoder_control_parameters_v1_5 dig; 419 }; 420 421 struct dmub_rb_cmd_digx_encoder_control { 422 struct dmub_cmd_header header; 423 struct dmub_cmd_digx_encoder_control_data encoder_control; 424 }; 425 426 struct dmub_cmd_set_pixel_clock_data { 427 struct set_pixel_clock_parameter_v1_7 clk; 428 }; 429 430 struct dmub_rb_cmd_set_pixel_clock { 431 struct dmub_cmd_header header; 432 struct dmub_cmd_set_pixel_clock_data pixel_clock; 433 }; 434 435 struct dmub_cmd_enable_disp_power_gating_data { 436 struct enable_disp_power_gating_parameters_v2_1 pwr; 437 }; 438 439 struct dmub_rb_cmd_enable_disp_power_gating { 440 struct dmub_cmd_header header; 441 struct dmub_cmd_enable_disp_power_gating_data power_gating; 442 }; 443 444 struct dmub_cmd_dig1_transmitter_control_data { 445 struct dig_transmitter_control_parameters_v1_6 dig; 446 }; 447 448 struct dmub_rb_cmd_dig1_transmitter_control { 449 struct dmub_cmd_header header; 450 struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 451 }; 452 453 struct dmub_rb_cmd_dpphy_init { 454 struct dmub_cmd_header header; 455 uint8_t reserved[60]; 456 }; 457 458 /* 459 * Command IDs should be treated as stable ABI. 460 * Do not reuse or modify IDs. 461 */ 462 463 enum dmub_cmd_psr_type { 464 DMUB_CMD__PSR_SET_VERSION = 0, 465 DMUB_CMD__PSR_COPY_SETTINGS = 1, 466 DMUB_CMD__PSR_ENABLE = 2, 467 DMUB_CMD__PSR_DISABLE = 3, 468 DMUB_CMD__PSR_SET_LEVEL = 4, 469 }; 470 471 enum psr_version { 472 PSR_VERSION_1 = 0, 473 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 474 }; 475 476 struct dmub_cmd_psr_copy_settings_data { 477 union dmub_psr_debug_flags debug; 478 uint16_t psr_level; 479 uint8_t dpp_inst; 480 uint8_t mpcc_inst; 481 uint8_t opp_inst; 482 uint8_t otg_inst; 483 uint8_t digfe_inst; 484 uint8_t digbe_inst; 485 uint8_t dpphy_inst; 486 uint8_t aux_inst; 487 uint8_t smu_optimizations_en; 488 uint8_t frame_delay; 489 uint8_t frame_cap_ind; 490 uint8_t pad[3]; 491 uint16_t init_sdp_deadline; 492 uint16_t pad2; 493 }; 494 495 struct dmub_rb_cmd_psr_copy_settings { 496 struct dmub_cmd_header header; 497 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 498 }; 499 500 struct dmub_cmd_psr_set_level_data { 501 uint16_t psr_level; 502 uint8_t pad[2]; 503 }; 504 505 struct dmub_rb_cmd_psr_set_level { 506 struct dmub_cmd_header header; 507 struct dmub_cmd_psr_set_level_data psr_set_level_data; 508 }; 509 510 struct dmub_rb_cmd_psr_enable { 511 struct dmub_cmd_header header; 512 }; 513 514 struct dmub_cmd_psr_set_version_data { 515 enum psr_version version; // PSR version 1 or 2 516 }; 517 518 struct dmub_rb_cmd_psr_set_version { 519 struct dmub_cmd_header header; 520 struct dmub_cmd_psr_set_version_data psr_set_version_data; 521 }; 522 523 union dmub_hw_lock_flags { 524 struct { 525 uint8_t lock_pipe : 1; 526 uint8_t lock_cursor : 1; 527 uint8_t lock_dig : 1; 528 uint8_t triple_buffer_lock : 1; 529 } bits; 530 531 uint8_t u8All; 532 }; 533 534 struct dmub_hw_lock_inst_flags { 535 uint8_t otg_inst; 536 uint8_t opp_inst; 537 uint8_t dig_inst; 538 uint8_t pad; 539 }; 540 541 enum hw_lock_client { 542 HW_LOCK_CLIENT_DRIVER = 0, 543 HW_LOCK_CLIENT_FW, 544 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 545 }; 546 547 struct dmub_cmd_lock_hw_data { 548 enum hw_lock_client client; 549 struct dmub_hw_lock_inst_flags inst_flags; 550 union dmub_hw_lock_flags hw_locks; 551 uint8_t lock; 552 uint8_t should_release; 553 uint8_t pad; 554 }; 555 556 struct dmub_rb_cmd_lock_hw { 557 struct dmub_cmd_header header; 558 struct dmub_cmd_lock_hw_data lock_hw_data; 559 }; 560 561 enum dmub_cmd_abm_type { 562 DMUB_CMD__ABM_INIT_CONFIG = 0, 563 DMUB_CMD__ABM_SET_PIPE = 1, 564 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 565 DMUB_CMD__ABM_SET_LEVEL = 3, 566 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 567 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 568 }; 569 570 #define NUM_AMBI_LEVEL 5 571 #define NUM_AGGR_LEVEL 4 572 #define NUM_POWER_FN_SEGS 8 573 #define NUM_BL_CURVE_SEGS 16 574 575 /* 576 * Parameters for ABM2.4 algorithm. 577 * Padded explicitly to 32-bit boundary. 578 */ 579 struct abm_config_table { 580 /* Parameters for crgb conversion */ 581 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 582 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 15B 583 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 31B 584 585 /* Parameters for custom curve */ 586 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 47B 587 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 79B 588 589 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 111B 590 uint16_t min_abm_backlight; // 121B 591 592 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 123B 593 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 143B 594 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 163B 595 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 183B 596 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 203B 597 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 207B 598 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 211B 599 uint8_t min_knee[NUM_AGGR_LEVEL]; // 215B 600 uint8_t max_knee[NUM_AGGR_LEVEL]; // 219B 601 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 223B 602 uint8_t pad3[3]; // 228B 603 }; 604 605 struct dmub_cmd_abm_set_pipe_data { 606 uint8_t otg_inst; 607 uint8_t panel_inst; 608 uint8_t set_pipe_option; 609 uint8_t ramping_boundary; // TODO: Remove this 610 }; 611 612 struct dmub_rb_cmd_abm_set_pipe { 613 struct dmub_cmd_header header; 614 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 615 }; 616 617 struct dmub_cmd_abm_set_backlight_data { 618 uint32_t frame_ramp; 619 uint32_t backlight_user_level; 620 }; 621 622 struct dmub_rb_cmd_abm_set_backlight { 623 struct dmub_cmd_header header; 624 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 625 }; 626 627 struct dmub_cmd_abm_set_level_data { 628 uint32_t level; 629 }; 630 631 struct dmub_rb_cmd_abm_set_level { 632 struct dmub_cmd_header header; 633 struct dmub_cmd_abm_set_level_data abm_set_level_data; 634 }; 635 636 struct dmub_cmd_abm_set_ambient_level_data { 637 uint32_t ambient_lux; 638 }; 639 640 struct dmub_rb_cmd_abm_set_ambient_level { 641 struct dmub_cmd_header header; 642 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 643 }; 644 645 struct dmub_cmd_abm_set_pwm_frac_data { 646 uint32_t fractional_pwm; 647 }; 648 649 struct dmub_rb_cmd_abm_set_pwm_frac { 650 struct dmub_cmd_header header; 651 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 652 }; 653 654 struct dmub_cmd_abm_init_config_data { 655 union dmub_addr src; 656 uint16_t bytes; 657 }; 658 659 struct dmub_rb_cmd_abm_init_config { 660 struct dmub_cmd_header header; 661 struct dmub_cmd_abm_init_config_data abm_init_config_data; 662 }; 663 664 union dmub_rb_cmd { 665 struct dmub_rb_cmd_lock_hw lock_hw; 666 struct dmub_rb_cmd_read_modify_write read_modify_write; 667 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 668 struct dmub_rb_cmd_burst_write burst_write; 669 struct dmub_rb_cmd_reg_wait reg_wait; 670 struct dmub_rb_cmd_common cmd_common; 671 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 672 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 673 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 674 struct dmub_rb_cmd_dpphy_init dpphy_init; 675 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 676 struct dmub_rb_cmd_psr_set_version psr_set_version; 677 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 678 struct dmub_rb_cmd_psr_enable psr_enable; 679 struct dmub_rb_cmd_psr_set_level psr_set_level; 680 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 681 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 682 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 683 struct dmub_rb_cmd_abm_set_level abm_set_level; 684 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 685 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 686 struct dmub_rb_cmd_abm_init_config abm_init_config; 687 }; 688 689 #pragma pack(pop) 690 691 692 //============================================================================== 693 //</DMUB_CMD>=================================================================== 694 //============================================================================== 695 //< DMUB_RB>==================================================================== 696 //============================================================================== 697 698 #if defined(__cplusplus) 699 extern "C" { 700 #endif 701 702 struct dmub_rb_init_params { 703 void *ctx; 704 void *base_address; 705 uint32_t capacity; 706 uint32_t read_ptr; 707 uint32_t write_ptr; 708 }; 709 710 struct dmub_rb { 711 void *base_address; 712 uint32_t data_count; 713 uint32_t rptr; 714 uint32_t wrpt; 715 uint32_t capacity; 716 717 void *ctx; 718 void *dmub; 719 }; 720 721 722 static inline bool dmub_rb_empty(struct dmub_rb *rb) 723 { 724 return (rb->wrpt == rb->rptr); 725 } 726 727 static inline bool dmub_rb_full(struct dmub_rb *rb) 728 { 729 uint32_t data_count; 730 731 if (rb->wrpt >= rb->rptr) 732 data_count = rb->wrpt - rb->rptr; 733 else 734 data_count = rb->capacity - (rb->rptr - rb->wrpt); 735 736 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 737 } 738 739 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 740 const union dmub_rb_cmd *cmd) 741 { 742 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 743 const uint64_t *src = (const uint64_t *)cmd; 744 int i; 745 746 if (dmub_rb_full(rb)) 747 return false; 748 749 // copying data 750 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 751 *dst++ = *src++; 752 753 rb->wrpt += DMUB_RB_CMD_SIZE; 754 755 if (rb->wrpt >= rb->capacity) 756 rb->wrpt %= rb->capacity; 757 758 return true; 759 } 760 761 static inline bool dmub_rb_front(struct dmub_rb *rb, 762 union dmub_rb_cmd *cmd) 763 { 764 uint8_t *rd_ptr = (uint8_t *)rb->base_address + rb->rptr; 765 766 if (dmub_rb_empty(rb)) 767 return false; 768 769 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 770 771 return true; 772 } 773 774 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 775 { 776 if (dmub_rb_empty(rb)) 777 return false; 778 779 rb->rptr += DMUB_RB_CMD_SIZE; 780 781 if (rb->rptr >= rb->capacity) 782 rb->rptr %= rb->capacity; 783 784 return true; 785 } 786 787 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 788 { 789 uint32_t rptr = rb->rptr; 790 uint32_t wptr = rb->wrpt; 791 792 while (rptr != wptr) { 793 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 794 //uint64_t volatile *p = (uint64_t volatile *)data; 795 uint64_t temp; 796 int i; 797 798 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 799 temp = *data++; 800 801 rptr += DMUB_RB_CMD_SIZE; 802 if (rptr >= rb->capacity) 803 rptr %= rb->capacity; 804 } 805 } 806 807 static inline void dmub_rb_init(struct dmub_rb *rb, 808 struct dmub_rb_init_params *init_params) 809 { 810 rb->base_address = init_params->base_address; 811 rb->capacity = init_params->capacity; 812 rb->rptr = init_params->read_ptr; 813 rb->wrpt = init_params->write_ptr; 814 } 815 816 #if defined(__cplusplus) 817 } 818 #endif 819 820 //============================================================================== 821 //</DMUB_RB>==================================================================== 822 //============================================================================== 823 824 #endif /* _DMUB_CMD_H_ */ 825