1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef _DMUB_CMD_H_
27 #define _DMUB_CMD_H_
28 
29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4)
30 #include "dmub_fw_types.h"
31 #include "include_legacy/atomfirmware.h"
32 
33 #if defined(_TEST_HARNESS)
34 #include <string.h>
35 #endif
36 #else
37 
38 #include <asm/byteorder.h>
39 #include <linux/types.h>
40 #include <linux/string.h>
41 #include <linux/delay.h>
42 #include <stdarg.h>
43 
44 #include "atomfirmware.h"
45 
46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4)
47 
48 /* Firmware versioning. */
49 #ifdef DMUB_EXPOSE_VERSION
50 #define DMUB_FW_VERSION_GIT_HASH 0xf3da2b656
51 #define DMUB_FW_VERSION_MAJOR 0
52 #define DMUB_FW_VERSION_MINOR 0
53 #define DMUB_FW_VERSION_REVISION 71
54 #define DMUB_FW_VERSION_TEST 0
55 #define DMUB_FW_VERSION_VBIOS 0
56 #define DMUB_FW_VERSION_HOTFIX 0
57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \
58 		((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \
59 		((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \
60 		((DMUB_FW_VERSION_TEST & 0x1) << 7) | \
61 		((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \
62 		(DMUB_FW_VERSION_HOTFIX & 0x3F))
63 
64 #endif
65 
66 //<DMUB_TYPES>==================================================================
67 /* Basic type definitions. */
68 
69 #define __forceinline inline
70 
71 /**
72  * Flag from driver to indicate that ABM should be disabled gradually
73  * by slowly reversing all backlight programming and pixel compensation.
74  */
75 #define SET_ABM_PIPE_GRADUALLY_DISABLE           0
76 
77 /**
78  * Flag from driver to indicate that ABM should be disabled immediately
79  * and undo all backlight programming and pixel compensation.
80  */
81 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE         255
82 
83 /**
84  * Flag from driver to indicate that ABM should be disabled immediately
85  * and keep the current backlight programming and pixel compensation.
86  */
87 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
88 
89 /**
90  * Flag from driver to set the current ABM pipe index or ABM operating level.
91  */
92 #define SET_ABM_PIPE_NORMAL                      1
93 
94 /**
95  * Number of ambient light levels in ABM algorithm.
96  */
97 #define NUM_AMBI_LEVEL                  5
98 
99 /**
100  * Number of operating/aggression levels in ABM algorithm.
101  */
102 #define NUM_AGGR_LEVEL                  4
103 
104 /**
105  * Number of segments in the gamma curve.
106  */
107 #define NUM_POWER_FN_SEGS               8
108 
109 /**
110  * Number of segments in the backlight curve.
111  */
112 #define NUM_BL_CURVE_SEGS               16
113 
114 /* Maximum number of streams on any ASIC. */
115 #define DMUB_MAX_STREAMS 6
116 
117 /* Maximum number of planes on any ASIC. */
118 #define DMUB_MAX_PLANES 6
119 
120 /* Trace buffer offset for entry */
121 #define TRACE_BUFFER_ENTRY_OFFSET  16
122 
123 /**
124  *
125  * PSR control version legacy
126  */
127 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
128 /**
129  * PSR control version with multi edp support
130  */
131 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
132 
133 
134 /**
135  * ABM control version legacy
136  */
137 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
138 
139 /**
140  * ABM control version with multi edp support
141  */
142 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
143 
144 /**
145  * Physical framebuffer address location, 64-bit.
146  */
147 #ifndef PHYSICAL_ADDRESS_LOC
148 #define PHYSICAL_ADDRESS_LOC union large_integer
149 #endif
150 
151 /**
152  * OS/FW agnostic memcpy
153  */
154 #ifndef dmub_memcpy
155 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
156 #endif
157 
158 /**
159  * OS/FW agnostic memset
160  */
161 #ifndef dmub_memset
162 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
163 #endif
164 
165 #if defined(__cplusplus)
166 extern "C" {
167 #endif
168 
169 /**
170  * OS/FW agnostic udelay
171  */
172 #ifndef dmub_udelay
173 #define dmub_udelay(microseconds) udelay(microseconds)
174 #endif
175 
176 /**
177  * Number of nanoseconds per DMUB tick.
178  * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default.
179  * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true.
180  */
181 #define NS_PER_DMUB_TICK 10
182 
183 /**
184  * union dmub_addr - DMUB physical/virtual 64-bit address.
185  */
186 union dmub_addr {
187 	struct {
188 		uint32_t low_part; /**< Lower 32 bits */
189 		uint32_t high_part; /**< Upper 32 bits */
190 	} u; /*<< Low/high bit access */
191 	uint64_t quad_part; /*<< 64 bit address */
192 };
193 
194 /**
195  * Flags that can be set by driver to change some PSR behaviour.
196  */
197 union dmub_psr_debug_flags {
198 	/**
199 	 * Debug flags.
200 	 */
201 	struct {
202 		/**
203 		 * Enable visual confirm in FW.
204 		 */
205 		uint32_t visual_confirm : 1;
206 		/**
207 		 * Use HW Lock Mgr object to do HW locking in FW.
208 		 */
209 		uint32_t use_hw_lock_mgr : 1;
210 
211 		/**
212 		 * Unused.
213 		 * TODO: Remove.
214 		 */
215 		uint32_t log_line_nums : 1;
216 	} bitfields;
217 
218 	/**
219 	 * Union for debug flags.
220 	 */
221 	uint32_t u32All;
222 };
223 
224 /**
225  * DMUB feature capabilities.
226  * After DMUB init, driver will query FW capabilities prior to enabling certain features.
227  */
228 struct dmub_feature_caps {
229 	/**
230 	 * Max PSR version supported by FW.
231 	 */
232 	uint8_t psr;
233 	uint8_t reserved[7];
234 };
235 
236 #if defined(__cplusplus)
237 }
238 #endif
239 
240 //==============================================================================
241 //</DMUB_TYPES>=================================================================
242 //==============================================================================
243 //< DMUB_META>==================================================================
244 //==============================================================================
245 #pragma pack(push, 1)
246 
247 /* Magic value for identifying dmub_fw_meta_info */
248 #define DMUB_FW_META_MAGIC 0x444D5542
249 
250 /* Offset from the end of the file to the dmub_fw_meta_info */
251 #define DMUB_FW_META_OFFSET 0x24
252 
253 /**
254  * struct dmub_fw_meta_info - metadata associated with fw binary
255  *
256  * NOTE: This should be considered a stable API. Fields should
257  *       not be repurposed or reordered. New fields should be
258  *       added instead to extend the structure.
259  *
260  * @magic_value: magic value identifying DMUB firmware meta info
261  * @fw_region_size: size of the firmware state region
262  * @trace_buffer_size: size of the tracebuffer region
263  * @fw_version: the firmware version information
264  * @dal_fw: 1 if the firmware is DAL
265  */
266 struct dmub_fw_meta_info {
267 	uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
268 	uint32_t fw_region_size; /**< size of the firmware state region */
269 	uint32_t trace_buffer_size; /**< size of the tracebuffer region */
270 	uint32_t fw_version; /**< the firmware version information */
271 	uint8_t dal_fw; /**< 1 if the firmware is DAL */
272 	uint8_t reserved[3]; /**< padding bits */
273 };
274 
275 /**
276  * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
277  */
278 union dmub_fw_meta {
279 	struct dmub_fw_meta_info info; /**< metadata info */
280 	uint8_t reserved[64]; /**< padding bits */
281 };
282 
283 #pragma pack(pop)
284 
285 //==============================================================================
286 //< DMUB Trace Buffer>================================================================
287 //==============================================================================
288 /**
289  * dmub_trace_code_t - firmware trace code, 32-bits
290  */
291 typedef uint32_t dmub_trace_code_t;
292 
293 /**
294  * struct dmcub_trace_buf_entry - Firmware trace entry
295  */
296 struct dmcub_trace_buf_entry {
297 	dmub_trace_code_t trace_code; /**< trace code for the event */
298 	uint32_t tick_count; /**< the tick count at time of trace */
299 	uint32_t param0; /**< trace defined parameter 0 */
300 	uint32_t param1; /**< trace defined parameter 1 */
301 };
302 
303 //==============================================================================
304 //< DMUB_STATUS>================================================================
305 //==============================================================================
306 
307 /**
308  * DMCUB scratch registers can be used to determine firmware status.
309  * Current scratch register usage is as follows:
310  *
311  * SCRATCH0: FW Boot Status register
312  * SCRATCH5: LVTMA Status Register
313  * SCRATCH15: FW Boot Options register
314  */
315 
316 /**
317  * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
318  */
319 union dmub_fw_boot_status {
320 	struct {
321 		uint32_t dal_fw : 1; /**< 1 if DAL FW */
322 		uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
323 		uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
324 		uint32_t restore_required : 1; /**< 1 if driver should call restore */
325 	} bits; /**< status bits */
326 	uint32_t all; /**< 32-bit access to status bits */
327 };
328 
329 /**
330  * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
331  */
332 enum dmub_fw_boot_status_bit {
333 	DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
334 	DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
335 	DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
336 	DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
337 };
338 
339 /* Register bit definition for SCRATCH5 */
340 union dmub_lvtma_status {
341 	struct {
342 		uint32_t psp_ok : 1;
343 		uint32_t edp_on : 1;
344 		uint32_t reserved : 30;
345 	} bits;
346 	uint32_t all;
347 };
348 
349 enum dmub_lvtma_status_bit {
350 	DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
351 	DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
352 };
353 
354 /**
355  * union dmub_fw_boot_options - Boot option definitions for SCRATCH15
356  */
357 union dmub_fw_boot_options {
358 	struct {
359 		uint32_t pemu_env : 1; /**< 1 if PEMU */
360 		uint32_t fpga_env : 1; /**< 1 if FPGA */
361 		uint32_t optimized_init : 1; /**< 1 if optimized init */
362 		uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
363 		uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
364 		uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
365 		uint32_t z10_disable: 1; /**< 1 to disable z10 */
366 		uint32_t reserved : 25; /**< reserved */
367 	} bits; /**< boot bits */
368 	uint32_t all; /**< 32-bit access to bits */
369 };
370 
371 enum dmub_fw_boot_options_bit {
372 	DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
373 	DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
374 	DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
375 };
376 
377 //==============================================================================
378 //</DMUB_STATUS>================================================================
379 //==============================================================================
380 //< DMUB_VBIOS>=================================================================
381 //==============================================================================
382 
383 /*
384  * enum dmub_cmd_vbios_type - VBIOS commands.
385  *
386  * Command IDs should be treated as stable ABI.
387  * Do not reuse or modify IDs.
388  */
389 enum dmub_cmd_vbios_type {
390 	/**
391 	 * Configures the DIG encoder.
392 	 */
393 	DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
394 	/**
395 	 * Controls the PHY.
396 	 */
397 	DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
398 	/**
399 	 * Sets the pixel clock/symbol clock.
400 	 */
401 	DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
402 	/**
403 	 * Enables or disables power gating.
404 	 */
405 	DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
406 	DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
407 };
408 
409 //==============================================================================
410 //</DMUB_VBIOS>=================================================================
411 //==============================================================================
412 //< DMUB_GPINT>=================================================================
413 //==============================================================================
414 
415 /**
416  * The shifts and masks below may alternatively be used to format and read
417  * the command register bits.
418  */
419 
420 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
421 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
422 
423 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
424 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
425 
426 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
427 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
428 
429 /**
430  * Command responses.
431  */
432 
433 /**
434  * Return response for DMUB_GPINT__STOP_FW command.
435  */
436 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
437 
438 /**
439  * union dmub_gpint_data_register - Format for sending a command via the GPINT.
440  */
441 union dmub_gpint_data_register {
442 	struct {
443 		uint32_t param : 16; /**< 16-bit parameter */
444 		uint32_t command_code : 12; /**< GPINT command */
445 		uint32_t status : 4; /**< Command status bit */
446 	} bits; /**< GPINT bit access */
447 	uint32_t all; /**< GPINT  32-bit access */
448 };
449 
450 /*
451  * enum dmub_gpint_command - GPINT command to DMCUB FW
452  *
453  * Command IDs should be treated as stable ABI.
454  * Do not reuse or modify IDs.
455  */
456 enum dmub_gpint_command {
457 	/**
458 	 * Invalid command, ignored.
459 	 */
460 	DMUB_GPINT__INVALID_COMMAND = 0,
461 	/**
462 	 * DESC: Queries the firmware version.
463 	 * RETURN: Firmware version.
464 	 */
465 	DMUB_GPINT__GET_FW_VERSION = 1,
466 	/**
467 	 * DESC: Halts the firmware.
468 	 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
469 	 */
470 	DMUB_GPINT__STOP_FW = 2,
471 	/**
472 	 * DESC: Get PSR state from FW.
473 	 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
474 	 */
475 	DMUB_GPINT__GET_PSR_STATE = 7,
476 	/**
477 	 * DESC: Notifies DMCUB of the currently active streams.
478 	 * ARGS: Stream mask, 1 bit per active stream index.
479 	 */
480 	DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
481 	/**
482 	 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
483 	 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
484 	 *       By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
485 	 * RETURN: PSR residency in milli-percent.
486 	 */
487 	DMUB_GPINT__PSR_RESIDENCY = 9,
488 };
489 
490 /**
491  * INBOX0 generic command definition
492  */
493 union dmub_inbox0_cmd_common {
494 	struct {
495 		uint32_t command_code: 8; /**< INBOX0 command code */
496 		uint32_t param: 24; /**< 24-bit parameter */
497 	} bits;
498 	uint32_t all;
499 };
500 
501 /**
502  * INBOX0 hw_lock command definition
503  */
504 union dmub_inbox0_cmd_lock_hw {
505 	struct {
506 		uint32_t command_code: 8;
507 
508 		/* NOTE: Must be have enough bits to match: enum hw_lock_client */
509 		uint32_t hw_lock_client: 1;
510 
511 		/* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
512 		uint32_t otg_inst: 3;
513 		uint32_t opp_inst: 3;
514 		uint32_t dig_inst: 3;
515 
516 		/* NOTE: Below fields must match with: union dmub_hw_lock_flags */
517 		uint32_t lock_pipe: 1;
518 		uint32_t lock_cursor: 1;
519 		uint32_t lock_dig: 1;
520 		uint32_t triple_buffer_lock: 1;
521 
522 		uint32_t lock: 1;				/**< Lock */
523 		uint32_t should_release: 1;		/**< Release */
524 		uint32_t reserved: 8; 			/**< Reserved for extending more clients, HW, etc. */
525 	} bits;
526 	uint32_t all;
527 };
528 
529 union dmub_inbox0_data_register {
530 	union dmub_inbox0_cmd_common inbox0_cmd_common;
531 	union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
532 };
533 
534 enum dmub_inbox0_command {
535 	/**
536 	 * DESC: Invalid command, ignored.
537 	 */
538 	DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
539 	/**
540 	 * DESC: Notification to acquire/release HW lock
541 	 * ARGS:
542 	 */
543 	DMUB_INBOX0_CMD__HW_LOCK = 1,
544 };
545 //==============================================================================
546 //</DMUB_GPINT>=================================================================
547 //==============================================================================
548 //< DMUB_CMD>===================================================================
549 //==============================================================================
550 
551 /**
552  * Size in bytes of each DMUB command.
553  */
554 #define DMUB_RB_CMD_SIZE 64
555 
556 /**
557  * Maximum number of items in the DMUB ringbuffer.
558  */
559 #define DMUB_RB_MAX_ENTRY 128
560 
561 /**
562  * Ringbuffer size in bytes.
563  */
564 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
565 
566 /**
567  * REG_SET mask for reg offload.
568  */
569 #define REG_SET_MASK 0xFFFF
570 
571 /*
572  * enum dmub_cmd_type - DMUB inbox command.
573  *
574  * Command IDs should be treated as stable ABI.
575  * Do not reuse or modify IDs.
576  */
577 enum dmub_cmd_type {
578 	/**
579 	 * Invalid command.
580 	 */
581 	DMUB_CMD__NULL = 0,
582 	/**
583 	 * Read modify write register sequence offload.
584 	 */
585 	DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
586 	/**
587 	 * Field update register sequence offload.
588 	 */
589 	DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
590 	/**
591 	 * Burst write sequence offload.
592 	 */
593 	DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
594 	/**
595 	 * Reg wait sequence offload.
596 	 */
597 	DMUB_CMD__REG_REG_WAIT = 4,
598 	/**
599 	 * Workaround to avoid HUBP underflow during NV12 playback.
600 	 */
601 	DMUB_CMD__PLAT_54186_WA = 5,
602 	/**
603 	 * Command type used to query FW feature caps.
604 	 */
605 	DMUB_CMD__QUERY_FEATURE_CAPS = 6,
606 	/**
607 	 * Command type used for all PSR commands.
608 	 */
609 	DMUB_CMD__PSR = 64,
610 	/**
611 	 * Command type used for all MALL commands.
612 	 */
613 	DMUB_CMD__MALL = 65,
614 	/**
615 	 * Command type used for all ABM commands.
616 	 */
617 	DMUB_CMD__ABM = 66,
618 	/**
619 	 * Command type used for HW locking in FW.
620 	 */
621 	DMUB_CMD__HW_LOCK = 69,
622 	/**
623 	 * Command type used to access DP AUX.
624 	 */
625 	DMUB_CMD__DP_AUX_ACCESS = 70,
626 	/**
627 	 * Command type used for OUTBOX1 notification enable
628 	 */
629 	DMUB_CMD__OUTBOX1_ENABLE = 71,
630 	/**
631 	 * Command type used for all idle optimization commands.
632 	 */
633 	DMUB_CMD__IDLE_OPT = 72,
634 	/**
635 	 * Command type used for all clock manager commands.
636 	 */
637 	DMUB_CMD__CLK_MGR = 73,
638 	/**
639 	 * Command type used for all panel control commands.
640 	 */
641 	DMUB_CMD__PANEL_CNTL = 74,
642 	/**
643 	 * Command type used for EDID CEA parsing
644 	 */
645 	DMUB_CMD__EDID_CEA = 79,
646 	/**
647 	 * Command type used for all VBIOS interface commands.
648 	 */
649 	DMUB_CMD__VBIOS = 128,
650 };
651 
652 /**
653  * enum dmub_out_cmd_type - DMUB outbox commands.
654  */
655 enum dmub_out_cmd_type {
656 	/**
657 	 * Invalid outbox command, ignored.
658 	 */
659 	DMUB_OUT_CMD__NULL = 0,
660 	/**
661 	 * Command type used for DP AUX Reply data notification
662 	 */
663 	DMUB_OUT_CMD__DP_AUX_REPLY = 1,
664 };
665 
666 #pragma pack(push, 1)
667 
668 /**
669  * struct dmub_cmd_header - Common command header fields.
670  */
671 struct dmub_cmd_header {
672 	unsigned int type : 8; /**< command type */
673 	unsigned int sub_type : 8; /**< command sub type */
674 	unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
675 	unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
676 	unsigned int reserved0 : 6; /**< reserved bits */
677 	unsigned int payload_bytes : 6;  /* payload excluding header - up to 60 bytes */
678 	unsigned int reserved1 : 2; /**< reserved bits */
679 };
680 
681 /*
682  * struct dmub_cmd_read_modify_write_sequence - Read modify write
683  *
684  * 60 payload bytes can hold up to 5 sets of read modify writes,
685  * each take 3 dwords.
686  *
687  * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
688  *
689  * modify_mask = 0xffff'ffff means all fields are going to be updated.  in this case
690  * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
691  */
692 struct dmub_cmd_read_modify_write_sequence {
693 	uint32_t addr; /**< register address */
694 	uint32_t modify_mask; /**< modify mask */
695 	uint32_t modify_value; /**< modify value */
696 };
697 
698 /**
699  * Maximum number of ops in read modify write sequence.
700  */
701 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
702 
703 /**
704  * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
705  */
706 struct dmub_rb_cmd_read_modify_write {
707 	struct dmub_cmd_header header;  /**< command header */
708 	/**
709 	 * Read modify write sequence.
710 	 */
711 	struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
712 };
713 
714 /*
715  * Update a register with specified masks and values sequeunce
716  *
717  * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
718  *
719  * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
720  *
721  *
722  * USE CASE:
723  *   1. auto-increment register where additional read would update pointer and produce wrong result
724  *   2. toggle a bit without read in the middle
725  */
726 
727 struct dmub_cmd_reg_field_update_sequence {
728 	uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
729 	uint32_t modify_value; /**< value to update with */
730 };
731 
732 /**
733  * Maximum number of ops in field update sequence.
734  */
735 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
736 
737 /**
738  * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
739  */
740 struct dmub_rb_cmd_reg_field_update_sequence {
741 	struct dmub_cmd_header header; /**< command header */
742 	uint32_t addr; /**< register address */
743 	/**
744 	 * Field update sequence.
745 	 */
746 	struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
747 };
748 
749 
750 /**
751  * Maximum number of burst write values.
752  */
753 #define DMUB_BURST_WRITE_VALUES__MAX  14
754 
755 /*
756  * struct dmub_rb_cmd_burst_write - Burst write
757  *
758  * support use case such as writing out LUTs.
759  *
760  * 60 payload bytes can hold up to 14 values to write to given address
761  *
762  * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
763  */
764 struct dmub_rb_cmd_burst_write {
765 	struct dmub_cmd_header header; /**< command header */
766 	uint32_t addr; /**< register start address */
767 	/**
768 	 * Burst write register values.
769 	 */
770 	uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
771 };
772 
773 /**
774  * struct dmub_rb_cmd_common - Common command header
775  */
776 struct dmub_rb_cmd_common {
777 	struct dmub_cmd_header header; /**< command header */
778 	/**
779 	 * Padding to RB_CMD_SIZE
780 	 */
781 	uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
782 };
783 
784 /**
785  * struct dmub_cmd_reg_wait_data - Register wait data
786  */
787 struct dmub_cmd_reg_wait_data {
788 	uint32_t addr; /**< Register address */
789 	uint32_t mask; /**< Mask for register bits */
790 	uint32_t condition_field_value; /**< Value to wait for */
791 	uint32_t time_out_us; /**< Time out for reg wait in microseconds */
792 };
793 
794 /**
795  * struct dmub_rb_cmd_reg_wait - Register wait command
796  */
797 struct dmub_rb_cmd_reg_wait {
798 	struct dmub_cmd_header header; /**< Command header */
799 	struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
800 };
801 
802 /**
803  * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
804  *
805  * Reprograms surface parameters to avoid underflow.
806  */
807 struct dmub_cmd_PLAT_54186_wa {
808 	uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
809 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
810 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
811 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
812 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
813 	struct {
814 		uint8_t hubp_inst : 4; /**< HUBP instance */
815 		uint8_t tmz_surface : 1; /**< TMZ enable or disable */
816 		uint8_t immediate :1; /**< Immediate flip */
817 		uint8_t vmid : 4; /**< VMID */
818 		uint8_t grph_stereo : 1; /**< 1 if stereo */
819 		uint32_t reserved : 21; /**< Reserved */
820 	} flip_params; /**< Pageflip parameters */
821 	uint32_t reserved[9]; /**< Reserved bits */
822 };
823 
824 /**
825  * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
826  */
827 struct dmub_rb_cmd_PLAT_54186_wa {
828 	struct dmub_cmd_header header; /**< Command header */
829 	struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
830 };
831 
832 /**
833  * struct dmub_rb_cmd_mall - MALL command data.
834  */
835 struct dmub_rb_cmd_mall {
836 	struct dmub_cmd_header header; /**< Common command header */
837 	union dmub_addr cursor_copy_src; /**< Cursor copy address */
838 	union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
839 	uint32_t tmr_delay; /**< Timer delay */
840 	uint32_t tmr_scale; /**< Timer scale */
841 	uint16_t cursor_width; /**< Cursor width in pixels */
842 	uint16_t cursor_pitch; /**< Cursor pitch in pixels */
843 	uint16_t cursor_height; /**< Cursor height in pixels */
844 	uint8_t cursor_bpp; /**< Cursor bits per pixel */
845 	uint8_t debug_bits; /**< Debug bits */
846 
847 	uint8_t reserved1; /**< Reserved bits */
848 	uint8_t reserved2; /**< Reserved bits */
849 };
850 
851 /**
852  * enum dmub_cmd_idle_opt_type - Idle optimization command type.
853  */
854 enum dmub_cmd_idle_opt_type {
855 	/**
856 	 * DCN hardware restore.
857 	 */
858 	DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
859 };
860 
861 /**
862  * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
863  */
864 struct dmub_rb_cmd_idle_opt_dcn_restore {
865 	struct dmub_cmd_header header; /**< header */
866 };
867 
868 /**
869  * struct dmub_clocks - Clock update notification.
870  */
871 struct dmub_clocks {
872 	uint32_t dispclk_khz; /**< dispclk kHz */
873 	uint32_t dppclk_khz; /**< dppclk kHz */
874 	uint32_t dcfclk_khz; /**< dcfclk kHz */
875 	uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
876 };
877 
878 /**
879  * enum dmub_cmd_clk_mgr_type - Clock manager commands.
880  */
881 enum dmub_cmd_clk_mgr_type {
882 	/**
883 	 * Notify DMCUB of clock update.
884 	 */
885 	DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
886 };
887 
888 /**
889  * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
890  */
891 struct dmub_rb_cmd_clk_mgr_notify_clocks {
892 	struct dmub_cmd_header header; /**< header */
893 	struct dmub_clocks clocks; /**< clock data */
894 };
895 
896 /**
897  * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
898  */
899 struct dmub_cmd_digx_encoder_control_data {
900 	union dig_encoder_control_parameters_v1_5 dig; /**< payload */
901 };
902 
903 /**
904  * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
905  */
906 struct dmub_rb_cmd_digx_encoder_control {
907 	struct dmub_cmd_header header;  /**< header */
908 	struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
909 };
910 
911 /**
912  * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
913  */
914 struct dmub_cmd_set_pixel_clock_data {
915 	struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
916 };
917 
918 /**
919  * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
920  */
921 struct dmub_rb_cmd_set_pixel_clock {
922 	struct dmub_cmd_header header; /**< header */
923 	struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
924 };
925 
926 /**
927  * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
928  */
929 struct dmub_cmd_enable_disp_power_gating_data {
930 	struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
931 };
932 
933 /**
934  * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
935  */
936 struct dmub_rb_cmd_enable_disp_power_gating {
937 	struct dmub_cmd_header header; /**< header */
938 	struct dmub_cmd_enable_disp_power_gating_data power_gating;  /**< payload */
939 };
940 
941 /**
942  * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
943  */
944 struct dmub_dig_transmitter_control_data_v1_7 {
945 	uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
946 	uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
947 	union {
948 		uint8_t digmode; /**< enum atom_encode_mode_def */
949 		uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
950 	} mode_laneset;
951 	uint8_t lanenum; /**< Number of lanes */
952 	union {
953 		uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
954 	} symclk_units;
955 	uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
956 	uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
957 	uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
958 	uint8_t reserved0; /**< For future use */
959 	uint8_t reserved1; /**< For future use */
960 	uint8_t reserved2[3]; /**< For future use */
961 	uint32_t reserved3[11]; /**< For future use */
962 };
963 
964 /**
965  * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
966  */
967 union dmub_cmd_dig1_transmitter_control_data {
968 	struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
969 	struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7;  /**< payload 1.7 */
970 };
971 
972 /**
973  * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
974  */
975 struct dmub_rb_cmd_dig1_transmitter_control {
976 	struct dmub_cmd_header header; /**< header */
977 	union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
978 };
979 
980 /**
981  * struct dmub_rb_cmd_dpphy_init - DPPHY init.
982  */
983 struct dmub_rb_cmd_dpphy_init {
984 	struct dmub_cmd_header header; /**< header */
985 	uint8_t reserved[60]; /**< reserved bits */
986 };
987 
988 /**
989  * enum dp_aux_request_action - DP AUX request command listing.
990  *
991  * 4 AUX request command bits are shifted to high nibble.
992  */
993 enum dp_aux_request_action {
994 	/** I2C-over-AUX write request */
995 	DP_AUX_REQ_ACTION_I2C_WRITE		= 0x00,
996 	/** I2C-over-AUX read request */
997 	DP_AUX_REQ_ACTION_I2C_READ		= 0x10,
998 	/** I2C-over-AUX write status request */
999 	DP_AUX_REQ_ACTION_I2C_STATUS_REQ	= 0x20,
1000 	/** I2C-over-AUX write request with MOT=1 */
1001 	DP_AUX_REQ_ACTION_I2C_WRITE_MOT		= 0x40,
1002 	/** I2C-over-AUX read request with MOT=1 */
1003 	DP_AUX_REQ_ACTION_I2C_READ_MOT		= 0x50,
1004 	/** I2C-over-AUX write status request with MOT=1 */
1005 	DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT	= 0x60,
1006 	/** Native AUX write request */
1007 	DP_AUX_REQ_ACTION_DPCD_WRITE		= 0x80,
1008 	/** Native AUX read request */
1009 	DP_AUX_REQ_ACTION_DPCD_READ		= 0x90
1010 };
1011 
1012 /**
1013  * enum aux_return_code_type - DP AUX process return code listing.
1014  */
1015 enum aux_return_code_type {
1016 	/** AUX process succeeded */
1017 	AUX_RET_SUCCESS = 0,
1018 	/** AUX process failed with unknown reason */
1019 	AUX_RET_ERROR_UNKNOWN,
1020 	/** AUX process completed with invalid reply */
1021 	AUX_RET_ERROR_INVALID_REPLY,
1022 	/** AUX process timed out */
1023 	AUX_RET_ERROR_TIMEOUT,
1024 	/** HPD was low during AUX process */
1025 	AUX_RET_ERROR_HPD_DISCON,
1026 	/** Failed to acquire AUX engine */
1027 	AUX_RET_ERROR_ENGINE_ACQUIRE,
1028 	/** AUX request not supported */
1029 	AUX_RET_ERROR_INVALID_OPERATION,
1030 	/** AUX process not available */
1031 	AUX_RET_ERROR_PROTOCOL_ERROR,
1032 };
1033 
1034 /**
1035  * enum aux_channel_type - DP AUX channel type listing.
1036  */
1037 enum aux_channel_type {
1038 	/** AUX thru Legacy DP AUX */
1039 	AUX_CHANNEL_LEGACY_DDC,
1040 	/** AUX thru DPIA DP tunneling */
1041 	AUX_CHANNEL_DPIA
1042 };
1043 
1044 /**
1045  * struct aux_transaction_parameters - DP AUX request transaction data
1046  */
1047 struct aux_transaction_parameters {
1048 	uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
1049 	uint8_t action; /**< enum dp_aux_request_action */
1050 	uint8_t length; /**< DP AUX request data length */
1051 	uint8_t reserved; /**< For future use */
1052 	uint32_t address; /**< DP AUX address */
1053 	uint8_t data[16]; /**< DP AUX write data */
1054 };
1055 
1056 /**
1057  * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1058  */
1059 struct dmub_cmd_dp_aux_control_data {
1060 	uint8_t instance; /**< AUX instance or DPIA instance */
1061 	uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
1062 	uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
1063 	uint8_t reserved0; /**< For future use */
1064 	uint16_t timeout; /**< timeout time in us */
1065 	uint16_t reserved1; /**< For future use */
1066 	enum aux_channel_type type; /**< enum aux_channel_type */
1067 	struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
1068 };
1069 
1070 /**
1071  * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
1072  */
1073 struct dmub_rb_cmd_dp_aux_access {
1074 	/**
1075 	 * Command header.
1076 	 */
1077 	struct dmub_cmd_header header;
1078 	/**
1079 	 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1080 	 */
1081 	struct dmub_cmd_dp_aux_control_data aux_control;
1082 };
1083 
1084 /**
1085  * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
1086  */
1087 struct dmub_rb_cmd_outbox1_enable {
1088 	/**
1089 	 * Command header.
1090 	 */
1091 	struct dmub_cmd_header header;
1092 	/**
1093 	 *  enable: 0x0 -> disable outbox1 notification (default value)
1094 	 *			0x1 -> enable outbox1 notification
1095 	 */
1096 	uint32_t enable;
1097 };
1098 
1099 /* DP AUX Reply command - OutBox Cmd */
1100 /**
1101  * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1102  */
1103 struct aux_reply_data {
1104 	/**
1105 	 * Aux cmd
1106 	 */
1107 	uint8_t command;
1108 	/**
1109 	 * Aux reply data length (max: 16 bytes)
1110 	 */
1111 	uint8_t length;
1112 	/**
1113 	 * Alignment only
1114 	 */
1115 	uint8_t pad[2];
1116 	/**
1117 	 * Aux reply data
1118 	 */
1119 	uint8_t data[16];
1120 };
1121 
1122 /**
1123  * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1124  */
1125 struct aux_reply_control_data {
1126 	/**
1127 	 * Reserved for future use
1128 	 */
1129 	uint32_t handle;
1130 	/**
1131 	 * Aux Instance
1132 	 */
1133 	uint8_t instance;
1134 	/**
1135 	 * Aux transaction result: definition in enum aux_return_code_type
1136 	 */
1137 	uint8_t result;
1138 	/**
1139 	 * Alignment only
1140 	 */
1141 	uint16_t pad;
1142 };
1143 
1144 /**
1145  * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
1146  */
1147 struct dmub_rb_cmd_dp_aux_reply {
1148 	/**
1149 	 * Command header.
1150 	 */
1151 	struct dmub_cmd_header header;
1152 	/**
1153 	 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1154 	 */
1155 	struct aux_reply_control_data control;
1156 	/**
1157 	 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1158 	 */
1159 	struct aux_reply_data reply_data;
1160 };
1161 
1162 /* DP HPD Notify command - OutBox Cmd */
1163 /**
1164  * DP HPD Type
1165  */
1166 enum dp_hpd_type {
1167 	/**
1168 	 * Normal DP HPD
1169 	 */
1170 	DP_HPD = 0,
1171 	/**
1172 	 * DP HPD short pulse
1173 	 */
1174 	DP_IRQ
1175 };
1176 
1177 /**
1178  * DP HPD Status
1179  */
1180 enum dp_hpd_status {
1181 	/**
1182 	 * DP_HPD status low
1183 	 */
1184 	DP_HPD_UNPLUG = 0,
1185 	/**
1186 	 * DP_HPD status high
1187 	 */
1188 	DP_HPD_PLUG
1189 };
1190 
1191 /**
1192  * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1193  */
1194 struct dp_hpd_data {
1195 	/**
1196 	 * DP HPD instance
1197 	 */
1198 	uint8_t instance;
1199 	/**
1200 	 * HPD type
1201 	 */
1202 	uint8_t hpd_type;
1203 	/**
1204 	 * HPD status: only for type: DP_HPD to indicate status
1205 	 */
1206 	uint8_t hpd_status;
1207 	/**
1208 	 * Alignment only
1209 	 */
1210 	uint8_t pad;
1211 };
1212 
1213 /**
1214  * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1215  */
1216 struct dmub_rb_cmd_dp_hpd_notify {
1217 	/**
1218 	 * Command header.
1219 	 */
1220 	struct dmub_cmd_header header;
1221 	/**
1222 	 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1223 	 */
1224 	struct dp_hpd_data hpd_data;
1225 };
1226 
1227 /*
1228  * Command IDs should be treated as stable ABI.
1229  * Do not reuse or modify IDs.
1230  */
1231 
1232 /**
1233  * PSR command sub-types.
1234  */
1235 enum dmub_cmd_psr_type {
1236 	/**
1237 	 * Set PSR version support.
1238 	 */
1239 	DMUB_CMD__PSR_SET_VERSION		= 0,
1240 	/**
1241 	 * Copy driver-calculated parameters to PSR state.
1242 	 */
1243 	DMUB_CMD__PSR_COPY_SETTINGS		= 1,
1244 	/**
1245 	 * Enable PSR.
1246 	 */
1247 	DMUB_CMD__PSR_ENABLE			= 2,
1248 
1249 	/**
1250 	 * Disable PSR.
1251 	 */
1252 	DMUB_CMD__PSR_DISABLE			= 3,
1253 
1254 	/**
1255 	 * Set PSR level.
1256 	 * PSR level is a 16-bit value dicated by driver that
1257 	 * will enable/disable different functionality.
1258 	 */
1259 	DMUB_CMD__PSR_SET_LEVEL			= 4,
1260 
1261 	/**
1262 	 * Forces PSR enabled until an explicit PSR disable call.
1263 	 */
1264 	DMUB_CMD__PSR_FORCE_STATIC		= 5,
1265 };
1266 
1267 /**
1268  * PSR versions.
1269  */
1270 enum psr_version {
1271 	/**
1272 	 * PSR version 1.
1273 	 */
1274 	PSR_VERSION_1				= 0,
1275 	/**
1276 	 * PSR not supported.
1277 	 */
1278 	PSR_VERSION_UNSUPPORTED			= 0xFFFFFFFF,
1279 };
1280 
1281 /**
1282  * enum dmub_cmd_mall_type - MALL commands
1283  */
1284 enum dmub_cmd_mall_type {
1285 	/**
1286 	 * Allows display refresh from MALL.
1287 	 */
1288 	DMUB_CMD__MALL_ACTION_ALLOW = 0,
1289 	/**
1290 	 * Disallows display refresh from MALL.
1291 	 */
1292 	DMUB_CMD__MALL_ACTION_DISALLOW = 1,
1293 	/**
1294 	 * Cursor copy for MALL.
1295 	 */
1296 	DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
1297 	/**
1298 	 * Controls DF requests.
1299 	 */
1300 	DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
1301 };
1302 
1303 
1304 /**
1305  * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1306  */
1307 struct dmub_cmd_psr_copy_settings_data {
1308 	/**
1309 	 * Flags that can be set by driver to change some PSR behaviour.
1310 	 */
1311 	union dmub_psr_debug_flags debug;
1312 	/**
1313 	 * 16-bit value dicated by driver that will enable/disable different functionality.
1314 	 */
1315 	uint16_t psr_level;
1316 	/**
1317 	 * DPP HW instance.
1318 	 */
1319 	uint8_t dpp_inst;
1320 	/**
1321 	 * MPCC HW instance.
1322 	 * Not used in dmub fw,
1323 	 * dmub fw will get active opp by reading odm registers.
1324 	 */
1325 	uint8_t mpcc_inst;
1326 	/**
1327 	 * OPP HW instance.
1328 	 * Not used in dmub fw,
1329 	 * dmub fw will get active opp by reading odm registers.
1330 	 */
1331 	uint8_t opp_inst;
1332 	/**
1333 	 * OTG HW instance.
1334 	 */
1335 	uint8_t otg_inst;
1336 	/**
1337 	 * DIG FE HW instance.
1338 	 */
1339 	uint8_t digfe_inst;
1340 	/**
1341 	 * DIG BE HW instance.
1342 	 */
1343 	uint8_t digbe_inst;
1344 	/**
1345 	 * DP PHY HW instance.
1346 	 */
1347 	uint8_t dpphy_inst;
1348 	/**
1349 	 * AUX HW instance.
1350 	 */
1351 	uint8_t aux_inst;
1352 	/**
1353 	 * Determines if SMU optimzations are enabled/disabled.
1354 	 */
1355 	uint8_t smu_optimizations_en;
1356 	/**
1357 	 * Unused.
1358 	 * TODO: Remove.
1359 	 */
1360 	uint8_t frame_delay;
1361 	/**
1362 	 * If RFB setup time is greater than the total VBLANK time,
1363 	 * it is not possible for the sink to capture the video frame
1364 	 * in the same frame the SDP is sent. In this case,
1365 	 * the frame capture indication bit should be set and an extra
1366 	 * static frame should be transmitted to the sink.
1367 	 */
1368 	uint8_t frame_cap_ind;
1369 	/**
1370 	 * Explicit padding to 4 byte boundary.
1371 	 */
1372 	uint8_t pad[2];
1373 	/**
1374 	 * Multi-display optimizations are implemented on certain ASICs.
1375 	 */
1376 	uint8_t multi_disp_optimizations_en;
1377 	/**
1378 	 * The last possible line SDP may be transmitted without violating
1379 	 * the RFB setup time or entering the active video frame.
1380 	 */
1381 	uint16_t init_sdp_deadline;
1382 	/**
1383 	 * Explicit padding to 4 byte boundary.
1384 	 */
1385 	uint16_t pad2;
1386 	/**
1387 	 * Length of each horizontal line in us.
1388 	 */
1389 	uint32_t line_time_in_us;
1390 	/**
1391 	 * FEC enable status in driver
1392 	 */
1393 	uint8_t fec_enable_status;
1394 	/**
1395 	 * FEC re-enable delay when PSR exit.
1396 	 * unit is 100us, range form 0~255(0xFF).
1397 	 */
1398 	uint8_t fec_enable_delay_in100us;
1399 	/**
1400 	 * PSR control version.
1401 	 */
1402 	uint8_t cmd_version;
1403 	/**
1404 	 * Panel Instance.
1405 	 * Panel isntance to identify which psr_state to use
1406 	 * Currently the support is only for 0 or 1
1407 	 */
1408 	uint8_t panel_inst;
1409 };
1410 
1411 /**
1412  * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
1413  */
1414 struct dmub_rb_cmd_psr_copy_settings {
1415 	/**
1416 	 * Command header.
1417 	 */
1418 	struct dmub_cmd_header header;
1419 	/**
1420 	 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1421 	 */
1422 	struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
1423 };
1424 
1425 /**
1426  * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
1427  */
1428 struct dmub_cmd_psr_set_level_data {
1429 	/**
1430 	 * 16-bit value dicated by driver that will enable/disable different functionality.
1431 	 */
1432 	uint16_t psr_level;
1433 		/**
1434 	 * PSR control version.
1435 	 */
1436 	uint8_t cmd_version;
1437 	/**
1438 	 * Panel Instance.
1439 	 * Panel isntance to identify which psr_state to use
1440 	 * Currently the support is only for 0 or 1
1441 	 */
1442 	uint8_t panel_inst;
1443 };
1444 
1445 /**
1446  * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1447  */
1448 struct dmub_rb_cmd_psr_set_level {
1449 	/**
1450 	 * Command header.
1451 	 */
1452 	struct dmub_cmd_header header;
1453 	/**
1454 	 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1455 	 */
1456 	struct dmub_cmd_psr_set_level_data psr_set_level_data;
1457 };
1458 
1459 struct dmub_rb_cmd_psr_enable_data {
1460 	/**
1461 	 * PSR control version.
1462 	 */
1463 	uint8_t cmd_version;
1464 	/**
1465 	 * Panel Instance.
1466 	 * Panel isntance to identify which psr_state to use
1467 	 * Currently the support is only for 0 or 1
1468 	 */
1469 	uint8_t panel_inst;
1470 	/**
1471 	 * Explicit padding to 4 byte boundary.
1472 	 */
1473 	uint8_t pad[2];
1474 };
1475 
1476 /**
1477  * Definition of a DMUB_CMD__PSR_ENABLE command.
1478  * PSR enable/disable is controlled using the sub_type.
1479  */
1480 struct dmub_rb_cmd_psr_enable {
1481 	/**
1482 	 * Command header.
1483 	 */
1484 	struct dmub_cmd_header header;
1485 
1486 	struct dmub_rb_cmd_psr_enable_data data;
1487 };
1488 
1489 /**
1490  * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
1491  */
1492 struct dmub_cmd_psr_set_version_data {
1493 	/**
1494 	 * PSR version that FW should implement.
1495 	 */
1496 	enum psr_version version;
1497 	/**
1498 	 * PSR control version.
1499 	 */
1500 	uint8_t cmd_version;
1501 	/**
1502 	 * Panel Instance.
1503 	 * Panel isntance to identify which psr_state to use
1504 	 * Currently the support is only for 0 or 1
1505 	 */
1506 	uint8_t panel_inst;
1507 	/**
1508 	 * Explicit padding to 4 byte boundary.
1509 	 */
1510 	uint8_t pad[2];
1511 };
1512 
1513 /**
1514  * Definition of a DMUB_CMD__PSR_SET_VERSION command.
1515  */
1516 struct dmub_rb_cmd_psr_set_version {
1517 	/**
1518 	 * Command header.
1519 	 */
1520 	struct dmub_cmd_header header;
1521 	/**
1522 	 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
1523 	 */
1524 	struct dmub_cmd_psr_set_version_data psr_set_version_data;
1525 };
1526 
1527 struct dmub_cmd_psr_force_static_data {
1528 	/**
1529 	 * PSR control version.
1530 	 */
1531 	uint8_t cmd_version;
1532 	/**
1533 	 * Panel Instance.
1534 	 * Panel isntance to identify which psr_state to use
1535 	 * Currently the support is only for 0 or 1
1536 	 */
1537 	uint8_t panel_inst;
1538 	/**
1539 	 * Explicit padding to 4 byte boundary.
1540 	 */
1541 	uint8_t pad[2];
1542 };
1543 
1544 /**
1545  * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
1546  */
1547 struct dmub_rb_cmd_psr_force_static {
1548 	/**
1549 	 * Command header.
1550 	 */
1551 	struct dmub_cmd_header header;
1552 	/**
1553 	 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
1554 	 */
1555 	struct dmub_cmd_psr_force_static_data psr_force_static_data;
1556 };
1557 
1558 /**
1559  * Set of HW components that can be locked.
1560  *
1561  * Note: If updating with more HW components, fields
1562  * in dmub_inbox0_cmd_lock_hw must be updated to match.
1563  */
1564 union dmub_hw_lock_flags {
1565 	/**
1566 	 * Set of HW components that can be locked.
1567 	 */
1568 	struct {
1569 		/**
1570 		 * Lock/unlock OTG master update lock.
1571 		 */
1572 		uint8_t lock_pipe   : 1;
1573 		/**
1574 		 * Lock/unlock cursor.
1575 		 */
1576 		uint8_t lock_cursor : 1;
1577 		/**
1578 		 * Lock/unlock global update lock.
1579 		 */
1580 		uint8_t lock_dig    : 1;
1581 		/**
1582 		 * Triple buffer lock requires additional hw programming to usual OTG master lock.
1583 		 */
1584 		uint8_t triple_buffer_lock : 1;
1585 	} bits;
1586 
1587 	/**
1588 	 * Union for HW Lock flags.
1589 	 */
1590 	uint8_t u8All;
1591 };
1592 
1593 /**
1594  * Instances of HW to be locked.
1595  *
1596  * Note: If updating with more HW components, fields
1597  * in dmub_inbox0_cmd_lock_hw must be updated to match.
1598  */
1599 struct dmub_hw_lock_inst_flags {
1600 	/**
1601 	 * OTG HW instance for OTG master update lock.
1602 	 */
1603 	uint8_t otg_inst;
1604 	/**
1605 	 * OPP instance for cursor lock.
1606 	 */
1607 	uint8_t opp_inst;
1608 	/**
1609 	 * OTG HW instance for global update lock.
1610 	 * TODO: Remove, and re-use otg_inst.
1611 	 */
1612 	uint8_t dig_inst;
1613 	/**
1614 	 * Explicit pad to 4 byte boundary.
1615 	 */
1616 	uint8_t pad;
1617 };
1618 
1619 /**
1620  * Clients that can acquire the HW Lock Manager.
1621  *
1622  * Note: If updating with more clients, fields in
1623  * dmub_inbox0_cmd_lock_hw must be updated to match.
1624  */
1625 enum hw_lock_client {
1626 	/**
1627 	 * Driver is the client of HW Lock Manager.
1628 	 */
1629 	HW_LOCK_CLIENT_DRIVER = 0,
1630 	/**
1631 	 * Invalid client.
1632 	 */
1633 	HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
1634 };
1635 
1636 /**
1637  * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
1638  */
1639 struct dmub_cmd_lock_hw_data {
1640 	/**
1641 	 * Specifies the client accessing HW Lock Manager.
1642 	 */
1643 	enum hw_lock_client client;
1644 	/**
1645 	 * HW instances to be locked.
1646 	 */
1647 	struct dmub_hw_lock_inst_flags inst_flags;
1648 	/**
1649 	 * Which components to be locked.
1650 	 */
1651 	union dmub_hw_lock_flags hw_locks;
1652 	/**
1653 	 * Specifies lock/unlock.
1654 	 */
1655 	uint8_t lock;
1656 	/**
1657 	 * HW can be unlocked separately from releasing the HW Lock Mgr.
1658 	 * This flag is set if the client wishes to release the object.
1659 	 */
1660 	uint8_t should_release;
1661 	/**
1662 	 * Explicit padding to 4 byte boundary.
1663 	 */
1664 	uint8_t pad;
1665 };
1666 
1667 /**
1668  * Definition of a DMUB_CMD__HW_LOCK command.
1669  * Command is used by driver and FW.
1670  */
1671 struct dmub_rb_cmd_lock_hw {
1672 	/**
1673 	 * Command header.
1674 	 */
1675 	struct dmub_cmd_header header;
1676 	/**
1677 	 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
1678 	 */
1679 	struct dmub_cmd_lock_hw_data lock_hw_data;
1680 };
1681 
1682 /**
1683  * ABM command sub-types.
1684  */
1685 enum dmub_cmd_abm_type {
1686 	/**
1687 	 * Initialize parameters for ABM algorithm.
1688 	 * Data is passed through an indirect buffer.
1689 	 */
1690 	DMUB_CMD__ABM_INIT_CONFIG	= 0,
1691 	/**
1692 	 * Set OTG and panel HW instance.
1693 	 */
1694 	DMUB_CMD__ABM_SET_PIPE		= 1,
1695 	/**
1696 	 * Set user requested backklight level.
1697 	 */
1698 	DMUB_CMD__ABM_SET_BACKLIGHT	= 2,
1699 	/**
1700 	 * Set ABM operating/aggression level.
1701 	 */
1702 	DMUB_CMD__ABM_SET_LEVEL		= 3,
1703 	/**
1704 	 * Set ambient light level.
1705 	 */
1706 	DMUB_CMD__ABM_SET_AMBIENT_LEVEL	= 4,
1707 	/**
1708 	 * Enable/disable fractional duty cycle for backlight PWM.
1709 	 */
1710 	DMUB_CMD__ABM_SET_PWM_FRAC	= 5,
1711 };
1712 
1713 /**
1714  * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
1715  * Requirements:
1716  *  - Padded explicitly to 32-bit boundary.
1717  *  - Must ensure this structure matches the one on driver-side,
1718  *    otherwise it won't be aligned.
1719  */
1720 struct abm_config_table {
1721 	/**
1722 	 * Gamma curve thresholds, used for crgb conversion.
1723 	 */
1724 	uint16_t crgb_thresh[NUM_POWER_FN_SEGS];                 // 0B
1725 	/**
1726 	 * Gamma curve offsets, used for crgb conversion.
1727 	 */
1728 	uint16_t crgb_offset[NUM_POWER_FN_SEGS];                 // 16B
1729 	/**
1730 	 * Gamma curve slopes, used for crgb conversion.
1731 	 */
1732 	uint16_t crgb_slope[NUM_POWER_FN_SEGS];                  // 32B
1733 	/**
1734 	 * Custom backlight curve thresholds.
1735 	 */
1736 	uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS];        // 48B
1737 	/**
1738 	 * Custom backlight curve offsets.
1739 	 */
1740 	uint16_t backlight_offsets[NUM_BL_CURVE_SEGS];           // 78B
1741 	/**
1742 	 * Ambient light thresholds.
1743 	 */
1744 	uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL];         // 112B
1745 	/**
1746 	 * Minimum programmable backlight.
1747 	 */
1748 	uint16_t min_abm_backlight;                              // 122B
1749 	/**
1750 	 * Minimum reduction values.
1751 	 */
1752 	uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];   // 124B
1753 	/**
1754 	 * Maximum reduction values.
1755 	 */
1756 	uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];   // 144B
1757 	/**
1758 	 * Bright positive gain.
1759 	 */
1760 	uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
1761 	/**
1762 	 * Dark negative gain.
1763 	 */
1764 	uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];   // 184B
1765 	/**
1766 	 * Hybrid factor.
1767 	 */
1768 	uint8_t hybrid_factor[NUM_AGGR_LEVEL];                   // 204B
1769 	/**
1770 	 * Contrast factor.
1771 	 */
1772 	uint8_t contrast_factor[NUM_AGGR_LEVEL];                 // 208B
1773 	/**
1774 	 * Deviation gain.
1775 	 */
1776 	uint8_t deviation_gain[NUM_AGGR_LEVEL];                  // 212B
1777 	/**
1778 	 * Minimum knee.
1779 	 */
1780 	uint8_t min_knee[NUM_AGGR_LEVEL];                        // 216B
1781 	/**
1782 	 * Maximum knee.
1783 	 */
1784 	uint8_t max_knee[NUM_AGGR_LEVEL];                        // 220B
1785 	/**
1786 	 * Unused.
1787 	 */
1788 	uint8_t iir_curve[NUM_AMBI_LEVEL];                       // 224B
1789 	/**
1790 	 * Explicit padding to 4 byte boundary.
1791 	 */
1792 	uint8_t pad3[3];                                         // 229B
1793 	/**
1794 	 * Backlight ramp reduction.
1795 	 */
1796 	uint16_t blRampReduction[NUM_AGGR_LEVEL];                // 232B
1797 	/**
1798 	 * Backlight ramp start.
1799 	 */
1800 	uint16_t blRampStart[NUM_AGGR_LEVEL];                    // 240B
1801 };
1802 
1803 /**
1804  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
1805  */
1806 struct dmub_cmd_abm_set_pipe_data {
1807 	/**
1808 	 * OTG HW instance.
1809 	 */
1810 	uint8_t otg_inst;
1811 
1812 	/**
1813 	 * Panel Control HW instance.
1814 	 */
1815 	uint8_t panel_inst;
1816 
1817 	/**
1818 	 * Controls how ABM will interpret a set pipe or set level command.
1819 	 */
1820 	uint8_t set_pipe_option;
1821 
1822 	/**
1823 	 * Unused.
1824 	 * TODO: Remove.
1825 	 */
1826 	uint8_t ramping_boundary;
1827 };
1828 
1829 /**
1830  * Definition of a DMUB_CMD__ABM_SET_PIPE command.
1831  */
1832 struct dmub_rb_cmd_abm_set_pipe {
1833 	/**
1834 	 * Command header.
1835 	 */
1836 	struct dmub_cmd_header header;
1837 
1838 	/**
1839 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
1840 	 */
1841 	struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
1842 };
1843 
1844 /**
1845  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
1846  */
1847 struct dmub_cmd_abm_set_backlight_data {
1848 	/**
1849 	 * Number of frames to ramp to backlight user level.
1850 	 */
1851 	uint32_t frame_ramp;
1852 
1853 	/**
1854 	 * Requested backlight level from user.
1855 	 */
1856 	uint32_t backlight_user_level;
1857 
1858 	/**
1859 	 * ABM control version.
1860 	 */
1861 	uint8_t version;
1862 
1863 	/**
1864 	 * Panel Control HW instance mask.
1865 	 * Bit 0 is Panel Control HW instance 0.
1866 	 * Bit 1 is Panel Control HW instance 1.
1867 	 */
1868 	uint8_t panel_mask;
1869 
1870 	/**
1871 	 * Explicit padding to 4 byte boundary.
1872 	 */
1873 	uint8_t pad[2];
1874 };
1875 
1876 /**
1877  * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
1878  */
1879 struct dmub_rb_cmd_abm_set_backlight {
1880 	/**
1881 	 * Command header.
1882 	 */
1883 	struct dmub_cmd_header header;
1884 
1885 	/**
1886 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
1887 	 */
1888 	struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
1889 };
1890 
1891 /**
1892  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
1893  */
1894 struct dmub_cmd_abm_set_level_data {
1895 	/**
1896 	 * Set current ABM operating/aggression level.
1897 	 */
1898 	uint32_t level;
1899 
1900 	/**
1901 	 * ABM control version.
1902 	 */
1903 	uint8_t version;
1904 
1905 	/**
1906 	 * Panel Control HW instance mask.
1907 	 * Bit 0 is Panel Control HW instance 0.
1908 	 * Bit 1 is Panel Control HW instance 1.
1909 	 */
1910 	uint8_t panel_mask;
1911 
1912 	/**
1913 	 * Explicit padding to 4 byte boundary.
1914 	 */
1915 	uint8_t pad[2];
1916 };
1917 
1918 /**
1919  * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
1920  */
1921 struct dmub_rb_cmd_abm_set_level {
1922 	/**
1923 	 * Command header.
1924 	 */
1925 	struct dmub_cmd_header header;
1926 
1927 	/**
1928 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
1929 	 */
1930 	struct dmub_cmd_abm_set_level_data abm_set_level_data;
1931 };
1932 
1933 /**
1934  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1935  */
1936 struct dmub_cmd_abm_set_ambient_level_data {
1937 	/**
1938 	 * Ambient light sensor reading from OS.
1939 	 */
1940 	uint32_t ambient_lux;
1941 
1942 	/**
1943 	 * ABM control version.
1944 	 */
1945 	uint8_t version;
1946 
1947 	/**
1948 	 * Panel Control HW instance mask.
1949 	 * Bit 0 is Panel Control HW instance 0.
1950 	 * Bit 1 is Panel Control HW instance 1.
1951 	 */
1952 	uint8_t panel_mask;
1953 
1954 	/**
1955 	 * Explicit padding to 4 byte boundary.
1956 	 */
1957 	uint8_t pad[2];
1958 };
1959 
1960 /**
1961  * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1962  */
1963 struct dmub_rb_cmd_abm_set_ambient_level {
1964 	/**
1965 	 * Command header.
1966 	 */
1967 	struct dmub_cmd_header header;
1968 
1969 	/**
1970 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1971 	 */
1972 	struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
1973 };
1974 
1975 /**
1976  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
1977  */
1978 struct dmub_cmd_abm_set_pwm_frac_data {
1979 	/**
1980 	 * Enable/disable fractional duty cycle for backlight PWM.
1981 	 * TODO: Convert to uint8_t.
1982 	 */
1983 	uint32_t fractional_pwm;
1984 
1985 	/**
1986 	 * ABM control version.
1987 	 */
1988 	uint8_t version;
1989 
1990 	/**
1991 	 * Panel Control HW instance mask.
1992 	 * Bit 0 is Panel Control HW instance 0.
1993 	 * Bit 1 is Panel Control HW instance 1.
1994 	 */
1995 	uint8_t panel_mask;
1996 
1997 	/**
1998 	 * Explicit padding to 4 byte boundary.
1999 	 */
2000 	uint8_t pad[2];
2001 };
2002 
2003 /**
2004  * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
2005  */
2006 struct dmub_rb_cmd_abm_set_pwm_frac {
2007 	/**
2008 	 * Command header.
2009 	 */
2010 	struct dmub_cmd_header header;
2011 
2012 	/**
2013 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
2014 	 */
2015 	struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
2016 };
2017 
2018 /**
2019  * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
2020  */
2021 struct dmub_cmd_abm_init_config_data {
2022 	/**
2023 	 * Location of indirect buffer used to pass init data to ABM.
2024 	 */
2025 	union dmub_addr src;
2026 
2027 	/**
2028 	 * Indirect buffer length.
2029 	 */
2030 	uint16_t bytes;
2031 
2032 
2033 	/**
2034 	 * ABM control version.
2035 	 */
2036 	uint8_t version;
2037 
2038 	/**
2039 	 * Panel Control HW instance mask.
2040 	 * Bit 0 is Panel Control HW instance 0.
2041 	 * Bit 1 is Panel Control HW instance 1.
2042 	 */
2043 	uint8_t panel_mask;
2044 
2045 	/**
2046 	 * Explicit padding to 4 byte boundary.
2047 	 */
2048 	uint8_t pad[2];
2049 };
2050 
2051 /**
2052  * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
2053  */
2054 struct dmub_rb_cmd_abm_init_config {
2055 	/**
2056 	 * Command header.
2057 	 */
2058 	struct dmub_cmd_header header;
2059 
2060 	/**
2061 	 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
2062 	 */
2063 	struct dmub_cmd_abm_init_config_data abm_init_config_data;
2064 };
2065 
2066 /**
2067  * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
2068  */
2069 struct dmub_cmd_query_feature_caps_data {
2070 	/**
2071 	 * DMUB feature capabilities.
2072 	 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
2073 	 */
2074 	struct dmub_feature_caps feature_caps;
2075 };
2076 
2077 /**
2078  * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
2079  */
2080 struct dmub_rb_cmd_query_feature_caps {
2081 	/**
2082 	 * Command header.
2083 	 */
2084 	struct dmub_cmd_header header;
2085 	/**
2086 	 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
2087 	 */
2088 	struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
2089 };
2090 
2091 struct dmub_optc_state {
2092 	uint32_t v_total_max;
2093 	uint32_t v_total_min;
2094 	uint32_t v_total_mid;
2095 	uint32_t v_total_mid_frame_num;
2096 	uint32_t tg_inst;
2097 	uint32_t enable_manual_trigger;
2098 	uint32_t clear_force_vsync;
2099 };
2100 
2101 struct dmub_rb_cmd_drr_update {
2102 		struct dmub_cmd_header header;
2103 		struct dmub_optc_state dmub_optc_state_req;
2104 };
2105 
2106 /**
2107  * enum dmub_cmd_panel_cntl_type - Panel control command.
2108  */
2109 enum dmub_cmd_panel_cntl_type {
2110 	/**
2111 	 * Initializes embedded panel hardware blocks.
2112 	 */
2113 	DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
2114 	/**
2115 	 * Queries backlight info for the embedded panel.
2116 	 */
2117 	DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
2118 };
2119 
2120 /**
2121  * struct dmub_cmd_panel_cntl_data - Panel control data.
2122  */
2123 struct dmub_cmd_panel_cntl_data {
2124 	uint32_t inst; /**< panel instance */
2125 	uint32_t current_backlight; /* in/out */
2126 	uint32_t bl_pwm_cntl; /* in/out */
2127 	uint32_t bl_pwm_period_cntl; /* in/out */
2128 	uint32_t bl_pwm_ref_div1; /* in/out */
2129 	uint8_t is_backlight_on : 1; /* in/out */
2130 	uint8_t is_powered_on : 1; /* in/out */
2131 };
2132 
2133 /**
2134  * struct dmub_rb_cmd_panel_cntl - Panel control command.
2135  */
2136 struct dmub_rb_cmd_panel_cntl {
2137 	struct dmub_cmd_header header; /**< header */
2138 	struct dmub_cmd_panel_cntl_data data; /**< payload */
2139 };
2140 
2141 /**
2142  * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2143  */
2144 struct dmub_cmd_lvtma_control_data {
2145 	uint8_t uc_pwr_action; /**< LVTMA_ACTION */
2146 	uint8_t reserved_0[3]; /**< For future use */
2147 	uint8_t panel_inst; /**< LVTMA control instance */
2148 	uint8_t reserved_1[3]; /**< For future use */
2149 };
2150 
2151 /**
2152  * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2153  */
2154 struct dmub_rb_cmd_lvtma_control {
2155 	/**
2156 	 * Command header.
2157 	 */
2158 	struct dmub_cmd_header header;
2159 	/**
2160 	 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2161 	 */
2162 	struct dmub_cmd_lvtma_control_data data;
2163 };
2164 
2165 /**
2166  * Maximum number of bytes a chunk sent to DMUB for parsing
2167  */
2168 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
2169 
2170 /**
2171  *  Represent a chunk of CEA blocks sent to DMUB for parsing
2172  */
2173 struct dmub_cmd_send_edid_cea {
2174 	uint16_t offset;	/**< offset into the CEA block */
2175 	uint8_t length;	/**< number of bytes in payload to copy as part of CEA block */
2176 	uint16_t total_length;  /**< total length of the CEA block */
2177 	uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
2178 	uint8_t pad[3]; /**< padding and for future expansion */
2179 };
2180 
2181 /**
2182  * Result of VSDB parsing from CEA block
2183  */
2184 struct dmub_cmd_edid_cea_amd_vsdb {
2185 	uint8_t vsdb_found;		/**< 1 if parsing has found valid AMD VSDB */
2186 	uint8_t freesync_supported;	/**< 1 if Freesync is supported */
2187 	uint16_t amd_vsdb_version;	/**< AMD VSDB version */
2188 	uint16_t min_frame_rate;	/**< Maximum frame rate */
2189 	uint16_t max_frame_rate;	/**< Minimum frame rate */
2190 };
2191 
2192 /**
2193  * Result of sending a CEA chunk
2194  */
2195 struct dmub_cmd_edid_cea_ack {
2196 	uint16_t offset;	/**< offset of the chunk into the CEA block */
2197 	uint8_t success;	/**< 1 if this sending of chunk succeeded */
2198 	uint8_t pad;		/**< padding and for future expansion */
2199 };
2200 
2201 /**
2202  * Specify whether the result is an ACK/NACK or the parsing has finished
2203  */
2204 enum dmub_cmd_edid_cea_reply_type {
2205 	DMUB_CMD__EDID_CEA_AMD_VSDB	= 1, /**< VSDB parsing has finished */
2206 	DMUB_CMD__EDID_CEA_ACK		= 2, /**< acknowledges the CEA sending is OK or failing */
2207 };
2208 
2209 /**
2210  * Definition of a DMUB_CMD__EDID_CEA command.
2211  */
2212 struct dmub_rb_cmd_edid_cea {
2213 	struct dmub_cmd_header header;	/**< Command header */
2214 	union dmub_cmd_edid_cea_data {
2215 		struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
2216 		struct dmub_cmd_edid_cea_output { /**< output with results */
2217 			uint8_t type;	/**< dmub_cmd_edid_cea_reply_type */
2218 			union {
2219 				struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
2220 				struct dmub_cmd_edid_cea_ack ack;
2221 			};
2222 		} output;	/**< output to retrieve ACK/NACK or VSDB parsing results */
2223 	} data;	/**< Command data */
2224 
2225 };
2226 
2227 /**
2228  * union dmub_rb_cmd - DMUB inbox command.
2229  */
2230 union dmub_rb_cmd {
2231 	struct dmub_rb_cmd_lock_hw lock_hw;
2232 	/**
2233 	 * Elements shared with all commands.
2234 	 */
2235 	struct dmub_rb_cmd_common cmd_common;
2236 	/**
2237 	 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
2238 	 */
2239 	struct dmub_rb_cmd_read_modify_write read_modify_write;
2240 	/**
2241 	 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
2242 	 */
2243 	struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
2244 	/**
2245 	 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
2246 	 */
2247 	struct dmub_rb_cmd_burst_write burst_write;
2248 	/**
2249 	 * Definition of a DMUB_CMD__REG_REG_WAIT command.
2250 	 */
2251 	struct dmub_rb_cmd_reg_wait reg_wait;
2252 	/**
2253 	 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
2254 	 */
2255 	struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
2256 	/**
2257 	 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
2258 	 */
2259 	struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
2260 	/**
2261 	 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
2262 	 */
2263 	struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
2264 	/**
2265 	 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
2266 	 */
2267 	struct dmub_rb_cmd_dpphy_init dpphy_init;
2268 	/**
2269 	 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
2270 	 */
2271 	struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
2272 	/**
2273 	 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
2274 	 */
2275 	struct dmub_rb_cmd_psr_set_version psr_set_version;
2276 	/**
2277 	 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
2278 	 */
2279 	struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
2280 	/**
2281 	 * Definition of a DMUB_CMD__PSR_ENABLE command.
2282 	 */
2283 	struct dmub_rb_cmd_psr_enable psr_enable;
2284 	/**
2285 	 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2286 	 */
2287 	struct dmub_rb_cmd_psr_set_level psr_set_level;
2288 	/**
2289 	 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
2290 	 */
2291 	struct dmub_rb_cmd_psr_force_static psr_force_static;
2292 	/**
2293 	 * Definition of a DMUB_CMD__PLAT_54186_WA command.
2294 	 */
2295 	struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
2296 	/**
2297 	 * Definition of a DMUB_CMD__MALL command.
2298 	 */
2299 	struct dmub_rb_cmd_mall mall;
2300 	/**
2301 	 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
2302 	 */
2303 	struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
2304 
2305 	/**
2306 	 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
2307 	 */
2308 	struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
2309 
2310 	/**
2311 	 * Definition of DMUB_CMD__PANEL_CNTL commands.
2312 	 */
2313 	struct dmub_rb_cmd_panel_cntl panel_cntl;
2314 	/**
2315 	 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
2316 	 */
2317 	struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
2318 
2319 	/**
2320 	 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
2321 	 */
2322 	struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
2323 
2324 	/**
2325 	 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
2326 	 */
2327 	struct dmub_rb_cmd_abm_set_level abm_set_level;
2328 
2329 	/**
2330 	 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
2331 	 */
2332 	struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
2333 
2334 	/**
2335 	 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
2336 	 */
2337 	struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
2338 
2339 	/**
2340 	 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
2341 	 */
2342 	struct dmub_rb_cmd_abm_init_config abm_init_config;
2343 
2344 	/**
2345 	 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
2346 	 */
2347 	struct dmub_rb_cmd_dp_aux_access dp_aux_access;
2348 
2349 	/**
2350 	 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
2351 	 */
2352 	struct dmub_rb_cmd_outbox1_enable outbox1_enable;
2353 
2354 	/**
2355 	 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
2356 	 */
2357 	struct dmub_rb_cmd_query_feature_caps query_feature_caps;
2358 	struct dmub_rb_cmd_drr_update drr_update;
2359 	/**
2360 	 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2361 	 */
2362 	struct dmub_rb_cmd_lvtma_control lvtma_control;
2363 	/**
2364 	 * Definition of a DMUB_CMD__EDID_CEA command.
2365 	 */
2366 	struct dmub_rb_cmd_edid_cea edid_cea;
2367 };
2368 
2369 /**
2370  * union dmub_rb_out_cmd - Outbox command
2371  */
2372 union dmub_rb_out_cmd {
2373 	/**
2374 	 * Parameters common to every command.
2375 	 */
2376 	struct dmub_rb_cmd_common cmd_common;
2377 	/**
2378 	 * AUX reply command.
2379 	 */
2380 	struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
2381 	/**
2382 	 * HPD notify command.
2383 	 */
2384 	struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
2385 };
2386 #pragma pack(pop)
2387 
2388 
2389 //==============================================================================
2390 //</DMUB_CMD>===================================================================
2391 //==============================================================================
2392 //< DMUB_RB>====================================================================
2393 //==============================================================================
2394 
2395 #if defined(__cplusplus)
2396 extern "C" {
2397 #endif
2398 
2399 /**
2400  * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
2401  */
2402 struct dmub_rb_init_params {
2403 	void *ctx; /**< Caller provided context pointer */
2404 	void *base_address; /**< CPU base address for ring's data */
2405 	uint32_t capacity; /**< Ringbuffer capacity in bytes */
2406 	uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
2407 	uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
2408 };
2409 
2410 /**
2411  * struct dmub_rb - Inbox or outbox DMUB ringbuffer
2412  */
2413 struct dmub_rb {
2414 	void *base_address; /**< CPU address for the ring's data */
2415 	uint32_t rptr; /**< Read pointer for consumer in bytes */
2416 	uint32_t wrpt; /**< Write pointer for producer in bytes */
2417 	uint32_t capacity; /**< Ringbuffer capacity in bytes */
2418 
2419 	void *ctx; /**< Caller provided context pointer */
2420 	void *dmub; /**< Pointer to the DMUB interface */
2421 };
2422 
2423 /**
2424  * @brief Checks if the ringbuffer is empty.
2425  *
2426  * @param rb DMUB Ringbuffer
2427  * @return true if empty
2428  * @return false otherwise
2429  */
2430 static inline bool dmub_rb_empty(struct dmub_rb *rb)
2431 {
2432 	return (rb->wrpt == rb->rptr);
2433 }
2434 
2435 /**
2436  * @brief Checks if the ringbuffer is full
2437  *
2438  * @param rb DMUB Ringbuffer
2439  * @return true if full
2440  * @return false otherwise
2441  */
2442 static inline bool dmub_rb_full(struct dmub_rb *rb)
2443 {
2444 	uint32_t data_count;
2445 
2446 	if (rb->wrpt >= rb->rptr)
2447 		data_count = rb->wrpt - rb->rptr;
2448 	else
2449 		data_count = rb->capacity - (rb->rptr - rb->wrpt);
2450 
2451 	return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
2452 }
2453 
2454 /**
2455  * @brief Pushes a command into the ringbuffer
2456  *
2457  * @param rb DMUB ringbuffer
2458  * @param cmd The command to push
2459  * @return true if the ringbuffer was not full
2460  * @return false otherwise
2461  */
2462 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
2463 				      const union dmub_rb_cmd *cmd)
2464 {
2465 	uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t);
2466 	const uint64_t *src = (const uint64_t *)cmd;
2467 	uint8_t i;
2468 
2469 	if (dmub_rb_full(rb))
2470 		return false;
2471 
2472 	// copying data
2473 	for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
2474 		*dst++ = *src++;
2475 
2476 	rb->wrpt += DMUB_RB_CMD_SIZE;
2477 
2478 	if (rb->wrpt >= rb->capacity)
2479 		rb->wrpt %= rb->capacity;
2480 
2481 	return true;
2482 }
2483 
2484 /**
2485  * @brief Pushes a command into the DMUB outbox ringbuffer
2486  *
2487  * @param rb DMUB outbox ringbuffer
2488  * @param cmd Outbox command
2489  * @return true if not full
2490  * @return false otherwise
2491  */
2492 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
2493 				      const union dmub_rb_out_cmd *cmd)
2494 {
2495 	uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
2496 	const uint8_t *src = (uint8_t *)cmd;
2497 
2498 	if (dmub_rb_full(rb))
2499 		return false;
2500 
2501 	dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
2502 
2503 	rb->wrpt += DMUB_RB_CMD_SIZE;
2504 
2505 	if (rb->wrpt >= rb->capacity)
2506 		rb->wrpt %= rb->capacity;
2507 
2508 	return true;
2509 }
2510 
2511 /**
2512  * @brief Returns the next unprocessed command in the ringbuffer.
2513  *
2514  * @param rb DMUB ringbuffer
2515  * @param cmd The command to return
2516  * @return true if not empty
2517  * @return false otherwise
2518  */
2519 static inline bool dmub_rb_front(struct dmub_rb *rb,
2520 				 union dmub_rb_cmd  **cmd)
2521 {
2522 	uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
2523 
2524 	if (dmub_rb_empty(rb))
2525 		return false;
2526 
2527 	*cmd = (union dmub_rb_cmd *)rb_cmd;
2528 
2529 	return true;
2530 }
2531 
2532 /**
2533  * @brief Determines the next ringbuffer offset.
2534  *
2535  * @param rb DMUB inbox ringbuffer
2536  * @param num_cmds Number of commands
2537  * @param next_rptr The next offset in the ringbuffer
2538  */
2539 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
2540 				  uint32_t num_cmds,
2541 				  uint32_t *next_rptr)
2542 {
2543 	*next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
2544 
2545 	if (*next_rptr >= rb->capacity)
2546 		*next_rptr %= rb->capacity;
2547 }
2548 
2549 /**
2550  * @brief Returns a pointer to a command in the inbox.
2551  *
2552  * @param rb DMUB inbox ringbuffer
2553  * @param cmd The inbox command to return
2554  * @param rptr The ringbuffer offset
2555  * @return true if not empty
2556  * @return false otherwise
2557  */
2558 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
2559 				 union dmub_rb_cmd  **cmd,
2560 				 uint32_t rptr)
2561 {
2562 	uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
2563 
2564 	if (dmub_rb_empty(rb))
2565 		return false;
2566 
2567 	*cmd = (union dmub_rb_cmd *)rb_cmd;
2568 
2569 	return true;
2570 }
2571 
2572 /**
2573  * @brief Returns the next unprocessed command in the outbox.
2574  *
2575  * @param rb DMUB outbox ringbuffer
2576  * @param cmd The outbox command to return
2577  * @return true if not empty
2578  * @return false otherwise
2579  */
2580 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
2581 				 union dmub_rb_out_cmd  *cmd)
2582 {
2583 	const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t);
2584 	uint64_t *dst = (uint64_t *)cmd;
2585 	uint8_t i;
2586 
2587 	if (dmub_rb_empty(rb))
2588 		return false;
2589 
2590 	// copying data
2591 	for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
2592 		*dst++ = *src++;
2593 
2594 	return true;
2595 }
2596 
2597 /**
2598  * @brief Removes the front entry in the ringbuffer.
2599  *
2600  * @param rb DMUB ringbuffer
2601  * @return true if the command was removed
2602  * @return false if there were no commands
2603  */
2604 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
2605 {
2606 	if (dmub_rb_empty(rb))
2607 		return false;
2608 
2609 	rb->rptr += DMUB_RB_CMD_SIZE;
2610 
2611 	if (rb->rptr >= rb->capacity)
2612 		rb->rptr %= rb->capacity;
2613 
2614 	return true;
2615 }
2616 
2617 /**
2618  * @brief Flushes commands in the ringbuffer to framebuffer memory.
2619  *
2620  * Avoids a race condition where DMCUB accesses memory while
2621  * there are still writes in flight to framebuffer.
2622  *
2623  * @param rb DMUB ringbuffer
2624  */
2625 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
2626 {
2627 	uint32_t rptr = rb->rptr;
2628 	uint32_t wptr = rb->wrpt;
2629 
2630 	while (rptr != wptr) {
2631 		uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t);
2632 		uint8_t i;
2633 
2634 		for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
2635 			*data++;
2636 
2637 		rptr += DMUB_RB_CMD_SIZE;
2638 		if (rptr >= rb->capacity)
2639 			rptr %= rb->capacity;
2640 	}
2641 }
2642 
2643 /**
2644  * @brief Initializes a DMCUB ringbuffer
2645  *
2646  * @param rb DMUB ringbuffer
2647  * @param init_params initial configuration for the ringbuffer
2648  */
2649 static inline void dmub_rb_init(struct dmub_rb *rb,
2650 				struct dmub_rb_init_params *init_params)
2651 {
2652 	rb->base_address = init_params->base_address;
2653 	rb->capacity = init_params->capacity;
2654 	rb->rptr = init_params->read_ptr;
2655 	rb->wrpt = init_params->write_ptr;
2656 }
2657 
2658 /**
2659  * @brief Copies output data from in/out commands into the given command.
2660  *
2661  * @param rb DMUB ringbuffer
2662  * @param cmd Command to copy data into
2663  */
2664 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
2665 					   union dmub_rb_cmd *cmd)
2666 {
2667 	// Copy rb entry back into command
2668 	uint8_t *rd_ptr = (rb->rptr == 0) ?
2669 		(uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
2670 		(uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
2671 
2672 	dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
2673 }
2674 
2675 #if defined(__cplusplus)
2676 }
2677 #endif
2678 
2679 //==============================================================================
2680 //</DMUB_RB>====================================================================
2681 //==============================================================================
2682 
2683 #endif /* _DMUB_CMD_H_ */
2684