1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Maximum number of streams on any ASIC. */ 99 #define DMUB_MAX_STREAMS 6 100 101 /* Maximum number of planes on any ASIC. */ 102 #define DMUB_MAX_PLANES 6 103 104 /* Trace buffer offset for entry */ 105 #define TRACE_BUFFER_ENTRY_OFFSET 16 106 107 /** 108 * Maximum number of dirty rects supported by FW. 109 */ 110 #define DMUB_MAX_DIRTY_RECTS 3 111 112 /** 113 * 114 * PSR control version legacy 115 */ 116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117 /** 118 * PSR control version with multi edp support 119 */ 120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121 122 123 /** 124 * ABM control version legacy 125 */ 126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127 128 /** 129 * ABM control version with multi edp support 130 */ 131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132 133 /** 134 * Physical framebuffer address location, 64-bit. 135 */ 136 #ifndef PHYSICAL_ADDRESS_LOC 137 #define PHYSICAL_ADDRESS_LOC union large_integer 138 #endif 139 140 /** 141 * OS/FW agnostic memcpy 142 */ 143 #ifndef dmub_memcpy 144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 145 #endif 146 147 /** 148 * OS/FW agnostic memset 149 */ 150 #ifndef dmub_memset 151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 152 #endif 153 154 #if defined(__cplusplus) 155 extern "C" { 156 #endif 157 158 /** 159 * OS/FW agnostic udelay 160 */ 161 #ifndef dmub_udelay 162 #define dmub_udelay(microseconds) udelay(microseconds) 163 #endif 164 165 /** 166 * union dmub_addr - DMUB physical/virtual 64-bit address. 167 */ 168 union dmub_addr { 169 struct { 170 uint32_t low_part; /**< Lower 32 bits */ 171 uint32_t high_part; /**< Upper 32 bits */ 172 } u; /*<< Low/high bit access */ 173 uint64_t quad_part; /*<< 64 bit address */ 174 }; 175 176 /** 177 * Dirty rect definition. 178 */ 179 struct dmub_rect { 180 /** 181 * Dirty rect x offset. 182 */ 183 uint32_t x; 184 185 /** 186 * Dirty rect y offset. 187 */ 188 uint32_t y; 189 190 /** 191 * Dirty rect width. 192 */ 193 uint32_t width; 194 195 /** 196 * Dirty rect height. 197 */ 198 uint32_t height; 199 }; 200 201 /** 202 * Flags that can be set by driver to change some PSR behaviour. 203 */ 204 union dmub_psr_debug_flags { 205 /** 206 * Debug flags. 207 */ 208 struct { 209 /** 210 * Enable visual confirm in FW. 211 */ 212 uint32_t visual_confirm : 1; 213 214 /** 215 * Force all selective updates to bw full frame updates. 216 */ 217 uint32_t force_full_frame_update : 1; 218 219 /** 220 * Use HW Lock Mgr object to do HW locking in FW. 221 */ 222 uint32_t use_hw_lock_mgr : 1; 223 224 /** 225 * Use TPS3 signal when restore main link. 226 */ 227 uint32_t force_wakeup_by_tps3 : 1; 228 229 /** 230 * Back to back flip, therefore cannot power down PHY 231 */ 232 uint32_t back_to_back_flip : 1; 233 234 } bitfields; 235 236 /** 237 * Union for debug flags. 238 */ 239 uint32_t u32All; 240 }; 241 242 /** 243 * DMUB visual confirm color 244 */ 245 struct dmub_feature_caps { 246 /** 247 * Max PSR version supported by FW. 248 */ 249 uint8_t psr; 250 uint8_t fw_assisted_mclk_switch; 251 uint8_t reserved[6]; 252 }; 253 254 struct dmub_visual_confirm_color { 255 /** 256 * Maximum 10 bits color value 257 */ 258 uint16_t color_r_cr; 259 uint16_t color_g_y; 260 uint16_t color_b_cb; 261 uint16_t panel_inst; 262 }; 263 264 #if defined(__cplusplus) 265 } 266 #endif 267 268 //============================================================================== 269 //</DMUB_TYPES>================================================================= 270 //============================================================================== 271 //< DMUB_META>================================================================== 272 //============================================================================== 273 #pragma pack(push, 1) 274 275 /* Magic value for identifying dmub_fw_meta_info */ 276 #define DMUB_FW_META_MAGIC 0x444D5542 277 278 /* Offset from the end of the file to the dmub_fw_meta_info */ 279 #define DMUB_FW_META_OFFSET 0x24 280 281 /** 282 * struct dmub_fw_meta_info - metadata associated with fw binary 283 * 284 * NOTE: This should be considered a stable API. Fields should 285 * not be repurposed or reordered. New fields should be 286 * added instead to extend the structure. 287 * 288 * @magic_value: magic value identifying DMUB firmware meta info 289 * @fw_region_size: size of the firmware state region 290 * @trace_buffer_size: size of the tracebuffer region 291 * @fw_version: the firmware version information 292 * @dal_fw: 1 if the firmware is DAL 293 */ 294 struct dmub_fw_meta_info { 295 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 296 uint32_t fw_region_size; /**< size of the firmware state region */ 297 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 298 uint32_t fw_version; /**< the firmware version information */ 299 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 300 uint8_t reserved[3]; /**< padding bits */ 301 }; 302 303 /** 304 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 305 */ 306 union dmub_fw_meta { 307 struct dmub_fw_meta_info info; /**< metadata info */ 308 uint8_t reserved[64]; /**< padding bits */ 309 }; 310 311 #pragma pack(pop) 312 313 //============================================================================== 314 //< DMUB Trace Buffer>================================================================ 315 //============================================================================== 316 /** 317 * dmub_trace_code_t - firmware trace code, 32-bits 318 */ 319 typedef uint32_t dmub_trace_code_t; 320 321 /** 322 * struct dmcub_trace_buf_entry - Firmware trace entry 323 */ 324 struct dmcub_trace_buf_entry { 325 dmub_trace_code_t trace_code; /**< trace code for the event */ 326 uint32_t tick_count; /**< the tick count at time of trace */ 327 uint32_t param0; /**< trace defined parameter 0 */ 328 uint32_t param1; /**< trace defined parameter 1 */ 329 }; 330 331 //============================================================================== 332 //< DMUB_STATUS>================================================================ 333 //============================================================================== 334 335 /** 336 * DMCUB scratch registers can be used to determine firmware status. 337 * Current scratch register usage is as follows: 338 * 339 * SCRATCH0: FW Boot Status register 340 * SCRATCH5: LVTMA Status Register 341 * SCRATCH15: FW Boot Options register 342 */ 343 344 /** 345 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 346 */ 347 union dmub_fw_boot_status { 348 struct { 349 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 350 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 351 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 352 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 353 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 354 uint32_t reserved : 1; 355 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 356 357 } bits; /**< status bits */ 358 uint32_t all; /**< 32-bit access to status bits */ 359 }; 360 361 /** 362 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 363 */ 364 enum dmub_fw_boot_status_bit { 365 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 366 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 367 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 368 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 369 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 370 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 371 }; 372 373 /* Register bit definition for SCRATCH5 */ 374 union dmub_lvtma_status { 375 struct { 376 uint32_t psp_ok : 1; 377 uint32_t edp_on : 1; 378 uint32_t reserved : 30; 379 } bits; 380 uint32_t all; 381 }; 382 383 enum dmub_lvtma_status_bit { 384 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 385 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 386 }; 387 388 /** 389 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 390 */ 391 union dmub_fw_boot_options { 392 struct { 393 uint32_t pemu_env : 1; /**< 1 if PEMU */ 394 uint32_t fpga_env : 1; /**< 1 if FPGA */ 395 uint32_t optimized_init : 1; /**< 1 if optimized init */ 396 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 397 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 398 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 399 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 400 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 401 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 402 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 403 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 404 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 405 uint32_t power_optimization: 1; 406 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 407 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 408 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 409 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 410 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 411 412 uint32_t reserved : 15; /**< reserved */ 413 } bits; /**< boot bits */ 414 uint32_t all; /**< 32-bit access to bits */ 415 }; 416 417 enum dmub_fw_boot_options_bit { 418 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 419 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 420 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 421 }; 422 423 //============================================================================== 424 //</DMUB_STATUS>================================================================ 425 //============================================================================== 426 //< DMUB_VBIOS>================================================================= 427 //============================================================================== 428 429 /* 430 * enum dmub_cmd_vbios_type - VBIOS commands. 431 * 432 * Command IDs should be treated as stable ABI. 433 * Do not reuse or modify IDs. 434 */ 435 enum dmub_cmd_vbios_type { 436 /** 437 * Configures the DIG encoder. 438 */ 439 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 440 /** 441 * Controls the PHY. 442 */ 443 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 444 /** 445 * Sets the pixel clock/symbol clock. 446 */ 447 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 448 /** 449 * Enables or disables power gating. 450 */ 451 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 452 /** 453 * Controls embedded panels. 454 */ 455 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 456 /** 457 * Query DP alt status on a transmitter. 458 */ 459 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 460 /** 461 * Controls domain power gating 462 */ 463 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 464 }; 465 466 //============================================================================== 467 //</DMUB_VBIOS>================================================================= 468 //============================================================================== 469 //< DMUB_GPINT>================================================================= 470 //============================================================================== 471 472 /** 473 * The shifts and masks below may alternatively be used to format and read 474 * the command register bits. 475 */ 476 477 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 478 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 479 480 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 481 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 482 483 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 484 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 485 486 /** 487 * Command responses. 488 */ 489 490 /** 491 * Return response for DMUB_GPINT__STOP_FW command. 492 */ 493 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 494 495 /** 496 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 497 */ 498 union dmub_gpint_data_register { 499 struct { 500 uint32_t param : 16; /**< 16-bit parameter */ 501 uint32_t command_code : 12; /**< GPINT command */ 502 uint32_t status : 4; /**< Command status bit */ 503 } bits; /**< GPINT bit access */ 504 uint32_t all; /**< GPINT 32-bit access */ 505 }; 506 507 /* 508 * enum dmub_gpint_command - GPINT command to DMCUB FW 509 * 510 * Command IDs should be treated as stable ABI. 511 * Do not reuse or modify IDs. 512 */ 513 enum dmub_gpint_command { 514 /** 515 * Invalid command, ignored. 516 */ 517 DMUB_GPINT__INVALID_COMMAND = 0, 518 /** 519 * DESC: Queries the firmware version. 520 * RETURN: Firmware version. 521 */ 522 DMUB_GPINT__GET_FW_VERSION = 1, 523 /** 524 * DESC: Halts the firmware. 525 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 526 */ 527 DMUB_GPINT__STOP_FW = 2, 528 /** 529 * DESC: Get PSR state from FW. 530 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 531 */ 532 DMUB_GPINT__GET_PSR_STATE = 7, 533 /** 534 * DESC: Notifies DMCUB of the currently active streams. 535 * ARGS: Stream mask, 1 bit per active stream index. 536 */ 537 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 538 /** 539 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 540 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 541 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 542 * RETURN: PSR residency in milli-percent. 543 */ 544 DMUB_GPINT__PSR_RESIDENCY = 9, 545 546 /** 547 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 548 */ 549 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 550 }; 551 552 /** 553 * INBOX0 generic command definition 554 */ 555 union dmub_inbox0_cmd_common { 556 struct { 557 uint32_t command_code: 8; /**< INBOX0 command code */ 558 uint32_t param: 24; /**< 24-bit parameter */ 559 } bits; 560 uint32_t all; 561 }; 562 563 /** 564 * INBOX0 hw_lock command definition 565 */ 566 union dmub_inbox0_cmd_lock_hw { 567 struct { 568 uint32_t command_code: 8; 569 570 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 571 uint32_t hw_lock_client: 2; 572 573 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 574 uint32_t otg_inst: 3; 575 uint32_t opp_inst: 3; 576 uint32_t dig_inst: 3; 577 578 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 579 uint32_t lock_pipe: 1; 580 uint32_t lock_cursor: 1; 581 uint32_t lock_dig: 1; 582 uint32_t triple_buffer_lock: 1; 583 584 uint32_t lock: 1; /**< Lock */ 585 uint32_t should_release: 1; /**< Release */ 586 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 587 } bits; 588 uint32_t all; 589 }; 590 591 union dmub_inbox0_data_register { 592 union dmub_inbox0_cmd_common inbox0_cmd_common; 593 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 594 }; 595 596 enum dmub_inbox0_command { 597 /** 598 * DESC: Invalid command, ignored. 599 */ 600 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 601 /** 602 * DESC: Notification to acquire/release HW lock 603 * ARGS: 604 */ 605 DMUB_INBOX0_CMD__HW_LOCK = 1, 606 }; 607 //============================================================================== 608 //</DMUB_GPINT>================================================================= 609 //============================================================================== 610 //< DMUB_CMD>=================================================================== 611 //============================================================================== 612 613 /** 614 * Size in bytes of each DMUB command. 615 */ 616 #define DMUB_RB_CMD_SIZE 64 617 618 /** 619 * Maximum number of items in the DMUB ringbuffer. 620 */ 621 #define DMUB_RB_MAX_ENTRY 128 622 623 /** 624 * Ringbuffer size in bytes. 625 */ 626 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 627 628 /** 629 * REG_SET mask for reg offload. 630 */ 631 #define REG_SET_MASK 0xFFFF 632 633 /* 634 * enum dmub_cmd_type - DMUB inbox command. 635 * 636 * Command IDs should be treated as stable ABI. 637 * Do not reuse or modify IDs. 638 */ 639 enum dmub_cmd_type { 640 /** 641 * Invalid command. 642 */ 643 DMUB_CMD__NULL = 0, 644 /** 645 * Read modify write register sequence offload. 646 */ 647 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 648 /** 649 * Field update register sequence offload. 650 */ 651 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 652 /** 653 * Burst write sequence offload. 654 */ 655 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 656 /** 657 * Reg wait sequence offload. 658 */ 659 DMUB_CMD__REG_REG_WAIT = 4, 660 /** 661 * Workaround to avoid HUBP underflow during NV12 playback. 662 */ 663 DMUB_CMD__PLAT_54186_WA = 5, 664 /** 665 * Command type used to query FW feature caps. 666 */ 667 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 668 /** 669 * Command type used to get visual confirm color. 670 */ 671 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 672 /** 673 * Command type used for all PSR commands. 674 */ 675 DMUB_CMD__PSR = 64, 676 /** 677 * Command type used for all MALL commands. 678 */ 679 DMUB_CMD__MALL = 65, 680 /** 681 * Command type used for all ABM commands. 682 */ 683 DMUB_CMD__ABM = 66, 684 /** 685 * Command type used to update dirty rects in FW. 686 */ 687 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 688 /** 689 * Command type used to update cursor info in FW. 690 */ 691 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 692 /** 693 * Command type used for HW locking in FW. 694 */ 695 DMUB_CMD__HW_LOCK = 69, 696 /** 697 * Command type used to access DP AUX. 698 */ 699 DMUB_CMD__DP_AUX_ACCESS = 70, 700 /** 701 * Command type used for OUTBOX1 notification enable 702 */ 703 DMUB_CMD__OUTBOX1_ENABLE = 71, 704 705 /** 706 * Command type used for all idle optimization commands. 707 */ 708 DMUB_CMD__IDLE_OPT = 72, 709 /** 710 * Command type used for all clock manager commands. 711 */ 712 DMUB_CMD__CLK_MGR = 73, 713 /** 714 * Command type used for all panel control commands. 715 */ 716 DMUB_CMD__PANEL_CNTL = 74, 717 /** 718 * Command type used for <TODO:description> 719 */ 720 DMUB_CMD__CAB_FOR_SS = 75, 721 722 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 723 724 /** 725 * Command type used for interfacing with DPIA. 726 */ 727 DMUB_CMD__DPIA = 77, 728 /** 729 * Command type used for EDID CEA parsing 730 */ 731 DMUB_CMD__EDID_CEA = 79, 732 /** 733 * Command type used for getting usbc cable ID 734 */ 735 DMUB_CMD_GET_USBC_CABLE_ID = 81, 736 /** 737 * Command type used to query HPD state. 738 */ 739 DMUB_CMD__QUERY_HPD_STATE = 82, 740 /** 741 * Command type used for all VBIOS interface commands. 742 */ 743 744 /** 745 * Command type used for all SECURE_DISPLAY commands. 746 */ 747 DMUB_CMD__SECURE_DISPLAY = 85, 748 749 /** 750 * Command type used to set DPIA HPD interrupt state 751 */ 752 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 753 754 DMUB_CMD__VBIOS = 128, 755 }; 756 757 /** 758 * enum dmub_out_cmd_type - DMUB outbox commands. 759 */ 760 enum dmub_out_cmd_type { 761 /** 762 * Invalid outbox command, ignored. 763 */ 764 DMUB_OUT_CMD__NULL = 0, 765 /** 766 * Command type used for DP AUX Reply data notification 767 */ 768 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 769 /** 770 * Command type used for DP HPD event notification 771 */ 772 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 773 /** 774 * Command type used for SET_CONFIG Reply notification 775 */ 776 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 777 /** 778 * Command type used for USB4 DPIA notification 779 */ 780 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 781 }; 782 783 /* DMUB_CMD__DPIA command sub-types. */ 784 enum dmub_cmd_dpia_type { 785 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 786 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 787 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 788 }; 789 790 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 791 enum dmub_cmd_dpia_notification_type { 792 DPIA_NOTIFY__BW_ALLOCATION = 0, 793 }; 794 795 #pragma pack(push, 1) 796 797 /** 798 * struct dmub_cmd_header - Common command header fields. 799 */ 800 struct dmub_cmd_header { 801 unsigned int type : 8; /**< command type */ 802 unsigned int sub_type : 8; /**< command sub type */ 803 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 804 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 805 unsigned int reserved0 : 6; /**< reserved bits */ 806 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 807 unsigned int reserved1 : 2; /**< reserved bits */ 808 }; 809 810 /* 811 * struct dmub_cmd_read_modify_write_sequence - Read modify write 812 * 813 * 60 payload bytes can hold up to 5 sets of read modify writes, 814 * each take 3 dwords. 815 * 816 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 817 * 818 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 819 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 820 */ 821 struct dmub_cmd_read_modify_write_sequence { 822 uint32_t addr; /**< register address */ 823 uint32_t modify_mask; /**< modify mask */ 824 uint32_t modify_value; /**< modify value */ 825 }; 826 827 /** 828 * Maximum number of ops in read modify write sequence. 829 */ 830 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 831 832 /** 833 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 834 */ 835 struct dmub_rb_cmd_read_modify_write { 836 struct dmub_cmd_header header; /**< command header */ 837 /** 838 * Read modify write sequence. 839 */ 840 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 841 }; 842 843 /* 844 * Update a register with specified masks and values sequeunce 845 * 846 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 847 * 848 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 849 * 850 * 851 * USE CASE: 852 * 1. auto-increment register where additional read would update pointer and produce wrong result 853 * 2. toggle a bit without read in the middle 854 */ 855 856 struct dmub_cmd_reg_field_update_sequence { 857 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 858 uint32_t modify_value; /**< value to update with */ 859 }; 860 861 /** 862 * Maximum number of ops in field update sequence. 863 */ 864 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 865 866 /** 867 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 868 */ 869 struct dmub_rb_cmd_reg_field_update_sequence { 870 struct dmub_cmd_header header; /**< command header */ 871 uint32_t addr; /**< register address */ 872 /** 873 * Field update sequence. 874 */ 875 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 876 }; 877 878 879 /** 880 * Maximum number of burst write values. 881 */ 882 #define DMUB_BURST_WRITE_VALUES__MAX 14 883 884 /* 885 * struct dmub_rb_cmd_burst_write - Burst write 886 * 887 * support use case such as writing out LUTs. 888 * 889 * 60 payload bytes can hold up to 14 values to write to given address 890 * 891 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 892 */ 893 struct dmub_rb_cmd_burst_write { 894 struct dmub_cmd_header header; /**< command header */ 895 uint32_t addr; /**< register start address */ 896 /** 897 * Burst write register values. 898 */ 899 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 900 }; 901 902 /** 903 * struct dmub_rb_cmd_common - Common command header 904 */ 905 struct dmub_rb_cmd_common { 906 struct dmub_cmd_header header; /**< command header */ 907 /** 908 * Padding to RB_CMD_SIZE 909 */ 910 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 911 }; 912 913 /** 914 * struct dmub_cmd_reg_wait_data - Register wait data 915 */ 916 struct dmub_cmd_reg_wait_data { 917 uint32_t addr; /**< Register address */ 918 uint32_t mask; /**< Mask for register bits */ 919 uint32_t condition_field_value; /**< Value to wait for */ 920 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 921 }; 922 923 /** 924 * struct dmub_rb_cmd_reg_wait - Register wait command 925 */ 926 struct dmub_rb_cmd_reg_wait { 927 struct dmub_cmd_header header; /**< Command header */ 928 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 929 }; 930 931 /** 932 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 933 * 934 * Reprograms surface parameters to avoid underflow. 935 */ 936 struct dmub_cmd_PLAT_54186_wa { 937 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 938 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 939 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 940 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 941 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 942 struct { 943 uint8_t hubp_inst : 4; /**< HUBP instance */ 944 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 945 uint8_t immediate :1; /**< Immediate flip */ 946 uint8_t vmid : 4; /**< VMID */ 947 uint8_t grph_stereo : 1; /**< 1 if stereo */ 948 uint32_t reserved : 21; /**< Reserved */ 949 } flip_params; /**< Pageflip parameters */ 950 uint32_t reserved[9]; /**< Reserved bits */ 951 }; 952 953 /** 954 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 955 */ 956 struct dmub_rb_cmd_PLAT_54186_wa { 957 struct dmub_cmd_header header; /**< Command header */ 958 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 959 }; 960 961 /** 962 * struct dmub_rb_cmd_mall - MALL command data. 963 */ 964 struct dmub_rb_cmd_mall { 965 struct dmub_cmd_header header; /**< Common command header */ 966 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 967 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 968 uint32_t tmr_delay; /**< Timer delay */ 969 uint32_t tmr_scale; /**< Timer scale */ 970 uint16_t cursor_width; /**< Cursor width in pixels */ 971 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 972 uint16_t cursor_height; /**< Cursor height in pixels */ 973 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 974 uint8_t debug_bits; /**< Debug bits */ 975 976 uint8_t reserved1; /**< Reserved bits */ 977 uint8_t reserved2; /**< Reserved bits */ 978 }; 979 980 /** 981 * enum dmub_cmd_cab_type - TODO: 982 */ 983 enum dmub_cmd_cab_type { 984 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 985 DMUB_CMD__CAB_NO_DCN_REQ = 1, 986 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 987 }; 988 989 /** 990 * struct dmub_rb_cmd_cab_for_ss - TODO: 991 */ 992 struct dmub_rb_cmd_cab_for_ss { 993 struct dmub_cmd_header header; 994 uint8_t cab_alloc_ways; /* total number of ways */ 995 uint8_t debug_bits; /* debug bits */ 996 }; 997 998 enum mclk_switch_mode { 999 NONE = 0, 1000 FPO = 1, 1001 SUBVP = 2, 1002 VBLANK = 3, 1003 }; 1004 1005 /* Per pipe struct which stores the MCLK switch mode 1006 * data to be sent to DMUB. 1007 * Named "v2" for now -- once FPO and SUBVP are fully merged 1008 * the type name can be updated 1009 */ 1010 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1011 union { 1012 struct { 1013 uint32_t pix_clk_100hz; 1014 uint16_t main_vblank_start; 1015 uint16_t main_vblank_end; 1016 uint16_t mall_region_lines; 1017 uint16_t prefetch_lines; 1018 uint16_t prefetch_to_mall_start_lines; 1019 uint16_t processing_delay_lines; 1020 uint16_t htotal; // required to calculate line time for multi-display cases 1021 uint16_t vtotal; 1022 uint8_t main_pipe_index; 1023 uint8_t phantom_pipe_index; 1024 /* Since the microschedule is calculated in terms of OTG lines, 1025 * include any scaling factors to make sure when we get accurate 1026 * conversion when programming MALL_START_LINE (which is in terms 1027 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1028 * is 1/2 (numerator = 1, denominator = 2). 1029 */ 1030 uint8_t scale_factor_numerator; 1031 uint8_t scale_factor_denominator; 1032 uint8_t is_drr; 1033 uint8_t main_split_pipe_index; 1034 uint8_t phantom_split_pipe_index; 1035 } subvp_data; 1036 1037 struct { 1038 uint32_t pix_clk_100hz; 1039 uint16_t vblank_start; 1040 uint16_t vblank_end; 1041 uint16_t vstartup_start; 1042 uint16_t vtotal; 1043 uint16_t htotal; 1044 uint8_t vblank_pipe_index; 1045 uint8_t padding[1]; 1046 struct { 1047 uint8_t drr_in_use; 1048 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1049 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1050 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1051 uint8_t use_ramping; // Use ramping or not 1052 uint8_t drr_vblank_start_margin; 1053 } drr_info; // DRR considered as part of SubVP + VBLANK case 1054 } vblank_data; 1055 } pipe_config; 1056 1057 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1058 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1059 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1060 */ 1061 uint8_t mode; // enum mclk_switch_mode 1062 }; 1063 1064 /** 1065 * Config data for Sub-VP and FPO 1066 * Named "v2" for now -- once FPO and SUBVP are fully merged 1067 * the type name can be updated 1068 */ 1069 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1070 uint16_t watermark_a_cache; 1071 uint8_t vertical_int_margin_us; 1072 uint8_t pstate_allow_width_us; 1073 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1074 }; 1075 1076 /** 1077 * DMUB rb command definition for Sub-VP and FPO 1078 * Named "v2" for now -- once FPO and SUBVP are fully merged 1079 * the type name can be updated 1080 */ 1081 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1082 struct dmub_cmd_header header; 1083 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1084 }; 1085 1086 /** 1087 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1088 */ 1089 enum dmub_cmd_idle_opt_type { 1090 /** 1091 * DCN hardware restore. 1092 */ 1093 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1094 1095 /** 1096 * DCN hardware save. 1097 */ 1098 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1099 }; 1100 1101 /** 1102 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1103 */ 1104 struct dmub_rb_cmd_idle_opt_dcn_restore { 1105 struct dmub_cmd_header header; /**< header */ 1106 }; 1107 1108 /** 1109 * struct dmub_clocks - Clock update notification. 1110 */ 1111 struct dmub_clocks { 1112 uint32_t dispclk_khz; /**< dispclk kHz */ 1113 uint32_t dppclk_khz; /**< dppclk kHz */ 1114 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1115 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1116 }; 1117 1118 /** 1119 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1120 */ 1121 enum dmub_cmd_clk_mgr_type { 1122 /** 1123 * Notify DMCUB of clock update. 1124 */ 1125 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1126 }; 1127 1128 /** 1129 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1130 */ 1131 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1132 struct dmub_cmd_header header; /**< header */ 1133 struct dmub_clocks clocks; /**< clock data */ 1134 }; 1135 1136 /** 1137 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1138 */ 1139 struct dmub_cmd_digx_encoder_control_data { 1140 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1141 }; 1142 1143 /** 1144 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1145 */ 1146 struct dmub_rb_cmd_digx_encoder_control { 1147 struct dmub_cmd_header header; /**< header */ 1148 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1149 }; 1150 1151 /** 1152 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1153 */ 1154 struct dmub_cmd_set_pixel_clock_data { 1155 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1156 }; 1157 1158 /** 1159 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1160 */ 1161 struct dmub_rb_cmd_set_pixel_clock { 1162 struct dmub_cmd_header header; /**< header */ 1163 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1164 }; 1165 1166 /** 1167 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1168 */ 1169 struct dmub_cmd_enable_disp_power_gating_data { 1170 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1171 }; 1172 1173 /** 1174 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1175 */ 1176 struct dmub_rb_cmd_enable_disp_power_gating { 1177 struct dmub_cmd_header header; /**< header */ 1178 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1179 }; 1180 1181 /** 1182 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1183 */ 1184 struct dmub_dig_transmitter_control_data_v1_7 { 1185 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1186 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1187 union { 1188 uint8_t digmode; /**< enum atom_encode_mode_def */ 1189 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1190 } mode_laneset; 1191 uint8_t lanenum; /**< Number of lanes */ 1192 union { 1193 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1194 } symclk_units; 1195 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1196 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1197 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1198 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1199 uint8_t reserved1; /**< For future use */ 1200 uint8_t reserved2[3]; /**< For future use */ 1201 uint32_t reserved3[11]; /**< For future use */ 1202 }; 1203 1204 /** 1205 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1206 */ 1207 union dmub_cmd_dig1_transmitter_control_data { 1208 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1209 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1210 }; 1211 1212 /** 1213 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1214 */ 1215 struct dmub_rb_cmd_dig1_transmitter_control { 1216 struct dmub_cmd_header header; /**< header */ 1217 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1218 }; 1219 1220 /** 1221 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1222 */ 1223 struct dmub_rb_cmd_domain_control_data { 1224 uint8_t inst : 6; /**< DOMAIN instance to control */ 1225 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1226 uint8_t reserved[3]; /**< Reserved for future use */ 1227 }; 1228 1229 /** 1230 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1231 */ 1232 struct dmub_rb_cmd_domain_control { 1233 struct dmub_cmd_header header; /**< header */ 1234 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1235 }; 1236 1237 /** 1238 * DPIA tunnel command parameters. 1239 */ 1240 struct dmub_cmd_dig_dpia_control_data { 1241 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1242 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1243 union { 1244 uint8_t digmode; /** enum atom_encode_mode_def */ 1245 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1246 } mode_laneset; 1247 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1248 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1249 uint8_t hpdsel; /** =0: HPD is not assigned */ 1250 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1251 uint8_t dpia_id; /** Index of DPIA */ 1252 uint8_t fec_rdy : 1; 1253 uint8_t reserved : 7; 1254 uint32_t reserved1; 1255 }; 1256 1257 /** 1258 * DMUB command for DPIA tunnel control. 1259 */ 1260 struct dmub_rb_cmd_dig1_dpia_control { 1261 struct dmub_cmd_header header; 1262 struct dmub_cmd_dig_dpia_control_data dpia_control; 1263 }; 1264 1265 /** 1266 * SET_CONFIG Command Payload 1267 */ 1268 struct set_config_cmd_payload { 1269 uint8_t msg_type; /* set config message type */ 1270 uint8_t msg_data; /* set config message data */ 1271 }; 1272 1273 /** 1274 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1275 */ 1276 struct dmub_cmd_set_config_control_data { 1277 struct set_config_cmd_payload cmd_pkt; 1278 uint8_t instance; /* DPIA instance */ 1279 uint8_t immed_status; /* Immediate status returned in case of error */ 1280 }; 1281 1282 /** 1283 * DMUB command structure for SET_CONFIG command. 1284 */ 1285 struct dmub_rb_cmd_set_config_access { 1286 struct dmub_cmd_header header; /* header */ 1287 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1288 }; 1289 1290 /** 1291 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1292 */ 1293 struct dmub_cmd_mst_alloc_slots_control_data { 1294 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1295 uint8_t instance; /* DPIA instance */ 1296 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1297 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1298 }; 1299 1300 /** 1301 * DMUB command structure for SET_ command. 1302 */ 1303 struct dmub_rb_cmd_set_mst_alloc_slots { 1304 struct dmub_cmd_header header; /* header */ 1305 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1306 }; 1307 1308 /** 1309 * DMUB command structure for DPIA HPD int enable control. 1310 */ 1311 struct dmub_rb_cmd_dpia_hpd_int_enable { 1312 struct dmub_cmd_header header; /* header */ 1313 uint32_t enable; /* dpia hpd interrupt enable */ 1314 }; 1315 1316 /** 1317 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1318 */ 1319 struct dmub_rb_cmd_dpphy_init { 1320 struct dmub_cmd_header header; /**< header */ 1321 uint8_t reserved[60]; /**< reserved bits */ 1322 }; 1323 1324 /** 1325 * enum dp_aux_request_action - DP AUX request command listing. 1326 * 1327 * 4 AUX request command bits are shifted to high nibble. 1328 */ 1329 enum dp_aux_request_action { 1330 /** I2C-over-AUX write request */ 1331 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1332 /** I2C-over-AUX read request */ 1333 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1334 /** I2C-over-AUX write status request */ 1335 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1336 /** I2C-over-AUX write request with MOT=1 */ 1337 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1338 /** I2C-over-AUX read request with MOT=1 */ 1339 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1340 /** I2C-over-AUX write status request with MOT=1 */ 1341 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1342 /** Native AUX write request */ 1343 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1344 /** Native AUX read request */ 1345 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1346 }; 1347 1348 /** 1349 * enum aux_return_code_type - DP AUX process return code listing. 1350 */ 1351 enum aux_return_code_type { 1352 /** AUX process succeeded */ 1353 AUX_RET_SUCCESS = 0, 1354 /** AUX process failed with unknown reason */ 1355 AUX_RET_ERROR_UNKNOWN, 1356 /** AUX process completed with invalid reply */ 1357 AUX_RET_ERROR_INVALID_REPLY, 1358 /** AUX process timed out */ 1359 AUX_RET_ERROR_TIMEOUT, 1360 /** HPD was low during AUX process */ 1361 AUX_RET_ERROR_HPD_DISCON, 1362 /** Failed to acquire AUX engine */ 1363 AUX_RET_ERROR_ENGINE_ACQUIRE, 1364 /** AUX request not supported */ 1365 AUX_RET_ERROR_INVALID_OPERATION, 1366 /** AUX process not available */ 1367 AUX_RET_ERROR_PROTOCOL_ERROR, 1368 }; 1369 1370 /** 1371 * enum aux_channel_type - DP AUX channel type listing. 1372 */ 1373 enum aux_channel_type { 1374 /** AUX thru Legacy DP AUX */ 1375 AUX_CHANNEL_LEGACY_DDC, 1376 /** AUX thru DPIA DP tunneling */ 1377 AUX_CHANNEL_DPIA 1378 }; 1379 1380 /** 1381 * struct aux_transaction_parameters - DP AUX request transaction data 1382 */ 1383 struct aux_transaction_parameters { 1384 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1385 uint8_t action; /**< enum dp_aux_request_action */ 1386 uint8_t length; /**< DP AUX request data length */ 1387 uint8_t reserved; /**< For future use */ 1388 uint32_t address; /**< DP AUX address */ 1389 uint8_t data[16]; /**< DP AUX write data */ 1390 }; 1391 1392 /** 1393 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1394 */ 1395 struct dmub_cmd_dp_aux_control_data { 1396 uint8_t instance; /**< AUX instance or DPIA instance */ 1397 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1398 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1399 uint8_t reserved0; /**< For future use */ 1400 uint16_t timeout; /**< timeout time in us */ 1401 uint16_t reserved1; /**< For future use */ 1402 enum aux_channel_type type; /**< enum aux_channel_type */ 1403 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1404 }; 1405 1406 /** 1407 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1408 */ 1409 struct dmub_rb_cmd_dp_aux_access { 1410 /** 1411 * Command header. 1412 */ 1413 struct dmub_cmd_header header; 1414 /** 1415 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1416 */ 1417 struct dmub_cmd_dp_aux_control_data aux_control; 1418 }; 1419 1420 /** 1421 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1422 */ 1423 struct dmub_rb_cmd_outbox1_enable { 1424 /** 1425 * Command header. 1426 */ 1427 struct dmub_cmd_header header; 1428 /** 1429 * enable: 0x0 -> disable outbox1 notification (default value) 1430 * 0x1 -> enable outbox1 notification 1431 */ 1432 uint32_t enable; 1433 }; 1434 1435 /* DP AUX Reply command - OutBox Cmd */ 1436 /** 1437 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1438 */ 1439 struct aux_reply_data { 1440 /** 1441 * Aux cmd 1442 */ 1443 uint8_t command; 1444 /** 1445 * Aux reply data length (max: 16 bytes) 1446 */ 1447 uint8_t length; 1448 /** 1449 * Alignment only 1450 */ 1451 uint8_t pad[2]; 1452 /** 1453 * Aux reply data 1454 */ 1455 uint8_t data[16]; 1456 }; 1457 1458 /** 1459 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1460 */ 1461 struct aux_reply_control_data { 1462 /** 1463 * Reserved for future use 1464 */ 1465 uint32_t handle; 1466 /** 1467 * Aux Instance 1468 */ 1469 uint8_t instance; 1470 /** 1471 * Aux transaction result: definition in enum aux_return_code_type 1472 */ 1473 uint8_t result; 1474 /** 1475 * Alignment only 1476 */ 1477 uint16_t pad; 1478 }; 1479 1480 /** 1481 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1482 */ 1483 struct dmub_rb_cmd_dp_aux_reply { 1484 /** 1485 * Command header. 1486 */ 1487 struct dmub_cmd_header header; 1488 /** 1489 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1490 */ 1491 struct aux_reply_control_data control; 1492 /** 1493 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1494 */ 1495 struct aux_reply_data reply_data; 1496 }; 1497 1498 /* DP HPD Notify command - OutBox Cmd */ 1499 /** 1500 * DP HPD Type 1501 */ 1502 enum dp_hpd_type { 1503 /** 1504 * Normal DP HPD 1505 */ 1506 DP_HPD = 0, 1507 /** 1508 * DP HPD short pulse 1509 */ 1510 DP_IRQ 1511 }; 1512 1513 /** 1514 * DP HPD Status 1515 */ 1516 enum dp_hpd_status { 1517 /** 1518 * DP_HPD status low 1519 */ 1520 DP_HPD_UNPLUG = 0, 1521 /** 1522 * DP_HPD status high 1523 */ 1524 DP_HPD_PLUG 1525 }; 1526 1527 /** 1528 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1529 */ 1530 struct dp_hpd_data { 1531 /** 1532 * DP HPD instance 1533 */ 1534 uint8_t instance; 1535 /** 1536 * HPD type 1537 */ 1538 uint8_t hpd_type; 1539 /** 1540 * HPD status: only for type: DP_HPD to indicate status 1541 */ 1542 uint8_t hpd_status; 1543 /** 1544 * Alignment only 1545 */ 1546 uint8_t pad; 1547 }; 1548 1549 /** 1550 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1551 */ 1552 struct dmub_rb_cmd_dp_hpd_notify { 1553 /** 1554 * Command header. 1555 */ 1556 struct dmub_cmd_header header; 1557 /** 1558 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1559 */ 1560 struct dp_hpd_data hpd_data; 1561 }; 1562 1563 /** 1564 * Definition of a SET_CONFIG reply from DPOA. 1565 */ 1566 enum set_config_status { 1567 SET_CONFIG_PENDING = 0, 1568 SET_CONFIG_ACK_RECEIVED, 1569 SET_CONFIG_RX_TIMEOUT, 1570 SET_CONFIG_UNKNOWN_ERROR, 1571 }; 1572 1573 /** 1574 * Definition of a set_config reply 1575 */ 1576 struct set_config_reply_control_data { 1577 uint8_t instance; /* DPIA Instance */ 1578 uint8_t status; /* Set Config reply */ 1579 uint16_t pad; /* Alignment */ 1580 }; 1581 1582 /** 1583 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1584 */ 1585 struct dmub_rb_cmd_dp_set_config_reply { 1586 struct dmub_cmd_header header; 1587 struct set_config_reply_control_data set_config_reply_control; 1588 }; 1589 1590 /** 1591 * Definition of a DPIA notification header 1592 */ 1593 struct dpia_notification_header { 1594 uint8_t instance; /**< DPIA Instance */ 1595 uint8_t reserved[3]; 1596 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 1597 }; 1598 1599 /** 1600 * Definition of the common data struct of DPIA notification 1601 */ 1602 struct dpia_notification_common { 1603 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 1604 - sizeof(struct dpia_notification_header)]; 1605 }; 1606 1607 /** 1608 * Definition of a DPIA notification data 1609 */ 1610 struct dpia_bw_allocation_notify_data { 1611 union { 1612 struct { 1613 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 1614 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 1615 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 1616 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 1617 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 1618 uint16_t reserved: 11; /**< Reserved */ 1619 } bits; 1620 1621 uint16_t flags; 1622 }; 1623 1624 uint8_t cm_id; /**< CM ID */ 1625 uint8_t group_id; /**< Group ID */ 1626 uint8_t granularity; /**< BW Allocation Granularity */ 1627 uint8_t estimated_bw; /**< Estimated_BW */ 1628 uint8_t allocated_bw; /**< Allocated_BW */ 1629 uint8_t reserved; 1630 }; 1631 1632 /** 1633 * union dpia_notify_data_type - DPIA Notification in Outbox command 1634 */ 1635 union dpia_notification_data { 1636 /** 1637 * DPIA Notification for common data struct 1638 */ 1639 struct dpia_notification_common common_data; 1640 1641 /** 1642 * DPIA Notification for DP BW Allocation support 1643 */ 1644 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 1645 }; 1646 1647 /** 1648 * Definition of a DPIA notification payload 1649 */ 1650 struct dpia_notification_payload { 1651 struct dpia_notification_header header; 1652 union dpia_notification_data data; /**< DPIA notification payload data */ 1653 }; 1654 1655 /** 1656 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 1657 */ 1658 struct dmub_rb_cmd_dpia_notification { 1659 struct dmub_cmd_header header; /**< DPIA notification header */ 1660 struct dpia_notification_payload payload; /**< DPIA notification payload */ 1661 }; 1662 1663 /** 1664 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1665 */ 1666 struct dmub_cmd_hpd_state_query_data { 1667 uint8_t instance; /**< HPD instance or DPIA instance */ 1668 uint8_t result; /**< For returning HPD state */ 1669 uint16_t pad; /** < Alignment */ 1670 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1671 enum aux_return_code_type status; /**< for returning the status of command */ 1672 }; 1673 1674 /** 1675 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1676 */ 1677 struct dmub_rb_cmd_query_hpd_state { 1678 /** 1679 * Command header. 1680 */ 1681 struct dmub_cmd_header header; 1682 /** 1683 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1684 */ 1685 struct dmub_cmd_hpd_state_query_data data; 1686 }; 1687 1688 /* 1689 * Command IDs should be treated as stable ABI. 1690 * Do not reuse or modify IDs. 1691 */ 1692 1693 /** 1694 * PSR command sub-types. 1695 */ 1696 enum dmub_cmd_psr_type { 1697 /** 1698 * Set PSR version support. 1699 */ 1700 DMUB_CMD__PSR_SET_VERSION = 0, 1701 /** 1702 * Copy driver-calculated parameters to PSR state. 1703 */ 1704 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1705 /** 1706 * Enable PSR. 1707 */ 1708 DMUB_CMD__PSR_ENABLE = 2, 1709 1710 /** 1711 * Disable PSR. 1712 */ 1713 DMUB_CMD__PSR_DISABLE = 3, 1714 1715 /** 1716 * Set PSR level. 1717 * PSR level is a 16-bit value dicated by driver that 1718 * will enable/disable different functionality. 1719 */ 1720 DMUB_CMD__PSR_SET_LEVEL = 4, 1721 1722 /** 1723 * Forces PSR enabled until an explicit PSR disable call. 1724 */ 1725 DMUB_CMD__PSR_FORCE_STATIC = 5, 1726 /** 1727 * Set vtotal in psr active for FreeSync PSR. 1728 */ 1729 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1730 /** 1731 * Set PSR power option 1732 */ 1733 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1734 }; 1735 1736 enum dmub_cmd_fams_type { 1737 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1738 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1739 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1740 /** 1741 * For SubVP set manual trigger in FW because it 1742 * triggers DRR_UPDATE_PENDING which SubVP relies 1743 * on (for any SubVP cases that use a DRR display) 1744 */ 1745 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1746 }; 1747 1748 /** 1749 * PSR versions. 1750 */ 1751 enum psr_version { 1752 /** 1753 * PSR version 1. 1754 */ 1755 PSR_VERSION_1 = 0, 1756 /** 1757 * Freesync PSR SU. 1758 */ 1759 PSR_VERSION_SU_1 = 1, 1760 /** 1761 * PSR not supported. 1762 */ 1763 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1764 }; 1765 1766 /** 1767 * enum dmub_cmd_mall_type - MALL commands 1768 */ 1769 enum dmub_cmd_mall_type { 1770 /** 1771 * Allows display refresh from MALL. 1772 */ 1773 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1774 /** 1775 * Disallows display refresh from MALL. 1776 */ 1777 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1778 /** 1779 * Cursor copy for MALL. 1780 */ 1781 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1782 /** 1783 * Controls DF requests. 1784 */ 1785 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1786 }; 1787 1788 /** 1789 * PHY Link rate for DP. 1790 */ 1791 enum phy_link_rate { 1792 /** 1793 * not supported. 1794 */ 1795 PHY_RATE_UNKNOWN = 0, 1796 /** 1797 * Rate_1 (RBR) - 1.62 Gbps/Lane 1798 */ 1799 PHY_RATE_162 = 1, 1800 /** 1801 * Rate_2 - 2.16 Gbps/Lane 1802 */ 1803 PHY_RATE_216 = 2, 1804 /** 1805 * Rate_3 - 2.43 Gbps/Lane 1806 */ 1807 PHY_RATE_243 = 3, 1808 /** 1809 * Rate_4 (HBR) - 2.70 Gbps/Lane 1810 */ 1811 PHY_RATE_270 = 4, 1812 /** 1813 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1814 */ 1815 PHY_RATE_324 = 5, 1816 /** 1817 * Rate_6 - 4.32 Gbps/Lane 1818 */ 1819 PHY_RATE_432 = 6, 1820 /** 1821 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1822 */ 1823 PHY_RATE_540 = 7, 1824 /** 1825 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1826 */ 1827 PHY_RATE_810 = 8, 1828 /** 1829 * UHBR10 - 10.0 Gbps/Lane 1830 */ 1831 PHY_RATE_1000 = 9, 1832 /** 1833 * UHBR13.5 - 13.5 Gbps/Lane 1834 */ 1835 PHY_RATE_1350 = 10, 1836 /** 1837 * UHBR10 - 20.0 Gbps/Lane 1838 */ 1839 PHY_RATE_2000 = 11, 1840 }; 1841 1842 /** 1843 * enum dmub_phy_fsm_state - PHY FSM states. 1844 * PHY FSM state to transit to during PSR enable/disable. 1845 */ 1846 enum dmub_phy_fsm_state { 1847 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1848 DMUB_PHY_FSM_RESET, 1849 DMUB_PHY_FSM_RESET_RELEASED, 1850 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1851 DMUB_PHY_FSM_INITIALIZED, 1852 DMUB_PHY_FSM_CALIBRATED, 1853 DMUB_PHY_FSM_CALIBRATED_LP, 1854 DMUB_PHY_FSM_CALIBRATED_PG, 1855 DMUB_PHY_FSM_POWER_DOWN, 1856 DMUB_PHY_FSM_PLL_EN, 1857 DMUB_PHY_FSM_TX_EN, 1858 DMUB_PHY_FSM_FAST_LP, 1859 }; 1860 1861 /** 1862 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1863 */ 1864 struct dmub_cmd_psr_copy_settings_data { 1865 /** 1866 * Flags that can be set by driver to change some PSR behaviour. 1867 */ 1868 union dmub_psr_debug_flags debug; 1869 /** 1870 * 16-bit value dicated by driver that will enable/disable different functionality. 1871 */ 1872 uint16_t psr_level; 1873 /** 1874 * DPP HW instance. 1875 */ 1876 uint8_t dpp_inst; 1877 /** 1878 * MPCC HW instance. 1879 * Not used in dmub fw, 1880 * dmub fw will get active opp by reading odm registers. 1881 */ 1882 uint8_t mpcc_inst; 1883 /** 1884 * OPP HW instance. 1885 * Not used in dmub fw, 1886 * dmub fw will get active opp by reading odm registers. 1887 */ 1888 uint8_t opp_inst; 1889 /** 1890 * OTG HW instance. 1891 */ 1892 uint8_t otg_inst; 1893 /** 1894 * DIG FE HW instance. 1895 */ 1896 uint8_t digfe_inst; 1897 /** 1898 * DIG BE HW instance. 1899 */ 1900 uint8_t digbe_inst; 1901 /** 1902 * DP PHY HW instance. 1903 */ 1904 uint8_t dpphy_inst; 1905 /** 1906 * AUX HW instance. 1907 */ 1908 uint8_t aux_inst; 1909 /** 1910 * Determines if SMU optimzations are enabled/disabled. 1911 */ 1912 uint8_t smu_optimizations_en; 1913 /** 1914 * Unused. 1915 * TODO: Remove. 1916 */ 1917 uint8_t frame_delay; 1918 /** 1919 * If RFB setup time is greater than the total VBLANK time, 1920 * it is not possible for the sink to capture the video frame 1921 * in the same frame the SDP is sent. In this case, 1922 * the frame capture indication bit should be set and an extra 1923 * static frame should be transmitted to the sink. 1924 */ 1925 uint8_t frame_cap_ind; 1926 /** 1927 * Granularity of Y offset supported by sink. 1928 */ 1929 uint8_t su_y_granularity; 1930 /** 1931 * Indicates whether sink should start capturing 1932 * immediately following active scan line, 1933 * or starting with the 2nd active scan line. 1934 */ 1935 uint8_t line_capture_indication; 1936 /** 1937 * Multi-display optimizations are implemented on certain ASICs. 1938 */ 1939 uint8_t multi_disp_optimizations_en; 1940 /** 1941 * The last possible line SDP may be transmitted without violating 1942 * the RFB setup time or entering the active video frame. 1943 */ 1944 uint16_t init_sdp_deadline; 1945 /** 1946 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1947 */ 1948 uint8_t rate_control_caps ; 1949 /* 1950 * Force PSRSU always doing full frame update 1951 */ 1952 uint8_t force_ffu_mode; 1953 /** 1954 * Length of each horizontal line in us. 1955 */ 1956 uint32_t line_time_in_us; 1957 /** 1958 * FEC enable status in driver 1959 */ 1960 uint8_t fec_enable_status; 1961 /** 1962 * FEC re-enable delay when PSR exit. 1963 * unit is 100us, range form 0~255(0xFF). 1964 */ 1965 uint8_t fec_enable_delay_in100us; 1966 /** 1967 * PSR control version. 1968 */ 1969 uint8_t cmd_version; 1970 /** 1971 * Panel Instance. 1972 * Panel isntance to identify which psr_state to use 1973 * Currently the support is only for 0 or 1 1974 */ 1975 uint8_t panel_inst; 1976 /* 1977 * DSC enable status in driver 1978 */ 1979 uint8_t dsc_enable_status; 1980 /* 1981 * Use FSM state for PSR power up/down 1982 */ 1983 uint8_t use_phy_fsm; 1984 /** 1985 * frame delay for frame re-lock 1986 */ 1987 uint8_t relock_delay_frame_cnt; 1988 /** 1989 * Explicit padding to 2 byte boundary. 1990 */ 1991 uint8_t pad3; 1992 /** 1993 * DSC Slice height. 1994 */ 1995 uint16_t dsc_slice_height; 1996 /** 1997 * Explicit padding to 4 byte boundary. 1998 */ 1999 uint16_t pad; 2000 }; 2001 2002 /** 2003 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2004 */ 2005 struct dmub_rb_cmd_psr_copy_settings { 2006 /** 2007 * Command header. 2008 */ 2009 struct dmub_cmd_header header; 2010 /** 2011 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2012 */ 2013 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2014 }; 2015 2016 /** 2017 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2018 */ 2019 struct dmub_cmd_psr_set_level_data { 2020 /** 2021 * 16-bit value dicated by driver that will enable/disable different functionality. 2022 */ 2023 uint16_t psr_level; 2024 /** 2025 * PSR control version. 2026 */ 2027 uint8_t cmd_version; 2028 /** 2029 * Panel Instance. 2030 * Panel isntance to identify which psr_state to use 2031 * Currently the support is only for 0 or 1 2032 */ 2033 uint8_t panel_inst; 2034 }; 2035 2036 /** 2037 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2038 */ 2039 struct dmub_rb_cmd_psr_set_level { 2040 /** 2041 * Command header. 2042 */ 2043 struct dmub_cmd_header header; 2044 /** 2045 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2046 */ 2047 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2048 }; 2049 2050 struct dmub_rb_cmd_psr_enable_data { 2051 /** 2052 * PSR control version. 2053 */ 2054 uint8_t cmd_version; 2055 /** 2056 * Panel Instance. 2057 * Panel isntance to identify which psr_state to use 2058 * Currently the support is only for 0 or 1 2059 */ 2060 uint8_t panel_inst; 2061 /** 2062 * Phy state to enter. 2063 * Values to use are defined in dmub_phy_fsm_state 2064 */ 2065 uint8_t phy_fsm_state; 2066 /** 2067 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2068 * Set this using enum phy_link_rate. 2069 * This does not support HDMI/DP2 for now. 2070 */ 2071 uint8_t phy_rate; 2072 }; 2073 2074 /** 2075 * Definition of a DMUB_CMD__PSR_ENABLE command. 2076 * PSR enable/disable is controlled using the sub_type. 2077 */ 2078 struct dmub_rb_cmd_psr_enable { 2079 /** 2080 * Command header. 2081 */ 2082 struct dmub_cmd_header header; 2083 2084 struct dmub_rb_cmd_psr_enable_data data; 2085 }; 2086 2087 /** 2088 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2089 */ 2090 struct dmub_cmd_psr_set_version_data { 2091 /** 2092 * PSR version that FW should implement. 2093 */ 2094 enum psr_version version; 2095 /** 2096 * PSR control version. 2097 */ 2098 uint8_t cmd_version; 2099 /** 2100 * Panel Instance. 2101 * Panel isntance to identify which psr_state to use 2102 * Currently the support is only for 0 or 1 2103 */ 2104 uint8_t panel_inst; 2105 /** 2106 * Explicit padding to 4 byte boundary. 2107 */ 2108 uint8_t pad[2]; 2109 }; 2110 2111 /** 2112 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2113 */ 2114 struct dmub_rb_cmd_psr_set_version { 2115 /** 2116 * Command header. 2117 */ 2118 struct dmub_cmd_header header; 2119 /** 2120 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2121 */ 2122 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2123 }; 2124 2125 struct dmub_cmd_psr_force_static_data { 2126 /** 2127 * PSR control version. 2128 */ 2129 uint8_t cmd_version; 2130 /** 2131 * Panel Instance. 2132 * Panel isntance to identify which psr_state to use 2133 * Currently the support is only for 0 or 1 2134 */ 2135 uint8_t panel_inst; 2136 /** 2137 * Explicit padding to 4 byte boundary. 2138 */ 2139 uint8_t pad[2]; 2140 }; 2141 2142 /** 2143 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2144 */ 2145 struct dmub_rb_cmd_psr_force_static { 2146 /** 2147 * Command header. 2148 */ 2149 struct dmub_cmd_header header; 2150 /** 2151 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2152 */ 2153 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2154 }; 2155 2156 /** 2157 * PSR SU debug flags. 2158 */ 2159 union dmub_psr_su_debug_flags { 2160 /** 2161 * PSR SU debug flags. 2162 */ 2163 struct { 2164 /** 2165 * Update dirty rect in SW only. 2166 */ 2167 uint8_t update_dirty_rect_only : 1; 2168 /** 2169 * Reset the cursor/plane state before processing the call. 2170 */ 2171 uint8_t reset_state : 1; 2172 } bitfields; 2173 2174 /** 2175 * Union for debug flags. 2176 */ 2177 uint32_t u32All; 2178 }; 2179 2180 /** 2181 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2182 * This triggers a selective update for PSR SU. 2183 */ 2184 struct dmub_cmd_update_dirty_rect_data { 2185 /** 2186 * Dirty rects from OS. 2187 */ 2188 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2189 /** 2190 * PSR SU debug flags. 2191 */ 2192 union dmub_psr_su_debug_flags debug_flags; 2193 /** 2194 * OTG HW instance. 2195 */ 2196 uint8_t pipe_idx; 2197 /** 2198 * Number of dirty rects. 2199 */ 2200 uint8_t dirty_rect_count; 2201 /** 2202 * PSR control version. 2203 */ 2204 uint8_t cmd_version; 2205 /** 2206 * Panel Instance. 2207 * Panel isntance to identify which psr_state to use 2208 * Currently the support is only for 0 or 1 2209 */ 2210 uint8_t panel_inst; 2211 }; 2212 2213 /** 2214 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2215 */ 2216 struct dmub_rb_cmd_update_dirty_rect { 2217 /** 2218 * Command header. 2219 */ 2220 struct dmub_cmd_header header; 2221 /** 2222 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2223 */ 2224 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2225 }; 2226 2227 /** 2228 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2229 */ 2230 union dmub_reg_cursor_control_cfg { 2231 struct { 2232 uint32_t cur_enable: 1; 2233 uint32_t reser0: 3; 2234 uint32_t cur_2x_magnify: 1; 2235 uint32_t reser1: 3; 2236 uint32_t mode: 3; 2237 uint32_t reser2: 5; 2238 uint32_t pitch: 2; 2239 uint32_t reser3: 6; 2240 uint32_t line_per_chunk: 5; 2241 uint32_t reser4: 3; 2242 } bits; 2243 uint32_t raw; 2244 }; 2245 struct dmub_cursor_position_cache_hubp { 2246 union dmub_reg_cursor_control_cfg cur_ctl; 2247 union dmub_reg_position_cfg { 2248 struct { 2249 uint32_t cur_x_pos: 16; 2250 uint32_t cur_y_pos: 16; 2251 } bits; 2252 uint32_t raw; 2253 } position; 2254 union dmub_reg_hot_spot_cfg { 2255 struct { 2256 uint32_t hot_x: 16; 2257 uint32_t hot_y: 16; 2258 } bits; 2259 uint32_t raw; 2260 } hot_spot; 2261 union dmub_reg_dst_offset_cfg { 2262 struct { 2263 uint32_t dst_x_offset: 13; 2264 uint32_t reserved: 19; 2265 } bits; 2266 uint32_t raw; 2267 } dst_offset; 2268 }; 2269 2270 union dmub_reg_cur0_control_cfg { 2271 struct { 2272 uint32_t cur0_enable: 1; 2273 uint32_t expansion_mode: 1; 2274 uint32_t reser0: 1; 2275 uint32_t cur0_rom_en: 1; 2276 uint32_t mode: 3; 2277 uint32_t reserved: 25; 2278 } bits; 2279 uint32_t raw; 2280 }; 2281 struct dmub_cursor_position_cache_dpp { 2282 union dmub_reg_cur0_control_cfg cur0_ctl; 2283 }; 2284 struct dmub_cursor_position_cfg { 2285 struct dmub_cursor_position_cache_hubp pHubp; 2286 struct dmub_cursor_position_cache_dpp pDpp; 2287 uint8_t pipe_idx; 2288 /* 2289 * Padding is required. To be 4 Bytes Aligned. 2290 */ 2291 uint8_t padding[3]; 2292 }; 2293 2294 struct dmub_cursor_attribute_cache_hubp { 2295 uint32_t SURFACE_ADDR_HIGH; 2296 uint32_t SURFACE_ADDR; 2297 union dmub_reg_cursor_control_cfg cur_ctl; 2298 union dmub_reg_cursor_size_cfg { 2299 struct { 2300 uint32_t width: 16; 2301 uint32_t height: 16; 2302 } bits; 2303 uint32_t raw; 2304 } size; 2305 union dmub_reg_cursor_settings_cfg { 2306 struct { 2307 uint32_t dst_y_offset: 8; 2308 uint32_t chunk_hdl_adjust: 2; 2309 uint32_t reserved: 22; 2310 } bits; 2311 uint32_t raw; 2312 } settings; 2313 }; 2314 struct dmub_cursor_attribute_cache_dpp { 2315 union dmub_reg_cur0_control_cfg cur0_ctl; 2316 }; 2317 struct dmub_cursor_attributes_cfg { 2318 struct dmub_cursor_attribute_cache_hubp aHubp; 2319 struct dmub_cursor_attribute_cache_dpp aDpp; 2320 }; 2321 2322 struct dmub_cmd_update_cursor_payload0 { 2323 /** 2324 * Cursor dirty rects. 2325 */ 2326 struct dmub_rect cursor_rect; 2327 /** 2328 * PSR SU debug flags. 2329 */ 2330 union dmub_psr_su_debug_flags debug_flags; 2331 /** 2332 * Cursor enable/disable. 2333 */ 2334 uint8_t enable; 2335 /** 2336 * OTG HW instance. 2337 */ 2338 uint8_t pipe_idx; 2339 /** 2340 * PSR control version. 2341 */ 2342 uint8_t cmd_version; 2343 /** 2344 * Panel Instance. 2345 * Panel isntance to identify which psr_state to use 2346 * Currently the support is only for 0 or 1 2347 */ 2348 uint8_t panel_inst; 2349 /** 2350 * Cursor Position Register. 2351 * Registers contains Hubp & Dpp modules 2352 */ 2353 struct dmub_cursor_position_cfg position_cfg; 2354 }; 2355 2356 struct dmub_cmd_update_cursor_payload1 { 2357 struct dmub_cursor_attributes_cfg attribute_cfg; 2358 }; 2359 2360 union dmub_cmd_update_cursor_info_data { 2361 struct dmub_cmd_update_cursor_payload0 payload0; 2362 struct dmub_cmd_update_cursor_payload1 payload1; 2363 }; 2364 /** 2365 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2366 */ 2367 struct dmub_rb_cmd_update_cursor_info { 2368 /** 2369 * Command header. 2370 */ 2371 struct dmub_cmd_header header; 2372 /** 2373 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2374 */ 2375 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2376 }; 2377 2378 /** 2379 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2380 */ 2381 struct dmub_cmd_psr_set_vtotal_data { 2382 /** 2383 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2384 */ 2385 uint16_t psr_vtotal_idle; 2386 /** 2387 * PSR control version. 2388 */ 2389 uint8_t cmd_version; 2390 /** 2391 * Panel Instance. 2392 * Panel isntance to identify which psr_state to use 2393 * Currently the support is only for 0 or 1 2394 */ 2395 uint8_t panel_inst; 2396 /* 2397 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2398 */ 2399 uint16_t psr_vtotal_su; 2400 /** 2401 * Explicit padding to 4 byte boundary. 2402 */ 2403 uint8_t pad2[2]; 2404 }; 2405 2406 /** 2407 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2408 */ 2409 struct dmub_rb_cmd_psr_set_vtotal { 2410 /** 2411 * Command header. 2412 */ 2413 struct dmub_cmd_header header; 2414 /** 2415 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2416 */ 2417 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2418 }; 2419 2420 /** 2421 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2422 */ 2423 struct dmub_cmd_psr_set_power_opt_data { 2424 /** 2425 * PSR control version. 2426 */ 2427 uint8_t cmd_version; 2428 /** 2429 * Panel Instance. 2430 * Panel isntance to identify which psr_state to use 2431 * Currently the support is only for 0 or 1 2432 */ 2433 uint8_t panel_inst; 2434 /** 2435 * Explicit padding to 4 byte boundary. 2436 */ 2437 uint8_t pad[2]; 2438 /** 2439 * PSR power option 2440 */ 2441 uint32_t power_opt; 2442 }; 2443 2444 /** 2445 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2446 */ 2447 struct dmub_rb_cmd_psr_set_power_opt { 2448 /** 2449 * Command header. 2450 */ 2451 struct dmub_cmd_header header; 2452 /** 2453 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2454 */ 2455 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2456 }; 2457 2458 /** 2459 * Set of HW components that can be locked. 2460 * 2461 * Note: If updating with more HW components, fields 2462 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2463 */ 2464 union dmub_hw_lock_flags { 2465 /** 2466 * Set of HW components that can be locked. 2467 */ 2468 struct { 2469 /** 2470 * Lock/unlock OTG master update lock. 2471 */ 2472 uint8_t lock_pipe : 1; 2473 /** 2474 * Lock/unlock cursor. 2475 */ 2476 uint8_t lock_cursor : 1; 2477 /** 2478 * Lock/unlock global update lock. 2479 */ 2480 uint8_t lock_dig : 1; 2481 /** 2482 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2483 */ 2484 uint8_t triple_buffer_lock : 1; 2485 } bits; 2486 2487 /** 2488 * Union for HW Lock flags. 2489 */ 2490 uint8_t u8All; 2491 }; 2492 2493 /** 2494 * Instances of HW to be locked. 2495 * 2496 * Note: If updating with more HW components, fields 2497 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2498 */ 2499 struct dmub_hw_lock_inst_flags { 2500 /** 2501 * OTG HW instance for OTG master update lock. 2502 */ 2503 uint8_t otg_inst; 2504 /** 2505 * OPP instance for cursor lock. 2506 */ 2507 uint8_t opp_inst; 2508 /** 2509 * OTG HW instance for global update lock. 2510 * TODO: Remove, and re-use otg_inst. 2511 */ 2512 uint8_t dig_inst; 2513 /** 2514 * Explicit pad to 4 byte boundary. 2515 */ 2516 uint8_t pad; 2517 }; 2518 2519 /** 2520 * Clients that can acquire the HW Lock Manager. 2521 * 2522 * Note: If updating with more clients, fields in 2523 * dmub_inbox0_cmd_lock_hw must be updated to match. 2524 */ 2525 enum hw_lock_client { 2526 /** 2527 * Driver is the client of HW Lock Manager. 2528 */ 2529 HW_LOCK_CLIENT_DRIVER = 0, 2530 /** 2531 * PSR SU is the client of HW Lock Manager. 2532 */ 2533 HW_LOCK_CLIENT_PSR_SU = 1, 2534 /** 2535 * Invalid client. 2536 */ 2537 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2538 }; 2539 2540 /** 2541 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2542 */ 2543 struct dmub_cmd_lock_hw_data { 2544 /** 2545 * Specifies the client accessing HW Lock Manager. 2546 */ 2547 enum hw_lock_client client; 2548 /** 2549 * HW instances to be locked. 2550 */ 2551 struct dmub_hw_lock_inst_flags inst_flags; 2552 /** 2553 * Which components to be locked. 2554 */ 2555 union dmub_hw_lock_flags hw_locks; 2556 /** 2557 * Specifies lock/unlock. 2558 */ 2559 uint8_t lock; 2560 /** 2561 * HW can be unlocked separately from releasing the HW Lock Mgr. 2562 * This flag is set if the client wishes to release the object. 2563 */ 2564 uint8_t should_release; 2565 /** 2566 * Explicit padding to 4 byte boundary. 2567 */ 2568 uint8_t pad; 2569 }; 2570 2571 /** 2572 * Definition of a DMUB_CMD__HW_LOCK command. 2573 * Command is used by driver and FW. 2574 */ 2575 struct dmub_rb_cmd_lock_hw { 2576 /** 2577 * Command header. 2578 */ 2579 struct dmub_cmd_header header; 2580 /** 2581 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2582 */ 2583 struct dmub_cmd_lock_hw_data lock_hw_data; 2584 }; 2585 2586 /** 2587 * ABM command sub-types. 2588 */ 2589 enum dmub_cmd_abm_type { 2590 /** 2591 * Initialize parameters for ABM algorithm. 2592 * Data is passed through an indirect buffer. 2593 */ 2594 DMUB_CMD__ABM_INIT_CONFIG = 0, 2595 /** 2596 * Set OTG and panel HW instance. 2597 */ 2598 DMUB_CMD__ABM_SET_PIPE = 1, 2599 /** 2600 * Set user requested backklight level. 2601 */ 2602 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2603 /** 2604 * Set ABM operating/aggression level. 2605 */ 2606 DMUB_CMD__ABM_SET_LEVEL = 3, 2607 /** 2608 * Set ambient light level. 2609 */ 2610 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2611 /** 2612 * Enable/disable fractional duty cycle for backlight PWM. 2613 */ 2614 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2615 2616 /** 2617 * unregister vertical interrupt after steady state is reached 2618 */ 2619 DMUB_CMD__ABM_PAUSE = 6, 2620 }; 2621 2622 /** 2623 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2624 * Requirements: 2625 * - Padded explicitly to 32-bit boundary. 2626 * - Must ensure this structure matches the one on driver-side, 2627 * otherwise it won't be aligned. 2628 */ 2629 struct abm_config_table { 2630 /** 2631 * Gamma curve thresholds, used for crgb conversion. 2632 */ 2633 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2634 /** 2635 * Gamma curve offsets, used for crgb conversion. 2636 */ 2637 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2638 /** 2639 * Gamma curve slopes, used for crgb conversion. 2640 */ 2641 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2642 /** 2643 * Custom backlight curve thresholds. 2644 */ 2645 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2646 /** 2647 * Custom backlight curve offsets. 2648 */ 2649 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2650 /** 2651 * Ambient light thresholds. 2652 */ 2653 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2654 /** 2655 * Minimum programmable backlight. 2656 */ 2657 uint16_t min_abm_backlight; // 122B 2658 /** 2659 * Minimum reduction values. 2660 */ 2661 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2662 /** 2663 * Maximum reduction values. 2664 */ 2665 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2666 /** 2667 * Bright positive gain. 2668 */ 2669 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2670 /** 2671 * Dark negative gain. 2672 */ 2673 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2674 /** 2675 * Hybrid factor. 2676 */ 2677 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2678 /** 2679 * Contrast factor. 2680 */ 2681 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2682 /** 2683 * Deviation gain. 2684 */ 2685 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2686 /** 2687 * Minimum knee. 2688 */ 2689 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2690 /** 2691 * Maximum knee. 2692 */ 2693 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2694 /** 2695 * Unused. 2696 */ 2697 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2698 /** 2699 * Explicit padding to 4 byte boundary. 2700 */ 2701 uint8_t pad3[3]; // 229B 2702 /** 2703 * Backlight ramp reduction. 2704 */ 2705 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2706 /** 2707 * Backlight ramp start. 2708 */ 2709 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2710 }; 2711 2712 /** 2713 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2714 */ 2715 struct dmub_cmd_abm_set_pipe_data { 2716 /** 2717 * OTG HW instance. 2718 */ 2719 uint8_t otg_inst; 2720 2721 /** 2722 * Panel Control HW instance. 2723 */ 2724 uint8_t panel_inst; 2725 2726 /** 2727 * Controls how ABM will interpret a set pipe or set level command. 2728 */ 2729 uint8_t set_pipe_option; 2730 2731 /** 2732 * Unused. 2733 * TODO: Remove. 2734 */ 2735 uint8_t ramping_boundary; 2736 }; 2737 2738 /** 2739 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2740 */ 2741 struct dmub_rb_cmd_abm_set_pipe { 2742 /** 2743 * Command header. 2744 */ 2745 struct dmub_cmd_header header; 2746 2747 /** 2748 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2749 */ 2750 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2751 }; 2752 2753 /** 2754 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2755 */ 2756 struct dmub_cmd_abm_set_backlight_data { 2757 /** 2758 * Number of frames to ramp to backlight user level. 2759 */ 2760 uint32_t frame_ramp; 2761 2762 /** 2763 * Requested backlight level from user. 2764 */ 2765 uint32_t backlight_user_level; 2766 2767 /** 2768 * ABM control version. 2769 */ 2770 uint8_t version; 2771 2772 /** 2773 * Panel Control HW instance mask. 2774 * Bit 0 is Panel Control HW instance 0. 2775 * Bit 1 is Panel Control HW instance 1. 2776 */ 2777 uint8_t panel_mask; 2778 2779 /** 2780 * Explicit padding to 4 byte boundary. 2781 */ 2782 uint8_t pad[2]; 2783 }; 2784 2785 /** 2786 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2787 */ 2788 struct dmub_rb_cmd_abm_set_backlight { 2789 /** 2790 * Command header. 2791 */ 2792 struct dmub_cmd_header header; 2793 2794 /** 2795 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2796 */ 2797 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2798 }; 2799 2800 /** 2801 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2802 */ 2803 struct dmub_cmd_abm_set_level_data { 2804 /** 2805 * Set current ABM operating/aggression level. 2806 */ 2807 uint32_t level; 2808 2809 /** 2810 * ABM control version. 2811 */ 2812 uint8_t version; 2813 2814 /** 2815 * Panel Control HW instance mask. 2816 * Bit 0 is Panel Control HW instance 0. 2817 * Bit 1 is Panel Control HW instance 1. 2818 */ 2819 uint8_t panel_mask; 2820 2821 /** 2822 * Explicit padding to 4 byte boundary. 2823 */ 2824 uint8_t pad[2]; 2825 }; 2826 2827 /** 2828 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2829 */ 2830 struct dmub_rb_cmd_abm_set_level { 2831 /** 2832 * Command header. 2833 */ 2834 struct dmub_cmd_header header; 2835 2836 /** 2837 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2838 */ 2839 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2840 }; 2841 2842 /** 2843 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2844 */ 2845 struct dmub_cmd_abm_set_ambient_level_data { 2846 /** 2847 * Ambient light sensor reading from OS. 2848 */ 2849 uint32_t ambient_lux; 2850 2851 /** 2852 * ABM control version. 2853 */ 2854 uint8_t version; 2855 2856 /** 2857 * Panel Control HW instance mask. 2858 * Bit 0 is Panel Control HW instance 0. 2859 * Bit 1 is Panel Control HW instance 1. 2860 */ 2861 uint8_t panel_mask; 2862 2863 /** 2864 * Explicit padding to 4 byte boundary. 2865 */ 2866 uint8_t pad[2]; 2867 }; 2868 2869 /** 2870 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2871 */ 2872 struct dmub_rb_cmd_abm_set_ambient_level { 2873 /** 2874 * Command header. 2875 */ 2876 struct dmub_cmd_header header; 2877 2878 /** 2879 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2880 */ 2881 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2882 }; 2883 2884 /** 2885 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2886 */ 2887 struct dmub_cmd_abm_set_pwm_frac_data { 2888 /** 2889 * Enable/disable fractional duty cycle for backlight PWM. 2890 * TODO: Convert to uint8_t. 2891 */ 2892 uint32_t fractional_pwm; 2893 2894 /** 2895 * ABM control version. 2896 */ 2897 uint8_t version; 2898 2899 /** 2900 * Panel Control HW instance mask. 2901 * Bit 0 is Panel Control HW instance 0. 2902 * Bit 1 is Panel Control HW instance 1. 2903 */ 2904 uint8_t panel_mask; 2905 2906 /** 2907 * Explicit padding to 4 byte boundary. 2908 */ 2909 uint8_t pad[2]; 2910 }; 2911 2912 /** 2913 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2914 */ 2915 struct dmub_rb_cmd_abm_set_pwm_frac { 2916 /** 2917 * Command header. 2918 */ 2919 struct dmub_cmd_header header; 2920 2921 /** 2922 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2923 */ 2924 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2925 }; 2926 2927 /** 2928 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2929 */ 2930 struct dmub_cmd_abm_init_config_data { 2931 /** 2932 * Location of indirect buffer used to pass init data to ABM. 2933 */ 2934 union dmub_addr src; 2935 2936 /** 2937 * Indirect buffer length. 2938 */ 2939 uint16_t bytes; 2940 2941 2942 /** 2943 * ABM control version. 2944 */ 2945 uint8_t version; 2946 2947 /** 2948 * Panel Control HW instance mask. 2949 * Bit 0 is Panel Control HW instance 0. 2950 * Bit 1 is Panel Control HW instance 1. 2951 */ 2952 uint8_t panel_mask; 2953 2954 /** 2955 * Explicit padding to 4 byte boundary. 2956 */ 2957 uint8_t pad[2]; 2958 }; 2959 2960 /** 2961 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2962 */ 2963 struct dmub_rb_cmd_abm_init_config { 2964 /** 2965 * Command header. 2966 */ 2967 struct dmub_cmd_header header; 2968 2969 /** 2970 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2971 */ 2972 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2973 }; 2974 2975 /** 2976 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2977 */ 2978 2979 struct dmub_cmd_abm_pause_data { 2980 2981 /** 2982 * Panel Control HW instance mask. 2983 * Bit 0 is Panel Control HW instance 0. 2984 * Bit 1 is Panel Control HW instance 1. 2985 */ 2986 uint8_t panel_mask; 2987 2988 /** 2989 * OTG hw instance 2990 */ 2991 uint8_t otg_inst; 2992 2993 /** 2994 * Enable or disable ABM pause 2995 */ 2996 uint8_t enable; 2997 2998 /** 2999 * Explicit padding to 4 byte boundary. 3000 */ 3001 uint8_t pad[1]; 3002 }; 3003 3004 /** 3005 * Definition of a DMUB_CMD__ABM_PAUSE command. 3006 */ 3007 struct dmub_rb_cmd_abm_pause { 3008 /** 3009 * Command header. 3010 */ 3011 struct dmub_cmd_header header; 3012 3013 /** 3014 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3015 */ 3016 struct dmub_cmd_abm_pause_data abm_pause_data; 3017 }; 3018 3019 /** 3020 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3021 */ 3022 struct dmub_cmd_query_feature_caps_data { 3023 /** 3024 * DMUB feature capabilities. 3025 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3026 */ 3027 struct dmub_feature_caps feature_caps; 3028 }; 3029 3030 /** 3031 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3032 */ 3033 struct dmub_rb_cmd_query_feature_caps { 3034 /** 3035 * Command header. 3036 */ 3037 struct dmub_cmd_header header; 3038 /** 3039 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3040 */ 3041 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 3042 }; 3043 3044 /** 3045 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3046 */ 3047 struct dmub_cmd_visual_confirm_color_data { 3048 /** 3049 * DMUB feature capabilities. 3050 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3051 */ 3052 struct dmub_visual_confirm_color visual_confirm_color; 3053 }; 3054 3055 /** 3056 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3057 */ 3058 struct dmub_rb_cmd_get_visual_confirm_color { 3059 /** 3060 * Command header. 3061 */ 3062 struct dmub_cmd_header header; 3063 /** 3064 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3065 */ 3066 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3067 }; 3068 3069 struct dmub_optc_state { 3070 uint32_t v_total_max; 3071 uint32_t v_total_min; 3072 uint32_t tg_inst; 3073 }; 3074 3075 struct dmub_rb_cmd_drr_update { 3076 struct dmub_cmd_header header; 3077 struct dmub_optc_state dmub_optc_state_req; 3078 }; 3079 3080 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 3081 uint32_t pix_clk_100hz; 3082 uint8_t max_ramp_step; 3083 uint8_t pipes; 3084 uint8_t min_refresh_in_hz; 3085 uint8_t padding[1]; 3086 }; 3087 3088 struct dmub_cmd_fw_assisted_mclk_switch_config { 3089 uint8_t fams_enabled; 3090 uint8_t visual_confirm_enabled; 3091 uint8_t padding[2]; 3092 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 3093 }; 3094 3095 struct dmub_rb_cmd_fw_assisted_mclk_switch { 3096 struct dmub_cmd_header header; 3097 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 3098 }; 3099 3100 /** 3101 * enum dmub_cmd_panel_cntl_type - Panel control command. 3102 */ 3103 enum dmub_cmd_panel_cntl_type { 3104 /** 3105 * Initializes embedded panel hardware blocks. 3106 */ 3107 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3108 /** 3109 * Queries backlight info for the embedded panel. 3110 */ 3111 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3112 }; 3113 3114 /** 3115 * struct dmub_cmd_panel_cntl_data - Panel control data. 3116 */ 3117 struct dmub_cmd_panel_cntl_data { 3118 uint32_t inst; /**< panel instance */ 3119 uint32_t current_backlight; /* in/out */ 3120 uint32_t bl_pwm_cntl; /* in/out */ 3121 uint32_t bl_pwm_period_cntl; /* in/out */ 3122 uint32_t bl_pwm_ref_div1; /* in/out */ 3123 uint8_t is_backlight_on : 1; /* in/out */ 3124 uint8_t is_powered_on : 1; /* in/out */ 3125 uint8_t padding[3]; 3126 uint32_t bl_pwm_ref_div2; /* in/out */ 3127 uint8_t reserved[4]; 3128 }; 3129 3130 /** 3131 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3132 */ 3133 struct dmub_rb_cmd_panel_cntl { 3134 struct dmub_cmd_header header; /**< header */ 3135 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3136 }; 3137 3138 /** 3139 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3140 */ 3141 struct dmub_cmd_lvtma_control_data { 3142 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3143 uint8_t bypass_panel_control_wait; 3144 uint8_t reserved_0[2]; /**< For future use */ 3145 uint8_t panel_inst; /**< LVTMA control instance */ 3146 uint8_t reserved_1[3]; /**< For future use */ 3147 }; 3148 3149 /** 3150 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3151 */ 3152 struct dmub_rb_cmd_lvtma_control { 3153 /** 3154 * Command header. 3155 */ 3156 struct dmub_cmd_header header; 3157 /** 3158 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3159 */ 3160 struct dmub_cmd_lvtma_control_data data; 3161 }; 3162 3163 /** 3164 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3165 */ 3166 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3167 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3168 uint8_t is_usb; /**< is phy is usb */ 3169 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3170 uint8_t is_dp4; /**< is dp in 4 lane */ 3171 }; 3172 3173 /** 3174 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3175 */ 3176 struct dmub_rb_cmd_transmitter_query_dp_alt { 3177 struct dmub_cmd_header header; /**< header */ 3178 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3179 }; 3180 3181 /** 3182 * Maximum number of bytes a chunk sent to DMUB for parsing 3183 */ 3184 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3185 3186 /** 3187 * Represent a chunk of CEA blocks sent to DMUB for parsing 3188 */ 3189 struct dmub_cmd_send_edid_cea { 3190 uint16_t offset; /**< offset into the CEA block */ 3191 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3192 uint16_t cea_total_length; /**< total length of the CEA block */ 3193 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3194 uint8_t pad[3]; /**< padding and for future expansion */ 3195 }; 3196 3197 /** 3198 * Result of VSDB parsing from CEA block 3199 */ 3200 struct dmub_cmd_edid_cea_amd_vsdb { 3201 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3202 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3203 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3204 uint16_t min_frame_rate; /**< Maximum frame rate */ 3205 uint16_t max_frame_rate; /**< Minimum frame rate */ 3206 }; 3207 3208 /** 3209 * Result of sending a CEA chunk 3210 */ 3211 struct dmub_cmd_edid_cea_ack { 3212 uint16_t offset; /**< offset of the chunk into the CEA block */ 3213 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3214 uint8_t pad; /**< padding and for future expansion */ 3215 }; 3216 3217 /** 3218 * Specify whether the result is an ACK/NACK or the parsing has finished 3219 */ 3220 enum dmub_cmd_edid_cea_reply_type { 3221 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3222 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3223 }; 3224 3225 /** 3226 * Definition of a DMUB_CMD__EDID_CEA command. 3227 */ 3228 struct dmub_rb_cmd_edid_cea { 3229 struct dmub_cmd_header header; /**< Command header */ 3230 union dmub_cmd_edid_cea_data { 3231 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3232 struct dmub_cmd_edid_cea_output { /**< output with results */ 3233 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3234 union { 3235 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3236 struct dmub_cmd_edid_cea_ack ack; 3237 }; 3238 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3239 } data; /**< Command data */ 3240 3241 }; 3242 3243 /** 3244 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3245 */ 3246 struct dmub_cmd_cable_id_input { 3247 uint8_t phy_inst; /**< phy inst for cable id data */ 3248 }; 3249 3250 /** 3251 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3252 */ 3253 struct dmub_cmd_cable_id_output { 3254 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3255 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3256 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3257 uint8_t RESERVED :2; /**< reserved means not defined */ 3258 }; 3259 3260 /** 3261 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3262 */ 3263 struct dmub_rb_cmd_get_usbc_cable_id { 3264 struct dmub_cmd_header header; /**< Command header */ 3265 /** 3266 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3267 */ 3268 union dmub_cmd_cable_id_data { 3269 struct dmub_cmd_cable_id_input input; /**< Input */ 3270 struct dmub_cmd_cable_id_output output; /**< Output */ 3271 uint8_t output_raw; /**< Raw data output */ 3272 } data; 3273 }; 3274 3275 /** 3276 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3277 */ 3278 enum dmub_cmd_secure_display_type { 3279 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3280 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3281 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3282 }; 3283 3284 /** 3285 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3286 */ 3287 struct dmub_rb_cmd_secure_display { 3288 struct dmub_cmd_header header; 3289 /** 3290 * Data passed from driver to dmub firmware. 3291 */ 3292 struct dmub_cmd_roi_info { 3293 uint16_t x_start; 3294 uint16_t x_end; 3295 uint16_t y_start; 3296 uint16_t y_end; 3297 uint8_t otg_id; 3298 uint8_t phy_id; 3299 } roi_info; 3300 }; 3301 3302 /** 3303 * union dmub_rb_cmd - DMUB inbox command. 3304 */ 3305 union dmub_rb_cmd { 3306 /** 3307 * Elements shared with all commands. 3308 */ 3309 struct dmub_rb_cmd_common cmd_common; 3310 /** 3311 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3312 */ 3313 struct dmub_rb_cmd_read_modify_write read_modify_write; 3314 /** 3315 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3316 */ 3317 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3318 /** 3319 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3320 */ 3321 struct dmub_rb_cmd_burst_write burst_write; 3322 /** 3323 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3324 */ 3325 struct dmub_rb_cmd_reg_wait reg_wait; 3326 /** 3327 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3328 */ 3329 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3330 /** 3331 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3332 */ 3333 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3334 /** 3335 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3336 */ 3337 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3338 /** 3339 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3340 */ 3341 struct dmub_rb_cmd_dpphy_init dpphy_init; 3342 /** 3343 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3344 */ 3345 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3346 /** 3347 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3348 */ 3349 struct dmub_rb_cmd_domain_control domain_control; 3350 /** 3351 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3352 */ 3353 struct dmub_rb_cmd_psr_set_version psr_set_version; 3354 /** 3355 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3356 */ 3357 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3358 /** 3359 * Definition of a DMUB_CMD__PSR_ENABLE command. 3360 */ 3361 struct dmub_rb_cmd_psr_enable psr_enable; 3362 /** 3363 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3364 */ 3365 struct dmub_rb_cmd_psr_set_level psr_set_level; 3366 /** 3367 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3368 */ 3369 struct dmub_rb_cmd_psr_force_static psr_force_static; 3370 /** 3371 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3372 */ 3373 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3374 /** 3375 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3376 */ 3377 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3378 /** 3379 * Definition of a DMUB_CMD__HW_LOCK command. 3380 * Command is used by driver and FW. 3381 */ 3382 struct dmub_rb_cmd_lock_hw lock_hw; 3383 /** 3384 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3385 */ 3386 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3387 /** 3388 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3389 */ 3390 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3391 /** 3392 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3393 */ 3394 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3395 /** 3396 * Definition of a DMUB_CMD__MALL command. 3397 */ 3398 struct dmub_rb_cmd_mall mall; 3399 /** 3400 * Definition of a DMUB_CMD__CAB command. 3401 */ 3402 struct dmub_rb_cmd_cab_for_ss cab; 3403 3404 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3405 3406 /** 3407 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3408 */ 3409 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3410 3411 /** 3412 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3413 */ 3414 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3415 3416 /** 3417 * Definition of DMUB_CMD__PANEL_CNTL commands. 3418 */ 3419 struct dmub_rb_cmd_panel_cntl panel_cntl; 3420 /** 3421 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3422 */ 3423 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3424 3425 /** 3426 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3427 */ 3428 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3429 3430 /** 3431 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3432 */ 3433 struct dmub_rb_cmd_abm_set_level abm_set_level; 3434 3435 /** 3436 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3437 */ 3438 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3439 3440 /** 3441 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3442 */ 3443 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3444 3445 /** 3446 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3447 */ 3448 struct dmub_rb_cmd_abm_init_config abm_init_config; 3449 3450 /** 3451 * Definition of a DMUB_CMD__ABM_PAUSE command. 3452 */ 3453 struct dmub_rb_cmd_abm_pause abm_pause; 3454 3455 /** 3456 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3457 */ 3458 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3459 3460 /** 3461 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3462 */ 3463 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3464 3465 /** 3466 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3467 */ 3468 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3469 3470 /** 3471 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3472 */ 3473 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3474 struct dmub_rb_cmd_drr_update drr_update; 3475 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3476 3477 /** 3478 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3479 */ 3480 struct dmub_rb_cmd_lvtma_control lvtma_control; 3481 /** 3482 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3483 */ 3484 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3485 /** 3486 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3487 */ 3488 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3489 /** 3490 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3491 */ 3492 struct dmub_rb_cmd_set_config_access set_config_access; 3493 /** 3494 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3495 */ 3496 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3497 /** 3498 * Definition of a DMUB_CMD__EDID_CEA command. 3499 */ 3500 struct dmub_rb_cmd_edid_cea edid_cea; 3501 /** 3502 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3503 */ 3504 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3505 3506 /** 3507 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3508 */ 3509 struct dmub_rb_cmd_query_hpd_state query_hpd; 3510 /** 3511 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3512 */ 3513 struct dmub_rb_cmd_secure_display secure_display; 3514 3515 /** 3516 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3517 */ 3518 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3519 }; 3520 3521 /** 3522 * union dmub_rb_out_cmd - Outbox command 3523 */ 3524 union dmub_rb_out_cmd { 3525 /** 3526 * Parameters common to every command. 3527 */ 3528 struct dmub_rb_cmd_common cmd_common; 3529 /** 3530 * AUX reply command. 3531 */ 3532 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3533 /** 3534 * HPD notify command. 3535 */ 3536 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3537 /** 3538 * SET_CONFIG reply command. 3539 */ 3540 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3541 /** 3542 * DPIA notification command. 3543 */ 3544 struct dmub_rb_cmd_dpia_notification dpia_notification; 3545 }; 3546 #pragma pack(pop) 3547 3548 3549 //============================================================================== 3550 //</DMUB_CMD>=================================================================== 3551 //============================================================================== 3552 //< DMUB_RB>==================================================================== 3553 //============================================================================== 3554 3555 #if defined(__cplusplus) 3556 extern "C" { 3557 #endif 3558 3559 /** 3560 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3561 */ 3562 struct dmub_rb_init_params { 3563 void *ctx; /**< Caller provided context pointer */ 3564 void *base_address; /**< CPU base address for ring's data */ 3565 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3566 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3567 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3568 }; 3569 3570 /** 3571 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3572 */ 3573 struct dmub_rb { 3574 void *base_address; /**< CPU address for the ring's data */ 3575 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3576 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3577 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3578 3579 void *ctx; /**< Caller provided context pointer */ 3580 void *dmub; /**< Pointer to the DMUB interface */ 3581 }; 3582 3583 /** 3584 * @brief Checks if the ringbuffer is empty. 3585 * 3586 * @param rb DMUB Ringbuffer 3587 * @return true if empty 3588 * @return false otherwise 3589 */ 3590 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3591 { 3592 return (rb->wrpt == rb->rptr); 3593 } 3594 3595 /** 3596 * @brief Checks if the ringbuffer is full 3597 * 3598 * @param rb DMUB Ringbuffer 3599 * @return true if full 3600 * @return false otherwise 3601 */ 3602 static inline bool dmub_rb_full(struct dmub_rb *rb) 3603 { 3604 uint32_t data_count; 3605 3606 if (rb->wrpt >= rb->rptr) 3607 data_count = rb->wrpt - rb->rptr; 3608 else 3609 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3610 3611 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3612 } 3613 3614 /** 3615 * @brief Pushes a command into the ringbuffer 3616 * 3617 * @param rb DMUB ringbuffer 3618 * @param cmd The command to push 3619 * @return true if the ringbuffer was not full 3620 * @return false otherwise 3621 */ 3622 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3623 const union dmub_rb_cmd *cmd) 3624 { 3625 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3626 const uint64_t *src = (const uint64_t *)cmd; 3627 uint8_t i; 3628 3629 if (dmub_rb_full(rb)) 3630 return false; 3631 3632 // copying data 3633 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3634 *dst++ = *src++; 3635 3636 rb->wrpt += DMUB_RB_CMD_SIZE; 3637 3638 if (rb->wrpt >= rb->capacity) 3639 rb->wrpt %= rb->capacity; 3640 3641 return true; 3642 } 3643 3644 /** 3645 * @brief Pushes a command into the DMUB outbox ringbuffer 3646 * 3647 * @param rb DMUB outbox ringbuffer 3648 * @param cmd Outbox command 3649 * @return true if not full 3650 * @return false otherwise 3651 */ 3652 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3653 const union dmub_rb_out_cmd *cmd) 3654 { 3655 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3656 const uint8_t *src = (const uint8_t *)cmd; 3657 3658 if (dmub_rb_full(rb)) 3659 return false; 3660 3661 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3662 3663 rb->wrpt += DMUB_RB_CMD_SIZE; 3664 3665 if (rb->wrpt >= rb->capacity) 3666 rb->wrpt %= rb->capacity; 3667 3668 return true; 3669 } 3670 3671 /** 3672 * @brief Returns the next unprocessed command in the ringbuffer. 3673 * 3674 * @param rb DMUB ringbuffer 3675 * @param cmd The command to return 3676 * @return true if not empty 3677 * @return false otherwise 3678 */ 3679 static inline bool dmub_rb_front(struct dmub_rb *rb, 3680 union dmub_rb_cmd **cmd) 3681 { 3682 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3683 3684 if (dmub_rb_empty(rb)) 3685 return false; 3686 3687 *cmd = (union dmub_rb_cmd *)rb_cmd; 3688 3689 return true; 3690 } 3691 3692 /** 3693 * @brief Determines the next ringbuffer offset. 3694 * 3695 * @param rb DMUB inbox ringbuffer 3696 * @param num_cmds Number of commands 3697 * @param next_rptr The next offset in the ringbuffer 3698 */ 3699 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3700 uint32_t num_cmds, 3701 uint32_t *next_rptr) 3702 { 3703 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3704 3705 if (*next_rptr >= rb->capacity) 3706 *next_rptr %= rb->capacity; 3707 } 3708 3709 /** 3710 * @brief Returns a pointer to a command in the inbox. 3711 * 3712 * @param rb DMUB inbox ringbuffer 3713 * @param cmd The inbox command to return 3714 * @param rptr The ringbuffer offset 3715 * @return true if not empty 3716 * @return false otherwise 3717 */ 3718 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3719 union dmub_rb_cmd **cmd, 3720 uint32_t rptr) 3721 { 3722 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3723 3724 if (dmub_rb_empty(rb)) 3725 return false; 3726 3727 *cmd = (union dmub_rb_cmd *)rb_cmd; 3728 3729 return true; 3730 } 3731 3732 /** 3733 * @brief Returns the next unprocessed command in the outbox. 3734 * 3735 * @param rb DMUB outbox ringbuffer 3736 * @param cmd The outbox command to return 3737 * @return true if not empty 3738 * @return false otherwise 3739 */ 3740 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3741 union dmub_rb_out_cmd *cmd) 3742 { 3743 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3744 uint64_t *dst = (uint64_t *)cmd; 3745 uint8_t i; 3746 3747 if (dmub_rb_empty(rb)) 3748 return false; 3749 3750 // copying data 3751 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3752 *dst++ = *src++; 3753 3754 return true; 3755 } 3756 3757 /** 3758 * @brief Removes the front entry in the ringbuffer. 3759 * 3760 * @param rb DMUB ringbuffer 3761 * @return true if the command was removed 3762 * @return false if there were no commands 3763 */ 3764 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3765 { 3766 if (dmub_rb_empty(rb)) 3767 return false; 3768 3769 rb->rptr += DMUB_RB_CMD_SIZE; 3770 3771 if (rb->rptr >= rb->capacity) 3772 rb->rptr %= rb->capacity; 3773 3774 return true; 3775 } 3776 3777 /** 3778 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3779 * 3780 * Avoids a race condition where DMCUB accesses memory while 3781 * there are still writes in flight to framebuffer. 3782 * 3783 * @param rb DMUB ringbuffer 3784 */ 3785 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3786 { 3787 uint32_t rptr = rb->rptr; 3788 uint32_t wptr = rb->wrpt; 3789 3790 while (rptr != wptr) { 3791 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3792 uint8_t i; 3793 3794 /* Don't remove this. 3795 * The contents need to actually be read from the ring buffer 3796 * for this function to be effective. 3797 */ 3798 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3799 (void)READ_ONCE(*data++); 3800 3801 rptr += DMUB_RB_CMD_SIZE; 3802 if (rptr >= rb->capacity) 3803 rptr %= rb->capacity; 3804 } 3805 } 3806 3807 /** 3808 * @brief Initializes a DMCUB ringbuffer 3809 * 3810 * @param rb DMUB ringbuffer 3811 * @param init_params initial configuration for the ringbuffer 3812 */ 3813 static inline void dmub_rb_init(struct dmub_rb *rb, 3814 struct dmub_rb_init_params *init_params) 3815 { 3816 rb->base_address = init_params->base_address; 3817 rb->capacity = init_params->capacity; 3818 rb->rptr = init_params->read_ptr; 3819 rb->wrpt = init_params->write_ptr; 3820 } 3821 3822 /** 3823 * @brief Copies output data from in/out commands into the given command. 3824 * 3825 * @param rb DMUB ringbuffer 3826 * @param cmd Command to copy data into 3827 */ 3828 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3829 union dmub_rb_cmd *cmd) 3830 { 3831 // Copy rb entry back into command 3832 uint8_t *rd_ptr = (rb->rptr == 0) ? 3833 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3834 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3835 3836 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3837 } 3838 3839 #if defined(__cplusplus) 3840 } 3841 #endif 3842 3843 //============================================================================== 3844 //</DMUB_RB>==================================================================== 3845 //============================================================================== 3846 3847 #endif /* _DMUB_CMD_H_ */ 3848