1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Maximum number of streams on any ASIC. */ 99 #define DMUB_MAX_STREAMS 6 100 101 /* Maximum number of planes on any ASIC. */ 102 #define DMUB_MAX_PLANES 6 103 104 /* Trace buffer offset for entry */ 105 #define TRACE_BUFFER_ENTRY_OFFSET 16 106 107 /** 108 * Maximum number of dirty rects supported by FW. 109 */ 110 #define DMUB_MAX_DIRTY_RECTS 3 111 112 /** 113 * 114 * PSR control version legacy 115 */ 116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117 /** 118 * PSR control version with multi edp support 119 */ 120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121 122 123 /** 124 * ABM control version legacy 125 */ 126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127 128 /** 129 * ABM control version with multi edp support 130 */ 131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132 133 /** 134 * Physical framebuffer address location, 64-bit. 135 */ 136 #ifndef PHYSICAL_ADDRESS_LOC 137 #define PHYSICAL_ADDRESS_LOC union large_integer 138 #endif 139 140 /** 141 * OS/FW agnostic memcpy 142 */ 143 #ifndef dmub_memcpy 144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 145 #endif 146 147 /** 148 * OS/FW agnostic memset 149 */ 150 #ifndef dmub_memset 151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 152 #endif 153 154 #if defined(__cplusplus) 155 extern "C" { 156 #endif 157 158 /** 159 * OS/FW agnostic udelay 160 */ 161 #ifndef dmub_udelay 162 #define dmub_udelay(microseconds) udelay(microseconds) 163 #endif 164 165 /** 166 * union dmub_addr - DMUB physical/virtual 64-bit address. 167 */ 168 union dmub_addr { 169 struct { 170 uint32_t low_part; /**< Lower 32 bits */ 171 uint32_t high_part; /**< Upper 32 bits */ 172 } u; /*<< Low/high bit access */ 173 uint64_t quad_part; /*<< 64 bit address */ 174 }; 175 176 /** 177 * Dirty rect definition. 178 */ 179 struct dmub_rect { 180 /** 181 * Dirty rect x offset. 182 */ 183 uint32_t x; 184 185 /** 186 * Dirty rect y offset. 187 */ 188 uint32_t y; 189 190 /** 191 * Dirty rect width. 192 */ 193 uint32_t width; 194 195 /** 196 * Dirty rect height. 197 */ 198 uint32_t height; 199 }; 200 201 /** 202 * Flags that can be set by driver to change some PSR behaviour. 203 */ 204 union dmub_psr_debug_flags { 205 /** 206 * Debug flags. 207 */ 208 struct { 209 /** 210 * Enable visual confirm in FW. 211 */ 212 uint32_t visual_confirm : 1; 213 214 /** 215 * Force all selective updates to bw full frame updates. 216 */ 217 uint32_t force_full_frame_update : 1; 218 219 /** 220 * Use HW Lock Mgr object to do HW locking in FW. 221 */ 222 uint32_t use_hw_lock_mgr : 1; 223 224 /** 225 * Use TPS3 signal when restore main link. 226 */ 227 uint32_t force_wakeup_by_tps3 : 1; 228 } bitfields; 229 230 /** 231 * Union for debug flags. 232 */ 233 uint32_t u32All; 234 }; 235 236 /** 237 * DMUB visual confirm color 238 */ 239 struct dmub_feature_caps { 240 /** 241 * Max PSR version supported by FW. 242 */ 243 uint8_t psr; 244 uint8_t fw_assisted_mclk_switch; 245 uint8_t reserved[6]; 246 }; 247 248 struct dmub_visual_confirm_color { 249 /** 250 * Maximum 10 bits color value 251 */ 252 uint16_t color_r_cr; 253 uint16_t color_g_y; 254 uint16_t color_b_cb; 255 uint16_t panel_inst; 256 }; 257 258 #if defined(__cplusplus) 259 } 260 #endif 261 262 //============================================================================== 263 //</DMUB_TYPES>================================================================= 264 //============================================================================== 265 //< DMUB_META>================================================================== 266 //============================================================================== 267 #pragma pack(push, 1) 268 269 /* Magic value for identifying dmub_fw_meta_info */ 270 #define DMUB_FW_META_MAGIC 0x444D5542 271 272 /* Offset from the end of the file to the dmub_fw_meta_info */ 273 #define DMUB_FW_META_OFFSET 0x24 274 275 /** 276 * struct dmub_fw_meta_info - metadata associated with fw binary 277 * 278 * NOTE: This should be considered a stable API. Fields should 279 * not be repurposed or reordered. New fields should be 280 * added instead to extend the structure. 281 * 282 * @magic_value: magic value identifying DMUB firmware meta info 283 * @fw_region_size: size of the firmware state region 284 * @trace_buffer_size: size of the tracebuffer region 285 * @fw_version: the firmware version information 286 * @dal_fw: 1 if the firmware is DAL 287 */ 288 struct dmub_fw_meta_info { 289 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 290 uint32_t fw_region_size; /**< size of the firmware state region */ 291 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 292 uint32_t fw_version; /**< the firmware version information */ 293 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 294 uint8_t reserved[3]; /**< padding bits */ 295 }; 296 297 /** 298 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 299 */ 300 union dmub_fw_meta { 301 struct dmub_fw_meta_info info; /**< metadata info */ 302 uint8_t reserved[64]; /**< padding bits */ 303 }; 304 305 #pragma pack(pop) 306 307 //============================================================================== 308 //< DMUB Trace Buffer>================================================================ 309 //============================================================================== 310 /** 311 * dmub_trace_code_t - firmware trace code, 32-bits 312 */ 313 typedef uint32_t dmub_trace_code_t; 314 315 /** 316 * struct dmcub_trace_buf_entry - Firmware trace entry 317 */ 318 struct dmcub_trace_buf_entry { 319 dmub_trace_code_t trace_code; /**< trace code for the event */ 320 uint32_t tick_count; /**< the tick count at time of trace */ 321 uint32_t param0; /**< trace defined parameter 0 */ 322 uint32_t param1; /**< trace defined parameter 1 */ 323 }; 324 325 //============================================================================== 326 //< DMUB_STATUS>================================================================ 327 //============================================================================== 328 329 /** 330 * DMCUB scratch registers can be used to determine firmware status. 331 * Current scratch register usage is as follows: 332 * 333 * SCRATCH0: FW Boot Status register 334 * SCRATCH5: LVTMA Status Register 335 * SCRATCH15: FW Boot Options register 336 */ 337 338 /** 339 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 340 */ 341 union dmub_fw_boot_status { 342 struct { 343 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 344 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 345 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 346 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 347 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 348 uint32_t reserved : 1; 349 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 350 351 } bits; /**< status bits */ 352 uint32_t all; /**< 32-bit access to status bits */ 353 }; 354 355 /** 356 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 357 */ 358 enum dmub_fw_boot_status_bit { 359 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 360 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 361 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 362 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 363 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 364 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 365 }; 366 367 /* Register bit definition for SCRATCH5 */ 368 union dmub_lvtma_status { 369 struct { 370 uint32_t psp_ok : 1; 371 uint32_t edp_on : 1; 372 uint32_t reserved : 30; 373 } bits; 374 uint32_t all; 375 }; 376 377 enum dmub_lvtma_status_bit { 378 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 379 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 380 }; 381 382 /** 383 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 384 */ 385 union dmub_fw_boot_options { 386 struct { 387 uint32_t pemu_env : 1; /**< 1 if PEMU */ 388 uint32_t fpga_env : 1; /**< 1 if FPGA */ 389 uint32_t optimized_init : 1; /**< 1 if optimized init */ 390 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 391 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 392 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 393 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 394 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 395 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 396 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 397 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 398 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 399 uint32_t power_optimization: 1; 400 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 401 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 402 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 403 404 uint32_t reserved : 17; /**< reserved */ 405 } bits; /**< boot bits */ 406 uint32_t all; /**< 32-bit access to bits */ 407 }; 408 409 enum dmub_fw_boot_options_bit { 410 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 411 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 412 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 413 }; 414 415 //============================================================================== 416 //</DMUB_STATUS>================================================================ 417 //============================================================================== 418 //< DMUB_VBIOS>================================================================= 419 //============================================================================== 420 421 /* 422 * enum dmub_cmd_vbios_type - VBIOS commands. 423 * 424 * Command IDs should be treated as stable ABI. 425 * Do not reuse or modify IDs. 426 */ 427 enum dmub_cmd_vbios_type { 428 /** 429 * Configures the DIG encoder. 430 */ 431 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 432 /** 433 * Controls the PHY. 434 */ 435 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 436 /** 437 * Sets the pixel clock/symbol clock. 438 */ 439 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 440 /** 441 * Enables or disables power gating. 442 */ 443 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 444 /** 445 * Controls embedded panels. 446 */ 447 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 448 /** 449 * Query DP alt status on a transmitter. 450 */ 451 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 452 }; 453 454 //============================================================================== 455 //</DMUB_VBIOS>================================================================= 456 //============================================================================== 457 //< DMUB_GPINT>================================================================= 458 //============================================================================== 459 460 /** 461 * The shifts and masks below may alternatively be used to format and read 462 * the command register bits. 463 */ 464 465 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 466 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 467 468 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 469 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 470 471 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 472 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 473 474 /** 475 * Command responses. 476 */ 477 478 /** 479 * Return response for DMUB_GPINT__STOP_FW command. 480 */ 481 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 482 483 /** 484 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 485 */ 486 union dmub_gpint_data_register { 487 struct { 488 uint32_t param : 16; /**< 16-bit parameter */ 489 uint32_t command_code : 12; /**< GPINT command */ 490 uint32_t status : 4; /**< Command status bit */ 491 } bits; /**< GPINT bit access */ 492 uint32_t all; /**< GPINT 32-bit access */ 493 }; 494 495 /* 496 * enum dmub_gpint_command - GPINT command to DMCUB FW 497 * 498 * Command IDs should be treated as stable ABI. 499 * Do not reuse or modify IDs. 500 */ 501 enum dmub_gpint_command { 502 /** 503 * Invalid command, ignored. 504 */ 505 DMUB_GPINT__INVALID_COMMAND = 0, 506 /** 507 * DESC: Queries the firmware version. 508 * RETURN: Firmware version. 509 */ 510 DMUB_GPINT__GET_FW_VERSION = 1, 511 /** 512 * DESC: Halts the firmware. 513 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 514 */ 515 DMUB_GPINT__STOP_FW = 2, 516 /** 517 * DESC: Get PSR state from FW. 518 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 519 */ 520 DMUB_GPINT__GET_PSR_STATE = 7, 521 /** 522 * DESC: Notifies DMCUB of the currently active streams. 523 * ARGS: Stream mask, 1 bit per active stream index. 524 */ 525 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 526 /** 527 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 528 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 529 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 530 * RETURN: PSR residency in milli-percent. 531 */ 532 DMUB_GPINT__PSR_RESIDENCY = 9, 533 534 /** 535 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 536 */ 537 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 538 }; 539 540 /** 541 * INBOX0 generic command definition 542 */ 543 union dmub_inbox0_cmd_common { 544 struct { 545 uint32_t command_code: 8; /**< INBOX0 command code */ 546 uint32_t param: 24; /**< 24-bit parameter */ 547 } bits; 548 uint32_t all; 549 }; 550 551 /** 552 * INBOX0 hw_lock command definition 553 */ 554 union dmub_inbox0_cmd_lock_hw { 555 struct { 556 uint32_t command_code: 8; 557 558 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 559 uint32_t hw_lock_client: 2; 560 561 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 562 uint32_t otg_inst: 3; 563 uint32_t opp_inst: 3; 564 uint32_t dig_inst: 3; 565 566 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 567 uint32_t lock_pipe: 1; 568 uint32_t lock_cursor: 1; 569 uint32_t lock_dig: 1; 570 uint32_t triple_buffer_lock: 1; 571 572 uint32_t lock: 1; /**< Lock */ 573 uint32_t should_release: 1; /**< Release */ 574 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 575 } bits; 576 uint32_t all; 577 }; 578 579 union dmub_inbox0_data_register { 580 union dmub_inbox0_cmd_common inbox0_cmd_common; 581 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 582 }; 583 584 enum dmub_inbox0_command { 585 /** 586 * DESC: Invalid command, ignored. 587 */ 588 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 589 /** 590 * DESC: Notification to acquire/release HW lock 591 * ARGS: 592 */ 593 DMUB_INBOX0_CMD__HW_LOCK = 1, 594 }; 595 //============================================================================== 596 //</DMUB_GPINT>================================================================= 597 //============================================================================== 598 //< DMUB_CMD>=================================================================== 599 //============================================================================== 600 601 /** 602 * Size in bytes of each DMUB command. 603 */ 604 #define DMUB_RB_CMD_SIZE 64 605 606 /** 607 * Maximum number of items in the DMUB ringbuffer. 608 */ 609 #define DMUB_RB_MAX_ENTRY 128 610 611 /** 612 * Ringbuffer size in bytes. 613 */ 614 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 615 616 /** 617 * REG_SET mask for reg offload. 618 */ 619 #define REG_SET_MASK 0xFFFF 620 621 /* 622 * enum dmub_cmd_type - DMUB inbox command. 623 * 624 * Command IDs should be treated as stable ABI. 625 * Do not reuse or modify IDs. 626 */ 627 enum dmub_cmd_type { 628 /** 629 * Invalid command. 630 */ 631 DMUB_CMD__NULL = 0, 632 /** 633 * Read modify write register sequence offload. 634 */ 635 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 636 /** 637 * Field update register sequence offload. 638 */ 639 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 640 /** 641 * Burst write sequence offload. 642 */ 643 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 644 /** 645 * Reg wait sequence offload. 646 */ 647 DMUB_CMD__REG_REG_WAIT = 4, 648 /** 649 * Workaround to avoid HUBP underflow during NV12 playback. 650 */ 651 DMUB_CMD__PLAT_54186_WA = 5, 652 /** 653 * Command type used to query FW feature caps. 654 */ 655 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 656 /** 657 * Command type used to get visual confirm color. 658 */ 659 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 660 /** 661 * Command type used for all PSR commands. 662 */ 663 DMUB_CMD__PSR = 64, 664 /** 665 * Command type used for all MALL commands. 666 */ 667 DMUB_CMD__MALL = 65, 668 /** 669 * Command type used for all ABM commands. 670 */ 671 DMUB_CMD__ABM = 66, 672 /** 673 * Command type used to update dirty rects in FW. 674 */ 675 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 676 /** 677 * Command type used to update cursor info in FW. 678 */ 679 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 680 /** 681 * Command type used for HW locking in FW. 682 */ 683 DMUB_CMD__HW_LOCK = 69, 684 /** 685 * Command type used to access DP AUX. 686 */ 687 DMUB_CMD__DP_AUX_ACCESS = 70, 688 /** 689 * Command type used for OUTBOX1 notification enable 690 */ 691 DMUB_CMD__OUTBOX1_ENABLE = 71, 692 693 /** 694 * Command type used for all idle optimization commands. 695 */ 696 DMUB_CMD__IDLE_OPT = 72, 697 /** 698 * Command type used for all clock manager commands. 699 */ 700 DMUB_CMD__CLK_MGR = 73, 701 /** 702 * Command type used for all panel control commands. 703 */ 704 DMUB_CMD__PANEL_CNTL = 74, 705 /** 706 * Command type used for <TODO:description> 707 */ 708 DMUB_CMD__CAB_FOR_SS = 75, 709 710 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 711 712 /** 713 * Command type used for interfacing with DPIA. 714 */ 715 DMUB_CMD__DPIA = 77, 716 /** 717 * Command type used for EDID CEA parsing 718 */ 719 DMUB_CMD__EDID_CEA = 79, 720 /** 721 * Command type used for getting usbc cable ID 722 */ 723 DMUB_CMD_GET_USBC_CABLE_ID = 81, 724 /** 725 * Command type used to query HPD state. 726 */ 727 DMUB_CMD__QUERY_HPD_STATE = 82, 728 /** 729 * Command type used for all VBIOS interface commands. 730 */ 731 DMUB_CMD__VBIOS = 128, 732 }; 733 734 /** 735 * enum dmub_out_cmd_type - DMUB outbox commands. 736 */ 737 enum dmub_out_cmd_type { 738 /** 739 * Invalid outbox command, ignored. 740 */ 741 DMUB_OUT_CMD__NULL = 0, 742 /** 743 * Command type used for DP AUX Reply data notification 744 */ 745 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 746 /** 747 * Command type used for DP HPD event notification 748 */ 749 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 750 /** 751 * Command type used for SET_CONFIG Reply notification 752 */ 753 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 754 }; 755 756 /* DMUB_CMD__DPIA command sub-types. */ 757 enum dmub_cmd_dpia_type { 758 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 759 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 760 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 761 }; 762 763 #pragma pack(push, 1) 764 765 /** 766 * struct dmub_cmd_header - Common command header fields. 767 */ 768 struct dmub_cmd_header { 769 unsigned int type : 8; /**< command type */ 770 unsigned int sub_type : 8; /**< command sub type */ 771 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 772 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 773 unsigned int reserved0 : 6; /**< reserved bits */ 774 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 775 unsigned int reserved1 : 2; /**< reserved bits */ 776 }; 777 778 /* 779 * struct dmub_cmd_read_modify_write_sequence - Read modify write 780 * 781 * 60 payload bytes can hold up to 5 sets of read modify writes, 782 * each take 3 dwords. 783 * 784 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 785 * 786 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 787 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 788 */ 789 struct dmub_cmd_read_modify_write_sequence { 790 uint32_t addr; /**< register address */ 791 uint32_t modify_mask; /**< modify mask */ 792 uint32_t modify_value; /**< modify value */ 793 }; 794 795 /** 796 * Maximum number of ops in read modify write sequence. 797 */ 798 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 799 800 /** 801 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 802 */ 803 struct dmub_rb_cmd_read_modify_write { 804 struct dmub_cmd_header header; /**< command header */ 805 /** 806 * Read modify write sequence. 807 */ 808 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 809 }; 810 811 /* 812 * Update a register with specified masks and values sequeunce 813 * 814 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 815 * 816 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 817 * 818 * 819 * USE CASE: 820 * 1. auto-increment register where additional read would update pointer and produce wrong result 821 * 2. toggle a bit without read in the middle 822 */ 823 824 struct dmub_cmd_reg_field_update_sequence { 825 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 826 uint32_t modify_value; /**< value to update with */ 827 }; 828 829 /** 830 * Maximum number of ops in field update sequence. 831 */ 832 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 833 834 /** 835 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 836 */ 837 struct dmub_rb_cmd_reg_field_update_sequence { 838 struct dmub_cmd_header header; /**< command header */ 839 uint32_t addr; /**< register address */ 840 /** 841 * Field update sequence. 842 */ 843 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 844 }; 845 846 847 /** 848 * Maximum number of burst write values. 849 */ 850 #define DMUB_BURST_WRITE_VALUES__MAX 14 851 852 /* 853 * struct dmub_rb_cmd_burst_write - Burst write 854 * 855 * support use case such as writing out LUTs. 856 * 857 * 60 payload bytes can hold up to 14 values to write to given address 858 * 859 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 860 */ 861 struct dmub_rb_cmd_burst_write { 862 struct dmub_cmd_header header; /**< command header */ 863 uint32_t addr; /**< register start address */ 864 /** 865 * Burst write register values. 866 */ 867 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 868 }; 869 870 /** 871 * struct dmub_rb_cmd_common - Common command header 872 */ 873 struct dmub_rb_cmd_common { 874 struct dmub_cmd_header header; /**< command header */ 875 /** 876 * Padding to RB_CMD_SIZE 877 */ 878 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 879 }; 880 881 /** 882 * struct dmub_cmd_reg_wait_data - Register wait data 883 */ 884 struct dmub_cmd_reg_wait_data { 885 uint32_t addr; /**< Register address */ 886 uint32_t mask; /**< Mask for register bits */ 887 uint32_t condition_field_value; /**< Value to wait for */ 888 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 889 }; 890 891 /** 892 * struct dmub_rb_cmd_reg_wait - Register wait command 893 */ 894 struct dmub_rb_cmd_reg_wait { 895 struct dmub_cmd_header header; /**< Command header */ 896 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 897 }; 898 899 /** 900 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 901 * 902 * Reprograms surface parameters to avoid underflow. 903 */ 904 struct dmub_cmd_PLAT_54186_wa { 905 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 906 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 907 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 908 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 909 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 910 struct { 911 uint8_t hubp_inst : 4; /**< HUBP instance */ 912 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 913 uint8_t immediate :1; /**< Immediate flip */ 914 uint8_t vmid : 4; /**< VMID */ 915 uint8_t grph_stereo : 1; /**< 1 if stereo */ 916 uint32_t reserved : 21; /**< Reserved */ 917 } flip_params; /**< Pageflip parameters */ 918 uint32_t reserved[9]; /**< Reserved bits */ 919 }; 920 921 /** 922 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 923 */ 924 struct dmub_rb_cmd_PLAT_54186_wa { 925 struct dmub_cmd_header header; /**< Command header */ 926 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 927 }; 928 929 /** 930 * struct dmub_rb_cmd_mall - MALL command data. 931 */ 932 struct dmub_rb_cmd_mall { 933 struct dmub_cmd_header header; /**< Common command header */ 934 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 935 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 936 uint32_t tmr_delay; /**< Timer delay */ 937 uint32_t tmr_scale; /**< Timer scale */ 938 uint16_t cursor_width; /**< Cursor width in pixels */ 939 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 940 uint16_t cursor_height; /**< Cursor height in pixels */ 941 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 942 uint8_t debug_bits; /**< Debug bits */ 943 944 uint8_t reserved1; /**< Reserved bits */ 945 uint8_t reserved2; /**< Reserved bits */ 946 }; 947 948 /** 949 * enum dmub_cmd_cab_type - TODO: 950 */ 951 enum dmub_cmd_cab_type { 952 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 953 DMUB_CMD__CAB_NO_DCN_REQ = 1, 954 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 955 }; 956 957 /** 958 * struct dmub_rb_cmd_cab_for_ss - TODO: 959 */ 960 struct dmub_rb_cmd_cab_for_ss { 961 struct dmub_cmd_header header; 962 uint8_t cab_alloc_ways; /* total number of ways */ 963 uint8_t debug_bits; /* debug bits */ 964 }; 965 966 enum mclk_switch_mode { 967 NONE = 0, 968 FPO = 1, 969 SUBVP = 2, 970 VBLANK = 3, 971 }; 972 973 /* Per pipe struct which stores the MCLK switch mode 974 * data to be sent to DMUB. 975 * Named "v2" for now -- once FPO and SUBVP are fully merged 976 * the type name can be updated 977 */ 978 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 979 union { 980 struct { 981 uint32_t pix_clk_100hz; 982 uint16_t main_vblank_start; 983 uint16_t main_vblank_end; 984 uint16_t mall_region_lines; 985 uint16_t prefetch_lines; 986 uint16_t prefetch_to_mall_start_lines; 987 uint16_t processing_delay_lines; 988 uint16_t htotal; // required to calculate line time for multi-display cases 989 uint16_t vtotal; 990 uint8_t main_pipe_index; 991 uint8_t phantom_pipe_index; 992 /* Since the microschedule is calculated in terms of OTG lines, 993 * include any scaling factors to make sure when we get accurate 994 * conversion when programming MALL_START_LINE (which is in terms 995 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 996 * is 1/2 (numerator = 1, denominator = 2). 997 */ 998 uint8_t scale_factor_numerator; 999 uint8_t scale_factor_denominator; 1000 uint8_t is_drr; 1001 uint8_t main_split_pipe_index; 1002 uint8_t phantom_split_pipe_index; 1003 } subvp_data; 1004 1005 struct { 1006 uint32_t pix_clk_100hz; 1007 uint16_t vblank_start; 1008 uint16_t vblank_end; 1009 uint16_t vstartup_start; 1010 uint16_t vtotal; 1011 uint16_t htotal; 1012 uint8_t vblank_pipe_index; 1013 uint8_t padding[2]; 1014 struct { 1015 uint8_t drr_in_use; 1016 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1017 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1018 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1019 uint8_t use_ramping; // Use ramping or not 1020 } drr_info; // DRR considered as part of SubVP + VBLANK case 1021 } vblank_data; 1022 } pipe_config; 1023 1024 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1025 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1026 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1027 */ 1028 uint8_t mode; // enum mclk_switch_mode 1029 }; 1030 1031 /** 1032 * Config data for Sub-VP and FPO 1033 * Named "v2" for now -- once FPO and SUBVP are fully merged 1034 * the type name can be updated 1035 */ 1036 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1037 uint16_t watermark_a_cache; 1038 uint8_t vertical_int_margin_us; 1039 uint8_t pstate_allow_width_us; 1040 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1041 }; 1042 1043 /** 1044 * DMUB rb command definition for Sub-VP and FPO 1045 * Named "v2" for now -- once FPO and SUBVP are fully merged 1046 * the type name can be updated 1047 */ 1048 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1049 struct dmub_cmd_header header; 1050 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1051 }; 1052 1053 /** 1054 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1055 */ 1056 enum dmub_cmd_idle_opt_type { 1057 /** 1058 * DCN hardware restore. 1059 */ 1060 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1061 1062 /** 1063 * DCN hardware save. 1064 */ 1065 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1066 }; 1067 1068 /** 1069 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1070 */ 1071 struct dmub_rb_cmd_idle_opt_dcn_restore { 1072 struct dmub_cmd_header header; /**< header */ 1073 }; 1074 1075 /** 1076 * struct dmub_clocks - Clock update notification. 1077 */ 1078 struct dmub_clocks { 1079 uint32_t dispclk_khz; /**< dispclk kHz */ 1080 uint32_t dppclk_khz; /**< dppclk kHz */ 1081 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1082 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1083 }; 1084 1085 /** 1086 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1087 */ 1088 enum dmub_cmd_clk_mgr_type { 1089 /** 1090 * Notify DMCUB of clock update. 1091 */ 1092 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1093 }; 1094 1095 /** 1096 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1097 */ 1098 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1099 struct dmub_cmd_header header; /**< header */ 1100 struct dmub_clocks clocks; /**< clock data */ 1101 }; 1102 1103 /** 1104 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1105 */ 1106 struct dmub_cmd_digx_encoder_control_data { 1107 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1108 }; 1109 1110 /** 1111 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1112 */ 1113 struct dmub_rb_cmd_digx_encoder_control { 1114 struct dmub_cmd_header header; /**< header */ 1115 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1116 }; 1117 1118 /** 1119 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1120 */ 1121 struct dmub_cmd_set_pixel_clock_data { 1122 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1123 }; 1124 1125 /** 1126 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1127 */ 1128 struct dmub_rb_cmd_set_pixel_clock { 1129 struct dmub_cmd_header header; /**< header */ 1130 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1131 }; 1132 1133 /** 1134 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1135 */ 1136 struct dmub_cmd_enable_disp_power_gating_data { 1137 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1138 }; 1139 1140 /** 1141 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1142 */ 1143 struct dmub_rb_cmd_enable_disp_power_gating { 1144 struct dmub_cmd_header header; /**< header */ 1145 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1146 }; 1147 1148 /** 1149 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1150 */ 1151 struct dmub_dig_transmitter_control_data_v1_7 { 1152 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1153 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1154 union { 1155 uint8_t digmode; /**< enum atom_encode_mode_def */ 1156 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1157 } mode_laneset; 1158 uint8_t lanenum; /**< Number of lanes */ 1159 union { 1160 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1161 } symclk_units; 1162 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1163 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1164 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1165 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1166 uint8_t reserved1; /**< For future use */ 1167 uint8_t reserved2[3]; /**< For future use */ 1168 uint32_t reserved3[11]; /**< For future use */ 1169 }; 1170 1171 /** 1172 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1173 */ 1174 union dmub_cmd_dig1_transmitter_control_data { 1175 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1176 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1177 }; 1178 1179 /** 1180 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1181 */ 1182 struct dmub_rb_cmd_dig1_transmitter_control { 1183 struct dmub_cmd_header header; /**< header */ 1184 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1185 }; 1186 1187 /** 1188 * DPIA tunnel command parameters. 1189 */ 1190 struct dmub_cmd_dig_dpia_control_data { 1191 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1192 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1193 union { 1194 uint8_t digmode; /** enum atom_encode_mode_def */ 1195 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1196 } mode_laneset; 1197 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1198 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1199 uint8_t hpdsel; /** =0: HPD is not assigned */ 1200 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1201 uint8_t dpia_id; /** Index of DPIA */ 1202 uint8_t fec_rdy : 1; 1203 uint8_t reserved : 7; 1204 uint32_t reserved1; 1205 }; 1206 1207 /** 1208 * DMUB command for DPIA tunnel control. 1209 */ 1210 struct dmub_rb_cmd_dig1_dpia_control { 1211 struct dmub_cmd_header header; 1212 struct dmub_cmd_dig_dpia_control_data dpia_control; 1213 }; 1214 1215 /** 1216 * SET_CONFIG Command Payload 1217 */ 1218 struct set_config_cmd_payload { 1219 uint8_t msg_type; /* set config message type */ 1220 uint8_t msg_data; /* set config message data */ 1221 }; 1222 1223 /** 1224 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1225 */ 1226 struct dmub_cmd_set_config_control_data { 1227 struct set_config_cmd_payload cmd_pkt; 1228 uint8_t instance; /* DPIA instance */ 1229 uint8_t immed_status; /* Immediate status returned in case of error */ 1230 }; 1231 1232 /** 1233 * DMUB command structure for SET_CONFIG command. 1234 */ 1235 struct dmub_rb_cmd_set_config_access { 1236 struct dmub_cmd_header header; /* header */ 1237 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1238 }; 1239 1240 /** 1241 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1242 */ 1243 struct dmub_cmd_mst_alloc_slots_control_data { 1244 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1245 uint8_t instance; /* DPIA instance */ 1246 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1247 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1248 }; 1249 1250 /** 1251 * DMUB command structure for SET_ command. 1252 */ 1253 struct dmub_rb_cmd_set_mst_alloc_slots { 1254 struct dmub_cmd_header header; /* header */ 1255 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1256 }; 1257 1258 /** 1259 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1260 */ 1261 struct dmub_rb_cmd_dpphy_init { 1262 struct dmub_cmd_header header; /**< header */ 1263 uint8_t reserved[60]; /**< reserved bits */ 1264 }; 1265 1266 /** 1267 * enum dp_aux_request_action - DP AUX request command listing. 1268 * 1269 * 4 AUX request command bits are shifted to high nibble. 1270 */ 1271 enum dp_aux_request_action { 1272 /** I2C-over-AUX write request */ 1273 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1274 /** I2C-over-AUX read request */ 1275 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1276 /** I2C-over-AUX write status request */ 1277 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1278 /** I2C-over-AUX write request with MOT=1 */ 1279 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1280 /** I2C-over-AUX read request with MOT=1 */ 1281 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1282 /** I2C-over-AUX write status request with MOT=1 */ 1283 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1284 /** Native AUX write request */ 1285 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1286 /** Native AUX read request */ 1287 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1288 }; 1289 1290 /** 1291 * enum aux_return_code_type - DP AUX process return code listing. 1292 */ 1293 enum aux_return_code_type { 1294 /** AUX process succeeded */ 1295 AUX_RET_SUCCESS = 0, 1296 /** AUX process failed with unknown reason */ 1297 AUX_RET_ERROR_UNKNOWN, 1298 /** AUX process completed with invalid reply */ 1299 AUX_RET_ERROR_INVALID_REPLY, 1300 /** AUX process timed out */ 1301 AUX_RET_ERROR_TIMEOUT, 1302 /** HPD was low during AUX process */ 1303 AUX_RET_ERROR_HPD_DISCON, 1304 /** Failed to acquire AUX engine */ 1305 AUX_RET_ERROR_ENGINE_ACQUIRE, 1306 /** AUX request not supported */ 1307 AUX_RET_ERROR_INVALID_OPERATION, 1308 /** AUX process not available */ 1309 AUX_RET_ERROR_PROTOCOL_ERROR, 1310 }; 1311 1312 /** 1313 * enum aux_channel_type - DP AUX channel type listing. 1314 */ 1315 enum aux_channel_type { 1316 /** AUX thru Legacy DP AUX */ 1317 AUX_CHANNEL_LEGACY_DDC, 1318 /** AUX thru DPIA DP tunneling */ 1319 AUX_CHANNEL_DPIA 1320 }; 1321 1322 /** 1323 * struct aux_transaction_parameters - DP AUX request transaction data 1324 */ 1325 struct aux_transaction_parameters { 1326 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1327 uint8_t action; /**< enum dp_aux_request_action */ 1328 uint8_t length; /**< DP AUX request data length */ 1329 uint8_t reserved; /**< For future use */ 1330 uint32_t address; /**< DP AUX address */ 1331 uint8_t data[16]; /**< DP AUX write data */ 1332 }; 1333 1334 /** 1335 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1336 */ 1337 struct dmub_cmd_dp_aux_control_data { 1338 uint8_t instance; /**< AUX instance or DPIA instance */ 1339 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1340 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1341 uint8_t reserved0; /**< For future use */ 1342 uint16_t timeout; /**< timeout time in us */ 1343 uint16_t reserved1; /**< For future use */ 1344 enum aux_channel_type type; /**< enum aux_channel_type */ 1345 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1346 }; 1347 1348 /** 1349 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1350 */ 1351 struct dmub_rb_cmd_dp_aux_access { 1352 /** 1353 * Command header. 1354 */ 1355 struct dmub_cmd_header header; 1356 /** 1357 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1358 */ 1359 struct dmub_cmd_dp_aux_control_data aux_control; 1360 }; 1361 1362 /** 1363 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1364 */ 1365 struct dmub_rb_cmd_outbox1_enable { 1366 /** 1367 * Command header. 1368 */ 1369 struct dmub_cmd_header header; 1370 /** 1371 * enable: 0x0 -> disable outbox1 notification (default value) 1372 * 0x1 -> enable outbox1 notification 1373 */ 1374 uint32_t enable; 1375 }; 1376 1377 /* DP AUX Reply command - OutBox Cmd */ 1378 /** 1379 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1380 */ 1381 struct aux_reply_data { 1382 /** 1383 * Aux cmd 1384 */ 1385 uint8_t command; 1386 /** 1387 * Aux reply data length (max: 16 bytes) 1388 */ 1389 uint8_t length; 1390 /** 1391 * Alignment only 1392 */ 1393 uint8_t pad[2]; 1394 /** 1395 * Aux reply data 1396 */ 1397 uint8_t data[16]; 1398 }; 1399 1400 /** 1401 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1402 */ 1403 struct aux_reply_control_data { 1404 /** 1405 * Reserved for future use 1406 */ 1407 uint32_t handle; 1408 /** 1409 * Aux Instance 1410 */ 1411 uint8_t instance; 1412 /** 1413 * Aux transaction result: definition in enum aux_return_code_type 1414 */ 1415 uint8_t result; 1416 /** 1417 * Alignment only 1418 */ 1419 uint16_t pad; 1420 }; 1421 1422 /** 1423 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1424 */ 1425 struct dmub_rb_cmd_dp_aux_reply { 1426 /** 1427 * Command header. 1428 */ 1429 struct dmub_cmd_header header; 1430 /** 1431 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1432 */ 1433 struct aux_reply_control_data control; 1434 /** 1435 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1436 */ 1437 struct aux_reply_data reply_data; 1438 }; 1439 1440 /* DP HPD Notify command - OutBox Cmd */ 1441 /** 1442 * DP HPD Type 1443 */ 1444 enum dp_hpd_type { 1445 /** 1446 * Normal DP HPD 1447 */ 1448 DP_HPD = 0, 1449 /** 1450 * DP HPD short pulse 1451 */ 1452 DP_IRQ 1453 }; 1454 1455 /** 1456 * DP HPD Status 1457 */ 1458 enum dp_hpd_status { 1459 /** 1460 * DP_HPD status low 1461 */ 1462 DP_HPD_UNPLUG = 0, 1463 /** 1464 * DP_HPD status high 1465 */ 1466 DP_HPD_PLUG 1467 }; 1468 1469 /** 1470 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1471 */ 1472 struct dp_hpd_data { 1473 /** 1474 * DP HPD instance 1475 */ 1476 uint8_t instance; 1477 /** 1478 * HPD type 1479 */ 1480 uint8_t hpd_type; 1481 /** 1482 * HPD status: only for type: DP_HPD to indicate status 1483 */ 1484 uint8_t hpd_status; 1485 /** 1486 * Alignment only 1487 */ 1488 uint8_t pad; 1489 }; 1490 1491 /** 1492 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1493 */ 1494 struct dmub_rb_cmd_dp_hpd_notify { 1495 /** 1496 * Command header. 1497 */ 1498 struct dmub_cmd_header header; 1499 /** 1500 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1501 */ 1502 struct dp_hpd_data hpd_data; 1503 }; 1504 1505 /** 1506 * Definition of a SET_CONFIG reply from DPOA. 1507 */ 1508 enum set_config_status { 1509 SET_CONFIG_PENDING = 0, 1510 SET_CONFIG_ACK_RECEIVED, 1511 SET_CONFIG_RX_TIMEOUT, 1512 SET_CONFIG_UNKNOWN_ERROR, 1513 }; 1514 1515 /** 1516 * Definition of a set_config reply 1517 */ 1518 struct set_config_reply_control_data { 1519 uint8_t instance; /* DPIA Instance */ 1520 uint8_t status; /* Set Config reply */ 1521 uint16_t pad; /* Alignment */ 1522 }; 1523 1524 /** 1525 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1526 */ 1527 struct dmub_rb_cmd_dp_set_config_reply { 1528 struct dmub_cmd_header header; 1529 struct set_config_reply_control_data set_config_reply_control; 1530 }; 1531 1532 /** 1533 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1534 */ 1535 struct dmub_cmd_hpd_state_query_data { 1536 uint8_t instance; /**< HPD instance or DPIA instance */ 1537 uint8_t result; /**< For returning HPD state */ 1538 uint16_t pad; /** < Alignment */ 1539 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1540 enum aux_return_code_type status; /**< for returning the status of command */ 1541 }; 1542 1543 /** 1544 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1545 */ 1546 struct dmub_rb_cmd_query_hpd_state { 1547 /** 1548 * Command header. 1549 */ 1550 struct dmub_cmd_header header; 1551 /** 1552 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1553 */ 1554 struct dmub_cmd_hpd_state_query_data data; 1555 }; 1556 1557 /* 1558 * Command IDs should be treated as stable ABI. 1559 * Do not reuse or modify IDs. 1560 */ 1561 1562 /** 1563 * PSR command sub-types. 1564 */ 1565 enum dmub_cmd_psr_type { 1566 /** 1567 * Set PSR version support. 1568 */ 1569 DMUB_CMD__PSR_SET_VERSION = 0, 1570 /** 1571 * Copy driver-calculated parameters to PSR state. 1572 */ 1573 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1574 /** 1575 * Enable PSR. 1576 */ 1577 DMUB_CMD__PSR_ENABLE = 2, 1578 1579 /** 1580 * Disable PSR. 1581 */ 1582 DMUB_CMD__PSR_DISABLE = 3, 1583 1584 /** 1585 * Set PSR level. 1586 * PSR level is a 16-bit value dicated by driver that 1587 * will enable/disable different functionality. 1588 */ 1589 DMUB_CMD__PSR_SET_LEVEL = 4, 1590 1591 /** 1592 * Forces PSR enabled until an explicit PSR disable call. 1593 */ 1594 DMUB_CMD__PSR_FORCE_STATIC = 5, 1595 /** 1596 * Set vtotal in psr active for FreeSync PSR. 1597 */ 1598 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1599 /** 1600 * Set PSR power option 1601 */ 1602 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1603 }; 1604 1605 enum dmub_cmd_fams_type { 1606 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1607 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1608 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1609 /** 1610 * For SubVP set manual trigger in FW because it 1611 * triggers DRR_UPDATE_PENDING which SubVP relies 1612 * on (for any SubVP cases that use a DRR display) 1613 */ 1614 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1615 }; 1616 1617 /** 1618 * PSR versions. 1619 */ 1620 enum psr_version { 1621 /** 1622 * PSR version 1. 1623 */ 1624 PSR_VERSION_1 = 0, 1625 /** 1626 * Freesync PSR SU. 1627 */ 1628 PSR_VERSION_SU_1 = 1, 1629 /** 1630 * PSR not supported. 1631 */ 1632 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1633 }; 1634 1635 /** 1636 * enum dmub_cmd_mall_type - MALL commands 1637 */ 1638 enum dmub_cmd_mall_type { 1639 /** 1640 * Allows display refresh from MALL. 1641 */ 1642 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1643 /** 1644 * Disallows display refresh from MALL. 1645 */ 1646 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1647 /** 1648 * Cursor copy for MALL. 1649 */ 1650 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1651 /** 1652 * Controls DF requests. 1653 */ 1654 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1655 }; 1656 1657 /** 1658 * PHY Link rate for DP. 1659 */ 1660 enum phy_link_rate { 1661 /** 1662 * not supported. 1663 */ 1664 PHY_RATE_UNKNOWN = 0, 1665 /** 1666 * Rate_1 (RBR) - 1.62 Gbps/Lane 1667 */ 1668 PHY_RATE_162 = 1, 1669 /** 1670 * Rate_2 - 2.16 Gbps/Lane 1671 */ 1672 PHY_RATE_216 = 2, 1673 /** 1674 * Rate_3 - 2.43 Gbps/Lane 1675 */ 1676 PHY_RATE_243 = 3, 1677 /** 1678 * Rate_4 (HBR) - 2.70 Gbps/Lane 1679 */ 1680 PHY_RATE_270 = 4, 1681 /** 1682 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1683 */ 1684 PHY_RATE_324 = 5, 1685 /** 1686 * Rate_6 - 4.32 Gbps/Lane 1687 */ 1688 PHY_RATE_432 = 6, 1689 /** 1690 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1691 */ 1692 PHY_RATE_540 = 7, 1693 /** 1694 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1695 */ 1696 PHY_RATE_810 = 8, 1697 /** 1698 * UHBR10 - 10.0 Gbps/Lane 1699 */ 1700 PHY_RATE_1000 = 9, 1701 /** 1702 * UHBR13.5 - 13.5 Gbps/Lane 1703 */ 1704 PHY_RATE_1350 = 10, 1705 /** 1706 * UHBR10 - 20.0 Gbps/Lane 1707 */ 1708 PHY_RATE_2000 = 11, 1709 }; 1710 1711 /** 1712 * enum dmub_phy_fsm_state - PHY FSM states. 1713 * PHY FSM state to transit to during PSR enable/disable. 1714 */ 1715 enum dmub_phy_fsm_state { 1716 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1717 DMUB_PHY_FSM_RESET, 1718 DMUB_PHY_FSM_RESET_RELEASED, 1719 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1720 DMUB_PHY_FSM_INITIALIZED, 1721 DMUB_PHY_FSM_CALIBRATED, 1722 DMUB_PHY_FSM_CALIBRATED_LP, 1723 DMUB_PHY_FSM_CALIBRATED_PG, 1724 DMUB_PHY_FSM_POWER_DOWN, 1725 DMUB_PHY_FSM_PLL_EN, 1726 DMUB_PHY_FSM_TX_EN, 1727 DMUB_PHY_FSM_FAST_LP, 1728 }; 1729 1730 /** 1731 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1732 */ 1733 struct dmub_cmd_psr_copy_settings_data { 1734 /** 1735 * Flags that can be set by driver to change some PSR behaviour. 1736 */ 1737 union dmub_psr_debug_flags debug; 1738 /** 1739 * 16-bit value dicated by driver that will enable/disable different functionality. 1740 */ 1741 uint16_t psr_level; 1742 /** 1743 * DPP HW instance. 1744 */ 1745 uint8_t dpp_inst; 1746 /** 1747 * MPCC HW instance. 1748 * Not used in dmub fw, 1749 * dmub fw will get active opp by reading odm registers. 1750 */ 1751 uint8_t mpcc_inst; 1752 /** 1753 * OPP HW instance. 1754 * Not used in dmub fw, 1755 * dmub fw will get active opp by reading odm registers. 1756 */ 1757 uint8_t opp_inst; 1758 /** 1759 * OTG HW instance. 1760 */ 1761 uint8_t otg_inst; 1762 /** 1763 * DIG FE HW instance. 1764 */ 1765 uint8_t digfe_inst; 1766 /** 1767 * DIG BE HW instance. 1768 */ 1769 uint8_t digbe_inst; 1770 /** 1771 * DP PHY HW instance. 1772 */ 1773 uint8_t dpphy_inst; 1774 /** 1775 * AUX HW instance. 1776 */ 1777 uint8_t aux_inst; 1778 /** 1779 * Determines if SMU optimzations are enabled/disabled. 1780 */ 1781 uint8_t smu_optimizations_en; 1782 /** 1783 * Unused. 1784 * TODO: Remove. 1785 */ 1786 uint8_t frame_delay; 1787 /** 1788 * If RFB setup time is greater than the total VBLANK time, 1789 * it is not possible for the sink to capture the video frame 1790 * in the same frame the SDP is sent. In this case, 1791 * the frame capture indication bit should be set and an extra 1792 * static frame should be transmitted to the sink. 1793 */ 1794 uint8_t frame_cap_ind; 1795 /** 1796 * Granularity of Y offset supported by sink. 1797 */ 1798 uint8_t su_y_granularity; 1799 /** 1800 * Indicates whether sink should start capturing 1801 * immediately following active scan line, 1802 * or starting with the 2nd active scan line. 1803 */ 1804 uint8_t line_capture_indication; 1805 /** 1806 * Multi-display optimizations are implemented on certain ASICs. 1807 */ 1808 uint8_t multi_disp_optimizations_en; 1809 /** 1810 * The last possible line SDP may be transmitted without violating 1811 * the RFB setup time or entering the active video frame. 1812 */ 1813 uint16_t init_sdp_deadline; 1814 /** 1815 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1816 */ 1817 uint8_t rate_control_caps ; 1818 /* 1819 * Force PSRSU always doing full frame update 1820 */ 1821 uint8_t force_ffu_mode; 1822 /** 1823 * Length of each horizontal line in us. 1824 */ 1825 uint32_t line_time_in_us; 1826 /** 1827 * FEC enable status in driver 1828 */ 1829 uint8_t fec_enable_status; 1830 /** 1831 * FEC re-enable delay when PSR exit. 1832 * unit is 100us, range form 0~255(0xFF). 1833 */ 1834 uint8_t fec_enable_delay_in100us; 1835 /** 1836 * PSR control version. 1837 */ 1838 uint8_t cmd_version; 1839 /** 1840 * Panel Instance. 1841 * Panel isntance to identify which psr_state to use 1842 * Currently the support is only for 0 or 1 1843 */ 1844 uint8_t panel_inst; 1845 /* 1846 * DSC enable status in driver 1847 */ 1848 uint8_t dsc_enable_status; 1849 /* 1850 * Use FSM state for PSR power up/down 1851 */ 1852 uint8_t use_phy_fsm; 1853 /** 1854 * Explicit padding to 2 byte boundary. 1855 */ 1856 uint8_t pad3[2]; 1857 }; 1858 1859 /** 1860 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1861 */ 1862 struct dmub_rb_cmd_psr_copy_settings { 1863 /** 1864 * Command header. 1865 */ 1866 struct dmub_cmd_header header; 1867 /** 1868 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1869 */ 1870 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1871 }; 1872 1873 /** 1874 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1875 */ 1876 struct dmub_cmd_psr_set_level_data { 1877 /** 1878 * 16-bit value dicated by driver that will enable/disable different functionality. 1879 */ 1880 uint16_t psr_level; 1881 /** 1882 * PSR control version. 1883 */ 1884 uint8_t cmd_version; 1885 /** 1886 * Panel Instance. 1887 * Panel isntance to identify which psr_state to use 1888 * Currently the support is only for 0 or 1 1889 */ 1890 uint8_t panel_inst; 1891 }; 1892 1893 /** 1894 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1895 */ 1896 struct dmub_rb_cmd_psr_set_level { 1897 /** 1898 * Command header. 1899 */ 1900 struct dmub_cmd_header header; 1901 /** 1902 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1903 */ 1904 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1905 }; 1906 1907 struct dmub_rb_cmd_psr_enable_data { 1908 /** 1909 * PSR control version. 1910 */ 1911 uint8_t cmd_version; 1912 /** 1913 * Panel Instance. 1914 * Panel isntance to identify which psr_state to use 1915 * Currently the support is only for 0 or 1 1916 */ 1917 uint8_t panel_inst; 1918 /** 1919 * Phy state to enter. 1920 * Values to use are defined in dmub_phy_fsm_state 1921 */ 1922 uint8_t phy_fsm_state; 1923 /** 1924 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1925 * Set this using enum phy_link_rate. 1926 * This does not support HDMI/DP2 for now. 1927 */ 1928 uint8_t phy_rate; 1929 }; 1930 1931 /** 1932 * Definition of a DMUB_CMD__PSR_ENABLE command. 1933 * PSR enable/disable is controlled using the sub_type. 1934 */ 1935 struct dmub_rb_cmd_psr_enable { 1936 /** 1937 * Command header. 1938 */ 1939 struct dmub_cmd_header header; 1940 1941 struct dmub_rb_cmd_psr_enable_data data; 1942 }; 1943 1944 /** 1945 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1946 */ 1947 struct dmub_cmd_psr_set_version_data { 1948 /** 1949 * PSR version that FW should implement. 1950 */ 1951 enum psr_version version; 1952 /** 1953 * PSR control version. 1954 */ 1955 uint8_t cmd_version; 1956 /** 1957 * Panel Instance. 1958 * Panel isntance to identify which psr_state to use 1959 * Currently the support is only for 0 or 1 1960 */ 1961 uint8_t panel_inst; 1962 /** 1963 * Explicit padding to 4 byte boundary. 1964 */ 1965 uint8_t pad[2]; 1966 }; 1967 1968 /** 1969 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1970 */ 1971 struct dmub_rb_cmd_psr_set_version { 1972 /** 1973 * Command header. 1974 */ 1975 struct dmub_cmd_header header; 1976 /** 1977 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1978 */ 1979 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1980 }; 1981 1982 struct dmub_cmd_psr_force_static_data { 1983 /** 1984 * PSR control version. 1985 */ 1986 uint8_t cmd_version; 1987 /** 1988 * Panel Instance. 1989 * Panel isntance to identify which psr_state to use 1990 * Currently the support is only for 0 or 1 1991 */ 1992 uint8_t panel_inst; 1993 /** 1994 * Explicit padding to 4 byte boundary. 1995 */ 1996 uint8_t pad[2]; 1997 }; 1998 1999 /** 2000 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2001 */ 2002 struct dmub_rb_cmd_psr_force_static { 2003 /** 2004 * Command header. 2005 */ 2006 struct dmub_cmd_header header; 2007 /** 2008 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2009 */ 2010 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2011 }; 2012 2013 /** 2014 * PSR SU debug flags. 2015 */ 2016 union dmub_psr_su_debug_flags { 2017 /** 2018 * PSR SU debug flags. 2019 */ 2020 struct { 2021 /** 2022 * Update dirty rect in SW only. 2023 */ 2024 uint8_t update_dirty_rect_only : 1; 2025 /** 2026 * Reset the cursor/plane state before processing the call. 2027 */ 2028 uint8_t reset_state : 1; 2029 } bitfields; 2030 2031 /** 2032 * Union for debug flags. 2033 */ 2034 uint32_t u32All; 2035 }; 2036 2037 /** 2038 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2039 * This triggers a selective update for PSR SU. 2040 */ 2041 struct dmub_cmd_update_dirty_rect_data { 2042 /** 2043 * Dirty rects from OS. 2044 */ 2045 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2046 /** 2047 * PSR SU debug flags. 2048 */ 2049 union dmub_psr_su_debug_flags debug_flags; 2050 /** 2051 * OTG HW instance. 2052 */ 2053 uint8_t pipe_idx; 2054 /** 2055 * Number of dirty rects. 2056 */ 2057 uint8_t dirty_rect_count; 2058 /** 2059 * PSR control version. 2060 */ 2061 uint8_t cmd_version; 2062 /** 2063 * Panel Instance. 2064 * Panel isntance to identify which psr_state to use 2065 * Currently the support is only for 0 or 1 2066 */ 2067 uint8_t panel_inst; 2068 }; 2069 2070 /** 2071 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2072 */ 2073 struct dmub_rb_cmd_update_dirty_rect { 2074 /** 2075 * Command header. 2076 */ 2077 struct dmub_cmd_header header; 2078 /** 2079 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2080 */ 2081 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2082 }; 2083 2084 /** 2085 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2086 */ 2087 struct dmub_cmd_update_cursor_info_data { 2088 /** 2089 * Cursor dirty rects. 2090 */ 2091 struct dmub_rect cursor_rect; 2092 /** 2093 * PSR SU debug flags. 2094 */ 2095 union dmub_psr_su_debug_flags debug_flags; 2096 /** 2097 * Cursor enable/disable. 2098 */ 2099 uint8_t enable; 2100 /** 2101 * OTG HW instance. 2102 */ 2103 uint8_t pipe_idx; 2104 /** 2105 * PSR control version. 2106 */ 2107 uint8_t cmd_version; 2108 /** 2109 * Panel Instance. 2110 * Panel isntance to identify which psr_state to use 2111 * Currently the support is only for 0 or 1 2112 */ 2113 uint8_t panel_inst; 2114 }; 2115 /** 2116 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2117 */ 2118 struct dmub_rb_cmd_update_cursor_info { 2119 /** 2120 * Command header. 2121 */ 2122 struct dmub_cmd_header header; 2123 /** 2124 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2125 */ 2126 struct dmub_cmd_update_cursor_info_data update_cursor_info_data; 2127 }; 2128 2129 /** 2130 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2131 */ 2132 struct dmub_cmd_psr_set_vtotal_data { 2133 /** 2134 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2135 */ 2136 uint16_t psr_vtotal_idle; 2137 /** 2138 * PSR control version. 2139 */ 2140 uint8_t cmd_version; 2141 /** 2142 * Panel Instance. 2143 * Panel isntance to identify which psr_state to use 2144 * Currently the support is only for 0 or 1 2145 */ 2146 uint8_t panel_inst; 2147 /* 2148 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2149 */ 2150 uint16_t psr_vtotal_su; 2151 /** 2152 * Explicit padding to 4 byte boundary. 2153 */ 2154 uint8_t pad2[2]; 2155 }; 2156 2157 /** 2158 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2159 */ 2160 struct dmub_rb_cmd_psr_set_vtotal { 2161 /** 2162 * Command header. 2163 */ 2164 struct dmub_cmd_header header; 2165 /** 2166 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2167 */ 2168 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2169 }; 2170 2171 /** 2172 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2173 */ 2174 struct dmub_cmd_psr_set_power_opt_data { 2175 /** 2176 * PSR control version. 2177 */ 2178 uint8_t cmd_version; 2179 /** 2180 * Panel Instance. 2181 * Panel isntance to identify which psr_state to use 2182 * Currently the support is only for 0 or 1 2183 */ 2184 uint8_t panel_inst; 2185 /** 2186 * Explicit padding to 4 byte boundary. 2187 */ 2188 uint8_t pad[2]; 2189 /** 2190 * PSR power option 2191 */ 2192 uint32_t power_opt; 2193 }; 2194 2195 /** 2196 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2197 */ 2198 struct dmub_rb_cmd_psr_set_power_opt { 2199 /** 2200 * Command header. 2201 */ 2202 struct dmub_cmd_header header; 2203 /** 2204 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2205 */ 2206 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2207 }; 2208 2209 /** 2210 * Set of HW components that can be locked. 2211 * 2212 * Note: If updating with more HW components, fields 2213 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2214 */ 2215 union dmub_hw_lock_flags { 2216 /** 2217 * Set of HW components that can be locked. 2218 */ 2219 struct { 2220 /** 2221 * Lock/unlock OTG master update lock. 2222 */ 2223 uint8_t lock_pipe : 1; 2224 /** 2225 * Lock/unlock cursor. 2226 */ 2227 uint8_t lock_cursor : 1; 2228 /** 2229 * Lock/unlock global update lock. 2230 */ 2231 uint8_t lock_dig : 1; 2232 /** 2233 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2234 */ 2235 uint8_t triple_buffer_lock : 1; 2236 } bits; 2237 2238 /** 2239 * Union for HW Lock flags. 2240 */ 2241 uint8_t u8All; 2242 }; 2243 2244 /** 2245 * Instances of HW to be locked. 2246 * 2247 * Note: If updating with more HW components, fields 2248 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2249 */ 2250 struct dmub_hw_lock_inst_flags { 2251 /** 2252 * OTG HW instance for OTG master update lock. 2253 */ 2254 uint8_t otg_inst; 2255 /** 2256 * OPP instance for cursor lock. 2257 */ 2258 uint8_t opp_inst; 2259 /** 2260 * OTG HW instance for global update lock. 2261 * TODO: Remove, and re-use otg_inst. 2262 */ 2263 uint8_t dig_inst; 2264 /** 2265 * Explicit pad to 4 byte boundary. 2266 */ 2267 uint8_t pad; 2268 }; 2269 2270 /** 2271 * Clients that can acquire the HW Lock Manager. 2272 * 2273 * Note: If updating with more clients, fields in 2274 * dmub_inbox0_cmd_lock_hw must be updated to match. 2275 */ 2276 enum hw_lock_client { 2277 /** 2278 * Driver is the client of HW Lock Manager. 2279 */ 2280 HW_LOCK_CLIENT_DRIVER = 0, 2281 /** 2282 * PSR SU is the client of HW Lock Manager. 2283 */ 2284 HW_LOCK_CLIENT_PSR_SU = 1, 2285 /** 2286 * Invalid client. 2287 */ 2288 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2289 }; 2290 2291 /** 2292 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2293 */ 2294 struct dmub_cmd_lock_hw_data { 2295 /** 2296 * Specifies the client accessing HW Lock Manager. 2297 */ 2298 enum hw_lock_client client; 2299 /** 2300 * HW instances to be locked. 2301 */ 2302 struct dmub_hw_lock_inst_flags inst_flags; 2303 /** 2304 * Which components to be locked. 2305 */ 2306 union dmub_hw_lock_flags hw_locks; 2307 /** 2308 * Specifies lock/unlock. 2309 */ 2310 uint8_t lock; 2311 /** 2312 * HW can be unlocked separately from releasing the HW Lock Mgr. 2313 * This flag is set if the client wishes to release the object. 2314 */ 2315 uint8_t should_release; 2316 /** 2317 * Explicit padding to 4 byte boundary. 2318 */ 2319 uint8_t pad; 2320 }; 2321 2322 /** 2323 * Definition of a DMUB_CMD__HW_LOCK command. 2324 * Command is used by driver and FW. 2325 */ 2326 struct dmub_rb_cmd_lock_hw { 2327 /** 2328 * Command header. 2329 */ 2330 struct dmub_cmd_header header; 2331 /** 2332 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2333 */ 2334 struct dmub_cmd_lock_hw_data lock_hw_data; 2335 }; 2336 2337 /** 2338 * ABM command sub-types. 2339 */ 2340 enum dmub_cmd_abm_type { 2341 /** 2342 * Initialize parameters for ABM algorithm. 2343 * Data is passed through an indirect buffer. 2344 */ 2345 DMUB_CMD__ABM_INIT_CONFIG = 0, 2346 /** 2347 * Set OTG and panel HW instance. 2348 */ 2349 DMUB_CMD__ABM_SET_PIPE = 1, 2350 /** 2351 * Set user requested backklight level. 2352 */ 2353 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2354 /** 2355 * Set ABM operating/aggression level. 2356 */ 2357 DMUB_CMD__ABM_SET_LEVEL = 3, 2358 /** 2359 * Set ambient light level. 2360 */ 2361 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2362 /** 2363 * Enable/disable fractional duty cycle for backlight PWM. 2364 */ 2365 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2366 2367 /** 2368 * unregister vertical interrupt after steady state is reached 2369 */ 2370 DMUB_CMD__ABM_PAUSE = 6, 2371 }; 2372 2373 /** 2374 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2375 * Requirements: 2376 * - Padded explicitly to 32-bit boundary. 2377 * - Must ensure this structure matches the one on driver-side, 2378 * otherwise it won't be aligned. 2379 */ 2380 struct abm_config_table { 2381 /** 2382 * Gamma curve thresholds, used for crgb conversion. 2383 */ 2384 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2385 /** 2386 * Gamma curve offsets, used for crgb conversion. 2387 */ 2388 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2389 /** 2390 * Gamma curve slopes, used for crgb conversion. 2391 */ 2392 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2393 /** 2394 * Custom backlight curve thresholds. 2395 */ 2396 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2397 /** 2398 * Custom backlight curve offsets. 2399 */ 2400 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2401 /** 2402 * Ambient light thresholds. 2403 */ 2404 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2405 /** 2406 * Minimum programmable backlight. 2407 */ 2408 uint16_t min_abm_backlight; // 122B 2409 /** 2410 * Minimum reduction values. 2411 */ 2412 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2413 /** 2414 * Maximum reduction values. 2415 */ 2416 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2417 /** 2418 * Bright positive gain. 2419 */ 2420 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2421 /** 2422 * Dark negative gain. 2423 */ 2424 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2425 /** 2426 * Hybrid factor. 2427 */ 2428 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2429 /** 2430 * Contrast factor. 2431 */ 2432 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2433 /** 2434 * Deviation gain. 2435 */ 2436 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2437 /** 2438 * Minimum knee. 2439 */ 2440 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2441 /** 2442 * Maximum knee. 2443 */ 2444 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2445 /** 2446 * Unused. 2447 */ 2448 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2449 /** 2450 * Explicit padding to 4 byte boundary. 2451 */ 2452 uint8_t pad3[3]; // 229B 2453 /** 2454 * Backlight ramp reduction. 2455 */ 2456 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2457 /** 2458 * Backlight ramp start. 2459 */ 2460 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2461 }; 2462 2463 /** 2464 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2465 */ 2466 struct dmub_cmd_abm_set_pipe_data { 2467 /** 2468 * OTG HW instance. 2469 */ 2470 uint8_t otg_inst; 2471 2472 /** 2473 * Panel Control HW instance. 2474 */ 2475 uint8_t panel_inst; 2476 2477 /** 2478 * Controls how ABM will interpret a set pipe or set level command. 2479 */ 2480 uint8_t set_pipe_option; 2481 2482 /** 2483 * Unused. 2484 * TODO: Remove. 2485 */ 2486 uint8_t ramping_boundary; 2487 }; 2488 2489 /** 2490 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2491 */ 2492 struct dmub_rb_cmd_abm_set_pipe { 2493 /** 2494 * Command header. 2495 */ 2496 struct dmub_cmd_header header; 2497 2498 /** 2499 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2500 */ 2501 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2502 }; 2503 2504 /** 2505 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2506 */ 2507 struct dmub_cmd_abm_set_backlight_data { 2508 /** 2509 * Number of frames to ramp to backlight user level. 2510 */ 2511 uint32_t frame_ramp; 2512 2513 /** 2514 * Requested backlight level from user. 2515 */ 2516 uint32_t backlight_user_level; 2517 2518 /** 2519 * ABM control version. 2520 */ 2521 uint8_t version; 2522 2523 /** 2524 * Panel Control HW instance mask. 2525 * Bit 0 is Panel Control HW instance 0. 2526 * Bit 1 is Panel Control HW instance 1. 2527 */ 2528 uint8_t panel_mask; 2529 2530 /** 2531 * Explicit padding to 4 byte boundary. 2532 */ 2533 uint8_t pad[2]; 2534 }; 2535 2536 /** 2537 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2538 */ 2539 struct dmub_rb_cmd_abm_set_backlight { 2540 /** 2541 * Command header. 2542 */ 2543 struct dmub_cmd_header header; 2544 2545 /** 2546 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2547 */ 2548 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2549 }; 2550 2551 /** 2552 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2553 */ 2554 struct dmub_cmd_abm_set_level_data { 2555 /** 2556 * Set current ABM operating/aggression level. 2557 */ 2558 uint32_t level; 2559 2560 /** 2561 * ABM control version. 2562 */ 2563 uint8_t version; 2564 2565 /** 2566 * Panel Control HW instance mask. 2567 * Bit 0 is Panel Control HW instance 0. 2568 * Bit 1 is Panel Control HW instance 1. 2569 */ 2570 uint8_t panel_mask; 2571 2572 /** 2573 * Explicit padding to 4 byte boundary. 2574 */ 2575 uint8_t pad[2]; 2576 }; 2577 2578 /** 2579 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2580 */ 2581 struct dmub_rb_cmd_abm_set_level { 2582 /** 2583 * Command header. 2584 */ 2585 struct dmub_cmd_header header; 2586 2587 /** 2588 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2589 */ 2590 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2591 }; 2592 2593 /** 2594 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2595 */ 2596 struct dmub_cmd_abm_set_ambient_level_data { 2597 /** 2598 * Ambient light sensor reading from OS. 2599 */ 2600 uint32_t ambient_lux; 2601 2602 /** 2603 * ABM control version. 2604 */ 2605 uint8_t version; 2606 2607 /** 2608 * Panel Control HW instance mask. 2609 * Bit 0 is Panel Control HW instance 0. 2610 * Bit 1 is Panel Control HW instance 1. 2611 */ 2612 uint8_t panel_mask; 2613 2614 /** 2615 * Explicit padding to 4 byte boundary. 2616 */ 2617 uint8_t pad[2]; 2618 }; 2619 2620 /** 2621 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2622 */ 2623 struct dmub_rb_cmd_abm_set_ambient_level { 2624 /** 2625 * Command header. 2626 */ 2627 struct dmub_cmd_header header; 2628 2629 /** 2630 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2631 */ 2632 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2633 }; 2634 2635 /** 2636 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2637 */ 2638 struct dmub_cmd_abm_set_pwm_frac_data { 2639 /** 2640 * Enable/disable fractional duty cycle for backlight PWM. 2641 * TODO: Convert to uint8_t. 2642 */ 2643 uint32_t fractional_pwm; 2644 2645 /** 2646 * ABM control version. 2647 */ 2648 uint8_t version; 2649 2650 /** 2651 * Panel Control HW instance mask. 2652 * Bit 0 is Panel Control HW instance 0. 2653 * Bit 1 is Panel Control HW instance 1. 2654 */ 2655 uint8_t panel_mask; 2656 2657 /** 2658 * Explicit padding to 4 byte boundary. 2659 */ 2660 uint8_t pad[2]; 2661 }; 2662 2663 /** 2664 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2665 */ 2666 struct dmub_rb_cmd_abm_set_pwm_frac { 2667 /** 2668 * Command header. 2669 */ 2670 struct dmub_cmd_header header; 2671 2672 /** 2673 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2674 */ 2675 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2676 }; 2677 2678 /** 2679 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2680 */ 2681 struct dmub_cmd_abm_init_config_data { 2682 /** 2683 * Location of indirect buffer used to pass init data to ABM. 2684 */ 2685 union dmub_addr src; 2686 2687 /** 2688 * Indirect buffer length. 2689 */ 2690 uint16_t bytes; 2691 2692 2693 /** 2694 * ABM control version. 2695 */ 2696 uint8_t version; 2697 2698 /** 2699 * Panel Control HW instance mask. 2700 * Bit 0 is Panel Control HW instance 0. 2701 * Bit 1 is Panel Control HW instance 1. 2702 */ 2703 uint8_t panel_mask; 2704 2705 /** 2706 * Explicit padding to 4 byte boundary. 2707 */ 2708 uint8_t pad[2]; 2709 }; 2710 2711 /** 2712 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2713 */ 2714 struct dmub_rb_cmd_abm_init_config { 2715 /** 2716 * Command header. 2717 */ 2718 struct dmub_cmd_header header; 2719 2720 /** 2721 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2722 */ 2723 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2724 }; 2725 2726 /** 2727 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2728 */ 2729 2730 struct dmub_cmd_abm_pause_data { 2731 2732 /** 2733 * Panel Control HW instance mask. 2734 * Bit 0 is Panel Control HW instance 0. 2735 * Bit 1 is Panel Control HW instance 1. 2736 */ 2737 uint8_t panel_mask; 2738 2739 /** 2740 * OTG hw instance 2741 */ 2742 uint8_t otg_inst; 2743 2744 /** 2745 * Enable or disable ABM pause 2746 */ 2747 uint8_t enable; 2748 2749 /** 2750 * Explicit padding to 4 byte boundary. 2751 */ 2752 uint8_t pad[1]; 2753 }; 2754 2755 /** 2756 * Definition of a DMUB_CMD__ABM_PAUSE command. 2757 */ 2758 struct dmub_rb_cmd_abm_pause { 2759 /** 2760 * Command header. 2761 */ 2762 struct dmub_cmd_header header; 2763 2764 /** 2765 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2766 */ 2767 struct dmub_cmd_abm_pause_data abm_pause_data; 2768 }; 2769 2770 /** 2771 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2772 */ 2773 struct dmub_cmd_query_feature_caps_data { 2774 /** 2775 * DMUB feature capabilities. 2776 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2777 */ 2778 struct dmub_feature_caps feature_caps; 2779 }; 2780 2781 /** 2782 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2783 */ 2784 struct dmub_rb_cmd_query_feature_caps { 2785 /** 2786 * Command header. 2787 */ 2788 struct dmub_cmd_header header; 2789 /** 2790 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2791 */ 2792 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2793 }; 2794 2795 /** 2796 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2797 */ 2798 struct dmub_cmd_visual_confirm_color_data { 2799 /** 2800 * DMUB feature capabilities. 2801 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2802 */ 2803 struct dmub_visual_confirm_color visual_confirm_color; 2804 }; 2805 2806 /** 2807 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2808 */ 2809 struct dmub_rb_cmd_get_visual_confirm_color { 2810 /** 2811 * Command header. 2812 */ 2813 struct dmub_cmd_header header; 2814 /** 2815 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2816 */ 2817 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 2818 }; 2819 2820 struct dmub_optc_state { 2821 uint32_t v_total_max; 2822 uint32_t v_total_min; 2823 uint32_t v_total_mid; 2824 uint32_t v_total_mid_frame_num; 2825 uint32_t tg_inst; 2826 uint32_t enable_manual_trigger; 2827 uint32_t clear_force_vsync; 2828 }; 2829 2830 struct dmub_rb_cmd_drr_update { 2831 struct dmub_cmd_header header; 2832 struct dmub_optc_state dmub_optc_state_req; 2833 }; 2834 2835 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 2836 uint32_t pix_clk_100hz; 2837 uint8_t max_ramp_step; 2838 uint8_t pipes; 2839 uint8_t min_refresh_in_hz; 2840 uint8_t padding[1]; 2841 }; 2842 2843 struct dmub_cmd_fw_assisted_mclk_switch_config { 2844 uint8_t fams_enabled; 2845 uint8_t visual_confirm_enabled; 2846 uint8_t padding[2]; 2847 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 2848 }; 2849 2850 struct dmub_rb_cmd_fw_assisted_mclk_switch { 2851 struct dmub_cmd_header header; 2852 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 2853 }; 2854 2855 /** 2856 * enum dmub_cmd_panel_cntl_type - Panel control command. 2857 */ 2858 enum dmub_cmd_panel_cntl_type { 2859 /** 2860 * Initializes embedded panel hardware blocks. 2861 */ 2862 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2863 /** 2864 * Queries backlight info for the embedded panel. 2865 */ 2866 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2867 }; 2868 2869 /** 2870 * struct dmub_cmd_panel_cntl_data - Panel control data. 2871 */ 2872 struct dmub_cmd_panel_cntl_data { 2873 uint32_t inst; /**< panel instance */ 2874 uint32_t current_backlight; /* in/out */ 2875 uint32_t bl_pwm_cntl; /* in/out */ 2876 uint32_t bl_pwm_period_cntl; /* in/out */ 2877 uint32_t bl_pwm_ref_div1; /* in/out */ 2878 uint8_t is_backlight_on : 1; /* in/out */ 2879 uint8_t is_powered_on : 1; /* in/out */ 2880 uint8_t padding[3]; 2881 uint32_t bl_pwm_ref_div2; /* in/out */ 2882 uint8_t reserved[4]; 2883 }; 2884 2885 /** 2886 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2887 */ 2888 struct dmub_rb_cmd_panel_cntl { 2889 struct dmub_cmd_header header; /**< header */ 2890 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2891 }; 2892 2893 /** 2894 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2895 */ 2896 struct dmub_cmd_lvtma_control_data { 2897 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2898 uint8_t reserved_0[3]; /**< For future use */ 2899 uint8_t panel_inst; /**< LVTMA control instance */ 2900 uint8_t reserved_1[3]; /**< For future use */ 2901 }; 2902 2903 /** 2904 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2905 */ 2906 struct dmub_rb_cmd_lvtma_control { 2907 /** 2908 * Command header. 2909 */ 2910 struct dmub_cmd_header header; 2911 /** 2912 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2913 */ 2914 struct dmub_cmd_lvtma_control_data data; 2915 }; 2916 2917 /** 2918 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2919 */ 2920 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 2921 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2922 uint8_t is_usb; /**< is phy is usb */ 2923 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 2924 uint8_t is_dp4; /**< is dp in 4 lane */ 2925 }; 2926 2927 /** 2928 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2929 */ 2930 struct dmub_rb_cmd_transmitter_query_dp_alt { 2931 struct dmub_cmd_header header; /**< header */ 2932 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 2933 }; 2934 2935 /** 2936 * Maximum number of bytes a chunk sent to DMUB for parsing 2937 */ 2938 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2939 2940 /** 2941 * Represent a chunk of CEA blocks sent to DMUB for parsing 2942 */ 2943 struct dmub_cmd_send_edid_cea { 2944 uint16_t offset; /**< offset into the CEA block */ 2945 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2946 uint16_t cea_total_length; /**< total length of the CEA block */ 2947 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2948 uint8_t pad[3]; /**< padding and for future expansion */ 2949 }; 2950 2951 /** 2952 * Result of VSDB parsing from CEA block 2953 */ 2954 struct dmub_cmd_edid_cea_amd_vsdb { 2955 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2956 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2957 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2958 uint16_t min_frame_rate; /**< Maximum frame rate */ 2959 uint16_t max_frame_rate; /**< Minimum frame rate */ 2960 }; 2961 2962 /** 2963 * Result of sending a CEA chunk 2964 */ 2965 struct dmub_cmd_edid_cea_ack { 2966 uint16_t offset; /**< offset of the chunk into the CEA block */ 2967 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2968 uint8_t pad; /**< padding and for future expansion */ 2969 }; 2970 2971 /** 2972 * Specify whether the result is an ACK/NACK or the parsing has finished 2973 */ 2974 enum dmub_cmd_edid_cea_reply_type { 2975 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2976 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2977 }; 2978 2979 /** 2980 * Definition of a DMUB_CMD__EDID_CEA command. 2981 */ 2982 struct dmub_rb_cmd_edid_cea { 2983 struct dmub_cmd_header header; /**< Command header */ 2984 union dmub_cmd_edid_cea_data { 2985 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2986 struct dmub_cmd_edid_cea_output { /**< output with results */ 2987 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2988 union { 2989 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2990 struct dmub_cmd_edid_cea_ack ack; 2991 }; 2992 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2993 } data; /**< Command data */ 2994 2995 }; 2996 2997 /** 2998 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 2999 */ 3000 struct dmub_cmd_cable_id_input { 3001 uint8_t phy_inst; /**< phy inst for cable id data */ 3002 }; 3003 3004 /** 3005 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3006 */ 3007 struct dmub_cmd_cable_id_output { 3008 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3009 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3010 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3011 uint8_t RESERVED :2; /**< reserved means not defined */ 3012 }; 3013 3014 /** 3015 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3016 */ 3017 struct dmub_rb_cmd_get_usbc_cable_id { 3018 struct dmub_cmd_header header; /**< Command header */ 3019 /** 3020 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3021 */ 3022 union dmub_cmd_cable_id_data { 3023 struct dmub_cmd_cable_id_input input; /**< Input */ 3024 struct dmub_cmd_cable_id_output output; /**< Output */ 3025 uint8_t output_raw; /**< Raw data output */ 3026 } data; 3027 }; 3028 3029 /** 3030 * union dmub_rb_cmd - DMUB inbox command. 3031 */ 3032 union dmub_rb_cmd { 3033 /** 3034 * Elements shared with all commands. 3035 */ 3036 struct dmub_rb_cmd_common cmd_common; 3037 /** 3038 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3039 */ 3040 struct dmub_rb_cmd_read_modify_write read_modify_write; 3041 /** 3042 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3043 */ 3044 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3045 /** 3046 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3047 */ 3048 struct dmub_rb_cmd_burst_write burst_write; 3049 /** 3050 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3051 */ 3052 struct dmub_rb_cmd_reg_wait reg_wait; 3053 /** 3054 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3055 */ 3056 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3057 /** 3058 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3059 */ 3060 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3061 /** 3062 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3063 */ 3064 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3065 /** 3066 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3067 */ 3068 struct dmub_rb_cmd_dpphy_init dpphy_init; 3069 /** 3070 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3071 */ 3072 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3073 /** 3074 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3075 */ 3076 struct dmub_rb_cmd_psr_set_version psr_set_version; 3077 /** 3078 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3079 */ 3080 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3081 /** 3082 * Definition of a DMUB_CMD__PSR_ENABLE command. 3083 */ 3084 struct dmub_rb_cmd_psr_enable psr_enable; 3085 /** 3086 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3087 */ 3088 struct dmub_rb_cmd_psr_set_level psr_set_level; 3089 /** 3090 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3091 */ 3092 struct dmub_rb_cmd_psr_force_static psr_force_static; 3093 /** 3094 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3095 */ 3096 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3097 /** 3098 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3099 */ 3100 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3101 /** 3102 * Definition of a DMUB_CMD__HW_LOCK command. 3103 * Command is used by driver and FW. 3104 */ 3105 struct dmub_rb_cmd_lock_hw lock_hw; 3106 /** 3107 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3108 */ 3109 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3110 /** 3111 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3112 */ 3113 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3114 /** 3115 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3116 */ 3117 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3118 /** 3119 * Definition of a DMUB_CMD__MALL command. 3120 */ 3121 struct dmub_rb_cmd_mall mall; 3122 /** 3123 * Definition of a DMUB_CMD__CAB command. 3124 */ 3125 struct dmub_rb_cmd_cab_for_ss cab; 3126 3127 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3128 3129 /** 3130 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3131 */ 3132 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3133 3134 /** 3135 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3136 */ 3137 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3138 3139 /** 3140 * Definition of DMUB_CMD__PANEL_CNTL commands. 3141 */ 3142 struct dmub_rb_cmd_panel_cntl panel_cntl; 3143 /** 3144 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3145 */ 3146 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3147 3148 /** 3149 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3150 */ 3151 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3152 3153 /** 3154 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3155 */ 3156 struct dmub_rb_cmd_abm_set_level abm_set_level; 3157 3158 /** 3159 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3160 */ 3161 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3162 3163 /** 3164 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3165 */ 3166 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3167 3168 /** 3169 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3170 */ 3171 struct dmub_rb_cmd_abm_init_config abm_init_config; 3172 3173 /** 3174 * Definition of a DMUB_CMD__ABM_PAUSE command. 3175 */ 3176 struct dmub_rb_cmd_abm_pause abm_pause; 3177 3178 /** 3179 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3180 */ 3181 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3182 3183 /** 3184 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3185 */ 3186 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3187 3188 /** 3189 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3190 */ 3191 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3192 3193 /** 3194 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3195 */ 3196 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3197 struct dmub_rb_cmd_drr_update drr_update; 3198 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3199 3200 /** 3201 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3202 */ 3203 struct dmub_rb_cmd_lvtma_control lvtma_control; 3204 /** 3205 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3206 */ 3207 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3208 /** 3209 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3210 */ 3211 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3212 /** 3213 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3214 */ 3215 struct dmub_rb_cmd_set_config_access set_config_access; 3216 /** 3217 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3218 */ 3219 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3220 /** 3221 * Definition of a DMUB_CMD__EDID_CEA command. 3222 */ 3223 struct dmub_rb_cmd_edid_cea edid_cea; 3224 /** 3225 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3226 */ 3227 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3228 3229 /** 3230 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3231 */ 3232 struct dmub_rb_cmd_query_hpd_state query_hpd; 3233 }; 3234 3235 /** 3236 * union dmub_rb_out_cmd - Outbox command 3237 */ 3238 union dmub_rb_out_cmd { 3239 /** 3240 * Parameters common to every command. 3241 */ 3242 struct dmub_rb_cmd_common cmd_common; 3243 /** 3244 * AUX reply command. 3245 */ 3246 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3247 /** 3248 * HPD notify command. 3249 */ 3250 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3251 /** 3252 * SET_CONFIG reply command. 3253 */ 3254 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3255 }; 3256 #pragma pack(pop) 3257 3258 3259 //============================================================================== 3260 //</DMUB_CMD>=================================================================== 3261 //============================================================================== 3262 //< DMUB_RB>==================================================================== 3263 //============================================================================== 3264 3265 #if defined(__cplusplus) 3266 extern "C" { 3267 #endif 3268 3269 /** 3270 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3271 */ 3272 struct dmub_rb_init_params { 3273 void *ctx; /**< Caller provided context pointer */ 3274 void *base_address; /**< CPU base address for ring's data */ 3275 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3276 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3277 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3278 }; 3279 3280 /** 3281 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3282 */ 3283 struct dmub_rb { 3284 void *base_address; /**< CPU address for the ring's data */ 3285 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3286 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3287 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3288 3289 void *ctx; /**< Caller provided context pointer */ 3290 void *dmub; /**< Pointer to the DMUB interface */ 3291 }; 3292 3293 /** 3294 * @brief Checks if the ringbuffer is empty. 3295 * 3296 * @param rb DMUB Ringbuffer 3297 * @return true if empty 3298 * @return false otherwise 3299 */ 3300 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3301 { 3302 return (rb->wrpt == rb->rptr); 3303 } 3304 3305 /** 3306 * @brief Checks if the ringbuffer is full 3307 * 3308 * @param rb DMUB Ringbuffer 3309 * @return true if full 3310 * @return false otherwise 3311 */ 3312 static inline bool dmub_rb_full(struct dmub_rb *rb) 3313 { 3314 uint32_t data_count; 3315 3316 if (rb->wrpt >= rb->rptr) 3317 data_count = rb->wrpt - rb->rptr; 3318 else 3319 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3320 3321 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3322 } 3323 3324 /** 3325 * @brief Pushes a command into the ringbuffer 3326 * 3327 * @param rb DMUB ringbuffer 3328 * @param cmd The command to push 3329 * @return true if the ringbuffer was not full 3330 * @return false otherwise 3331 */ 3332 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3333 const union dmub_rb_cmd *cmd) 3334 { 3335 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3336 const uint64_t *src = (const uint64_t *)cmd; 3337 uint8_t i; 3338 3339 if (dmub_rb_full(rb)) 3340 return false; 3341 3342 // copying data 3343 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3344 *dst++ = *src++; 3345 3346 rb->wrpt += DMUB_RB_CMD_SIZE; 3347 3348 if (rb->wrpt >= rb->capacity) 3349 rb->wrpt %= rb->capacity; 3350 3351 return true; 3352 } 3353 3354 /** 3355 * @brief Pushes a command into the DMUB outbox ringbuffer 3356 * 3357 * @param rb DMUB outbox ringbuffer 3358 * @param cmd Outbox command 3359 * @return true if not full 3360 * @return false otherwise 3361 */ 3362 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3363 const union dmub_rb_out_cmd *cmd) 3364 { 3365 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3366 const uint8_t *src = (const uint8_t *)cmd; 3367 3368 if (dmub_rb_full(rb)) 3369 return false; 3370 3371 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3372 3373 rb->wrpt += DMUB_RB_CMD_SIZE; 3374 3375 if (rb->wrpt >= rb->capacity) 3376 rb->wrpt %= rb->capacity; 3377 3378 return true; 3379 } 3380 3381 /** 3382 * @brief Returns the next unprocessed command in the ringbuffer. 3383 * 3384 * @param rb DMUB ringbuffer 3385 * @param cmd The command to return 3386 * @return true if not empty 3387 * @return false otherwise 3388 */ 3389 static inline bool dmub_rb_front(struct dmub_rb *rb, 3390 union dmub_rb_cmd **cmd) 3391 { 3392 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3393 3394 if (dmub_rb_empty(rb)) 3395 return false; 3396 3397 *cmd = (union dmub_rb_cmd *)rb_cmd; 3398 3399 return true; 3400 } 3401 3402 /** 3403 * @brief Determines the next ringbuffer offset. 3404 * 3405 * @param rb DMUB inbox ringbuffer 3406 * @param num_cmds Number of commands 3407 * @param next_rptr The next offset in the ringbuffer 3408 */ 3409 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3410 uint32_t num_cmds, 3411 uint32_t *next_rptr) 3412 { 3413 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3414 3415 if (*next_rptr >= rb->capacity) 3416 *next_rptr %= rb->capacity; 3417 } 3418 3419 /** 3420 * @brief Returns a pointer to a command in the inbox. 3421 * 3422 * @param rb DMUB inbox ringbuffer 3423 * @param cmd The inbox command to return 3424 * @param rptr The ringbuffer offset 3425 * @return true if not empty 3426 * @return false otherwise 3427 */ 3428 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3429 union dmub_rb_cmd **cmd, 3430 uint32_t rptr) 3431 { 3432 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3433 3434 if (dmub_rb_empty(rb)) 3435 return false; 3436 3437 *cmd = (union dmub_rb_cmd *)rb_cmd; 3438 3439 return true; 3440 } 3441 3442 /** 3443 * @brief Returns the next unprocessed command in the outbox. 3444 * 3445 * @param rb DMUB outbox ringbuffer 3446 * @param cmd The outbox command to return 3447 * @return true if not empty 3448 * @return false otherwise 3449 */ 3450 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3451 union dmub_rb_out_cmd *cmd) 3452 { 3453 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3454 uint64_t *dst = (uint64_t *)cmd; 3455 uint8_t i; 3456 3457 if (dmub_rb_empty(rb)) 3458 return false; 3459 3460 // copying data 3461 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3462 *dst++ = *src++; 3463 3464 return true; 3465 } 3466 3467 /** 3468 * @brief Removes the front entry in the ringbuffer. 3469 * 3470 * @param rb DMUB ringbuffer 3471 * @return true if the command was removed 3472 * @return false if there were no commands 3473 */ 3474 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3475 { 3476 if (dmub_rb_empty(rb)) 3477 return false; 3478 3479 rb->rptr += DMUB_RB_CMD_SIZE; 3480 3481 if (rb->rptr >= rb->capacity) 3482 rb->rptr %= rb->capacity; 3483 3484 return true; 3485 } 3486 3487 /** 3488 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3489 * 3490 * Avoids a race condition where DMCUB accesses memory while 3491 * there are still writes in flight to framebuffer. 3492 * 3493 * @param rb DMUB ringbuffer 3494 */ 3495 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3496 { 3497 uint32_t rptr = rb->rptr; 3498 uint32_t wptr = rb->wrpt; 3499 3500 while (rptr != wptr) { 3501 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3502 uint8_t i; 3503 3504 /* Don't remove this. 3505 * The contents need to actually be read from the ring buffer 3506 * for this function to be effective. 3507 */ 3508 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3509 (void)READ_ONCE(*data++); 3510 3511 rptr += DMUB_RB_CMD_SIZE; 3512 if (rptr >= rb->capacity) 3513 rptr %= rb->capacity; 3514 } 3515 } 3516 3517 /** 3518 * @brief Initializes a DMCUB ringbuffer 3519 * 3520 * @param rb DMUB ringbuffer 3521 * @param init_params initial configuration for the ringbuffer 3522 */ 3523 static inline void dmub_rb_init(struct dmub_rb *rb, 3524 struct dmub_rb_init_params *init_params) 3525 { 3526 rb->base_address = init_params->base_address; 3527 rb->capacity = init_params->capacity; 3528 rb->rptr = init_params->read_ptr; 3529 rb->wrpt = init_params->write_ptr; 3530 } 3531 3532 /** 3533 * @brief Copies output data from in/out commands into the given command. 3534 * 3535 * @param rb DMUB ringbuffer 3536 * @param cmd Command to copy data into 3537 */ 3538 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3539 union dmub_rb_cmd *cmd) 3540 { 3541 // Copy rb entry back into command 3542 uint8_t *rd_ptr = (rb->rptr == 0) ? 3543 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3544 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3545 3546 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3547 } 3548 3549 #if defined(__cplusplus) 3550 } 3551 #endif 3552 3553 //============================================================================== 3554 //</DMUB_RB>==================================================================== 3555 //============================================================================== 3556 3557 #endif /* _DMUB_CMD_H_ */ 3558