1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 #include <stdarg.h> 43 44 #include "atomfirmware.h" 45 46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 47 48 /* Firmware versioning. */ 49 #ifdef DMUB_EXPOSE_VERSION 50 #define DMUB_FW_VERSION_GIT_HASH 0x8bb402f5a 51 #define DMUB_FW_VERSION_MAJOR 0 52 #define DMUB_FW_VERSION_MINOR 0 53 #define DMUB_FW_VERSION_REVISION 58 54 #define DMUB_FW_VERSION_TEST 0 55 #define DMUB_FW_VERSION_VBIOS 0 56 #define DMUB_FW_VERSION_HOTFIX 0 57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 62 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 63 64 #endif 65 66 //<DMUB_TYPES>================================================================== 67 /* Basic type definitions. */ 68 69 #define __forceinline inline 70 71 /** 72 * Flag from driver to indicate that ABM should be disabled gradually 73 * by slowly reversing all backlight programming and pixel compensation. 74 */ 75 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 76 77 /** 78 * Flag from driver to indicate that ABM should be disabled immediately 79 * and undo all backlight programming and pixel compensation. 80 */ 81 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 82 83 /** 84 * Flag from driver to indicate that ABM should be disabled immediately 85 * and keep the current backlight programming and pixel compensation. 86 */ 87 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 88 89 /** 90 * Flag from driver to set the current ABM pipe index or ABM operating level. 91 */ 92 #define SET_ABM_PIPE_NORMAL 1 93 94 /** 95 * Number of ambient light levels in ABM algorithm. 96 */ 97 #define NUM_AMBI_LEVEL 5 98 99 /** 100 * Number of operating/aggression levels in ABM algorithm. 101 */ 102 #define NUM_AGGR_LEVEL 4 103 104 /** 105 * Number of segments in the gamma curve. 106 */ 107 #define NUM_POWER_FN_SEGS 8 108 109 /** 110 * Number of segments in the backlight curve. 111 */ 112 #define NUM_BL_CURVE_SEGS 16 113 114 /* Maximum number of streams on any ASIC. */ 115 #define DMUB_MAX_STREAMS 6 116 117 /* Maximum number of planes on any ASIC. */ 118 #define DMUB_MAX_PLANES 6 119 120 /* Trace buffer offset for entry */ 121 #define TRACE_BUFFER_ENTRY_OFFSET 16 122 123 /** 124 * Physical framebuffer address location, 64-bit. 125 */ 126 #ifndef PHYSICAL_ADDRESS_LOC 127 #define PHYSICAL_ADDRESS_LOC union large_integer 128 #endif 129 130 /** 131 * OS/FW agnostic memcpy 132 */ 133 #ifndef dmub_memcpy 134 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 135 #endif 136 137 /** 138 * OS/FW agnostic memset 139 */ 140 #ifndef dmub_memset 141 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 142 #endif 143 144 #if defined(__cplusplus) 145 extern "C" { 146 #endif 147 148 /** 149 * OS/FW agnostic udelay 150 */ 151 #ifndef dmub_udelay 152 #define dmub_udelay(microseconds) udelay(microseconds) 153 #endif 154 155 /** 156 * union dmub_addr - DMUB physical/virtual 64-bit address. 157 */ 158 union dmub_addr { 159 struct { 160 uint32_t low_part; /**< Lower 32 bits */ 161 uint32_t high_part; /**< Upper 32 bits */ 162 } u; /*<< Low/high bit access */ 163 uint64_t quad_part; /*<< 64 bit address */ 164 }; 165 166 /** 167 * Flags that can be set by driver to change some PSR behaviour. 168 */ 169 union dmub_psr_debug_flags { 170 /** 171 * Debug flags. 172 */ 173 struct { 174 /** 175 * Enable visual confirm in FW. 176 */ 177 uint32_t visual_confirm : 1; 178 /** 179 * Use HW Lock Mgr object to do HW locking in FW. 180 */ 181 uint32_t use_hw_lock_mgr : 1; 182 183 /** 184 * Unused. 185 * TODO: Remove. 186 */ 187 uint32_t log_line_nums : 1; 188 } bitfields; 189 190 /** 191 * Union for debug flags. 192 */ 193 uint32_t u32All; 194 }; 195 196 /** 197 * DMUB feature capabilities. 198 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 199 */ 200 struct dmub_feature_caps { 201 /** 202 * Max PSR version supported by FW. 203 */ 204 uint8_t psr; 205 uint8_t reserved[7]; 206 }; 207 208 #if defined(__cplusplus) 209 } 210 #endif 211 212 //============================================================================== 213 //</DMUB_TYPES>================================================================= 214 //============================================================================== 215 //< DMUB_META>================================================================== 216 //============================================================================== 217 #pragma pack(push, 1) 218 219 /* Magic value for identifying dmub_fw_meta_info */ 220 #define DMUB_FW_META_MAGIC 0x444D5542 221 222 /* Offset from the end of the file to the dmub_fw_meta_info */ 223 #define DMUB_FW_META_OFFSET 0x24 224 225 /** 226 * struct dmub_fw_meta_info - metadata associated with fw binary 227 * 228 * NOTE: This should be considered a stable API. Fields should 229 * not be repurposed or reordered. New fields should be 230 * added instead to extend the structure. 231 * 232 * @magic_value: magic value identifying DMUB firmware meta info 233 * @fw_region_size: size of the firmware state region 234 * @trace_buffer_size: size of the tracebuffer region 235 * @fw_version: the firmware version information 236 * @dal_fw: 1 if the firmware is DAL 237 */ 238 struct dmub_fw_meta_info { 239 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 240 uint32_t fw_region_size; /**< size of the firmware state region */ 241 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 242 uint32_t fw_version; /**< the firmware version information */ 243 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 244 uint8_t reserved[3]; /**< padding bits */ 245 }; 246 247 /** 248 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 249 */ 250 union dmub_fw_meta { 251 struct dmub_fw_meta_info info; /**< metadata info */ 252 uint8_t reserved[64]; /**< padding bits */ 253 }; 254 255 #pragma pack(pop) 256 257 //============================================================================== 258 //< DMUB Trace Buffer>================================================================ 259 //============================================================================== 260 /** 261 * dmub_trace_code_t - firmware trace code, 32-bits 262 */ 263 typedef uint32_t dmub_trace_code_t; 264 265 /** 266 * struct dmcub_trace_buf_entry - Firmware trace entry 267 */ 268 struct dmcub_trace_buf_entry { 269 dmub_trace_code_t trace_code; /**< trace code for the event */ 270 uint32_t tick_count; /**< the tick count at time of trace */ 271 uint32_t param0; /**< trace defined parameter 0 */ 272 uint32_t param1; /**< trace defined parameter 1 */ 273 }; 274 275 //============================================================================== 276 //< DMUB_STATUS>================================================================ 277 //============================================================================== 278 279 /** 280 * DMCUB scratch registers can be used to determine firmware status. 281 * Current scratch register usage is as follows: 282 * 283 * SCRATCH0: FW Boot Status register 284 * SCRATCH15: FW Boot Options register 285 */ 286 287 /** 288 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 289 */ 290 union dmub_fw_boot_status { 291 struct { 292 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 293 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 294 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 295 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 296 } bits; /**< status bits */ 297 uint32_t all; /**< 32-bit access to status bits */ 298 }; 299 300 /** 301 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 302 */ 303 enum dmub_fw_boot_status_bit { 304 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 305 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 306 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 307 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 308 }; 309 310 /** 311 * union dmub_fw_boot_options - Boot option definitions for SCRATCH15 312 */ 313 union dmub_fw_boot_options { 314 struct { 315 uint32_t pemu_env : 1; /**< 1 if PEMU */ 316 uint32_t fpga_env : 1; /**< 1 if FPGA */ 317 uint32_t optimized_init : 1; /**< 1 if optimized init */ 318 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 319 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 320 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 321 uint32_t reserved : 26; /**< reserved */ 322 } bits; /**< boot bits */ 323 uint32_t all; /**< 32-bit access to bits */ 324 }; 325 326 enum dmub_fw_boot_options_bit { 327 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 328 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 329 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 330 }; 331 332 //============================================================================== 333 //</DMUB_STATUS>================================================================ 334 //============================================================================== 335 //< DMUB_VBIOS>================================================================= 336 //============================================================================== 337 338 /* 339 * enum dmub_cmd_vbios_type - VBIOS commands. 340 * 341 * Command IDs should be treated as stable ABI. 342 * Do not reuse or modify IDs. 343 */ 344 enum dmub_cmd_vbios_type { 345 /** 346 * Configures the DIG encoder. 347 */ 348 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 349 /** 350 * Controls the PHY. 351 */ 352 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 353 /** 354 * Sets the pixel clock/symbol clock. 355 */ 356 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 357 /** 358 * Enables or disables power gating. 359 */ 360 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 361 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 362 }; 363 364 //============================================================================== 365 //</DMUB_VBIOS>================================================================= 366 //============================================================================== 367 //< DMUB_GPINT>================================================================= 368 //============================================================================== 369 370 /** 371 * The shifts and masks below may alternatively be used to format and read 372 * the command register bits. 373 */ 374 375 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 376 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 377 378 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 379 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 380 381 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 382 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 383 384 /** 385 * Command responses. 386 */ 387 388 /** 389 * Return response for DMUB_GPINT__STOP_FW command. 390 */ 391 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 392 393 /** 394 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 395 */ 396 union dmub_gpint_data_register { 397 struct { 398 uint32_t param : 16; /**< 16-bit parameter */ 399 uint32_t command_code : 12; /**< GPINT command */ 400 uint32_t status : 4; /**< Command status bit */ 401 } bits; /**< GPINT bit access */ 402 uint32_t all; /**< GPINT 32-bit access */ 403 }; 404 405 /* 406 * enum dmub_gpint_command - GPINT command to DMCUB FW 407 * 408 * Command IDs should be treated as stable ABI. 409 * Do not reuse or modify IDs. 410 */ 411 enum dmub_gpint_command { 412 /** 413 * Invalid command, ignored. 414 */ 415 DMUB_GPINT__INVALID_COMMAND = 0, 416 /** 417 * DESC: Queries the firmware version. 418 * RETURN: Firmware version. 419 */ 420 DMUB_GPINT__GET_FW_VERSION = 1, 421 /** 422 * DESC: Halts the firmware. 423 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 424 */ 425 DMUB_GPINT__STOP_FW = 2, 426 /** 427 * DESC: Get PSR state from FW. 428 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 429 */ 430 DMUB_GPINT__GET_PSR_STATE = 7, 431 /** 432 * DESC: Notifies DMCUB of the currently active streams. 433 * ARGS: Stream mask, 1 bit per active stream index. 434 */ 435 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 436 /** 437 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 438 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 439 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 440 * RETURN: PSR residency in milli-percent. 441 */ 442 DMUB_GPINT__PSR_RESIDENCY = 9, 443 }; 444 445 //============================================================================== 446 //</DMUB_GPINT>================================================================= 447 //============================================================================== 448 //< DMUB_CMD>=================================================================== 449 //============================================================================== 450 451 /** 452 * Size in bytes of each DMUB command. 453 */ 454 #define DMUB_RB_CMD_SIZE 64 455 456 /** 457 * Maximum number of items in the DMUB ringbuffer. 458 */ 459 #define DMUB_RB_MAX_ENTRY 128 460 461 /** 462 * Ringbuffer size in bytes. 463 */ 464 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 465 466 /** 467 * REG_SET mask for reg offload. 468 */ 469 #define REG_SET_MASK 0xFFFF 470 471 /* 472 * enum dmub_cmd_type - DMUB inbox command. 473 * 474 * Command IDs should be treated as stable ABI. 475 * Do not reuse or modify IDs. 476 */ 477 enum dmub_cmd_type { 478 /** 479 * Invalid command. 480 */ 481 DMUB_CMD__NULL = 0, 482 /** 483 * Read modify write register sequence offload. 484 */ 485 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 486 /** 487 * Field update register sequence offload. 488 */ 489 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 490 /** 491 * Burst write sequence offload. 492 */ 493 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 494 /** 495 * Reg wait sequence offload. 496 */ 497 DMUB_CMD__REG_REG_WAIT = 4, 498 /** 499 * Workaround to avoid HUBP underflow during NV12 playback. 500 */ 501 DMUB_CMD__PLAT_54186_WA = 5, 502 /** 503 * Command type used to query FW feature caps. 504 */ 505 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 506 /** 507 * Command type used for all PSR commands. 508 */ 509 DMUB_CMD__PSR = 64, 510 /** 511 * Command type used for all MALL commands. 512 */ 513 DMUB_CMD__MALL = 65, 514 /** 515 * Command type used for all ABM commands. 516 */ 517 DMUB_CMD__ABM = 66, 518 /** 519 * Command type used for HW locking in FW. 520 */ 521 DMUB_CMD__HW_LOCK = 69, 522 /** 523 * Command type used to access DP AUX. 524 */ 525 DMUB_CMD__DP_AUX_ACCESS = 70, 526 /** 527 * Command type used for OUTBOX1 notification enable 528 */ 529 DMUB_CMD__OUTBOX1_ENABLE = 71, 530 /** 531 * Command type used for all VBIOS interface commands. 532 */ 533 DMUB_CMD__VBIOS = 128, 534 }; 535 536 /** 537 * enum dmub_out_cmd_type - DMUB outbox commands. 538 */ 539 enum dmub_out_cmd_type { 540 /** 541 * Invalid outbox command, ignored. 542 */ 543 DMUB_OUT_CMD__NULL = 0, 544 /** 545 * Command type used for DP AUX Reply data notification 546 */ 547 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 548 /** 549 * Command type used for DP HPD event notification 550 */ 551 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 552 }; 553 554 #pragma pack(push, 1) 555 556 /** 557 * struct dmub_cmd_header - Common command header fields. 558 */ 559 struct dmub_cmd_header { 560 unsigned int type : 8; /**< command type */ 561 unsigned int sub_type : 8; /**< command sub type */ 562 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 563 unsigned int reserved0 : 7; /**< reserved bits */ 564 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 565 unsigned int reserved1 : 2; /**< reserved bits */ 566 }; 567 568 /* 569 * struct dmub_cmd_read_modify_write_sequence - Read modify write 570 * 571 * 60 payload bytes can hold up to 5 sets of read modify writes, 572 * each take 3 dwords. 573 * 574 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 575 * 576 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 577 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 578 */ 579 struct dmub_cmd_read_modify_write_sequence { 580 uint32_t addr; /**< register address */ 581 uint32_t modify_mask; /**< modify mask */ 582 uint32_t modify_value; /**< modify value */ 583 }; 584 585 /** 586 * Maximum number of ops in read modify write sequence. 587 */ 588 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 589 590 /** 591 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 592 */ 593 struct dmub_rb_cmd_read_modify_write { 594 struct dmub_cmd_header header; /**< command header */ 595 /** 596 * Read modify write sequence. 597 */ 598 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 599 }; 600 601 /* 602 * Update a register with specified masks and values sequeunce 603 * 604 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 605 * 606 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 607 * 608 * 609 * USE CASE: 610 * 1. auto-increment register where additional read would update pointer and produce wrong result 611 * 2. toggle a bit without read in the middle 612 */ 613 614 struct dmub_cmd_reg_field_update_sequence { 615 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 616 uint32_t modify_value; /**< value to update with */ 617 }; 618 619 /** 620 * Maximum number of ops in field update sequence. 621 */ 622 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 623 624 /** 625 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 626 */ 627 struct dmub_rb_cmd_reg_field_update_sequence { 628 struct dmub_cmd_header header; /**< command header */ 629 uint32_t addr; /**< register address */ 630 /** 631 * Field update sequence. 632 */ 633 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 634 }; 635 636 637 /** 638 * Maximum number of burst write values. 639 */ 640 #define DMUB_BURST_WRITE_VALUES__MAX 14 641 642 /* 643 * struct dmub_rb_cmd_burst_write - Burst write 644 * 645 * support use case such as writing out LUTs. 646 * 647 * 60 payload bytes can hold up to 14 values to write to given address 648 * 649 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 650 */ 651 struct dmub_rb_cmd_burst_write { 652 struct dmub_cmd_header header; /**< command header */ 653 uint32_t addr; /**< register start address */ 654 /** 655 * Burst write register values. 656 */ 657 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 658 }; 659 660 /** 661 * struct dmub_rb_cmd_common - Common command header 662 */ 663 struct dmub_rb_cmd_common { 664 struct dmub_cmd_header header; /**< command header */ 665 /** 666 * Padding to RB_CMD_SIZE 667 */ 668 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 669 }; 670 671 /** 672 * struct dmub_cmd_reg_wait_data - Register wait data 673 */ 674 struct dmub_cmd_reg_wait_data { 675 uint32_t addr; /**< Register address */ 676 uint32_t mask; /**< Mask for register bits */ 677 uint32_t condition_field_value; /**< Value to wait for */ 678 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 679 }; 680 681 /** 682 * struct dmub_rb_cmd_reg_wait - Register wait command 683 */ 684 struct dmub_rb_cmd_reg_wait { 685 struct dmub_cmd_header header; /**< Command header */ 686 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 687 }; 688 689 /** 690 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 691 * 692 * Reprograms surface parameters to avoid underflow. 693 */ 694 struct dmub_cmd_PLAT_54186_wa { 695 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 696 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 697 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 698 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 699 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 700 struct { 701 uint8_t hubp_inst : 4; /**< HUBP instance */ 702 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 703 uint8_t immediate :1; /**< Immediate flip */ 704 uint8_t vmid : 4; /**< VMID */ 705 uint8_t grph_stereo : 1; /**< 1 if stereo */ 706 uint32_t reserved : 21; /**< Reserved */ 707 } flip_params; /**< Pageflip parameters */ 708 uint32_t reserved[9]; /**< Reserved bits */ 709 }; 710 711 /** 712 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 713 */ 714 struct dmub_rb_cmd_PLAT_54186_wa { 715 struct dmub_cmd_header header; /**< Command header */ 716 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 717 }; 718 719 /** 720 * struct dmub_rb_cmd_mall - MALL command data. 721 */ 722 struct dmub_rb_cmd_mall { 723 struct dmub_cmd_header header; /**< Common command header */ 724 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 725 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 726 uint32_t tmr_delay; /**< Timer delay */ 727 uint32_t tmr_scale; /**< Timer scale */ 728 uint16_t cursor_width; /**< Cursor width in pixels */ 729 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 730 uint16_t cursor_height; /**< Cursor height in pixels */ 731 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 732 uint8_t debug_bits; /**< Debug bits */ 733 734 uint8_t reserved1; /**< Reserved bits */ 735 uint8_t reserved2; /**< Reserved bits */ 736 }; 737 738 /** 739 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 740 */ 741 struct dmub_cmd_digx_encoder_control_data { 742 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 743 }; 744 745 /** 746 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 747 */ 748 struct dmub_rb_cmd_digx_encoder_control { 749 struct dmub_cmd_header header; /**< header */ 750 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 751 }; 752 753 /** 754 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 755 */ 756 struct dmub_cmd_set_pixel_clock_data { 757 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 758 }; 759 760 /** 761 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 762 */ 763 struct dmub_rb_cmd_set_pixel_clock { 764 struct dmub_cmd_header header; /**< header */ 765 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 766 }; 767 768 /** 769 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 770 */ 771 struct dmub_cmd_enable_disp_power_gating_data { 772 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 773 }; 774 775 /** 776 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 777 */ 778 struct dmub_rb_cmd_enable_disp_power_gating { 779 struct dmub_cmd_header header; /**< header */ 780 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 781 }; 782 783 /** 784 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 785 */ 786 struct dmub_dig_transmitter_control_data_v1_7 { 787 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 788 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 789 union { 790 uint8_t digmode; /**< enum atom_encode_mode_def */ 791 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 792 } mode_laneset; 793 uint8_t lanenum; /**< Number of lanes */ 794 union { 795 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 796 } symclk_units; 797 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 798 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 799 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 800 uint8_t reserved0; /**< For future use */ 801 uint8_t reserved1; /**< For future use */ 802 uint8_t reserved2[3]; /**< For future use */ 803 uint32_t reserved3[11]; /**< For future use */ 804 }; 805 806 /** 807 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 808 */ 809 union dmub_cmd_dig1_transmitter_control_data { 810 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 811 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 812 }; 813 814 /** 815 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 816 */ 817 struct dmub_rb_cmd_dig1_transmitter_control { 818 struct dmub_cmd_header header; /**< header */ 819 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 820 }; 821 822 /** 823 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 824 */ 825 struct dmub_rb_cmd_dpphy_init { 826 struct dmub_cmd_header header; /**< header */ 827 uint8_t reserved[60]; /**< reserved bits */ 828 }; 829 830 /** 831 * enum dp_aux_request_action - DP AUX request command listing. 832 * 833 * 4 AUX request command bits are shifted to high nibble. 834 */ 835 enum dp_aux_request_action { 836 /** I2C-over-AUX write request */ 837 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 838 /** I2C-over-AUX read request */ 839 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 840 /** I2C-over-AUX write status request */ 841 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 842 /** I2C-over-AUX write request with MOT=1 */ 843 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 844 /** I2C-over-AUX read request with MOT=1 */ 845 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 846 /** I2C-over-AUX write status request with MOT=1 */ 847 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 848 /** Native AUX write request */ 849 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 850 /** Native AUX read request */ 851 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 852 }; 853 854 /** 855 * enum aux_return_code_type - DP AUX process return code listing. 856 */ 857 enum aux_return_code_type { 858 /** AUX process succeeded */ 859 AUX_RET_SUCCESS = 0, 860 /** AUX process failed with unknown reason */ 861 AUX_RET_ERROR_UNKNOWN, 862 /** AUX process completed with invalid reply */ 863 AUX_RET_ERROR_INVALID_REPLY, 864 /** AUX process timed out */ 865 AUX_RET_ERROR_TIMEOUT, 866 /** HPD was low during AUX process */ 867 AUX_RET_ERROR_HPD_DISCON, 868 /** Failed to acquire AUX engine */ 869 AUX_RET_ERROR_ENGINE_ACQUIRE, 870 /** AUX request not supported */ 871 AUX_RET_ERROR_INVALID_OPERATION, 872 /** AUX process not available */ 873 AUX_RET_ERROR_PROTOCOL_ERROR, 874 }; 875 876 /** 877 * enum aux_channel_type - DP AUX channel type listing. 878 */ 879 enum aux_channel_type { 880 /** AUX thru Legacy DP AUX */ 881 AUX_CHANNEL_LEGACY_DDC, 882 /** AUX thru DPIA DP tunneling */ 883 AUX_CHANNEL_DPIA 884 }; 885 886 /** 887 * struct aux_transaction_parameters - DP AUX request transaction data 888 */ 889 struct aux_transaction_parameters { 890 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 891 uint8_t action; /**< enum dp_aux_request_action */ 892 uint8_t length; /**< DP AUX request data length */ 893 uint8_t reserved; /**< For future use */ 894 uint32_t address; /**< DP AUX address */ 895 uint8_t data[16]; /**< DP AUX write data */ 896 }; 897 898 /** 899 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 900 */ 901 struct dmub_cmd_dp_aux_control_data { 902 uint8_t instance; /**< AUX instance or DPIA instance */ 903 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 904 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 905 uint8_t reserved0; /**< For future use */ 906 uint16_t timeout; /**< timeout time in us */ 907 uint16_t reserved1; /**< For future use */ 908 enum aux_channel_type type; /**< enum aux_channel_type */ 909 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 910 }; 911 912 /** 913 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 914 */ 915 struct dmub_rb_cmd_dp_aux_access { 916 /** 917 * Command header. 918 */ 919 struct dmub_cmd_header header; 920 /** 921 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 922 */ 923 struct dmub_cmd_dp_aux_control_data aux_control; 924 }; 925 926 /** 927 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 928 */ 929 struct dmub_rb_cmd_outbox1_enable { 930 /** 931 * Command header. 932 */ 933 struct dmub_cmd_header header; 934 /** 935 * enable: 0x0 -> disable outbox1 notification (default value) 936 * 0x1 -> enable outbox1 notification 937 */ 938 uint32_t enable; 939 }; 940 941 /* DP AUX Reply command - OutBox Cmd */ 942 /** 943 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 944 */ 945 struct aux_reply_data { 946 /** 947 * Aux cmd 948 */ 949 uint8_t command; 950 /** 951 * Aux reply data length (max: 16 bytes) 952 */ 953 uint8_t length; 954 /** 955 * Alignment only 956 */ 957 uint8_t pad[2]; 958 /** 959 * Aux reply data 960 */ 961 uint8_t data[16]; 962 }; 963 964 /** 965 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 966 */ 967 struct aux_reply_control_data { 968 /** 969 * Reserved for future use 970 */ 971 uint32_t handle; 972 /** 973 * Aux Instance 974 */ 975 uint8_t instance; 976 /** 977 * Aux transaction result: definition in enum aux_return_code_type 978 */ 979 uint8_t result; 980 /** 981 * Alignment only 982 */ 983 uint16_t pad; 984 }; 985 986 /** 987 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 988 */ 989 struct dmub_rb_cmd_dp_aux_reply { 990 /** 991 * Command header. 992 */ 993 struct dmub_cmd_header header; 994 /** 995 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 996 */ 997 struct aux_reply_control_data control; 998 /** 999 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1000 */ 1001 struct aux_reply_data reply_data; 1002 }; 1003 1004 /* DP HPD Notify command - OutBox Cmd */ 1005 /** 1006 * DP HPD Type 1007 */ 1008 enum dp_hpd_type { 1009 /** 1010 * Normal DP HPD 1011 */ 1012 DP_HPD = 0, 1013 /** 1014 * DP HPD short pulse 1015 */ 1016 DP_IRQ 1017 }; 1018 1019 /** 1020 * DP HPD Status 1021 */ 1022 enum dp_hpd_status { 1023 /** 1024 * DP_HPD status low 1025 */ 1026 DP_HPD_UNPLUG = 0, 1027 /** 1028 * DP_HPD status high 1029 */ 1030 DP_HPD_PLUG 1031 }; 1032 1033 /** 1034 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1035 */ 1036 struct dp_hpd_data { 1037 /** 1038 * DP HPD instance 1039 */ 1040 uint8_t instance; 1041 /** 1042 * HPD type 1043 */ 1044 uint8_t hpd_type; 1045 /** 1046 * HPD status: only for type: DP_HPD to indicate status 1047 */ 1048 uint8_t hpd_status; 1049 /** 1050 * Alignment only 1051 */ 1052 uint8_t pad; 1053 }; 1054 1055 /** 1056 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1057 */ 1058 struct dmub_rb_cmd_dp_hpd_notify { 1059 /** 1060 * Command header. 1061 */ 1062 struct dmub_cmd_header header; 1063 /** 1064 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1065 */ 1066 struct dp_hpd_data hpd_data; 1067 }; 1068 1069 /* 1070 * Command IDs should be treated as stable ABI. 1071 * Do not reuse or modify IDs. 1072 */ 1073 1074 /** 1075 * PSR command sub-types. 1076 */ 1077 enum dmub_cmd_psr_type { 1078 /** 1079 * Set PSR version support. 1080 */ 1081 DMUB_CMD__PSR_SET_VERSION = 0, 1082 /** 1083 * Copy driver-calculated parameters to PSR state. 1084 */ 1085 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1086 /** 1087 * Enable PSR. 1088 */ 1089 DMUB_CMD__PSR_ENABLE = 2, 1090 1091 /** 1092 * Disable PSR. 1093 */ 1094 DMUB_CMD__PSR_DISABLE = 3, 1095 1096 /** 1097 * Set PSR level. 1098 * PSR level is a 16-bit value dicated by driver that 1099 * will enable/disable different functionality. 1100 */ 1101 DMUB_CMD__PSR_SET_LEVEL = 4, 1102 1103 /** 1104 * Forces PSR enabled until an explicit PSR disable call. 1105 */ 1106 DMUB_CMD__PSR_FORCE_STATIC = 5, 1107 }; 1108 1109 /** 1110 * PSR versions. 1111 */ 1112 enum psr_version { 1113 /** 1114 * PSR version 1. 1115 */ 1116 PSR_VERSION_1 = 0, 1117 /** 1118 * PSR not supported. 1119 */ 1120 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1121 }; 1122 1123 /** 1124 * enum dmub_cmd_mall_type - MALL commands 1125 */ 1126 enum dmub_cmd_mall_type { 1127 /** 1128 * Allows display refresh from MALL. 1129 */ 1130 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1131 /** 1132 * Disallows display refresh from MALL. 1133 */ 1134 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1135 /** 1136 * Cursor copy for MALL. 1137 */ 1138 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1139 /** 1140 * Controls DF requests. 1141 */ 1142 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1143 }; 1144 1145 1146 /** 1147 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1148 */ 1149 struct dmub_cmd_psr_copy_settings_data { 1150 /** 1151 * Flags that can be set by driver to change some PSR behaviour. 1152 */ 1153 union dmub_psr_debug_flags debug; 1154 /** 1155 * 16-bit value dicated by driver that will enable/disable different functionality. 1156 */ 1157 uint16_t psr_level; 1158 /** 1159 * DPP HW instance. 1160 */ 1161 uint8_t dpp_inst; 1162 /** 1163 * MPCC HW instance. 1164 * Not used in dmub fw, 1165 * dmub fw will get active opp by reading odm registers. 1166 */ 1167 uint8_t mpcc_inst; 1168 /** 1169 * OPP HW instance. 1170 * Not used in dmub fw, 1171 * dmub fw will get active opp by reading odm registers. 1172 */ 1173 uint8_t opp_inst; 1174 /** 1175 * OTG HW instance. 1176 */ 1177 uint8_t otg_inst; 1178 /** 1179 * DIG FE HW instance. 1180 */ 1181 uint8_t digfe_inst; 1182 /** 1183 * DIG BE HW instance. 1184 */ 1185 uint8_t digbe_inst; 1186 /** 1187 * DP PHY HW instance. 1188 */ 1189 uint8_t dpphy_inst; 1190 /** 1191 * AUX HW instance. 1192 */ 1193 uint8_t aux_inst; 1194 /** 1195 * Determines if SMU optimzations are enabled/disabled. 1196 */ 1197 uint8_t smu_optimizations_en; 1198 /** 1199 * Unused. 1200 * TODO: Remove. 1201 */ 1202 uint8_t frame_delay; 1203 /** 1204 * If RFB setup time is greater than the total VBLANK time, 1205 * it is not possible for the sink to capture the video frame 1206 * in the same frame the SDP is sent. In this case, 1207 * the frame capture indication bit should be set and an extra 1208 * static frame should be transmitted to the sink. 1209 */ 1210 uint8_t frame_cap_ind; 1211 /** 1212 * Explicit padding to 4 byte boundary. 1213 */ 1214 uint8_t pad[2]; 1215 /** 1216 * Multi-display optimizations are implemented on certain ASICs. 1217 */ 1218 uint8_t multi_disp_optimizations_en; 1219 /** 1220 * The last possible line SDP may be transmitted without violating 1221 * the RFB setup time or entering the active video frame. 1222 */ 1223 uint16_t init_sdp_deadline; 1224 /** 1225 * Explicit padding to 4 byte boundary. 1226 */ 1227 uint16_t pad2; 1228 /** 1229 * Length of each horizontal line in us. 1230 */ 1231 uint32_t line_time_in_us; 1232 }; 1233 1234 /** 1235 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1236 */ 1237 struct dmub_rb_cmd_psr_copy_settings { 1238 /** 1239 * Command header. 1240 */ 1241 struct dmub_cmd_header header; 1242 /** 1243 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1244 */ 1245 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1246 }; 1247 1248 /** 1249 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1250 */ 1251 struct dmub_cmd_psr_set_level_data { 1252 /** 1253 * 16-bit value dicated by driver that will enable/disable different functionality. 1254 */ 1255 uint16_t psr_level; 1256 /** 1257 * Explicit padding to 4 byte boundary. 1258 */ 1259 uint8_t pad[2]; 1260 }; 1261 1262 /** 1263 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1264 */ 1265 struct dmub_rb_cmd_psr_set_level { 1266 /** 1267 * Command header. 1268 */ 1269 struct dmub_cmd_header header; 1270 /** 1271 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1272 */ 1273 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1274 }; 1275 1276 /** 1277 * Definition of a DMUB_CMD__PSR_ENABLE command. 1278 * PSR enable/disable is controlled using the sub_type. 1279 */ 1280 struct dmub_rb_cmd_psr_enable { 1281 /** 1282 * Command header. 1283 */ 1284 struct dmub_cmd_header header; 1285 }; 1286 1287 /** 1288 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1289 */ 1290 struct dmub_cmd_psr_set_version_data { 1291 /** 1292 * PSR version that FW should implement. 1293 */ 1294 enum psr_version version; 1295 }; 1296 1297 /** 1298 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1299 */ 1300 struct dmub_rb_cmd_psr_set_version { 1301 /** 1302 * Command header. 1303 */ 1304 struct dmub_cmd_header header; 1305 /** 1306 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1307 */ 1308 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1309 }; 1310 1311 /** 1312 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1313 */ 1314 struct dmub_rb_cmd_psr_force_static { 1315 /** 1316 * Command header. 1317 */ 1318 struct dmub_cmd_header header; 1319 }; 1320 1321 /** 1322 * Set of HW components that can be locked. 1323 */ 1324 union dmub_hw_lock_flags { 1325 /** 1326 * Set of HW components that can be locked. 1327 */ 1328 struct { 1329 /** 1330 * Lock/unlock OTG master update lock. 1331 */ 1332 uint8_t lock_pipe : 1; 1333 /** 1334 * Lock/unlock cursor. 1335 */ 1336 uint8_t lock_cursor : 1; 1337 /** 1338 * Lock/unlock global update lock. 1339 */ 1340 uint8_t lock_dig : 1; 1341 /** 1342 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1343 */ 1344 uint8_t triple_buffer_lock : 1; 1345 } bits; 1346 1347 /** 1348 * Union for HW Lock flags. 1349 */ 1350 uint8_t u8All; 1351 }; 1352 1353 /** 1354 * Instances of HW to be locked. 1355 */ 1356 struct dmub_hw_lock_inst_flags { 1357 /** 1358 * OTG HW instance for OTG master update lock. 1359 */ 1360 uint8_t otg_inst; 1361 /** 1362 * OPP instance for cursor lock. 1363 */ 1364 uint8_t opp_inst; 1365 /** 1366 * OTG HW instance for global update lock. 1367 * TODO: Remove, and re-use otg_inst. 1368 */ 1369 uint8_t dig_inst; 1370 /** 1371 * Explicit pad to 4 byte boundary. 1372 */ 1373 uint8_t pad; 1374 }; 1375 1376 /** 1377 * Clients that can acquire the HW Lock Manager. 1378 */ 1379 enum hw_lock_client { 1380 /** 1381 * Driver is the client of HW Lock Manager. 1382 */ 1383 HW_LOCK_CLIENT_DRIVER = 0, 1384 /** 1385 * FW is the client of HW Lock Manager. 1386 */ 1387 HW_LOCK_CLIENT_FW, 1388 /** 1389 * Invalid client. 1390 */ 1391 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1392 }; 1393 1394 /** 1395 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1396 */ 1397 struct dmub_cmd_lock_hw_data { 1398 /** 1399 * Specifies the client accessing HW Lock Manager. 1400 */ 1401 enum hw_lock_client client; 1402 /** 1403 * HW instances to be locked. 1404 */ 1405 struct dmub_hw_lock_inst_flags inst_flags; 1406 /** 1407 * Which components to be locked. 1408 */ 1409 union dmub_hw_lock_flags hw_locks; 1410 /** 1411 * Specifies lock/unlock. 1412 */ 1413 uint8_t lock; 1414 /** 1415 * HW can be unlocked separately from releasing the HW Lock Mgr. 1416 * This flag is set if the client wishes to release the object. 1417 */ 1418 uint8_t should_release; 1419 /** 1420 * Explicit padding to 4 byte boundary. 1421 */ 1422 uint8_t pad; 1423 }; 1424 1425 /** 1426 * Definition of a DMUB_CMD__HW_LOCK command. 1427 * Command is used by driver and FW. 1428 */ 1429 struct dmub_rb_cmd_lock_hw { 1430 /** 1431 * Command header. 1432 */ 1433 struct dmub_cmd_header header; 1434 /** 1435 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1436 */ 1437 struct dmub_cmd_lock_hw_data lock_hw_data; 1438 }; 1439 1440 /** 1441 * ABM command sub-types. 1442 */ 1443 enum dmub_cmd_abm_type { 1444 /** 1445 * Initialize parameters for ABM algorithm. 1446 * Data is passed through an indirect buffer. 1447 */ 1448 DMUB_CMD__ABM_INIT_CONFIG = 0, 1449 /** 1450 * Set OTG and panel HW instance. 1451 */ 1452 DMUB_CMD__ABM_SET_PIPE = 1, 1453 /** 1454 * Set user requested backklight level. 1455 */ 1456 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1457 /** 1458 * Set ABM operating/aggression level. 1459 */ 1460 DMUB_CMD__ABM_SET_LEVEL = 3, 1461 /** 1462 * Set ambient light level. 1463 */ 1464 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1465 /** 1466 * Enable/disable fractional duty cycle for backlight PWM. 1467 */ 1468 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1469 }; 1470 1471 /** 1472 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1473 * Requirements: 1474 * - Padded explicitly to 32-bit boundary. 1475 * - Must ensure this structure matches the one on driver-side, 1476 * otherwise it won't be aligned. 1477 */ 1478 struct abm_config_table { 1479 /** 1480 * Gamma curve thresholds, used for crgb conversion. 1481 */ 1482 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1483 /** 1484 * Gamma curve offsets, used for crgb conversion. 1485 */ 1486 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1487 /** 1488 * Gamma curve slopes, used for crgb conversion. 1489 */ 1490 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1491 /** 1492 * Custom backlight curve thresholds. 1493 */ 1494 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 1495 /** 1496 * Custom backlight curve offsets. 1497 */ 1498 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 1499 /** 1500 * Ambient light thresholds. 1501 */ 1502 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 1503 /** 1504 * Minimum programmable backlight. 1505 */ 1506 uint16_t min_abm_backlight; // 122B 1507 /** 1508 * Minimum reduction values. 1509 */ 1510 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 1511 /** 1512 * Maximum reduction values. 1513 */ 1514 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 1515 /** 1516 * Bright positive gain. 1517 */ 1518 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 1519 /** 1520 * Dark negative gain. 1521 */ 1522 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 1523 /** 1524 * Hybrid factor. 1525 */ 1526 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 1527 /** 1528 * Contrast factor. 1529 */ 1530 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 1531 /** 1532 * Deviation gain. 1533 */ 1534 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 1535 /** 1536 * Minimum knee. 1537 */ 1538 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 1539 /** 1540 * Maximum knee. 1541 */ 1542 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 1543 /** 1544 * Unused. 1545 */ 1546 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 1547 /** 1548 * Explicit padding to 4 byte boundary. 1549 */ 1550 uint8_t pad3[3]; // 229B 1551 /** 1552 * Backlight ramp reduction. 1553 */ 1554 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 1555 /** 1556 * Backlight ramp start. 1557 */ 1558 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 1559 }; 1560 1561 /** 1562 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1563 */ 1564 struct dmub_cmd_abm_set_pipe_data { 1565 /** 1566 * OTG HW instance. 1567 */ 1568 uint8_t otg_inst; 1569 1570 /** 1571 * Panel Control HW instance. 1572 */ 1573 uint8_t panel_inst; 1574 1575 /** 1576 * Controls how ABM will interpret a set pipe or set level command. 1577 */ 1578 uint8_t set_pipe_option; 1579 1580 /** 1581 * Unused. 1582 * TODO: Remove. 1583 */ 1584 uint8_t ramping_boundary; 1585 }; 1586 1587 /** 1588 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1589 */ 1590 struct dmub_rb_cmd_abm_set_pipe { 1591 /** 1592 * Command header. 1593 */ 1594 struct dmub_cmd_header header; 1595 1596 /** 1597 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1598 */ 1599 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 1600 }; 1601 1602 /** 1603 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1604 */ 1605 struct dmub_cmd_abm_set_backlight_data { 1606 /** 1607 * Number of frames to ramp to backlight user level. 1608 */ 1609 uint32_t frame_ramp; 1610 1611 /** 1612 * Requested backlight level from user. 1613 */ 1614 uint32_t backlight_user_level; 1615 }; 1616 1617 /** 1618 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 1619 */ 1620 struct dmub_rb_cmd_abm_set_backlight { 1621 /** 1622 * Command header. 1623 */ 1624 struct dmub_cmd_header header; 1625 1626 /** 1627 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1628 */ 1629 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 1630 }; 1631 1632 /** 1633 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1634 */ 1635 struct dmub_cmd_abm_set_level_data { 1636 /** 1637 * Set current ABM operating/aggression level. 1638 */ 1639 uint32_t level; 1640 }; 1641 1642 /** 1643 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 1644 */ 1645 struct dmub_rb_cmd_abm_set_level { 1646 /** 1647 * Command header. 1648 */ 1649 struct dmub_cmd_header header; 1650 1651 /** 1652 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1653 */ 1654 struct dmub_cmd_abm_set_level_data abm_set_level_data; 1655 }; 1656 1657 /** 1658 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1659 */ 1660 struct dmub_cmd_abm_set_ambient_level_data { 1661 /** 1662 * Ambient light sensor reading from OS. 1663 */ 1664 uint32_t ambient_lux; 1665 }; 1666 1667 /** 1668 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1669 */ 1670 struct dmub_rb_cmd_abm_set_ambient_level { 1671 /** 1672 * Command header. 1673 */ 1674 struct dmub_cmd_header header; 1675 1676 /** 1677 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1678 */ 1679 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 1680 }; 1681 1682 /** 1683 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1684 */ 1685 struct dmub_cmd_abm_set_pwm_frac_data { 1686 /** 1687 * Enable/disable fractional duty cycle for backlight PWM. 1688 * TODO: Convert to uint8_t. 1689 */ 1690 uint32_t fractional_pwm; 1691 }; 1692 1693 /** 1694 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 1695 */ 1696 struct dmub_rb_cmd_abm_set_pwm_frac { 1697 /** 1698 * Command header. 1699 */ 1700 struct dmub_cmd_header header; 1701 1702 /** 1703 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1704 */ 1705 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 1706 }; 1707 1708 /** 1709 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 1710 */ 1711 struct dmub_cmd_abm_init_config_data { 1712 /** 1713 * Location of indirect buffer used to pass init data to ABM. 1714 */ 1715 union dmub_addr src; 1716 1717 /** 1718 * Indirect buffer length. 1719 */ 1720 uint16_t bytes; 1721 }; 1722 1723 /** 1724 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 1725 */ 1726 struct dmub_rb_cmd_abm_init_config { 1727 /** 1728 * Command header. 1729 */ 1730 struct dmub_cmd_header header; 1731 1732 /** 1733 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 1734 */ 1735 struct dmub_cmd_abm_init_config_data abm_init_config_data; 1736 }; 1737 1738 /** 1739 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 1740 */ 1741 struct dmub_cmd_query_feature_caps_data { 1742 /** 1743 * DMUB feature capabilities. 1744 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 1745 */ 1746 struct dmub_feature_caps feature_caps; 1747 }; 1748 1749 /** 1750 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 1751 */ 1752 struct dmub_rb_cmd_query_feature_caps { 1753 /** 1754 * Command header. 1755 */ 1756 struct dmub_cmd_header header; 1757 /** 1758 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 1759 */ 1760 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 1761 }; 1762 1763 struct dmub_optc_state { 1764 uint32_t v_total_max; 1765 uint32_t v_total_min; 1766 uint32_t v_total_mid; 1767 uint32_t v_total_mid_frame_num; 1768 uint32_t tg_inst; 1769 uint32_t enable_manual_trigger; 1770 uint32_t clear_force_vsync; 1771 }; 1772 1773 struct dmub_rb_cmd_drr_update { 1774 struct dmub_cmd_header header; 1775 struct dmub_optc_state dmub_optc_state_req; 1776 }; 1777 1778 /** 1779 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1780 */ 1781 struct dmub_cmd_lvtma_control_data { 1782 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 1783 uint8_t reserved_0[3]; /**< For future use */ 1784 uint8_t panel_inst; /**< LVTMA control instance */ 1785 uint8_t reserved_1[3]; /**< For future use */ 1786 }; 1787 1788 /** 1789 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1790 */ 1791 struct dmub_rb_cmd_lvtma_control { 1792 /** 1793 * Command header. 1794 */ 1795 struct dmub_cmd_header header; 1796 /** 1797 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1798 */ 1799 struct dmub_cmd_lvtma_control_data data; 1800 }; 1801 1802 /** 1803 * union dmub_rb_cmd - DMUB inbox command. 1804 */ 1805 union dmub_rb_cmd { 1806 struct dmub_rb_cmd_lock_hw lock_hw; 1807 /** 1808 * Elements shared with all commands. 1809 */ 1810 struct dmub_rb_cmd_common cmd_common; 1811 /** 1812 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 1813 */ 1814 struct dmub_rb_cmd_read_modify_write read_modify_write; 1815 /** 1816 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 1817 */ 1818 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 1819 /** 1820 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 1821 */ 1822 struct dmub_rb_cmd_burst_write burst_write; 1823 /** 1824 * Definition of a DMUB_CMD__REG_REG_WAIT command. 1825 */ 1826 struct dmub_rb_cmd_reg_wait reg_wait; 1827 /** 1828 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 1829 */ 1830 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 1831 /** 1832 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 1833 */ 1834 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 1835 /** 1836 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 1837 */ 1838 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 1839 /** 1840 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 1841 */ 1842 struct dmub_rb_cmd_dpphy_init dpphy_init; 1843 /** 1844 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 1845 */ 1846 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 1847 /** 1848 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1849 */ 1850 struct dmub_rb_cmd_psr_set_version psr_set_version; 1851 /** 1852 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1853 */ 1854 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 1855 /** 1856 * Definition of a DMUB_CMD__PSR_ENABLE command. 1857 */ 1858 struct dmub_rb_cmd_psr_enable psr_enable; 1859 /** 1860 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1861 */ 1862 struct dmub_rb_cmd_psr_set_level psr_set_level; 1863 /** 1864 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1865 */ 1866 struct dmub_rb_cmd_psr_force_static psr_force_static; 1867 /** 1868 * Definition of a DMUB_CMD__PLAT_54186_WA command. 1869 */ 1870 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 1871 /** 1872 * Definition of a DMUB_CMD__MALL command. 1873 */ 1874 struct dmub_rb_cmd_mall mall; 1875 /** 1876 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1877 */ 1878 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 1879 1880 /** 1881 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 1882 */ 1883 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 1884 1885 /** 1886 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 1887 */ 1888 struct dmub_rb_cmd_abm_set_level abm_set_level; 1889 1890 /** 1891 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1892 */ 1893 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 1894 1895 /** 1896 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 1897 */ 1898 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 1899 1900 /** 1901 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 1902 */ 1903 struct dmub_rb_cmd_abm_init_config abm_init_config; 1904 1905 /** 1906 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1907 */ 1908 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 1909 1910 /** 1911 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1912 */ 1913 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 1914 1915 /** 1916 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 1917 */ 1918 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 1919 struct dmub_rb_cmd_drr_update drr_update; 1920 /** 1921 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1922 */ 1923 struct dmub_rb_cmd_lvtma_control lvtma_control; 1924 }; 1925 1926 /** 1927 * union dmub_rb_out_cmd - Outbox command 1928 */ 1929 union dmub_rb_out_cmd { 1930 /** 1931 * Parameters common to every command. 1932 */ 1933 struct dmub_rb_cmd_common cmd_common; 1934 /** 1935 * AUX reply command. 1936 */ 1937 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 1938 /** 1939 * HPD notify command. 1940 */ 1941 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 1942 }; 1943 #pragma pack(pop) 1944 1945 1946 //============================================================================== 1947 //</DMUB_CMD>=================================================================== 1948 //============================================================================== 1949 //< DMUB_RB>==================================================================== 1950 //============================================================================== 1951 1952 #if defined(__cplusplus) 1953 extern "C" { 1954 #endif 1955 1956 /** 1957 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 1958 */ 1959 struct dmub_rb_init_params { 1960 void *ctx; /**< Caller provided context pointer */ 1961 void *base_address; /**< CPU base address for ring's data */ 1962 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 1963 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 1964 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 1965 }; 1966 1967 /** 1968 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 1969 */ 1970 struct dmub_rb { 1971 void *base_address; /**< CPU address for the ring's data */ 1972 uint32_t rptr; /**< Read pointer for consumer in bytes */ 1973 uint32_t wrpt; /**< Write pointer for producer in bytes */ 1974 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 1975 1976 void *ctx; /**< Caller provided context pointer */ 1977 void *dmub; /**< Pointer to the DMUB interface */ 1978 }; 1979 1980 /** 1981 * @brief Checks if the ringbuffer is empty. 1982 * 1983 * @param rb DMUB Ringbuffer 1984 * @return true if empty 1985 * @return false otherwise 1986 */ 1987 static inline bool dmub_rb_empty(struct dmub_rb *rb) 1988 { 1989 return (rb->wrpt == rb->rptr); 1990 } 1991 1992 /** 1993 * @brief Checks if the ringbuffer is full 1994 * 1995 * @param rb DMUB Ringbuffer 1996 * @return true if full 1997 * @return false otherwise 1998 */ 1999 static inline bool dmub_rb_full(struct dmub_rb *rb) 2000 { 2001 uint32_t data_count; 2002 2003 if (rb->wrpt >= rb->rptr) 2004 data_count = rb->wrpt - rb->rptr; 2005 else 2006 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2007 2008 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2009 } 2010 2011 /** 2012 * @brief Pushes a command into the ringbuffer 2013 * 2014 * @param rb DMUB ringbuffer 2015 * @param cmd The command to push 2016 * @return true if the ringbuffer was not full 2017 * @return false otherwise 2018 */ 2019 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2020 const union dmub_rb_cmd *cmd) 2021 { 2022 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 2023 const uint64_t *src = (const uint64_t *)cmd; 2024 uint8_t i; 2025 2026 if (dmub_rb_full(rb)) 2027 return false; 2028 2029 // copying data 2030 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2031 *dst++ = *src++; 2032 2033 rb->wrpt += DMUB_RB_CMD_SIZE; 2034 2035 if (rb->wrpt >= rb->capacity) 2036 rb->wrpt %= rb->capacity; 2037 2038 return true; 2039 } 2040 2041 /** 2042 * @brief Pushes a command into the DMUB outbox ringbuffer 2043 * 2044 * @param rb DMUB outbox ringbuffer 2045 * @param cmd Outbox command 2046 * @return true if not full 2047 * @return false otherwise 2048 */ 2049 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2050 const union dmub_rb_out_cmd *cmd) 2051 { 2052 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2053 const uint8_t *src = (uint8_t *)cmd; 2054 2055 if (dmub_rb_full(rb)) 2056 return false; 2057 2058 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2059 2060 rb->wrpt += DMUB_RB_CMD_SIZE; 2061 2062 if (rb->wrpt >= rb->capacity) 2063 rb->wrpt %= rb->capacity; 2064 2065 return true; 2066 } 2067 2068 /** 2069 * @brief Returns the next unprocessed command in the ringbuffer. 2070 * 2071 * @param rb DMUB ringbuffer 2072 * @param cmd The command to return 2073 * @return true if not empty 2074 * @return false otherwise 2075 */ 2076 static inline bool dmub_rb_front(struct dmub_rb *rb, 2077 union dmub_rb_cmd **cmd) 2078 { 2079 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2080 2081 if (dmub_rb_empty(rb)) 2082 return false; 2083 2084 *cmd = (union dmub_rb_cmd *)rb_cmd; 2085 2086 return true; 2087 } 2088 2089 /** 2090 * @brief Returns the next unprocessed command in the outbox. 2091 * 2092 * @param rb DMUB outbox ringbuffer 2093 * @param cmd The outbox command to return 2094 * @return true if not empty 2095 * @return false otherwise 2096 */ 2097 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2098 union dmub_rb_out_cmd *cmd) 2099 { 2100 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 2101 uint64_t *dst = (uint64_t *)cmd; 2102 uint8_t i; 2103 2104 if (dmub_rb_empty(rb)) 2105 return false; 2106 2107 // copying data 2108 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2109 *dst++ = *src++; 2110 2111 return true; 2112 } 2113 2114 /** 2115 * @brief Removes the front entry in the ringbuffer. 2116 * 2117 * @param rb DMUB ringbuffer 2118 * @return true if the command was removed 2119 * @return false if there were no commands 2120 */ 2121 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 2122 { 2123 if (dmub_rb_empty(rb)) 2124 return false; 2125 2126 rb->rptr += DMUB_RB_CMD_SIZE; 2127 2128 if (rb->rptr >= rb->capacity) 2129 rb->rptr %= rb->capacity; 2130 2131 return true; 2132 } 2133 2134 /** 2135 * @brief Flushes commands in the ringbuffer to framebuffer memory. 2136 * 2137 * Avoids a race condition where DMCUB accesses memory while 2138 * there are still writes in flight to framebuffer. 2139 * 2140 * @param rb DMUB ringbuffer 2141 */ 2142 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 2143 { 2144 uint32_t rptr = rb->rptr; 2145 uint32_t wptr = rb->wrpt; 2146 2147 while (rptr != wptr) { 2148 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 2149 uint8_t i; 2150 2151 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2152 *data++; 2153 2154 rptr += DMUB_RB_CMD_SIZE; 2155 if (rptr >= rb->capacity) 2156 rptr %= rb->capacity; 2157 } 2158 } 2159 2160 /** 2161 * @brief Initializes a DMCUB ringbuffer 2162 * 2163 * @param rb DMUB ringbuffer 2164 * @param init_params initial configuration for the ringbuffer 2165 */ 2166 static inline void dmub_rb_init(struct dmub_rb *rb, 2167 struct dmub_rb_init_params *init_params) 2168 { 2169 rb->base_address = init_params->base_address; 2170 rb->capacity = init_params->capacity; 2171 rb->rptr = init_params->read_ptr; 2172 rb->wrpt = init_params->write_ptr; 2173 } 2174 2175 /** 2176 * @brief Copies output data from in/out commands into the given command. 2177 * 2178 * @param rb DMUB ringbuffer 2179 * @param cmd Command to copy data into 2180 */ 2181 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 2182 union dmub_rb_cmd *cmd) 2183 { 2184 // Copy rb entry back into command 2185 uint8_t *rd_ptr = (rb->rptr == 0) ? 2186 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 2187 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 2188 2189 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 2190 } 2191 2192 #if defined(__cplusplus) 2193 } 2194 #endif 2195 2196 //============================================================================== 2197 //</DMUB_RB>==================================================================== 2198 //============================================================================== 2199 2200 #endif /* _DMUB_CMD_H_ */ 2201