1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 /* Firmware versioning. */ 48 #ifdef DMUB_EXPOSE_VERSION 49 #define DMUB_FW_VERSION_GIT_HASH 0x1288a7b7 50 #define DMUB_FW_VERSION_MAJOR 0 51 #define DMUB_FW_VERSION_MINOR 0 52 #define DMUB_FW_VERSION_REVISION 101 53 #define DMUB_FW_VERSION_TEST 0 54 #define DMUB_FW_VERSION_VBIOS 0 55 #define DMUB_FW_VERSION_HOTFIX 0 56 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 57 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 58 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 59 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 60 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 61 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 62 63 #endif 64 65 //<DMUB_TYPES>================================================================== 66 /* Basic type definitions. */ 67 68 #define __forceinline inline 69 70 /** 71 * Flag from driver to indicate that ABM should be disabled gradually 72 * by slowly reversing all backlight programming and pixel compensation. 73 */ 74 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 75 76 /** 77 * Flag from driver to indicate that ABM should be disabled immediately 78 * and undo all backlight programming and pixel compensation. 79 */ 80 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 81 82 /** 83 * Flag from driver to indicate that ABM should be disabled immediately 84 * and keep the current backlight programming and pixel compensation. 85 */ 86 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 87 88 /** 89 * Flag from driver to set the current ABM pipe index or ABM operating level. 90 */ 91 #define SET_ABM_PIPE_NORMAL 1 92 93 /** 94 * Number of ambient light levels in ABM algorithm. 95 */ 96 #define NUM_AMBI_LEVEL 5 97 98 /** 99 * Number of operating/aggression levels in ABM algorithm. 100 */ 101 #define NUM_AGGR_LEVEL 4 102 103 /** 104 * Number of segments in the gamma curve. 105 */ 106 #define NUM_POWER_FN_SEGS 8 107 108 /** 109 * Number of segments in the backlight curve. 110 */ 111 #define NUM_BL_CURVE_SEGS 16 112 113 /* Maximum number of streams on any ASIC. */ 114 #define DMUB_MAX_STREAMS 6 115 116 /* Maximum number of planes on any ASIC. */ 117 #define DMUB_MAX_PLANES 6 118 119 /* Trace buffer offset for entry */ 120 #define TRACE_BUFFER_ENTRY_OFFSET 16 121 122 /** 123 * 124 * PSR control version legacy 125 */ 126 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 127 /** 128 * PSR control version with multi edp support 129 */ 130 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 131 132 133 /** 134 * ABM control version legacy 135 */ 136 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 137 138 /** 139 * ABM control version with multi edp support 140 */ 141 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 142 143 /** 144 * Physical framebuffer address location, 64-bit. 145 */ 146 #ifndef PHYSICAL_ADDRESS_LOC 147 #define PHYSICAL_ADDRESS_LOC union large_integer 148 #endif 149 150 /** 151 * OS/FW agnostic memcpy 152 */ 153 #ifndef dmub_memcpy 154 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 155 #endif 156 157 /** 158 * OS/FW agnostic memset 159 */ 160 #ifndef dmub_memset 161 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 162 #endif 163 164 #if defined(__cplusplus) 165 extern "C" { 166 #endif 167 168 /** 169 * OS/FW agnostic udelay 170 */ 171 #ifndef dmub_udelay 172 #define dmub_udelay(microseconds) udelay(microseconds) 173 #endif 174 175 /** 176 * union dmub_addr - DMUB physical/virtual 64-bit address. 177 */ 178 union dmub_addr { 179 struct { 180 uint32_t low_part; /**< Lower 32 bits */ 181 uint32_t high_part; /**< Upper 32 bits */ 182 } u; /*<< Low/high bit access */ 183 uint64_t quad_part; /*<< 64 bit address */ 184 }; 185 186 /** 187 * Flags that can be set by driver to change some PSR behaviour. 188 */ 189 union dmub_psr_debug_flags { 190 /** 191 * Debug flags. 192 */ 193 struct { 194 /** 195 * Enable visual confirm in FW. 196 */ 197 uint32_t visual_confirm : 1; 198 /** 199 * Use HW Lock Mgr object to do HW locking in FW. 200 */ 201 uint32_t use_hw_lock_mgr : 1; 202 203 /** 204 * Use TPS3 signal when restore main link. 205 */ 206 uint32_t force_wakeup_by_tps3 : 1; 207 } bitfields; 208 209 /** 210 * Union for debug flags. 211 */ 212 uint32_t u32All; 213 }; 214 215 /** 216 * DMUB feature capabilities. 217 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 218 */ 219 struct dmub_feature_caps { 220 /** 221 * Max PSR version supported by FW. 222 */ 223 uint8_t psr; 224 uint8_t reserved[7]; 225 }; 226 227 #if defined(__cplusplus) 228 } 229 #endif 230 231 //============================================================================== 232 //</DMUB_TYPES>================================================================= 233 //============================================================================== 234 //< DMUB_META>================================================================== 235 //============================================================================== 236 #pragma pack(push, 1) 237 238 /* Magic value for identifying dmub_fw_meta_info */ 239 #define DMUB_FW_META_MAGIC 0x444D5542 240 241 /* Offset from the end of the file to the dmub_fw_meta_info */ 242 #define DMUB_FW_META_OFFSET 0x24 243 244 /** 245 * struct dmub_fw_meta_info - metadata associated with fw binary 246 * 247 * NOTE: This should be considered a stable API. Fields should 248 * not be repurposed or reordered. New fields should be 249 * added instead to extend the structure. 250 * 251 * @magic_value: magic value identifying DMUB firmware meta info 252 * @fw_region_size: size of the firmware state region 253 * @trace_buffer_size: size of the tracebuffer region 254 * @fw_version: the firmware version information 255 * @dal_fw: 1 if the firmware is DAL 256 */ 257 struct dmub_fw_meta_info { 258 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 259 uint32_t fw_region_size; /**< size of the firmware state region */ 260 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 261 uint32_t fw_version; /**< the firmware version information */ 262 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 263 uint8_t reserved[3]; /**< padding bits */ 264 }; 265 266 /** 267 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 268 */ 269 union dmub_fw_meta { 270 struct dmub_fw_meta_info info; /**< metadata info */ 271 uint8_t reserved[64]; /**< padding bits */ 272 }; 273 274 #pragma pack(pop) 275 276 //============================================================================== 277 //< DMUB Trace Buffer>================================================================ 278 //============================================================================== 279 /** 280 * dmub_trace_code_t - firmware trace code, 32-bits 281 */ 282 typedef uint32_t dmub_trace_code_t; 283 284 /** 285 * struct dmcub_trace_buf_entry - Firmware trace entry 286 */ 287 struct dmcub_trace_buf_entry { 288 dmub_trace_code_t trace_code; /**< trace code for the event */ 289 uint32_t tick_count; /**< the tick count at time of trace */ 290 uint32_t param0; /**< trace defined parameter 0 */ 291 uint32_t param1; /**< trace defined parameter 1 */ 292 }; 293 294 //============================================================================== 295 //< DMUB_STATUS>================================================================ 296 //============================================================================== 297 298 /** 299 * DMCUB scratch registers can be used to determine firmware status. 300 * Current scratch register usage is as follows: 301 * 302 * SCRATCH0: FW Boot Status register 303 * SCRATCH5: LVTMA Status Register 304 * SCRATCH15: FW Boot Options register 305 */ 306 307 /** 308 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 309 */ 310 union dmub_fw_boot_status { 311 struct { 312 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 313 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 314 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 315 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 316 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 317 uint32_t reserved : 1; 318 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 319 320 } bits; /**< status bits */ 321 uint32_t all; /**< 32-bit access to status bits */ 322 }; 323 324 /** 325 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 326 */ 327 enum dmub_fw_boot_status_bit { 328 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 329 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 330 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 331 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 332 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 333 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 334 }; 335 336 /* Register bit definition for SCRATCH5 */ 337 union dmub_lvtma_status { 338 struct { 339 uint32_t psp_ok : 1; 340 uint32_t edp_on : 1; 341 uint32_t reserved : 30; 342 } bits; 343 uint32_t all; 344 }; 345 346 enum dmub_lvtma_status_bit { 347 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 348 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 349 }; 350 351 /** 352 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 353 */ 354 union dmub_fw_boot_options { 355 struct { 356 uint32_t pemu_env : 1; /**< 1 if PEMU */ 357 uint32_t fpga_env : 1; /**< 1 if FPGA */ 358 uint32_t optimized_init : 1; /**< 1 if optimized init */ 359 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 360 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 361 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 362 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 363 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 364 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 365 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 366 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 367 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 368 uint32_t power_optimization: 1; 369 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 370 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 371 372 uint32_t reserved : 18; /**< reserved */ 373 } bits; /**< boot bits */ 374 uint32_t all; /**< 32-bit access to bits */ 375 }; 376 377 enum dmub_fw_boot_options_bit { 378 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 379 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 380 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 381 }; 382 383 //============================================================================== 384 //</DMUB_STATUS>================================================================ 385 //============================================================================== 386 //< DMUB_VBIOS>================================================================= 387 //============================================================================== 388 389 /* 390 * enum dmub_cmd_vbios_type - VBIOS commands. 391 * 392 * Command IDs should be treated as stable ABI. 393 * Do not reuse or modify IDs. 394 */ 395 enum dmub_cmd_vbios_type { 396 /** 397 * Configures the DIG encoder. 398 */ 399 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 400 /** 401 * Controls the PHY. 402 */ 403 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 404 /** 405 * Sets the pixel clock/symbol clock. 406 */ 407 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 408 /** 409 * Enables or disables power gating. 410 */ 411 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 412 /** 413 * Controls embedded panels. 414 */ 415 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 416 /** 417 * Query DP alt status on a transmitter. 418 */ 419 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 420 }; 421 422 //============================================================================== 423 //</DMUB_VBIOS>================================================================= 424 //============================================================================== 425 //< DMUB_GPINT>================================================================= 426 //============================================================================== 427 428 /** 429 * The shifts and masks below may alternatively be used to format and read 430 * the command register bits. 431 */ 432 433 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 434 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 435 436 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 437 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 438 439 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 440 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 441 442 /** 443 * Command responses. 444 */ 445 446 /** 447 * Return response for DMUB_GPINT__STOP_FW command. 448 */ 449 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 450 451 /** 452 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 453 */ 454 union dmub_gpint_data_register { 455 struct { 456 uint32_t param : 16; /**< 16-bit parameter */ 457 uint32_t command_code : 12; /**< GPINT command */ 458 uint32_t status : 4; /**< Command status bit */ 459 } bits; /**< GPINT bit access */ 460 uint32_t all; /**< GPINT 32-bit access */ 461 }; 462 463 /* 464 * enum dmub_gpint_command - GPINT command to DMCUB FW 465 * 466 * Command IDs should be treated as stable ABI. 467 * Do not reuse or modify IDs. 468 */ 469 enum dmub_gpint_command { 470 /** 471 * Invalid command, ignored. 472 */ 473 DMUB_GPINT__INVALID_COMMAND = 0, 474 /** 475 * DESC: Queries the firmware version. 476 * RETURN: Firmware version. 477 */ 478 DMUB_GPINT__GET_FW_VERSION = 1, 479 /** 480 * DESC: Halts the firmware. 481 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 482 */ 483 DMUB_GPINT__STOP_FW = 2, 484 /** 485 * DESC: Get PSR state from FW. 486 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 487 */ 488 DMUB_GPINT__GET_PSR_STATE = 7, 489 /** 490 * DESC: Notifies DMCUB of the currently active streams. 491 * ARGS: Stream mask, 1 bit per active stream index. 492 */ 493 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 494 /** 495 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 496 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 497 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 498 * RETURN: PSR residency in milli-percent. 499 */ 500 DMUB_GPINT__PSR_RESIDENCY = 9, 501 502 /** 503 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 504 */ 505 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 506 }; 507 508 /** 509 * INBOX0 generic command definition 510 */ 511 union dmub_inbox0_cmd_common { 512 struct { 513 uint32_t command_code: 8; /**< INBOX0 command code */ 514 uint32_t param: 24; /**< 24-bit parameter */ 515 } bits; 516 uint32_t all; 517 }; 518 519 /** 520 * INBOX0 hw_lock command definition 521 */ 522 union dmub_inbox0_cmd_lock_hw { 523 struct { 524 uint32_t command_code: 8; 525 526 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 527 uint32_t hw_lock_client: 1; 528 529 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 530 uint32_t otg_inst: 3; 531 uint32_t opp_inst: 3; 532 uint32_t dig_inst: 3; 533 534 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 535 uint32_t lock_pipe: 1; 536 uint32_t lock_cursor: 1; 537 uint32_t lock_dig: 1; 538 uint32_t triple_buffer_lock: 1; 539 540 uint32_t lock: 1; /**< Lock */ 541 uint32_t should_release: 1; /**< Release */ 542 uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ 543 } bits; 544 uint32_t all; 545 }; 546 547 union dmub_inbox0_data_register { 548 union dmub_inbox0_cmd_common inbox0_cmd_common; 549 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 550 }; 551 552 enum dmub_inbox0_command { 553 /** 554 * DESC: Invalid command, ignored. 555 */ 556 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 557 /** 558 * DESC: Notification to acquire/release HW lock 559 * ARGS: 560 */ 561 DMUB_INBOX0_CMD__HW_LOCK = 1, 562 }; 563 //============================================================================== 564 //</DMUB_GPINT>================================================================= 565 //============================================================================== 566 //< DMUB_CMD>=================================================================== 567 //============================================================================== 568 569 /** 570 * Size in bytes of each DMUB command. 571 */ 572 #define DMUB_RB_CMD_SIZE 64 573 574 /** 575 * Maximum number of items in the DMUB ringbuffer. 576 */ 577 #define DMUB_RB_MAX_ENTRY 128 578 579 /** 580 * Ringbuffer size in bytes. 581 */ 582 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 583 584 /** 585 * REG_SET mask for reg offload. 586 */ 587 #define REG_SET_MASK 0xFFFF 588 589 /* 590 * enum dmub_cmd_type - DMUB inbox command. 591 * 592 * Command IDs should be treated as stable ABI. 593 * Do not reuse or modify IDs. 594 */ 595 enum dmub_cmd_type { 596 /** 597 * Invalid command. 598 */ 599 DMUB_CMD__NULL = 0, 600 /** 601 * Read modify write register sequence offload. 602 */ 603 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 604 /** 605 * Field update register sequence offload. 606 */ 607 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 608 /** 609 * Burst write sequence offload. 610 */ 611 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 612 /** 613 * Reg wait sequence offload. 614 */ 615 DMUB_CMD__REG_REG_WAIT = 4, 616 /** 617 * Workaround to avoid HUBP underflow during NV12 playback. 618 */ 619 DMUB_CMD__PLAT_54186_WA = 5, 620 /** 621 * Command type used to query FW feature caps. 622 */ 623 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 624 /** 625 * Command type used for all PSR commands. 626 */ 627 DMUB_CMD__PSR = 64, 628 /** 629 * Command type used for all MALL commands. 630 */ 631 DMUB_CMD__MALL = 65, 632 /** 633 * Command type used for all ABM commands. 634 */ 635 DMUB_CMD__ABM = 66, 636 /** 637 * Command type used for HW locking in FW. 638 */ 639 DMUB_CMD__HW_LOCK = 69, 640 /** 641 * Command type used to access DP AUX. 642 */ 643 DMUB_CMD__DP_AUX_ACCESS = 70, 644 /** 645 * Command type used for OUTBOX1 notification enable 646 */ 647 DMUB_CMD__OUTBOX1_ENABLE = 71, 648 649 /** 650 * Command type used for all idle optimization commands. 651 */ 652 DMUB_CMD__IDLE_OPT = 72, 653 /** 654 * Command type used for all clock manager commands. 655 */ 656 DMUB_CMD__CLK_MGR = 73, 657 /** 658 * Command type used for all panel control commands. 659 */ 660 DMUB_CMD__PANEL_CNTL = 74, 661 662 /** 663 * Command type used for interfacing with DPIA. 664 */ 665 DMUB_CMD__DPIA = 77, 666 /** 667 * Command type used for EDID CEA parsing 668 */ 669 DMUB_CMD__EDID_CEA = 79, 670 /** 671 * Command type used for all VBIOS interface commands. 672 */ 673 DMUB_CMD__VBIOS = 128, 674 }; 675 676 /** 677 * enum dmub_out_cmd_type - DMUB outbox commands. 678 */ 679 enum dmub_out_cmd_type { 680 /** 681 * Invalid outbox command, ignored. 682 */ 683 DMUB_OUT_CMD__NULL = 0, 684 /** 685 * Command type used for DP AUX Reply data notification 686 */ 687 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 688 /** 689 * Command type used for DP HPD event notification 690 */ 691 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 692 /** 693 * Command type used for SET_CONFIG Reply notification 694 */ 695 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 696 }; 697 698 /* DMUB_CMD__DPIA command sub-types. */ 699 enum dmub_cmd_dpia_type { 700 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 701 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 702 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 703 }; 704 705 #pragma pack(push, 1) 706 707 /** 708 * struct dmub_cmd_header - Common command header fields. 709 */ 710 struct dmub_cmd_header { 711 unsigned int type : 8; /**< command type */ 712 unsigned int sub_type : 8; /**< command sub type */ 713 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 714 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 715 unsigned int reserved0 : 6; /**< reserved bits */ 716 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 717 unsigned int reserved1 : 2; /**< reserved bits */ 718 }; 719 720 /* 721 * struct dmub_cmd_read_modify_write_sequence - Read modify write 722 * 723 * 60 payload bytes can hold up to 5 sets of read modify writes, 724 * each take 3 dwords. 725 * 726 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 727 * 728 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 729 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 730 */ 731 struct dmub_cmd_read_modify_write_sequence { 732 uint32_t addr; /**< register address */ 733 uint32_t modify_mask; /**< modify mask */ 734 uint32_t modify_value; /**< modify value */ 735 }; 736 737 /** 738 * Maximum number of ops in read modify write sequence. 739 */ 740 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 741 742 /** 743 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 744 */ 745 struct dmub_rb_cmd_read_modify_write { 746 struct dmub_cmd_header header; /**< command header */ 747 /** 748 * Read modify write sequence. 749 */ 750 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 751 }; 752 753 /* 754 * Update a register with specified masks and values sequeunce 755 * 756 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 757 * 758 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 759 * 760 * 761 * USE CASE: 762 * 1. auto-increment register where additional read would update pointer and produce wrong result 763 * 2. toggle a bit without read in the middle 764 */ 765 766 struct dmub_cmd_reg_field_update_sequence { 767 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 768 uint32_t modify_value; /**< value to update with */ 769 }; 770 771 /** 772 * Maximum number of ops in field update sequence. 773 */ 774 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 775 776 /** 777 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 778 */ 779 struct dmub_rb_cmd_reg_field_update_sequence { 780 struct dmub_cmd_header header; /**< command header */ 781 uint32_t addr; /**< register address */ 782 /** 783 * Field update sequence. 784 */ 785 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 786 }; 787 788 789 /** 790 * Maximum number of burst write values. 791 */ 792 #define DMUB_BURST_WRITE_VALUES__MAX 14 793 794 /* 795 * struct dmub_rb_cmd_burst_write - Burst write 796 * 797 * support use case such as writing out LUTs. 798 * 799 * 60 payload bytes can hold up to 14 values to write to given address 800 * 801 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 802 */ 803 struct dmub_rb_cmd_burst_write { 804 struct dmub_cmd_header header; /**< command header */ 805 uint32_t addr; /**< register start address */ 806 /** 807 * Burst write register values. 808 */ 809 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 810 }; 811 812 /** 813 * struct dmub_rb_cmd_common - Common command header 814 */ 815 struct dmub_rb_cmd_common { 816 struct dmub_cmd_header header; /**< command header */ 817 /** 818 * Padding to RB_CMD_SIZE 819 */ 820 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 821 }; 822 823 /** 824 * struct dmub_cmd_reg_wait_data - Register wait data 825 */ 826 struct dmub_cmd_reg_wait_data { 827 uint32_t addr; /**< Register address */ 828 uint32_t mask; /**< Mask for register bits */ 829 uint32_t condition_field_value; /**< Value to wait for */ 830 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 831 }; 832 833 /** 834 * struct dmub_rb_cmd_reg_wait - Register wait command 835 */ 836 struct dmub_rb_cmd_reg_wait { 837 struct dmub_cmd_header header; /**< Command header */ 838 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 839 }; 840 841 /** 842 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 843 * 844 * Reprograms surface parameters to avoid underflow. 845 */ 846 struct dmub_cmd_PLAT_54186_wa { 847 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 848 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 849 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 850 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 851 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 852 struct { 853 uint8_t hubp_inst : 4; /**< HUBP instance */ 854 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 855 uint8_t immediate :1; /**< Immediate flip */ 856 uint8_t vmid : 4; /**< VMID */ 857 uint8_t grph_stereo : 1; /**< 1 if stereo */ 858 uint32_t reserved : 21; /**< Reserved */ 859 } flip_params; /**< Pageflip parameters */ 860 uint32_t reserved[9]; /**< Reserved bits */ 861 }; 862 863 /** 864 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 865 */ 866 struct dmub_rb_cmd_PLAT_54186_wa { 867 struct dmub_cmd_header header; /**< Command header */ 868 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 869 }; 870 871 /** 872 * struct dmub_rb_cmd_mall - MALL command data. 873 */ 874 struct dmub_rb_cmd_mall { 875 struct dmub_cmd_header header; /**< Common command header */ 876 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 877 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 878 uint32_t tmr_delay; /**< Timer delay */ 879 uint32_t tmr_scale; /**< Timer scale */ 880 uint16_t cursor_width; /**< Cursor width in pixels */ 881 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 882 uint16_t cursor_height; /**< Cursor height in pixels */ 883 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 884 uint8_t debug_bits; /**< Debug bits */ 885 886 uint8_t reserved1; /**< Reserved bits */ 887 uint8_t reserved2; /**< Reserved bits */ 888 }; 889 890 /** 891 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 892 */ 893 enum dmub_cmd_idle_opt_type { 894 /** 895 * DCN hardware restore. 896 */ 897 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 898 899 /** 900 * DCN hardware save. 901 */ 902 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 903 }; 904 905 /** 906 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 907 */ 908 struct dmub_rb_cmd_idle_opt_dcn_restore { 909 struct dmub_cmd_header header; /**< header */ 910 }; 911 912 /** 913 * struct dmub_clocks - Clock update notification. 914 */ 915 struct dmub_clocks { 916 uint32_t dispclk_khz; /**< dispclk kHz */ 917 uint32_t dppclk_khz; /**< dppclk kHz */ 918 uint32_t dcfclk_khz; /**< dcfclk kHz */ 919 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 920 }; 921 922 /** 923 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 924 */ 925 enum dmub_cmd_clk_mgr_type { 926 /** 927 * Notify DMCUB of clock update. 928 */ 929 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 930 }; 931 932 /** 933 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 934 */ 935 struct dmub_rb_cmd_clk_mgr_notify_clocks { 936 struct dmub_cmd_header header; /**< header */ 937 struct dmub_clocks clocks; /**< clock data */ 938 }; 939 940 /** 941 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 942 */ 943 struct dmub_cmd_digx_encoder_control_data { 944 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 945 }; 946 947 /** 948 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 949 */ 950 struct dmub_rb_cmd_digx_encoder_control { 951 struct dmub_cmd_header header; /**< header */ 952 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 953 }; 954 955 /** 956 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 957 */ 958 struct dmub_cmd_set_pixel_clock_data { 959 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 960 }; 961 962 /** 963 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 964 */ 965 struct dmub_rb_cmd_set_pixel_clock { 966 struct dmub_cmd_header header; /**< header */ 967 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 968 }; 969 970 /** 971 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 972 */ 973 struct dmub_cmd_enable_disp_power_gating_data { 974 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 975 }; 976 977 /** 978 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 979 */ 980 struct dmub_rb_cmd_enable_disp_power_gating { 981 struct dmub_cmd_header header; /**< header */ 982 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 983 }; 984 985 /** 986 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 987 */ 988 struct dmub_dig_transmitter_control_data_v1_7 { 989 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 990 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 991 union { 992 uint8_t digmode; /**< enum atom_encode_mode_def */ 993 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 994 } mode_laneset; 995 uint8_t lanenum; /**< Number of lanes */ 996 union { 997 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 998 } symclk_units; 999 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1000 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1001 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1002 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1003 uint8_t reserved1; /**< For future use */ 1004 uint8_t reserved2[3]; /**< For future use */ 1005 uint32_t reserved3[11]; /**< For future use */ 1006 }; 1007 1008 /** 1009 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1010 */ 1011 union dmub_cmd_dig1_transmitter_control_data { 1012 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1013 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1014 }; 1015 1016 /** 1017 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1018 */ 1019 struct dmub_rb_cmd_dig1_transmitter_control { 1020 struct dmub_cmd_header header; /**< header */ 1021 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1022 }; 1023 1024 /** 1025 * DPIA tunnel command parameters. 1026 */ 1027 struct dmub_cmd_dig_dpia_control_data { 1028 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1029 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1030 union { 1031 uint8_t digmode; /** enum atom_encode_mode_def */ 1032 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1033 } mode_laneset; 1034 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1035 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1036 uint8_t hpdsel; /** =0: HPD is not assigned */ 1037 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1038 uint8_t dpia_id; /** Index of DPIA */ 1039 uint8_t fec_rdy : 1; 1040 uint8_t reserved : 7; 1041 uint32_t reserved1; 1042 }; 1043 1044 /** 1045 * DMUB command for DPIA tunnel control. 1046 */ 1047 struct dmub_rb_cmd_dig1_dpia_control { 1048 struct dmub_cmd_header header; 1049 struct dmub_cmd_dig_dpia_control_data dpia_control; 1050 }; 1051 1052 /** 1053 * SET_CONFIG Command Payload 1054 */ 1055 struct set_config_cmd_payload { 1056 uint8_t msg_type; /* set config message type */ 1057 uint8_t msg_data; /* set config message data */ 1058 }; 1059 1060 /** 1061 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1062 */ 1063 struct dmub_cmd_set_config_control_data { 1064 struct set_config_cmd_payload cmd_pkt; 1065 uint8_t instance; /* DPIA instance */ 1066 uint8_t immed_status; /* Immediate status returned in case of error */ 1067 }; 1068 1069 /** 1070 * DMUB command structure for SET_CONFIG command. 1071 */ 1072 struct dmub_rb_cmd_set_config_access { 1073 struct dmub_cmd_header header; /* header */ 1074 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1075 }; 1076 1077 /** 1078 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1079 */ 1080 struct dmub_cmd_mst_alloc_slots_control_data { 1081 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1082 uint8_t instance; /* DPIA instance */ 1083 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1084 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1085 }; 1086 1087 /** 1088 * DMUB command structure for SET_ command. 1089 */ 1090 struct dmub_rb_cmd_set_mst_alloc_slots { 1091 struct dmub_cmd_header header; /* header */ 1092 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1093 }; 1094 1095 /** 1096 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1097 */ 1098 struct dmub_rb_cmd_dpphy_init { 1099 struct dmub_cmd_header header; /**< header */ 1100 uint8_t reserved[60]; /**< reserved bits */ 1101 }; 1102 1103 /** 1104 * enum dp_aux_request_action - DP AUX request command listing. 1105 * 1106 * 4 AUX request command bits are shifted to high nibble. 1107 */ 1108 enum dp_aux_request_action { 1109 /** I2C-over-AUX write request */ 1110 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1111 /** I2C-over-AUX read request */ 1112 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1113 /** I2C-over-AUX write status request */ 1114 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1115 /** I2C-over-AUX write request with MOT=1 */ 1116 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1117 /** I2C-over-AUX read request with MOT=1 */ 1118 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1119 /** I2C-over-AUX write status request with MOT=1 */ 1120 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1121 /** Native AUX write request */ 1122 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1123 /** Native AUX read request */ 1124 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1125 }; 1126 1127 /** 1128 * enum aux_return_code_type - DP AUX process return code listing. 1129 */ 1130 enum aux_return_code_type { 1131 /** AUX process succeeded */ 1132 AUX_RET_SUCCESS = 0, 1133 /** AUX process failed with unknown reason */ 1134 AUX_RET_ERROR_UNKNOWN, 1135 /** AUX process completed with invalid reply */ 1136 AUX_RET_ERROR_INVALID_REPLY, 1137 /** AUX process timed out */ 1138 AUX_RET_ERROR_TIMEOUT, 1139 /** HPD was low during AUX process */ 1140 AUX_RET_ERROR_HPD_DISCON, 1141 /** Failed to acquire AUX engine */ 1142 AUX_RET_ERROR_ENGINE_ACQUIRE, 1143 /** AUX request not supported */ 1144 AUX_RET_ERROR_INVALID_OPERATION, 1145 /** AUX process not available */ 1146 AUX_RET_ERROR_PROTOCOL_ERROR, 1147 }; 1148 1149 /** 1150 * enum aux_channel_type - DP AUX channel type listing. 1151 */ 1152 enum aux_channel_type { 1153 /** AUX thru Legacy DP AUX */ 1154 AUX_CHANNEL_LEGACY_DDC, 1155 /** AUX thru DPIA DP tunneling */ 1156 AUX_CHANNEL_DPIA 1157 }; 1158 1159 /** 1160 * struct aux_transaction_parameters - DP AUX request transaction data 1161 */ 1162 struct aux_transaction_parameters { 1163 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1164 uint8_t action; /**< enum dp_aux_request_action */ 1165 uint8_t length; /**< DP AUX request data length */ 1166 uint8_t reserved; /**< For future use */ 1167 uint32_t address; /**< DP AUX address */ 1168 uint8_t data[16]; /**< DP AUX write data */ 1169 }; 1170 1171 /** 1172 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1173 */ 1174 struct dmub_cmd_dp_aux_control_data { 1175 uint8_t instance; /**< AUX instance or DPIA instance */ 1176 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1177 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1178 uint8_t reserved0; /**< For future use */ 1179 uint16_t timeout; /**< timeout time in us */ 1180 uint16_t reserved1; /**< For future use */ 1181 enum aux_channel_type type; /**< enum aux_channel_type */ 1182 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1183 }; 1184 1185 /** 1186 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1187 */ 1188 struct dmub_rb_cmd_dp_aux_access { 1189 /** 1190 * Command header. 1191 */ 1192 struct dmub_cmd_header header; 1193 /** 1194 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1195 */ 1196 struct dmub_cmd_dp_aux_control_data aux_control; 1197 }; 1198 1199 /** 1200 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1201 */ 1202 struct dmub_rb_cmd_outbox1_enable { 1203 /** 1204 * Command header. 1205 */ 1206 struct dmub_cmd_header header; 1207 /** 1208 * enable: 0x0 -> disable outbox1 notification (default value) 1209 * 0x1 -> enable outbox1 notification 1210 */ 1211 uint32_t enable; 1212 }; 1213 1214 /* DP AUX Reply command - OutBox Cmd */ 1215 /** 1216 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1217 */ 1218 struct aux_reply_data { 1219 /** 1220 * Aux cmd 1221 */ 1222 uint8_t command; 1223 /** 1224 * Aux reply data length (max: 16 bytes) 1225 */ 1226 uint8_t length; 1227 /** 1228 * Alignment only 1229 */ 1230 uint8_t pad[2]; 1231 /** 1232 * Aux reply data 1233 */ 1234 uint8_t data[16]; 1235 }; 1236 1237 /** 1238 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1239 */ 1240 struct aux_reply_control_data { 1241 /** 1242 * Reserved for future use 1243 */ 1244 uint32_t handle; 1245 /** 1246 * Aux Instance 1247 */ 1248 uint8_t instance; 1249 /** 1250 * Aux transaction result: definition in enum aux_return_code_type 1251 */ 1252 uint8_t result; 1253 /** 1254 * Alignment only 1255 */ 1256 uint16_t pad; 1257 }; 1258 1259 /** 1260 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1261 */ 1262 struct dmub_rb_cmd_dp_aux_reply { 1263 /** 1264 * Command header. 1265 */ 1266 struct dmub_cmd_header header; 1267 /** 1268 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1269 */ 1270 struct aux_reply_control_data control; 1271 /** 1272 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1273 */ 1274 struct aux_reply_data reply_data; 1275 }; 1276 1277 /* DP HPD Notify command - OutBox Cmd */ 1278 /** 1279 * DP HPD Type 1280 */ 1281 enum dp_hpd_type { 1282 /** 1283 * Normal DP HPD 1284 */ 1285 DP_HPD = 0, 1286 /** 1287 * DP HPD short pulse 1288 */ 1289 DP_IRQ 1290 }; 1291 1292 /** 1293 * DP HPD Status 1294 */ 1295 enum dp_hpd_status { 1296 /** 1297 * DP_HPD status low 1298 */ 1299 DP_HPD_UNPLUG = 0, 1300 /** 1301 * DP_HPD status high 1302 */ 1303 DP_HPD_PLUG 1304 }; 1305 1306 /** 1307 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1308 */ 1309 struct dp_hpd_data { 1310 /** 1311 * DP HPD instance 1312 */ 1313 uint8_t instance; 1314 /** 1315 * HPD type 1316 */ 1317 uint8_t hpd_type; 1318 /** 1319 * HPD status: only for type: DP_HPD to indicate status 1320 */ 1321 uint8_t hpd_status; 1322 /** 1323 * Alignment only 1324 */ 1325 uint8_t pad; 1326 }; 1327 1328 /** 1329 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1330 */ 1331 struct dmub_rb_cmd_dp_hpd_notify { 1332 /** 1333 * Command header. 1334 */ 1335 struct dmub_cmd_header header; 1336 /** 1337 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1338 */ 1339 struct dp_hpd_data hpd_data; 1340 }; 1341 1342 /** 1343 * Definition of a SET_CONFIG reply from DPOA. 1344 */ 1345 enum set_config_status { 1346 SET_CONFIG_PENDING = 0, 1347 SET_CONFIG_ACK_RECEIVED, 1348 SET_CONFIG_RX_TIMEOUT, 1349 SET_CONFIG_UNKNOWN_ERROR, 1350 }; 1351 1352 /** 1353 * Definition of a set_config reply 1354 */ 1355 struct set_config_reply_control_data { 1356 uint8_t instance; /* DPIA Instance */ 1357 uint8_t status; /* Set Config reply */ 1358 uint16_t pad; /* Alignment */ 1359 }; 1360 1361 /** 1362 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1363 */ 1364 struct dmub_rb_cmd_dp_set_config_reply { 1365 struct dmub_cmd_header header; 1366 struct set_config_reply_control_data set_config_reply_control; 1367 }; 1368 1369 /* 1370 * Command IDs should be treated as stable ABI. 1371 * Do not reuse or modify IDs. 1372 */ 1373 1374 /** 1375 * PSR command sub-types. 1376 */ 1377 enum dmub_cmd_psr_type { 1378 /** 1379 * Set PSR version support. 1380 */ 1381 DMUB_CMD__PSR_SET_VERSION = 0, 1382 /** 1383 * Copy driver-calculated parameters to PSR state. 1384 */ 1385 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1386 /** 1387 * Enable PSR. 1388 */ 1389 DMUB_CMD__PSR_ENABLE = 2, 1390 1391 /** 1392 * Disable PSR. 1393 */ 1394 DMUB_CMD__PSR_DISABLE = 3, 1395 1396 /** 1397 * Set PSR level. 1398 * PSR level is a 16-bit value dicated by driver that 1399 * will enable/disable different functionality. 1400 */ 1401 DMUB_CMD__PSR_SET_LEVEL = 4, 1402 1403 /** 1404 * Forces PSR enabled until an explicit PSR disable call. 1405 */ 1406 DMUB_CMD__PSR_FORCE_STATIC = 5, 1407 /** 1408 * Set PSR power option 1409 */ 1410 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1411 }; 1412 1413 /** 1414 * PSR versions. 1415 */ 1416 enum psr_version { 1417 /** 1418 * PSR version 1. 1419 */ 1420 PSR_VERSION_1 = 0, 1421 /** 1422 * PSR not supported. 1423 */ 1424 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1425 }; 1426 1427 /** 1428 * enum dmub_cmd_mall_type - MALL commands 1429 */ 1430 enum dmub_cmd_mall_type { 1431 /** 1432 * Allows display refresh from MALL. 1433 */ 1434 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1435 /** 1436 * Disallows display refresh from MALL. 1437 */ 1438 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1439 /** 1440 * Cursor copy for MALL. 1441 */ 1442 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1443 /** 1444 * Controls DF requests. 1445 */ 1446 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1447 }; 1448 1449 1450 /** 1451 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1452 */ 1453 struct dmub_cmd_psr_copy_settings_data { 1454 /** 1455 * Flags that can be set by driver to change some PSR behaviour. 1456 */ 1457 union dmub_psr_debug_flags debug; 1458 /** 1459 * 16-bit value dicated by driver that will enable/disable different functionality. 1460 */ 1461 uint16_t psr_level; 1462 /** 1463 * DPP HW instance. 1464 */ 1465 uint8_t dpp_inst; 1466 /** 1467 * MPCC HW instance. 1468 * Not used in dmub fw, 1469 * dmub fw will get active opp by reading odm registers. 1470 */ 1471 uint8_t mpcc_inst; 1472 /** 1473 * OPP HW instance. 1474 * Not used in dmub fw, 1475 * dmub fw will get active opp by reading odm registers. 1476 */ 1477 uint8_t opp_inst; 1478 /** 1479 * OTG HW instance. 1480 */ 1481 uint8_t otg_inst; 1482 /** 1483 * DIG FE HW instance. 1484 */ 1485 uint8_t digfe_inst; 1486 /** 1487 * DIG BE HW instance. 1488 */ 1489 uint8_t digbe_inst; 1490 /** 1491 * DP PHY HW instance. 1492 */ 1493 uint8_t dpphy_inst; 1494 /** 1495 * AUX HW instance. 1496 */ 1497 uint8_t aux_inst; 1498 /** 1499 * Determines if SMU optimzations are enabled/disabled. 1500 */ 1501 uint8_t smu_optimizations_en; 1502 /** 1503 * Unused. 1504 * TODO: Remove. 1505 */ 1506 uint8_t frame_delay; 1507 /** 1508 * If RFB setup time is greater than the total VBLANK time, 1509 * it is not possible for the sink to capture the video frame 1510 * in the same frame the SDP is sent. In this case, 1511 * the frame capture indication bit should be set and an extra 1512 * static frame should be transmitted to the sink. 1513 */ 1514 uint8_t frame_cap_ind; 1515 /** 1516 * Explicit padding to 4 byte boundary. 1517 */ 1518 uint8_t pad[2]; 1519 /** 1520 * Multi-display optimizations are implemented on certain ASICs. 1521 */ 1522 uint8_t multi_disp_optimizations_en; 1523 /** 1524 * The last possible line SDP may be transmitted without violating 1525 * the RFB setup time or entering the active video frame. 1526 */ 1527 uint16_t init_sdp_deadline; 1528 /** 1529 * Explicit padding to 4 byte boundary. 1530 */ 1531 uint16_t pad2; 1532 /** 1533 * Length of each horizontal line in us. 1534 */ 1535 uint32_t line_time_in_us; 1536 /** 1537 * FEC enable status in driver 1538 */ 1539 uint8_t fec_enable_status; 1540 /** 1541 * FEC re-enable delay when PSR exit. 1542 * unit is 100us, range form 0~255(0xFF). 1543 */ 1544 uint8_t fec_enable_delay_in100us; 1545 /** 1546 * PSR control version. 1547 */ 1548 uint8_t cmd_version; 1549 /** 1550 * Panel Instance. 1551 * Panel isntance to identify which psr_state to use 1552 * Currently the support is only for 0 or 1 1553 */ 1554 uint8_t panel_inst; 1555 /* 1556 * DSC enable status in driver 1557 */ 1558 uint8_t dsc_enable_status; 1559 /** 1560 * Explicit padding to 3 byte boundary. 1561 */ 1562 uint8_t pad3[3]; 1563 }; 1564 1565 /** 1566 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1567 */ 1568 struct dmub_rb_cmd_psr_copy_settings { 1569 /** 1570 * Command header. 1571 */ 1572 struct dmub_cmd_header header; 1573 /** 1574 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1575 */ 1576 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1577 }; 1578 1579 /** 1580 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1581 */ 1582 struct dmub_cmd_psr_set_level_data { 1583 /** 1584 * 16-bit value dicated by driver that will enable/disable different functionality. 1585 */ 1586 uint16_t psr_level; 1587 /** 1588 * PSR control version. 1589 */ 1590 uint8_t cmd_version; 1591 /** 1592 * Panel Instance. 1593 * Panel isntance to identify which psr_state to use 1594 * Currently the support is only for 0 or 1 1595 */ 1596 uint8_t panel_inst; 1597 }; 1598 1599 /** 1600 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1601 */ 1602 struct dmub_rb_cmd_psr_set_level { 1603 /** 1604 * Command header. 1605 */ 1606 struct dmub_cmd_header header; 1607 /** 1608 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1609 */ 1610 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1611 }; 1612 1613 struct dmub_rb_cmd_psr_enable_data { 1614 /** 1615 * PSR control version. 1616 */ 1617 uint8_t cmd_version; 1618 /** 1619 * Panel Instance. 1620 * Panel isntance to identify which psr_state to use 1621 * Currently the support is only for 0 or 1 1622 */ 1623 uint8_t panel_inst; 1624 /** 1625 * Explicit padding to 4 byte boundary. 1626 */ 1627 uint8_t pad[2]; 1628 }; 1629 1630 /** 1631 * Definition of a DMUB_CMD__PSR_ENABLE command. 1632 * PSR enable/disable is controlled using the sub_type. 1633 */ 1634 struct dmub_rb_cmd_psr_enable { 1635 /** 1636 * Command header. 1637 */ 1638 struct dmub_cmd_header header; 1639 1640 struct dmub_rb_cmd_psr_enable_data data; 1641 }; 1642 1643 /** 1644 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1645 */ 1646 struct dmub_cmd_psr_set_version_data { 1647 /** 1648 * PSR version that FW should implement. 1649 */ 1650 enum psr_version version; 1651 /** 1652 * PSR control version. 1653 */ 1654 uint8_t cmd_version; 1655 /** 1656 * Panel Instance. 1657 * Panel isntance to identify which psr_state to use 1658 * Currently the support is only for 0 or 1 1659 */ 1660 uint8_t panel_inst; 1661 /** 1662 * Explicit padding to 4 byte boundary. 1663 */ 1664 uint8_t pad[2]; 1665 }; 1666 1667 /** 1668 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1669 */ 1670 struct dmub_rb_cmd_psr_set_version { 1671 /** 1672 * Command header. 1673 */ 1674 struct dmub_cmd_header header; 1675 /** 1676 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1677 */ 1678 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1679 }; 1680 1681 struct dmub_cmd_psr_force_static_data { 1682 /** 1683 * PSR control version. 1684 */ 1685 uint8_t cmd_version; 1686 /** 1687 * Panel Instance. 1688 * Panel isntance to identify which psr_state to use 1689 * Currently the support is only for 0 or 1 1690 */ 1691 uint8_t panel_inst; 1692 /** 1693 * Explicit padding to 4 byte boundary. 1694 */ 1695 uint8_t pad[2]; 1696 }; 1697 1698 /** 1699 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1700 */ 1701 struct dmub_rb_cmd_psr_force_static { 1702 /** 1703 * Command header. 1704 */ 1705 struct dmub_cmd_header header; 1706 /** 1707 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1708 */ 1709 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1710 }; 1711 1712 /** 1713 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 1714 */ 1715 struct dmub_cmd_psr_set_power_opt_data { 1716 /** 1717 * PSR control version. 1718 */ 1719 uint8_t cmd_version; 1720 /** 1721 * Panel Instance. 1722 * Panel isntance to identify which psr_state to use 1723 * Currently the support is only for 0 or 1 1724 */ 1725 uint8_t panel_inst; 1726 /** 1727 * Explicit padding to 4 byte boundary. 1728 */ 1729 uint8_t pad[2]; 1730 /** 1731 * PSR power option 1732 */ 1733 uint32_t power_opt; 1734 }; 1735 1736 /** 1737 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1738 */ 1739 struct dmub_rb_cmd_psr_set_power_opt { 1740 /** 1741 * Command header. 1742 */ 1743 struct dmub_cmd_header header; 1744 /** 1745 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1746 */ 1747 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 1748 }; 1749 1750 /** 1751 * Set of HW components that can be locked. 1752 * 1753 * Note: If updating with more HW components, fields 1754 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1755 */ 1756 union dmub_hw_lock_flags { 1757 /** 1758 * Set of HW components that can be locked. 1759 */ 1760 struct { 1761 /** 1762 * Lock/unlock OTG master update lock. 1763 */ 1764 uint8_t lock_pipe : 1; 1765 /** 1766 * Lock/unlock cursor. 1767 */ 1768 uint8_t lock_cursor : 1; 1769 /** 1770 * Lock/unlock global update lock. 1771 */ 1772 uint8_t lock_dig : 1; 1773 /** 1774 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1775 */ 1776 uint8_t triple_buffer_lock : 1; 1777 } bits; 1778 1779 /** 1780 * Union for HW Lock flags. 1781 */ 1782 uint8_t u8All; 1783 }; 1784 1785 /** 1786 * Instances of HW to be locked. 1787 * 1788 * Note: If updating with more HW components, fields 1789 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1790 */ 1791 struct dmub_hw_lock_inst_flags { 1792 /** 1793 * OTG HW instance for OTG master update lock. 1794 */ 1795 uint8_t otg_inst; 1796 /** 1797 * OPP instance for cursor lock. 1798 */ 1799 uint8_t opp_inst; 1800 /** 1801 * OTG HW instance for global update lock. 1802 * TODO: Remove, and re-use otg_inst. 1803 */ 1804 uint8_t dig_inst; 1805 /** 1806 * Explicit pad to 4 byte boundary. 1807 */ 1808 uint8_t pad; 1809 }; 1810 1811 /** 1812 * Clients that can acquire the HW Lock Manager. 1813 * 1814 * Note: If updating with more clients, fields in 1815 * dmub_inbox0_cmd_lock_hw must be updated to match. 1816 */ 1817 enum hw_lock_client { 1818 /** 1819 * Driver is the client of HW Lock Manager. 1820 */ 1821 HW_LOCK_CLIENT_DRIVER = 0, 1822 /** 1823 * Invalid client. 1824 */ 1825 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1826 }; 1827 1828 /** 1829 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1830 */ 1831 struct dmub_cmd_lock_hw_data { 1832 /** 1833 * Specifies the client accessing HW Lock Manager. 1834 */ 1835 enum hw_lock_client client; 1836 /** 1837 * HW instances to be locked. 1838 */ 1839 struct dmub_hw_lock_inst_flags inst_flags; 1840 /** 1841 * Which components to be locked. 1842 */ 1843 union dmub_hw_lock_flags hw_locks; 1844 /** 1845 * Specifies lock/unlock. 1846 */ 1847 uint8_t lock; 1848 /** 1849 * HW can be unlocked separately from releasing the HW Lock Mgr. 1850 * This flag is set if the client wishes to release the object. 1851 */ 1852 uint8_t should_release; 1853 /** 1854 * Explicit padding to 4 byte boundary. 1855 */ 1856 uint8_t pad; 1857 }; 1858 1859 /** 1860 * Definition of a DMUB_CMD__HW_LOCK command. 1861 * Command is used by driver and FW. 1862 */ 1863 struct dmub_rb_cmd_lock_hw { 1864 /** 1865 * Command header. 1866 */ 1867 struct dmub_cmd_header header; 1868 /** 1869 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1870 */ 1871 struct dmub_cmd_lock_hw_data lock_hw_data; 1872 }; 1873 1874 /** 1875 * ABM command sub-types. 1876 */ 1877 enum dmub_cmd_abm_type { 1878 /** 1879 * Initialize parameters for ABM algorithm. 1880 * Data is passed through an indirect buffer. 1881 */ 1882 DMUB_CMD__ABM_INIT_CONFIG = 0, 1883 /** 1884 * Set OTG and panel HW instance. 1885 */ 1886 DMUB_CMD__ABM_SET_PIPE = 1, 1887 /** 1888 * Set user requested backklight level. 1889 */ 1890 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1891 /** 1892 * Set ABM operating/aggression level. 1893 */ 1894 DMUB_CMD__ABM_SET_LEVEL = 3, 1895 /** 1896 * Set ambient light level. 1897 */ 1898 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1899 /** 1900 * Enable/disable fractional duty cycle for backlight PWM. 1901 */ 1902 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1903 1904 /** 1905 * unregister vertical interrupt after steady state is reached 1906 */ 1907 DMUB_CMD__ABM_PAUSE = 6, 1908 }; 1909 1910 /** 1911 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1912 * Requirements: 1913 * - Padded explicitly to 32-bit boundary. 1914 * - Must ensure this structure matches the one on driver-side, 1915 * otherwise it won't be aligned. 1916 */ 1917 struct abm_config_table { 1918 /** 1919 * Gamma curve thresholds, used for crgb conversion. 1920 */ 1921 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1922 /** 1923 * Gamma curve offsets, used for crgb conversion. 1924 */ 1925 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1926 /** 1927 * Gamma curve slopes, used for crgb conversion. 1928 */ 1929 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1930 /** 1931 * Custom backlight curve thresholds. 1932 */ 1933 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 1934 /** 1935 * Custom backlight curve offsets. 1936 */ 1937 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 1938 /** 1939 * Ambient light thresholds. 1940 */ 1941 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 1942 /** 1943 * Minimum programmable backlight. 1944 */ 1945 uint16_t min_abm_backlight; // 122B 1946 /** 1947 * Minimum reduction values. 1948 */ 1949 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 1950 /** 1951 * Maximum reduction values. 1952 */ 1953 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 1954 /** 1955 * Bright positive gain. 1956 */ 1957 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 1958 /** 1959 * Dark negative gain. 1960 */ 1961 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 1962 /** 1963 * Hybrid factor. 1964 */ 1965 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 1966 /** 1967 * Contrast factor. 1968 */ 1969 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 1970 /** 1971 * Deviation gain. 1972 */ 1973 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 1974 /** 1975 * Minimum knee. 1976 */ 1977 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 1978 /** 1979 * Maximum knee. 1980 */ 1981 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 1982 /** 1983 * Unused. 1984 */ 1985 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 1986 /** 1987 * Explicit padding to 4 byte boundary. 1988 */ 1989 uint8_t pad3[3]; // 229B 1990 /** 1991 * Backlight ramp reduction. 1992 */ 1993 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 1994 /** 1995 * Backlight ramp start. 1996 */ 1997 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 1998 }; 1999 2000 /** 2001 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2002 */ 2003 struct dmub_cmd_abm_set_pipe_data { 2004 /** 2005 * OTG HW instance. 2006 */ 2007 uint8_t otg_inst; 2008 2009 /** 2010 * Panel Control HW instance. 2011 */ 2012 uint8_t panel_inst; 2013 2014 /** 2015 * Controls how ABM will interpret a set pipe or set level command. 2016 */ 2017 uint8_t set_pipe_option; 2018 2019 /** 2020 * Unused. 2021 * TODO: Remove. 2022 */ 2023 uint8_t ramping_boundary; 2024 }; 2025 2026 /** 2027 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2028 */ 2029 struct dmub_rb_cmd_abm_set_pipe { 2030 /** 2031 * Command header. 2032 */ 2033 struct dmub_cmd_header header; 2034 2035 /** 2036 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2037 */ 2038 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2039 }; 2040 2041 /** 2042 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2043 */ 2044 struct dmub_cmd_abm_set_backlight_data { 2045 /** 2046 * Number of frames to ramp to backlight user level. 2047 */ 2048 uint32_t frame_ramp; 2049 2050 /** 2051 * Requested backlight level from user. 2052 */ 2053 uint32_t backlight_user_level; 2054 2055 /** 2056 * ABM control version. 2057 */ 2058 uint8_t version; 2059 2060 /** 2061 * Panel Control HW instance mask. 2062 * Bit 0 is Panel Control HW instance 0. 2063 * Bit 1 is Panel Control HW instance 1. 2064 */ 2065 uint8_t panel_mask; 2066 2067 /** 2068 * Explicit padding to 4 byte boundary. 2069 */ 2070 uint8_t pad[2]; 2071 }; 2072 2073 /** 2074 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2075 */ 2076 struct dmub_rb_cmd_abm_set_backlight { 2077 /** 2078 * Command header. 2079 */ 2080 struct dmub_cmd_header header; 2081 2082 /** 2083 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2084 */ 2085 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2086 }; 2087 2088 /** 2089 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2090 */ 2091 struct dmub_cmd_abm_set_level_data { 2092 /** 2093 * Set current ABM operating/aggression level. 2094 */ 2095 uint32_t level; 2096 2097 /** 2098 * ABM control version. 2099 */ 2100 uint8_t version; 2101 2102 /** 2103 * Panel Control HW instance mask. 2104 * Bit 0 is Panel Control HW instance 0. 2105 * Bit 1 is Panel Control HW instance 1. 2106 */ 2107 uint8_t panel_mask; 2108 2109 /** 2110 * Explicit padding to 4 byte boundary. 2111 */ 2112 uint8_t pad[2]; 2113 }; 2114 2115 /** 2116 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2117 */ 2118 struct dmub_rb_cmd_abm_set_level { 2119 /** 2120 * Command header. 2121 */ 2122 struct dmub_cmd_header header; 2123 2124 /** 2125 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2126 */ 2127 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2128 }; 2129 2130 /** 2131 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2132 */ 2133 struct dmub_cmd_abm_set_ambient_level_data { 2134 /** 2135 * Ambient light sensor reading from OS. 2136 */ 2137 uint32_t ambient_lux; 2138 2139 /** 2140 * ABM control version. 2141 */ 2142 uint8_t version; 2143 2144 /** 2145 * Panel Control HW instance mask. 2146 * Bit 0 is Panel Control HW instance 0. 2147 * Bit 1 is Panel Control HW instance 1. 2148 */ 2149 uint8_t panel_mask; 2150 2151 /** 2152 * Explicit padding to 4 byte boundary. 2153 */ 2154 uint8_t pad[2]; 2155 }; 2156 2157 /** 2158 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2159 */ 2160 struct dmub_rb_cmd_abm_set_ambient_level { 2161 /** 2162 * Command header. 2163 */ 2164 struct dmub_cmd_header header; 2165 2166 /** 2167 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2168 */ 2169 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2170 }; 2171 2172 /** 2173 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2174 */ 2175 struct dmub_cmd_abm_set_pwm_frac_data { 2176 /** 2177 * Enable/disable fractional duty cycle for backlight PWM. 2178 * TODO: Convert to uint8_t. 2179 */ 2180 uint32_t fractional_pwm; 2181 2182 /** 2183 * ABM control version. 2184 */ 2185 uint8_t version; 2186 2187 /** 2188 * Panel Control HW instance mask. 2189 * Bit 0 is Panel Control HW instance 0. 2190 * Bit 1 is Panel Control HW instance 1. 2191 */ 2192 uint8_t panel_mask; 2193 2194 /** 2195 * Explicit padding to 4 byte boundary. 2196 */ 2197 uint8_t pad[2]; 2198 }; 2199 2200 /** 2201 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2202 */ 2203 struct dmub_rb_cmd_abm_set_pwm_frac { 2204 /** 2205 * Command header. 2206 */ 2207 struct dmub_cmd_header header; 2208 2209 /** 2210 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2211 */ 2212 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2213 }; 2214 2215 /** 2216 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2217 */ 2218 struct dmub_cmd_abm_init_config_data { 2219 /** 2220 * Location of indirect buffer used to pass init data to ABM. 2221 */ 2222 union dmub_addr src; 2223 2224 /** 2225 * Indirect buffer length. 2226 */ 2227 uint16_t bytes; 2228 2229 2230 /** 2231 * ABM control version. 2232 */ 2233 uint8_t version; 2234 2235 /** 2236 * Panel Control HW instance mask. 2237 * Bit 0 is Panel Control HW instance 0. 2238 * Bit 1 is Panel Control HW instance 1. 2239 */ 2240 uint8_t panel_mask; 2241 2242 /** 2243 * Explicit padding to 4 byte boundary. 2244 */ 2245 uint8_t pad[2]; 2246 }; 2247 2248 /** 2249 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2250 */ 2251 struct dmub_rb_cmd_abm_init_config { 2252 /** 2253 * Command header. 2254 */ 2255 struct dmub_cmd_header header; 2256 2257 /** 2258 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2259 */ 2260 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2261 }; 2262 2263 /** 2264 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2265 */ 2266 2267 struct dmub_cmd_abm_pause_data { 2268 2269 /** 2270 * Panel Control HW instance mask. 2271 * Bit 0 is Panel Control HW instance 0. 2272 * Bit 1 is Panel Control HW instance 1. 2273 */ 2274 uint8_t panel_mask; 2275 2276 /** 2277 * OTG hw instance 2278 */ 2279 uint8_t otg_inst; 2280 2281 /** 2282 * Enable or disable ABM pause 2283 */ 2284 uint8_t enable; 2285 2286 /** 2287 * Explicit padding to 4 byte boundary. 2288 */ 2289 uint8_t pad[1]; 2290 }; 2291 2292 /** 2293 * Definition of a DMUB_CMD__ABM_PAUSE command. 2294 */ 2295 struct dmub_rb_cmd_abm_pause { 2296 /** 2297 * Command header. 2298 */ 2299 struct dmub_cmd_header header; 2300 2301 /** 2302 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2303 */ 2304 struct dmub_cmd_abm_pause_data abm_pause_data; 2305 }; 2306 2307 /** 2308 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2309 */ 2310 struct dmub_cmd_query_feature_caps_data { 2311 /** 2312 * DMUB feature capabilities. 2313 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2314 */ 2315 struct dmub_feature_caps feature_caps; 2316 }; 2317 2318 /** 2319 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2320 */ 2321 struct dmub_rb_cmd_query_feature_caps { 2322 /** 2323 * Command header. 2324 */ 2325 struct dmub_cmd_header header; 2326 /** 2327 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2328 */ 2329 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2330 }; 2331 2332 struct dmub_optc_state { 2333 uint32_t v_total_max; 2334 uint32_t v_total_min; 2335 uint32_t v_total_mid; 2336 uint32_t v_total_mid_frame_num; 2337 uint32_t tg_inst; 2338 uint32_t enable_manual_trigger; 2339 uint32_t clear_force_vsync; 2340 }; 2341 2342 struct dmub_rb_cmd_drr_update { 2343 struct dmub_cmd_header header; 2344 struct dmub_optc_state dmub_optc_state_req; 2345 }; 2346 2347 /** 2348 * enum dmub_cmd_panel_cntl_type - Panel control command. 2349 */ 2350 enum dmub_cmd_panel_cntl_type { 2351 /** 2352 * Initializes embedded panel hardware blocks. 2353 */ 2354 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2355 /** 2356 * Queries backlight info for the embedded panel. 2357 */ 2358 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2359 }; 2360 2361 /** 2362 * struct dmub_cmd_panel_cntl_data - Panel control data. 2363 */ 2364 struct dmub_cmd_panel_cntl_data { 2365 uint32_t inst; /**< panel instance */ 2366 uint32_t current_backlight; /* in/out */ 2367 uint32_t bl_pwm_cntl; /* in/out */ 2368 uint32_t bl_pwm_period_cntl; /* in/out */ 2369 uint32_t bl_pwm_ref_div1; /* in/out */ 2370 uint8_t is_backlight_on : 1; /* in/out */ 2371 uint8_t is_powered_on : 1; /* in/out */ 2372 }; 2373 2374 /** 2375 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2376 */ 2377 struct dmub_rb_cmd_panel_cntl { 2378 struct dmub_cmd_header header; /**< header */ 2379 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2380 }; 2381 2382 /** 2383 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2384 */ 2385 struct dmub_cmd_lvtma_control_data { 2386 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2387 uint8_t reserved_0[3]; /**< For future use */ 2388 uint8_t panel_inst; /**< LVTMA control instance */ 2389 uint8_t reserved_1[3]; /**< For future use */ 2390 }; 2391 2392 /** 2393 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2394 */ 2395 struct dmub_rb_cmd_lvtma_control { 2396 /** 2397 * Command header. 2398 */ 2399 struct dmub_cmd_header header; 2400 /** 2401 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2402 */ 2403 struct dmub_cmd_lvtma_control_data data; 2404 }; 2405 2406 /** 2407 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2408 */ 2409 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 2410 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2411 uint8_t is_usb; /**< is phy is usb */ 2412 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 2413 uint8_t is_dp4; /**< is dp in 4 lane */ 2414 }; 2415 2416 /** 2417 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2418 */ 2419 struct dmub_rb_cmd_transmitter_query_dp_alt { 2420 struct dmub_cmd_header header; /**< header */ 2421 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 2422 }; 2423 2424 /** 2425 * Maximum number of bytes a chunk sent to DMUB for parsing 2426 */ 2427 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2428 2429 /** 2430 * Represent a chunk of CEA blocks sent to DMUB for parsing 2431 */ 2432 struct dmub_cmd_send_edid_cea { 2433 uint16_t offset; /**< offset into the CEA block */ 2434 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2435 uint16_t cea_total_length; /**< total length of the CEA block */ 2436 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2437 uint8_t pad[3]; /**< padding and for future expansion */ 2438 }; 2439 2440 /** 2441 * Result of VSDB parsing from CEA block 2442 */ 2443 struct dmub_cmd_edid_cea_amd_vsdb { 2444 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2445 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2446 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2447 uint16_t min_frame_rate; /**< Maximum frame rate */ 2448 uint16_t max_frame_rate; /**< Minimum frame rate */ 2449 }; 2450 2451 /** 2452 * Result of sending a CEA chunk 2453 */ 2454 struct dmub_cmd_edid_cea_ack { 2455 uint16_t offset; /**< offset of the chunk into the CEA block */ 2456 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2457 uint8_t pad; /**< padding and for future expansion */ 2458 }; 2459 2460 /** 2461 * Specify whether the result is an ACK/NACK or the parsing has finished 2462 */ 2463 enum dmub_cmd_edid_cea_reply_type { 2464 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2465 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2466 }; 2467 2468 /** 2469 * Definition of a DMUB_CMD__EDID_CEA command. 2470 */ 2471 struct dmub_rb_cmd_edid_cea { 2472 struct dmub_cmd_header header; /**< Command header */ 2473 union dmub_cmd_edid_cea_data { 2474 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2475 struct dmub_cmd_edid_cea_output { /**< output with results */ 2476 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2477 union { 2478 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2479 struct dmub_cmd_edid_cea_ack ack; 2480 }; 2481 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2482 } data; /**< Command data */ 2483 2484 }; 2485 2486 /** 2487 * union dmub_rb_cmd - DMUB inbox command. 2488 */ 2489 union dmub_rb_cmd { 2490 struct dmub_rb_cmd_lock_hw lock_hw; 2491 /** 2492 * Elements shared with all commands. 2493 */ 2494 struct dmub_rb_cmd_common cmd_common; 2495 /** 2496 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2497 */ 2498 struct dmub_rb_cmd_read_modify_write read_modify_write; 2499 /** 2500 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2501 */ 2502 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2503 /** 2504 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2505 */ 2506 struct dmub_rb_cmd_burst_write burst_write; 2507 /** 2508 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2509 */ 2510 struct dmub_rb_cmd_reg_wait reg_wait; 2511 /** 2512 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2513 */ 2514 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2515 /** 2516 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2517 */ 2518 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2519 /** 2520 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2521 */ 2522 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2523 /** 2524 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2525 */ 2526 struct dmub_rb_cmd_dpphy_init dpphy_init; 2527 /** 2528 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2529 */ 2530 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2531 /** 2532 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2533 */ 2534 struct dmub_rb_cmd_psr_set_version psr_set_version; 2535 /** 2536 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2537 */ 2538 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2539 /** 2540 * Definition of a DMUB_CMD__PSR_ENABLE command. 2541 */ 2542 struct dmub_rb_cmd_psr_enable psr_enable; 2543 /** 2544 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2545 */ 2546 struct dmub_rb_cmd_psr_set_level psr_set_level; 2547 /** 2548 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2549 */ 2550 struct dmub_rb_cmd_psr_force_static psr_force_static; 2551 /** 2552 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2553 */ 2554 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 2555 /** 2556 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2557 */ 2558 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2559 /** 2560 * Definition of a DMUB_CMD__MALL command. 2561 */ 2562 struct dmub_rb_cmd_mall mall; 2563 /** 2564 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2565 */ 2566 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2567 2568 /** 2569 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2570 */ 2571 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2572 2573 /** 2574 * Definition of DMUB_CMD__PANEL_CNTL commands. 2575 */ 2576 struct dmub_rb_cmd_panel_cntl panel_cntl; 2577 /** 2578 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2579 */ 2580 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2581 2582 /** 2583 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2584 */ 2585 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2586 2587 /** 2588 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2589 */ 2590 struct dmub_rb_cmd_abm_set_level abm_set_level; 2591 2592 /** 2593 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2594 */ 2595 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2596 2597 /** 2598 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2599 */ 2600 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2601 2602 /** 2603 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2604 */ 2605 struct dmub_rb_cmd_abm_init_config abm_init_config; 2606 2607 /** 2608 * Definition of a DMUB_CMD__ABM_PAUSE command. 2609 */ 2610 struct dmub_rb_cmd_abm_pause abm_pause; 2611 2612 /** 2613 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2614 */ 2615 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2616 2617 /** 2618 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2619 */ 2620 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2621 2622 /** 2623 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2624 */ 2625 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2626 struct dmub_rb_cmd_drr_update drr_update; 2627 /** 2628 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2629 */ 2630 struct dmub_rb_cmd_lvtma_control lvtma_control; 2631 /** 2632 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2633 */ 2634 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 2635 /** 2636 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 2637 */ 2638 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 2639 /** 2640 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 2641 */ 2642 struct dmub_rb_cmd_set_config_access set_config_access; 2643 /** 2644 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2645 */ 2646 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 2647 /** 2648 * Definition of a DMUB_CMD__EDID_CEA command. 2649 */ 2650 struct dmub_rb_cmd_edid_cea edid_cea; 2651 }; 2652 2653 /** 2654 * union dmub_rb_out_cmd - Outbox command 2655 */ 2656 union dmub_rb_out_cmd { 2657 /** 2658 * Parameters common to every command. 2659 */ 2660 struct dmub_rb_cmd_common cmd_common; 2661 /** 2662 * AUX reply command. 2663 */ 2664 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2665 /** 2666 * HPD notify command. 2667 */ 2668 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2669 /** 2670 * SET_CONFIG reply command. 2671 */ 2672 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 2673 }; 2674 #pragma pack(pop) 2675 2676 2677 //============================================================================== 2678 //</DMUB_CMD>=================================================================== 2679 //============================================================================== 2680 //< DMUB_RB>==================================================================== 2681 //============================================================================== 2682 2683 #if defined(__cplusplus) 2684 extern "C" { 2685 #endif 2686 2687 /** 2688 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2689 */ 2690 struct dmub_rb_init_params { 2691 void *ctx; /**< Caller provided context pointer */ 2692 void *base_address; /**< CPU base address for ring's data */ 2693 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2694 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2695 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2696 }; 2697 2698 /** 2699 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2700 */ 2701 struct dmub_rb { 2702 void *base_address; /**< CPU address for the ring's data */ 2703 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2704 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2705 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2706 2707 void *ctx; /**< Caller provided context pointer */ 2708 void *dmub; /**< Pointer to the DMUB interface */ 2709 }; 2710 2711 /** 2712 * @brief Checks if the ringbuffer is empty. 2713 * 2714 * @param rb DMUB Ringbuffer 2715 * @return true if empty 2716 * @return false otherwise 2717 */ 2718 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2719 { 2720 return (rb->wrpt == rb->rptr); 2721 } 2722 2723 /** 2724 * @brief Checks if the ringbuffer is full 2725 * 2726 * @param rb DMUB Ringbuffer 2727 * @return true if full 2728 * @return false otherwise 2729 */ 2730 static inline bool dmub_rb_full(struct dmub_rb *rb) 2731 { 2732 uint32_t data_count; 2733 2734 if (rb->wrpt >= rb->rptr) 2735 data_count = rb->wrpt - rb->rptr; 2736 else 2737 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2738 2739 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2740 } 2741 2742 /** 2743 * @brief Pushes a command into the ringbuffer 2744 * 2745 * @param rb DMUB ringbuffer 2746 * @param cmd The command to push 2747 * @return true if the ringbuffer was not full 2748 * @return false otherwise 2749 */ 2750 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2751 const union dmub_rb_cmd *cmd) 2752 { 2753 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 2754 const uint64_t *src = (const uint64_t *)cmd; 2755 uint8_t i; 2756 2757 if (dmub_rb_full(rb)) 2758 return false; 2759 2760 // copying data 2761 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2762 *dst++ = *src++; 2763 2764 rb->wrpt += DMUB_RB_CMD_SIZE; 2765 2766 if (rb->wrpt >= rb->capacity) 2767 rb->wrpt %= rb->capacity; 2768 2769 return true; 2770 } 2771 2772 /** 2773 * @brief Pushes a command into the DMUB outbox ringbuffer 2774 * 2775 * @param rb DMUB outbox ringbuffer 2776 * @param cmd Outbox command 2777 * @return true if not full 2778 * @return false otherwise 2779 */ 2780 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2781 const union dmub_rb_out_cmd *cmd) 2782 { 2783 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2784 const uint8_t *src = (const uint8_t *)cmd; 2785 2786 if (dmub_rb_full(rb)) 2787 return false; 2788 2789 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2790 2791 rb->wrpt += DMUB_RB_CMD_SIZE; 2792 2793 if (rb->wrpt >= rb->capacity) 2794 rb->wrpt %= rb->capacity; 2795 2796 return true; 2797 } 2798 2799 /** 2800 * @brief Returns the next unprocessed command in the ringbuffer. 2801 * 2802 * @param rb DMUB ringbuffer 2803 * @param cmd The command to return 2804 * @return true if not empty 2805 * @return false otherwise 2806 */ 2807 static inline bool dmub_rb_front(struct dmub_rb *rb, 2808 union dmub_rb_cmd **cmd) 2809 { 2810 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2811 2812 if (dmub_rb_empty(rb)) 2813 return false; 2814 2815 *cmd = (union dmub_rb_cmd *)rb_cmd; 2816 2817 return true; 2818 } 2819 2820 /** 2821 * @brief Determines the next ringbuffer offset. 2822 * 2823 * @param rb DMUB inbox ringbuffer 2824 * @param num_cmds Number of commands 2825 * @param next_rptr The next offset in the ringbuffer 2826 */ 2827 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2828 uint32_t num_cmds, 2829 uint32_t *next_rptr) 2830 { 2831 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2832 2833 if (*next_rptr >= rb->capacity) 2834 *next_rptr %= rb->capacity; 2835 } 2836 2837 /** 2838 * @brief Returns a pointer to a command in the inbox. 2839 * 2840 * @param rb DMUB inbox ringbuffer 2841 * @param cmd The inbox command to return 2842 * @param rptr The ringbuffer offset 2843 * @return true if not empty 2844 * @return false otherwise 2845 */ 2846 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 2847 union dmub_rb_cmd **cmd, 2848 uint32_t rptr) 2849 { 2850 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 2851 2852 if (dmub_rb_empty(rb)) 2853 return false; 2854 2855 *cmd = (union dmub_rb_cmd *)rb_cmd; 2856 2857 return true; 2858 } 2859 2860 /** 2861 * @brief Returns the next unprocessed command in the outbox. 2862 * 2863 * @param rb DMUB outbox ringbuffer 2864 * @param cmd The outbox command to return 2865 * @return true if not empty 2866 * @return false otherwise 2867 */ 2868 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2869 union dmub_rb_out_cmd *cmd) 2870 { 2871 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 2872 uint64_t *dst = (uint64_t *)cmd; 2873 uint8_t i; 2874 2875 if (dmub_rb_empty(rb)) 2876 return false; 2877 2878 // copying data 2879 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2880 *dst++ = *src++; 2881 2882 return true; 2883 } 2884 2885 /** 2886 * @brief Removes the front entry in the ringbuffer. 2887 * 2888 * @param rb DMUB ringbuffer 2889 * @return true if the command was removed 2890 * @return false if there were no commands 2891 */ 2892 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 2893 { 2894 if (dmub_rb_empty(rb)) 2895 return false; 2896 2897 rb->rptr += DMUB_RB_CMD_SIZE; 2898 2899 if (rb->rptr >= rb->capacity) 2900 rb->rptr %= rb->capacity; 2901 2902 return true; 2903 } 2904 2905 /** 2906 * @brief Flushes commands in the ringbuffer to framebuffer memory. 2907 * 2908 * Avoids a race condition where DMCUB accesses memory while 2909 * there are still writes in flight to framebuffer. 2910 * 2911 * @param rb DMUB ringbuffer 2912 */ 2913 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 2914 { 2915 uint32_t rptr = rb->rptr; 2916 uint32_t wptr = rb->wrpt; 2917 2918 while (rptr != wptr) { 2919 uint64_t volatile *data = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rptr); 2920 //uint64_t volatile *p = (uint64_t volatile *)data; 2921 uint64_t temp; 2922 uint8_t i; 2923 2924 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2925 temp = *data++; 2926 2927 rptr += DMUB_RB_CMD_SIZE; 2928 if (rptr >= rb->capacity) 2929 rptr %= rb->capacity; 2930 } 2931 } 2932 2933 /** 2934 * @brief Initializes a DMCUB ringbuffer 2935 * 2936 * @param rb DMUB ringbuffer 2937 * @param init_params initial configuration for the ringbuffer 2938 */ 2939 static inline void dmub_rb_init(struct dmub_rb *rb, 2940 struct dmub_rb_init_params *init_params) 2941 { 2942 rb->base_address = init_params->base_address; 2943 rb->capacity = init_params->capacity; 2944 rb->rptr = init_params->read_ptr; 2945 rb->wrpt = init_params->write_ptr; 2946 } 2947 2948 /** 2949 * @brief Copies output data from in/out commands into the given command. 2950 * 2951 * @param rb DMUB ringbuffer 2952 * @param cmd Command to copy data into 2953 */ 2954 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 2955 union dmub_rb_cmd *cmd) 2956 { 2957 // Copy rb entry back into command 2958 uint8_t *rd_ptr = (rb->rptr == 0) ? 2959 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 2960 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 2961 2962 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 2963 } 2964 2965 #if defined(__cplusplus) 2966 } 2967 #endif 2968 2969 //============================================================================== 2970 //</DMUB_RB>==================================================================== 2971 //============================================================================== 2972 2973 #endif /* _DMUB_CMD_H_ */ 2974