1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 #include <stdarg.h> 43 44 #include "atomfirmware.h" 45 46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 47 48 /* Firmware versioning. */ 49 #ifdef DMUB_EXPOSE_VERSION 50 #define DMUB_FW_VERSION_GIT_HASH 0xc29b1734b 51 #define DMUB_FW_VERSION_MAJOR 0 52 #define DMUB_FW_VERSION_MINOR 0 53 #define DMUB_FW_VERSION_REVISION 56 54 #define DMUB_FW_VERSION_TEST 0 55 #define DMUB_FW_VERSION_VBIOS 0 56 #define DMUB_FW_VERSION_HOTFIX 0 57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 62 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 63 64 #endif 65 66 //<DMUB_TYPES>================================================================== 67 /* Basic type definitions. */ 68 69 #define __forceinline inline 70 71 /** 72 * Flag from driver to indicate that ABM should be disabled gradually 73 * by slowly reversing all backlight programming and pixel compensation. 74 */ 75 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 76 77 /** 78 * Flag from driver to indicate that ABM should be disabled immediately 79 * and undo all backlight programming and pixel compensation. 80 */ 81 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 82 83 /** 84 * Flag from driver to indicate that ABM should be disabled immediately 85 * and keep the current backlight programming and pixel compensation. 86 */ 87 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 88 89 /** 90 * Flag from driver to set the current ABM pipe index or ABM operating level. 91 */ 92 #define SET_ABM_PIPE_NORMAL 1 93 94 /** 95 * Number of ambient light levels in ABM algorithm. 96 */ 97 #define NUM_AMBI_LEVEL 5 98 99 /** 100 * Number of operating/aggression levels in ABM algorithm. 101 */ 102 #define NUM_AGGR_LEVEL 4 103 104 /** 105 * Number of segments in the gamma curve. 106 */ 107 #define NUM_POWER_FN_SEGS 8 108 109 /** 110 * Number of segments in the backlight curve. 111 */ 112 #define NUM_BL_CURVE_SEGS 16 113 114 /* Maximum number of streams on any ASIC. */ 115 #define DMUB_MAX_STREAMS 6 116 117 /* Maximum number of planes on any ASIC. */ 118 #define DMUB_MAX_PLANES 6 119 120 /* Trace buffer offset for entry */ 121 #define TRACE_BUFFER_ENTRY_OFFSET 16 122 123 /** 124 * Physical framebuffer address location, 64-bit. 125 */ 126 #ifndef PHYSICAL_ADDRESS_LOC 127 #define PHYSICAL_ADDRESS_LOC union large_integer 128 #endif 129 130 /** 131 * OS/FW agnostic memcpy 132 */ 133 #ifndef dmub_memcpy 134 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 135 #endif 136 137 /** 138 * OS/FW agnostic memset 139 */ 140 #ifndef dmub_memset 141 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 142 #endif 143 144 #if defined(__cplusplus) 145 extern "C" { 146 #endif 147 148 /** 149 * OS/FW agnostic udelay 150 */ 151 #ifndef dmub_udelay 152 #define dmub_udelay(microseconds) udelay(microseconds) 153 #endif 154 155 /** 156 * union dmub_addr - DMUB physical/virtual 64-bit address. 157 */ 158 union dmub_addr { 159 struct { 160 uint32_t low_part; /**< Lower 32 bits */ 161 uint32_t high_part; /**< Upper 32 bits */ 162 } u; /*<< Low/high bit access */ 163 uint64_t quad_part; /*<< 64 bit address */ 164 }; 165 166 /** 167 * Flags that can be set by driver to change some PSR behaviour. 168 */ 169 union dmub_psr_debug_flags { 170 /** 171 * Debug flags. 172 */ 173 struct { 174 /** 175 * Enable visual confirm in FW. 176 */ 177 uint32_t visual_confirm : 1; 178 /** 179 * Use HW Lock Mgr object to do HW locking in FW. 180 */ 181 uint32_t use_hw_lock_mgr : 1; 182 183 /** 184 * Unused. 185 * TODO: Remove. 186 */ 187 uint32_t log_line_nums : 1; 188 } bitfields; 189 190 /** 191 * Union for debug flags. 192 */ 193 uint32_t u32All; 194 }; 195 196 /** 197 * DMUB feature capabilities. 198 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 199 */ 200 struct dmub_feature_caps { 201 /** 202 * Max PSR version supported by FW. 203 */ 204 uint8_t psr; 205 #ifndef TRIM_FAMS 206 uint8_t fw_assisted_mclk_switch; 207 uint8_t reserved[6]; 208 #else 209 uint8_t reserved[7]; 210 #endif 211 }; 212 213 #if defined(__cplusplus) 214 } 215 #endif 216 217 //============================================================================== 218 //</DMUB_TYPES>================================================================= 219 //============================================================================== 220 //< DMUB_META>================================================================== 221 //============================================================================== 222 #pragma pack(push, 1) 223 224 /* Magic value for identifying dmub_fw_meta_info */ 225 #define DMUB_FW_META_MAGIC 0x444D5542 226 227 /* Offset from the end of the file to the dmub_fw_meta_info */ 228 #define DMUB_FW_META_OFFSET 0x24 229 230 /** 231 * struct dmub_fw_meta_info - metadata associated with fw binary 232 * 233 * NOTE: This should be considered a stable API. Fields should 234 * not be repurposed or reordered. New fields should be 235 * added instead to extend the structure. 236 * 237 * @magic_value: magic value identifying DMUB firmware meta info 238 * @fw_region_size: size of the firmware state region 239 * @trace_buffer_size: size of the tracebuffer region 240 * @fw_version: the firmware version information 241 * @dal_fw: 1 if the firmware is DAL 242 */ 243 struct dmub_fw_meta_info { 244 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 245 uint32_t fw_region_size; /**< size of the firmware state region */ 246 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 247 uint32_t fw_version; /**< the firmware version information */ 248 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 249 uint8_t reserved[3]; /**< padding bits */ 250 }; 251 252 /** 253 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 254 */ 255 union dmub_fw_meta { 256 struct dmub_fw_meta_info info; /**< metadata info */ 257 uint8_t reserved[64]; /**< padding bits */ 258 }; 259 260 #pragma pack(pop) 261 262 //============================================================================== 263 //< DMUB Trace Buffer>================================================================ 264 //============================================================================== 265 /** 266 * dmub_trace_code_t - firmware trace code, 32-bits 267 */ 268 typedef uint32_t dmub_trace_code_t; 269 270 /** 271 * struct dmcub_trace_buf_entry - Firmware trace entry 272 */ 273 struct dmcub_trace_buf_entry { 274 dmub_trace_code_t trace_code; /**< trace code for the event */ 275 uint32_t tick_count; /**< the tick count at time of trace */ 276 uint32_t param0; /**< trace defined parameter 0 */ 277 uint32_t param1; /**< trace defined parameter 1 */ 278 }; 279 280 //============================================================================== 281 //< DMUB_STATUS>================================================================ 282 //============================================================================== 283 284 /** 285 * DMCUB scratch registers can be used to determine firmware status. 286 * Current scratch register usage is as follows: 287 * 288 * SCRATCH0: FW Boot Status register 289 * SCRATCH15: FW Boot Options register 290 */ 291 292 /** 293 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 294 */ 295 union dmub_fw_boot_status { 296 struct { 297 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 298 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 299 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 300 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 301 } bits; /**< status bits */ 302 uint32_t all; /**< 32-bit access to status bits */ 303 }; 304 305 /** 306 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 307 */ 308 enum dmub_fw_boot_status_bit { 309 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 310 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 311 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 312 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 313 }; 314 315 /** 316 * union dmub_fw_boot_options - Boot option definitions for SCRATCH15 317 */ 318 union dmub_fw_boot_options { 319 struct { 320 uint32_t pemu_env : 1; /**< 1 if PEMU */ 321 uint32_t fpga_env : 1; /**< 1 if FPGA */ 322 uint32_t optimized_init : 1; /**< 1 if optimized init */ 323 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 324 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 325 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 326 uint32_t reserved : 26; /**< reserved */ 327 } bits; /**< boot bits */ 328 uint32_t all; /**< 32-bit access to bits */ 329 }; 330 331 enum dmub_fw_boot_options_bit { 332 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 333 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 334 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 335 }; 336 337 //============================================================================== 338 //</DMUB_STATUS>================================================================ 339 //============================================================================== 340 //< DMUB_VBIOS>================================================================= 341 //============================================================================== 342 343 /* 344 * enum dmub_cmd_vbios_type - VBIOS commands. 345 * 346 * Command IDs should be treated as stable ABI. 347 * Do not reuse or modify IDs. 348 */ 349 enum dmub_cmd_vbios_type { 350 /** 351 * Configures the DIG encoder. 352 */ 353 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 354 /** 355 * Controls the PHY. 356 */ 357 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 358 /** 359 * Sets the pixel clock/symbol clock. 360 */ 361 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 362 /** 363 * Enables or disables power gating. 364 */ 365 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 366 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 367 }; 368 369 //============================================================================== 370 //</DMUB_VBIOS>================================================================= 371 //============================================================================== 372 //< DMUB_GPINT>================================================================= 373 //============================================================================== 374 375 /** 376 * The shifts and masks below may alternatively be used to format and read 377 * the command register bits. 378 */ 379 380 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 381 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 382 383 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 384 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 385 386 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 387 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 388 389 /** 390 * Command responses. 391 */ 392 393 /** 394 * Return response for DMUB_GPINT__STOP_FW command. 395 */ 396 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 397 398 /** 399 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 400 */ 401 union dmub_gpint_data_register { 402 struct { 403 uint32_t param : 16; /**< 16-bit parameter */ 404 uint32_t command_code : 12; /**< GPINT command */ 405 uint32_t status : 4; /**< Command status bit */ 406 } bits; /**< GPINT bit access */ 407 uint32_t all; /**< GPINT 32-bit access */ 408 }; 409 410 /* 411 * enum dmub_gpint_command - GPINT command to DMCUB FW 412 * 413 * Command IDs should be treated as stable ABI. 414 * Do not reuse or modify IDs. 415 */ 416 enum dmub_gpint_command { 417 /** 418 * Invalid command, ignored. 419 */ 420 DMUB_GPINT__INVALID_COMMAND = 0, 421 /** 422 * DESC: Queries the firmware version. 423 * RETURN: Firmware version. 424 */ 425 DMUB_GPINT__GET_FW_VERSION = 1, 426 /** 427 * DESC: Halts the firmware. 428 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 429 */ 430 DMUB_GPINT__STOP_FW = 2, 431 /** 432 * DESC: Get PSR state from FW. 433 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 434 */ 435 DMUB_GPINT__GET_PSR_STATE = 7, 436 /** 437 * DESC: Notifies DMCUB of the currently active streams. 438 * ARGS: Stream mask, 1 bit per active stream index. 439 */ 440 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 441 /** 442 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 443 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 444 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 445 * RETURN: PSR residency in milli-percent. 446 */ 447 DMUB_GPINT__PSR_RESIDENCY = 9, 448 }; 449 450 //============================================================================== 451 //</DMUB_GPINT>================================================================= 452 //============================================================================== 453 //< DMUB_CMD>=================================================================== 454 //============================================================================== 455 456 /** 457 * Size in bytes of each DMUB command. 458 */ 459 #define DMUB_RB_CMD_SIZE 64 460 461 /** 462 * Maximum number of items in the DMUB ringbuffer. 463 */ 464 #define DMUB_RB_MAX_ENTRY 128 465 466 /** 467 * Ringbuffer size in bytes. 468 */ 469 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 470 471 /** 472 * REG_SET mask for reg offload. 473 */ 474 #define REG_SET_MASK 0xFFFF 475 476 /* 477 * enum dmub_cmd_type - DMUB inbox command. 478 * 479 * Command IDs should be treated as stable ABI. 480 * Do not reuse or modify IDs. 481 */ 482 enum dmub_cmd_type { 483 /** 484 * Invalid command. 485 */ 486 DMUB_CMD__NULL = 0, 487 /** 488 * Read modify write register sequence offload. 489 */ 490 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 491 /** 492 * Field update register sequence offload. 493 */ 494 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 495 /** 496 * Burst write sequence offload. 497 */ 498 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 499 /** 500 * Reg wait sequence offload. 501 */ 502 DMUB_CMD__REG_REG_WAIT = 4, 503 /** 504 * Workaround to avoid HUBP underflow during NV12 playback. 505 */ 506 DMUB_CMD__PLAT_54186_WA = 5, 507 /** 508 * Command type used to query FW feature caps. 509 */ 510 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 511 /** 512 * Command type used for all PSR commands. 513 */ 514 DMUB_CMD__PSR = 64, 515 /** 516 * Command type used for all MALL commands. 517 */ 518 DMUB_CMD__MALL = 65, 519 /** 520 * Command type used for all ABM commands. 521 */ 522 DMUB_CMD__ABM = 66, 523 /** 524 * Command type used for HW locking in FW. 525 */ 526 DMUB_CMD__HW_LOCK = 69, 527 /** 528 * Command type used to access DP AUX. 529 */ 530 DMUB_CMD__DP_AUX_ACCESS = 70, 531 /** 532 * Command type used for OUTBOX1 notification enable 533 */ 534 DMUB_CMD__OUTBOX1_ENABLE = 71, 535 #ifndef TRIM_FAMS 536 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 537 #endif 538 539 /** 540 * Command type used for all VBIOS interface commands. 541 */ 542 DMUB_CMD__VBIOS = 128, 543 }; 544 545 /** 546 * enum dmub_out_cmd_type - DMUB outbox commands. 547 */ 548 enum dmub_out_cmd_type { 549 /** 550 * Invalid outbox command, ignored. 551 */ 552 DMUB_OUT_CMD__NULL = 0, 553 /** 554 * Command type used for DP AUX Reply data notification 555 */ 556 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 557 /** 558 * Command type used for DP HPD event notification 559 */ 560 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 561 }; 562 563 #pragma pack(push, 1) 564 565 /** 566 * struct dmub_cmd_header - Common command header fields. 567 */ 568 struct dmub_cmd_header { 569 unsigned int type : 8; /**< command type */ 570 unsigned int sub_type : 8; /**< command sub type */ 571 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 572 unsigned int reserved0 : 7; /**< reserved bits */ 573 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 574 unsigned int reserved1 : 2; /**< reserved bits */ 575 }; 576 577 /* 578 * struct dmub_cmd_read_modify_write_sequence - Read modify write 579 * 580 * 60 payload bytes can hold up to 5 sets of read modify writes, 581 * each take 3 dwords. 582 * 583 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 584 * 585 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 586 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 587 */ 588 struct dmub_cmd_read_modify_write_sequence { 589 uint32_t addr; /**< register address */ 590 uint32_t modify_mask; /**< modify mask */ 591 uint32_t modify_value; /**< modify value */ 592 }; 593 594 /** 595 * Maximum number of ops in read modify write sequence. 596 */ 597 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 598 599 /** 600 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 601 */ 602 struct dmub_rb_cmd_read_modify_write { 603 struct dmub_cmd_header header; /**< command header */ 604 /** 605 * Read modify write sequence. 606 */ 607 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 608 }; 609 610 /* 611 * Update a register with specified masks and values sequeunce 612 * 613 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 614 * 615 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 616 * 617 * 618 * USE CASE: 619 * 1. auto-increment register where additional read would update pointer and produce wrong result 620 * 2. toggle a bit without read in the middle 621 */ 622 623 struct dmub_cmd_reg_field_update_sequence { 624 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 625 uint32_t modify_value; /**< value to update with */ 626 }; 627 628 /** 629 * Maximum number of ops in field update sequence. 630 */ 631 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 632 633 /** 634 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 635 */ 636 struct dmub_rb_cmd_reg_field_update_sequence { 637 struct dmub_cmd_header header; /**< command header */ 638 uint32_t addr; /**< register address */ 639 /** 640 * Field update sequence. 641 */ 642 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 643 }; 644 645 646 /** 647 * Maximum number of burst write values. 648 */ 649 #define DMUB_BURST_WRITE_VALUES__MAX 14 650 651 /* 652 * struct dmub_rb_cmd_burst_write - Burst write 653 * 654 * support use case such as writing out LUTs. 655 * 656 * 60 payload bytes can hold up to 14 values to write to given address 657 * 658 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 659 */ 660 struct dmub_rb_cmd_burst_write { 661 struct dmub_cmd_header header; /**< command header */ 662 uint32_t addr; /**< register start address */ 663 /** 664 * Burst write register values. 665 */ 666 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 667 }; 668 669 /** 670 * struct dmub_rb_cmd_common - Common command header 671 */ 672 struct dmub_rb_cmd_common { 673 struct dmub_cmd_header header; /**< command header */ 674 /** 675 * Padding to RB_CMD_SIZE 676 */ 677 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 678 }; 679 680 /** 681 * struct dmub_cmd_reg_wait_data - Register wait data 682 */ 683 struct dmub_cmd_reg_wait_data { 684 uint32_t addr; /**< Register address */ 685 uint32_t mask; /**< Mask for register bits */ 686 uint32_t condition_field_value; /**< Value to wait for */ 687 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 688 }; 689 690 /** 691 * struct dmub_rb_cmd_reg_wait - Register wait command 692 */ 693 struct dmub_rb_cmd_reg_wait { 694 struct dmub_cmd_header header; /**< Command header */ 695 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 696 }; 697 698 /** 699 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 700 * 701 * Reprograms surface parameters to avoid underflow. 702 */ 703 struct dmub_cmd_PLAT_54186_wa { 704 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 705 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 706 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 707 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 708 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 709 struct { 710 uint8_t hubp_inst : 4; /**< HUBP instance */ 711 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 712 uint8_t immediate :1; /**< Immediate flip */ 713 uint8_t vmid : 4; /**< VMID */ 714 uint8_t grph_stereo : 1; /**< 1 if stereo */ 715 uint32_t reserved : 21; /**< Reserved */ 716 } flip_params; /**< Pageflip parameters */ 717 uint32_t reserved[9]; /**< Reserved bits */ 718 }; 719 720 /** 721 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 722 */ 723 struct dmub_rb_cmd_PLAT_54186_wa { 724 struct dmub_cmd_header header; /**< Command header */ 725 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 726 }; 727 728 /** 729 * struct dmub_rb_cmd_mall - MALL command data. 730 */ 731 struct dmub_rb_cmd_mall { 732 struct dmub_cmd_header header; /**< Common command header */ 733 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 734 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 735 uint32_t tmr_delay; /**< Timer delay */ 736 uint32_t tmr_scale; /**< Timer scale */ 737 uint16_t cursor_width; /**< Cursor width in pixels */ 738 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 739 uint16_t cursor_height; /**< Cursor height in pixels */ 740 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 741 uint8_t debug_bits; /**< Debug bits */ 742 743 uint8_t reserved1; /**< Reserved bits */ 744 uint8_t reserved2; /**< Reserved bits */ 745 }; 746 747 /** 748 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 749 */ 750 struct dmub_cmd_digx_encoder_control_data { 751 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 752 }; 753 754 /** 755 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 756 */ 757 struct dmub_rb_cmd_digx_encoder_control { 758 struct dmub_cmd_header header; /**< header */ 759 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 760 }; 761 762 /** 763 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 764 */ 765 struct dmub_cmd_set_pixel_clock_data { 766 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 767 }; 768 769 /** 770 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 771 */ 772 struct dmub_rb_cmd_set_pixel_clock { 773 struct dmub_cmd_header header; /**< header */ 774 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 775 }; 776 777 /** 778 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 779 */ 780 struct dmub_cmd_enable_disp_power_gating_data { 781 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 782 }; 783 784 /** 785 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 786 */ 787 struct dmub_rb_cmd_enable_disp_power_gating { 788 struct dmub_cmd_header header; /**< header */ 789 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 790 }; 791 792 /** 793 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 794 */ 795 struct dmub_dig_transmitter_control_data_v1_7 { 796 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 797 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 798 union { 799 uint8_t digmode; /**< enum atom_encode_mode_def */ 800 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 801 } mode_laneset; 802 uint8_t lanenum; /**< Number of lanes */ 803 union { 804 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 805 } symclk_units; 806 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 807 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 808 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 809 uint8_t reserved0; /**< For future use */ 810 uint8_t reserved1; /**< For future use */ 811 uint8_t reserved2[3]; /**< For future use */ 812 uint32_t reserved3[11]; /**< For future use */ 813 }; 814 815 /** 816 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 817 */ 818 union dmub_cmd_dig1_transmitter_control_data { 819 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 820 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 821 }; 822 823 /** 824 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 825 */ 826 struct dmub_rb_cmd_dig1_transmitter_control { 827 struct dmub_cmd_header header; /**< header */ 828 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 829 }; 830 831 /** 832 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 833 */ 834 struct dmub_rb_cmd_dpphy_init { 835 struct dmub_cmd_header header; /**< header */ 836 uint8_t reserved[60]; /**< reserved bits */ 837 }; 838 839 /** 840 * enum dp_aux_request_action - DP AUX request command listing. 841 * 842 * 4 AUX request command bits are shifted to high nibble. 843 */ 844 enum dp_aux_request_action { 845 /** I2C-over-AUX write request */ 846 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 847 /** I2C-over-AUX read request */ 848 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 849 /** I2C-over-AUX write status request */ 850 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 851 /** I2C-over-AUX write request with MOT=1 */ 852 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 853 /** I2C-over-AUX read request with MOT=1 */ 854 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 855 /** I2C-over-AUX write status request with MOT=1 */ 856 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 857 /** Native AUX write request */ 858 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 859 /** Native AUX read request */ 860 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 861 }; 862 863 /** 864 * enum aux_return_code_type - DP AUX process return code listing. 865 */ 866 enum aux_return_code_type { 867 /** AUX process succeeded */ 868 AUX_RET_SUCCESS = 0, 869 /** AUX process failed with unknown reason */ 870 AUX_RET_ERROR_UNKNOWN, 871 /** AUX process completed with invalid reply */ 872 AUX_RET_ERROR_INVALID_REPLY, 873 /** AUX process timed out */ 874 AUX_RET_ERROR_TIMEOUT, 875 /** HPD was low during AUX process */ 876 AUX_RET_ERROR_HPD_DISCON, 877 /** Failed to acquire AUX engine */ 878 AUX_RET_ERROR_ENGINE_ACQUIRE, 879 /** AUX request not supported */ 880 AUX_RET_ERROR_INVALID_OPERATION, 881 /** AUX process not available */ 882 AUX_RET_ERROR_PROTOCOL_ERROR, 883 }; 884 885 /** 886 * enum aux_channel_type - DP AUX channel type listing. 887 */ 888 enum aux_channel_type { 889 /** AUX thru Legacy DP AUX */ 890 AUX_CHANNEL_LEGACY_DDC, 891 /** AUX thru DPIA DP tunneling */ 892 AUX_CHANNEL_DPIA 893 }; 894 895 /** 896 * struct aux_transaction_parameters - DP AUX request transaction data 897 */ 898 struct aux_transaction_parameters { 899 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 900 uint8_t action; /**< enum dp_aux_request_action */ 901 uint8_t length; /**< DP AUX request data length */ 902 uint8_t reserved; /**< For future use */ 903 uint32_t address; /**< DP AUX address */ 904 uint8_t data[16]; /**< DP AUX write data */ 905 }; 906 907 /** 908 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 909 */ 910 struct dmub_cmd_dp_aux_control_data { 911 uint8_t instance; /**< AUX instance or DPIA instance */ 912 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 913 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 914 uint8_t reserved0; /**< For future use */ 915 uint16_t timeout; /**< timeout time in us */ 916 uint16_t reserved1; /**< For future use */ 917 enum aux_channel_type type; /**< enum aux_channel_type */ 918 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 919 }; 920 921 /** 922 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 923 */ 924 struct dmub_rb_cmd_dp_aux_access { 925 /** 926 * Command header. 927 */ 928 struct dmub_cmd_header header; 929 /** 930 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 931 */ 932 struct dmub_cmd_dp_aux_control_data aux_control; 933 }; 934 935 /** 936 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 937 */ 938 struct dmub_rb_cmd_outbox1_enable { 939 /** 940 * Command header. 941 */ 942 struct dmub_cmd_header header; 943 /** 944 * enable: 0x0 -> disable outbox1 notification (default value) 945 * 0x1 -> enable outbox1 notification 946 */ 947 uint32_t enable; 948 }; 949 950 /* DP AUX Reply command - OutBox Cmd */ 951 /** 952 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 953 */ 954 struct aux_reply_data { 955 /** 956 * Aux cmd 957 */ 958 uint8_t command; 959 /** 960 * Aux reply data length (max: 16 bytes) 961 */ 962 uint8_t length; 963 /** 964 * Alignment only 965 */ 966 uint8_t pad[2]; 967 /** 968 * Aux reply data 969 */ 970 uint8_t data[16]; 971 }; 972 973 /** 974 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 975 */ 976 struct aux_reply_control_data { 977 /** 978 * Reserved for future use 979 */ 980 uint32_t handle; 981 /** 982 * Aux Instance 983 */ 984 uint8_t instance; 985 /** 986 * Aux transaction result: definition in enum aux_return_code_type 987 */ 988 uint8_t result; 989 /** 990 * Alignment only 991 */ 992 uint16_t pad; 993 }; 994 995 /** 996 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 997 */ 998 struct dmub_rb_cmd_dp_aux_reply { 999 /** 1000 * Command header. 1001 */ 1002 struct dmub_cmd_header header; 1003 /** 1004 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1005 */ 1006 struct aux_reply_control_data control; 1007 /** 1008 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1009 */ 1010 struct aux_reply_data reply_data; 1011 }; 1012 1013 /* DP HPD Notify command - OutBox Cmd */ 1014 /** 1015 * DP HPD Type 1016 */ 1017 enum dp_hpd_type { 1018 /** 1019 * Normal DP HPD 1020 */ 1021 DP_HPD = 0, 1022 /** 1023 * DP HPD short pulse 1024 */ 1025 DP_IRQ 1026 }; 1027 1028 /** 1029 * DP HPD Status 1030 */ 1031 enum dp_hpd_status { 1032 /** 1033 * DP_HPD status low 1034 */ 1035 DP_HPD_UNPLUG = 0, 1036 /** 1037 * DP_HPD status high 1038 */ 1039 DP_HPD_PLUG 1040 }; 1041 1042 /** 1043 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1044 */ 1045 struct dp_hpd_data { 1046 /** 1047 * DP HPD instance 1048 */ 1049 uint8_t instance; 1050 /** 1051 * HPD type 1052 */ 1053 uint8_t hpd_type; 1054 /** 1055 * HPD status: only for type: DP_HPD to indicate status 1056 */ 1057 uint8_t hpd_status; 1058 /** 1059 * Alignment only 1060 */ 1061 uint8_t pad; 1062 }; 1063 1064 /** 1065 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1066 */ 1067 struct dmub_rb_cmd_dp_hpd_notify { 1068 /** 1069 * Command header. 1070 */ 1071 struct dmub_cmd_header header; 1072 /** 1073 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1074 */ 1075 struct dp_hpd_data hpd_data; 1076 }; 1077 1078 /* 1079 * Command IDs should be treated as stable ABI. 1080 * Do not reuse or modify IDs. 1081 */ 1082 1083 /** 1084 * PSR command sub-types. 1085 */ 1086 enum dmub_cmd_psr_type { 1087 /** 1088 * Set PSR version support. 1089 */ 1090 DMUB_CMD__PSR_SET_VERSION = 0, 1091 /** 1092 * Copy driver-calculated parameters to PSR state. 1093 */ 1094 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1095 /** 1096 * Enable PSR. 1097 */ 1098 DMUB_CMD__PSR_ENABLE = 2, 1099 1100 /** 1101 * Disable PSR. 1102 */ 1103 DMUB_CMD__PSR_DISABLE = 3, 1104 1105 /** 1106 * Set PSR level. 1107 * PSR level is a 16-bit value dicated by driver that 1108 * will enable/disable different functionality. 1109 */ 1110 DMUB_CMD__PSR_SET_LEVEL = 4, 1111 1112 /** 1113 * Forces PSR enabled until an explicit PSR disable call. 1114 */ 1115 DMUB_CMD__PSR_FORCE_STATIC = 5, 1116 }; 1117 1118 #ifndef TRIM_FAMS 1119 enum dmub_cmd_fams_type { 1120 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1121 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1122 }; 1123 #endif 1124 1125 /** 1126 * PSR versions. 1127 */ 1128 enum psr_version { 1129 /** 1130 * PSR version 1. 1131 */ 1132 PSR_VERSION_1 = 0, 1133 /** 1134 * PSR not supported. 1135 */ 1136 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1137 }; 1138 1139 /** 1140 * enum dmub_cmd_mall_type - MALL commands 1141 */ 1142 enum dmub_cmd_mall_type { 1143 /** 1144 * Allows display refresh from MALL. 1145 */ 1146 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1147 /** 1148 * Disallows display refresh from MALL. 1149 */ 1150 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1151 /** 1152 * Cursor copy for MALL. 1153 */ 1154 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1155 /** 1156 * Controls DF requests. 1157 */ 1158 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1159 }; 1160 1161 1162 /** 1163 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1164 */ 1165 struct dmub_cmd_psr_copy_settings_data { 1166 /** 1167 * Flags that can be set by driver to change some PSR behaviour. 1168 */ 1169 union dmub_psr_debug_flags debug; 1170 /** 1171 * 16-bit value dicated by driver that will enable/disable different functionality. 1172 */ 1173 uint16_t psr_level; 1174 /** 1175 * DPP HW instance. 1176 */ 1177 uint8_t dpp_inst; 1178 /** 1179 * MPCC HW instance. 1180 * Not used in dmub fw, 1181 * dmub fw will get active opp by reading odm registers. 1182 */ 1183 uint8_t mpcc_inst; 1184 /** 1185 * OPP HW instance. 1186 * Not used in dmub fw, 1187 * dmub fw will get active opp by reading odm registers. 1188 */ 1189 uint8_t opp_inst; 1190 /** 1191 * OTG HW instance. 1192 */ 1193 uint8_t otg_inst; 1194 /** 1195 * DIG FE HW instance. 1196 */ 1197 uint8_t digfe_inst; 1198 /** 1199 * DIG BE HW instance. 1200 */ 1201 uint8_t digbe_inst; 1202 /** 1203 * DP PHY HW instance. 1204 */ 1205 uint8_t dpphy_inst; 1206 /** 1207 * AUX HW instance. 1208 */ 1209 uint8_t aux_inst; 1210 /** 1211 * Determines if SMU optimzations are enabled/disabled. 1212 */ 1213 uint8_t smu_optimizations_en; 1214 /** 1215 * Unused. 1216 * TODO: Remove. 1217 */ 1218 uint8_t frame_delay; 1219 /** 1220 * If RFB setup time is greater than the total VBLANK time, 1221 * it is not possible for the sink to capture the video frame 1222 * in the same frame the SDP is sent. In this case, 1223 * the frame capture indication bit should be set and an extra 1224 * static frame should be transmitted to the sink. 1225 */ 1226 uint8_t frame_cap_ind; 1227 /** 1228 * Explicit padding to 4 byte boundary. 1229 */ 1230 uint8_t pad[2]; 1231 /** 1232 * Multi-display optimizations are implemented on certain ASICs. 1233 */ 1234 uint8_t multi_disp_optimizations_en; 1235 /** 1236 * The last possible line SDP may be transmitted without violating 1237 * the RFB setup time or entering the active video frame. 1238 */ 1239 uint16_t init_sdp_deadline; 1240 /** 1241 * Explicit padding to 4 byte boundary. 1242 */ 1243 uint16_t pad2; 1244 /** 1245 * Length of each horizontal line in us. 1246 */ 1247 uint32_t line_time_in_us; 1248 }; 1249 1250 /** 1251 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1252 */ 1253 struct dmub_rb_cmd_psr_copy_settings { 1254 /** 1255 * Command header. 1256 */ 1257 struct dmub_cmd_header header; 1258 /** 1259 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1260 */ 1261 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1262 }; 1263 1264 /** 1265 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1266 */ 1267 struct dmub_cmd_psr_set_level_data { 1268 /** 1269 * 16-bit value dicated by driver that will enable/disable different functionality. 1270 */ 1271 uint16_t psr_level; 1272 /** 1273 * Explicit padding to 4 byte boundary. 1274 */ 1275 uint8_t pad[2]; 1276 }; 1277 1278 /** 1279 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1280 */ 1281 struct dmub_rb_cmd_psr_set_level { 1282 /** 1283 * Command header. 1284 */ 1285 struct dmub_cmd_header header; 1286 /** 1287 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1288 */ 1289 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1290 }; 1291 1292 /** 1293 * Definition of a DMUB_CMD__PSR_ENABLE command. 1294 * PSR enable/disable is controlled using the sub_type. 1295 */ 1296 struct dmub_rb_cmd_psr_enable { 1297 /** 1298 * Command header. 1299 */ 1300 struct dmub_cmd_header header; 1301 }; 1302 1303 /** 1304 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1305 */ 1306 struct dmub_cmd_psr_set_version_data { 1307 /** 1308 * PSR version that FW should implement. 1309 */ 1310 enum psr_version version; 1311 }; 1312 1313 /** 1314 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1315 */ 1316 struct dmub_rb_cmd_psr_set_version { 1317 /** 1318 * Command header. 1319 */ 1320 struct dmub_cmd_header header; 1321 /** 1322 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1323 */ 1324 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1325 }; 1326 1327 /** 1328 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1329 */ 1330 struct dmub_rb_cmd_psr_force_static { 1331 /** 1332 * Command header. 1333 */ 1334 struct dmub_cmd_header header; 1335 }; 1336 1337 /** 1338 * Set of HW components that can be locked. 1339 */ 1340 union dmub_hw_lock_flags { 1341 /** 1342 * Set of HW components that can be locked. 1343 */ 1344 struct { 1345 /** 1346 * Lock/unlock OTG master update lock. 1347 */ 1348 uint8_t lock_pipe : 1; 1349 /** 1350 * Lock/unlock cursor. 1351 */ 1352 uint8_t lock_cursor : 1; 1353 /** 1354 * Lock/unlock global update lock. 1355 */ 1356 uint8_t lock_dig : 1; 1357 /** 1358 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1359 */ 1360 uint8_t triple_buffer_lock : 1; 1361 } bits; 1362 1363 /** 1364 * Union for HW Lock flags. 1365 */ 1366 uint8_t u8All; 1367 }; 1368 1369 /** 1370 * Instances of HW to be locked. 1371 */ 1372 struct dmub_hw_lock_inst_flags { 1373 /** 1374 * OTG HW instance for OTG master update lock. 1375 */ 1376 uint8_t otg_inst; 1377 /** 1378 * OPP instance for cursor lock. 1379 */ 1380 uint8_t opp_inst; 1381 /** 1382 * OTG HW instance for global update lock. 1383 * TODO: Remove, and re-use otg_inst. 1384 */ 1385 uint8_t dig_inst; 1386 /** 1387 * Explicit pad to 4 byte boundary. 1388 */ 1389 uint8_t pad; 1390 }; 1391 1392 /** 1393 * Clients that can acquire the HW Lock Manager. 1394 */ 1395 enum hw_lock_client { 1396 /** 1397 * Driver is the client of HW Lock Manager. 1398 */ 1399 HW_LOCK_CLIENT_DRIVER = 0, 1400 /** 1401 * FW is the client of HW Lock Manager. 1402 */ 1403 HW_LOCK_CLIENT_FW, 1404 /** 1405 * Invalid client. 1406 */ 1407 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1408 }; 1409 1410 /** 1411 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1412 */ 1413 struct dmub_cmd_lock_hw_data { 1414 /** 1415 * Specifies the client accessing HW Lock Manager. 1416 */ 1417 enum hw_lock_client client; 1418 /** 1419 * HW instances to be locked. 1420 */ 1421 struct dmub_hw_lock_inst_flags inst_flags; 1422 /** 1423 * Which components to be locked. 1424 */ 1425 union dmub_hw_lock_flags hw_locks; 1426 /** 1427 * Specifies lock/unlock. 1428 */ 1429 uint8_t lock; 1430 /** 1431 * HW can be unlocked separately from releasing the HW Lock Mgr. 1432 * This flag is set if the client wishes to release the object. 1433 */ 1434 uint8_t should_release; 1435 /** 1436 * Explicit padding to 4 byte boundary. 1437 */ 1438 uint8_t pad; 1439 }; 1440 1441 /** 1442 * Definition of a DMUB_CMD__HW_LOCK command. 1443 * Command is used by driver and FW. 1444 */ 1445 struct dmub_rb_cmd_lock_hw { 1446 /** 1447 * Command header. 1448 */ 1449 struct dmub_cmd_header header; 1450 /** 1451 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1452 */ 1453 struct dmub_cmd_lock_hw_data lock_hw_data; 1454 }; 1455 1456 /** 1457 * ABM command sub-types. 1458 */ 1459 enum dmub_cmd_abm_type { 1460 /** 1461 * Initialize parameters for ABM algorithm. 1462 * Data is passed through an indirect buffer. 1463 */ 1464 DMUB_CMD__ABM_INIT_CONFIG = 0, 1465 /** 1466 * Set OTG and panel HW instance. 1467 */ 1468 DMUB_CMD__ABM_SET_PIPE = 1, 1469 /** 1470 * Set user requested backklight level. 1471 */ 1472 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1473 /** 1474 * Set ABM operating/aggression level. 1475 */ 1476 DMUB_CMD__ABM_SET_LEVEL = 3, 1477 /** 1478 * Set ambient light level. 1479 */ 1480 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1481 /** 1482 * Enable/disable fractional duty cycle for backlight PWM. 1483 */ 1484 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1485 }; 1486 1487 /** 1488 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1489 * Requirements: 1490 * - Padded explicitly to 32-bit boundary. 1491 * - Must ensure this structure matches the one on driver-side, 1492 * otherwise it won't be aligned. 1493 */ 1494 struct abm_config_table { 1495 /** 1496 * Gamma curve thresholds, used for crgb conversion. 1497 */ 1498 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1499 /** 1500 * Gamma curve offsets, used for crgb conversion. 1501 */ 1502 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1503 /** 1504 * Gamma curve slopes, used for crgb conversion. 1505 */ 1506 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1507 /** 1508 * Custom backlight curve thresholds. 1509 */ 1510 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 1511 /** 1512 * Custom backlight curve offsets. 1513 */ 1514 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 1515 /** 1516 * Ambient light thresholds. 1517 */ 1518 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 1519 /** 1520 * Minimum programmable backlight. 1521 */ 1522 uint16_t min_abm_backlight; // 122B 1523 /** 1524 * Minimum reduction values. 1525 */ 1526 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 1527 /** 1528 * Maximum reduction values. 1529 */ 1530 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 1531 /** 1532 * Bright positive gain. 1533 */ 1534 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 1535 /** 1536 * Dark negative gain. 1537 */ 1538 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 1539 /** 1540 * Hybrid factor. 1541 */ 1542 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 1543 /** 1544 * Contrast factor. 1545 */ 1546 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 1547 /** 1548 * Deviation gain. 1549 */ 1550 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 1551 /** 1552 * Minimum knee. 1553 */ 1554 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 1555 /** 1556 * Maximum knee. 1557 */ 1558 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 1559 /** 1560 * Unused. 1561 */ 1562 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 1563 /** 1564 * Explicit padding to 4 byte boundary. 1565 */ 1566 uint8_t pad3[3]; // 229B 1567 /** 1568 * Backlight ramp reduction. 1569 */ 1570 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 1571 /** 1572 * Backlight ramp start. 1573 */ 1574 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 1575 }; 1576 1577 /** 1578 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1579 */ 1580 struct dmub_cmd_abm_set_pipe_data { 1581 /** 1582 * OTG HW instance. 1583 */ 1584 uint8_t otg_inst; 1585 1586 /** 1587 * Panel Control HW instance. 1588 */ 1589 uint8_t panel_inst; 1590 1591 /** 1592 * Controls how ABM will interpret a set pipe or set level command. 1593 */ 1594 uint8_t set_pipe_option; 1595 1596 /** 1597 * Unused. 1598 * TODO: Remove. 1599 */ 1600 uint8_t ramping_boundary; 1601 }; 1602 1603 /** 1604 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1605 */ 1606 struct dmub_rb_cmd_abm_set_pipe { 1607 /** 1608 * Command header. 1609 */ 1610 struct dmub_cmd_header header; 1611 1612 /** 1613 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1614 */ 1615 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 1616 }; 1617 1618 /** 1619 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1620 */ 1621 struct dmub_cmd_abm_set_backlight_data { 1622 /** 1623 * Number of frames to ramp to backlight user level. 1624 */ 1625 uint32_t frame_ramp; 1626 1627 /** 1628 * Requested backlight level from user. 1629 */ 1630 uint32_t backlight_user_level; 1631 }; 1632 1633 /** 1634 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 1635 */ 1636 struct dmub_rb_cmd_abm_set_backlight { 1637 /** 1638 * Command header. 1639 */ 1640 struct dmub_cmd_header header; 1641 1642 /** 1643 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1644 */ 1645 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 1646 }; 1647 1648 /** 1649 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1650 */ 1651 struct dmub_cmd_abm_set_level_data { 1652 /** 1653 * Set current ABM operating/aggression level. 1654 */ 1655 uint32_t level; 1656 }; 1657 1658 /** 1659 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 1660 */ 1661 struct dmub_rb_cmd_abm_set_level { 1662 /** 1663 * Command header. 1664 */ 1665 struct dmub_cmd_header header; 1666 1667 /** 1668 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1669 */ 1670 struct dmub_cmd_abm_set_level_data abm_set_level_data; 1671 }; 1672 1673 /** 1674 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1675 */ 1676 struct dmub_cmd_abm_set_ambient_level_data { 1677 /** 1678 * Ambient light sensor reading from OS. 1679 */ 1680 uint32_t ambient_lux; 1681 }; 1682 1683 /** 1684 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1685 */ 1686 struct dmub_rb_cmd_abm_set_ambient_level { 1687 /** 1688 * Command header. 1689 */ 1690 struct dmub_cmd_header header; 1691 1692 /** 1693 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1694 */ 1695 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 1696 }; 1697 1698 /** 1699 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1700 */ 1701 struct dmub_cmd_abm_set_pwm_frac_data { 1702 /** 1703 * Enable/disable fractional duty cycle for backlight PWM. 1704 * TODO: Convert to uint8_t. 1705 */ 1706 uint32_t fractional_pwm; 1707 }; 1708 1709 /** 1710 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 1711 */ 1712 struct dmub_rb_cmd_abm_set_pwm_frac { 1713 /** 1714 * Command header. 1715 */ 1716 struct dmub_cmd_header header; 1717 1718 /** 1719 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 1720 */ 1721 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 1722 }; 1723 1724 /** 1725 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 1726 */ 1727 struct dmub_cmd_abm_init_config_data { 1728 /** 1729 * Location of indirect buffer used to pass init data to ABM. 1730 */ 1731 union dmub_addr src; 1732 1733 /** 1734 * Indirect buffer length. 1735 */ 1736 uint16_t bytes; 1737 }; 1738 1739 /** 1740 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 1741 */ 1742 struct dmub_rb_cmd_abm_init_config { 1743 /** 1744 * Command header. 1745 */ 1746 struct dmub_cmd_header header; 1747 1748 /** 1749 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 1750 */ 1751 struct dmub_cmd_abm_init_config_data abm_init_config_data; 1752 }; 1753 1754 /** 1755 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 1756 */ 1757 struct dmub_cmd_query_feature_caps_data { 1758 /** 1759 * DMUB feature capabilities. 1760 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 1761 */ 1762 struct dmub_feature_caps feature_caps; 1763 }; 1764 1765 /** 1766 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 1767 */ 1768 struct dmub_rb_cmd_query_feature_caps { 1769 /** 1770 * Command header. 1771 */ 1772 struct dmub_cmd_header header; 1773 /** 1774 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 1775 */ 1776 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 1777 }; 1778 1779 struct dmub_optc_state { 1780 uint32_t v_total_max; 1781 uint32_t v_total_min; 1782 uint32_t v_total_mid; 1783 uint32_t v_total_mid_frame_num; 1784 uint32_t tg_inst; 1785 uint32_t enable_manual_trigger; 1786 uint32_t clear_force_vsync; 1787 }; 1788 1789 struct dmub_rb_cmd_drr_update { 1790 struct dmub_cmd_header header; 1791 struct dmub_optc_state dmub_optc_state_req; 1792 }; 1793 1794 #ifndef TRIM_FAMS 1795 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 1796 uint32_t pix_clk_100hz; 1797 uint32_t min_refresh_in_uhz; 1798 uint32_t max_ramp_step; 1799 }; 1800 1801 struct dmub_cmd_fw_assisted_mclk_switch_config { 1802 uint32_t fams_enabled; 1803 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 1804 }; 1805 1806 struct dmub_rb_cmd_fw_assisted_mclk_switch { 1807 struct dmub_cmd_header header; 1808 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 1809 }; 1810 #endif 1811 1812 /** 1813 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1814 */ 1815 struct dmub_cmd_lvtma_control_data { 1816 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 1817 uint8_t reserved_0[3]; /**< For future use */ 1818 uint8_t panel_inst; /**< LVTMA control instance */ 1819 uint8_t reserved_1[3]; /**< For future use */ 1820 }; 1821 1822 /** 1823 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1824 */ 1825 struct dmub_rb_cmd_lvtma_control { 1826 /** 1827 * Command header. 1828 */ 1829 struct dmub_cmd_header header; 1830 /** 1831 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1832 */ 1833 struct dmub_cmd_lvtma_control_data data; 1834 }; 1835 1836 /** 1837 * union dmub_rb_cmd - DMUB inbox command. 1838 */ 1839 union dmub_rb_cmd { 1840 struct dmub_rb_cmd_lock_hw lock_hw; 1841 /** 1842 * Elements shared with all commands. 1843 */ 1844 struct dmub_rb_cmd_common cmd_common; 1845 /** 1846 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 1847 */ 1848 struct dmub_rb_cmd_read_modify_write read_modify_write; 1849 /** 1850 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 1851 */ 1852 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 1853 /** 1854 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 1855 */ 1856 struct dmub_rb_cmd_burst_write burst_write; 1857 /** 1858 * Definition of a DMUB_CMD__REG_REG_WAIT command. 1859 */ 1860 struct dmub_rb_cmd_reg_wait reg_wait; 1861 /** 1862 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 1863 */ 1864 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 1865 /** 1866 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 1867 */ 1868 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 1869 /** 1870 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 1871 */ 1872 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 1873 /** 1874 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 1875 */ 1876 struct dmub_rb_cmd_dpphy_init dpphy_init; 1877 /** 1878 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 1879 */ 1880 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 1881 /** 1882 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1883 */ 1884 struct dmub_rb_cmd_psr_set_version psr_set_version; 1885 /** 1886 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1887 */ 1888 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 1889 /** 1890 * Definition of a DMUB_CMD__PSR_ENABLE command. 1891 */ 1892 struct dmub_rb_cmd_psr_enable psr_enable; 1893 /** 1894 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1895 */ 1896 struct dmub_rb_cmd_psr_set_level psr_set_level; 1897 /** 1898 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1899 */ 1900 struct dmub_rb_cmd_psr_force_static psr_force_static; 1901 /** 1902 * Definition of a DMUB_CMD__PLAT_54186_WA command. 1903 */ 1904 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 1905 /** 1906 * Definition of a DMUB_CMD__MALL command. 1907 */ 1908 struct dmub_rb_cmd_mall mall; 1909 /** 1910 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1911 */ 1912 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 1913 1914 /** 1915 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 1916 */ 1917 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 1918 1919 /** 1920 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 1921 */ 1922 struct dmub_rb_cmd_abm_set_level abm_set_level; 1923 1924 /** 1925 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1926 */ 1927 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 1928 1929 /** 1930 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 1931 */ 1932 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 1933 1934 /** 1935 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 1936 */ 1937 struct dmub_rb_cmd_abm_init_config abm_init_config; 1938 1939 /** 1940 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1941 */ 1942 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 1943 1944 /** 1945 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1946 */ 1947 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 1948 1949 /** 1950 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 1951 */ 1952 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 1953 struct dmub_rb_cmd_drr_update drr_update; 1954 #ifndef TRIM_FAMS 1955 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 1956 #endif 1957 /** 1958 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 1959 */ 1960 struct dmub_rb_cmd_lvtma_control lvtma_control; 1961 }; 1962 1963 /** 1964 * union dmub_rb_out_cmd - Outbox command 1965 */ 1966 union dmub_rb_out_cmd { 1967 /** 1968 * Parameters common to every command. 1969 */ 1970 struct dmub_rb_cmd_common cmd_common; 1971 /** 1972 * AUX reply command. 1973 */ 1974 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 1975 /** 1976 * HPD notify command. 1977 */ 1978 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 1979 }; 1980 #pragma pack(pop) 1981 1982 1983 //============================================================================== 1984 //</DMUB_CMD>=================================================================== 1985 //============================================================================== 1986 //< DMUB_RB>==================================================================== 1987 //============================================================================== 1988 1989 #if defined(__cplusplus) 1990 extern "C" { 1991 #endif 1992 1993 /** 1994 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 1995 */ 1996 struct dmub_rb_init_params { 1997 void *ctx; /**< Caller provided context pointer */ 1998 void *base_address; /**< CPU base address for ring's data */ 1999 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2000 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2001 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2002 }; 2003 2004 /** 2005 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2006 */ 2007 struct dmub_rb { 2008 void *base_address; /**< CPU address for the ring's data */ 2009 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2010 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2011 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2012 2013 void *ctx; /**< Caller provided context pointer */ 2014 void *dmub; /**< Pointer to the DMUB interface */ 2015 }; 2016 2017 /** 2018 * @brief Checks if the ringbuffer is empty. 2019 * 2020 * @param rb DMUB Ringbuffer 2021 * @return true if empty 2022 * @return false otherwise 2023 */ 2024 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2025 { 2026 return (rb->wrpt == rb->rptr); 2027 } 2028 2029 /** 2030 * @brief Checks if the ringbuffer is full 2031 * 2032 * @param rb DMUB Ringbuffer 2033 * @return true if full 2034 * @return false otherwise 2035 */ 2036 static inline bool dmub_rb_full(struct dmub_rb *rb) 2037 { 2038 uint32_t data_count; 2039 2040 if (rb->wrpt >= rb->rptr) 2041 data_count = rb->wrpt - rb->rptr; 2042 else 2043 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2044 2045 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2046 } 2047 2048 /** 2049 * @brief Pushes a command into the ringbuffer 2050 * 2051 * @param rb DMUB ringbuffer 2052 * @param cmd The command to push 2053 * @return true if the ringbuffer was not full 2054 * @return false otherwise 2055 */ 2056 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2057 const union dmub_rb_cmd *cmd) 2058 { 2059 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 2060 const uint64_t *src = (const uint64_t *)cmd; 2061 uint8_t i; 2062 2063 if (dmub_rb_full(rb)) 2064 return false; 2065 2066 // copying data 2067 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2068 *dst++ = *src++; 2069 2070 rb->wrpt += DMUB_RB_CMD_SIZE; 2071 2072 if (rb->wrpt >= rb->capacity) 2073 rb->wrpt %= rb->capacity; 2074 2075 return true; 2076 } 2077 2078 /** 2079 * @brief Pushes a command into the DMUB outbox ringbuffer 2080 * 2081 * @param rb DMUB outbox ringbuffer 2082 * @param cmd Outbox command 2083 * @return true if not full 2084 * @return false otherwise 2085 */ 2086 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2087 const union dmub_rb_out_cmd *cmd) 2088 { 2089 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2090 const uint8_t *src = (uint8_t *)cmd; 2091 2092 if (dmub_rb_full(rb)) 2093 return false; 2094 2095 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2096 2097 rb->wrpt += DMUB_RB_CMD_SIZE; 2098 2099 if (rb->wrpt >= rb->capacity) 2100 rb->wrpt %= rb->capacity; 2101 2102 return true; 2103 } 2104 2105 /** 2106 * @brief Returns the next unprocessed command in the ringbuffer. 2107 * 2108 * @param rb DMUB ringbuffer 2109 * @param cmd The command to return 2110 * @return true if not empty 2111 * @return false otherwise 2112 */ 2113 static inline bool dmub_rb_front(struct dmub_rb *rb, 2114 union dmub_rb_cmd **cmd) 2115 { 2116 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2117 2118 if (dmub_rb_empty(rb)) 2119 return false; 2120 2121 *cmd = (union dmub_rb_cmd *)rb_cmd; 2122 2123 return true; 2124 } 2125 2126 /** 2127 * @brief Returns the next unprocessed command in the outbox. 2128 * 2129 * @param rb DMUB outbox ringbuffer 2130 * @param cmd The outbox command to return 2131 * @return true if not empty 2132 * @return false otherwise 2133 */ 2134 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2135 union dmub_rb_out_cmd *cmd) 2136 { 2137 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 2138 uint64_t *dst = (uint64_t *)cmd; 2139 uint8_t i; 2140 2141 if (dmub_rb_empty(rb)) 2142 return false; 2143 2144 // copying data 2145 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2146 *dst++ = *src++; 2147 2148 return true; 2149 } 2150 2151 /** 2152 * @brief Removes the front entry in the ringbuffer. 2153 * 2154 * @param rb DMUB ringbuffer 2155 * @return true if the command was removed 2156 * @return false if there were no commands 2157 */ 2158 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 2159 { 2160 if (dmub_rb_empty(rb)) 2161 return false; 2162 2163 rb->rptr += DMUB_RB_CMD_SIZE; 2164 2165 if (rb->rptr >= rb->capacity) 2166 rb->rptr %= rb->capacity; 2167 2168 return true; 2169 } 2170 2171 /** 2172 * @brief Flushes commands in the ringbuffer to framebuffer memory. 2173 * 2174 * Avoids a race condition where DMCUB accesses memory while 2175 * there are still writes in flight to framebuffer. 2176 * 2177 * @param rb DMUB ringbuffer 2178 */ 2179 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 2180 { 2181 uint32_t rptr = rb->rptr; 2182 uint32_t wptr = rb->wrpt; 2183 2184 while (rptr != wptr) { 2185 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 2186 uint8_t i; 2187 2188 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2189 *data++; 2190 2191 rptr += DMUB_RB_CMD_SIZE; 2192 if (rptr >= rb->capacity) 2193 rptr %= rb->capacity; 2194 } 2195 } 2196 2197 /** 2198 * @brief Initializes a DMCUB ringbuffer 2199 * 2200 * @param rb DMUB ringbuffer 2201 * @param init_params initial configuration for the ringbuffer 2202 */ 2203 static inline void dmub_rb_init(struct dmub_rb *rb, 2204 struct dmub_rb_init_params *init_params) 2205 { 2206 rb->base_address = init_params->base_address; 2207 rb->capacity = init_params->capacity; 2208 rb->rptr = init_params->read_ptr; 2209 rb->wrpt = init_params->write_ptr; 2210 } 2211 2212 /** 2213 * @brief Copies output data from in/out commands into the given command. 2214 * 2215 * @param rb DMUB ringbuffer 2216 * @param cmd Command to copy data into 2217 */ 2218 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 2219 union dmub_rb_cmd *cmd) 2220 { 2221 // Copy rb entry back into command 2222 uint8_t *rd_ptr = (rb->rptr == 0) ? 2223 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 2224 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 2225 2226 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 2227 } 2228 2229 #if defined(__cplusplus) 2230 } 2231 #endif 2232 2233 //============================================================================== 2234 //</DMUB_RB>==================================================================== 2235 //============================================================================== 2236 2237 #endif /* _DMUB_CMD_H_ */ 2238