1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of streams on any ASIC. */ 96 #define DMUB_MAX_STREAMS 6 97 98 /* Maximum number of planes on any ASIC. */ 99 #define DMUB_MAX_PLANES 6 100 101 /* Trace buffer offset for entry */ 102 #define TRACE_BUFFER_ENTRY_OFFSET 16 103 104 /** 105 * Maximum number of dirty rects supported by FW. 106 */ 107 #define DMUB_MAX_DIRTY_RECTS 3 108 109 /** 110 * 111 * PSR control version legacy 112 */ 113 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 114 /** 115 * PSR control version with multi edp support 116 */ 117 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 118 119 120 /** 121 * ABM control version legacy 122 */ 123 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 124 125 /** 126 * ABM control version with multi edp support 127 */ 128 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 129 130 /** 131 * Physical framebuffer address location, 64-bit. 132 */ 133 #ifndef PHYSICAL_ADDRESS_LOC 134 #define PHYSICAL_ADDRESS_LOC union large_integer 135 #endif 136 137 /** 138 * OS/FW agnostic memcpy 139 */ 140 #ifndef dmub_memcpy 141 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 142 #endif 143 144 /** 145 * OS/FW agnostic memset 146 */ 147 #ifndef dmub_memset 148 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 149 #endif 150 151 #if defined(__cplusplus) 152 extern "C" { 153 #endif 154 155 /** 156 * OS/FW agnostic udelay 157 */ 158 #ifndef dmub_udelay 159 #define dmub_udelay(microseconds) udelay(microseconds) 160 #endif 161 162 /** 163 * union dmub_addr - DMUB physical/virtual 64-bit address. 164 */ 165 union dmub_addr { 166 struct { 167 uint32_t low_part; /**< Lower 32 bits */ 168 uint32_t high_part; /**< Upper 32 bits */ 169 } u; /*<< Low/high bit access */ 170 uint64_t quad_part; /*<< 64 bit address */ 171 }; 172 173 /** 174 * Dirty rect definition. 175 */ 176 struct dmub_rect { 177 /** 178 * Dirty rect x offset. 179 */ 180 uint32_t x; 181 182 /** 183 * Dirty rect y offset. 184 */ 185 uint32_t y; 186 187 /** 188 * Dirty rect width. 189 */ 190 uint32_t width; 191 192 /** 193 * Dirty rect height. 194 */ 195 uint32_t height; 196 }; 197 198 /** 199 * Flags that can be set by driver to change some PSR behaviour. 200 */ 201 union dmub_psr_debug_flags { 202 /** 203 * Debug flags. 204 */ 205 struct { 206 /** 207 * Enable visual confirm in FW. 208 */ 209 uint32_t visual_confirm : 1; 210 211 /** 212 * Force all selective updates to bw full frame updates. 213 */ 214 uint32_t force_full_frame_update : 1; 215 216 /** 217 * Use HW Lock Mgr object to do HW locking in FW. 218 */ 219 uint32_t use_hw_lock_mgr : 1; 220 221 /** 222 * Use TPS3 signal when restore main link. 223 */ 224 uint32_t force_wakeup_by_tps3 : 1; 225 } bitfields; 226 227 /** 228 * Union for debug flags. 229 */ 230 uint32_t u32All; 231 }; 232 233 /** 234 * DMUB feature capabilities. 235 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 236 */ 237 struct dmub_feature_caps { 238 /** 239 * Max PSR version supported by FW. 240 */ 241 uint8_t psr; 242 uint8_t reserved[7]; 243 }; 244 245 #if defined(__cplusplus) 246 } 247 #endif 248 249 //============================================================================== 250 //</DMUB_TYPES>================================================================= 251 //============================================================================== 252 //< DMUB_META>================================================================== 253 //============================================================================== 254 #pragma pack(push, 1) 255 256 /* Magic value for identifying dmub_fw_meta_info */ 257 #define DMUB_FW_META_MAGIC 0x444D5542 258 259 /* Offset from the end of the file to the dmub_fw_meta_info */ 260 #define DMUB_FW_META_OFFSET 0x24 261 262 /** 263 * struct dmub_fw_meta_info - metadata associated with fw binary 264 * 265 * NOTE: This should be considered a stable API. Fields should 266 * not be repurposed or reordered. New fields should be 267 * added instead to extend the structure. 268 * 269 * @magic_value: magic value identifying DMUB firmware meta info 270 * @fw_region_size: size of the firmware state region 271 * @trace_buffer_size: size of the tracebuffer region 272 * @fw_version: the firmware version information 273 * @dal_fw: 1 if the firmware is DAL 274 */ 275 struct dmub_fw_meta_info { 276 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 277 uint32_t fw_region_size; /**< size of the firmware state region */ 278 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 279 uint32_t fw_version; /**< the firmware version information */ 280 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 281 uint8_t reserved[3]; /**< padding bits */ 282 }; 283 284 /** 285 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 286 */ 287 union dmub_fw_meta { 288 struct dmub_fw_meta_info info; /**< metadata info */ 289 uint8_t reserved[64]; /**< padding bits */ 290 }; 291 292 #pragma pack(pop) 293 294 //============================================================================== 295 //< DMUB Trace Buffer>================================================================ 296 //============================================================================== 297 /** 298 * dmub_trace_code_t - firmware trace code, 32-bits 299 */ 300 typedef uint32_t dmub_trace_code_t; 301 302 /** 303 * struct dmcub_trace_buf_entry - Firmware trace entry 304 */ 305 struct dmcub_trace_buf_entry { 306 dmub_trace_code_t trace_code; /**< trace code for the event */ 307 uint32_t tick_count; /**< the tick count at time of trace */ 308 uint32_t param0; /**< trace defined parameter 0 */ 309 uint32_t param1; /**< trace defined parameter 1 */ 310 }; 311 312 //============================================================================== 313 //< DMUB_STATUS>================================================================ 314 //============================================================================== 315 316 /** 317 * DMCUB scratch registers can be used to determine firmware status. 318 * Current scratch register usage is as follows: 319 * 320 * SCRATCH0: FW Boot Status register 321 * SCRATCH5: LVTMA Status Register 322 * SCRATCH15: FW Boot Options register 323 */ 324 325 /** 326 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 327 */ 328 union dmub_fw_boot_status { 329 struct { 330 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 331 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 332 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 333 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 334 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 335 uint32_t reserved : 1; 336 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 337 338 } bits; /**< status bits */ 339 uint32_t all; /**< 32-bit access to status bits */ 340 }; 341 342 /** 343 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 344 */ 345 enum dmub_fw_boot_status_bit { 346 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 347 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 348 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 349 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 350 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 351 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 352 }; 353 354 /* Register bit definition for SCRATCH5 */ 355 union dmub_lvtma_status { 356 struct { 357 uint32_t psp_ok : 1; 358 uint32_t edp_on : 1; 359 uint32_t reserved : 30; 360 } bits; 361 uint32_t all; 362 }; 363 364 enum dmub_lvtma_status_bit { 365 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 366 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 367 }; 368 369 /** 370 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 371 */ 372 union dmub_fw_boot_options { 373 struct { 374 uint32_t pemu_env : 1; /**< 1 if PEMU */ 375 uint32_t fpga_env : 1; /**< 1 if FPGA */ 376 uint32_t optimized_init : 1; /**< 1 if optimized init */ 377 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 378 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 379 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 380 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 381 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 382 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 383 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 384 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 385 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 386 uint32_t power_optimization: 1; 387 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 388 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 389 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 390 391 uint32_t reserved : 17; /**< reserved */ 392 } bits; /**< boot bits */ 393 uint32_t all; /**< 32-bit access to bits */ 394 }; 395 396 enum dmub_fw_boot_options_bit { 397 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 398 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 399 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 400 }; 401 402 //============================================================================== 403 //</DMUB_STATUS>================================================================ 404 //============================================================================== 405 //< DMUB_VBIOS>================================================================= 406 //============================================================================== 407 408 /* 409 * enum dmub_cmd_vbios_type - VBIOS commands. 410 * 411 * Command IDs should be treated as stable ABI. 412 * Do not reuse or modify IDs. 413 */ 414 enum dmub_cmd_vbios_type { 415 /** 416 * Configures the DIG encoder. 417 */ 418 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 419 /** 420 * Controls the PHY. 421 */ 422 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 423 /** 424 * Sets the pixel clock/symbol clock. 425 */ 426 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 427 /** 428 * Enables or disables power gating. 429 */ 430 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 431 /** 432 * Controls embedded panels. 433 */ 434 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 435 /** 436 * Query DP alt status on a transmitter. 437 */ 438 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 439 }; 440 441 //============================================================================== 442 //</DMUB_VBIOS>================================================================= 443 //============================================================================== 444 //< DMUB_GPINT>================================================================= 445 //============================================================================== 446 447 /** 448 * The shifts and masks below may alternatively be used to format and read 449 * the command register bits. 450 */ 451 452 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 453 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 454 455 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 456 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 457 458 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 459 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 460 461 /** 462 * Command responses. 463 */ 464 465 /** 466 * Return response for DMUB_GPINT__STOP_FW command. 467 */ 468 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 469 470 /** 471 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 472 */ 473 union dmub_gpint_data_register { 474 struct { 475 uint32_t param : 16; /**< 16-bit parameter */ 476 uint32_t command_code : 12; /**< GPINT command */ 477 uint32_t status : 4; /**< Command status bit */ 478 } bits; /**< GPINT bit access */ 479 uint32_t all; /**< GPINT 32-bit access */ 480 }; 481 482 /* 483 * enum dmub_gpint_command - GPINT command to DMCUB FW 484 * 485 * Command IDs should be treated as stable ABI. 486 * Do not reuse or modify IDs. 487 */ 488 enum dmub_gpint_command { 489 /** 490 * Invalid command, ignored. 491 */ 492 DMUB_GPINT__INVALID_COMMAND = 0, 493 /** 494 * DESC: Queries the firmware version. 495 * RETURN: Firmware version. 496 */ 497 DMUB_GPINT__GET_FW_VERSION = 1, 498 /** 499 * DESC: Halts the firmware. 500 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 501 */ 502 DMUB_GPINT__STOP_FW = 2, 503 /** 504 * DESC: Get PSR state from FW. 505 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 506 */ 507 DMUB_GPINT__GET_PSR_STATE = 7, 508 /** 509 * DESC: Notifies DMCUB of the currently active streams. 510 * ARGS: Stream mask, 1 bit per active stream index. 511 */ 512 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 513 /** 514 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 515 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 516 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 517 * RETURN: PSR residency in milli-percent. 518 */ 519 DMUB_GPINT__PSR_RESIDENCY = 9, 520 521 /** 522 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 523 */ 524 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 525 }; 526 527 /** 528 * INBOX0 generic command definition 529 */ 530 union dmub_inbox0_cmd_common { 531 struct { 532 uint32_t command_code: 8; /**< INBOX0 command code */ 533 uint32_t param: 24; /**< 24-bit parameter */ 534 } bits; 535 uint32_t all; 536 }; 537 538 /** 539 * INBOX0 hw_lock command definition 540 */ 541 union dmub_inbox0_cmd_lock_hw { 542 struct { 543 uint32_t command_code: 8; 544 545 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 546 uint32_t hw_lock_client: 2; 547 548 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 549 uint32_t otg_inst: 3; 550 uint32_t opp_inst: 3; 551 uint32_t dig_inst: 3; 552 553 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 554 uint32_t lock_pipe: 1; 555 uint32_t lock_cursor: 1; 556 uint32_t lock_dig: 1; 557 uint32_t triple_buffer_lock: 1; 558 559 uint32_t lock: 1; /**< Lock */ 560 uint32_t should_release: 1; /**< Release */ 561 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 562 } bits; 563 uint32_t all; 564 }; 565 566 union dmub_inbox0_data_register { 567 union dmub_inbox0_cmd_common inbox0_cmd_common; 568 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 569 }; 570 571 enum dmub_inbox0_command { 572 /** 573 * DESC: Invalid command, ignored. 574 */ 575 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 576 /** 577 * DESC: Notification to acquire/release HW lock 578 * ARGS: 579 */ 580 DMUB_INBOX0_CMD__HW_LOCK = 1, 581 }; 582 //============================================================================== 583 //</DMUB_GPINT>================================================================= 584 //============================================================================== 585 //< DMUB_CMD>=================================================================== 586 //============================================================================== 587 588 /** 589 * Size in bytes of each DMUB command. 590 */ 591 #define DMUB_RB_CMD_SIZE 64 592 593 /** 594 * Maximum number of items in the DMUB ringbuffer. 595 */ 596 #define DMUB_RB_MAX_ENTRY 128 597 598 /** 599 * Ringbuffer size in bytes. 600 */ 601 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 602 603 /** 604 * REG_SET mask for reg offload. 605 */ 606 #define REG_SET_MASK 0xFFFF 607 608 /* 609 * enum dmub_cmd_type - DMUB inbox command. 610 * 611 * Command IDs should be treated as stable ABI. 612 * Do not reuse or modify IDs. 613 */ 614 enum dmub_cmd_type { 615 /** 616 * Invalid command. 617 */ 618 DMUB_CMD__NULL = 0, 619 /** 620 * Read modify write register sequence offload. 621 */ 622 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 623 /** 624 * Field update register sequence offload. 625 */ 626 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 627 /** 628 * Burst write sequence offload. 629 */ 630 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 631 /** 632 * Reg wait sequence offload. 633 */ 634 DMUB_CMD__REG_REG_WAIT = 4, 635 /** 636 * Workaround to avoid HUBP underflow during NV12 playback. 637 */ 638 DMUB_CMD__PLAT_54186_WA = 5, 639 /** 640 * Command type used to query FW feature caps. 641 */ 642 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 643 /** 644 * Command type used for all PSR commands. 645 */ 646 DMUB_CMD__PSR = 64, 647 /** 648 * Command type used for all MALL commands. 649 */ 650 DMUB_CMD__MALL = 65, 651 /** 652 * Command type used for all ABM commands. 653 */ 654 DMUB_CMD__ABM = 66, 655 /** 656 * Command type used to update dirty rects in FW. 657 */ 658 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 659 /** 660 * Command type used to update cursor info in FW. 661 */ 662 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 663 /** 664 * Command type used for HW locking in FW. 665 */ 666 DMUB_CMD__HW_LOCK = 69, 667 /** 668 * Command type used to access DP AUX. 669 */ 670 DMUB_CMD__DP_AUX_ACCESS = 70, 671 /** 672 * Command type used for OUTBOX1 notification enable 673 */ 674 DMUB_CMD__OUTBOX1_ENABLE = 71, 675 676 /** 677 * Command type used for all idle optimization commands. 678 */ 679 DMUB_CMD__IDLE_OPT = 72, 680 /** 681 * Command type used for all clock manager commands. 682 */ 683 DMUB_CMD__CLK_MGR = 73, 684 /** 685 * Command type used for all panel control commands. 686 */ 687 DMUB_CMD__PANEL_CNTL = 74, 688 /** 689 * Command type used for <TODO:description> 690 */ 691 DMUB_CMD__CAB_FOR_SS = 75, 692 /** 693 * Command type used for interfacing with DPIA. 694 */ 695 DMUB_CMD__DPIA = 77, 696 /** 697 * Command type used for EDID CEA parsing 698 */ 699 DMUB_CMD__EDID_CEA = 79, 700 /** 701 * Command type used for getting usbc cable ID 702 */ 703 DMUB_CMD_GET_USBC_CABLE_ID = 81, 704 /** 705 * Command type used to query HPD state. 706 */ 707 DMUB_CMD__QUERY_HPD_STATE = 82, 708 /** 709 * Command type used for all VBIOS interface commands. 710 */ 711 DMUB_CMD__VBIOS = 128, 712 }; 713 714 /** 715 * enum dmub_out_cmd_type - DMUB outbox commands. 716 */ 717 enum dmub_out_cmd_type { 718 /** 719 * Invalid outbox command, ignored. 720 */ 721 DMUB_OUT_CMD__NULL = 0, 722 /** 723 * Command type used for DP AUX Reply data notification 724 */ 725 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 726 /** 727 * Command type used for DP HPD event notification 728 */ 729 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 730 /** 731 * Command type used for SET_CONFIG Reply notification 732 */ 733 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 734 }; 735 736 /* DMUB_CMD__DPIA command sub-types. */ 737 enum dmub_cmd_dpia_type { 738 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 739 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 740 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 741 }; 742 743 #pragma pack(push, 1) 744 745 /** 746 * struct dmub_cmd_header - Common command header fields. 747 */ 748 struct dmub_cmd_header { 749 unsigned int type : 8; /**< command type */ 750 unsigned int sub_type : 8; /**< command sub type */ 751 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 752 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 753 unsigned int reserved0 : 6; /**< reserved bits */ 754 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 755 unsigned int reserved1 : 2; /**< reserved bits */ 756 }; 757 758 /* 759 * struct dmub_cmd_read_modify_write_sequence - Read modify write 760 * 761 * 60 payload bytes can hold up to 5 sets of read modify writes, 762 * each take 3 dwords. 763 * 764 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 765 * 766 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 767 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 768 */ 769 struct dmub_cmd_read_modify_write_sequence { 770 uint32_t addr; /**< register address */ 771 uint32_t modify_mask; /**< modify mask */ 772 uint32_t modify_value; /**< modify value */ 773 }; 774 775 /** 776 * Maximum number of ops in read modify write sequence. 777 */ 778 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 779 780 /** 781 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 782 */ 783 struct dmub_rb_cmd_read_modify_write { 784 struct dmub_cmd_header header; /**< command header */ 785 /** 786 * Read modify write sequence. 787 */ 788 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 789 }; 790 791 /* 792 * Update a register with specified masks and values sequeunce 793 * 794 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 795 * 796 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 797 * 798 * 799 * USE CASE: 800 * 1. auto-increment register where additional read would update pointer and produce wrong result 801 * 2. toggle a bit without read in the middle 802 */ 803 804 struct dmub_cmd_reg_field_update_sequence { 805 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 806 uint32_t modify_value; /**< value to update with */ 807 }; 808 809 /** 810 * Maximum number of ops in field update sequence. 811 */ 812 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 813 814 /** 815 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 816 */ 817 struct dmub_rb_cmd_reg_field_update_sequence { 818 struct dmub_cmd_header header; /**< command header */ 819 uint32_t addr; /**< register address */ 820 /** 821 * Field update sequence. 822 */ 823 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 824 }; 825 826 827 /** 828 * Maximum number of burst write values. 829 */ 830 #define DMUB_BURST_WRITE_VALUES__MAX 14 831 832 /* 833 * struct dmub_rb_cmd_burst_write - Burst write 834 * 835 * support use case such as writing out LUTs. 836 * 837 * 60 payload bytes can hold up to 14 values to write to given address 838 * 839 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 840 */ 841 struct dmub_rb_cmd_burst_write { 842 struct dmub_cmd_header header; /**< command header */ 843 uint32_t addr; /**< register start address */ 844 /** 845 * Burst write register values. 846 */ 847 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 848 }; 849 850 /** 851 * struct dmub_rb_cmd_common - Common command header 852 */ 853 struct dmub_rb_cmd_common { 854 struct dmub_cmd_header header; /**< command header */ 855 /** 856 * Padding to RB_CMD_SIZE 857 */ 858 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 859 }; 860 861 /** 862 * struct dmub_cmd_reg_wait_data - Register wait data 863 */ 864 struct dmub_cmd_reg_wait_data { 865 uint32_t addr; /**< Register address */ 866 uint32_t mask; /**< Mask for register bits */ 867 uint32_t condition_field_value; /**< Value to wait for */ 868 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 869 }; 870 871 /** 872 * struct dmub_rb_cmd_reg_wait - Register wait command 873 */ 874 struct dmub_rb_cmd_reg_wait { 875 struct dmub_cmd_header header; /**< Command header */ 876 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 877 }; 878 879 /** 880 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 881 * 882 * Reprograms surface parameters to avoid underflow. 883 */ 884 struct dmub_cmd_PLAT_54186_wa { 885 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 886 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 887 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 888 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 889 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 890 struct { 891 uint8_t hubp_inst : 4; /**< HUBP instance */ 892 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 893 uint8_t immediate :1; /**< Immediate flip */ 894 uint8_t vmid : 4; /**< VMID */ 895 uint8_t grph_stereo : 1; /**< 1 if stereo */ 896 uint32_t reserved : 21; /**< Reserved */ 897 } flip_params; /**< Pageflip parameters */ 898 uint32_t reserved[9]; /**< Reserved bits */ 899 }; 900 901 /** 902 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 903 */ 904 struct dmub_rb_cmd_PLAT_54186_wa { 905 struct dmub_cmd_header header; /**< Command header */ 906 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 907 }; 908 909 /** 910 * struct dmub_rb_cmd_mall - MALL command data. 911 */ 912 struct dmub_rb_cmd_mall { 913 struct dmub_cmd_header header; /**< Common command header */ 914 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 915 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 916 uint32_t tmr_delay; /**< Timer delay */ 917 uint32_t tmr_scale; /**< Timer scale */ 918 uint16_t cursor_width; /**< Cursor width in pixels */ 919 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 920 uint16_t cursor_height; /**< Cursor height in pixels */ 921 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 922 uint8_t debug_bits; /**< Debug bits */ 923 924 uint8_t reserved1; /**< Reserved bits */ 925 uint8_t reserved2; /**< Reserved bits */ 926 }; 927 928 /** 929 * enum dmub_cmd_cab_type - TODO: 930 */ 931 enum dmub_cmd_cab_type { 932 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 933 DMUB_CMD__CAB_NO_DCN_REQ = 1, 934 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 935 }; 936 937 /** 938 * struct dmub_rb_cmd_cab_for_ss - TODO: 939 */ 940 struct dmub_rb_cmd_cab_for_ss { 941 struct dmub_cmd_header header; 942 uint8_t cab_alloc_ways; /* total number of ways */ 943 uint8_t debug_bits; /* debug bits */ 944 }; 945 /** 946 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 947 */ 948 enum dmub_cmd_idle_opt_type { 949 /** 950 * DCN hardware restore. 951 */ 952 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 953 954 /** 955 * DCN hardware save. 956 */ 957 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 958 }; 959 960 /** 961 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 962 */ 963 struct dmub_rb_cmd_idle_opt_dcn_restore { 964 struct dmub_cmd_header header; /**< header */ 965 }; 966 967 /** 968 * struct dmub_clocks - Clock update notification. 969 */ 970 struct dmub_clocks { 971 uint32_t dispclk_khz; /**< dispclk kHz */ 972 uint32_t dppclk_khz; /**< dppclk kHz */ 973 uint32_t dcfclk_khz; /**< dcfclk kHz */ 974 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 975 }; 976 977 /** 978 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 979 */ 980 enum dmub_cmd_clk_mgr_type { 981 /** 982 * Notify DMCUB of clock update. 983 */ 984 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 985 }; 986 987 /** 988 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 989 */ 990 struct dmub_rb_cmd_clk_mgr_notify_clocks { 991 struct dmub_cmd_header header; /**< header */ 992 struct dmub_clocks clocks; /**< clock data */ 993 }; 994 995 /** 996 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 997 */ 998 struct dmub_cmd_digx_encoder_control_data { 999 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1000 }; 1001 1002 /** 1003 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1004 */ 1005 struct dmub_rb_cmd_digx_encoder_control { 1006 struct dmub_cmd_header header; /**< header */ 1007 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1008 }; 1009 1010 /** 1011 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1012 */ 1013 struct dmub_cmd_set_pixel_clock_data { 1014 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1015 }; 1016 1017 /** 1018 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1019 */ 1020 struct dmub_rb_cmd_set_pixel_clock { 1021 struct dmub_cmd_header header; /**< header */ 1022 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1023 }; 1024 1025 /** 1026 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1027 */ 1028 struct dmub_cmd_enable_disp_power_gating_data { 1029 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1030 }; 1031 1032 /** 1033 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1034 */ 1035 struct dmub_rb_cmd_enable_disp_power_gating { 1036 struct dmub_cmd_header header; /**< header */ 1037 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1038 }; 1039 1040 /** 1041 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1042 */ 1043 struct dmub_dig_transmitter_control_data_v1_7 { 1044 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1045 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1046 union { 1047 uint8_t digmode; /**< enum atom_encode_mode_def */ 1048 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1049 } mode_laneset; 1050 uint8_t lanenum; /**< Number of lanes */ 1051 union { 1052 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1053 } symclk_units; 1054 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1055 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1056 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1057 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1058 uint8_t reserved1; /**< For future use */ 1059 uint8_t reserved2[3]; /**< For future use */ 1060 uint32_t reserved3[11]; /**< For future use */ 1061 }; 1062 1063 /** 1064 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1065 */ 1066 union dmub_cmd_dig1_transmitter_control_data { 1067 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1068 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1069 }; 1070 1071 /** 1072 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1073 */ 1074 struct dmub_rb_cmd_dig1_transmitter_control { 1075 struct dmub_cmd_header header; /**< header */ 1076 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1077 }; 1078 1079 /** 1080 * DPIA tunnel command parameters. 1081 */ 1082 struct dmub_cmd_dig_dpia_control_data { 1083 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1084 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1085 union { 1086 uint8_t digmode; /** enum atom_encode_mode_def */ 1087 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1088 } mode_laneset; 1089 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1090 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1091 uint8_t hpdsel; /** =0: HPD is not assigned */ 1092 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1093 uint8_t dpia_id; /** Index of DPIA */ 1094 uint8_t fec_rdy : 1; 1095 uint8_t reserved : 7; 1096 uint32_t reserved1; 1097 }; 1098 1099 /** 1100 * DMUB command for DPIA tunnel control. 1101 */ 1102 struct dmub_rb_cmd_dig1_dpia_control { 1103 struct dmub_cmd_header header; 1104 struct dmub_cmd_dig_dpia_control_data dpia_control; 1105 }; 1106 1107 /** 1108 * SET_CONFIG Command Payload 1109 */ 1110 struct set_config_cmd_payload { 1111 uint8_t msg_type; /* set config message type */ 1112 uint8_t msg_data; /* set config message data */ 1113 }; 1114 1115 /** 1116 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1117 */ 1118 struct dmub_cmd_set_config_control_data { 1119 struct set_config_cmd_payload cmd_pkt; 1120 uint8_t instance; /* DPIA instance */ 1121 uint8_t immed_status; /* Immediate status returned in case of error */ 1122 }; 1123 1124 /** 1125 * DMUB command structure for SET_CONFIG command. 1126 */ 1127 struct dmub_rb_cmd_set_config_access { 1128 struct dmub_cmd_header header; /* header */ 1129 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1130 }; 1131 1132 /** 1133 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1134 */ 1135 struct dmub_cmd_mst_alloc_slots_control_data { 1136 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1137 uint8_t instance; /* DPIA instance */ 1138 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1139 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1140 }; 1141 1142 /** 1143 * DMUB command structure for SET_ command. 1144 */ 1145 struct dmub_rb_cmd_set_mst_alloc_slots { 1146 struct dmub_cmd_header header; /* header */ 1147 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1148 }; 1149 1150 /** 1151 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1152 */ 1153 struct dmub_rb_cmd_dpphy_init { 1154 struct dmub_cmd_header header; /**< header */ 1155 uint8_t reserved[60]; /**< reserved bits */ 1156 }; 1157 1158 /** 1159 * enum dp_aux_request_action - DP AUX request command listing. 1160 * 1161 * 4 AUX request command bits are shifted to high nibble. 1162 */ 1163 enum dp_aux_request_action { 1164 /** I2C-over-AUX write request */ 1165 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1166 /** I2C-over-AUX read request */ 1167 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1168 /** I2C-over-AUX write status request */ 1169 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1170 /** I2C-over-AUX write request with MOT=1 */ 1171 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1172 /** I2C-over-AUX read request with MOT=1 */ 1173 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1174 /** I2C-over-AUX write status request with MOT=1 */ 1175 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1176 /** Native AUX write request */ 1177 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1178 /** Native AUX read request */ 1179 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1180 }; 1181 1182 /** 1183 * enum aux_return_code_type - DP AUX process return code listing. 1184 */ 1185 enum aux_return_code_type { 1186 /** AUX process succeeded */ 1187 AUX_RET_SUCCESS = 0, 1188 /** AUX process failed with unknown reason */ 1189 AUX_RET_ERROR_UNKNOWN, 1190 /** AUX process completed with invalid reply */ 1191 AUX_RET_ERROR_INVALID_REPLY, 1192 /** AUX process timed out */ 1193 AUX_RET_ERROR_TIMEOUT, 1194 /** HPD was low during AUX process */ 1195 AUX_RET_ERROR_HPD_DISCON, 1196 /** Failed to acquire AUX engine */ 1197 AUX_RET_ERROR_ENGINE_ACQUIRE, 1198 /** AUX request not supported */ 1199 AUX_RET_ERROR_INVALID_OPERATION, 1200 /** AUX process not available */ 1201 AUX_RET_ERROR_PROTOCOL_ERROR, 1202 }; 1203 1204 /** 1205 * enum aux_channel_type - DP AUX channel type listing. 1206 */ 1207 enum aux_channel_type { 1208 /** AUX thru Legacy DP AUX */ 1209 AUX_CHANNEL_LEGACY_DDC, 1210 /** AUX thru DPIA DP tunneling */ 1211 AUX_CHANNEL_DPIA 1212 }; 1213 1214 /** 1215 * struct aux_transaction_parameters - DP AUX request transaction data 1216 */ 1217 struct aux_transaction_parameters { 1218 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1219 uint8_t action; /**< enum dp_aux_request_action */ 1220 uint8_t length; /**< DP AUX request data length */ 1221 uint8_t reserved; /**< For future use */ 1222 uint32_t address; /**< DP AUX address */ 1223 uint8_t data[16]; /**< DP AUX write data */ 1224 }; 1225 1226 /** 1227 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1228 */ 1229 struct dmub_cmd_dp_aux_control_data { 1230 uint8_t instance; /**< AUX instance or DPIA instance */ 1231 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1232 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1233 uint8_t reserved0; /**< For future use */ 1234 uint16_t timeout; /**< timeout time in us */ 1235 uint16_t reserved1; /**< For future use */ 1236 enum aux_channel_type type; /**< enum aux_channel_type */ 1237 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1238 }; 1239 1240 /** 1241 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1242 */ 1243 struct dmub_rb_cmd_dp_aux_access { 1244 /** 1245 * Command header. 1246 */ 1247 struct dmub_cmd_header header; 1248 /** 1249 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1250 */ 1251 struct dmub_cmd_dp_aux_control_data aux_control; 1252 }; 1253 1254 /** 1255 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1256 */ 1257 struct dmub_rb_cmd_outbox1_enable { 1258 /** 1259 * Command header. 1260 */ 1261 struct dmub_cmd_header header; 1262 /** 1263 * enable: 0x0 -> disable outbox1 notification (default value) 1264 * 0x1 -> enable outbox1 notification 1265 */ 1266 uint32_t enable; 1267 }; 1268 1269 /* DP AUX Reply command - OutBox Cmd */ 1270 /** 1271 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1272 */ 1273 struct aux_reply_data { 1274 /** 1275 * Aux cmd 1276 */ 1277 uint8_t command; 1278 /** 1279 * Aux reply data length (max: 16 bytes) 1280 */ 1281 uint8_t length; 1282 /** 1283 * Alignment only 1284 */ 1285 uint8_t pad[2]; 1286 /** 1287 * Aux reply data 1288 */ 1289 uint8_t data[16]; 1290 }; 1291 1292 /** 1293 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1294 */ 1295 struct aux_reply_control_data { 1296 /** 1297 * Reserved for future use 1298 */ 1299 uint32_t handle; 1300 /** 1301 * Aux Instance 1302 */ 1303 uint8_t instance; 1304 /** 1305 * Aux transaction result: definition in enum aux_return_code_type 1306 */ 1307 uint8_t result; 1308 /** 1309 * Alignment only 1310 */ 1311 uint16_t pad; 1312 }; 1313 1314 /** 1315 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1316 */ 1317 struct dmub_rb_cmd_dp_aux_reply { 1318 /** 1319 * Command header. 1320 */ 1321 struct dmub_cmd_header header; 1322 /** 1323 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1324 */ 1325 struct aux_reply_control_data control; 1326 /** 1327 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1328 */ 1329 struct aux_reply_data reply_data; 1330 }; 1331 1332 /* DP HPD Notify command - OutBox Cmd */ 1333 /** 1334 * DP HPD Type 1335 */ 1336 enum dp_hpd_type { 1337 /** 1338 * Normal DP HPD 1339 */ 1340 DP_HPD = 0, 1341 /** 1342 * DP HPD short pulse 1343 */ 1344 DP_IRQ 1345 }; 1346 1347 /** 1348 * DP HPD Status 1349 */ 1350 enum dp_hpd_status { 1351 /** 1352 * DP_HPD status low 1353 */ 1354 DP_HPD_UNPLUG = 0, 1355 /** 1356 * DP_HPD status high 1357 */ 1358 DP_HPD_PLUG 1359 }; 1360 1361 /** 1362 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1363 */ 1364 struct dp_hpd_data { 1365 /** 1366 * DP HPD instance 1367 */ 1368 uint8_t instance; 1369 /** 1370 * HPD type 1371 */ 1372 uint8_t hpd_type; 1373 /** 1374 * HPD status: only for type: DP_HPD to indicate status 1375 */ 1376 uint8_t hpd_status; 1377 /** 1378 * Alignment only 1379 */ 1380 uint8_t pad; 1381 }; 1382 1383 /** 1384 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1385 */ 1386 struct dmub_rb_cmd_dp_hpd_notify { 1387 /** 1388 * Command header. 1389 */ 1390 struct dmub_cmd_header header; 1391 /** 1392 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1393 */ 1394 struct dp_hpd_data hpd_data; 1395 }; 1396 1397 /** 1398 * Definition of a SET_CONFIG reply from DPOA. 1399 */ 1400 enum set_config_status { 1401 SET_CONFIG_PENDING = 0, 1402 SET_CONFIG_ACK_RECEIVED, 1403 SET_CONFIG_RX_TIMEOUT, 1404 SET_CONFIG_UNKNOWN_ERROR, 1405 }; 1406 1407 /** 1408 * Definition of a set_config reply 1409 */ 1410 struct set_config_reply_control_data { 1411 uint8_t instance; /* DPIA Instance */ 1412 uint8_t status; /* Set Config reply */ 1413 uint16_t pad; /* Alignment */ 1414 }; 1415 1416 /** 1417 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1418 */ 1419 struct dmub_rb_cmd_dp_set_config_reply { 1420 struct dmub_cmd_header header; 1421 struct set_config_reply_control_data set_config_reply_control; 1422 }; 1423 1424 /** 1425 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1426 */ 1427 struct dmub_cmd_hpd_state_query_data { 1428 uint8_t instance; /**< HPD instance or DPIA instance */ 1429 uint8_t result; /**< For returning HPD state */ 1430 uint16_t pad; /** < Alignment */ 1431 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1432 enum aux_return_code_type status; /**< for returning the status of command */ 1433 }; 1434 1435 /** 1436 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1437 */ 1438 struct dmub_rb_cmd_query_hpd_state { 1439 /** 1440 * Command header. 1441 */ 1442 struct dmub_cmd_header header; 1443 /** 1444 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1445 */ 1446 struct dmub_cmd_hpd_state_query_data data; 1447 }; 1448 1449 /* 1450 * Command IDs should be treated as stable ABI. 1451 * Do not reuse or modify IDs. 1452 */ 1453 1454 /** 1455 * PSR command sub-types. 1456 */ 1457 enum dmub_cmd_psr_type { 1458 /** 1459 * Set PSR version support. 1460 */ 1461 DMUB_CMD__PSR_SET_VERSION = 0, 1462 /** 1463 * Copy driver-calculated parameters to PSR state. 1464 */ 1465 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1466 /** 1467 * Enable PSR. 1468 */ 1469 DMUB_CMD__PSR_ENABLE = 2, 1470 1471 /** 1472 * Disable PSR. 1473 */ 1474 DMUB_CMD__PSR_DISABLE = 3, 1475 1476 /** 1477 * Set PSR level. 1478 * PSR level is a 16-bit value dicated by driver that 1479 * will enable/disable different functionality. 1480 */ 1481 DMUB_CMD__PSR_SET_LEVEL = 4, 1482 1483 /** 1484 * Forces PSR enabled until an explicit PSR disable call. 1485 */ 1486 DMUB_CMD__PSR_FORCE_STATIC = 5, 1487 /** 1488 * Set vtotal in psr active for FreeSync PSR. 1489 */ 1490 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1491 /** 1492 * Set PSR power option 1493 */ 1494 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1495 }; 1496 1497 /** 1498 * PSR versions. 1499 */ 1500 enum psr_version { 1501 /** 1502 * PSR version 1. 1503 */ 1504 PSR_VERSION_1 = 0, 1505 /** 1506 * Freesync PSR SU. 1507 */ 1508 PSR_VERSION_SU_1 = 1, 1509 /** 1510 * PSR not supported. 1511 */ 1512 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1513 }; 1514 1515 /** 1516 * enum dmub_cmd_mall_type - MALL commands 1517 */ 1518 enum dmub_cmd_mall_type { 1519 /** 1520 * Allows display refresh from MALL. 1521 */ 1522 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1523 /** 1524 * Disallows display refresh from MALL. 1525 */ 1526 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1527 /** 1528 * Cursor copy for MALL. 1529 */ 1530 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1531 /** 1532 * Controls DF requests. 1533 */ 1534 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1535 }; 1536 1537 /** 1538 * PHY Link rate for DP. 1539 */ 1540 enum phy_link_rate { 1541 /** 1542 * not supported. 1543 */ 1544 PHY_RATE_UNKNOWN = 0, 1545 /** 1546 * Rate_1 (RBR) - 1.62 Gbps/Lane 1547 */ 1548 PHY_RATE_162 = 1, 1549 /** 1550 * Rate_2 - 2.16 Gbps/Lane 1551 */ 1552 PHY_RATE_216 = 2, 1553 /** 1554 * Rate_3 - 2.43 Gbps/Lane 1555 */ 1556 PHY_RATE_243 = 3, 1557 /** 1558 * Rate_4 (HBR) - 2.70 Gbps/Lane 1559 */ 1560 PHY_RATE_270 = 4, 1561 /** 1562 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1563 */ 1564 PHY_RATE_324 = 5, 1565 /** 1566 * Rate_6 - 4.32 Gbps/Lane 1567 */ 1568 PHY_RATE_432 = 6, 1569 /** 1570 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1571 */ 1572 PHY_RATE_540 = 7, 1573 /** 1574 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1575 */ 1576 PHY_RATE_810 = 8, 1577 /** 1578 * UHBR10 - 10.0 Gbps/Lane 1579 */ 1580 PHY_RATE_1000 = 9, 1581 /** 1582 * UHBR13.5 - 13.5 Gbps/Lane 1583 */ 1584 PHY_RATE_1350 = 10, 1585 /** 1586 * UHBR10 - 20.0 Gbps/Lane 1587 */ 1588 PHY_RATE_2000 = 11, 1589 }; 1590 1591 /** 1592 * enum dmub_phy_fsm_state - PHY FSM states. 1593 * PHY FSM state to transit to during PSR enable/disable. 1594 */ 1595 enum dmub_phy_fsm_state { 1596 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1597 DMUB_PHY_FSM_RESET, 1598 DMUB_PHY_FSM_RESET_RELEASED, 1599 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1600 DMUB_PHY_FSM_INITIALIZED, 1601 DMUB_PHY_FSM_CALIBRATED, 1602 DMUB_PHY_FSM_CALIBRATED_LP, 1603 DMUB_PHY_FSM_CALIBRATED_PG, 1604 DMUB_PHY_FSM_POWER_DOWN, 1605 DMUB_PHY_FSM_PLL_EN, 1606 DMUB_PHY_FSM_TX_EN, 1607 DMUB_PHY_FSM_FAST_LP, 1608 }; 1609 1610 /** 1611 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1612 */ 1613 struct dmub_cmd_psr_copy_settings_data { 1614 /** 1615 * Flags that can be set by driver to change some PSR behaviour. 1616 */ 1617 union dmub_psr_debug_flags debug; 1618 /** 1619 * 16-bit value dicated by driver that will enable/disable different functionality. 1620 */ 1621 uint16_t psr_level; 1622 /** 1623 * DPP HW instance. 1624 */ 1625 uint8_t dpp_inst; 1626 /** 1627 * MPCC HW instance. 1628 * Not used in dmub fw, 1629 * dmub fw will get active opp by reading odm registers. 1630 */ 1631 uint8_t mpcc_inst; 1632 /** 1633 * OPP HW instance. 1634 * Not used in dmub fw, 1635 * dmub fw will get active opp by reading odm registers. 1636 */ 1637 uint8_t opp_inst; 1638 /** 1639 * OTG HW instance. 1640 */ 1641 uint8_t otg_inst; 1642 /** 1643 * DIG FE HW instance. 1644 */ 1645 uint8_t digfe_inst; 1646 /** 1647 * DIG BE HW instance. 1648 */ 1649 uint8_t digbe_inst; 1650 /** 1651 * DP PHY HW instance. 1652 */ 1653 uint8_t dpphy_inst; 1654 /** 1655 * AUX HW instance. 1656 */ 1657 uint8_t aux_inst; 1658 /** 1659 * Determines if SMU optimzations are enabled/disabled. 1660 */ 1661 uint8_t smu_optimizations_en; 1662 /** 1663 * Unused. 1664 * TODO: Remove. 1665 */ 1666 uint8_t frame_delay; 1667 /** 1668 * If RFB setup time is greater than the total VBLANK time, 1669 * it is not possible for the sink to capture the video frame 1670 * in the same frame the SDP is sent. In this case, 1671 * the frame capture indication bit should be set and an extra 1672 * static frame should be transmitted to the sink. 1673 */ 1674 uint8_t frame_cap_ind; 1675 /** 1676 * Granularity of Y offset supported by sink. 1677 */ 1678 uint8_t su_y_granularity; 1679 /** 1680 * Indicates whether sink should start capturing 1681 * immediately following active scan line, 1682 * or starting with the 2nd active scan line. 1683 */ 1684 uint8_t line_capture_indication; 1685 /** 1686 * Multi-display optimizations are implemented on certain ASICs. 1687 */ 1688 uint8_t multi_disp_optimizations_en; 1689 /** 1690 * The last possible line SDP may be transmitted without violating 1691 * the RFB setup time or entering the active video frame. 1692 */ 1693 uint16_t init_sdp_deadline; 1694 /** 1695 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1696 */ 1697 uint8_t rate_control_caps ; 1698 /* 1699 * Force PSRSU always doing full frame update 1700 */ 1701 uint8_t force_ffu_mode; 1702 /** 1703 * Length of each horizontal line in us. 1704 */ 1705 uint32_t line_time_in_us; 1706 /** 1707 * FEC enable status in driver 1708 */ 1709 uint8_t fec_enable_status; 1710 /** 1711 * FEC re-enable delay when PSR exit. 1712 * unit is 100us, range form 0~255(0xFF). 1713 */ 1714 uint8_t fec_enable_delay_in100us; 1715 /** 1716 * PSR control version. 1717 */ 1718 uint8_t cmd_version; 1719 /** 1720 * Panel Instance. 1721 * Panel isntance to identify which psr_state to use 1722 * Currently the support is only for 0 or 1 1723 */ 1724 uint8_t panel_inst; 1725 /* 1726 * DSC enable status in driver 1727 */ 1728 uint8_t dsc_enable_status; 1729 /* 1730 * Use FSM state for PSR power up/down 1731 */ 1732 uint8_t use_phy_fsm; 1733 /** 1734 * Explicit padding to 2 byte boundary. 1735 */ 1736 uint8_t pad3[2]; 1737 }; 1738 1739 /** 1740 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1741 */ 1742 struct dmub_rb_cmd_psr_copy_settings { 1743 /** 1744 * Command header. 1745 */ 1746 struct dmub_cmd_header header; 1747 /** 1748 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1749 */ 1750 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1751 }; 1752 1753 /** 1754 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1755 */ 1756 struct dmub_cmd_psr_set_level_data { 1757 /** 1758 * 16-bit value dicated by driver that will enable/disable different functionality. 1759 */ 1760 uint16_t psr_level; 1761 /** 1762 * PSR control version. 1763 */ 1764 uint8_t cmd_version; 1765 /** 1766 * Panel Instance. 1767 * Panel isntance to identify which psr_state to use 1768 * Currently the support is only for 0 or 1 1769 */ 1770 uint8_t panel_inst; 1771 }; 1772 1773 /** 1774 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1775 */ 1776 struct dmub_rb_cmd_psr_set_level { 1777 /** 1778 * Command header. 1779 */ 1780 struct dmub_cmd_header header; 1781 /** 1782 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1783 */ 1784 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1785 }; 1786 1787 struct dmub_rb_cmd_psr_enable_data { 1788 /** 1789 * PSR control version. 1790 */ 1791 uint8_t cmd_version; 1792 /** 1793 * Panel Instance. 1794 * Panel isntance to identify which psr_state to use 1795 * Currently the support is only for 0 or 1 1796 */ 1797 uint8_t panel_inst; 1798 /** 1799 * Phy state to enter. 1800 * Values to use are defined in dmub_phy_fsm_state 1801 */ 1802 uint8_t phy_fsm_state; 1803 /** 1804 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1805 * Set this using enum phy_link_rate. 1806 * This does not support HDMI/DP2 for now. 1807 */ 1808 uint8_t phy_rate; 1809 }; 1810 1811 /** 1812 * Definition of a DMUB_CMD__PSR_ENABLE command. 1813 * PSR enable/disable is controlled using the sub_type. 1814 */ 1815 struct dmub_rb_cmd_psr_enable { 1816 /** 1817 * Command header. 1818 */ 1819 struct dmub_cmd_header header; 1820 1821 struct dmub_rb_cmd_psr_enable_data data; 1822 }; 1823 1824 /** 1825 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1826 */ 1827 struct dmub_cmd_psr_set_version_data { 1828 /** 1829 * PSR version that FW should implement. 1830 */ 1831 enum psr_version version; 1832 /** 1833 * PSR control version. 1834 */ 1835 uint8_t cmd_version; 1836 /** 1837 * Panel Instance. 1838 * Panel isntance to identify which psr_state to use 1839 * Currently the support is only for 0 or 1 1840 */ 1841 uint8_t panel_inst; 1842 /** 1843 * Explicit padding to 4 byte boundary. 1844 */ 1845 uint8_t pad[2]; 1846 }; 1847 1848 /** 1849 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1850 */ 1851 struct dmub_rb_cmd_psr_set_version { 1852 /** 1853 * Command header. 1854 */ 1855 struct dmub_cmd_header header; 1856 /** 1857 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1858 */ 1859 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1860 }; 1861 1862 struct dmub_cmd_psr_force_static_data { 1863 /** 1864 * PSR control version. 1865 */ 1866 uint8_t cmd_version; 1867 /** 1868 * Panel Instance. 1869 * Panel isntance to identify which psr_state to use 1870 * Currently the support is only for 0 or 1 1871 */ 1872 uint8_t panel_inst; 1873 /** 1874 * Explicit padding to 4 byte boundary. 1875 */ 1876 uint8_t pad[2]; 1877 }; 1878 1879 /** 1880 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1881 */ 1882 struct dmub_rb_cmd_psr_force_static { 1883 /** 1884 * Command header. 1885 */ 1886 struct dmub_cmd_header header; 1887 /** 1888 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1889 */ 1890 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1891 }; 1892 1893 /** 1894 * PSR SU debug flags. 1895 */ 1896 union dmub_psr_su_debug_flags { 1897 /** 1898 * PSR SU debug flags. 1899 */ 1900 struct { 1901 /** 1902 * Update dirty rect in SW only. 1903 */ 1904 uint8_t update_dirty_rect_only : 1; 1905 /** 1906 * Reset the cursor/plane state before processing the call. 1907 */ 1908 uint8_t reset_state : 1; 1909 } bitfields; 1910 1911 /** 1912 * Union for debug flags. 1913 */ 1914 uint32_t u32All; 1915 }; 1916 1917 /** 1918 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 1919 * This triggers a selective update for PSR SU. 1920 */ 1921 struct dmub_cmd_update_dirty_rect_data { 1922 /** 1923 * Dirty rects from OS. 1924 */ 1925 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 1926 /** 1927 * PSR SU debug flags. 1928 */ 1929 union dmub_psr_su_debug_flags debug_flags; 1930 /** 1931 * OTG HW instance. 1932 */ 1933 uint8_t pipe_idx; 1934 /** 1935 * Number of dirty rects. 1936 */ 1937 uint8_t dirty_rect_count; 1938 /** 1939 * PSR control version. 1940 */ 1941 uint8_t cmd_version; 1942 /** 1943 * Panel Instance. 1944 * Panel isntance to identify which psr_state to use 1945 * Currently the support is only for 0 or 1 1946 */ 1947 uint8_t panel_inst; 1948 }; 1949 1950 /** 1951 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 1952 */ 1953 struct dmub_rb_cmd_update_dirty_rect { 1954 /** 1955 * Command header. 1956 */ 1957 struct dmub_cmd_header header; 1958 /** 1959 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 1960 */ 1961 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 1962 }; 1963 1964 /** 1965 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 1966 */ 1967 struct dmub_cmd_update_cursor_info_data { 1968 /** 1969 * Cursor dirty rects. 1970 */ 1971 struct dmub_rect cursor_rect; 1972 /** 1973 * PSR SU debug flags. 1974 */ 1975 union dmub_psr_su_debug_flags debug_flags; 1976 /** 1977 * Cursor enable/disable. 1978 */ 1979 uint8_t enable; 1980 /** 1981 * OTG HW instance. 1982 */ 1983 uint8_t pipe_idx; 1984 /** 1985 * PSR control version. 1986 */ 1987 uint8_t cmd_version; 1988 /** 1989 * Panel Instance. 1990 * Panel isntance to identify which psr_state to use 1991 * Currently the support is only for 0 or 1 1992 */ 1993 uint8_t panel_inst; 1994 }; 1995 /** 1996 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 1997 */ 1998 struct dmub_rb_cmd_update_cursor_info { 1999 /** 2000 * Command header. 2001 */ 2002 struct dmub_cmd_header header; 2003 /** 2004 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2005 */ 2006 struct dmub_cmd_update_cursor_info_data update_cursor_info_data; 2007 }; 2008 2009 /** 2010 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2011 */ 2012 struct dmub_cmd_psr_set_vtotal_data { 2013 /** 2014 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2015 */ 2016 uint16_t psr_vtotal_idle; 2017 /** 2018 * PSR control version. 2019 */ 2020 uint8_t cmd_version; 2021 /** 2022 * Panel Instance. 2023 * Panel isntance to identify which psr_state to use 2024 * Currently the support is only for 0 or 1 2025 */ 2026 uint8_t panel_inst; 2027 /* 2028 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2029 */ 2030 uint16_t psr_vtotal_su; 2031 /** 2032 * Explicit padding to 4 byte boundary. 2033 */ 2034 uint8_t pad2[2]; 2035 }; 2036 2037 /** 2038 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2039 */ 2040 struct dmub_rb_cmd_psr_set_vtotal { 2041 /** 2042 * Command header. 2043 */ 2044 struct dmub_cmd_header header; 2045 /** 2046 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2047 */ 2048 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2049 }; 2050 2051 /** 2052 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2053 */ 2054 struct dmub_cmd_psr_set_power_opt_data { 2055 /** 2056 * PSR control version. 2057 */ 2058 uint8_t cmd_version; 2059 /** 2060 * Panel Instance. 2061 * Panel isntance to identify which psr_state to use 2062 * Currently the support is only for 0 or 1 2063 */ 2064 uint8_t panel_inst; 2065 /** 2066 * Explicit padding to 4 byte boundary. 2067 */ 2068 uint8_t pad[2]; 2069 /** 2070 * PSR power option 2071 */ 2072 uint32_t power_opt; 2073 }; 2074 2075 /** 2076 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2077 */ 2078 struct dmub_rb_cmd_psr_set_power_opt { 2079 /** 2080 * Command header. 2081 */ 2082 struct dmub_cmd_header header; 2083 /** 2084 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2085 */ 2086 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2087 }; 2088 2089 /** 2090 * Set of HW components that can be locked. 2091 * 2092 * Note: If updating with more HW components, fields 2093 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2094 */ 2095 union dmub_hw_lock_flags { 2096 /** 2097 * Set of HW components that can be locked. 2098 */ 2099 struct { 2100 /** 2101 * Lock/unlock OTG master update lock. 2102 */ 2103 uint8_t lock_pipe : 1; 2104 /** 2105 * Lock/unlock cursor. 2106 */ 2107 uint8_t lock_cursor : 1; 2108 /** 2109 * Lock/unlock global update lock. 2110 */ 2111 uint8_t lock_dig : 1; 2112 /** 2113 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2114 */ 2115 uint8_t triple_buffer_lock : 1; 2116 } bits; 2117 2118 /** 2119 * Union for HW Lock flags. 2120 */ 2121 uint8_t u8All; 2122 }; 2123 2124 /** 2125 * Instances of HW to be locked. 2126 * 2127 * Note: If updating with more HW components, fields 2128 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2129 */ 2130 struct dmub_hw_lock_inst_flags { 2131 /** 2132 * OTG HW instance for OTG master update lock. 2133 */ 2134 uint8_t otg_inst; 2135 /** 2136 * OPP instance for cursor lock. 2137 */ 2138 uint8_t opp_inst; 2139 /** 2140 * OTG HW instance for global update lock. 2141 * TODO: Remove, and re-use otg_inst. 2142 */ 2143 uint8_t dig_inst; 2144 /** 2145 * Explicit pad to 4 byte boundary. 2146 */ 2147 uint8_t pad; 2148 }; 2149 2150 /** 2151 * Clients that can acquire the HW Lock Manager. 2152 * 2153 * Note: If updating with more clients, fields in 2154 * dmub_inbox0_cmd_lock_hw must be updated to match. 2155 */ 2156 enum hw_lock_client { 2157 /** 2158 * Driver is the client of HW Lock Manager. 2159 */ 2160 HW_LOCK_CLIENT_DRIVER = 0, 2161 /** 2162 * PSR SU is the client of HW Lock Manager. 2163 */ 2164 HW_LOCK_CLIENT_PSR_SU = 1, 2165 /** 2166 * Invalid client. 2167 */ 2168 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2169 }; 2170 2171 /** 2172 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2173 */ 2174 struct dmub_cmd_lock_hw_data { 2175 /** 2176 * Specifies the client accessing HW Lock Manager. 2177 */ 2178 enum hw_lock_client client; 2179 /** 2180 * HW instances to be locked. 2181 */ 2182 struct dmub_hw_lock_inst_flags inst_flags; 2183 /** 2184 * Which components to be locked. 2185 */ 2186 union dmub_hw_lock_flags hw_locks; 2187 /** 2188 * Specifies lock/unlock. 2189 */ 2190 uint8_t lock; 2191 /** 2192 * HW can be unlocked separately from releasing the HW Lock Mgr. 2193 * This flag is set if the client wishes to release the object. 2194 */ 2195 uint8_t should_release; 2196 /** 2197 * Explicit padding to 4 byte boundary. 2198 */ 2199 uint8_t pad; 2200 }; 2201 2202 /** 2203 * Definition of a DMUB_CMD__HW_LOCK command. 2204 * Command is used by driver and FW. 2205 */ 2206 struct dmub_rb_cmd_lock_hw { 2207 /** 2208 * Command header. 2209 */ 2210 struct dmub_cmd_header header; 2211 /** 2212 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2213 */ 2214 struct dmub_cmd_lock_hw_data lock_hw_data; 2215 }; 2216 2217 /** 2218 * ABM command sub-types. 2219 */ 2220 enum dmub_cmd_abm_type { 2221 /** 2222 * Initialize parameters for ABM algorithm. 2223 * Data is passed through an indirect buffer. 2224 */ 2225 DMUB_CMD__ABM_INIT_CONFIG = 0, 2226 /** 2227 * Set OTG and panel HW instance. 2228 */ 2229 DMUB_CMD__ABM_SET_PIPE = 1, 2230 /** 2231 * Set user requested backklight level. 2232 */ 2233 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2234 /** 2235 * Set ABM operating/aggression level. 2236 */ 2237 DMUB_CMD__ABM_SET_LEVEL = 3, 2238 /** 2239 * Set ambient light level. 2240 */ 2241 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2242 /** 2243 * Enable/disable fractional duty cycle for backlight PWM. 2244 */ 2245 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2246 2247 /** 2248 * unregister vertical interrupt after steady state is reached 2249 */ 2250 DMUB_CMD__ABM_PAUSE = 6, 2251 }; 2252 2253 /** 2254 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2255 * Requirements: 2256 * - Padded explicitly to 32-bit boundary. 2257 * - Must ensure this structure matches the one on driver-side, 2258 * otherwise it won't be aligned. 2259 */ 2260 struct abm_config_table { 2261 /** 2262 * Gamma curve thresholds, used for crgb conversion. 2263 */ 2264 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2265 /** 2266 * Gamma curve offsets, used for crgb conversion. 2267 */ 2268 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2269 /** 2270 * Gamma curve slopes, used for crgb conversion. 2271 */ 2272 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2273 /** 2274 * Custom backlight curve thresholds. 2275 */ 2276 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2277 /** 2278 * Custom backlight curve offsets. 2279 */ 2280 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2281 /** 2282 * Ambient light thresholds. 2283 */ 2284 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2285 /** 2286 * Minimum programmable backlight. 2287 */ 2288 uint16_t min_abm_backlight; // 122B 2289 /** 2290 * Minimum reduction values. 2291 */ 2292 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2293 /** 2294 * Maximum reduction values. 2295 */ 2296 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2297 /** 2298 * Bright positive gain. 2299 */ 2300 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2301 /** 2302 * Dark negative gain. 2303 */ 2304 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2305 /** 2306 * Hybrid factor. 2307 */ 2308 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2309 /** 2310 * Contrast factor. 2311 */ 2312 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2313 /** 2314 * Deviation gain. 2315 */ 2316 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2317 /** 2318 * Minimum knee. 2319 */ 2320 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2321 /** 2322 * Maximum knee. 2323 */ 2324 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2325 /** 2326 * Unused. 2327 */ 2328 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2329 /** 2330 * Explicit padding to 4 byte boundary. 2331 */ 2332 uint8_t pad3[3]; // 229B 2333 /** 2334 * Backlight ramp reduction. 2335 */ 2336 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2337 /** 2338 * Backlight ramp start. 2339 */ 2340 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2341 }; 2342 2343 /** 2344 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2345 */ 2346 struct dmub_cmd_abm_set_pipe_data { 2347 /** 2348 * OTG HW instance. 2349 */ 2350 uint8_t otg_inst; 2351 2352 /** 2353 * Panel Control HW instance. 2354 */ 2355 uint8_t panel_inst; 2356 2357 /** 2358 * Controls how ABM will interpret a set pipe or set level command. 2359 */ 2360 uint8_t set_pipe_option; 2361 2362 /** 2363 * Unused. 2364 * TODO: Remove. 2365 */ 2366 uint8_t ramping_boundary; 2367 }; 2368 2369 /** 2370 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2371 */ 2372 struct dmub_rb_cmd_abm_set_pipe { 2373 /** 2374 * Command header. 2375 */ 2376 struct dmub_cmd_header header; 2377 2378 /** 2379 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2380 */ 2381 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2382 }; 2383 2384 /** 2385 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2386 */ 2387 struct dmub_cmd_abm_set_backlight_data { 2388 /** 2389 * Number of frames to ramp to backlight user level. 2390 */ 2391 uint32_t frame_ramp; 2392 2393 /** 2394 * Requested backlight level from user. 2395 */ 2396 uint32_t backlight_user_level; 2397 2398 /** 2399 * ABM control version. 2400 */ 2401 uint8_t version; 2402 2403 /** 2404 * Panel Control HW instance mask. 2405 * Bit 0 is Panel Control HW instance 0. 2406 * Bit 1 is Panel Control HW instance 1. 2407 */ 2408 uint8_t panel_mask; 2409 2410 /** 2411 * Explicit padding to 4 byte boundary. 2412 */ 2413 uint8_t pad[2]; 2414 }; 2415 2416 /** 2417 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2418 */ 2419 struct dmub_rb_cmd_abm_set_backlight { 2420 /** 2421 * Command header. 2422 */ 2423 struct dmub_cmd_header header; 2424 2425 /** 2426 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2427 */ 2428 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2429 }; 2430 2431 /** 2432 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2433 */ 2434 struct dmub_cmd_abm_set_level_data { 2435 /** 2436 * Set current ABM operating/aggression level. 2437 */ 2438 uint32_t level; 2439 2440 /** 2441 * ABM control version. 2442 */ 2443 uint8_t version; 2444 2445 /** 2446 * Panel Control HW instance mask. 2447 * Bit 0 is Panel Control HW instance 0. 2448 * Bit 1 is Panel Control HW instance 1. 2449 */ 2450 uint8_t panel_mask; 2451 2452 /** 2453 * Explicit padding to 4 byte boundary. 2454 */ 2455 uint8_t pad[2]; 2456 }; 2457 2458 /** 2459 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2460 */ 2461 struct dmub_rb_cmd_abm_set_level { 2462 /** 2463 * Command header. 2464 */ 2465 struct dmub_cmd_header header; 2466 2467 /** 2468 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2469 */ 2470 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2471 }; 2472 2473 /** 2474 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2475 */ 2476 struct dmub_cmd_abm_set_ambient_level_data { 2477 /** 2478 * Ambient light sensor reading from OS. 2479 */ 2480 uint32_t ambient_lux; 2481 2482 /** 2483 * ABM control version. 2484 */ 2485 uint8_t version; 2486 2487 /** 2488 * Panel Control HW instance mask. 2489 * Bit 0 is Panel Control HW instance 0. 2490 * Bit 1 is Panel Control HW instance 1. 2491 */ 2492 uint8_t panel_mask; 2493 2494 /** 2495 * Explicit padding to 4 byte boundary. 2496 */ 2497 uint8_t pad[2]; 2498 }; 2499 2500 /** 2501 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2502 */ 2503 struct dmub_rb_cmd_abm_set_ambient_level { 2504 /** 2505 * Command header. 2506 */ 2507 struct dmub_cmd_header header; 2508 2509 /** 2510 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2511 */ 2512 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2513 }; 2514 2515 /** 2516 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2517 */ 2518 struct dmub_cmd_abm_set_pwm_frac_data { 2519 /** 2520 * Enable/disable fractional duty cycle for backlight PWM. 2521 * TODO: Convert to uint8_t. 2522 */ 2523 uint32_t fractional_pwm; 2524 2525 /** 2526 * ABM control version. 2527 */ 2528 uint8_t version; 2529 2530 /** 2531 * Panel Control HW instance mask. 2532 * Bit 0 is Panel Control HW instance 0. 2533 * Bit 1 is Panel Control HW instance 1. 2534 */ 2535 uint8_t panel_mask; 2536 2537 /** 2538 * Explicit padding to 4 byte boundary. 2539 */ 2540 uint8_t pad[2]; 2541 }; 2542 2543 /** 2544 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2545 */ 2546 struct dmub_rb_cmd_abm_set_pwm_frac { 2547 /** 2548 * Command header. 2549 */ 2550 struct dmub_cmd_header header; 2551 2552 /** 2553 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2554 */ 2555 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2556 }; 2557 2558 /** 2559 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2560 */ 2561 struct dmub_cmd_abm_init_config_data { 2562 /** 2563 * Location of indirect buffer used to pass init data to ABM. 2564 */ 2565 union dmub_addr src; 2566 2567 /** 2568 * Indirect buffer length. 2569 */ 2570 uint16_t bytes; 2571 2572 2573 /** 2574 * ABM control version. 2575 */ 2576 uint8_t version; 2577 2578 /** 2579 * Panel Control HW instance mask. 2580 * Bit 0 is Panel Control HW instance 0. 2581 * Bit 1 is Panel Control HW instance 1. 2582 */ 2583 uint8_t panel_mask; 2584 2585 /** 2586 * Explicit padding to 4 byte boundary. 2587 */ 2588 uint8_t pad[2]; 2589 }; 2590 2591 /** 2592 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2593 */ 2594 struct dmub_rb_cmd_abm_init_config { 2595 /** 2596 * Command header. 2597 */ 2598 struct dmub_cmd_header header; 2599 2600 /** 2601 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2602 */ 2603 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2604 }; 2605 2606 /** 2607 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2608 */ 2609 2610 struct dmub_cmd_abm_pause_data { 2611 2612 /** 2613 * Panel Control HW instance mask. 2614 * Bit 0 is Panel Control HW instance 0. 2615 * Bit 1 is Panel Control HW instance 1. 2616 */ 2617 uint8_t panel_mask; 2618 2619 /** 2620 * OTG hw instance 2621 */ 2622 uint8_t otg_inst; 2623 2624 /** 2625 * Enable or disable ABM pause 2626 */ 2627 uint8_t enable; 2628 2629 /** 2630 * Explicit padding to 4 byte boundary. 2631 */ 2632 uint8_t pad[1]; 2633 }; 2634 2635 /** 2636 * Definition of a DMUB_CMD__ABM_PAUSE command. 2637 */ 2638 struct dmub_rb_cmd_abm_pause { 2639 /** 2640 * Command header. 2641 */ 2642 struct dmub_cmd_header header; 2643 2644 /** 2645 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2646 */ 2647 struct dmub_cmd_abm_pause_data abm_pause_data; 2648 }; 2649 2650 /** 2651 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2652 */ 2653 struct dmub_cmd_query_feature_caps_data { 2654 /** 2655 * DMUB feature capabilities. 2656 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2657 */ 2658 struct dmub_feature_caps feature_caps; 2659 }; 2660 2661 /** 2662 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2663 */ 2664 struct dmub_rb_cmd_query_feature_caps { 2665 /** 2666 * Command header. 2667 */ 2668 struct dmub_cmd_header header; 2669 /** 2670 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2671 */ 2672 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2673 }; 2674 2675 struct dmub_optc_state { 2676 uint32_t v_total_max; 2677 uint32_t v_total_min; 2678 uint32_t v_total_mid; 2679 uint32_t v_total_mid_frame_num; 2680 uint32_t tg_inst; 2681 uint32_t enable_manual_trigger; 2682 uint32_t clear_force_vsync; 2683 }; 2684 2685 struct dmub_rb_cmd_drr_update { 2686 struct dmub_cmd_header header; 2687 struct dmub_optc_state dmub_optc_state_req; 2688 }; 2689 2690 /** 2691 * enum dmub_cmd_panel_cntl_type - Panel control command. 2692 */ 2693 enum dmub_cmd_panel_cntl_type { 2694 /** 2695 * Initializes embedded panel hardware blocks. 2696 */ 2697 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2698 /** 2699 * Queries backlight info for the embedded panel. 2700 */ 2701 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2702 }; 2703 2704 /** 2705 * struct dmub_cmd_panel_cntl_data - Panel control data. 2706 */ 2707 struct dmub_cmd_panel_cntl_data { 2708 uint32_t inst; /**< panel instance */ 2709 uint32_t current_backlight; /* in/out */ 2710 uint32_t bl_pwm_cntl; /* in/out */ 2711 uint32_t bl_pwm_period_cntl; /* in/out */ 2712 uint32_t bl_pwm_ref_div1; /* in/out */ 2713 uint8_t is_backlight_on : 1; /* in/out */ 2714 uint8_t is_powered_on : 1; /* in/out */ 2715 uint8_t padding[3]; 2716 uint32_t bl_pwm_ref_div2; /* in/out */ 2717 uint8_t reserved[4]; 2718 }; 2719 2720 /** 2721 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2722 */ 2723 struct dmub_rb_cmd_panel_cntl { 2724 struct dmub_cmd_header header; /**< header */ 2725 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2726 }; 2727 2728 /** 2729 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2730 */ 2731 struct dmub_cmd_lvtma_control_data { 2732 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2733 uint8_t reserved_0[3]; /**< For future use */ 2734 uint8_t panel_inst; /**< LVTMA control instance */ 2735 uint8_t reserved_1[3]; /**< For future use */ 2736 }; 2737 2738 /** 2739 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2740 */ 2741 struct dmub_rb_cmd_lvtma_control { 2742 /** 2743 * Command header. 2744 */ 2745 struct dmub_cmd_header header; 2746 /** 2747 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2748 */ 2749 struct dmub_cmd_lvtma_control_data data; 2750 }; 2751 2752 /** 2753 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2754 */ 2755 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 2756 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2757 uint8_t is_usb; /**< is phy is usb */ 2758 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 2759 uint8_t is_dp4; /**< is dp in 4 lane */ 2760 }; 2761 2762 /** 2763 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2764 */ 2765 struct dmub_rb_cmd_transmitter_query_dp_alt { 2766 struct dmub_cmd_header header; /**< header */ 2767 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 2768 }; 2769 2770 /** 2771 * Maximum number of bytes a chunk sent to DMUB for parsing 2772 */ 2773 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2774 2775 /** 2776 * Represent a chunk of CEA blocks sent to DMUB for parsing 2777 */ 2778 struct dmub_cmd_send_edid_cea { 2779 uint16_t offset; /**< offset into the CEA block */ 2780 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2781 uint16_t cea_total_length; /**< total length of the CEA block */ 2782 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2783 uint8_t pad[3]; /**< padding and for future expansion */ 2784 }; 2785 2786 /** 2787 * Result of VSDB parsing from CEA block 2788 */ 2789 struct dmub_cmd_edid_cea_amd_vsdb { 2790 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2791 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2792 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2793 uint16_t min_frame_rate; /**< Maximum frame rate */ 2794 uint16_t max_frame_rate; /**< Minimum frame rate */ 2795 }; 2796 2797 /** 2798 * Result of sending a CEA chunk 2799 */ 2800 struct dmub_cmd_edid_cea_ack { 2801 uint16_t offset; /**< offset of the chunk into the CEA block */ 2802 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2803 uint8_t pad; /**< padding and for future expansion */ 2804 }; 2805 2806 /** 2807 * Specify whether the result is an ACK/NACK or the parsing has finished 2808 */ 2809 enum dmub_cmd_edid_cea_reply_type { 2810 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2811 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2812 }; 2813 2814 /** 2815 * Definition of a DMUB_CMD__EDID_CEA command. 2816 */ 2817 struct dmub_rb_cmd_edid_cea { 2818 struct dmub_cmd_header header; /**< Command header */ 2819 union dmub_cmd_edid_cea_data { 2820 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2821 struct dmub_cmd_edid_cea_output { /**< output with results */ 2822 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2823 union { 2824 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2825 struct dmub_cmd_edid_cea_ack ack; 2826 }; 2827 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2828 } data; /**< Command data */ 2829 2830 }; 2831 2832 /** 2833 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 2834 */ 2835 struct dmub_cmd_cable_id_input { 2836 uint8_t phy_inst; /**< phy inst for cable id data */ 2837 }; 2838 2839 /** 2840 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 2841 */ 2842 struct dmub_cmd_cable_id_output { 2843 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 2844 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 2845 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 2846 uint8_t RESERVED :2; /**< reserved means not defined */ 2847 }; 2848 2849 /** 2850 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 2851 */ 2852 struct dmub_rb_cmd_get_usbc_cable_id { 2853 struct dmub_cmd_header header; /**< Command header */ 2854 /** 2855 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 2856 */ 2857 union dmub_cmd_cable_id_data { 2858 struct dmub_cmd_cable_id_input input; /**< Input */ 2859 struct dmub_cmd_cable_id_output output; /**< Output */ 2860 uint8_t output_raw; /**< Raw data output */ 2861 } data; 2862 }; 2863 2864 /** 2865 * union dmub_rb_cmd - DMUB inbox command. 2866 */ 2867 union dmub_rb_cmd { 2868 /** 2869 * Elements shared with all commands. 2870 */ 2871 struct dmub_rb_cmd_common cmd_common; 2872 /** 2873 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2874 */ 2875 struct dmub_rb_cmd_read_modify_write read_modify_write; 2876 /** 2877 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2878 */ 2879 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2880 /** 2881 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2882 */ 2883 struct dmub_rb_cmd_burst_write burst_write; 2884 /** 2885 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2886 */ 2887 struct dmub_rb_cmd_reg_wait reg_wait; 2888 /** 2889 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2890 */ 2891 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2892 /** 2893 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2894 */ 2895 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2896 /** 2897 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2898 */ 2899 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2900 /** 2901 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2902 */ 2903 struct dmub_rb_cmd_dpphy_init dpphy_init; 2904 /** 2905 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2906 */ 2907 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2908 /** 2909 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2910 */ 2911 struct dmub_rb_cmd_psr_set_version psr_set_version; 2912 /** 2913 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2914 */ 2915 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2916 /** 2917 * Definition of a DMUB_CMD__PSR_ENABLE command. 2918 */ 2919 struct dmub_rb_cmd_psr_enable psr_enable; 2920 /** 2921 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2922 */ 2923 struct dmub_rb_cmd_psr_set_level psr_set_level; 2924 /** 2925 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2926 */ 2927 struct dmub_rb_cmd_psr_force_static psr_force_static; 2928 /** 2929 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2930 */ 2931 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 2932 /** 2933 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2934 */ 2935 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 2936 /** 2937 * Definition of a DMUB_CMD__HW_LOCK command. 2938 * Command is used by driver and FW. 2939 */ 2940 struct dmub_rb_cmd_lock_hw lock_hw; 2941 /** 2942 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2943 */ 2944 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 2945 /** 2946 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2947 */ 2948 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 2949 /** 2950 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2951 */ 2952 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2953 /** 2954 * Definition of a DMUB_CMD__MALL command. 2955 */ 2956 struct dmub_rb_cmd_mall mall; 2957 /** 2958 * Definition of a DMUB_CMD__CAB command. 2959 */ 2960 struct dmub_rb_cmd_cab_for_ss cab; 2961 /** 2962 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2963 */ 2964 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2965 2966 /** 2967 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2968 */ 2969 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2970 2971 /** 2972 * Definition of DMUB_CMD__PANEL_CNTL commands. 2973 */ 2974 struct dmub_rb_cmd_panel_cntl panel_cntl; 2975 /** 2976 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2977 */ 2978 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2979 2980 /** 2981 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2982 */ 2983 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2984 2985 /** 2986 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2987 */ 2988 struct dmub_rb_cmd_abm_set_level abm_set_level; 2989 2990 /** 2991 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2992 */ 2993 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2994 2995 /** 2996 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2997 */ 2998 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2999 3000 /** 3001 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3002 */ 3003 struct dmub_rb_cmd_abm_init_config abm_init_config; 3004 3005 /** 3006 * Definition of a DMUB_CMD__ABM_PAUSE command. 3007 */ 3008 struct dmub_rb_cmd_abm_pause abm_pause; 3009 3010 /** 3011 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3012 */ 3013 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3014 3015 /** 3016 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3017 */ 3018 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3019 3020 /** 3021 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3022 */ 3023 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3024 struct dmub_rb_cmd_drr_update drr_update; 3025 /** 3026 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3027 */ 3028 struct dmub_rb_cmd_lvtma_control lvtma_control; 3029 /** 3030 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3031 */ 3032 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3033 /** 3034 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3035 */ 3036 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3037 /** 3038 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3039 */ 3040 struct dmub_rb_cmd_set_config_access set_config_access; 3041 /** 3042 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3043 */ 3044 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3045 /** 3046 * Definition of a DMUB_CMD__EDID_CEA command. 3047 */ 3048 struct dmub_rb_cmd_edid_cea edid_cea; 3049 /** 3050 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3051 */ 3052 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3053 3054 /** 3055 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3056 */ 3057 struct dmub_rb_cmd_query_hpd_state query_hpd; 3058 }; 3059 3060 /** 3061 * union dmub_rb_out_cmd - Outbox command 3062 */ 3063 union dmub_rb_out_cmd { 3064 /** 3065 * Parameters common to every command. 3066 */ 3067 struct dmub_rb_cmd_common cmd_common; 3068 /** 3069 * AUX reply command. 3070 */ 3071 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3072 /** 3073 * HPD notify command. 3074 */ 3075 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3076 /** 3077 * SET_CONFIG reply command. 3078 */ 3079 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3080 }; 3081 #pragma pack(pop) 3082 3083 3084 //============================================================================== 3085 //</DMUB_CMD>=================================================================== 3086 //============================================================================== 3087 //< DMUB_RB>==================================================================== 3088 //============================================================================== 3089 3090 #if defined(__cplusplus) 3091 extern "C" { 3092 #endif 3093 3094 /** 3095 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3096 */ 3097 struct dmub_rb_init_params { 3098 void *ctx; /**< Caller provided context pointer */ 3099 void *base_address; /**< CPU base address for ring's data */ 3100 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3101 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3102 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3103 }; 3104 3105 /** 3106 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3107 */ 3108 struct dmub_rb { 3109 void *base_address; /**< CPU address for the ring's data */ 3110 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3111 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3112 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3113 3114 void *ctx; /**< Caller provided context pointer */ 3115 void *dmub; /**< Pointer to the DMUB interface */ 3116 }; 3117 3118 /** 3119 * @brief Checks if the ringbuffer is empty. 3120 * 3121 * @param rb DMUB Ringbuffer 3122 * @return true if empty 3123 * @return false otherwise 3124 */ 3125 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3126 { 3127 return (rb->wrpt == rb->rptr); 3128 } 3129 3130 /** 3131 * @brief Checks if the ringbuffer is full 3132 * 3133 * @param rb DMUB Ringbuffer 3134 * @return true if full 3135 * @return false otherwise 3136 */ 3137 static inline bool dmub_rb_full(struct dmub_rb *rb) 3138 { 3139 uint32_t data_count; 3140 3141 if (rb->wrpt >= rb->rptr) 3142 data_count = rb->wrpt - rb->rptr; 3143 else 3144 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3145 3146 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3147 } 3148 3149 /** 3150 * @brief Pushes a command into the ringbuffer 3151 * 3152 * @param rb DMUB ringbuffer 3153 * @param cmd The command to push 3154 * @return true if the ringbuffer was not full 3155 * @return false otherwise 3156 */ 3157 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3158 const union dmub_rb_cmd *cmd) 3159 { 3160 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3161 const uint64_t *src = (const uint64_t *)cmd; 3162 uint8_t i; 3163 3164 if (dmub_rb_full(rb)) 3165 return false; 3166 3167 // copying data 3168 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3169 *dst++ = *src++; 3170 3171 rb->wrpt += DMUB_RB_CMD_SIZE; 3172 3173 if (rb->wrpt >= rb->capacity) 3174 rb->wrpt %= rb->capacity; 3175 3176 return true; 3177 } 3178 3179 /** 3180 * @brief Pushes a command into the DMUB outbox ringbuffer 3181 * 3182 * @param rb DMUB outbox ringbuffer 3183 * @param cmd Outbox command 3184 * @return true if not full 3185 * @return false otherwise 3186 */ 3187 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3188 const union dmub_rb_out_cmd *cmd) 3189 { 3190 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3191 const uint8_t *src = (const uint8_t *)cmd; 3192 3193 if (dmub_rb_full(rb)) 3194 return false; 3195 3196 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3197 3198 rb->wrpt += DMUB_RB_CMD_SIZE; 3199 3200 if (rb->wrpt >= rb->capacity) 3201 rb->wrpt %= rb->capacity; 3202 3203 return true; 3204 } 3205 3206 /** 3207 * @brief Returns the next unprocessed command in the ringbuffer. 3208 * 3209 * @param rb DMUB ringbuffer 3210 * @param cmd The command to return 3211 * @return true if not empty 3212 * @return false otherwise 3213 */ 3214 static inline bool dmub_rb_front(struct dmub_rb *rb, 3215 union dmub_rb_cmd **cmd) 3216 { 3217 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3218 3219 if (dmub_rb_empty(rb)) 3220 return false; 3221 3222 *cmd = (union dmub_rb_cmd *)rb_cmd; 3223 3224 return true; 3225 } 3226 3227 /** 3228 * @brief Determines the next ringbuffer offset. 3229 * 3230 * @param rb DMUB inbox ringbuffer 3231 * @param num_cmds Number of commands 3232 * @param next_rptr The next offset in the ringbuffer 3233 */ 3234 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3235 uint32_t num_cmds, 3236 uint32_t *next_rptr) 3237 { 3238 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3239 3240 if (*next_rptr >= rb->capacity) 3241 *next_rptr %= rb->capacity; 3242 } 3243 3244 /** 3245 * @brief Returns a pointer to a command in the inbox. 3246 * 3247 * @param rb DMUB inbox ringbuffer 3248 * @param cmd The inbox command to return 3249 * @param rptr The ringbuffer offset 3250 * @return true if not empty 3251 * @return false otherwise 3252 */ 3253 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3254 union dmub_rb_cmd **cmd, 3255 uint32_t rptr) 3256 { 3257 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3258 3259 if (dmub_rb_empty(rb)) 3260 return false; 3261 3262 *cmd = (union dmub_rb_cmd *)rb_cmd; 3263 3264 return true; 3265 } 3266 3267 /** 3268 * @brief Returns the next unprocessed command in the outbox. 3269 * 3270 * @param rb DMUB outbox ringbuffer 3271 * @param cmd The outbox command to return 3272 * @return true if not empty 3273 * @return false otherwise 3274 */ 3275 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3276 union dmub_rb_out_cmd *cmd) 3277 { 3278 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3279 uint64_t *dst = (uint64_t *)cmd; 3280 uint8_t i; 3281 3282 if (dmub_rb_empty(rb)) 3283 return false; 3284 3285 // copying data 3286 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3287 *dst++ = *src++; 3288 3289 return true; 3290 } 3291 3292 /** 3293 * @brief Removes the front entry in the ringbuffer. 3294 * 3295 * @param rb DMUB ringbuffer 3296 * @return true if the command was removed 3297 * @return false if there were no commands 3298 */ 3299 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3300 { 3301 if (dmub_rb_empty(rb)) 3302 return false; 3303 3304 rb->rptr += DMUB_RB_CMD_SIZE; 3305 3306 if (rb->rptr >= rb->capacity) 3307 rb->rptr %= rb->capacity; 3308 3309 return true; 3310 } 3311 3312 /** 3313 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3314 * 3315 * Avoids a race condition where DMCUB accesses memory while 3316 * there are still writes in flight to framebuffer. 3317 * 3318 * @param rb DMUB ringbuffer 3319 */ 3320 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3321 { 3322 uint32_t rptr = rb->rptr; 3323 uint32_t wptr = rb->wrpt; 3324 3325 while (rptr != wptr) { 3326 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3327 uint8_t i; 3328 3329 /* Don't remove this. 3330 * The contents need to actually be read from the ring buffer 3331 * for this function to be effective. 3332 */ 3333 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3334 (void)READ_ONCE(*data++); 3335 3336 rptr += DMUB_RB_CMD_SIZE; 3337 if (rptr >= rb->capacity) 3338 rptr %= rb->capacity; 3339 } 3340 } 3341 3342 /** 3343 * @brief Initializes a DMCUB ringbuffer 3344 * 3345 * @param rb DMUB ringbuffer 3346 * @param init_params initial configuration for the ringbuffer 3347 */ 3348 static inline void dmub_rb_init(struct dmub_rb *rb, 3349 struct dmub_rb_init_params *init_params) 3350 { 3351 rb->base_address = init_params->base_address; 3352 rb->capacity = init_params->capacity; 3353 rb->rptr = init_params->read_ptr; 3354 rb->wrpt = init_params->write_ptr; 3355 } 3356 3357 /** 3358 * @brief Copies output data from in/out commands into the given command. 3359 * 3360 * @param rb DMUB ringbuffer 3361 * @param cmd Command to copy data into 3362 */ 3363 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3364 union dmub_rb_cmd *cmd) 3365 { 3366 // Copy rb entry back into command 3367 uint8_t *rd_ptr = (rb->rptr == 0) ? 3368 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3369 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3370 3371 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3372 } 3373 3374 #if defined(__cplusplus) 3375 } 3376 #endif 3377 3378 //============================================================================== 3379 //</DMUB_RB>==================================================================== 3380 //============================================================================== 3381 3382 #endif /* _DMUB_CMD_H_ */ 3383