1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #include "dmub_types.h" 30 #include "dmub_cmd_dal.h" 31 #include "dmub_cmd_vbios.h" 32 #include "atomfirmware.h" 33 34 #define DMUB_RB_CMD_SIZE 64 35 #define DMUB_RB_MAX_ENTRY 128 36 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 37 #define REG_SET_MASK 0xFFFF 38 39 40 /* 41 * Command IDs should be treated as stable ABI. 42 * Do not reuse or modify IDs. 43 */ 44 45 enum dmub_cmd_type { 46 DMUB_CMD__NULL = 0, 47 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 48 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 49 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 50 DMUB_CMD__REG_REG_WAIT = 4, 51 DMUB_CMD__PLAT_54186_WA = 5, 52 DMUB_CMD__PSR = 64, 53 DMUB_CMD__ABM = 66, 54 DMUB_CMD__VBIOS = 128, 55 }; 56 57 #pragma pack(push, 1) 58 59 struct dmub_cmd_header { 60 unsigned int type : 8; 61 unsigned int sub_type : 8; 62 unsigned int reserved0 : 8; 63 unsigned int payload_bytes : 6; /* up to 60 bytes */ 64 unsigned int reserved1 : 2; 65 }; 66 67 /* 68 * Read modify write 69 * 70 * 60 payload bytes can hold up to 5 sets of read modify writes, 71 * each take 3 dwords. 72 * 73 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 74 * 75 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 76 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 77 */ 78 struct dmub_cmd_read_modify_write_sequence { 79 uint32_t addr; 80 uint32_t modify_mask; 81 uint32_t modify_value; 82 }; 83 84 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 85 struct dmub_rb_cmd_read_modify_write { 86 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 87 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 88 }; 89 90 /* 91 * Update a register with specified masks and values sequeunce 92 * 93 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 94 * 95 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 96 * 97 * 98 * USE CASE: 99 * 1. auto-increment register where additional read would update pointer and produce wrong result 100 * 2. toggle a bit without read in the middle 101 */ 102 103 struct dmub_cmd_reg_field_update_sequence { 104 uint32_t modify_mask; // 0xffff'ffff to skip initial read 105 uint32_t modify_value; 106 }; 107 108 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 109 110 struct dmub_rb_cmd_reg_field_update_sequence { 111 struct dmub_cmd_header header; 112 uint32_t addr; 113 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 114 }; 115 116 117 /* 118 * Burst write 119 * 120 * support use case such as writing out LUTs. 121 * 122 * 60 payload bytes can hold up to 14 values to write to given address 123 * 124 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 125 */ 126 #define DMUB_BURST_WRITE_VALUES__MAX 14 127 struct dmub_rb_cmd_burst_write { 128 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 129 uint32_t addr; 130 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 131 }; 132 133 134 struct dmub_rb_cmd_common { 135 struct dmub_cmd_header header; 136 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 137 }; 138 139 struct dmub_cmd_reg_wait_data { 140 uint32_t addr; 141 uint32_t mask; 142 uint32_t condition_field_value; 143 uint32_t time_out_us; 144 }; 145 146 struct dmub_rb_cmd_reg_wait { 147 struct dmub_cmd_header header; 148 struct dmub_cmd_reg_wait_data reg_wait; 149 }; 150 151 #ifndef PHYSICAL_ADDRESS_LOC 152 #define PHYSICAL_ADDRESS_LOC union large_integer 153 #endif 154 155 struct dmub_cmd_PLAT_54186_wa { 156 uint32_t DCSURF_SURFACE_CONTROL; 157 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 158 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 159 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 160 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 161 struct { 162 uint8_t hubp_inst : 4; 163 uint8_t tmz_surface : 1; 164 uint8_t immediate :1; 165 uint8_t vmid : 4; 166 uint8_t grph_stereo : 1; 167 uint32_t reserved : 21; 168 } flip_params; 169 uint32_t reserved[9]; 170 }; 171 172 struct dmub_rb_cmd_PLAT_54186_wa { 173 struct dmub_cmd_header header; 174 struct dmub_cmd_PLAT_54186_wa flip; 175 }; 176 177 struct dmub_cmd_digx_encoder_control_data { 178 union dig_encoder_control_parameters_v1_5 dig; 179 }; 180 181 struct dmub_rb_cmd_digx_encoder_control { 182 struct dmub_cmd_header header; 183 struct dmub_cmd_digx_encoder_control_data encoder_control; 184 }; 185 186 struct dmub_cmd_set_pixel_clock_data { 187 struct set_pixel_clock_parameter_v1_7 clk; 188 }; 189 190 struct dmub_rb_cmd_set_pixel_clock { 191 struct dmub_cmd_header header; 192 struct dmub_cmd_set_pixel_clock_data pixel_clock; 193 }; 194 195 struct dmub_cmd_enable_disp_power_gating_data { 196 struct enable_disp_power_gating_parameters_v2_1 pwr; 197 }; 198 199 struct dmub_rb_cmd_enable_disp_power_gating { 200 struct dmub_cmd_header header; 201 struct dmub_cmd_enable_disp_power_gating_data power_gating; 202 }; 203 204 struct dmub_cmd_dig1_transmitter_control_data { 205 struct dig_transmitter_control_parameters_v1_6 dig; 206 }; 207 208 struct dmub_rb_cmd_dig1_transmitter_control { 209 struct dmub_cmd_header header; 210 struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 211 }; 212 213 struct dmub_rb_cmd_dpphy_init { 214 struct dmub_cmd_header header; 215 uint8_t reserved[60]; 216 }; 217 218 struct dmub_cmd_psr_copy_settings_data { 219 uint16_t psr_level; 220 uint8_t dpp_inst; 221 uint8_t mpcc_inst; 222 uint8_t opp_inst; 223 uint8_t otg_inst; 224 uint8_t digfe_inst; 225 uint8_t digbe_inst; 226 uint8_t dpphy_inst; 227 uint8_t aux_inst; 228 uint8_t smu_optimizations_en; 229 uint8_t frame_delay; 230 uint8_t frame_cap_ind; 231 }; 232 233 struct dmub_rb_cmd_psr_copy_settings { 234 struct dmub_cmd_header header; 235 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 236 }; 237 238 struct dmub_cmd_psr_set_level_data { 239 uint16_t psr_level; 240 }; 241 242 struct dmub_rb_cmd_psr_set_level { 243 struct dmub_cmd_header header; 244 struct dmub_cmd_psr_set_level_data psr_set_level_data; 245 }; 246 247 struct dmub_rb_cmd_psr_enable { 248 struct dmub_cmd_header header; 249 }; 250 251 struct dmub_cmd_psr_set_version_data { 252 enum psr_version version; // PSR version 1 or 2 253 }; 254 255 struct dmub_rb_cmd_psr_set_version { 256 struct dmub_cmd_header header; 257 struct dmub_cmd_psr_set_version_data psr_set_version_data; 258 }; 259 260 struct dmub_cmd_abm_set_pipe_data { 261 uint32_t ramping_boundary; 262 uint32_t otg_inst; 263 }; 264 265 struct dmub_rb_cmd_abm_set_pipe { 266 struct dmub_cmd_header header; 267 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 268 }; 269 270 struct dmub_cmd_abm_set_backlight_data { 271 uint32_t frame_ramp; 272 }; 273 274 struct dmub_rb_cmd_abm_set_backlight { 275 struct dmub_cmd_header header; 276 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 277 }; 278 279 struct dmub_cmd_abm_set_level_data { 280 uint32_t level; 281 }; 282 283 struct dmub_rb_cmd_abm_set_level { 284 struct dmub_cmd_header header; 285 struct dmub_cmd_abm_set_level_data abm_set_level_data; 286 }; 287 288 struct dmub_cmd_abm_set_ambient_level_data { 289 uint32_t ambient_lux; 290 }; 291 292 struct dmub_rb_cmd_abm_set_ambient_level { 293 struct dmub_cmd_header header; 294 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 295 }; 296 297 struct dmub_cmd_abm_set_pwm_frac_data { 298 uint32_t fractional_pwm; 299 }; 300 301 struct dmub_rb_cmd_abm_set_pwm_frac { 302 struct dmub_cmd_header header; 303 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 304 }; 305 306 struct dmub_cmd_abm_init_config_data { 307 union dmub_addr src; 308 uint16_t bytes; 309 }; 310 311 struct dmub_rb_cmd_abm_init_config { 312 struct dmub_cmd_header header; 313 struct dmub_cmd_abm_init_config_data abm_init_config_data; 314 }; 315 316 union dmub_rb_cmd { 317 struct dmub_rb_cmd_read_modify_write read_modify_write; 318 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 319 struct dmub_rb_cmd_burst_write burst_write; 320 struct dmub_rb_cmd_reg_wait reg_wait; 321 struct dmub_rb_cmd_common cmd_common; 322 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 323 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 324 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 325 struct dmub_rb_cmd_dpphy_init dpphy_init; 326 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 327 struct dmub_rb_cmd_psr_set_version psr_set_version; 328 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 329 struct dmub_rb_cmd_psr_enable psr_enable; 330 struct dmub_rb_cmd_psr_set_level psr_set_level; 331 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 332 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 333 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 334 struct dmub_rb_cmd_abm_set_level abm_set_level; 335 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 336 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 337 struct dmub_rb_cmd_abm_init_config abm_init_config; 338 }; 339 340 #pragma pack(pop) 341 342 #endif /* _DMUB_CMD_H_ */ 343