1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 /* Firmware versioning. */ 48 #ifdef DMUB_EXPOSE_VERSION 49 #define DMUB_FW_VERSION_GIT_HASH 0xf0c64c97 50 #define DMUB_FW_VERSION_MAJOR 0 51 #define DMUB_FW_VERSION_MINOR 0 52 #define DMUB_FW_VERSION_REVISION 87 53 #define DMUB_FW_VERSION_TEST 0 54 #define DMUB_FW_VERSION_VBIOS 0 55 #define DMUB_FW_VERSION_HOTFIX 0 56 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 57 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 58 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 59 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 60 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 61 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 62 63 #endif 64 65 //<DMUB_TYPES>================================================================== 66 /* Basic type definitions. */ 67 68 #define __forceinline inline 69 70 /** 71 * Flag from driver to indicate that ABM should be disabled gradually 72 * by slowly reversing all backlight programming and pixel compensation. 73 */ 74 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 75 76 /** 77 * Flag from driver to indicate that ABM should be disabled immediately 78 * and undo all backlight programming and pixel compensation. 79 */ 80 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 81 82 /** 83 * Flag from driver to indicate that ABM should be disabled immediately 84 * and keep the current backlight programming and pixel compensation. 85 */ 86 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 87 88 /** 89 * Flag from driver to set the current ABM pipe index or ABM operating level. 90 */ 91 #define SET_ABM_PIPE_NORMAL 1 92 93 /** 94 * Number of ambient light levels in ABM algorithm. 95 */ 96 #define NUM_AMBI_LEVEL 5 97 98 /** 99 * Number of operating/aggression levels in ABM algorithm. 100 */ 101 #define NUM_AGGR_LEVEL 4 102 103 /** 104 * Number of segments in the gamma curve. 105 */ 106 #define NUM_POWER_FN_SEGS 8 107 108 /** 109 * Number of segments in the backlight curve. 110 */ 111 #define NUM_BL_CURVE_SEGS 16 112 113 /* Maximum number of streams on any ASIC. */ 114 #define DMUB_MAX_STREAMS 6 115 116 /* Maximum number of planes on any ASIC. */ 117 #define DMUB_MAX_PLANES 6 118 119 /* Trace buffer offset for entry */ 120 #define TRACE_BUFFER_ENTRY_OFFSET 16 121 122 /** 123 * 124 * PSR control version legacy 125 */ 126 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 127 /** 128 * PSR control version with multi edp support 129 */ 130 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 131 132 133 /** 134 * ABM control version legacy 135 */ 136 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 137 138 /** 139 * ABM control version with multi edp support 140 */ 141 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 142 143 /** 144 * Physical framebuffer address location, 64-bit. 145 */ 146 #ifndef PHYSICAL_ADDRESS_LOC 147 #define PHYSICAL_ADDRESS_LOC union large_integer 148 #endif 149 150 /** 151 * OS/FW agnostic memcpy 152 */ 153 #ifndef dmub_memcpy 154 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 155 #endif 156 157 /** 158 * OS/FW agnostic memset 159 */ 160 #ifndef dmub_memset 161 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 162 #endif 163 164 #if defined(__cplusplus) 165 extern "C" { 166 #endif 167 168 /** 169 * OS/FW agnostic udelay 170 */ 171 #ifndef dmub_udelay 172 #define dmub_udelay(microseconds) udelay(microseconds) 173 #endif 174 175 /** 176 * Number of nanoseconds per DMUB tick. 177 * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default. 178 * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true. 179 */ 180 #define NS_PER_DMUB_TICK 10 181 182 /** 183 * union dmub_addr - DMUB physical/virtual 64-bit address. 184 */ 185 union dmub_addr { 186 struct { 187 uint32_t low_part; /**< Lower 32 bits */ 188 uint32_t high_part; /**< Upper 32 bits */ 189 } u; /*<< Low/high bit access */ 190 uint64_t quad_part; /*<< 64 bit address */ 191 }; 192 193 /** 194 * Flags that can be set by driver to change some PSR behaviour. 195 */ 196 union dmub_psr_debug_flags { 197 /** 198 * Debug flags. 199 */ 200 struct { 201 /** 202 * Enable visual confirm in FW. 203 */ 204 uint32_t visual_confirm : 1; 205 /** 206 * Use HW Lock Mgr object to do HW locking in FW. 207 */ 208 uint32_t use_hw_lock_mgr : 1; 209 210 /** 211 * Unused. 212 * TODO: Remove. 213 */ 214 uint32_t log_line_nums : 1; 215 } bitfields; 216 217 /** 218 * Union for debug flags. 219 */ 220 uint32_t u32All; 221 }; 222 223 /** 224 * DMUB feature capabilities. 225 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 226 */ 227 struct dmub_feature_caps { 228 /** 229 * Max PSR version supported by FW. 230 */ 231 uint8_t psr; 232 uint8_t reserved[7]; 233 }; 234 235 #if defined(__cplusplus) 236 } 237 #endif 238 239 //============================================================================== 240 //</DMUB_TYPES>================================================================= 241 //============================================================================== 242 //< DMUB_META>================================================================== 243 //============================================================================== 244 #pragma pack(push, 1) 245 246 /* Magic value for identifying dmub_fw_meta_info */ 247 #define DMUB_FW_META_MAGIC 0x444D5542 248 249 /* Offset from the end of the file to the dmub_fw_meta_info */ 250 #define DMUB_FW_META_OFFSET 0x24 251 252 /** 253 * struct dmub_fw_meta_info - metadata associated with fw binary 254 * 255 * NOTE: This should be considered a stable API. Fields should 256 * not be repurposed or reordered. New fields should be 257 * added instead to extend the structure. 258 * 259 * @magic_value: magic value identifying DMUB firmware meta info 260 * @fw_region_size: size of the firmware state region 261 * @trace_buffer_size: size of the tracebuffer region 262 * @fw_version: the firmware version information 263 * @dal_fw: 1 if the firmware is DAL 264 */ 265 struct dmub_fw_meta_info { 266 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 267 uint32_t fw_region_size; /**< size of the firmware state region */ 268 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 269 uint32_t fw_version; /**< the firmware version information */ 270 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 271 uint8_t reserved[3]; /**< padding bits */ 272 }; 273 274 /** 275 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 276 */ 277 union dmub_fw_meta { 278 struct dmub_fw_meta_info info; /**< metadata info */ 279 uint8_t reserved[64]; /**< padding bits */ 280 }; 281 282 #pragma pack(pop) 283 284 //============================================================================== 285 //< DMUB Trace Buffer>================================================================ 286 //============================================================================== 287 /** 288 * dmub_trace_code_t - firmware trace code, 32-bits 289 */ 290 typedef uint32_t dmub_trace_code_t; 291 292 /** 293 * struct dmcub_trace_buf_entry - Firmware trace entry 294 */ 295 struct dmcub_trace_buf_entry { 296 dmub_trace_code_t trace_code; /**< trace code for the event */ 297 uint32_t tick_count; /**< the tick count at time of trace */ 298 uint32_t param0; /**< trace defined parameter 0 */ 299 uint32_t param1; /**< trace defined parameter 1 */ 300 }; 301 302 //============================================================================== 303 //< DMUB_STATUS>================================================================ 304 //============================================================================== 305 306 /** 307 * DMCUB scratch registers can be used to determine firmware status. 308 * Current scratch register usage is as follows: 309 * 310 * SCRATCH0: FW Boot Status register 311 * SCRATCH5: LVTMA Status Register 312 * SCRATCH15: FW Boot Options register 313 */ 314 315 /** 316 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 317 */ 318 union dmub_fw_boot_status { 319 struct { 320 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 321 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 322 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 323 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 324 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 325 uint32_t reserved : 1; 326 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 327 328 } bits; /**< status bits */ 329 uint32_t all; /**< 32-bit access to status bits */ 330 }; 331 332 /** 333 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 334 */ 335 enum dmub_fw_boot_status_bit { 336 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 337 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 338 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 339 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 340 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 341 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 342 }; 343 344 /* Register bit definition for SCRATCH5 */ 345 union dmub_lvtma_status { 346 struct { 347 uint32_t psp_ok : 1; 348 uint32_t edp_on : 1; 349 uint32_t reserved : 30; 350 } bits; 351 uint32_t all; 352 }; 353 354 enum dmub_lvtma_status_bit { 355 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 356 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 357 }; 358 359 /** 360 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 361 */ 362 union dmub_fw_boot_options { 363 struct { 364 uint32_t pemu_env : 1; /**< 1 if PEMU */ 365 uint32_t fpga_env : 1; /**< 1 if FPGA */ 366 uint32_t optimized_init : 1; /**< 1 if optimized init */ 367 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 368 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 369 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 370 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 371 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 372 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 373 uint32_t reserved_unreleased2: 1; /**< reserved for an unreleased feature */ 374 uint32_t reserved : 22; /**< reserved */ 375 } bits; /**< boot bits */ 376 uint32_t all; /**< 32-bit access to bits */ 377 }; 378 379 enum dmub_fw_boot_options_bit { 380 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 381 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 382 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 383 }; 384 385 //============================================================================== 386 //</DMUB_STATUS>================================================================ 387 //============================================================================== 388 //< DMUB_VBIOS>================================================================= 389 //============================================================================== 390 391 /* 392 * enum dmub_cmd_vbios_type - VBIOS commands. 393 * 394 * Command IDs should be treated as stable ABI. 395 * Do not reuse or modify IDs. 396 */ 397 enum dmub_cmd_vbios_type { 398 /** 399 * Configures the DIG encoder. 400 */ 401 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 402 /** 403 * Controls the PHY. 404 */ 405 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 406 /** 407 * Sets the pixel clock/symbol clock. 408 */ 409 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 410 /** 411 * Enables or disables power gating. 412 */ 413 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 414 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 415 }; 416 417 //============================================================================== 418 //</DMUB_VBIOS>================================================================= 419 //============================================================================== 420 //< DMUB_GPINT>================================================================= 421 //============================================================================== 422 423 /** 424 * The shifts and masks below may alternatively be used to format and read 425 * the command register bits. 426 */ 427 428 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 429 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 430 431 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 432 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 433 434 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 435 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 436 437 /** 438 * Command responses. 439 */ 440 441 /** 442 * Return response for DMUB_GPINT__STOP_FW command. 443 */ 444 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 445 446 /** 447 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 448 */ 449 union dmub_gpint_data_register { 450 struct { 451 uint32_t param : 16; /**< 16-bit parameter */ 452 uint32_t command_code : 12; /**< GPINT command */ 453 uint32_t status : 4; /**< Command status bit */ 454 } bits; /**< GPINT bit access */ 455 uint32_t all; /**< GPINT 32-bit access */ 456 }; 457 458 /* 459 * enum dmub_gpint_command - GPINT command to DMCUB FW 460 * 461 * Command IDs should be treated as stable ABI. 462 * Do not reuse or modify IDs. 463 */ 464 enum dmub_gpint_command { 465 /** 466 * Invalid command, ignored. 467 */ 468 DMUB_GPINT__INVALID_COMMAND = 0, 469 /** 470 * DESC: Queries the firmware version. 471 * RETURN: Firmware version. 472 */ 473 DMUB_GPINT__GET_FW_VERSION = 1, 474 /** 475 * DESC: Halts the firmware. 476 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 477 */ 478 DMUB_GPINT__STOP_FW = 2, 479 /** 480 * DESC: Get PSR state from FW. 481 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 482 */ 483 DMUB_GPINT__GET_PSR_STATE = 7, 484 /** 485 * DESC: Notifies DMCUB of the currently active streams. 486 * ARGS: Stream mask, 1 bit per active stream index. 487 */ 488 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 489 /** 490 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 491 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 492 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 493 * RETURN: PSR residency in milli-percent. 494 */ 495 DMUB_GPINT__PSR_RESIDENCY = 9, 496 497 /** 498 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 499 */ 500 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 501 }; 502 503 /** 504 * INBOX0 generic command definition 505 */ 506 union dmub_inbox0_cmd_common { 507 struct { 508 uint32_t command_code: 8; /**< INBOX0 command code */ 509 uint32_t param: 24; /**< 24-bit parameter */ 510 } bits; 511 uint32_t all; 512 }; 513 514 /** 515 * INBOX0 hw_lock command definition 516 */ 517 union dmub_inbox0_cmd_lock_hw { 518 struct { 519 uint32_t command_code: 8; 520 521 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 522 uint32_t hw_lock_client: 1; 523 524 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 525 uint32_t otg_inst: 3; 526 uint32_t opp_inst: 3; 527 uint32_t dig_inst: 3; 528 529 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 530 uint32_t lock_pipe: 1; 531 uint32_t lock_cursor: 1; 532 uint32_t lock_dig: 1; 533 uint32_t triple_buffer_lock: 1; 534 535 uint32_t lock: 1; /**< Lock */ 536 uint32_t should_release: 1; /**< Release */ 537 uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ 538 } bits; 539 uint32_t all; 540 }; 541 542 union dmub_inbox0_data_register { 543 union dmub_inbox0_cmd_common inbox0_cmd_common; 544 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 545 }; 546 547 enum dmub_inbox0_command { 548 /** 549 * DESC: Invalid command, ignored. 550 */ 551 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 552 /** 553 * DESC: Notification to acquire/release HW lock 554 * ARGS: 555 */ 556 DMUB_INBOX0_CMD__HW_LOCK = 1, 557 }; 558 //============================================================================== 559 //</DMUB_GPINT>================================================================= 560 //============================================================================== 561 //< DMUB_CMD>=================================================================== 562 //============================================================================== 563 564 /** 565 * Size in bytes of each DMUB command. 566 */ 567 #define DMUB_RB_CMD_SIZE 64 568 569 /** 570 * Maximum number of items in the DMUB ringbuffer. 571 */ 572 #define DMUB_RB_MAX_ENTRY 128 573 574 /** 575 * Ringbuffer size in bytes. 576 */ 577 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 578 579 /** 580 * REG_SET mask for reg offload. 581 */ 582 #define REG_SET_MASK 0xFFFF 583 584 /* 585 * enum dmub_cmd_type - DMUB inbox command. 586 * 587 * Command IDs should be treated as stable ABI. 588 * Do not reuse or modify IDs. 589 */ 590 enum dmub_cmd_type { 591 /** 592 * Invalid command. 593 */ 594 DMUB_CMD__NULL = 0, 595 /** 596 * Read modify write register sequence offload. 597 */ 598 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 599 /** 600 * Field update register sequence offload. 601 */ 602 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 603 /** 604 * Burst write sequence offload. 605 */ 606 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 607 /** 608 * Reg wait sequence offload. 609 */ 610 DMUB_CMD__REG_REG_WAIT = 4, 611 /** 612 * Workaround to avoid HUBP underflow during NV12 playback. 613 */ 614 DMUB_CMD__PLAT_54186_WA = 5, 615 /** 616 * Command type used to query FW feature caps. 617 */ 618 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 619 /** 620 * Command type used for all PSR commands. 621 */ 622 DMUB_CMD__PSR = 64, 623 /** 624 * Command type used for all MALL commands. 625 */ 626 DMUB_CMD__MALL = 65, 627 /** 628 * Command type used for all ABM commands. 629 */ 630 DMUB_CMD__ABM = 66, 631 /** 632 * Command type used for HW locking in FW. 633 */ 634 DMUB_CMD__HW_LOCK = 69, 635 /** 636 * Command type used to access DP AUX. 637 */ 638 DMUB_CMD__DP_AUX_ACCESS = 70, 639 /** 640 * Command type used for OUTBOX1 notification enable 641 */ 642 DMUB_CMD__OUTBOX1_ENABLE = 71, 643 /** 644 * Command type used for all idle optimization commands. 645 */ 646 DMUB_CMD__IDLE_OPT = 72, 647 /** 648 * Command type used for all clock manager commands. 649 */ 650 DMUB_CMD__CLK_MGR = 73, 651 /** 652 * Command type used for all panel control commands. 653 */ 654 DMUB_CMD__PANEL_CNTL = 74, 655 /** 656 * Command type used for interfacing with DPIA. 657 */ 658 DMUB_CMD__DPIA = 77, 659 /** 660 * Command type used for EDID CEA parsing 661 */ 662 DMUB_CMD__EDID_CEA = 79, 663 /** 664 * Command type used for all VBIOS interface commands. 665 */ 666 DMUB_CMD__VBIOS = 128, 667 }; 668 669 /** 670 * enum dmub_out_cmd_type - DMUB outbox commands. 671 */ 672 enum dmub_out_cmd_type { 673 /** 674 * Invalid outbox command, ignored. 675 */ 676 DMUB_OUT_CMD__NULL = 0, 677 /** 678 * Command type used for DP AUX Reply data notification 679 */ 680 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 681 /** 682 * Command type used for DP HPD event notification 683 */ 684 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 685 /** 686 * Command type used for SET_CONFIG Reply notification 687 */ 688 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 689 }; 690 691 /* DMUB_CMD__DPIA command sub-types. */ 692 enum dmub_cmd_dpia_type { 693 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 694 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 695 }; 696 697 #pragma pack(push, 1) 698 699 /** 700 * struct dmub_cmd_header - Common command header fields. 701 */ 702 struct dmub_cmd_header { 703 unsigned int type : 8; /**< command type */ 704 unsigned int sub_type : 8; /**< command sub type */ 705 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 706 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 707 unsigned int reserved0 : 6; /**< reserved bits */ 708 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 709 unsigned int reserved1 : 2; /**< reserved bits */ 710 }; 711 712 /* 713 * struct dmub_cmd_read_modify_write_sequence - Read modify write 714 * 715 * 60 payload bytes can hold up to 5 sets of read modify writes, 716 * each take 3 dwords. 717 * 718 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 719 * 720 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 721 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 722 */ 723 struct dmub_cmd_read_modify_write_sequence { 724 uint32_t addr; /**< register address */ 725 uint32_t modify_mask; /**< modify mask */ 726 uint32_t modify_value; /**< modify value */ 727 }; 728 729 /** 730 * Maximum number of ops in read modify write sequence. 731 */ 732 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 733 734 /** 735 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 736 */ 737 struct dmub_rb_cmd_read_modify_write { 738 struct dmub_cmd_header header; /**< command header */ 739 /** 740 * Read modify write sequence. 741 */ 742 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 743 }; 744 745 /* 746 * Update a register with specified masks and values sequeunce 747 * 748 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 749 * 750 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 751 * 752 * 753 * USE CASE: 754 * 1. auto-increment register where additional read would update pointer and produce wrong result 755 * 2. toggle a bit without read in the middle 756 */ 757 758 struct dmub_cmd_reg_field_update_sequence { 759 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 760 uint32_t modify_value; /**< value to update with */ 761 }; 762 763 /** 764 * Maximum number of ops in field update sequence. 765 */ 766 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 767 768 /** 769 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 770 */ 771 struct dmub_rb_cmd_reg_field_update_sequence { 772 struct dmub_cmd_header header; /**< command header */ 773 uint32_t addr; /**< register address */ 774 /** 775 * Field update sequence. 776 */ 777 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 778 }; 779 780 781 /** 782 * Maximum number of burst write values. 783 */ 784 #define DMUB_BURST_WRITE_VALUES__MAX 14 785 786 /* 787 * struct dmub_rb_cmd_burst_write - Burst write 788 * 789 * support use case such as writing out LUTs. 790 * 791 * 60 payload bytes can hold up to 14 values to write to given address 792 * 793 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 794 */ 795 struct dmub_rb_cmd_burst_write { 796 struct dmub_cmd_header header; /**< command header */ 797 uint32_t addr; /**< register start address */ 798 /** 799 * Burst write register values. 800 */ 801 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 802 }; 803 804 /** 805 * struct dmub_rb_cmd_common - Common command header 806 */ 807 struct dmub_rb_cmd_common { 808 struct dmub_cmd_header header; /**< command header */ 809 /** 810 * Padding to RB_CMD_SIZE 811 */ 812 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 813 }; 814 815 /** 816 * struct dmub_cmd_reg_wait_data - Register wait data 817 */ 818 struct dmub_cmd_reg_wait_data { 819 uint32_t addr; /**< Register address */ 820 uint32_t mask; /**< Mask for register bits */ 821 uint32_t condition_field_value; /**< Value to wait for */ 822 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 823 }; 824 825 /** 826 * struct dmub_rb_cmd_reg_wait - Register wait command 827 */ 828 struct dmub_rb_cmd_reg_wait { 829 struct dmub_cmd_header header; /**< Command header */ 830 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 831 }; 832 833 /** 834 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 835 * 836 * Reprograms surface parameters to avoid underflow. 837 */ 838 struct dmub_cmd_PLAT_54186_wa { 839 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 840 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 841 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 842 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 843 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 844 struct { 845 uint8_t hubp_inst : 4; /**< HUBP instance */ 846 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 847 uint8_t immediate :1; /**< Immediate flip */ 848 uint8_t vmid : 4; /**< VMID */ 849 uint8_t grph_stereo : 1; /**< 1 if stereo */ 850 uint32_t reserved : 21; /**< Reserved */ 851 } flip_params; /**< Pageflip parameters */ 852 uint32_t reserved[9]; /**< Reserved bits */ 853 }; 854 855 /** 856 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 857 */ 858 struct dmub_rb_cmd_PLAT_54186_wa { 859 struct dmub_cmd_header header; /**< Command header */ 860 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 861 }; 862 863 /** 864 * struct dmub_rb_cmd_mall - MALL command data. 865 */ 866 struct dmub_rb_cmd_mall { 867 struct dmub_cmd_header header; /**< Common command header */ 868 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 869 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 870 uint32_t tmr_delay; /**< Timer delay */ 871 uint32_t tmr_scale; /**< Timer scale */ 872 uint16_t cursor_width; /**< Cursor width in pixels */ 873 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 874 uint16_t cursor_height; /**< Cursor height in pixels */ 875 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 876 uint8_t debug_bits; /**< Debug bits */ 877 878 uint8_t reserved1; /**< Reserved bits */ 879 uint8_t reserved2; /**< Reserved bits */ 880 }; 881 882 /** 883 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 884 */ 885 enum dmub_cmd_idle_opt_type { 886 /** 887 * DCN hardware restore. 888 */ 889 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 890 891 /** 892 * DCN hardware save. 893 */ 894 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 895 }; 896 897 /** 898 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 899 */ 900 struct dmub_rb_cmd_idle_opt_dcn_restore { 901 struct dmub_cmd_header header; /**< header */ 902 }; 903 904 /** 905 * struct dmub_clocks - Clock update notification. 906 */ 907 struct dmub_clocks { 908 uint32_t dispclk_khz; /**< dispclk kHz */ 909 uint32_t dppclk_khz; /**< dppclk kHz */ 910 uint32_t dcfclk_khz; /**< dcfclk kHz */ 911 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 912 }; 913 914 /** 915 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 916 */ 917 enum dmub_cmd_clk_mgr_type { 918 /** 919 * Notify DMCUB of clock update. 920 */ 921 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 922 }; 923 924 /** 925 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 926 */ 927 struct dmub_rb_cmd_clk_mgr_notify_clocks { 928 struct dmub_cmd_header header; /**< header */ 929 struct dmub_clocks clocks; /**< clock data */ 930 }; 931 932 /** 933 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 934 */ 935 struct dmub_cmd_digx_encoder_control_data { 936 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 937 }; 938 939 /** 940 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 941 */ 942 struct dmub_rb_cmd_digx_encoder_control { 943 struct dmub_cmd_header header; /**< header */ 944 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 945 }; 946 947 /** 948 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 949 */ 950 struct dmub_cmd_set_pixel_clock_data { 951 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 952 }; 953 954 /** 955 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 956 */ 957 struct dmub_rb_cmd_set_pixel_clock { 958 struct dmub_cmd_header header; /**< header */ 959 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 960 }; 961 962 /** 963 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 964 */ 965 struct dmub_cmd_enable_disp_power_gating_data { 966 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 967 }; 968 969 /** 970 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 971 */ 972 struct dmub_rb_cmd_enable_disp_power_gating { 973 struct dmub_cmd_header header; /**< header */ 974 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 975 }; 976 977 /** 978 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 979 */ 980 struct dmub_dig_transmitter_control_data_v1_7 { 981 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 982 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 983 union { 984 uint8_t digmode; /**< enum atom_encode_mode_def */ 985 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 986 } mode_laneset; 987 uint8_t lanenum; /**< Number of lanes */ 988 union { 989 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 990 } symclk_units; 991 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 992 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 993 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 994 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 995 uint8_t reserved1; /**< For future use */ 996 uint8_t reserved2[3]; /**< For future use */ 997 uint32_t reserved3[11]; /**< For future use */ 998 }; 999 1000 /** 1001 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1002 */ 1003 union dmub_cmd_dig1_transmitter_control_data { 1004 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1005 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1006 }; 1007 1008 /** 1009 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1010 */ 1011 struct dmub_rb_cmd_dig1_transmitter_control { 1012 struct dmub_cmd_header header; /**< header */ 1013 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1014 }; 1015 1016 /** 1017 * DPIA tunnel command parameters. 1018 */ 1019 struct dmub_cmd_dig_dpia_control_data { 1020 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1021 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1022 union { 1023 uint8_t digmode; /** enum atom_encode_mode_def */ 1024 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1025 } mode_laneset; 1026 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1027 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1028 uint8_t hpdsel; /** =0: HPD is not assigned */ 1029 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1030 uint8_t dpia_id; /** Index of DPIA */ 1031 uint8_t fec_rdy : 1; 1032 uint8_t reserved : 7; 1033 uint32_t reserved1; 1034 }; 1035 1036 /** 1037 * DMUB command for DPIA tunnel control. 1038 */ 1039 struct dmub_rb_cmd_dig1_dpia_control { 1040 struct dmub_cmd_header header; 1041 struct dmub_cmd_dig_dpia_control_data dpia_control; 1042 }; 1043 1044 /** 1045 * SET_CONFIG Command Payload 1046 */ 1047 struct set_config_cmd_payload { 1048 uint8_t msg_type; /* set config message type */ 1049 uint8_t msg_data; /* set config message data */ 1050 }; 1051 1052 /** 1053 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1054 */ 1055 struct dmub_cmd_set_config_control_data { 1056 struct set_config_cmd_payload cmd_pkt; 1057 uint8_t instance; /* DPIA instance */ 1058 uint8_t immed_status; /* Immediate status returned in case of error */ 1059 }; 1060 1061 /** 1062 * DMUB command structure for SET_CONFIG command. 1063 */ 1064 struct dmub_rb_cmd_set_config_access { 1065 struct dmub_cmd_header header; /* header */ 1066 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1067 }; 1068 1069 /** 1070 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1071 */ 1072 struct dmub_rb_cmd_dpphy_init { 1073 struct dmub_cmd_header header; /**< header */ 1074 uint8_t reserved[60]; /**< reserved bits */ 1075 }; 1076 1077 /** 1078 * enum dp_aux_request_action - DP AUX request command listing. 1079 * 1080 * 4 AUX request command bits are shifted to high nibble. 1081 */ 1082 enum dp_aux_request_action { 1083 /** I2C-over-AUX write request */ 1084 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1085 /** I2C-over-AUX read request */ 1086 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1087 /** I2C-over-AUX write status request */ 1088 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1089 /** I2C-over-AUX write request with MOT=1 */ 1090 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1091 /** I2C-over-AUX read request with MOT=1 */ 1092 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1093 /** I2C-over-AUX write status request with MOT=1 */ 1094 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1095 /** Native AUX write request */ 1096 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1097 /** Native AUX read request */ 1098 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1099 }; 1100 1101 /** 1102 * enum aux_return_code_type - DP AUX process return code listing. 1103 */ 1104 enum aux_return_code_type { 1105 /** AUX process succeeded */ 1106 AUX_RET_SUCCESS = 0, 1107 /** AUX process failed with unknown reason */ 1108 AUX_RET_ERROR_UNKNOWN, 1109 /** AUX process completed with invalid reply */ 1110 AUX_RET_ERROR_INVALID_REPLY, 1111 /** AUX process timed out */ 1112 AUX_RET_ERROR_TIMEOUT, 1113 /** HPD was low during AUX process */ 1114 AUX_RET_ERROR_HPD_DISCON, 1115 /** Failed to acquire AUX engine */ 1116 AUX_RET_ERROR_ENGINE_ACQUIRE, 1117 /** AUX request not supported */ 1118 AUX_RET_ERROR_INVALID_OPERATION, 1119 /** AUX process not available */ 1120 AUX_RET_ERROR_PROTOCOL_ERROR, 1121 }; 1122 1123 /** 1124 * enum aux_channel_type - DP AUX channel type listing. 1125 */ 1126 enum aux_channel_type { 1127 /** AUX thru Legacy DP AUX */ 1128 AUX_CHANNEL_LEGACY_DDC, 1129 /** AUX thru DPIA DP tunneling */ 1130 AUX_CHANNEL_DPIA 1131 }; 1132 1133 /** 1134 * struct aux_transaction_parameters - DP AUX request transaction data 1135 */ 1136 struct aux_transaction_parameters { 1137 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1138 uint8_t action; /**< enum dp_aux_request_action */ 1139 uint8_t length; /**< DP AUX request data length */ 1140 uint8_t reserved; /**< For future use */ 1141 uint32_t address; /**< DP AUX address */ 1142 uint8_t data[16]; /**< DP AUX write data */ 1143 }; 1144 1145 /** 1146 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1147 */ 1148 struct dmub_cmd_dp_aux_control_data { 1149 uint8_t instance; /**< AUX instance or DPIA instance */ 1150 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1151 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1152 uint8_t reserved0; /**< For future use */ 1153 uint16_t timeout; /**< timeout time in us */ 1154 uint16_t reserved1; /**< For future use */ 1155 enum aux_channel_type type; /**< enum aux_channel_type */ 1156 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1157 }; 1158 1159 /** 1160 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1161 */ 1162 struct dmub_rb_cmd_dp_aux_access { 1163 /** 1164 * Command header. 1165 */ 1166 struct dmub_cmd_header header; 1167 /** 1168 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1169 */ 1170 struct dmub_cmd_dp_aux_control_data aux_control; 1171 }; 1172 1173 /** 1174 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1175 */ 1176 struct dmub_rb_cmd_outbox1_enable { 1177 /** 1178 * Command header. 1179 */ 1180 struct dmub_cmd_header header; 1181 /** 1182 * enable: 0x0 -> disable outbox1 notification (default value) 1183 * 0x1 -> enable outbox1 notification 1184 */ 1185 uint32_t enable; 1186 }; 1187 1188 /* DP AUX Reply command - OutBox Cmd */ 1189 /** 1190 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1191 */ 1192 struct aux_reply_data { 1193 /** 1194 * Aux cmd 1195 */ 1196 uint8_t command; 1197 /** 1198 * Aux reply data length (max: 16 bytes) 1199 */ 1200 uint8_t length; 1201 /** 1202 * Alignment only 1203 */ 1204 uint8_t pad[2]; 1205 /** 1206 * Aux reply data 1207 */ 1208 uint8_t data[16]; 1209 }; 1210 1211 /** 1212 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1213 */ 1214 struct aux_reply_control_data { 1215 /** 1216 * Reserved for future use 1217 */ 1218 uint32_t handle; 1219 /** 1220 * Aux Instance 1221 */ 1222 uint8_t instance; 1223 /** 1224 * Aux transaction result: definition in enum aux_return_code_type 1225 */ 1226 uint8_t result; 1227 /** 1228 * Alignment only 1229 */ 1230 uint16_t pad; 1231 }; 1232 1233 /** 1234 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1235 */ 1236 struct dmub_rb_cmd_dp_aux_reply { 1237 /** 1238 * Command header. 1239 */ 1240 struct dmub_cmd_header header; 1241 /** 1242 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1243 */ 1244 struct aux_reply_control_data control; 1245 /** 1246 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1247 */ 1248 struct aux_reply_data reply_data; 1249 }; 1250 1251 /* DP HPD Notify command - OutBox Cmd */ 1252 /** 1253 * DP HPD Type 1254 */ 1255 enum dp_hpd_type { 1256 /** 1257 * Normal DP HPD 1258 */ 1259 DP_HPD = 0, 1260 /** 1261 * DP HPD short pulse 1262 */ 1263 DP_IRQ 1264 }; 1265 1266 /** 1267 * DP HPD Status 1268 */ 1269 enum dp_hpd_status { 1270 /** 1271 * DP_HPD status low 1272 */ 1273 DP_HPD_UNPLUG = 0, 1274 /** 1275 * DP_HPD status high 1276 */ 1277 DP_HPD_PLUG 1278 }; 1279 1280 /** 1281 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1282 */ 1283 struct dp_hpd_data { 1284 /** 1285 * DP HPD instance 1286 */ 1287 uint8_t instance; 1288 /** 1289 * HPD type 1290 */ 1291 uint8_t hpd_type; 1292 /** 1293 * HPD status: only for type: DP_HPD to indicate status 1294 */ 1295 uint8_t hpd_status; 1296 /** 1297 * Alignment only 1298 */ 1299 uint8_t pad; 1300 }; 1301 1302 /** 1303 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1304 */ 1305 struct dmub_rb_cmd_dp_hpd_notify { 1306 /** 1307 * Command header. 1308 */ 1309 struct dmub_cmd_header header; 1310 /** 1311 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1312 */ 1313 struct dp_hpd_data hpd_data; 1314 }; 1315 1316 /** 1317 * Definition of a SET_CONFIG reply from DPOA. 1318 */ 1319 enum set_config_status { 1320 SET_CONFIG_PENDING = 0, 1321 SET_CONFIG_ACK_RECEIVED, 1322 SET_CONFIG_RX_TIMEOUT, 1323 SET_CONFIG_UNKNOWN_ERROR, 1324 }; 1325 1326 /** 1327 * Definition of a set_config reply 1328 */ 1329 struct set_config_reply_control_data { 1330 uint8_t instance; /* DPIA Instance */ 1331 uint8_t status; /* Set Config reply */ 1332 uint16_t pad; /* Alignment */ 1333 }; 1334 1335 /** 1336 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1337 */ 1338 struct dmub_rb_cmd_dp_set_config_reply { 1339 struct dmub_cmd_header header; 1340 struct set_config_reply_control_data set_config_reply_control; 1341 }; 1342 1343 /* 1344 * Command IDs should be treated as stable ABI. 1345 * Do not reuse or modify IDs. 1346 */ 1347 1348 /** 1349 * PSR command sub-types. 1350 */ 1351 enum dmub_cmd_psr_type { 1352 /** 1353 * Set PSR version support. 1354 */ 1355 DMUB_CMD__PSR_SET_VERSION = 0, 1356 /** 1357 * Copy driver-calculated parameters to PSR state. 1358 */ 1359 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1360 /** 1361 * Enable PSR. 1362 */ 1363 DMUB_CMD__PSR_ENABLE = 2, 1364 1365 /** 1366 * Disable PSR. 1367 */ 1368 DMUB_CMD__PSR_DISABLE = 3, 1369 1370 /** 1371 * Set PSR level. 1372 * PSR level is a 16-bit value dicated by driver that 1373 * will enable/disable different functionality. 1374 */ 1375 DMUB_CMD__PSR_SET_LEVEL = 4, 1376 1377 /** 1378 * Forces PSR enabled until an explicit PSR disable call. 1379 */ 1380 DMUB_CMD__PSR_FORCE_STATIC = 5, 1381 }; 1382 1383 /** 1384 * PSR versions. 1385 */ 1386 enum psr_version { 1387 /** 1388 * PSR version 1. 1389 */ 1390 PSR_VERSION_1 = 0, 1391 /** 1392 * PSR not supported. 1393 */ 1394 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1395 }; 1396 1397 /** 1398 * enum dmub_cmd_mall_type - MALL commands 1399 */ 1400 enum dmub_cmd_mall_type { 1401 /** 1402 * Allows display refresh from MALL. 1403 */ 1404 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1405 /** 1406 * Disallows display refresh from MALL. 1407 */ 1408 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1409 /** 1410 * Cursor copy for MALL. 1411 */ 1412 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1413 /** 1414 * Controls DF requests. 1415 */ 1416 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1417 }; 1418 1419 1420 /** 1421 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1422 */ 1423 struct dmub_cmd_psr_copy_settings_data { 1424 /** 1425 * Flags that can be set by driver to change some PSR behaviour. 1426 */ 1427 union dmub_psr_debug_flags debug; 1428 /** 1429 * 16-bit value dicated by driver that will enable/disable different functionality. 1430 */ 1431 uint16_t psr_level; 1432 /** 1433 * DPP HW instance. 1434 */ 1435 uint8_t dpp_inst; 1436 /** 1437 * MPCC HW instance. 1438 * Not used in dmub fw, 1439 * dmub fw will get active opp by reading odm registers. 1440 */ 1441 uint8_t mpcc_inst; 1442 /** 1443 * OPP HW instance. 1444 * Not used in dmub fw, 1445 * dmub fw will get active opp by reading odm registers. 1446 */ 1447 uint8_t opp_inst; 1448 /** 1449 * OTG HW instance. 1450 */ 1451 uint8_t otg_inst; 1452 /** 1453 * DIG FE HW instance. 1454 */ 1455 uint8_t digfe_inst; 1456 /** 1457 * DIG BE HW instance. 1458 */ 1459 uint8_t digbe_inst; 1460 /** 1461 * DP PHY HW instance. 1462 */ 1463 uint8_t dpphy_inst; 1464 /** 1465 * AUX HW instance. 1466 */ 1467 uint8_t aux_inst; 1468 /** 1469 * Determines if SMU optimzations are enabled/disabled. 1470 */ 1471 uint8_t smu_optimizations_en; 1472 /** 1473 * Unused. 1474 * TODO: Remove. 1475 */ 1476 uint8_t frame_delay; 1477 /** 1478 * If RFB setup time is greater than the total VBLANK time, 1479 * it is not possible for the sink to capture the video frame 1480 * in the same frame the SDP is sent. In this case, 1481 * the frame capture indication bit should be set and an extra 1482 * static frame should be transmitted to the sink. 1483 */ 1484 uint8_t frame_cap_ind; 1485 /** 1486 * Explicit padding to 4 byte boundary. 1487 */ 1488 uint8_t pad[2]; 1489 /** 1490 * Multi-display optimizations are implemented on certain ASICs. 1491 */ 1492 uint8_t multi_disp_optimizations_en; 1493 /** 1494 * The last possible line SDP may be transmitted without violating 1495 * the RFB setup time or entering the active video frame. 1496 */ 1497 uint16_t init_sdp_deadline; 1498 /** 1499 * Explicit padding to 4 byte boundary. 1500 */ 1501 uint16_t pad2; 1502 /** 1503 * Length of each horizontal line in us. 1504 */ 1505 uint32_t line_time_in_us; 1506 /** 1507 * FEC enable status in driver 1508 */ 1509 uint8_t fec_enable_status; 1510 /** 1511 * FEC re-enable delay when PSR exit. 1512 * unit is 100us, range form 0~255(0xFF). 1513 */ 1514 uint8_t fec_enable_delay_in100us; 1515 /** 1516 * PSR control version. 1517 */ 1518 uint8_t cmd_version; 1519 /** 1520 * Panel Instance. 1521 * Panel isntance to identify which psr_state to use 1522 * Currently the support is only for 0 or 1 1523 */ 1524 uint8_t panel_inst; 1525 /** 1526 * Explicit padding to 4 byte boundary. 1527 */ 1528 uint8_t pad3[4]; 1529 }; 1530 1531 /** 1532 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1533 */ 1534 struct dmub_rb_cmd_psr_copy_settings { 1535 /** 1536 * Command header. 1537 */ 1538 struct dmub_cmd_header header; 1539 /** 1540 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1541 */ 1542 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1543 }; 1544 1545 /** 1546 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1547 */ 1548 struct dmub_cmd_psr_set_level_data { 1549 /** 1550 * 16-bit value dicated by driver that will enable/disable different functionality. 1551 */ 1552 uint16_t psr_level; 1553 /** 1554 * PSR control version. 1555 */ 1556 uint8_t cmd_version; 1557 /** 1558 * Panel Instance. 1559 * Panel isntance to identify which psr_state to use 1560 * Currently the support is only for 0 or 1 1561 */ 1562 uint8_t panel_inst; 1563 }; 1564 1565 /** 1566 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1567 */ 1568 struct dmub_rb_cmd_psr_set_level { 1569 /** 1570 * Command header. 1571 */ 1572 struct dmub_cmd_header header; 1573 /** 1574 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1575 */ 1576 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1577 }; 1578 1579 struct dmub_rb_cmd_psr_enable_data { 1580 /** 1581 * PSR control version. 1582 */ 1583 uint8_t cmd_version; 1584 /** 1585 * Panel Instance. 1586 * Panel isntance to identify which psr_state to use 1587 * Currently the support is only for 0 or 1 1588 */ 1589 uint8_t panel_inst; 1590 /** 1591 * Explicit padding to 4 byte boundary. 1592 */ 1593 uint8_t pad[2]; 1594 }; 1595 1596 /** 1597 * Definition of a DMUB_CMD__PSR_ENABLE command. 1598 * PSR enable/disable is controlled using the sub_type. 1599 */ 1600 struct dmub_rb_cmd_psr_enable { 1601 /** 1602 * Command header. 1603 */ 1604 struct dmub_cmd_header header; 1605 1606 struct dmub_rb_cmd_psr_enable_data data; 1607 }; 1608 1609 /** 1610 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1611 */ 1612 struct dmub_cmd_psr_set_version_data { 1613 /** 1614 * PSR version that FW should implement. 1615 */ 1616 enum psr_version version; 1617 /** 1618 * PSR control version. 1619 */ 1620 uint8_t cmd_version; 1621 /** 1622 * Panel Instance. 1623 * Panel isntance to identify which psr_state to use 1624 * Currently the support is only for 0 or 1 1625 */ 1626 uint8_t panel_inst; 1627 /** 1628 * Explicit padding to 4 byte boundary. 1629 */ 1630 uint8_t pad[2]; 1631 }; 1632 1633 /** 1634 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1635 */ 1636 struct dmub_rb_cmd_psr_set_version { 1637 /** 1638 * Command header. 1639 */ 1640 struct dmub_cmd_header header; 1641 /** 1642 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1643 */ 1644 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1645 }; 1646 1647 struct dmub_cmd_psr_force_static_data { 1648 /** 1649 * PSR control version. 1650 */ 1651 uint8_t cmd_version; 1652 /** 1653 * Panel Instance. 1654 * Panel isntance to identify which psr_state to use 1655 * Currently the support is only for 0 or 1 1656 */ 1657 uint8_t panel_inst; 1658 /** 1659 * Explicit padding to 4 byte boundary. 1660 */ 1661 uint8_t pad[2]; 1662 }; 1663 1664 /** 1665 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1666 */ 1667 struct dmub_rb_cmd_psr_force_static { 1668 /** 1669 * Command header. 1670 */ 1671 struct dmub_cmd_header header; 1672 /** 1673 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1674 */ 1675 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1676 }; 1677 1678 /** 1679 * Set of HW components that can be locked. 1680 * 1681 * Note: If updating with more HW components, fields 1682 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1683 */ 1684 union dmub_hw_lock_flags { 1685 /** 1686 * Set of HW components that can be locked. 1687 */ 1688 struct { 1689 /** 1690 * Lock/unlock OTG master update lock. 1691 */ 1692 uint8_t lock_pipe : 1; 1693 /** 1694 * Lock/unlock cursor. 1695 */ 1696 uint8_t lock_cursor : 1; 1697 /** 1698 * Lock/unlock global update lock. 1699 */ 1700 uint8_t lock_dig : 1; 1701 /** 1702 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1703 */ 1704 uint8_t triple_buffer_lock : 1; 1705 } bits; 1706 1707 /** 1708 * Union for HW Lock flags. 1709 */ 1710 uint8_t u8All; 1711 }; 1712 1713 /** 1714 * Instances of HW to be locked. 1715 * 1716 * Note: If updating with more HW components, fields 1717 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1718 */ 1719 struct dmub_hw_lock_inst_flags { 1720 /** 1721 * OTG HW instance for OTG master update lock. 1722 */ 1723 uint8_t otg_inst; 1724 /** 1725 * OPP instance for cursor lock. 1726 */ 1727 uint8_t opp_inst; 1728 /** 1729 * OTG HW instance for global update lock. 1730 * TODO: Remove, and re-use otg_inst. 1731 */ 1732 uint8_t dig_inst; 1733 /** 1734 * Explicit pad to 4 byte boundary. 1735 */ 1736 uint8_t pad; 1737 }; 1738 1739 /** 1740 * Clients that can acquire the HW Lock Manager. 1741 * 1742 * Note: If updating with more clients, fields in 1743 * dmub_inbox0_cmd_lock_hw must be updated to match. 1744 */ 1745 enum hw_lock_client { 1746 /** 1747 * Driver is the client of HW Lock Manager. 1748 */ 1749 HW_LOCK_CLIENT_DRIVER = 0, 1750 /** 1751 * Invalid client. 1752 */ 1753 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1754 }; 1755 1756 /** 1757 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1758 */ 1759 struct dmub_cmd_lock_hw_data { 1760 /** 1761 * Specifies the client accessing HW Lock Manager. 1762 */ 1763 enum hw_lock_client client; 1764 /** 1765 * HW instances to be locked. 1766 */ 1767 struct dmub_hw_lock_inst_flags inst_flags; 1768 /** 1769 * Which components to be locked. 1770 */ 1771 union dmub_hw_lock_flags hw_locks; 1772 /** 1773 * Specifies lock/unlock. 1774 */ 1775 uint8_t lock; 1776 /** 1777 * HW can be unlocked separately from releasing the HW Lock Mgr. 1778 * This flag is set if the client wishes to release the object. 1779 */ 1780 uint8_t should_release; 1781 /** 1782 * Explicit padding to 4 byte boundary. 1783 */ 1784 uint8_t pad; 1785 }; 1786 1787 /** 1788 * Definition of a DMUB_CMD__HW_LOCK command. 1789 * Command is used by driver and FW. 1790 */ 1791 struct dmub_rb_cmd_lock_hw { 1792 /** 1793 * Command header. 1794 */ 1795 struct dmub_cmd_header header; 1796 /** 1797 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1798 */ 1799 struct dmub_cmd_lock_hw_data lock_hw_data; 1800 }; 1801 1802 /** 1803 * ABM command sub-types. 1804 */ 1805 enum dmub_cmd_abm_type { 1806 /** 1807 * Initialize parameters for ABM algorithm. 1808 * Data is passed through an indirect buffer. 1809 */ 1810 DMUB_CMD__ABM_INIT_CONFIG = 0, 1811 /** 1812 * Set OTG and panel HW instance. 1813 */ 1814 DMUB_CMD__ABM_SET_PIPE = 1, 1815 /** 1816 * Set user requested backklight level. 1817 */ 1818 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1819 /** 1820 * Set ABM operating/aggression level. 1821 */ 1822 DMUB_CMD__ABM_SET_LEVEL = 3, 1823 /** 1824 * Set ambient light level. 1825 */ 1826 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1827 /** 1828 * Enable/disable fractional duty cycle for backlight PWM. 1829 */ 1830 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1831 1832 /** 1833 * unregister vertical interrupt after steady state is reached 1834 */ 1835 DMUB_CMD__ABM_PAUSE = 6, 1836 }; 1837 1838 /** 1839 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1840 * Requirements: 1841 * - Padded explicitly to 32-bit boundary. 1842 * - Must ensure this structure matches the one on driver-side, 1843 * otherwise it won't be aligned. 1844 */ 1845 struct abm_config_table { 1846 /** 1847 * Gamma curve thresholds, used for crgb conversion. 1848 */ 1849 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1850 /** 1851 * Gamma curve offsets, used for crgb conversion. 1852 */ 1853 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1854 /** 1855 * Gamma curve slopes, used for crgb conversion. 1856 */ 1857 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1858 /** 1859 * Custom backlight curve thresholds. 1860 */ 1861 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 1862 /** 1863 * Custom backlight curve offsets. 1864 */ 1865 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 1866 /** 1867 * Ambient light thresholds. 1868 */ 1869 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 1870 /** 1871 * Minimum programmable backlight. 1872 */ 1873 uint16_t min_abm_backlight; // 122B 1874 /** 1875 * Minimum reduction values. 1876 */ 1877 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 1878 /** 1879 * Maximum reduction values. 1880 */ 1881 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 1882 /** 1883 * Bright positive gain. 1884 */ 1885 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 1886 /** 1887 * Dark negative gain. 1888 */ 1889 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 1890 /** 1891 * Hybrid factor. 1892 */ 1893 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 1894 /** 1895 * Contrast factor. 1896 */ 1897 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 1898 /** 1899 * Deviation gain. 1900 */ 1901 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 1902 /** 1903 * Minimum knee. 1904 */ 1905 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 1906 /** 1907 * Maximum knee. 1908 */ 1909 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 1910 /** 1911 * Unused. 1912 */ 1913 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 1914 /** 1915 * Explicit padding to 4 byte boundary. 1916 */ 1917 uint8_t pad3[3]; // 229B 1918 /** 1919 * Backlight ramp reduction. 1920 */ 1921 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 1922 /** 1923 * Backlight ramp start. 1924 */ 1925 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 1926 }; 1927 1928 /** 1929 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1930 */ 1931 struct dmub_cmd_abm_set_pipe_data { 1932 /** 1933 * OTG HW instance. 1934 */ 1935 uint8_t otg_inst; 1936 1937 /** 1938 * Panel Control HW instance. 1939 */ 1940 uint8_t panel_inst; 1941 1942 /** 1943 * Controls how ABM will interpret a set pipe or set level command. 1944 */ 1945 uint8_t set_pipe_option; 1946 1947 /** 1948 * Unused. 1949 * TODO: Remove. 1950 */ 1951 uint8_t ramping_boundary; 1952 }; 1953 1954 /** 1955 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1956 */ 1957 struct dmub_rb_cmd_abm_set_pipe { 1958 /** 1959 * Command header. 1960 */ 1961 struct dmub_cmd_header header; 1962 1963 /** 1964 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1965 */ 1966 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 1967 }; 1968 1969 /** 1970 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1971 */ 1972 struct dmub_cmd_abm_set_backlight_data { 1973 /** 1974 * Number of frames to ramp to backlight user level. 1975 */ 1976 uint32_t frame_ramp; 1977 1978 /** 1979 * Requested backlight level from user. 1980 */ 1981 uint32_t backlight_user_level; 1982 1983 /** 1984 * ABM control version. 1985 */ 1986 uint8_t version; 1987 1988 /** 1989 * Panel Control HW instance mask. 1990 * Bit 0 is Panel Control HW instance 0. 1991 * Bit 1 is Panel Control HW instance 1. 1992 */ 1993 uint8_t panel_mask; 1994 1995 /** 1996 * Explicit padding to 4 byte boundary. 1997 */ 1998 uint8_t pad[2]; 1999 }; 2000 2001 /** 2002 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2003 */ 2004 struct dmub_rb_cmd_abm_set_backlight { 2005 /** 2006 * Command header. 2007 */ 2008 struct dmub_cmd_header header; 2009 2010 /** 2011 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2012 */ 2013 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2014 }; 2015 2016 /** 2017 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2018 */ 2019 struct dmub_cmd_abm_set_level_data { 2020 /** 2021 * Set current ABM operating/aggression level. 2022 */ 2023 uint32_t level; 2024 2025 /** 2026 * ABM control version. 2027 */ 2028 uint8_t version; 2029 2030 /** 2031 * Panel Control HW instance mask. 2032 * Bit 0 is Panel Control HW instance 0. 2033 * Bit 1 is Panel Control HW instance 1. 2034 */ 2035 uint8_t panel_mask; 2036 2037 /** 2038 * Explicit padding to 4 byte boundary. 2039 */ 2040 uint8_t pad[2]; 2041 }; 2042 2043 /** 2044 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2045 */ 2046 struct dmub_rb_cmd_abm_set_level { 2047 /** 2048 * Command header. 2049 */ 2050 struct dmub_cmd_header header; 2051 2052 /** 2053 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2054 */ 2055 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2056 }; 2057 2058 /** 2059 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2060 */ 2061 struct dmub_cmd_abm_set_ambient_level_data { 2062 /** 2063 * Ambient light sensor reading from OS. 2064 */ 2065 uint32_t ambient_lux; 2066 2067 /** 2068 * ABM control version. 2069 */ 2070 uint8_t version; 2071 2072 /** 2073 * Panel Control HW instance mask. 2074 * Bit 0 is Panel Control HW instance 0. 2075 * Bit 1 is Panel Control HW instance 1. 2076 */ 2077 uint8_t panel_mask; 2078 2079 /** 2080 * Explicit padding to 4 byte boundary. 2081 */ 2082 uint8_t pad[2]; 2083 }; 2084 2085 /** 2086 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2087 */ 2088 struct dmub_rb_cmd_abm_set_ambient_level { 2089 /** 2090 * Command header. 2091 */ 2092 struct dmub_cmd_header header; 2093 2094 /** 2095 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2096 */ 2097 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2098 }; 2099 2100 /** 2101 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2102 */ 2103 struct dmub_cmd_abm_set_pwm_frac_data { 2104 /** 2105 * Enable/disable fractional duty cycle for backlight PWM. 2106 * TODO: Convert to uint8_t. 2107 */ 2108 uint32_t fractional_pwm; 2109 2110 /** 2111 * ABM control version. 2112 */ 2113 uint8_t version; 2114 2115 /** 2116 * Panel Control HW instance mask. 2117 * Bit 0 is Panel Control HW instance 0. 2118 * Bit 1 is Panel Control HW instance 1. 2119 */ 2120 uint8_t panel_mask; 2121 2122 /** 2123 * Explicit padding to 4 byte boundary. 2124 */ 2125 uint8_t pad[2]; 2126 }; 2127 2128 /** 2129 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2130 */ 2131 struct dmub_rb_cmd_abm_set_pwm_frac { 2132 /** 2133 * Command header. 2134 */ 2135 struct dmub_cmd_header header; 2136 2137 /** 2138 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2139 */ 2140 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2141 }; 2142 2143 /** 2144 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2145 */ 2146 struct dmub_cmd_abm_init_config_data { 2147 /** 2148 * Location of indirect buffer used to pass init data to ABM. 2149 */ 2150 union dmub_addr src; 2151 2152 /** 2153 * Indirect buffer length. 2154 */ 2155 uint16_t bytes; 2156 2157 2158 /** 2159 * ABM control version. 2160 */ 2161 uint8_t version; 2162 2163 /** 2164 * Panel Control HW instance mask. 2165 * Bit 0 is Panel Control HW instance 0. 2166 * Bit 1 is Panel Control HW instance 1. 2167 */ 2168 uint8_t panel_mask; 2169 2170 /** 2171 * Explicit padding to 4 byte boundary. 2172 */ 2173 uint8_t pad[2]; 2174 }; 2175 2176 /** 2177 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2178 */ 2179 struct dmub_rb_cmd_abm_init_config { 2180 /** 2181 * Command header. 2182 */ 2183 struct dmub_cmd_header header; 2184 2185 /** 2186 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2187 */ 2188 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2189 }; 2190 2191 /** 2192 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2193 */ 2194 2195 struct dmub_cmd_abm_pause_data { 2196 2197 /** 2198 * Panel Control HW instance mask. 2199 * Bit 0 is Panel Control HW instance 0. 2200 * Bit 1 is Panel Control HW instance 1. 2201 */ 2202 uint8_t panel_mask; 2203 2204 /** 2205 * OTG hw instance 2206 */ 2207 uint8_t otg_inst; 2208 2209 /** 2210 * Enable or disable ABM pause 2211 */ 2212 uint8_t enable; 2213 2214 /** 2215 * Explicit padding to 4 byte boundary. 2216 */ 2217 uint8_t pad[1]; 2218 }; 2219 2220 /** 2221 * Definition of a DMUB_CMD__ABM_PAUSE command. 2222 */ 2223 struct dmub_rb_cmd_abm_pause { 2224 /** 2225 * Command header. 2226 */ 2227 struct dmub_cmd_header header; 2228 2229 /** 2230 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2231 */ 2232 struct dmub_cmd_abm_pause_data abm_pause_data; 2233 }; 2234 2235 /** 2236 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2237 */ 2238 struct dmub_cmd_query_feature_caps_data { 2239 /** 2240 * DMUB feature capabilities. 2241 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2242 */ 2243 struct dmub_feature_caps feature_caps; 2244 }; 2245 2246 /** 2247 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2248 */ 2249 struct dmub_rb_cmd_query_feature_caps { 2250 /** 2251 * Command header. 2252 */ 2253 struct dmub_cmd_header header; 2254 /** 2255 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2256 */ 2257 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2258 }; 2259 2260 struct dmub_optc_state { 2261 uint32_t v_total_max; 2262 uint32_t v_total_min; 2263 uint32_t v_total_mid; 2264 uint32_t v_total_mid_frame_num; 2265 uint32_t tg_inst; 2266 uint32_t enable_manual_trigger; 2267 uint32_t clear_force_vsync; 2268 }; 2269 2270 struct dmub_rb_cmd_drr_update { 2271 struct dmub_cmd_header header; 2272 struct dmub_optc_state dmub_optc_state_req; 2273 }; 2274 2275 /** 2276 * enum dmub_cmd_panel_cntl_type - Panel control command. 2277 */ 2278 enum dmub_cmd_panel_cntl_type { 2279 /** 2280 * Initializes embedded panel hardware blocks. 2281 */ 2282 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2283 /** 2284 * Queries backlight info for the embedded panel. 2285 */ 2286 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2287 }; 2288 2289 /** 2290 * struct dmub_cmd_panel_cntl_data - Panel control data. 2291 */ 2292 struct dmub_cmd_panel_cntl_data { 2293 uint32_t inst; /**< panel instance */ 2294 uint32_t current_backlight; /* in/out */ 2295 uint32_t bl_pwm_cntl; /* in/out */ 2296 uint32_t bl_pwm_period_cntl; /* in/out */ 2297 uint32_t bl_pwm_ref_div1; /* in/out */ 2298 uint8_t is_backlight_on : 1; /* in/out */ 2299 uint8_t is_powered_on : 1; /* in/out */ 2300 }; 2301 2302 /** 2303 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2304 */ 2305 struct dmub_rb_cmd_panel_cntl { 2306 struct dmub_cmd_header header; /**< header */ 2307 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2308 }; 2309 2310 /** 2311 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2312 */ 2313 struct dmub_cmd_lvtma_control_data { 2314 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2315 uint8_t reserved_0[3]; /**< For future use */ 2316 uint8_t panel_inst; /**< LVTMA control instance */ 2317 uint8_t reserved_1[3]; /**< For future use */ 2318 }; 2319 2320 /** 2321 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2322 */ 2323 struct dmub_rb_cmd_lvtma_control { 2324 /** 2325 * Command header. 2326 */ 2327 struct dmub_cmd_header header; 2328 /** 2329 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2330 */ 2331 struct dmub_cmd_lvtma_control_data data; 2332 }; 2333 2334 /** 2335 * Maximum number of bytes a chunk sent to DMUB for parsing 2336 */ 2337 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2338 2339 /** 2340 * Represent a chunk of CEA blocks sent to DMUB for parsing 2341 */ 2342 struct dmub_cmd_send_edid_cea { 2343 uint16_t offset; /**< offset into the CEA block */ 2344 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2345 uint16_t total_length; /**< total length of the CEA block */ 2346 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2347 uint8_t pad[3]; /**< padding and for future expansion */ 2348 }; 2349 2350 /** 2351 * Result of VSDB parsing from CEA block 2352 */ 2353 struct dmub_cmd_edid_cea_amd_vsdb { 2354 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2355 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2356 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2357 uint16_t min_frame_rate; /**< Maximum frame rate */ 2358 uint16_t max_frame_rate; /**< Minimum frame rate */ 2359 }; 2360 2361 /** 2362 * Result of sending a CEA chunk 2363 */ 2364 struct dmub_cmd_edid_cea_ack { 2365 uint16_t offset; /**< offset of the chunk into the CEA block */ 2366 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2367 uint8_t pad; /**< padding and for future expansion */ 2368 }; 2369 2370 /** 2371 * Specify whether the result is an ACK/NACK or the parsing has finished 2372 */ 2373 enum dmub_cmd_edid_cea_reply_type { 2374 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2375 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2376 }; 2377 2378 /** 2379 * Definition of a DMUB_CMD__EDID_CEA command. 2380 */ 2381 struct dmub_rb_cmd_edid_cea { 2382 struct dmub_cmd_header header; /**< Command header */ 2383 union dmub_cmd_edid_cea_data { 2384 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2385 struct dmub_cmd_edid_cea_output { /**< output with results */ 2386 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2387 union { 2388 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2389 struct dmub_cmd_edid_cea_ack ack; 2390 }; 2391 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2392 } data; /**< Command data */ 2393 2394 }; 2395 2396 /** 2397 * union dmub_rb_cmd - DMUB inbox command. 2398 */ 2399 union dmub_rb_cmd { 2400 struct dmub_rb_cmd_lock_hw lock_hw; 2401 /** 2402 * Elements shared with all commands. 2403 */ 2404 struct dmub_rb_cmd_common cmd_common; 2405 /** 2406 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2407 */ 2408 struct dmub_rb_cmd_read_modify_write read_modify_write; 2409 /** 2410 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2411 */ 2412 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2413 /** 2414 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2415 */ 2416 struct dmub_rb_cmd_burst_write burst_write; 2417 /** 2418 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2419 */ 2420 struct dmub_rb_cmd_reg_wait reg_wait; 2421 /** 2422 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2423 */ 2424 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2425 /** 2426 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2427 */ 2428 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2429 /** 2430 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2431 */ 2432 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2433 /** 2434 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2435 */ 2436 struct dmub_rb_cmd_dpphy_init dpphy_init; 2437 /** 2438 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2439 */ 2440 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2441 /** 2442 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2443 */ 2444 struct dmub_rb_cmd_psr_set_version psr_set_version; 2445 /** 2446 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2447 */ 2448 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2449 /** 2450 * Definition of a DMUB_CMD__PSR_ENABLE command. 2451 */ 2452 struct dmub_rb_cmd_psr_enable psr_enable; 2453 /** 2454 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2455 */ 2456 struct dmub_rb_cmd_psr_set_level psr_set_level; 2457 /** 2458 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2459 */ 2460 struct dmub_rb_cmd_psr_force_static psr_force_static; 2461 /** 2462 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2463 */ 2464 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2465 /** 2466 * Definition of a DMUB_CMD__MALL command. 2467 */ 2468 struct dmub_rb_cmd_mall mall; 2469 /** 2470 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2471 */ 2472 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2473 2474 /** 2475 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2476 */ 2477 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2478 2479 /** 2480 * Definition of DMUB_CMD__PANEL_CNTL commands. 2481 */ 2482 struct dmub_rb_cmd_panel_cntl panel_cntl; 2483 /** 2484 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2485 */ 2486 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2487 2488 /** 2489 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2490 */ 2491 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2492 2493 /** 2494 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2495 */ 2496 struct dmub_rb_cmd_abm_set_level abm_set_level; 2497 2498 /** 2499 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2500 */ 2501 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2502 2503 /** 2504 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2505 */ 2506 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2507 2508 /** 2509 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2510 */ 2511 struct dmub_rb_cmd_abm_init_config abm_init_config; 2512 2513 /** 2514 * Definition of a DMUB_CMD__ABM_PAUSE command. 2515 */ 2516 struct dmub_rb_cmd_abm_pause abm_pause; 2517 2518 /** 2519 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2520 */ 2521 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2522 2523 /** 2524 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2525 */ 2526 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2527 2528 /** 2529 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2530 */ 2531 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2532 struct dmub_rb_cmd_drr_update drr_update; 2533 /** 2534 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2535 */ 2536 struct dmub_rb_cmd_lvtma_control lvtma_control; 2537 /** 2538 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 2539 */ 2540 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 2541 /** 2542 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 2543 */ 2544 struct dmub_rb_cmd_set_config_access set_config_access; 2545 /** 2546 * Definition of a DMUB_CMD__EDID_CEA command. 2547 */ 2548 struct dmub_rb_cmd_edid_cea edid_cea; 2549 }; 2550 2551 /** 2552 * union dmub_rb_out_cmd - Outbox command 2553 */ 2554 union dmub_rb_out_cmd { 2555 /** 2556 * Parameters common to every command. 2557 */ 2558 struct dmub_rb_cmd_common cmd_common; 2559 /** 2560 * AUX reply command. 2561 */ 2562 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2563 /** 2564 * HPD notify command. 2565 */ 2566 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2567 /** 2568 * SET_CONFIG reply command. 2569 */ 2570 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 2571 }; 2572 #pragma pack(pop) 2573 2574 2575 //============================================================================== 2576 //</DMUB_CMD>=================================================================== 2577 //============================================================================== 2578 //< DMUB_RB>==================================================================== 2579 //============================================================================== 2580 2581 #if defined(__cplusplus) 2582 extern "C" { 2583 #endif 2584 2585 /** 2586 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2587 */ 2588 struct dmub_rb_init_params { 2589 void *ctx; /**< Caller provided context pointer */ 2590 void *base_address; /**< CPU base address for ring's data */ 2591 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2592 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2593 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2594 }; 2595 2596 /** 2597 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2598 */ 2599 struct dmub_rb { 2600 void *base_address; /**< CPU address for the ring's data */ 2601 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2602 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2603 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2604 2605 void *ctx; /**< Caller provided context pointer */ 2606 void *dmub; /**< Pointer to the DMUB interface */ 2607 }; 2608 2609 /** 2610 * @brief Checks if the ringbuffer is empty. 2611 * 2612 * @param rb DMUB Ringbuffer 2613 * @return true if empty 2614 * @return false otherwise 2615 */ 2616 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2617 { 2618 return (rb->wrpt == rb->rptr); 2619 } 2620 2621 /** 2622 * @brief Checks if the ringbuffer is full 2623 * 2624 * @param rb DMUB Ringbuffer 2625 * @return true if full 2626 * @return false otherwise 2627 */ 2628 static inline bool dmub_rb_full(struct dmub_rb *rb) 2629 { 2630 uint32_t data_count; 2631 2632 if (rb->wrpt >= rb->rptr) 2633 data_count = rb->wrpt - rb->rptr; 2634 else 2635 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2636 2637 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2638 } 2639 2640 /** 2641 * @brief Pushes a command into the ringbuffer 2642 * 2643 * @param rb DMUB ringbuffer 2644 * @param cmd The command to push 2645 * @return true if the ringbuffer was not full 2646 * @return false otherwise 2647 */ 2648 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2649 const union dmub_rb_cmd *cmd) 2650 { 2651 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 2652 const uint64_t *src = (const uint64_t *)cmd; 2653 uint8_t i; 2654 2655 if (dmub_rb_full(rb)) 2656 return false; 2657 2658 // copying data 2659 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2660 *dst++ = *src++; 2661 2662 rb->wrpt += DMUB_RB_CMD_SIZE; 2663 2664 if (rb->wrpt >= rb->capacity) 2665 rb->wrpt %= rb->capacity; 2666 2667 return true; 2668 } 2669 2670 /** 2671 * @brief Pushes a command into the DMUB outbox ringbuffer 2672 * 2673 * @param rb DMUB outbox ringbuffer 2674 * @param cmd Outbox command 2675 * @return true if not full 2676 * @return false otherwise 2677 */ 2678 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2679 const union dmub_rb_out_cmd *cmd) 2680 { 2681 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2682 const uint8_t *src = (const uint8_t *)cmd; 2683 2684 if (dmub_rb_full(rb)) 2685 return false; 2686 2687 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2688 2689 rb->wrpt += DMUB_RB_CMD_SIZE; 2690 2691 if (rb->wrpt >= rb->capacity) 2692 rb->wrpt %= rb->capacity; 2693 2694 return true; 2695 } 2696 2697 /** 2698 * @brief Returns the next unprocessed command in the ringbuffer. 2699 * 2700 * @param rb DMUB ringbuffer 2701 * @param cmd The command to return 2702 * @return true if not empty 2703 * @return false otherwise 2704 */ 2705 static inline bool dmub_rb_front(struct dmub_rb *rb, 2706 union dmub_rb_cmd **cmd) 2707 { 2708 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2709 2710 if (dmub_rb_empty(rb)) 2711 return false; 2712 2713 *cmd = (union dmub_rb_cmd *)rb_cmd; 2714 2715 return true; 2716 } 2717 2718 /** 2719 * @brief Determines the next ringbuffer offset. 2720 * 2721 * @param rb DMUB inbox ringbuffer 2722 * @param num_cmds Number of commands 2723 * @param next_rptr The next offset in the ringbuffer 2724 */ 2725 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2726 uint32_t num_cmds, 2727 uint32_t *next_rptr) 2728 { 2729 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2730 2731 if (*next_rptr >= rb->capacity) 2732 *next_rptr %= rb->capacity; 2733 } 2734 2735 /** 2736 * @brief Returns a pointer to a command in the inbox. 2737 * 2738 * @param rb DMUB inbox ringbuffer 2739 * @param cmd The inbox command to return 2740 * @param rptr The ringbuffer offset 2741 * @return true if not empty 2742 * @return false otherwise 2743 */ 2744 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 2745 union dmub_rb_cmd **cmd, 2746 uint32_t rptr) 2747 { 2748 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 2749 2750 if (dmub_rb_empty(rb)) 2751 return false; 2752 2753 *cmd = (union dmub_rb_cmd *)rb_cmd; 2754 2755 return true; 2756 } 2757 2758 /** 2759 * @brief Returns the next unprocessed command in the outbox. 2760 * 2761 * @param rb DMUB outbox ringbuffer 2762 * @param cmd The outbox command to return 2763 * @return true if not empty 2764 * @return false otherwise 2765 */ 2766 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2767 union dmub_rb_out_cmd *cmd) 2768 { 2769 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 2770 uint64_t *dst = (uint64_t *)cmd; 2771 uint8_t i; 2772 2773 if (dmub_rb_empty(rb)) 2774 return false; 2775 2776 // copying data 2777 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2778 *dst++ = *src++; 2779 2780 return true; 2781 } 2782 2783 /** 2784 * @brief Removes the front entry in the ringbuffer. 2785 * 2786 * @param rb DMUB ringbuffer 2787 * @return true if the command was removed 2788 * @return false if there were no commands 2789 */ 2790 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 2791 { 2792 if (dmub_rb_empty(rb)) 2793 return false; 2794 2795 rb->rptr += DMUB_RB_CMD_SIZE; 2796 2797 if (rb->rptr >= rb->capacity) 2798 rb->rptr %= rb->capacity; 2799 2800 return true; 2801 } 2802 2803 /** 2804 * @brief Flushes commands in the ringbuffer to framebuffer memory. 2805 * 2806 * Avoids a race condition where DMCUB accesses memory while 2807 * there are still writes in flight to framebuffer. 2808 * 2809 * @param rb DMUB ringbuffer 2810 */ 2811 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 2812 { 2813 uint32_t rptr = rb->rptr; 2814 uint32_t wptr = rb->wrpt; 2815 2816 while (rptr != wptr) { 2817 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 2818 //uint64_t volatile *p = (uint64_t volatile *)data; 2819 uint64_t temp; 2820 uint8_t i; 2821 2822 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2823 temp = *data++; 2824 2825 rptr += DMUB_RB_CMD_SIZE; 2826 if (rptr >= rb->capacity) 2827 rptr %= rb->capacity; 2828 } 2829 } 2830 2831 /** 2832 * @brief Initializes a DMCUB ringbuffer 2833 * 2834 * @param rb DMUB ringbuffer 2835 * @param init_params initial configuration for the ringbuffer 2836 */ 2837 static inline void dmub_rb_init(struct dmub_rb *rb, 2838 struct dmub_rb_init_params *init_params) 2839 { 2840 rb->base_address = init_params->base_address; 2841 rb->capacity = init_params->capacity; 2842 rb->rptr = init_params->read_ptr; 2843 rb->wrpt = init_params->write_ptr; 2844 } 2845 2846 /** 2847 * @brief Copies output data from in/out commands into the given command. 2848 * 2849 * @param rb DMUB ringbuffer 2850 * @param cmd Command to copy data into 2851 */ 2852 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 2853 union dmub_rb_cmd *cmd) 2854 { 2855 // Copy rb entry back into command 2856 uint8_t *rd_ptr = (rb->rptr == 0) ? 2857 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 2858 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 2859 2860 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 2861 } 2862 2863 #if defined(__cplusplus) 2864 } 2865 #endif 2866 2867 //============================================================================== 2868 //</DMUB_RB>==================================================================== 2869 //============================================================================== 2870 2871 #endif /* _DMUB_CMD_H_ */ 2872