1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Maximum number of streams on any ASIC. */ 99 #define DMUB_MAX_STREAMS 6 100 101 /* Maximum number of planes on any ASIC. */ 102 #define DMUB_MAX_PLANES 6 103 104 /* Trace buffer offset for entry */ 105 #define TRACE_BUFFER_ENTRY_OFFSET 16 106 107 /** 108 * Maximum number of dirty rects supported by FW. 109 */ 110 #define DMUB_MAX_DIRTY_RECTS 3 111 112 /** 113 * 114 * PSR control version legacy 115 */ 116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117 /** 118 * PSR control version with multi edp support 119 */ 120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121 122 123 /** 124 * ABM control version legacy 125 */ 126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127 128 /** 129 * ABM control version with multi edp support 130 */ 131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132 133 /** 134 * Physical framebuffer address location, 64-bit. 135 */ 136 #ifndef PHYSICAL_ADDRESS_LOC 137 #define PHYSICAL_ADDRESS_LOC union large_integer 138 #endif 139 140 /** 141 * OS/FW agnostic memcpy 142 */ 143 #ifndef dmub_memcpy 144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 145 #endif 146 147 /** 148 * OS/FW agnostic memset 149 */ 150 #ifndef dmub_memset 151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 152 #endif 153 154 #if defined(__cplusplus) 155 extern "C" { 156 #endif 157 158 /** 159 * OS/FW agnostic udelay 160 */ 161 #ifndef dmub_udelay 162 #define dmub_udelay(microseconds) udelay(microseconds) 163 #endif 164 165 /** 166 * union dmub_addr - DMUB physical/virtual 64-bit address. 167 */ 168 union dmub_addr { 169 struct { 170 uint32_t low_part; /**< Lower 32 bits */ 171 uint32_t high_part; /**< Upper 32 bits */ 172 } u; /*<< Low/high bit access */ 173 uint64_t quad_part; /*<< 64 bit address */ 174 }; 175 176 /** 177 * Dirty rect definition. 178 */ 179 struct dmub_rect { 180 /** 181 * Dirty rect x offset. 182 */ 183 uint32_t x; 184 185 /** 186 * Dirty rect y offset. 187 */ 188 uint32_t y; 189 190 /** 191 * Dirty rect width. 192 */ 193 uint32_t width; 194 195 /** 196 * Dirty rect height. 197 */ 198 uint32_t height; 199 }; 200 201 /** 202 * Flags that can be set by driver to change some PSR behaviour. 203 */ 204 union dmub_psr_debug_flags { 205 /** 206 * Debug flags. 207 */ 208 struct { 209 /** 210 * Enable visual confirm in FW. 211 */ 212 uint32_t visual_confirm : 1; 213 214 /** 215 * Force all selective updates to bw full frame updates. 216 */ 217 uint32_t force_full_frame_update : 1; 218 219 /** 220 * Use HW Lock Mgr object to do HW locking in FW. 221 */ 222 uint32_t use_hw_lock_mgr : 1; 223 224 /** 225 * Use TPS3 signal when restore main link. 226 */ 227 uint32_t force_wakeup_by_tps3 : 1; 228 229 /** 230 * Back to back flip, therefore cannot power down PHY 231 */ 232 uint32_t back_to_back_flip : 1; 233 234 } bitfields; 235 236 /** 237 * Union for debug flags. 238 */ 239 uint32_t u32All; 240 }; 241 242 /** 243 * DMUB visual confirm color 244 */ 245 struct dmub_feature_caps { 246 /** 247 * Max PSR version supported by FW. 248 */ 249 uint8_t psr; 250 uint8_t fw_assisted_mclk_switch; 251 uint8_t reserved[6]; 252 }; 253 254 struct dmub_visual_confirm_color { 255 /** 256 * Maximum 10 bits color value 257 */ 258 uint16_t color_r_cr; 259 uint16_t color_g_y; 260 uint16_t color_b_cb; 261 uint16_t panel_inst; 262 }; 263 264 #if defined(__cplusplus) 265 } 266 #endif 267 268 //============================================================================== 269 //</DMUB_TYPES>================================================================= 270 //============================================================================== 271 //< DMUB_META>================================================================== 272 //============================================================================== 273 #pragma pack(push, 1) 274 275 /* Magic value for identifying dmub_fw_meta_info */ 276 #define DMUB_FW_META_MAGIC 0x444D5542 277 278 /* Offset from the end of the file to the dmub_fw_meta_info */ 279 #define DMUB_FW_META_OFFSET 0x24 280 281 /** 282 * struct dmub_fw_meta_info - metadata associated with fw binary 283 * 284 * NOTE: This should be considered a stable API. Fields should 285 * not be repurposed or reordered. New fields should be 286 * added instead to extend the structure. 287 * 288 * @magic_value: magic value identifying DMUB firmware meta info 289 * @fw_region_size: size of the firmware state region 290 * @trace_buffer_size: size of the tracebuffer region 291 * @fw_version: the firmware version information 292 * @dal_fw: 1 if the firmware is DAL 293 */ 294 struct dmub_fw_meta_info { 295 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 296 uint32_t fw_region_size; /**< size of the firmware state region */ 297 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 298 uint32_t fw_version; /**< the firmware version information */ 299 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 300 uint8_t reserved[3]; /**< padding bits */ 301 }; 302 303 /** 304 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 305 */ 306 union dmub_fw_meta { 307 struct dmub_fw_meta_info info; /**< metadata info */ 308 uint8_t reserved[64]; /**< padding bits */ 309 }; 310 311 #pragma pack(pop) 312 313 //============================================================================== 314 //< DMUB Trace Buffer>================================================================ 315 //============================================================================== 316 /** 317 * dmub_trace_code_t - firmware trace code, 32-bits 318 */ 319 typedef uint32_t dmub_trace_code_t; 320 321 /** 322 * struct dmcub_trace_buf_entry - Firmware trace entry 323 */ 324 struct dmcub_trace_buf_entry { 325 dmub_trace_code_t trace_code; /**< trace code for the event */ 326 uint32_t tick_count; /**< the tick count at time of trace */ 327 uint32_t param0; /**< trace defined parameter 0 */ 328 uint32_t param1; /**< trace defined parameter 1 */ 329 }; 330 331 //============================================================================== 332 //< DMUB_STATUS>================================================================ 333 //============================================================================== 334 335 /** 336 * DMCUB scratch registers can be used to determine firmware status. 337 * Current scratch register usage is as follows: 338 * 339 * SCRATCH0: FW Boot Status register 340 * SCRATCH5: LVTMA Status Register 341 * SCRATCH15: FW Boot Options register 342 */ 343 344 /** 345 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 346 */ 347 union dmub_fw_boot_status { 348 struct { 349 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 350 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 351 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 352 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 353 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 354 uint32_t reserved : 1; 355 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 356 357 } bits; /**< status bits */ 358 uint32_t all; /**< 32-bit access to status bits */ 359 }; 360 361 /** 362 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 363 */ 364 enum dmub_fw_boot_status_bit { 365 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 366 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 367 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 368 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 369 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 370 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 371 }; 372 373 /* Register bit definition for SCRATCH5 */ 374 union dmub_lvtma_status { 375 struct { 376 uint32_t psp_ok : 1; 377 uint32_t edp_on : 1; 378 uint32_t reserved : 30; 379 } bits; 380 uint32_t all; 381 }; 382 383 enum dmub_lvtma_status_bit { 384 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 385 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 386 }; 387 388 /** 389 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 390 */ 391 union dmub_fw_boot_options { 392 struct { 393 uint32_t pemu_env : 1; /**< 1 if PEMU */ 394 uint32_t fpga_env : 1; /**< 1 if FPGA */ 395 uint32_t optimized_init : 1; /**< 1 if optimized init */ 396 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 397 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 398 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 399 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 400 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 401 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 402 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 403 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 404 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 405 uint32_t power_optimization: 1; 406 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 407 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 408 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 409 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 410 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 411 412 uint32_t reserved : 15; /**< reserved */ 413 } bits; /**< boot bits */ 414 uint32_t all; /**< 32-bit access to bits */ 415 }; 416 417 enum dmub_fw_boot_options_bit { 418 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 419 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 420 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 421 }; 422 423 //============================================================================== 424 //</DMUB_STATUS>================================================================ 425 //============================================================================== 426 //< DMUB_VBIOS>================================================================= 427 //============================================================================== 428 429 /* 430 * enum dmub_cmd_vbios_type - VBIOS commands. 431 * 432 * Command IDs should be treated as stable ABI. 433 * Do not reuse or modify IDs. 434 */ 435 enum dmub_cmd_vbios_type { 436 /** 437 * Configures the DIG encoder. 438 */ 439 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 440 /** 441 * Controls the PHY. 442 */ 443 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 444 /** 445 * Sets the pixel clock/symbol clock. 446 */ 447 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 448 /** 449 * Enables or disables power gating. 450 */ 451 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 452 /** 453 * Controls embedded panels. 454 */ 455 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 456 /** 457 * Query DP alt status on a transmitter. 458 */ 459 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 460 }; 461 462 //============================================================================== 463 //</DMUB_VBIOS>================================================================= 464 //============================================================================== 465 //< DMUB_GPINT>================================================================= 466 //============================================================================== 467 468 /** 469 * The shifts and masks below may alternatively be used to format and read 470 * the command register bits. 471 */ 472 473 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 474 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 475 476 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 477 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 478 479 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 480 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 481 482 /** 483 * Command responses. 484 */ 485 486 /** 487 * Return response for DMUB_GPINT__STOP_FW command. 488 */ 489 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 490 491 /** 492 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 493 */ 494 union dmub_gpint_data_register { 495 struct { 496 uint32_t param : 16; /**< 16-bit parameter */ 497 uint32_t command_code : 12; /**< GPINT command */ 498 uint32_t status : 4; /**< Command status bit */ 499 } bits; /**< GPINT bit access */ 500 uint32_t all; /**< GPINT 32-bit access */ 501 }; 502 503 /* 504 * enum dmub_gpint_command - GPINT command to DMCUB FW 505 * 506 * Command IDs should be treated as stable ABI. 507 * Do not reuse or modify IDs. 508 */ 509 enum dmub_gpint_command { 510 /** 511 * Invalid command, ignored. 512 */ 513 DMUB_GPINT__INVALID_COMMAND = 0, 514 /** 515 * DESC: Queries the firmware version. 516 * RETURN: Firmware version. 517 */ 518 DMUB_GPINT__GET_FW_VERSION = 1, 519 /** 520 * DESC: Halts the firmware. 521 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 522 */ 523 DMUB_GPINT__STOP_FW = 2, 524 /** 525 * DESC: Get PSR state from FW. 526 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 527 */ 528 DMUB_GPINT__GET_PSR_STATE = 7, 529 /** 530 * DESC: Notifies DMCUB of the currently active streams. 531 * ARGS: Stream mask, 1 bit per active stream index. 532 */ 533 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 534 /** 535 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 536 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 537 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 538 * RETURN: PSR residency in milli-percent. 539 */ 540 DMUB_GPINT__PSR_RESIDENCY = 9, 541 542 /** 543 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 544 */ 545 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 546 }; 547 548 /** 549 * INBOX0 generic command definition 550 */ 551 union dmub_inbox0_cmd_common { 552 struct { 553 uint32_t command_code: 8; /**< INBOX0 command code */ 554 uint32_t param: 24; /**< 24-bit parameter */ 555 } bits; 556 uint32_t all; 557 }; 558 559 /** 560 * INBOX0 hw_lock command definition 561 */ 562 union dmub_inbox0_cmd_lock_hw { 563 struct { 564 uint32_t command_code: 8; 565 566 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 567 uint32_t hw_lock_client: 2; 568 569 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 570 uint32_t otg_inst: 3; 571 uint32_t opp_inst: 3; 572 uint32_t dig_inst: 3; 573 574 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 575 uint32_t lock_pipe: 1; 576 uint32_t lock_cursor: 1; 577 uint32_t lock_dig: 1; 578 uint32_t triple_buffer_lock: 1; 579 580 uint32_t lock: 1; /**< Lock */ 581 uint32_t should_release: 1; /**< Release */ 582 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 583 } bits; 584 uint32_t all; 585 }; 586 587 union dmub_inbox0_data_register { 588 union dmub_inbox0_cmd_common inbox0_cmd_common; 589 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 590 }; 591 592 enum dmub_inbox0_command { 593 /** 594 * DESC: Invalid command, ignored. 595 */ 596 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 597 /** 598 * DESC: Notification to acquire/release HW lock 599 * ARGS: 600 */ 601 DMUB_INBOX0_CMD__HW_LOCK = 1, 602 }; 603 //============================================================================== 604 //</DMUB_GPINT>================================================================= 605 //============================================================================== 606 //< DMUB_CMD>=================================================================== 607 //============================================================================== 608 609 /** 610 * Size in bytes of each DMUB command. 611 */ 612 #define DMUB_RB_CMD_SIZE 64 613 614 /** 615 * Maximum number of items in the DMUB ringbuffer. 616 */ 617 #define DMUB_RB_MAX_ENTRY 128 618 619 /** 620 * Ringbuffer size in bytes. 621 */ 622 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 623 624 /** 625 * REG_SET mask for reg offload. 626 */ 627 #define REG_SET_MASK 0xFFFF 628 629 /* 630 * enum dmub_cmd_type - DMUB inbox command. 631 * 632 * Command IDs should be treated as stable ABI. 633 * Do not reuse or modify IDs. 634 */ 635 enum dmub_cmd_type { 636 /** 637 * Invalid command. 638 */ 639 DMUB_CMD__NULL = 0, 640 /** 641 * Read modify write register sequence offload. 642 */ 643 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 644 /** 645 * Field update register sequence offload. 646 */ 647 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 648 /** 649 * Burst write sequence offload. 650 */ 651 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 652 /** 653 * Reg wait sequence offload. 654 */ 655 DMUB_CMD__REG_REG_WAIT = 4, 656 /** 657 * Workaround to avoid HUBP underflow during NV12 playback. 658 */ 659 DMUB_CMD__PLAT_54186_WA = 5, 660 /** 661 * Command type used to query FW feature caps. 662 */ 663 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 664 /** 665 * Command type used to get visual confirm color. 666 */ 667 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 668 /** 669 * Command type used for all PSR commands. 670 */ 671 DMUB_CMD__PSR = 64, 672 /** 673 * Command type used for all MALL commands. 674 */ 675 DMUB_CMD__MALL = 65, 676 /** 677 * Command type used for all ABM commands. 678 */ 679 DMUB_CMD__ABM = 66, 680 /** 681 * Command type used to update dirty rects in FW. 682 */ 683 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 684 /** 685 * Command type used to update cursor info in FW. 686 */ 687 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 688 /** 689 * Command type used for HW locking in FW. 690 */ 691 DMUB_CMD__HW_LOCK = 69, 692 /** 693 * Command type used to access DP AUX. 694 */ 695 DMUB_CMD__DP_AUX_ACCESS = 70, 696 /** 697 * Command type used for OUTBOX1 notification enable 698 */ 699 DMUB_CMD__OUTBOX1_ENABLE = 71, 700 701 /** 702 * Command type used for all idle optimization commands. 703 */ 704 DMUB_CMD__IDLE_OPT = 72, 705 /** 706 * Command type used for all clock manager commands. 707 */ 708 DMUB_CMD__CLK_MGR = 73, 709 /** 710 * Command type used for all panel control commands. 711 */ 712 DMUB_CMD__PANEL_CNTL = 74, 713 /** 714 * Command type used for <TODO:description> 715 */ 716 DMUB_CMD__CAB_FOR_SS = 75, 717 718 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 719 720 /** 721 * Command type used for interfacing with DPIA. 722 */ 723 DMUB_CMD__DPIA = 77, 724 /** 725 * Command type used for EDID CEA parsing 726 */ 727 DMUB_CMD__EDID_CEA = 79, 728 /** 729 * Command type used for getting usbc cable ID 730 */ 731 DMUB_CMD_GET_USBC_CABLE_ID = 81, 732 /** 733 * Command type used to query HPD state. 734 */ 735 DMUB_CMD__QUERY_HPD_STATE = 82, 736 /** 737 * Command type used for all VBIOS interface commands. 738 */ 739 740 /** 741 * Command type used for all SECURE_DISPLAY commands. 742 */ 743 DMUB_CMD__SECURE_DISPLAY = 85, 744 745 /** 746 * Command type used to set DPIA HPD interrupt state 747 */ 748 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 749 750 DMUB_CMD__VBIOS = 128, 751 }; 752 753 /** 754 * enum dmub_out_cmd_type - DMUB outbox commands. 755 */ 756 enum dmub_out_cmd_type { 757 /** 758 * Invalid outbox command, ignored. 759 */ 760 DMUB_OUT_CMD__NULL = 0, 761 /** 762 * Command type used for DP AUX Reply data notification 763 */ 764 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 765 /** 766 * Command type used for DP HPD event notification 767 */ 768 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 769 /** 770 * Command type used for SET_CONFIG Reply notification 771 */ 772 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 773 }; 774 775 /* DMUB_CMD__DPIA command sub-types. */ 776 enum dmub_cmd_dpia_type { 777 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 778 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 779 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 780 }; 781 782 #pragma pack(push, 1) 783 784 /** 785 * struct dmub_cmd_header - Common command header fields. 786 */ 787 struct dmub_cmd_header { 788 unsigned int type : 8; /**< command type */ 789 unsigned int sub_type : 8; /**< command sub type */ 790 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 791 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 792 unsigned int reserved0 : 6; /**< reserved bits */ 793 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 794 unsigned int reserved1 : 2; /**< reserved bits */ 795 }; 796 797 /* 798 * struct dmub_cmd_read_modify_write_sequence - Read modify write 799 * 800 * 60 payload bytes can hold up to 5 sets of read modify writes, 801 * each take 3 dwords. 802 * 803 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 804 * 805 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 806 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 807 */ 808 struct dmub_cmd_read_modify_write_sequence { 809 uint32_t addr; /**< register address */ 810 uint32_t modify_mask; /**< modify mask */ 811 uint32_t modify_value; /**< modify value */ 812 }; 813 814 /** 815 * Maximum number of ops in read modify write sequence. 816 */ 817 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 818 819 /** 820 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 821 */ 822 struct dmub_rb_cmd_read_modify_write { 823 struct dmub_cmd_header header; /**< command header */ 824 /** 825 * Read modify write sequence. 826 */ 827 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 828 }; 829 830 /* 831 * Update a register with specified masks and values sequeunce 832 * 833 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 834 * 835 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 836 * 837 * 838 * USE CASE: 839 * 1. auto-increment register where additional read would update pointer and produce wrong result 840 * 2. toggle a bit without read in the middle 841 */ 842 843 struct dmub_cmd_reg_field_update_sequence { 844 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 845 uint32_t modify_value; /**< value to update with */ 846 }; 847 848 /** 849 * Maximum number of ops in field update sequence. 850 */ 851 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 852 853 /** 854 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 855 */ 856 struct dmub_rb_cmd_reg_field_update_sequence { 857 struct dmub_cmd_header header; /**< command header */ 858 uint32_t addr; /**< register address */ 859 /** 860 * Field update sequence. 861 */ 862 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 863 }; 864 865 866 /** 867 * Maximum number of burst write values. 868 */ 869 #define DMUB_BURST_WRITE_VALUES__MAX 14 870 871 /* 872 * struct dmub_rb_cmd_burst_write - Burst write 873 * 874 * support use case such as writing out LUTs. 875 * 876 * 60 payload bytes can hold up to 14 values to write to given address 877 * 878 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 879 */ 880 struct dmub_rb_cmd_burst_write { 881 struct dmub_cmd_header header; /**< command header */ 882 uint32_t addr; /**< register start address */ 883 /** 884 * Burst write register values. 885 */ 886 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 887 }; 888 889 /** 890 * struct dmub_rb_cmd_common - Common command header 891 */ 892 struct dmub_rb_cmd_common { 893 struct dmub_cmd_header header; /**< command header */ 894 /** 895 * Padding to RB_CMD_SIZE 896 */ 897 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 898 }; 899 900 /** 901 * struct dmub_cmd_reg_wait_data - Register wait data 902 */ 903 struct dmub_cmd_reg_wait_data { 904 uint32_t addr; /**< Register address */ 905 uint32_t mask; /**< Mask for register bits */ 906 uint32_t condition_field_value; /**< Value to wait for */ 907 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 908 }; 909 910 /** 911 * struct dmub_rb_cmd_reg_wait - Register wait command 912 */ 913 struct dmub_rb_cmd_reg_wait { 914 struct dmub_cmd_header header; /**< Command header */ 915 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 916 }; 917 918 /** 919 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 920 * 921 * Reprograms surface parameters to avoid underflow. 922 */ 923 struct dmub_cmd_PLAT_54186_wa { 924 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 925 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 926 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 927 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 928 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 929 struct { 930 uint8_t hubp_inst : 4; /**< HUBP instance */ 931 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 932 uint8_t immediate :1; /**< Immediate flip */ 933 uint8_t vmid : 4; /**< VMID */ 934 uint8_t grph_stereo : 1; /**< 1 if stereo */ 935 uint32_t reserved : 21; /**< Reserved */ 936 } flip_params; /**< Pageflip parameters */ 937 uint32_t reserved[9]; /**< Reserved bits */ 938 }; 939 940 /** 941 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 942 */ 943 struct dmub_rb_cmd_PLAT_54186_wa { 944 struct dmub_cmd_header header; /**< Command header */ 945 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 946 }; 947 948 /** 949 * struct dmub_rb_cmd_mall - MALL command data. 950 */ 951 struct dmub_rb_cmd_mall { 952 struct dmub_cmd_header header; /**< Common command header */ 953 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 954 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 955 uint32_t tmr_delay; /**< Timer delay */ 956 uint32_t tmr_scale; /**< Timer scale */ 957 uint16_t cursor_width; /**< Cursor width in pixels */ 958 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 959 uint16_t cursor_height; /**< Cursor height in pixels */ 960 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 961 uint8_t debug_bits; /**< Debug bits */ 962 963 uint8_t reserved1; /**< Reserved bits */ 964 uint8_t reserved2; /**< Reserved bits */ 965 }; 966 967 /** 968 * enum dmub_cmd_cab_type - TODO: 969 */ 970 enum dmub_cmd_cab_type { 971 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 972 DMUB_CMD__CAB_NO_DCN_REQ = 1, 973 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 974 }; 975 976 /** 977 * struct dmub_rb_cmd_cab_for_ss - TODO: 978 */ 979 struct dmub_rb_cmd_cab_for_ss { 980 struct dmub_cmd_header header; 981 uint8_t cab_alloc_ways; /* total number of ways */ 982 uint8_t debug_bits; /* debug bits */ 983 }; 984 985 enum mclk_switch_mode { 986 NONE = 0, 987 FPO = 1, 988 SUBVP = 2, 989 VBLANK = 3, 990 }; 991 992 /* Per pipe struct which stores the MCLK switch mode 993 * data to be sent to DMUB. 994 * Named "v2" for now -- once FPO and SUBVP are fully merged 995 * the type name can be updated 996 */ 997 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 998 union { 999 struct { 1000 uint32_t pix_clk_100hz; 1001 uint16_t main_vblank_start; 1002 uint16_t main_vblank_end; 1003 uint16_t mall_region_lines; 1004 uint16_t prefetch_lines; 1005 uint16_t prefetch_to_mall_start_lines; 1006 uint16_t processing_delay_lines; 1007 uint16_t htotal; // required to calculate line time for multi-display cases 1008 uint16_t vtotal; 1009 uint8_t main_pipe_index; 1010 uint8_t phantom_pipe_index; 1011 /* Since the microschedule is calculated in terms of OTG lines, 1012 * include any scaling factors to make sure when we get accurate 1013 * conversion when programming MALL_START_LINE (which is in terms 1014 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1015 * is 1/2 (numerator = 1, denominator = 2). 1016 */ 1017 uint8_t scale_factor_numerator; 1018 uint8_t scale_factor_denominator; 1019 uint8_t is_drr; 1020 uint8_t main_split_pipe_index; 1021 uint8_t phantom_split_pipe_index; 1022 } subvp_data; 1023 1024 struct { 1025 uint32_t pix_clk_100hz; 1026 uint16_t vblank_start; 1027 uint16_t vblank_end; 1028 uint16_t vstartup_start; 1029 uint16_t vtotal; 1030 uint16_t htotal; 1031 uint8_t vblank_pipe_index; 1032 uint8_t padding[2]; 1033 struct { 1034 uint8_t drr_in_use; 1035 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1036 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1037 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1038 uint8_t use_ramping; // Use ramping or not 1039 } drr_info; // DRR considered as part of SubVP + VBLANK case 1040 } vblank_data; 1041 } pipe_config; 1042 1043 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1044 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1045 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1046 */ 1047 uint8_t mode; // enum mclk_switch_mode 1048 }; 1049 1050 /** 1051 * Config data for Sub-VP and FPO 1052 * Named "v2" for now -- once FPO and SUBVP are fully merged 1053 * the type name can be updated 1054 */ 1055 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1056 uint16_t watermark_a_cache; 1057 uint8_t vertical_int_margin_us; 1058 uint8_t pstate_allow_width_us; 1059 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1060 }; 1061 1062 /** 1063 * DMUB rb command definition for Sub-VP and FPO 1064 * Named "v2" for now -- once FPO and SUBVP are fully merged 1065 * the type name can be updated 1066 */ 1067 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1068 struct dmub_cmd_header header; 1069 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1070 }; 1071 1072 /** 1073 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1074 */ 1075 enum dmub_cmd_idle_opt_type { 1076 /** 1077 * DCN hardware restore. 1078 */ 1079 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1080 1081 /** 1082 * DCN hardware save. 1083 */ 1084 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1085 }; 1086 1087 /** 1088 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1089 */ 1090 struct dmub_rb_cmd_idle_opt_dcn_restore { 1091 struct dmub_cmd_header header; /**< header */ 1092 }; 1093 1094 /** 1095 * struct dmub_clocks - Clock update notification. 1096 */ 1097 struct dmub_clocks { 1098 uint32_t dispclk_khz; /**< dispclk kHz */ 1099 uint32_t dppclk_khz; /**< dppclk kHz */ 1100 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1101 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1102 }; 1103 1104 /** 1105 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1106 */ 1107 enum dmub_cmd_clk_mgr_type { 1108 /** 1109 * Notify DMCUB of clock update. 1110 */ 1111 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1112 }; 1113 1114 /** 1115 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1116 */ 1117 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1118 struct dmub_cmd_header header; /**< header */ 1119 struct dmub_clocks clocks; /**< clock data */ 1120 }; 1121 1122 /** 1123 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1124 */ 1125 struct dmub_cmd_digx_encoder_control_data { 1126 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1127 }; 1128 1129 /** 1130 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1131 */ 1132 struct dmub_rb_cmd_digx_encoder_control { 1133 struct dmub_cmd_header header; /**< header */ 1134 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1135 }; 1136 1137 /** 1138 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1139 */ 1140 struct dmub_cmd_set_pixel_clock_data { 1141 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1142 }; 1143 1144 /** 1145 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1146 */ 1147 struct dmub_rb_cmd_set_pixel_clock { 1148 struct dmub_cmd_header header; /**< header */ 1149 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1150 }; 1151 1152 /** 1153 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1154 */ 1155 struct dmub_cmd_enable_disp_power_gating_data { 1156 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1157 }; 1158 1159 /** 1160 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1161 */ 1162 struct dmub_rb_cmd_enable_disp_power_gating { 1163 struct dmub_cmd_header header; /**< header */ 1164 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1165 }; 1166 1167 /** 1168 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1169 */ 1170 struct dmub_dig_transmitter_control_data_v1_7 { 1171 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1172 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1173 union { 1174 uint8_t digmode; /**< enum atom_encode_mode_def */ 1175 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1176 } mode_laneset; 1177 uint8_t lanenum; /**< Number of lanes */ 1178 union { 1179 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1180 } symclk_units; 1181 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1182 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1183 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1184 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1185 uint8_t reserved1; /**< For future use */ 1186 uint8_t reserved2[3]; /**< For future use */ 1187 uint32_t reserved3[11]; /**< For future use */ 1188 }; 1189 1190 /** 1191 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1192 */ 1193 union dmub_cmd_dig1_transmitter_control_data { 1194 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1195 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1196 }; 1197 1198 /** 1199 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1200 */ 1201 struct dmub_rb_cmd_dig1_transmitter_control { 1202 struct dmub_cmd_header header; /**< header */ 1203 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1204 }; 1205 1206 /** 1207 * DPIA tunnel command parameters. 1208 */ 1209 struct dmub_cmd_dig_dpia_control_data { 1210 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1211 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1212 union { 1213 uint8_t digmode; /** enum atom_encode_mode_def */ 1214 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1215 } mode_laneset; 1216 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1217 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1218 uint8_t hpdsel; /** =0: HPD is not assigned */ 1219 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1220 uint8_t dpia_id; /** Index of DPIA */ 1221 uint8_t fec_rdy : 1; 1222 uint8_t reserved : 7; 1223 uint32_t reserved1; 1224 }; 1225 1226 /** 1227 * DMUB command for DPIA tunnel control. 1228 */ 1229 struct dmub_rb_cmd_dig1_dpia_control { 1230 struct dmub_cmd_header header; 1231 struct dmub_cmd_dig_dpia_control_data dpia_control; 1232 }; 1233 1234 /** 1235 * SET_CONFIG Command Payload 1236 */ 1237 struct set_config_cmd_payload { 1238 uint8_t msg_type; /* set config message type */ 1239 uint8_t msg_data; /* set config message data */ 1240 }; 1241 1242 /** 1243 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1244 */ 1245 struct dmub_cmd_set_config_control_data { 1246 struct set_config_cmd_payload cmd_pkt; 1247 uint8_t instance; /* DPIA instance */ 1248 uint8_t immed_status; /* Immediate status returned in case of error */ 1249 }; 1250 1251 /** 1252 * DMUB command structure for SET_CONFIG command. 1253 */ 1254 struct dmub_rb_cmd_set_config_access { 1255 struct dmub_cmd_header header; /* header */ 1256 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1257 }; 1258 1259 /** 1260 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1261 */ 1262 struct dmub_cmd_mst_alloc_slots_control_data { 1263 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1264 uint8_t instance; /* DPIA instance */ 1265 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1266 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1267 }; 1268 1269 /** 1270 * DMUB command structure for SET_ command. 1271 */ 1272 struct dmub_rb_cmd_set_mst_alloc_slots { 1273 struct dmub_cmd_header header; /* header */ 1274 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1275 }; 1276 1277 /** 1278 * DMUB command structure for DPIA HPD int enable control. 1279 */ 1280 struct dmub_rb_cmd_dpia_hpd_int_enable { 1281 struct dmub_cmd_header header; /* header */ 1282 uint32_t enable; /* dpia hpd interrupt enable */ 1283 }; 1284 1285 /** 1286 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1287 */ 1288 struct dmub_rb_cmd_dpphy_init { 1289 struct dmub_cmd_header header; /**< header */ 1290 uint8_t reserved[60]; /**< reserved bits */ 1291 }; 1292 1293 /** 1294 * enum dp_aux_request_action - DP AUX request command listing. 1295 * 1296 * 4 AUX request command bits are shifted to high nibble. 1297 */ 1298 enum dp_aux_request_action { 1299 /** I2C-over-AUX write request */ 1300 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1301 /** I2C-over-AUX read request */ 1302 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1303 /** I2C-over-AUX write status request */ 1304 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1305 /** I2C-over-AUX write request with MOT=1 */ 1306 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1307 /** I2C-over-AUX read request with MOT=1 */ 1308 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1309 /** I2C-over-AUX write status request with MOT=1 */ 1310 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1311 /** Native AUX write request */ 1312 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1313 /** Native AUX read request */ 1314 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1315 }; 1316 1317 /** 1318 * enum aux_return_code_type - DP AUX process return code listing. 1319 */ 1320 enum aux_return_code_type { 1321 /** AUX process succeeded */ 1322 AUX_RET_SUCCESS = 0, 1323 /** AUX process failed with unknown reason */ 1324 AUX_RET_ERROR_UNKNOWN, 1325 /** AUX process completed with invalid reply */ 1326 AUX_RET_ERROR_INVALID_REPLY, 1327 /** AUX process timed out */ 1328 AUX_RET_ERROR_TIMEOUT, 1329 /** HPD was low during AUX process */ 1330 AUX_RET_ERROR_HPD_DISCON, 1331 /** Failed to acquire AUX engine */ 1332 AUX_RET_ERROR_ENGINE_ACQUIRE, 1333 /** AUX request not supported */ 1334 AUX_RET_ERROR_INVALID_OPERATION, 1335 /** AUX process not available */ 1336 AUX_RET_ERROR_PROTOCOL_ERROR, 1337 }; 1338 1339 /** 1340 * enum aux_channel_type - DP AUX channel type listing. 1341 */ 1342 enum aux_channel_type { 1343 /** AUX thru Legacy DP AUX */ 1344 AUX_CHANNEL_LEGACY_DDC, 1345 /** AUX thru DPIA DP tunneling */ 1346 AUX_CHANNEL_DPIA 1347 }; 1348 1349 /** 1350 * struct aux_transaction_parameters - DP AUX request transaction data 1351 */ 1352 struct aux_transaction_parameters { 1353 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1354 uint8_t action; /**< enum dp_aux_request_action */ 1355 uint8_t length; /**< DP AUX request data length */ 1356 uint8_t reserved; /**< For future use */ 1357 uint32_t address; /**< DP AUX address */ 1358 uint8_t data[16]; /**< DP AUX write data */ 1359 }; 1360 1361 /** 1362 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1363 */ 1364 struct dmub_cmd_dp_aux_control_data { 1365 uint8_t instance; /**< AUX instance or DPIA instance */ 1366 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1367 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1368 uint8_t reserved0; /**< For future use */ 1369 uint16_t timeout; /**< timeout time in us */ 1370 uint16_t reserved1; /**< For future use */ 1371 enum aux_channel_type type; /**< enum aux_channel_type */ 1372 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1373 }; 1374 1375 /** 1376 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1377 */ 1378 struct dmub_rb_cmd_dp_aux_access { 1379 /** 1380 * Command header. 1381 */ 1382 struct dmub_cmd_header header; 1383 /** 1384 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1385 */ 1386 struct dmub_cmd_dp_aux_control_data aux_control; 1387 }; 1388 1389 /** 1390 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1391 */ 1392 struct dmub_rb_cmd_outbox1_enable { 1393 /** 1394 * Command header. 1395 */ 1396 struct dmub_cmd_header header; 1397 /** 1398 * enable: 0x0 -> disable outbox1 notification (default value) 1399 * 0x1 -> enable outbox1 notification 1400 */ 1401 uint32_t enable; 1402 }; 1403 1404 /* DP AUX Reply command - OutBox Cmd */ 1405 /** 1406 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1407 */ 1408 struct aux_reply_data { 1409 /** 1410 * Aux cmd 1411 */ 1412 uint8_t command; 1413 /** 1414 * Aux reply data length (max: 16 bytes) 1415 */ 1416 uint8_t length; 1417 /** 1418 * Alignment only 1419 */ 1420 uint8_t pad[2]; 1421 /** 1422 * Aux reply data 1423 */ 1424 uint8_t data[16]; 1425 }; 1426 1427 /** 1428 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1429 */ 1430 struct aux_reply_control_data { 1431 /** 1432 * Reserved for future use 1433 */ 1434 uint32_t handle; 1435 /** 1436 * Aux Instance 1437 */ 1438 uint8_t instance; 1439 /** 1440 * Aux transaction result: definition in enum aux_return_code_type 1441 */ 1442 uint8_t result; 1443 /** 1444 * Alignment only 1445 */ 1446 uint16_t pad; 1447 }; 1448 1449 /** 1450 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1451 */ 1452 struct dmub_rb_cmd_dp_aux_reply { 1453 /** 1454 * Command header. 1455 */ 1456 struct dmub_cmd_header header; 1457 /** 1458 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1459 */ 1460 struct aux_reply_control_data control; 1461 /** 1462 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1463 */ 1464 struct aux_reply_data reply_data; 1465 }; 1466 1467 /* DP HPD Notify command - OutBox Cmd */ 1468 /** 1469 * DP HPD Type 1470 */ 1471 enum dp_hpd_type { 1472 /** 1473 * Normal DP HPD 1474 */ 1475 DP_HPD = 0, 1476 /** 1477 * DP HPD short pulse 1478 */ 1479 DP_IRQ 1480 }; 1481 1482 /** 1483 * DP HPD Status 1484 */ 1485 enum dp_hpd_status { 1486 /** 1487 * DP_HPD status low 1488 */ 1489 DP_HPD_UNPLUG = 0, 1490 /** 1491 * DP_HPD status high 1492 */ 1493 DP_HPD_PLUG 1494 }; 1495 1496 /** 1497 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1498 */ 1499 struct dp_hpd_data { 1500 /** 1501 * DP HPD instance 1502 */ 1503 uint8_t instance; 1504 /** 1505 * HPD type 1506 */ 1507 uint8_t hpd_type; 1508 /** 1509 * HPD status: only for type: DP_HPD to indicate status 1510 */ 1511 uint8_t hpd_status; 1512 /** 1513 * Alignment only 1514 */ 1515 uint8_t pad; 1516 }; 1517 1518 /** 1519 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1520 */ 1521 struct dmub_rb_cmd_dp_hpd_notify { 1522 /** 1523 * Command header. 1524 */ 1525 struct dmub_cmd_header header; 1526 /** 1527 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1528 */ 1529 struct dp_hpd_data hpd_data; 1530 }; 1531 1532 /** 1533 * Definition of a SET_CONFIG reply from DPOA. 1534 */ 1535 enum set_config_status { 1536 SET_CONFIG_PENDING = 0, 1537 SET_CONFIG_ACK_RECEIVED, 1538 SET_CONFIG_RX_TIMEOUT, 1539 SET_CONFIG_UNKNOWN_ERROR, 1540 }; 1541 1542 /** 1543 * Definition of a set_config reply 1544 */ 1545 struct set_config_reply_control_data { 1546 uint8_t instance; /* DPIA Instance */ 1547 uint8_t status; /* Set Config reply */ 1548 uint16_t pad; /* Alignment */ 1549 }; 1550 1551 /** 1552 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1553 */ 1554 struct dmub_rb_cmd_dp_set_config_reply { 1555 struct dmub_cmd_header header; 1556 struct set_config_reply_control_data set_config_reply_control; 1557 }; 1558 1559 /** 1560 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1561 */ 1562 struct dmub_cmd_hpd_state_query_data { 1563 uint8_t instance; /**< HPD instance or DPIA instance */ 1564 uint8_t result; /**< For returning HPD state */ 1565 uint16_t pad; /** < Alignment */ 1566 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1567 enum aux_return_code_type status; /**< for returning the status of command */ 1568 }; 1569 1570 /** 1571 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1572 */ 1573 struct dmub_rb_cmd_query_hpd_state { 1574 /** 1575 * Command header. 1576 */ 1577 struct dmub_cmd_header header; 1578 /** 1579 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1580 */ 1581 struct dmub_cmd_hpd_state_query_data data; 1582 }; 1583 1584 /* 1585 * Command IDs should be treated as stable ABI. 1586 * Do not reuse or modify IDs. 1587 */ 1588 1589 /** 1590 * PSR command sub-types. 1591 */ 1592 enum dmub_cmd_psr_type { 1593 /** 1594 * Set PSR version support. 1595 */ 1596 DMUB_CMD__PSR_SET_VERSION = 0, 1597 /** 1598 * Copy driver-calculated parameters to PSR state. 1599 */ 1600 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1601 /** 1602 * Enable PSR. 1603 */ 1604 DMUB_CMD__PSR_ENABLE = 2, 1605 1606 /** 1607 * Disable PSR. 1608 */ 1609 DMUB_CMD__PSR_DISABLE = 3, 1610 1611 /** 1612 * Set PSR level. 1613 * PSR level is a 16-bit value dicated by driver that 1614 * will enable/disable different functionality. 1615 */ 1616 DMUB_CMD__PSR_SET_LEVEL = 4, 1617 1618 /** 1619 * Forces PSR enabled until an explicit PSR disable call. 1620 */ 1621 DMUB_CMD__PSR_FORCE_STATIC = 5, 1622 /** 1623 * Set vtotal in psr active for FreeSync PSR. 1624 */ 1625 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1626 /** 1627 * Set PSR power option 1628 */ 1629 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1630 }; 1631 1632 enum dmub_cmd_fams_type { 1633 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1634 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1635 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1636 /** 1637 * For SubVP set manual trigger in FW because it 1638 * triggers DRR_UPDATE_PENDING which SubVP relies 1639 * on (for any SubVP cases that use a DRR display) 1640 */ 1641 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1642 }; 1643 1644 /** 1645 * PSR versions. 1646 */ 1647 enum psr_version { 1648 /** 1649 * PSR version 1. 1650 */ 1651 PSR_VERSION_1 = 0, 1652 /** 1653 * Freesync PSR SU. 1654 */ 1655 PSR_VERSION_SU_1 = 1, 1656 /** 1657 * PSR not supported. 1658 */ 1659 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1660 }; 1661 1662 /** 1663 * enum dmub_cmd_mall_type - MALL commands 1664 */ 1665 enum dmub_cmd_mall_type { 1666 /** 1667 * Allows display refresh from MALL. 1668 */ 1669 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1670 /** 1671 * Disallows display refresh from MALL. 1672 */ 1673 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1674 /** 1675 * Cursor copy for MALL. 1676 */ 1677 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1678 /** 1679 * Controls DF requests. 1680 */ 1681 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1682 }; 1683 1684 /** 1685 * PHY Link rate for DP. 1686 */ 1687 enum phy_link_rate { 1688 /** 1689 * not supported. 1690 */ 1691 PHY_RATE_UNKNOWN = 0, 1692 /** 1693 * Rate_1 (RBR) - 1.62 Gbps/Lane 1694 */ 1695 PHY_RATE_162 = 1, 1696 /** 1697 * Rate_2 - 2.16 Gbps/Lane 1698 */ 1699 PHY_RATE_216 = 2, 1700 /** 1701 * Rate_3 - 2.43 Gbps/Lane 1702 */ 1703 PHY_RATE_243 = 3, 1704 /** 1705 * Rate_4 (HBR) - 2.70 Gbps/Lane 1706 */ 1707 PHY_RATE_270 = 4, 1708 /** 1709 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1710 */ 1711 PHY_RATE_324 = 5, 1712 /** 1713 * Rate_6 - 4.32 Gbps/Lane 1714 */ 1715 PHY_RATE_432 = 6, 1716 /** 1717 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1718 */ 1719 PHY_RATE_540 = 7, 1720 /** 1721 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1722 */ 1723 PHY_RATE_810 = 8, 1724 /** 1725 * UHBR10 - 10.0 Gbps/Lane 1726 */ 1727 PHY_RATE_1000 = 9, 1728 /** 1729 * UHBR13.5 - 13.5 Gbps/Lane 1730 */ 1731 PHY_RATE_1350 = 10, 1732 /** 1733 * UHBR10 - 20.0 Gbps/Lane 1734 */ 1735 PHY_RATE_2000 = 11, 1736 }; 1737 1738 /** 1739 * enum dmub_phy_fsm_state - PHY FSM states. 1740 * PHY FSM state to transit to during PSR enable/disable. 1741 */ 1742 enum dmub_phy_fsm_state { 1743 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1744 DMUB_PHY_FSM_RESET, 1745 DMUB_PHY_FSM_RESET_RELEASED, 1746 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1747 DMUB_PHY_FSM_INITIALIZED, 1748 DMUB_PHY_FSM_CALIBRATED, 1749 DMUB_PHY_FSM_CALIBRATED_LP, 1750 DMUB_PHY_FSM_CALIBRATED_PG, 1751 DMUB_PHY_FSM_POWER_DOWN, 1752 DMUB_PHY_FSM_PLL_EN, 1753 DMUB_PHY_FSM_TX_EN, 1754 DMUB_PHY_FSM_FAST_LP, 1755 }; 1756 1757 /** 1758 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1759 */ 1760 struct dmub_cmd_psr_copy_settings_data { 1761 /** 1762 * Flags that can be set by driver to change some PSR behaviour. 1763 */ 1764 union dmub_psr_debug_flags debug; 1765 /** 1766 * 16-bit value dicated by driver that will enable/disable different functionality. 1767 */ 1768 uint16_t psr_level; 1769 /** 1770 * DPP HW instance. 1771 */ 1772 uint8_t dpp_inst; 1773 /** 1774 * MPCC HW instance. 1775 * Not used in dmub fw, 1776 * dmub fw will get active opp by reading odm registers. 1777 */ 1778 uint8_t mpcc_inst; 1779 /** 1780 * OPP HW instance. 1781 * Not used in dmub fw, 1782 * dmub fw will get active opp by reading odm registers. 1783 */ 1784 uint8_t opp_inst; 1785 /** 1786 * OTG HW instance. 1787 */ 1788 uint8_t otg_inst; 1789 /** 1790 * DIG FE HW instance. 1791 */ 1792 uint8_t digfe_inst; 1793 /** 1794 * DIG BE HW instance. 1795 */ 1796 uint8_t digbe_inst; 1797 /** 1798 * DP PHY HW instance. 1799 */ 1800 uint8_t dpphy_inst; 1801 /** 1802 * AUX HW instance. 1803 */ 1804 uint8_t aux_inst; 1805 /** 1806 * Determines if SMU optimzations are enabled/disabled. 1807 */ 1808 uint8_t smu_optimizations_en; 1809 /** 1810 * Unused. 1811 * TODO: Remove. 1812 */ 1813 uint8_t frame_delay; 1814 /** 1815 * If RFB setup time is greater than the total VBLANK time, 1816 * it is not possible for the sink to capture the video frame 1817 * in the same frame the SDP is sent. In this case, 1818 * the frame capture indication bit should be set and an extra 1819 * static frame should be transmitted to the sink. 1820 */ 1821 uint8_t frame_cap_ind; 1822 /** 1823 * Granularity of Y offset supported by sink. 1824 */ 1825 uint8_t su_y_granularity; 1826 /** 1827 * Indicates whether sink should start capturing 1828 * immediately following active scan line, 1829 * or starting with the 2nd active scan line. 1830 */ 1831 uint8_t line_capture_indication; 1832 /** 1833 * Multi-display optimizations are implemented on certain ASICs. 1834 */ 1835 uint8_t multi_disp_optimizations_en; 1836 /** 1837 * The last possible line SDP may be transmitted without violating 1838 * the RFB setup time or entering the active video frame. 1839 */ 1840 uint16_t init_sdp_deadline; 1841 /** 1842 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1843 */ 1844 uint8_t rate_control_caps ; 1845 /* 1846 * Force PSRSU always doing full frame update 1847 */ 1848 uint8_t force_ffu_mode; 1849 /** 1850 * Length of each horizontal line in us. 1851 */ 1852 uint32_t line_time_in_us; 1853 /** 1854 * FEC enable status in driver 1855 */ 1856 uint8_t fec_enable_status; 1857 /** 1858 * FEC re-enable delay when PSR exit. 1859 * unit is 100us, range form 0~255(0xFF). 1860 */ 1861 uint8_t fec_enable_delay_in100us; 1862 /** 1863 * PSR control version. 1864 */ 1865 uint8_t cmd_version; 1866 /** 1867 * Panel Instance. 1868 * Panel isntance to identify which psr_state to use 1869 * Currently the support is only for 0 or 1 1870 */ 1871 uint8_t panel_inst; 1872 /* 1873 * DSC enable status in driver 1874 */ 1875 uint8_t dsc_enable_status; 1876 /* 1877 * Use FSM state for PSR power up/down 1878 */ 1879 uint8_t use_phy_fsm; 1880 /** 1881 * frame delay for frame re-lock 1882 */ 1883 uint8_t relock_delay_frame_cnt; 1884 /** 1885 * Explicit padding to 2 byte boundary. 1886 */ 1887 uint8_t pad3; 1888 }; 1889 1890 /** 1891 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1892 */ 1893 struct dmub_rb_cmd_psr_copy_settings { 1894 /** 1895 * Command header. 1896 */ 1897 struct dmub_cmd_header header; 1898 /** 1899 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1900 */ 1901 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1902 }; 1903 1904 /** 1905 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1906 */ 1907 struct dmub_cmd_psr_set_level_data { 1908 /** 1909 * 16-bit value dicated by driver that will enable/disable different functionality. 1910 */ 1911 uint16_t psr_level; 1912 /** 1913 * PSR control version. 1914 */ 1915 uint8_t cmd_version; 1916 /** 1917 * Panel Instance. 1918 * Panel isntance to identify which psr_state to use 1919 * Currently the support is only for 0 or 1 1920 */ 1921 uint8_t panel_inst; 1922 }; 1923 1924 /** 1925 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1926 */ 1927 struct dmub_rb_cmd_psr_set_level { 1928 /** 1929 * Command header. 1930 */ 1931 struct dmub_cmd_header header; 1932 /** 1933 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1934 */ 1935 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1936 }; 1937 1938 struct dmub_rb_cmd_psr_enable_data { 1939 /** 1940 * PSR control version. 1941 */ 1942 uint8_t cmd_version; 1943 /** 1944 * Panel Instance. 1945 * Panel isntance to identify which psr_state to use 1946 * Currently the support is only for 0 or 1 1947 */ 1948 uint8_t panel_inst; 1949 /** 1950 * Phy state to enter. 1951 * Values to use are defined in dmub_phy_fsm_state 1952 */ 1953 uint8_t phy_fsm_state; 1954 /** 1955 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1956 * Set this using enum phy_link_rate. 1957 * This does not support HDMI/DP2 for now. 1958 */ 1959 uint8_t phy_rate; 1960 }; 1961 1962 /** 1963 * Definition of a DMUB_CMD__PSR_ENABLE command. 1964 * PSR enable/disable is controlled using the sub_type. 1965 */ 1966 struct dmub_rb_cmd_psr_enable { 1967 /** 1968 * Command header. 1969 */ 1970 struct dmub_cmd_header header; 1971 1972 struct dmub_rb_cmd_psr_enable_data data; 1973 }; 1974 1975 /** 1976 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1977 */ 1978 struct dmub_cmd_psr_set_version_data { 1979 /** 1980 * PSR version that FW should implement. 1981 */ 1982 enum psr_version version; 1983 /** 1984 * PSR control version. 1985 */ 1986 uint8_t cmd_version; 1987 /** 1988 * Panel Instance. 1989 * Panel isntance to identify which psr_state to use 1990 * Currently the support is only for 0 or 1 1991 */ 1992 uint8_t panel_inst; 1993 /** 1994 * Explicit padding to 4 byte boundary. 1995 */ 1996 uint8_t pad[2]; 1997 }; 1998 1999 /** 2000 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2001 */ 2002 struct dmub_rb_cmd_psr_set_version { 2003 /** 2004 * Command header. 2005 */ 2006 struct dmub_cmd_header header; 2007 /** 2008 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2009 */ 2010 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2011 }; 2012 2013 struct dmub_cmd_psr_force_static_data { 2014 /** 2015 * PSR control version. 2016 */ 2017 uint8_t cmd_version; 2018 /** 2019 * Panel Instance. 2020 * Panel isntance to identify which psr_state to use 2021 * Currently the support is only for 0 or 1 2022 */ 2023 uint8_t panel_inst; 2024 /** 2025 * Explicit padding to 4 byte boundary. 2026 */ 2027 uint8_t pad[2]; 2028 }; 2029 2030 /** 2031 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2032 */ 2033 struct dmub_rb_cmd_psr_force_static { 2034 /** 2035 * Command header. 2036 */ 2037 struct dmub_cmd_header header; 2038 /** 2039 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2040 */ 2041 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2042 }; 2043 2044 /** 2045 * PSR SU debug flags. 2046 */ 2047 union dmub_psr_su_debug_flags { 2048 /** 2049 * PSR SU debug flags. 2050 */ 2051 struct { 2052 /** 2053 * Update dirty rect in SW only. 2054 */ 2055 uint8_t update_dirty_rect_only : 1; 2056 /** 2057 * Reset the cursor/plane state before processing the call. 2058 */ 2059 uint8_t reset_state : 1; 2060 } bitfields; 2061 2062 /** 2063 * Union for debug flags. 2064 */ 2065 uint32_t u32All; 2066 }; 2067 2068 /** 2069 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2070 * This triggers a selective update for PSR SU. 2071 */ 2072 struct dmub_cmd_update_dirty_rect_data { 2073 /** 2074 * Dirty rects from OS. 2075 */ 2076 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2077 /** 2078 * PSR SU debug flags. 2079 */ 2080 union dmub_psr_su_debug_flags debug_flags; 2081 /** 2082 * OTG HW instance. 2083 */ 2084 uint8_t pipe_idx; 2085 /** 2086 * Number of dirty rects. 2087 */ 2088 uint8_t dirty_rect_count; 2089 /** 2090 * PSR control version. 2091 */ 2092 uint8_t cmd_version; 2093 /** 2094 * Panel Instance. 2095 * Panel isntance to identify which psr_state to use 2096 * Currently the support is only for 0 or 1 2097 */ 2098 uint8_t panel_inst; 2099 }; 2100 2101 /** 2102 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2103 */ 2104 struct dmub_rb_cmd_update_dirty_rect { 2105 /** 2106 * Command header. 2107 */ 2108 struct dmub_cmd_header header; 2109 /** 2110 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2111 */ 2112 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2113 }; 2114 2115 /** 2116 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2117 */ 2118 union dmub_reg_cursor_control_cfg { 2119 struct { 2120 uint32_t cur_enable: 1; 2121 uint32_t reser0: 3; 2122 uint32_t cur_2x_magnify: 1; 2123 uint32_t reser1: 3; 2124 uint32_t mode: 3; 2125 uint32_t reser2: 5; 2126 uint32_t pitch: 2; 2127 uint32_t reser3: 6; 2128 uint32_t line_per_chunk: 5; 2129 uint32_t reser4: 3; 2130 } bits; 2131 uint32_t raw; 2132 }; 2133 struct dmub_cursor_position_cache_hubp { 2134 union dmub_reg_cursor_control_cfg cur_ctl; 2135 union dmub_reg_position_cfg { 2136 struct { 2137 uint32_t cur_x_pos: 16; 2138 uint32_t cur_y_pos: 16; 2139 } bits; 2140 uint32_t raw; 2141 } position; 2142 union dmub_reg_hot_spot_cfg { 2143 struct { 2144 uint32_t hot_x: 16; 2145 uint32_t hot_y: 16; 2146 } bits; 2147 uint32_t raw; 2148 } hot_spot; 2149 union dmub_reg_dst_offset_cfg { 2150 struct { 2151 uint32_t dst_x_offset: 13; 2152 uint32_t reserved: 19; 2153 } bits; 2154 uint32_t raw; 2155 } dst_offset; 2156 }; 2157 2158 union dmub_reg_cur0_control_cfg { 2159 struct { 2160 uint32_t cur0_enable: 1; 2161 uint32_t expansion_mode: 1; 2162 uint32_t reser0: 1; 2163 uint32_t cur0_rom_en: 1; 2164 uint32_t mode: 3; 2165 uint32_t reserved: 25; 2166 } bits; 2167 uint32_t raw; 2168 }; 2169 struct dmub_cursor_position_cache_dpp { 2170 union dmub_reg_cur0_control_cfg cur0_ctl; 2171 }; 2172 struct dmub_cursor_position_cfg { 2173 struct dmub_cursor_position_cache_hubp pHubp; 2174 struct dmub_cursor_position_cache_dpp pDpp; 2175 uint8_t pipe_idx; 2176 /* 2177 * Padding is required. To be 4 Bytes Aligned. 2178 */ 2179 uint8_t padding[3]; 2180 }; 2181 2182 struct dmub_cursor_attribute_cache_hubp { 2183 uint32_t SURFACE_ADDR_HIGH; 2184 uint32_t SURFACE_ADDR; 2185 union dmub_reg_cursor_control_cfg cur_ctl; 2186 union dmub_reg_cursor_size_cfg { 2187 struct { 2188 uint32_t width: 16; 2189 uint32_t height: 16; 2190 } bits; 2191 uint32_t raw; 2192 } size; 2193 union dmub_reg_cursor_settings_cfg { 2194 struct { 2195 uint32_t dst_y_offset: 8; 2196 uint32_t chunk_hdl_adjust: 2; 2197 uint32_t reserved: 22; 2198 } bits; 2199 uint32_t raw; 2200 } settings; 2201 }; 2202 struct dmub_cursor_attribute_cache_dpp { 2203 union dmub_reg_cur0_control_cfg cur0_ctl; 2204 }; 2205 struct dmub_cursor_attributes_cfg { 2206 struct dmub_cursor_attribute_cache_hubp aHubp; 2207 struct dmub_cursor_attribute_cache_dpp aDpp; 2208 }; 2209 2210 struct dmub_cmd_update_cursor_payload0 { 2211 /** 2212 * Cursor dirty rects. 2213 */ 2214 struct dmub_rect cursor_rect; 2215 /** 2216 * PSR SU debug flags. 2217 */ 2218 union dmub_psr_su_debug_flags debug_flags; 2219 /** 2220 * Cursor enable/disable. 2221 */ 2222 uint8_t enable; 2223 /** 2224 * OTG HW instance. 2225 */ 2226 uint8_t pipe_idx; 2227 /** 2228 * PSR control version. 2229 */ 2230 uint8_t cmd_version; 2231 /** 2232 * Panel Instance. 2233 * Panel isntance to identify which psr_state to use 2234 * Currently the support is only for 0 or 1 2235 */ 2236 uint8_t panel_inst; 2237 /** 2238 * Cursor Position Register. 2239 * Registers contains Hubp & Dpp modules 2240 */ 2241 struct dmub_cursor_position_cfg position_cfg; 2242 }; 2243 2244 struct dmub_cmd_update_cursor_payload1 { 2245 struct dmub_cursor_attributes_cfg attribute_cfg; 2246 }; 2247 2248 union dmub_cmd_update_cursor_info_data { 2249 struct dmub_cmd_update_cursor_payload0 payload0; 2250 struct dmub_cmd_update_cursor_payload1 payload1; 2251 }; 2252 /** 2253 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2254 */ 2255 struct dmub_rb_cmd_update_cursor_info { 2256 /** 2257 * Command header. 2258 */ 2259 struct dmub_cmd_header header; 2260 /** 2261 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2262 */ 2263 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2264 }; 2265 2266 /** 2267 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2268 */ 2269 struct dmub_cmd_psr_set_vtotal_data { 2270 /** 2271 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2272 */ 2273 uint16_t psr_vtotal_idle; 2274 /** 2275 * PSR control version. 2276 */ 2277 uint8_t cmd_version; 2278 /** 2279 * Panel Instance. 2280 * Panel isntance to identify which psr_state to use 2281 * Currently the support is only for 0 or 1 2282 */ 2283 uint8_t panel_inst; 2284 /* 2285 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2286 */ 2287 uint16_t psr_vtotal_su; 2288 /** 2289 * Explicit padding to 4 byte boundary. 2290 */ 2291 uint8_t pad2[2]; 2292 }; 2293 2294 /** 2295 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2296 */ 2297 struct dmub_rb_cmd_psr_set_vtotal { 2298 /** 2299 * Command header. 2300 */ 2301 struct dmub_cmd_header header; 2302 /** 2303 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2304 */ 2305 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2306 }; 2307 2308 /** 2309 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2310 */ 2311 struct dmub_cmd_psr_set_power_opt_data { 2312 /** 2313 * PSR control version. 2314 */ 2315 uint8_t cmd_version; 2316 /** 2317 * Panel Instance. 2318 * Panel isntance to identify which psr_state to use 2319 * Currently the support is only for 0 or 1 2320 */ 2321 uint8_t panel_inst; 2322 /** 2323 * Explicit padding to 4 byte boundary. 2324 */ 2325 uint8_t pad[2]; 2326 /** 2327 * PSR power option 2328 */ 2329 uint32_t power_opt; 2330 }; 2331 2332 /** 2333 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2334 */ 2335 struct dmub_rb_cmd_psr_set_power_opt { 2336 /** 2337 * Command header. 2338 */ 2339 struct dmub_cmd_header header; 2340 /** 2341 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2342 */ 2343 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2344 }; 2345 2346 /** 2347 * Set of HW components that can be locked. 2348 * 2349 * Note: If updating with more HW components, fields 2350 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2351 */ 2352 union dmub_hw_lock_flags { 2353 /** 2354 * Set of HW components that can be locked. 2355 */ 2356 struct { 2357 /** 2358 * Lock/unlock OTG master update lock. 2359 */ 2360 uint8_t lock_pipe : 1; 2361 /** 2362 * Lock/unlock cursor. 2363 */ 2364 uint8_t lock_cursor : 1; 2365 /** 2366 * Lock/unlock global update lock. 2367 */ 2368 uint8_t lock_dig : 1; 2369 /** 2370 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2371 */ 2372 uint8_t triple_buffer_lock : 1; 2373 } bits; 2374 2375 /** 2376 * Union for HW Lock flags. 2377 */ 2378 uint8_t u8All; 2379 }; 2380 2381 /** 2382 * Instances of HW to be locked. 2383 * 2384 * Note: If updating with more HW components, fields 2385 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2386 */ 2387 struct dmub_hw_lock_inst_flags { 2388 /** 2389 * OTG HW instance for OTG master update lock. 2390 */ 2391 uint8_t otg_inst; 2392 /** 2393 * OPP instance for cursor lock. 2394 */ 2395 uint8_t opp_inst; 2396 /** 2397 * OTG HW instance for global update lock. 2398 * TODO: Remove, and re-use otg_inst. 2399 */ 2400 uint8_t dig_inst; 2401 /** 2402 * Explicit pad to 4 byte boundary. 2403 */ 2404 uint8_t pad; 2405 }; 2406 2407 /** 2408 * Clients that can acquire the HW Lock Manager. 2409 * 2410 * Note: If updating with more clients, fields in 2411 * dmub_inbox0_cmd_lock_hw must be updated to match. 2412 */ 2413 enum hw_lock_client { 2414 /** 2415 * Driver is the client of HW Lock Manager. 2416 */ 2417 HW_LOCK_CLIENT_DRIVER = 0, 2418 /** 2419 * PSR SU is the client of HW Lock Manager. 2420 */ 2421 HW_LOCK_CLIENT_PSR_SU = 1, 2422 /** 2423 * Invalid client. 2424 */ 2425 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2426 }; 2427 2428 /** 2429 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2430 */ 2431 struct dmub_cmd_lock_hw_data { 2432 /** 2433 * Specifies the client accessing HW Lock Manager. 2434 */ 2435 enum hw_lock_client client; 2436 /** 2437 * HW instances to be locked. 2438 */ 2439 struct dmub_hw_lock_inst_flags inst_flags; 2440 /** 2441 * Which components to be locked. 2442 */ 2443 union dmub_hw_lock_flags hw_locks; 2444 /** 2445 * Specifies lock/unlock. 2446 */ 2447 uint8_t lock; 2448 /** 2449 * HW can be unlocked separately from releasing the HW Lock Mgr. 2450 * This flag is set if the client wishes to release the object. 2451 */ 2452 uint8_t should_release; 2453 /** 2454 * Explicit padding to 4 byte boundary. 2455 */ 2456 uint8_t pad; 2457 }; 2458 2459 /** 2460 * Definition of a DMUB_CMD__HW_LOCK command. 2461 * Command is used by driver and FW. 2462 */ 2463 struct dmub_rb_cmd_lock_hw { 2464 /** 2465 * Command header. 2466 */ 2467 struct dmub_cmd_header header; 2468 /** 2469 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2470 */ 2471 struct dmub_cmd_lock_hw_data lock_hw_data; 2472 }; 2473 2474 /** 2475 * ABM command sub-types. 2476 */ 2477 enum dmub_cmd_abm_type { 2478 /** 2479 * Initialize parameters for ABM algorithm. 2480 * Data is passed through an indirect buffer. 2481 */ 2482 DMUB_CMD__ABM_INIT_CONFIG = 0, 2483 /** 2484 * Set OTG and panel HW instance. 2485 */ 2486 DMUB_CMD__ABM_SET_PIPE = 1, 2487 /** 2488 * Set user requested backklight level. 2489 */ 2490 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2491 /** 2492 * Set ABM operating/aggression level. 2493 */ 2494 DMUB_CMD__ABM_SET_LEVEL = 3, 2495 /** 2496 * Set ambient light level. 2497 */ 2498 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2499 /** 2500 * Enable/disable fractional duty cycle for backlight PWM. 2501 */ 2502 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2503 2504 /** 2505 * unregister vertical interrupt after steady state is reached 2506 */ 2507 DMUB_CMD__ABM_PAUSE = 6, 2508 }; 2509 2510 /** 2511 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2512 * Requirements: 2513 * - Padded explicitly to 32-bit boundary. 2514 * - Must ensure this structure matches the one on driver-side, 2515 * otherwise it won't be aligned. 2516 */ 2517 struct abm_config_table { 2518 /** 2519 * Gamma curve thresholds, used for crgb conversion. 2520 */ 2521 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2522 /** 2523 * Gamma curve offsets, used for crgb conversion. 2524 */ 2525 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2526 /** 2527 * Gamma curve slopes, used for crgb conversion. 2528 */ 2529 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2530 /** 2531 * Custom backlight curve thresholds. 2532 */ 2533 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2534 /** 2535 * Custom backlight curve offsets. 2536 */ 2537 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2538 /** 2539 * Ambient light thresholds. 2540 */ 2541 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2542 /** 2543 * Minimum programmable backlight. 2544 */ 2545 uint16_t min_abm_backlight; // 122B 2546 /** 2547 * Minimum reduction values. 2548 */ 2549 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2550 /** 2551 * Maximum reduction values. 2552 */ 2553 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2554 /** 2555 * Bright positive gain. 2556 */ 2557 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2558 /** 2559 * Dark negative gain. 2560 */ 2561 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2562 /** 2563 * Hybrid factor. 2564 */ 2565 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2566 /** 2567 * Contrast factor. 2568 */ 2569 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2570 /** 2571 * Deviation gain. 2572 */ 2573 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2574 /** 2575 * Minimum knee. 2576 */ 2577 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2578 /** 2579 * Maximum knee. 2580 */ 2581 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2582 /** 2583 * Unused. 2584 */ 2585 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2586 /** 2587 * Explicit padding to 4 byte boundary. 2588 */ 2589 uint8_t pad3[3]; // 229B 2590 /** 2591 * Backlight ramp reduction. 2592 */ 2593 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2594 /** 2595 * Backlight ramp start. 2596 */ 2597 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2598 }; 2599 2600 /** 2601 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2602 */ 2603 struct dmub_cmd_abm_set_pipe_data { 2604 /** 2605 * OTG HW instance. 2606 */ 2607 uint8_t otg_inst; 2608 2609 /** 2610 * Panel Control HW instance. 2611 */ 2612 uint8_t panel_inst; 2613 2614 /** 2615 * Controls how ABM will interpret a set pipe or set level command. 2616 */ 2617 uint8_t set_pipe_option; 2618 2619 /** 2620 * Unused. 2621 * TODO: Remove. 2622 */ 2623 uint8_t ramping_boundary; 2624 }; 2625 2626 /** 2627 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2628 */ 2629 struct dmub_rb_cmd_abm_set_pipe { 2630 /** 2631 * Command header. 2632 */ 2633 struct dmub_cmd_header header; 2634 2635 /** 2636 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2637 */ 2638 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2639 }; 2640 2641 /** 2642 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2643 */ 2644 struct dmub_cmd_abm_set_backlight_data { 2645 /** 2646 * Number of frames to ramp to backlight user level. 2647 */ 2648 uint32_t frame_ramp; 2649 2650 /** 2651 * Requested backlight level from user. 2652 */ 2653 uint32_t backlight_user_level; 2654 2655 /** 2656 * ABM control version. 2657 */ 2658 uint8_t version; 2659 2660 /** 2661 * Panel Control HW instance mask. 2662 * Bit 0 is Panel Control HW instance 0. 2663 * Bit 1 is Panel Control HW instance 1. 2664 */ 2665 uint8_t panel_mask; 2666 2667 /** 2668 * Explicit padding to 4 byte boundary. 2669 */ 2670 uint8_t pad[2]; 2671 }; 2672 2673 /** 2674 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2675 */ 2676 struct dmub_rb_cmd_abm_set_backlight { 2677 /** 2678 * Command header. 2679 */ 2680 struct dmub_cmd_header header; 2681 2682 /** 2683 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2684 */ 2685 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2686 }; 2687 2688 /** 2689 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2690 */ 2691 struct dmub_cmd_abm_set_level_data { 2692 /** 2693 * Set current ABM operating/aggression level. 2694 */ 2695 uint32_t level; 2696 2697 /** 2698 * ABM control version. 2699 */ 2700 uint8_t version; 2701 2702 /** 2703 * Panel Control HW instance mask. 2704 * Bit 0 is Panel Control HW instance 0. 2705 * Bit 1 is Panel Control HW instance 1. 2706 */ 2707 uint8_t panel_mask; 2708 2709 /** 2710 * Explicit padding to 4 byte boundary. 2711 */ 2712 uint8_t pad[2]; 2713 }; 2714 2715 /** 2716 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2717 */ 2718 struct dmub_rb_cmd_abm_set_level { 2719 /** 2720 * Command header. 2721 */ 2722 struct dmub_cmd_header header; 2723 2724 /** 2725 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2726 */ 2727 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2728 }; 2729 2730 /** 2731 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2732 */ 2733 struct dmub_cmd_abm_set_ambient_level_data { 2734 /** 2735 * Ambient light sensor reading from OS. 2736 */ 2737 uint32_t ambient_lux; 2738 2739 /** 2740 * ABM control version. 2741 */ 2742 uint8_t version; 2743 2744 /** 2745 * Panel Control HW instance mask. 2746 * Bit 0 is Panel Control HW instance 0. 2747 * Bit 1 is Panel Control HW instance 1. 2748 */ 2749 uint8_t panel_mask; 2750 2751 /** 2752 * Explicit padding to 4 byte boundary. 2753 */ 2754 uint8_t pad[2]; 2755 }; 2756 2757 /** 2758 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2759 */ 2760 struct dmub_rb_cmd_abm_set_ambient_level { 2761 /** 2762 * Command header. 2763 */ 2764 struct dmub_cmd_header header; 2765 2766 /** 2767 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2768 */ 2769 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2770 }; 2771 2772 /** 2773 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2774 */ 2775 struct dmub_cmd_abm_set_pwm_frac_data { 2776 /** 2777 * Enable/disable fractional duty cycle for backlight PWM. 2778 * TODO: Convert to uint8_t. 2779 */ 2780 uint32_t fractional_pwm; 2781 2782 /** 2783 * ABM control version. 2784 */ 2785 uint8_t version; 2786 2787 /** 2788 * Panel Control HW instance mask. 2789 * Bit 0 is Panel Control HW instance 0. 2790 * Bit 1 is Panel Control HW instance 1. 2791 */ 2792 uint8_t panel_mask; 2793 2794 /** 2795 * Explicit padding to 4 byte boundary. 2796 */ 2797 uint8_t pad[2]; 2798 }; 2799 2800 /** 2801 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2802 */ 2803 struct dmub_rb_cmd_abm_set_pwm_frac { 2804 /** 2805 * Command header. 2806 */ 2807 struct dmub_cmd_header header; 2808 2809 /** 2810 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2811 */ 2812 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2813 }; 2814 2815 /** 2816 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2817 */ 2818 struct dmub_cmd_abm_init_config_data { 2819 /** 2820 * Location of indirect buffer used to pass init data to ABM. 2821 */ 2822 union dmub_addr src; 2823 2824 /** 2825 * Indirect buffer length. 2826 */ 2827 uint16_t bytes; 2828 2829 2830 /** 2831 * ABM control version. 2832 */ 2833 uint8_t version; 2834 2835 /** 2836 * Panel Control HW instance mask. 2837 * Bit 0 is Panel Control HW instance 0. 2838 * Bit 1 is Panel Control HW instance 1. 2839 */ 2840 uint8_t panel_mask; 2841 2842 /** 2843 * Explicit padding to 4 byte boundary. 2844 */ 2845 uint8_t pad[2]; 2846 }; 2847 2848 /** 2849 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2850 */ 2851 struct dmub_rb_cmd_abm_init_config { 2852 /** 2853 * Command header. 2854 */ 2855 struct dmub_cmd_header header; 2856 2857 /** 2858 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2859 */ 2860 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2861 }; 2862 2863 /** 2864 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2865 */ 2866 2867 struct dmub_cmd_abm_pause_data { 2868 2869 /** 2870 * Panel Control HW instance mask. 2871 * Bit 0 is Panel Control HW instance 0. 2872 * Bit 1 is Panel Control HW instance 1. 2873 */ 2874 uint8_t panel_mask; 2875 2876 /** 2877 * OTG hw instance 2878 */ 2879 uint8_t otg_inst; 2880 2881 /** 2882 * Enable or disable ABM pause 2883 */ 2884 uint8_t enable; 2885 2886 /** 2887 * Explicit padding to 4 byte boundary. 2888 */ 2889 uint8_t pad[1]; 2890 }; 2891 2892 /** 2893 * Definition of a DMUB_CMD__ABM_PAUSE command. 2894 */ 2895 struct dmub_rb_cmd_abm_pause { 2896 /** 2897 * Command header. 2898 */ 2899 struct dmub_cmd_header header; 2900 2901 /** 2902 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2903 */ 2904 struct dmub_cmd_abm_pause_data abm_pause_data; 2905 }; 2906 2907 /** 2908 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2909 */ 2910 struct dmub_cmd_query_feature_caps_data { 2911 /** 2912 * DMUB feature capabilities. 2913 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2914 */ 2915 struct dmub_feature_caps feature_caps; 2916 }; 2917 2918 /** 2919 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2920 */ 2921 struct dmub_rb_cmd_query_feature_caps { 2922 /** 2923 * Command header. 2924 */ 2925 struct dmub_cmd_header header; 2926 /** 2927 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2928 */ 2929 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2930 }; 2931 2932 /** 2933 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2934 */ 2935 struct dmub_cmd_visual_confirm_color_data { 2936 /** 2937 * DMUB feature capabilities. 2938 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2939 */ 2940 struct dmub_visual_confirm_color visual_confirm_color; 2941 }; 2942 2943 /** 2944 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2945 */ 2946 struct dmub_rb_cmd_get_visual_confirm_color { 2947 /** 2948 * Command header. 2949 */ 2950 struct dmub_cmd_header header; 2951 /** 2952 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2953 */ 2954 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 2955 }; 2956 2957 struct dmub_optc_state { 2958 uint32_t v_total_max; 2959 uint32_t v_total_min; 2960 uint32_t tg_inst; 2961 }; 2962 2963 struct dmub_rb_cmd_drr_update { 2964 struct dmub_cmd_header header; 2965 struct dmub_optc_state dmub_optc_state_req; 2966 }; 2967 2968 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 2969 uint32_t pix_clk_100hz; 2970 uint8_t max_ramp_step; 2971 uint8_t pipes; 2972 uint8_t min_refresh_in_hz; 2973 uint8_t padding[1]; 2974 }; 2975 2976 struct dmub_cmd_fw_assisted_mclk_switch_config { 2977 uint8_t fams_enabled; 2978 uint8_t visual_confirm_enabled; 2979 uint8_t padding[2]; 2980 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 2981 }; 2982 2983 struct dmub_rb_cmd_fw_assisted_mclk_switch { 2984 struct dmub_cmd_header header; 2985 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 2986 }; 2987 2988 /** 2989 * enum dmub_cmd_panel_cntl_type - Panel control command. 2990 */ 2991 enum dmub_cmd_panel_cntl_type { 2992 /** 2993 * Initializes embedded panel hardware blocks. 2994 */ 2995 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2996 /** 2997 * Queries backlight info for the embedded panel. 2998 */ 2999 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3000 }; 3001 3002 /** 3003 * struct dmub_cmd_panel_cntl_data - Panel control data. 3004 */ 3005 struct dmub_cmd_panel_cntl_data { 3006 uint32_t inst; /**< panel instance */ 3007 uint32_t current_backlight; /* in/out */ 3008 uint32_t bl_pwm_cntl; /* in/out */ 3009 uint32_t bl_pwm_period_cntl; /* in/out */ 3010 uint32_t bl_pwm_ref_div1; /* in/out */ 3011 uint8_t is_backlight_on : 1; /* in/out */ 3012 uint8_t is_powered_on : 1; /* in/out */ 3013 uint8_t padding[3]; 3014 uint32_t bl_pwm_ref_div2; /* in/out */ 3015 uint8_t reserved[4]; 3016 }; 3017 3018 /** 3019 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3020 */ 3021 struct dmub_rb_cmd_panel_cntl { 3022 struct dmub_cmd_header header; /**< header */ 3023 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3024 }; 3025 3026 /** 3027 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3028 */ 3029 struct dmub_cmd_lvtma_control_data { 3030 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3031 uint8_t reserved_0[3]; /**< For future use */ 3032 uint8_t panel_inst; /**< LVTMA control instance */ 3033 uint8_t reserved_1[3]; /**< For future use */ 3034 }; 3035 3036 /** 3037 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3038 */ 3039 struct dmub_rb_cmd_lvtma_control { 3040 /** 3041 * Command header. 3042 */ 3043 struct dmub_cmd_header header; 3044 /** 3045 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3046 */ 3047 struct dmub_cmd_lvtma_control_data data; 3048 }; 3049 3050 /** 3051 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3052 */ 3053 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3054 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3055 uint8_t is_usb; /**< is phy is usb */ 3056 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3057 uint8_t is_dp4; /**< is dp in 4 lane */ 3058 }; 3059 3060 /** 3061 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3062 */ 3063 struct dmub_rb_cmd_transmitter_query_dp_alt { 3064 struct dmub_cmd_header header; /**< header */ 3065 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3066 }; 3067 3068 /** 3069 * Maximum number of bytes a chunk sent to DMUB for parsing 3070 */ 3071 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3072 3073 /** 3074 * Represent a chunk of CEA blocks sent to DMUB for parsing 3075 */ 3076 struct dmub_cmd_send_edid_cea { 3077 uint16_t offset; /**< offset into the CEA block */ 3078 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3079 uint16_t cea_total_length; /**< total length of the CEA block */ 3080 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3081 uint8_t pad[3]; /**< padding and for future expansion */ 3082 }; 3083 3084 /** 3085 * Result of VSDB parsing from CEA block 3086 */ 3087 struct dmub_cmd_edid_cea_amd_vsdb { 3088 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3089 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3090 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3091 uint16_t min_frame_rate; /**< Maximum frame rate */ 3092 uint16_t max_frame_rate; /**< Minimum frame rate */ 3093 }; 3094 3095 /** 3096 * Result of sending a CEA chunk 3097 */ 3098 struct dmub_cmd_edid_cea_ack { 3099 uint16_t offset; /**< offset of the chunk into the CEA block */ 3100 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3101 uint8_t pad; /**< padding and for future expansion */ 3102 }; 3103 3104 /** 3105 * Specify whether the result is an ACK/NACK or the parsing has finished 3106 */ 3107 enum dmub_cmd_edid_cea_reply_type { 3108 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3109 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3110 }; 3111 3112 /** 3113 * Definition of a DMUB_CMD__EDID_CEA command. 3114 */ 3115 struct dmub_rb_cmd_edid_cea { 3116 struct dmub_cmd_header header; /**< Command header */ 3117 union dmub_cmd_edid_cea_data { 3118 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3119 struct dmub_cmd_edid_cea_output { /**< output with results */ 3120 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3121 union { 3122 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3123 struct dmub_cmd_edid_cea_ack ack; 3124 }; 3125 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3126 } data; /**< Command data */ 3127 3128 }; 3129 3130 /** 3131 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3132 */ 3133 struct dmub_cmd_cable_id_input { 3134 uint8_t phy_inst; /**< phy inst for cable id data */ 3135 }; 3136 3137 /** 3138 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3139 */ 3140 struct dmub_cmd_cable_id_output { 3141 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3142 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3143 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3144 uint8_t RESERVED :2; /**< reserved means not defined */ 3145 }; 3146 3147 /** 3148 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3149 */ 3150 struct dmub_rb_cmd_get_usbc_cable_id { 3151 struct dmub_cmd_header header; /**< Command header */ 3152 /** 3153 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3154 */ 3155 union dmub_cmd_cable_id_data { 3156 struct dmub_cmd_cable_id_input input; /**< Input */ 3157 struct dmub_cmd_cable_id_output output; /**< Output */ 3158 uint8_t output_raw; /**< Raw data output */ 3159 } data; 3160 }; 3161 3162 /** 3163 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3164 */ 3165 enum dmub_cmd_secure_display_type { 3166 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3167 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3168 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3169 }; 3170 3171 /** 3172 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3173 */ 3174 struct dmub_rb_cmd_secure_display { 3175 struct dmub_cmd_header header; 3176 /** 3177 * Data passed from driver to dmub firmware. 3178 */ 3179 struct dmub_cmd_roi_info { 3180 uint16_t x_start; 3181 uint16_t x_end; 3182 uint16_t y_start; 3183 uint16_t y_end; 3184 uint8_t otg_id; 3185 uint8_t phy_id; 3186 } roi_info; 3187 }; 3188 3189 /** 3190 * union dmub_rb_cmd - DMUB inbox command. 3191 */ 3192 union dmub_rb_cmd { 3193 /** 3194 * Elements shared with all commands. 3195 */ 3196 struct dmub_rb_cmd_common cmd_common; 3197 /** 3198 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3199 */ 3200 struct dmub_rb_cmd_read_modify_write read_modify_write; 3201 /** 3202 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3203 */ 3204 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3205 /** 3206 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3207 */ 3208 struct dmub_rb_cmd_burst_write burst_write; 3209 /** 3210 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3211 */ 3212 struct dmub_rb_cmd_reg_wait reg_wait; 3213 /** 3214 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3215 */ 3216 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3217 /** 3218 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3219 */ 3220 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3221 /** 3222 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3223 */ 3224 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3225 /** 3226 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3227 */ 3228 struct dmub_rb_cmd_dpphy_init dpphy_init; 3229 /** 3230 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3231 */ 3232 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3233 /** 3234 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3235 */ 3236 struct dmub_rb_cmd_psr_set_version psr_set_version; 3237 /** 3238 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3239 */ 3240 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3241 /** 3242 * Definition of a DMUB_CMD__PSR_ENABLE command. 3243 */ 3244 struct dmub_rb_cmd_psr_enable psr_enable; 3245 /** 3246 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3247 */ 3248 struct dmub_rb_cmd_psr_set_level psr_set_level; 3249 /** 3250 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3251 */ 3252 struct dmub_rb_cmd_psr_force_static psr_force_static; 3253 /** 3254 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3255 */ 3256 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3257 /** 3258 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3259 */ 3260 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3261 /** 3262 * Definition of a DMUB_CMD__HW_LOCK command. 3263 * Command is used by driver and FW. 3264 */ 3265 struct dmub_rb_cmd_lock_hw lock_hw; 3266 /** 3267 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3268 */ 3269 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3270 /** 3271 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3272 */ 3273 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3274 /** 3275 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3276 */ 3277 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3278 /** 3279 * Definition of a DMUB_CMD__MALL command. 3280 */ 3281 struct dmub_rb_cmd_mall mall; 3282 /** 3283 * Definition of a DMUB_CMD__CAB command. 3284 */ 3285 struct dmub_rb_cmd_cab_for_ss cab; 3286 3287 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3288 3289 /** 3290 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3291 */ 3292 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3293 3294 /** 3295 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3296 */ 3297 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3298 3299 /** 3300 * Definition of DMUB_CMD__PANEL_CNTL commands. 3301 */ 3302 struct dmub_rb_cmd_panel_cntl panel_cntl; 3303 /** 3304 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3305 */ 3306 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3307 3308 /** 3309 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3310 */ 3311 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3312 3313 /** 3314 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3315 */ 3316 struct dmub_rb_cmd_abm_set_level abm_set_level; 3317 3318 /** 3319 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3320 */ 3321 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3322 3323 /** 3324 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3325 */ 3326 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3327 3328 /** 3329 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3330 */ 3331 struct dmub_rb_cmd_abm_init_config abm_init_config; 3332 3333 /** 3334 * Definition of a DMUB_CMD__ABM_PAUSE command. 3335 */ 3336 struct dmub_rb_cmd_abm_pause abm_pause; 3337 3338 /** 3339 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3340 */ 3341 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3342 3343 /** 3344 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3345 */ 3346 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3347 3348 /** 3349 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3350 */ 3351 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3352 3353 /** 3354 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3355 */ 3356 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3357 struct dmub_rb_cmd_drr_update drr_update; 3358 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3359 3360 /** 3361 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3362 */ 3363 struct dmub_rb_cmd_lvtma_control lvtma_control; 3364 /** 3365 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3366 */ 3367 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3368 /** 3369 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3370 */ 3371 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3372 /** 3373 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3374 */ 3375 struct dmub_rb_cmd_set_config_access set_config_access; 3376 /** 3377 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3378 */ 3379 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3380 /** 3381 * Definition of a DMUB_CMD__EDID_CEA command. 3382 */ 3383 struct dmub_rb_cmd_edid_cea edid_cea; 3384 /** 3385 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3386 */ 3387 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3388 3389 /** 3390 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3391 */ 3392 struct dmub_rb_cmd_query_hpd_state query_hpd; 3393 /** 3394 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3395 */ 3396 struct dmub_rb_cmd_secure_display secure_display; 3397 3398 /** 3399 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3400 */ 3401 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3402 }; 3403 3404 /** 3405 * union dmub_rb_out_cmd - Outbox command 3406 */ 3407 union dmub_rb_out_cmd { 3408 /** 3409 * Parameters common to every command. 3410 */ 3411 struct dmub_rb_cmd_common cmd_common; 3412 /** 3413 * AUX reply command. 3414 */ 3415 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3416 /** 3417 * HPD notify command. 3418 */ 3419 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3420 /** 3421 * SET_CONFIG reply command. 3422 */ 3423 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3424 }; 3425 #pragma pack(pop) 3426 3427 3428 //============================================================================== 3429 //</DMUB_CMD>=================================================================== 3430 //============================================================================== 3431 //< DMUB_RB>==================================================================== 3432 //============================================================================== 3433 3434 #if defined(__cplusplus) 3435 extern "C" { 3436 #endif 3437 3438 /** 3439 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3440 */ 3441 struct dmub_rb_init_params { 3442 void *ctx; /**< Caller provided context pointer */ 3443 void *base_address; /**< CPU base address for ring's data */ 3444 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3445 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3446 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3447 }; 3448 3449 /** 3450 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3451 */ 3452 struct dmub_rb { 3453 void *base_address; /**< CPU address for the ring's data */ 3454 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3455 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3456 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3457 3458 void *ctx; /**< Caller provided context pointer */ 3459 void *dmub; /**< Pointer to the DMUB interface */ 3460 }; 3461 3462 /** 3463 * @brief Checks if the ringbuffer is empty. 3464 * 3465 * @param rb DMUB Ringbuffer 3466 * @return true if empty 3467 * @return false otherwise 3468 */ 3469 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3470 { 3471 return (rb->wrpt == rb->rptr); 3472 } 3473 3474 /** 3475 * @brief Checks if the ringbuffer is full 3476 * 3477 * @param rb DMUB Ringbuffer 3478 * @return true if full 3479 * @return false otherwise 3480 */ 3481 static inline bool dmub_rb_full(struct dmub_rb *rb) 3482 { 3483 uint32_t data_count; 3484 3485 if (rb->wrpt >= rb->rptr) 3486 data_count = rb->wrpt - rb->rptr; 3487 else 3488 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3489 3490 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3491 } 3492 3493 /** 3494 * @brief Pushes a command into the ringbuffer 3495 * 3496 * @param rb DMUB ringbuffer 3497 * @param cmd The command to push 3498 * @return true if the ringbuffer was not full 3499 * @return false otherwise 3500 */ 3501 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3502 const union dmub_rb_cmd *cmd) 3503 { 3504 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3505 const uint64_t *src = (const uint64_t *)cmd; 3506 uint8_t i; 3507 3508 if (dmub_rb_full(rb)) 3509 return false; 3510 3511 // copying data 3512 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3513 *dst++ = *src++; 3514 3515 rb->wrpt += DMUB_RB_CMD_SIZE; 3516 3517 if (rb->wrpt >= rb->capacity) 3518 rb->wrpt %= rb->capacity; 3519 3520 return true; 3521 } 3522 3523 /** 3524 * @brief Pushes a command into the DMUB outbox ringbuffer 3525 * 3526 * @param rb DMUB outbox ringbuffer 3527 * @param cmd Outbox command 3528 * @return true if not full 3529 * @return false otherwise 3530 */ 3531 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3532 const union dmub_rb_out_cmd *cmd) 3533 { 3534 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3535 const uint8_t *src = (const uint8_t *)cmd; 3536 3537 if (dmub_rb_full(rb)) 3538 return false; 3539 3540 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3541 3542 rb->wrpt += DMUB_RB_CMD_SIZE; 3543 3544 if (rb->wrpt >= rb->capacity) 3545 rb->wrpt %= rb->capacity; 3546 3547 return true; 3548 } 3549 3550 /** 3551 * @brief Returns the next unprocessed command in the ringbuffer. 3552 * 3553 * @param rb DMUB ringbuffer 3554 * @param cmd The command to return 3555 * @return true if not empty 3556 * @return false otherwise 3557 */ 3558 static inline bool dmub_rb_front(struct dmub_rb *rb, 3559 union dmub_rb_cmd **cmd) 3560 { 3561 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3562 3563 if (dmub_rb_empty(rb)) 3564 return false; 3565 3566 *cmd = (union dmub_rb_cmd *)rb_cmd; 3567 3568 return true; 3569 } 3570 3571 /** 3572 * @brief Determines the next ringbuffer offset. 3573 * 3574 * @param rb DMUB inbox ringbuffer 3575 * @param num_cmds Number of commands 3576 * @param next_rptr The next offset in the ringbuffer 3577 */ 3578 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3579 uint32_t num_cmds, 3580 uint32_t *next_rptr) 3581 { 3582 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3583 3584 if (*next_rptr >= rb->capacity) 3585 *next_rptr %= rb->capacity; 3586 } 3587 3588 /** 3589 * @brief Returns a pointer to a command in the inbox. 3590 * 3591 * @param rb DMUB inbox ringbuffer 3592 * @param cmd The inbox command to return 3593 * @param rptr The ringbuffer offset 3594 * @return true if not empty 3595 * @return false otherwise 3596 */ 3597 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3598 union dmub_rb_cmd **cmd, 3599 uint32_t rptr) 3600 { 3601 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3602 3603 if (dmub_rb_empty(rb)) 3604 return false; 3605 3606 *cmd = (union dmub_rb_cmd *)rb_cmd; 3607 3608 return true; 3609 } 3610 3611 /** 3612 * @brief Returns the next unprocessed command in the outbox. 3613 * 3614 * @param rb DMUB outbox ringbuffer 3615 * @param cmd The outbox command to return 3616 * @return true if not empty 3617 * @return false otherwise 3618 */ 3619 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3620 union dmub_rb_out_cmd *cmd) 3621 { 3622 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3623 uint64_t *dst = (uint64_t *)cmd; 3624 uint8_t i; 3625 3626 if (dmub_rb_empty(rb)) 3627 return false; 3628 3629 // copying data 3630 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3631 *dst++ = *src++; 3632 3633 return true; 3634 } 3635 3636 /** 3637 * @brief Removes the front entry in the ringbuffer. 3638 * 3639 * @param rb DMUB ringbuffer 3640 * @return true if the command was removed 3641 * @return false if there were no commands 3642 */ 3643 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3644 { 3645 if (dmub_rb_empty(rb)) 3646 return false; 3647 3648 rb->rptr += DMUB_RB_CMD_SIZE; 3649 3650 if (rb->rptr >= rb->capacity) 3651 rb->rptr %= rb->capacity; 3652 3653 return true; 3654 } 3655 3656 /** 3657 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3658 * 3659 * Avoids a race condition where DMCUB accesses memory while 3660 * there are still writes in flight to framebuffer. 3661 * 3662 * @param rb DMUB ringbuffer 3663 */ 3664 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3665 { 3666 uint32_t rptr = rb->rptr; 3667 uint32_t wptr = rb->wrpt; 3668 3669 while (rptr != wptr) { 3670 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3671 uint8_t i; 3672 3673 /* Don't remove this. 3674 * The contents need to actually be read from the ring buffer 3675 * for this function to be effective. 3676 */ 3677 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3678 (void)READ_ONCE(*data++); 3679 3680 rptr += DMUB_RB_CMD_SIZE; 3681 if (rptr >= rb->capacity) 3682 rptr %= rb->capacity; 3683 } 3684 } 3685 3686 /** 3687 * @brief Initializes a DMCUB ringbuffer 3688 * 3689 * @param rb DMUB ringbuffer 3690 * @param init_params initial configuration for the ringbuffer 3691 */ 3692 static inline void dmub_rb_init(struct dmub_rb *rb, 3693 struct dmub_rb_init_params *init_params) 3694 { 3695 rb->base_address = init_params->base_address; 3696 rb->capacity = init_params->capacity; 3697 rb->rptr = init_params->read_ptr; 3698 rb->wrpt = init_params->write_ptr; 3699 } 3700 3701 /** 3702 * @brief Copies output data from in/out commands into the given command. 3703 * 3704 * @param rb DMUB ringbuffer 3705 * @param cmd Command to copy data into 3706 */ 3707 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3708 union dmub_rb_cmd *cmd) 3709 { 3710 // Copy rb entry back into command 3711 uint8_t *rd_ptr = (rb->rptr == 0) ? 3712 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3713 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3714 3715 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3716 } 3717 3718 #if defined(__cplusplus) 3719 } 3720 #endif 3721 3722 //============================================================================== 3723 //</DMUB_RB>==================================================================== 3724 //============================================================================== 3725 3726 #endif /* _DMUB_CMD_H_ */ 3727