1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Maximum number of streams on any ASIC. */ 99 #define DMUB_MAX_STREAMS 6 100 101 /* Maximum number of planes on any ASIC. */ 102 #define DMUB_MAX_PLANES 6 103 104 /* Trace buffer offset for entry */ 105 #define TRACE_BUFFER_ENTRY_OFFSET 16 106 107 /** 108 * Maximum number of dirty rects supported by FW. 109 */ 110 #define DMUB_MAX_DIRTY_RECTS 3 111 112 /** 113 * 114 * PSR control version legacy 115 */ 116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117 /** 118 * PSR control version with multi edp support 119 */ 120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121 122 123 /** 124 * ABM control version legacy 125 */ 126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127 128 /** 129 * ABM control version with multi edp support 130 */ 131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132 133 /** 134 * Physical framebuffer address location, 64-bit. 135 */ 136 #ifndef PHYSICAL_ADDRESS_LOC 137 #define PHYSICAL_ADDRESS_LOC union large_integer 138 #endif 139 140 /** 141 * OS/FW agnostic memcpy 142 */ 143 #ifndef dmub_memcpy 144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 145 #endif 146 147 /** 148 * OS/FW agnostic memset 149 */ 150 #ifndef dmub_memset 151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 152 #endif 153 154 #if defined(__cplusplus) 155 extern "C" { 156 #endif 157 158 /** 159 * OS/FW agnostic udelay 160 */ 161 #ifndef dmub_udelay 162 #define dmub_udelay(microseconds) udelay(microseconds) 163 #endif 164 165 /** 166 * union dmub_addr - DMUB physical/virtual 64-bit address. 167 */ 168 union dmub_addr { 169 struct { 170 uint32_t low_part; /**< Lower 32 bits */ 171 uint32_t high_part; /**< Upper 32 bits */ 172 } u; /*<< Low/high bit access */ 173 uint64_t quad_part; /*<< 64 bit address */ 174 }; 175 176 /** 177 * Dirty rect definition. 178 */ 179 struct dmub_rect { 180 /** 181 * Dirty rect x offset. 182 */ 183 uint32_t x; 184 185 /** 186 * Dirty rect y offset. 187 */ 188 uint32_t y; 189 190 /** 191 * Dirty rect width. 192 */ 193 uint32_t width; 194 195 /** 196 * Dirty rect height. 197 */ 198 uint32_t height; 199 }; 200 201 /** 202 * Flags that can be set by driver to change some PSR behaviour. 203 */ 204 union dmub_psr_debug_flags { 205 /** 206 * Debug flags. 207 */ 208 struct { 209 /** 210 * Enable visual confirm in FW. 211 */ 212 uint32_t visual_confirm : 1; 213 214 /** 215 * Force all selective updates to bw full frame updates. 216 */ 217 uint32_t force_full_frame_update : 1; 218 219 /** 220 * Use HW Lock Mgr object to do HW locking in FW. 221 */ 222 uint32_t use_hw_lock_mgr : 1; 223 224 /** 225 * Use TPS3 signal when restore main link. 226 */ 227 uint32_t force_wakeup_by_tps3 : 1; 228 } bitfields; 229 230 /** 231 * Union for debug flags. 232 */ 233 uint32_t u32All; 234 }; 235 236 /** 237 * DMUB feature capabilities. 238 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 239 */ 240 struct dmub_feature_caps { 241 /** 242 * Max PSR version supported by FW. 243 */ 244 uint8_t psr; 245 uint8_t fw_assisted_mclk_switch; 246 uint8_t reserved[6]; 247 }; 248 249 #if defined(__cplusplus) 250 } 251 #endif 252 253 //============================================================================== 254 //</DMUB_TYPES>================================================================= 255 //============================================================================== 256 //< DMUB_META>================================================================== 257 //============================================================================== 258 #pragma pack(push, 1) 259 260 /* Magic value for identifying dmub_fw_meta_info */ 261 #define DMUB_FW_META_MAGIC 0x444D5542 262 263 /* Offset from the end of the file to the dmub_fw_meta_info */ 264 #define DMUB_FW_META_OFFSET 0x24 265 266 /** 267 * struct dmub_fw_meta_info - metadata associated with fw binary 268 * 269 * NOTE: This should be considered a stable API. Fields should 270 * not be repurposed or reordered. New fields should be 271 * added instead to extend the structure. 272 * 273 * @magic_value: magic value identifying DMUB firmware meta info 274 * @fw_region_size: size of the firmware state region 275 * @trace_buffer_size: size of the tracebuffer region 276 * @fw_version: the firmware version information 277 * @dal_fw: 1 if the firmware is DAL 278 */ 279 struct dmub_fw_meta_info { 280 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 281 uint32_t fw_region_size; /**< size of the firmware state region */ 282 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 283 uint32_t fw_version; /**< the firmware version information */ 284 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 285 uint8_t reserved[3]; /**< padding bits */ 286 }; 287 288 /** 289 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 290 */ 291 union dmub_fw_meta { 292 struct dmub_fw_meta_info info; /**< metadata info */ 293 uint8_t reserved[64]; /**< padding bits */ 294 }; 295 296 #pragma pack(pop) 297 298 //============================================================================== 299 //< DMUB Trace Buffer>================================================================ 300 //============================================================================== 301 /** 302 * dmub_trace_code_t - firmware trace code, 32-bits 303 */ 304 typedef uint32_t dmub_trace_code_t; 305 306 /** 307 * struct dmcub_trace_buf_entry - Firmware trace entry 308 */ 309 struct dmcub_trace_buf_entry { 310 dmub_trace_code_t trace_code; /**< trace code for the event */ 311 uint32_t tick_count; /**< the tick count at time of trace */ 312 uint32_t param0; /**< trace defined parameter 0 */ 313 uint32_t param1; /**< trace defined parameter 1 */ 314 }; 315 316 //============================================================================== 317 //< DMUB_STATUS>================================================================ 318 //============================================================================== 319 320 /** 321 * DMCUB scratch registers can be used to determine firmware status. 322 * Current scratch register usage is as follows: 323 * 324 * SCRATCH0: FW Boot Status register 325 * SCRATCH5: LVTMA Status Register 326 * SCRATCH15: FW Boot Options register 327 */ 328 329 /** 330 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 331 */ 332 union dmub_fw_boot_status { 333 struct { 334 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 335 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 336 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 337 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 338 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 339 uint32_t reserved : 1; 340 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 341 342 } bits; /**< status bits */ 343 uint32_t all; /**< 32-bit access to status bits */ 344 }; 345 346 /** 347 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 348 */ 349 enum dmub_fw_boot_status_bit { 350 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 351 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 352 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 353 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 354 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 355 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 356 }; 357 358 /* Register bit definition for SCRATCH5 */ 359 union dmub_lvtma_status { 360 struct { 361 uint32_t psp_ok : 1; 362 uint32_t edp_on : 1; 363 uint32_t reserved : 30; 364 } bits; 365 uint32_t all; 366 }; 367 368 enum dmub_lvtma_status_bit { 369 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 370 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 371 }; 372 373 /** 374 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 375 */ 376 union dmub_fw_boot_options { 377 struct { 378 uint32_t pemu_env : 1; /**< 1 if PEMU */ 379 uint32_t fpga_env : 1; /**< 1 if FPGA */ 380 uint32_t optimized_init : 1; /**< 1 if optimized init */ 381 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 382 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 383 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 384 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 385 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 386 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 387 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 388 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 389 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 390 uint32_t power_optimization: 1; 391 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 392 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 393 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 394 395 uint32_t reserved : 17; /**< reserved */ 396 } bits; /**< boot bits */ 397 uint32_t all; /**< 32-bit access to bits */ 398 }; 399 400 enum dmub_fw_boot_options_bit { 401 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 402 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 403 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 404 }; 405 406 //============================================================================== 407 //</DMUB_STATUS>================================================================ 408 //============================================================================== 409 //< DMUB_VBIOS>================================================================= 410 //============================================================================== 411 412 /* 413 * enum dmub_cmd_vbios_type - VBIOS commands. 414 * 415 * Command IDs should be treated as stable ABI. 416 * Do not reuse or modify IDs. 417 */ 418 enum dmub_cmd_vbios_type { 419 /** 420 * Configures the DIG encoder. 421 */ 422 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 423 /** 424 * Controls the PHY. 425 */ 426 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 427 /** 428 * Sets the pixel clock/symbol clock. 429 */ 430 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 431 /** 432 * Enables or disables power gating. 433 */ 434 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 435 /** 436 * Controls embedded panels. 437 */ 438 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 439 /** 440 * Query DP alt status on a transmitter. 441 */ 442 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 443 }; 444 445 //============================================================================== 446 //</DMUB_VBIOS>================================================================= 447 //============================================================================== 448 //< DMUB_GPINT>================================================================= 449 //============================================================================== 450 451 /** 452 * The shifts and masks below may alternatively be used to format and read 453 * the command register bits. 454 */ 455 456 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 457 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 458 459 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 460 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 461 462 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 463 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 464 465 /** 466 * Command responses. 467 */ 468 469 /** 470 * Return response for DMUB_GPINT__STOP_FW command. 471 */ 472 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 473 474 /** 475 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 476 */ 477 union dmub_gpint_data_register { 478 struct { 479 uint32_t param : 16; /**< 16-bit parameter */ 480 uint32_t command_code : 12; /**< GPINT command */ 481 uint32_t status : 4; /**< Command status bit */ 482 } bits; /**< GPINT bit access */ 483 uint32_t all; /**< GPINT 32-bit access */ 484 }; 485 486 /* 487 * enum dmub_gpint_command - GPINT command to DMCUB FW 488 * 489 * Command IDs should be treated as stable ABI. 490 * Do not reuse or modify IDs. 491 */ 492 enum dmub_gpint_command { 493 /** 494 * Invalid command, ignored. 495 */ 496 DMUB_GPINT__INVALID_COMMAND = 0, 497 /** 498 * DESC: Queries the firmware version. 499 * RETURN: Firmware version. 500 */ 501 DMUB_GPINT__GET_FW_VERSION = 1, 502 /** 503 * DESC: Halts the firmware. 504 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 505 */ 506 DMUB_GPINT__STOP_FW = 2, 507 /** 508 * DESC: Get PSR state from FW. 509 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 510 */ 511 DMUB_GPINT__GET_PSR_STATE = 7, 512 /** 513 * DESC: Notifies DMCUB of the currently active streams. 514 * ARGS: Stream mask, 1 bit per active stream index. 515 */ 516 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 517 /** 518 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 519 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 520 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 521 * RETURN: PSR residency in milli-percent. 522 */ 523 DMUB_GPINT__PSR_RESIDENCY = 9, 524 525 /** 526 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 527 */ 528 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 529 }; 530 531 /** 532 * INBOX0 generic command definition 533 */ 534 union dmub_inbox0_cmd_common { 535 struct { 536 uint32_t command_code: 8; /**< INBOX0 command code */ 537 uint32_t param: 24; /**< 24-bit parameter */ 538 } bits; 539 uint32_t all; 540 }; 541 542 /** 543 * INBOX0 hw_lock command definition 544 */ 545 union dmub_inbox0_cmd_lock_hw { 546 struct { 547 uint32_t command_code: 8; 548 549 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 550 uint32_t hw_lock_client: 2; 551 552 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 553 uint32_t otg_inst: 3; 554 uint32_t opp_inst: 3; 555 uint32_t dig_inst: 3; 556 557 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 558 uint32_t lock_pipe: 1; 559 uint32_t lock_cursor: 1; 560 uint32_t lock_dig: 1; 561 uint32_t triple_buffer_lock: 1; 562 563 uint32_t lock: 1; /**< Lock */ 564 uint32_t should_release: 1; /**< Release */ 565 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 566 } bits; 567 uint32_t all; 568 }; 569 570 union dmub_inbox0_data_register { 571 union dmub_inbox0_cmd_common inbox0_cmd_common; 572 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 573 }; 574 575 enum dmub_inbox0_command { 576 /** 577 * DESC: Invalid command, ignored. 578 */ 579 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 580 /** 581 * DESC: Notification to acquire/release HW lock 582 * ARGS: 583 */ 584 DMUB_INBOX0_CMD__HW_LOCK = 1, 585 }; 586 //============================================================================== 587 //</DMUB_GPINT>================================================================= 588 //============================================================================== 589 //< DMUB_CMD>=================================================================== 590 //============================================================================== 591 592 /** 593 * Size in bytes of each DMUB command. 594 */ 595 #define DMUB_RB_CMD_SIZE 64 596 597 /** 598 * Maximum number of items in the DMUB ringbuffer. 599 */ 600 #define DMUB_RB_MAX_ENTRY 128 601 602 /** 603 * Ringbuffer size in bytes. 604 */ 605 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 606 607 /** 608 * REG_SET mask for reg offload. 609 */ 610 #define REG_SET_MASK 0xFFFF 611 612 /* 613 * enum dmub_cmd_type - DMUB inbox command. 614 * 615 * Command IDs should be treated as stable ABI. 616 * Do not reuse or modify IDs. 617 */ 618 enum dmub_cmd_type { 619 /** 620 * Invalid command. 621 */ 622 DMUB_CMD__NULL = 0, 623 /** 624 * Read modify write register sequence offload. 625 */ 626 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 627 /** 628 * Field update register sequence offload. 629 */ 630 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 631 /** 632 * Burst write sequence offload. 633 */ 634 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 635 /** 636 * Reg wait sequence offload. 637 */ 638 DMUB_CMD__REG_REG_WAIT = 4, 639 /** 640 * Workaround to avoid HUBP underflow during NV12 playback. 641 */ 642 DMUB_CMD__PLAT_54186_WA = 5, 643 /** 644 * Command type used to query FW feature caps. 645 */ 646 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 647 /** 648 * Command type used for all PSR commands. 649 */ 650 DMUB_CMD__PSR = 64, 651 /** 652 * Command type used for all MALL commands. 653 */ 654 DMUB_CMD__MALL = 65, 655 /** 656 * Command type used for all ABM commands. 657 */ 658 DMUB_CMD__ABM = 66, 659 /** 660 * Command type used to update dirty rects in FW. 661 */ 662 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 663 /** 664 * Command type used to update cursor info in FW. 665 */ 666 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 667 /** 668 * Command type used for HW locking in FW. 669 */ 670 DMUB_CMD__HW_LOCK = 69, 671 /** 672 * Command type used to access DP AUX. 673 */ 674 DMUB_CMD__DP_AUX_ACCESS = 70, 675 /** 676 * Command type used for OUTBOX1 notification enable 677 */ 678 DMUB_CMD__OUTBOX1_ENABLE = 71, 679 680 /** 681 * Command type used for all idle optimization commands. 682 */ 683 DMUB_CMD__IDLE_OPT = 72, 684 /** 685 * Command type used for all clock manager commands. 686 */ 687 DMUB_CMD__CLK_MGR = 73, 688 /** 689 * Command type used for all panel control commands. 690 */ 691 DMUB_CMD__PANEL_CNTL = 74, 692 /** 693 * Command type used for <TODO:description> 694 */ 695 DMUB_CMD__CAB_FOR_SS = 75, 696 697 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 698 699 /** 700 * Command type used for interfacing with DPIA. 701 */ 702 DMUB_CMD__DPIA = 77, 703 /** 704 * Command type used for EDID CEA parsing 705 */ 706 DMUB_CMD__EDID_CEA = 79, 707 /** 708 * Command type used for getting usbc cable ID 709 */ 710 DMUB_CMD_GET_USBC_CABLE_ID = 81, 711 /** 712 * Command type used to query HPD state. 713 */ 714 DMUB_CMD__QUERY_HPD_STATE = 82, 715 /** 716 * Command type used for all VBIOS interface commands. 717 */ 718 DMUB_CMD__VBIOS = 128, 719 }; 720 721 /** 722 * enum dmub_out_cmd_type - DMUB outbox commands. 723 */ 724 enum dmub_out_cmd_type { 725 /** 726 * Invalid outbox command, ignored. 727 */ 728 DMUB_OUT_CMD__NULL = 0, 729 /** 730 * Command type used for DP AUX Reply data notification 731 */ 732 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 733 /** 734 * Command type used for DP HPD event notification 735 */ 736 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 737 /** 738 * Command type used for SET_CONFIG Reply notification 739 */ 740 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 741 }; 742 743 /* DMUB_CMD__DPIA command sub-types. */ 744 enum dmub_cmd_dpia_type { 745 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 746 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 747 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 748 }; 749 750 #pragma pack(push, 1) 751 752 /** 753 * struct dmub_cmd_header - Common command header fields. 754 */ 755 struct dmub_cmd_header { 756 unsigned int type : 8; /**< command type */ 757 unsigned int sub_type : 8; /**< command sub type */ 758 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 759 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 760 unsigned int reserved0 : 6; /**< reserved bits */ 761 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 762 unsigned int reserved1 : 2; /**< reserved bits */ 763 }; 764 765 /* 766 * struct dmub_cmd_read_modify_write_sequence - Read modify write 767 * 768 * 60 payload bytes can hold up to 5 sets of read modify writes, 769 * each take 3 dwords. 770 * 771 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 772 * 773 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 774 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 775 */ 776 struct dmub_cmd_read_modify_write_sequence { 777 uint32_t addr; /**< register address */ 778 uint32_t modify_mask; /**< modify mask */ 779 uint32_t modify_value; /**< modify value */ 780 }; 781 782 /** 783 * Maximum number of ops in read modify write sequence. 784 */ 785 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 786 787 /** 788 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 789 */ 790 struct dmub_rb_cmd_read_modify_write { 791 struct dmub_cmd_header header; /**< command header */ 792 /** 793 * Read modify write sequence. 794 */ 795 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 796 }; 797 798 /* 799 * Update a register with specified masks and values sequeunce 800 * 801 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 802 * 803 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 804 * 805 * 806 * USE CASE: 807 * 1. auto-increment register where additional read would update pointer and produce wrong result 808 * 2. toggle a bit without read in the middle 809 */ 810 811 struct dmub_cmd_reg_field_update_sequence { 812 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 813 uint32_t modify_value; /**< value to update with */ 814 }; 815 816 /** 817 * Maximum number of ops in field update sequence. 818 */ 819 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 820 821 /** 822 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 823 */ 824 struct dmub_rb_cmd_reg_field_update_sequence { 825 struct dmub_cmd_header header; /**< command header */ 826 uint32_t addr; /**< register address */ 827 /** 828 * Field update sequence. 829 */ 830 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 831 }; 832 833 834 /** 835 * Maximum number of burst write values. 836 */ 837 #define DMUB_BURST_WRITE_VALUES__MAX 14 838 839 /* 840 * struct dmub_rb_cmd_burst_write - Burst write 841 * 842 * support use case such as writing out LUTs. 843 * 844 * 60 payload bytes can hold up to 14 values to write to given address 845 * 846 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 847 */ 848 struct dmub_rb_cmd_burst_write { 849 struct dmub_cmd_header header; /**< command header */ 850 uint32_t addr; /**< register start address */ 851 /** 852 * Burst write register values. 853 */ 854 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 855 }; 856 857 /** 858 * struct dmub_rb_cmd_common - Common command header 859 */ 860 struct dmub_rb_cmd_common { 861 struct dmub_cmd_header header; /**< command header */ 862 /** 863 * Padding to RB_CMD_SIZE 864 */ 865 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 866 }; 867 868 /** 869 * struct dmub_cmd_reg_wait_data - Register wait data 870 */ 871 struct dmub_cmd_reg_wait_data { 872 uint32_t addr; /**< Register address */ 873 uint32_t mask; /**< Mask for register bits */ 874 uint32_t condition_field_value; /**< Value to wait for */ 875 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 876 }; 877 878 /** 879 * struct dmub_rb_cmd_reg_wait - Register wait command 880 */ 881 struct dmub_rb_cmd_reg_wait { 882 struct dmub_cmd_header header; /**< Command header */ 883 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 884 }; 885 886 /** 887 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 888 * 889 * Reprograms surface parameters to avoid underflow. 890 */ 891 struct dmub_cmd_PLAT_54186_wa { 892 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 893 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 894 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 895 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 896 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 897 struct { 898 uint8_t hubp_inst : 4; /**< HUBP instance */ 899 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 900 uint8_t immediate :1; /**< Immediate flip */ 901 uint8_t vmid : 4; /**< VMID */ 902 uint8_t grph_stereo : 1; /**< 1 if stereo */ 903 uint32_t reserved : 21; /**< Reserved */ 904 } flip_params; /**< Pageflip parameters */ 905 uint32_t reserved[9]; /**< Reserved bits */ 906 }; 907 908 /** 909 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 910 */ 911 struct dmub_rb_cmd_PLAT_54186_wa { 912 struct dmub_cmd_header header; /**< Command header */ 913 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 914 }; 915 916 /** 917 * struct dmub_rb_cmd_mall - MALL command data. 918 */ 919 struct dmub_rb_cmd_mall { 920 struct dmub_cmd_header header; /**< Common command header */ 921 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 922 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 923 uint32_t tmr_delay; /**< Timer delay */ 924 uint32_t tmr_scale; /**< Timer scale */ 925 uint16_t cursor_width; /**< Cursor width in pixels */ 926 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 927 uint16_t cursor_height; /**< Cursor height in pixels */ 928 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 929 uint8_t debug_bits; /**< Debug bits */ 930 931 uint8_t reserved1; /**< Reserved bits */ 932 uint8_t reserved2; /**< Reserved bits */ 933 }; 934 935 /** 936 * enum dmub_cmd_cab_type - TODO: 937 */ 938 enum dmub_cmd_cab_type { 939 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 940 DMUB_CMD__CAB_NO_DCN_REQ = 1, 941 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 942 }; 943 944 /** 945 * struct dmub_rb_cmd_cab_for_ss - TODO: 946 */ 947 struct dmub_rb_cmd_cab_for_ss { 948 struct dmub_cmd_header header; 949 uint8_t cab_alloc_ways; /* total number of ways */ 950 uint8_t debug_bits; /* debug bits */ 951 }; 952 953 enum mclk_switch_mode { 954 NONE = 0, 955 FPO = 1, 956 SUBVP = 2, 957 VBLANK = 3, 958 }; 959 960 /* Per pipe struct which stores the MCLK switch mode 961 * data to be sent to DMUB. 962 * Named "v2" for now -- once FPO and SUBVP are fully merged 963 * the type name can be updated 964 */ 965 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 966 union { 967 struct { 968 uint32_t pix_clk_100hz; 969 uint16_t main_vblank_start; 970 uint16_t main_vblank_end; 971 uint16_t mall_region_lines; 972 uint16_t prefetch_lines; 973 uint16_t prefetch_to_mall_start_lines; 974 uint16_t processing_delay_lines; 975 uint16_t htotal; // required to calculate line time for multi-display cases 976 uint16_t vtotal; 977 uint8_t main_pipe_index; 978 uint8_t phantom_pipe_index; 979 uint8_t is_drr; 980 uint8_t padding; 981 } subvp_data; 982 983 struct { 984 uint32_t pix_clk_100hz; 985 uint16_t vblank_start; 986 uint16_t vblank_end; 987 uint16_t vstartup_start; 988 uint16_t vtotal; 989 uint16_t htotal; 990 uint8_t vblank_pipe_index; 991 uint8_t padding[2]; 992 struct { 993 uint8_t drr_in_use; 994 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 995 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 996 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 997 uint8_t use_ramping; // Use ramping or not 998 } drr_info; // DRR considered as part of SubVP + VBLANK case 999 } vblank_data; 1000 } pipe_config; 1001 1002 enum mclk_switch_mode mode; 1003 }; 1004 1005 /** 1006 * Config data for Sub-VP and FPO 1007 * Named "v2" for now -- once FPO and SUBVP are fully merged 1008 * the type name can be updated 1009 */ 1010 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1011 uint16_t watermark_a_cache; 1012 uint8_t vertical_int_margin_us; 1013 uint8_t pstate_allow_width_us; 1014 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1015 }; 1016 1017 /** 1018 * DMUB rb command definition for Sub-VP and FPO 1019 * Named "v2" for now -- once FPO and SUBVP are fully merged 1020 * the type name can be updated 1021 */ 1022 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1023 struct dmub_cmd_header header; 1024 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1025 }; 1026 1027 /** 1028 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1029 */ 1030 enum dmub_cmd_idle_opt_type { 1031 /** 1032 * DCN hardware restore. 1033 */ 1034 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1035 1036 /** 1037 * DCN hardware save. 1038 */ 1039 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1040 }; 1041 1042 /** 1043 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1044 */ 1045 struct dmub_rb_cmd_idle_opt_dcn_restore { 1046 struct dmub_cmd_header header; /**< header */ 1047 }; 1048 1049 /** 1050 * struct dmub_clocks - Clock update notification. 1051 */ 1052 struct dmub_clocks { 1053 uint32_t dispclk_khz; /**< dispclk kHz */ 1054 uint32_t dppclk_khz; /**< dppclk kHz */ 1055 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1056 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1057 }; 1058 1059 /** 1060 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1061 */ 1062 enum dmub_cmd_clk_mgr_type { 1063 /** 1064 * Notify DMCUB of clock update. 1065 */ 1066 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1067 }; 1068 1069 /** 1070 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1071 */ 1072 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1073 struct dmub_cmd_header header; /**< header */ 1074 struct dmub_clocks clocks; /**< clock data */ 1075 }; 1076 1077 /** 1078 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1079 */ 1080 struct dmub_cmd_digx_encoder_control_data { 1081 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1082 }; 1083 1084 /** 1085 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1086 */ 1087 struct dmub_rb_cmd_digx_encoder_control { 1088 struct dmub_cmd_header header; /**< header */ 1089 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1090 }; 1091 1092 /** 1093 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1094 */ 1095 struct dmub_cmd_set_pixel_clock_data { 1096 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1097 }; 1098 1099 /** 1100 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1101 */ 1102 struct dmub_rb_cmd_set_pixel_clock { 1103 struct dmub_cmd_header header; /**< header */ 1104 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1105 }; 1106 1107 /** 1108 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1109 */ 1110 struct dmub_cmd_enable_disp_power_gating_data { 1111 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1112 }; 1113 1114 /** 1115 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1116 */ 1117 struct dmub_rb_cmd_enable_disp_power_gating { 1118 struct dmub_cmd_header header; /**< header */ 1119 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1120 }; 1121 1122 /** 1123 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1124 */ 1125 struct dmub_dig_transmitter_control_data_v1_7 { 1126 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1127 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1128 union { 1129 uint8_t digmode; /**< enum atom_encode_mode_def */ 1130 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1131 } mode_laneset; 1132 uint8_t lanenum; /**< Number of lanes */ 1133 union { 1134 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1135 } symclk_units; 1136 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1137 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1138 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1139 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1140 uint8_t reserved1; /**< For future use */ 1141 uint8_t reserved2[3]; /**< For future use */ 1142 uint32_t reserved3[11]; /**< For future use */ 1143 }; 1144 1145 /** 1146 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1147 */ 1148 union dmub_cmd_dig1_transmitter_control_data { 1149 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1150 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1151 }; 1152 1153 /** 1154 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1155 */ 1156 struct dmub_rb_cmd_dig1_transmitter_control { 1157 struct dmub_cmd_header header; /**< header */ 1158 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1159 }; 1160 1161 /** 1162 * DPIA tunnel command parameters. 1163 */ 1164 struct dmub_cmd_dig_dpia_control_data { 1165 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1166 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1167 union { 1168 uint8_t digmode; /** enum atom_encode_mode_def */ 1169 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1170 } mode_laneset; 1171 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1172 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1173 uint8_t hpdsel; /** =0: HPD is not assigned */ 1174 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1175 uint8_t dpia_id; /** Index of DPIA */ 1176 uint8_t fec_rdy : 1; 1177 uint8_t reserved : 7; 1178 uint32_t reserved1; 1179 }; 1180 1181 /** 1182 * DMUB command for DPIA tunnel control. 1183 */ 1184 struct dmub_rb_cmd_dig1_dpia_control { 1185 struct dmub_cmd_header header; 1186 struct dmub_cmd_dig_dpia_control_data dpia_control; 1187 }; 1188 1189 /** 1190 * SET_CONFIG Command Payload 1191 */ 1192 struct set_config_cmd_payload { 1193 uint8_t msg_type; /* set config message type */ 1194 uint8_t msg_data; /* set config message data */ 1195 }; 1196 1197 /** 1198 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1199 */ 1200 struct dmub_cmd_set_config_control_data { 1201 struct set_config_cmd_payload cmd_pkt; 1202 uint8_t instance; /* DPIA instance */ 1203 uint8_t immed_status; /* Immediate status returned in case of error */ 1204 }; 1205 1206 /** 1207 * DMUB command structure for SET_CONFIG command. 1208 */ 1209 struct dmub_rb_cmd_set_config_access { 1210 struct dmub_cmd_header header; /* header */ 1211 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1212 }; 1213 1214 /** 1215 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1216 */ 1217 struct dmub_cmd_mst_alloc_slots_control_data { 1218 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1219 uint8_t instance; /* DPIA instance */ 1220 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1221 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1222 }; 1223 1224 /** 1225 * DMUB command structure for SET_ command. 1226 */ 1227 struct dmub_rb_cmd_set_mst_alloc_slots { 1228 struct dmub_cmd_header header; /* header */ 1229 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1230 }; 1231 1232 /** 1233 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1234 */ 1235 struct dmub_rb_cmd_dpphy_init { 1236 struct dmub_cmd_header header; /**< header */ 1237 uint8_t reserved[60]; /**< reserved bits */ 1238 }; 1239 1240 /** 1241 * enum dp_aux_request_action - DP AUX request command listing. 1242 * 1243 * 4 AUX request command bits are shifted to high nibble. 1244 */ 1245 enum dp_aux_request_action { 1246 /** I2C-over-AUX write request */ 1247 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1248 /** I2C-over-AUX read request */ 1249 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1250 /** I2C-over-AUX write status request */ 1251 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1252 /** I2C-over-AUX write request with MOT=1 */ 1253 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1254 /** I2C-over-AUX read request with MOT=1 */ 1255 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1256 /** I2C-over-AUX write status request with MOT=1 */ 1257 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1258 /** Native AUX write request */ 1259 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1260 /** Native AUX read request */ 1261 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1262 }; 1263 1264 /** 1265 * enum aux_return_code_type - DP AUX process return code listing. 1266 */ 1267 enum aux_return_code_type { 1268 /** AUX process succeeded */ 1269 AUX_RET_SUCCESS = 0, 1270 /** AUX process failed with unknown reason */ 1271 AUX_RET_ERROR_UNKNOWN, 1272 /** AUX process completed with invalid reply */ 1273 AUX_RET_ERROR_INVALID_REPLY, 1274 /** AUX process timed out */ 1275 AUX_RET_ERROR_TIMEOUT, 1276 /** HPD was low during AUX process */ 1277 AUX_RET_ERROR_HPD_DISCON, 1278 /** Failed to acquire AUX engine */ 1279 AUX_RET_ERROR_ENGINE_ACQUIRE, 1280 /** AUX request not supported */ 1281 AUX_RET_ERROR_INVALID_OPERATION, 1282 /** AUX process not available */ 1283 AUX_RET_ERROR_PROTOCOL_ERROR, 1284 }; 1285 1286 /** 1287 * enum aux_channel_type - DP AUX channel type listing. 1288 */ 1289 enum aux_channel_type { 1290 /** AUX thru Legacy DP AUX */ 1291 AUX_CHANNEL_LEGACY_DDC, 1292 /** AUX thru DPIA DP tunneling */ 1293 AUX_CHANNEL_DPIA 1294 }; 1295 1296 /** 1297 * struct aux_transaction_parameters - DP AUX request transaction data 1298 */ 1299 struct aux_transaction_parameters { 1300 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1301 uint8_t action; /**< enum dp_aux_request_action */ 1302 uint8_t length; /**< DP AUX request data length */ 1303 uint8_t reserved; /**< For future use */ 1304 uint32_t address; /**< DP AUX address */ 1305 uint8_t data[16]; /**< DP AUX write data */ 1306 }; 1307 1308 /** 1309 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1310 */ 1311 struct dmub_cmd_dp_aux_control_data { 1312 uint8_t instance; /**< AUX instance or DPIA instance */ 1313 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1314 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1315 uint8_t reserved0; /**< For future use */ 1316 uint16_t timeout; /**< timeout time in us */ 1317 uint16_t reserved1; /**< For future use */ 1318 enum aux_channel_type type; /**< enum aux_channel_type */ 1319 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1320 }; 1321 1322 /** 1323 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1324 */ 1325 struct dmub_rb_cmd_dp_aux_access { 1326 /** 1327 * Command header. 1328 */ 1329 struct dmub_cmd_header header; 1330 /** 1331 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1332 */ 1333 struct dmub_cmd_dp_aux_control_data aux_control; 1334 }; 1335 1336 /** 1337 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1338 */ 1339 struct dmub_rb_cmd_outbox1_enable { 1340 /** 1341 * Command header. 1342 */ 1343 struct dmub_cmd_header header; 1344 /** 1345 * enable: 0x0 -> disable outbox1 notification (default value) 1346 * 0x1 -> enable outbox1 notification 1347 */ 1348 uint32_t enable; 1349 }; 1350 1351 /* DP AUX Reply command - OutBox Cmd */ 1352 /** 1353 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1354 */ 1355 struct aux_reply_data { 1356 /** 1357 * Aux cmd 1358 */ 1359 uint8_t command; 1360 /** 1361 * Aux reply data length (max: 16 bytes) 1362 */ 1363 uint8_t length; 1364 /** 1365 * Alignment only 1366 */ 1367 uint8_t pad[2]; 1368 /** 1369 * Aux reply data 1370 */ 1371 uint8_t data[16]; 1372 }; 1373 1374 /** 1375 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1376 */ 1377 struct aux_reply_control_data { 1378 /** 1379 * Reserved for future use 1380 */ 1381 uint32_t handle; 1382 /** 1383 * Aux Instance 1384 */ 1385 uint8_t instance; 1386 /** 1387 * Aux transaction result: definition in enum aux_return_code_type 1388 */ 1389 uint8_t result; 1390 /** 1391 * Alignment only 1392 */ 1393 uint16_t pad; 1394 }; 1395 1396 /** 1397 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1398 */ 1399 struct dmub_rb_cmd_dp_aux_reply { 1400 /** 1401 * Command header. 1402 */ 1403 struct dmub_cmd_header header; 1404 /** 1405 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1406 */ 1407 struct aux_reply_control_data control; 1408 /** 1409 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1410 */ 1411 struct aux_reply_data reply_data; 1412 }; 1413 1414 /* DP HPD Notify command - OutBox Cmd */ 1415 /** 1416 * DP HPD Type 1417 */ 1418 enum dp_hpd_type { 1419 /** 1420 * Normal DP HPD 1421 */ 1422 DP_HPD = 0, 1423 /** 1424 * DP HPD short pulse 1425 */ 1426 DP_IRQ 1427 }; 1428 1429 /** 1430 * DP HPD Status 1431 */ 1432 enum dp_hpd_status { 1433 /** 1434 * DP_HPD status low 1435 */ 1436 DP_HPD_UNPLUG = 0, 1437 /** 1438 * DP_HPD status high 1439 */ 1440 DP_HPD_PLUG 1441 }; 1442 1443 /** 1444 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1445 */ 1446 struct dp_hpd_data { 1447 /** 1448 * DP HPD instance 1449 */ 1450 uint8_t instance; 1451 /** 1452 * HPD type 1453 */ 1454 uint8_t hpd_type; 1455 /** 1456 * HPD status: only for type: DP_HPD to indicate status 1457 */ 1458 uint8_t hpd_status; 1459 /** 1460 * Alignment only 1461 */ 1462 uint8_t pad; 1463 }; 1464 1465 /** 1466 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1467 */ 1468 struct dmub_rb_cmd_dp_hpd_notify { 1469 /** 1470 * Command header. 1471 */ 1472 struct dmub_cmd_header header; 1473 /** 1474 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1475 */ 1476 struct dp_hpd_data hpd_data; 1477 }; 1478 1479 /** 1480 * Definition of a SET_CONFIG reply from DPOA. 1481 */ 1482 enum set_config_status { 1483 SET_CONFIG_PENDING = 0, 1484 SET_CONFIG_ACK_RECEIVED, 1485 SET_CONFIG_RX_TIMEOUT, 1486 SET_CONFIG_UNKNOWN_ERROR, 1487 }; 1488 1489 /** 1490 * Definition of a set_config reply 1491 */ 1492 struct set_config_reply_control_data { 1493 uint8_t instance; /* DPIA Instance */ 1494 uint8_t status; /* Set Config reply */ 1495 uint16_t pad; /* Alignment */ 1496 }; 1497 1498 /** 1499 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1500 */ 1501 struct dmub_rb_cmd_dp_set_config_reply { 1502 struct dmub_cmd_header header; 1503 struct set_config_reply_control_data set_config_reply_control; 1504 }; 1505 1506 /** 1507 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1508 */ 1509 struct dmub_cmd_hpd_state_query_data { 1510 uint8_t instance; /**< HPD instance or DPIA instance */ 1511 uint8_t result; /**< For returning HPD state */ 1512 uint16_t pad; /** < Alignment */ 1513 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1514 enum aux_return_code_type status; /**< for returning the status of command */ 1515 }; 1516 1517 /** 1518 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1519 */ 1520 struct dmub_rb_cmd_query_hpd_state { 1521 /** 1522 * Command header. 1523 */ 1524 struct dmub_cmd_header header; 1525 /** 1526 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1527 */ 1528 struct dmub_cmd_hpd_state_query_data data; 1529 }; 1530 1531 /* 1532 * Command IDs should be treated as stable ABI. 1533 * Do not reuse or modify IDs. 1534 */ 1535 1536 /** 1537 * PSR command sub-types. 1538 */ 1539 enum dmub_cmd_psr_type { 1540 /** 1541 * Set PSR version support. 1542 */ 1543 DMUB_CMD__PSR_SET_VERSION = 0, 1544 /** 1545 * Copy driver-calculated parameters to PSR state. 1546 */ 1547 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1548 /** 1549 * Enable PSR. 1550 */ 1551 DMUB_CMD__PSR_ENABLE = 2, 1552 1553 /** 1554 * Disable PSR. 1555 */ 1556 DMUB_CMD__PSR_DISABLE = 3, 1557 1558 /** 1559 * Set PSR level. 1560 * PSR level is a 16-bit value dicated by driver that 1561 * will enable/disable different functionality. 1562 */ 1563 DMUB_CMD__PSR_SET_LEVEL = 4, 1564 1565 /** 1566 * Forces PSR enabled until an explicit PSR disable call. 1567 */ 1568 DMUB_CMD__PSR_FORCE_STATIC = 5, 1569 /** 1570 * Set vtotal in psr active for FreeSync PSR. 1571 */ 1572 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1573 /** 1574 * Set PSR power option 1575 */ 1576 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1577 }; 1578 1579 enum dmub_cmd_fams_type { 1580 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1581 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1582 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1583 /** 1584 * For SubVP set manual trigger in FW because it 1585 * triggers DRR_UPDATE_PENDING which SubVP relies 1586 * on (for any SubVP cases that use a DRR display) 1587 */ 1588 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1589 }; 1590 1591 /** 1592 * PSR versions. 1593 */ 1594 enum psr_version { 1595 /** 1596 * PSR version 1. 1597 */ 1598 PSR_VERSION_1 = 0, 1599 /** 1600 * Freesync PSR SU. 1601 */ 1602 PSR_VERSION_SU_1 = 1, 1603 /** 1604 * PSR not supported. 1605 */ 1606 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1607 }; 1608 1609 /** 1610 * enum dmub_cmd_mall_type - MALL commands 1611 */ 1612 enum dmub_cmd_mall_type { 1613 /** 1614 * Allows display refresh from MALL. 1615 */ 1616 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1617 /** 1618 * Disallows display refresh from MALL. 1619 */ 1620 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1621 /** 1622 * Cursor copy for MALL. 1623 */ 1624 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1625 /** 1626 * Controls DF requests. 1627 */ 1628 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1629 }; 1630 1631 /** 1632 * PHY Link rate for DP. 1633 */ 1634 enum phy_link_rate { 1635 /** 1636 * not supported. 1637 */ 1638 PHY_RATE_UNKNOWN = 0, 1639 /** 1640 * Rate_1 (RBR) - 1.62 Gbps/Lane 1641 */ 1642 PHY_RATE_162 = 1, 1643 /** 1644 * Rate_2 - 2.16 Gbps/Lane 1645 */ 1646 PHY_RATE_216 = 2, 1647 /** 1648 * Rate_3 - 2.43 Gbps/Lane 1649 */ 1650 PHY_RATE_243 = 3, 1651 /** 1652 * Rate_4 (HBR) - 2.70 Gbps/Lane 1653 */ 1654 PHY_RATE_270 = 4, 1655 /** 1656 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1657 */ 1658 PHY_RATE_324 = 5, 1659 /** 1660 * Rate_6 - 4.32 Gbps/Lane 1661 */ 1662 PHY_RATE_432 = 6, 1663 /** 1664 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1665 */ 1666 PHY_RATE_540 = 7, 1667 /** 1668 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1669 */ 1670 PHY_RATE_810 = 8, 1671 /** 1672 * UHBR10 - 10.0 Gbps/Lane 1673 */ 1674 PHY_RATE_1000 = 9, 1675 /** 1676 * UHBR13.5 - 13.5 Gbps/Lane 1677 */ 1678 PHY_RATE_1350 = 10, 1679 /** 1680 * UHBR10 - 20.0 Gbps/Lane 1681 */ 1682 PHY_RATE_2000 = 11, 1683 }; 1684 1685 /** 1686 * enum dmub_phy_fsm_state - PHY FSM states. 1687 * PHY FSM state to transit to during PSR enable/disable. 1688 */ 1689 enum dmub_phy_fsm_state { 1690 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1691 DMUB_PHY_FSM_RESET, 1692 DMUB_PHY_FSM_RESET_RELEASED, 1693 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1694 DMUB_PHY_FSM_INITIALIZED, 1695 DMUB_PHY_FSM_CALIBRATED, 1696 DMUB_PHY_FSM_CALIBRATED_LP, 1697 DMUB_PHY_FSM_CALIBRATED_PG, 1698 DMUB_PHY_FSM_POWER_DOWN, 1699 DMUB_PHY_FSM_PLL_EN, 1700 DMUB_PHY_FSM_TX_EN, 1701 DMUB_PHY_FSM_FAST_LP, 1702 }; 1703 1704 /** 1705 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1706 */ 1707 struct dmub_cmd_psr_copy_settings_data { 1708 /** 1709 * Flags that can be set by driver to change some PSR behaviour. 1710 */ 1711 union dmub_psr_debug_flags debug; 1712 /** 1713 * 16-bit value dicated by driver that will enable/disable different functionality. 1714 */ 1715 uint16_t psr_level; 1716 /** 1717 * DPP HW instance. 1718 */ 1719 uint8_t dpp_inst; 1720 /** 1721 * MPCC HW instance. 1722 * Not used in dmub fw, 1723 * dmub fw will get active opp by reading odm registers. 1724 */ 1725 uint8_t mpcc_inst; 1726 /** 1727 * OPP HW instance. 1728 * Not used in dmub fw, 1729 * dmub fw will get active opp by reading odm registers. 1730 */ 1731 uint8_t opp_inst; 1732 /** 1733 * OTG HW instance. 1734 */ 1735 uint8_t otg_inst; 1736 /** 1737 * DIG FE HW instance. 1738 */ 1739 uint8_t digfe_inst; 1740 /** 1741 * DIG BE HW instance. 1742 */ 1743 uint8_t digbe_inst; 1744 /** 1745 * DP PHY HW instance. 1746 */ 1747 uint8_t dpphy_inst; 1748 /** 1749 * AUX HW instance. 1750 */ 1751 uint8_t aux_inst; 1752 /** 1753 * Determines if SMU optimzations are enabled/disabled. 1754 */ 1755 uint8_t smu_optimizations_en; 1756 /** 1757 * Unused. 1758 * TODO: Remove. 1759 */ 1760 uint8_t frame_delay; 1761 /** 1762 * If RFB setup time is greater than the total VBLANK time, 1763 * it is not possible for the sink to capture the video frame 1764 * in the same frame the SDP is sent. In this case, 1765 * the frame capture indication bit should be set and an extra 1766 * static frame should be transmitted to the sink. 1767 */ 1768 uint8_t frame_cap_ind; 1769 /** 1770 * Granularity of Y offset supported by sink. 1771 */ 1772 uint8_t su_y_granularity; 1773 /** 1774 * Indicates whether sink should start capturing 1775 * immediately following active scan line, 1776 * or starting with the 2nd active scan line. 1777 */ 1778 uint8_t line_capture_indication; 1779 /** 1780 * Multi-display optimizations are implemented on certain ASICs. 1781 */ 1782 uint8_t multi_disp_optimizations_en; 1783 /** 1784 * The last possible line SDP may be transmitted without violating 1785 * the RFB setup time or entering the active video frame. 1786 */ 1787 uint16_t init_sdp_deadline; 1788 /** 1789 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1790 */ 1791 uint8_t rate_control_caps ; 1792 /* 1793 * Force PSRSU always doing full frame update 1794 */ 1795 uint8_t force_ffu_mode; 1796 /** 1797 * Length of each horizontal line in us. 1798 */ 1799 uint32_t line_time_in_us; 1800 /** 1801 * FEC enable status in driver 1802 */ 1803 uint8_t fec_enable_status; 1804 /** 1805 * FEC re-enable delay when PSR exit. 1806 * unit is 100us, range form 0~255(0xFF). 1807 */ 1808 uint8_t fec_enable_delay_in100us; 1809 /** 1810 * PSR control version. 1811 */ 1812 uint8_t cmd_version; 1813 /** 1814 * Panel Instance. 1815 * Panel isntance to identify which psr_state to use 1816 * Currently the support is only for 0 or 1 1817 */ 1818 uint8_t panel_inst; 1819 /* 1820 * DSC enable status in driver 1821 */ 1822 uint8_t dsc_enable_status; 1823 /* 1824 * Use FSM state for PSR power up/down 1825 */ 1826 uint8_t use_phy_fsm; 1827 /** 1828 * Explicit padding to 2 byte boundary. 1829 */ 1830 uint8_t pad3[2]; 1831 }; 1832 1833 /** 1834 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1835 */ 1836 struct dmub_rb_cmd_psr_copy_settings { 1837 /** 1838 * Command header. 1839 */ 1840 struct dmub_cmd_header header; 1841 /** 1842 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1843 */ 1844 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1845 }; 1846 1847 /** 1848 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1849 */ 1850 struct dmub_cmd_psr_set_level_data { 1851 /** 1852 * 16-bit value dicated by driver that will enable/disable different functionality. 1853 */ 1854 uint16_t psr_level; 1855 /** 1856 * PSR control version. 1857 */ 1858 uint8_t cmd_version; 1859 /** 1860 * Panel Instance. 1861 * Panel isntance to identify which psr_state to use 1862 * Currently the support is only for 0 or 1 1863 */ 1864 uint8_t panel_inst; 1865 }; 1866 1867 /** 1868 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1869 */ 1870 struct dmub_rb_cmd_psr_set_level { 1871 /** 1872 * Command header. 1873 */ 1874 struct dmub_cmd_header header; 1875 /** 1876 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1877 */ 1878 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1879 }; 1880 1881 struct dmub_rb_cmd_psr_enable_data { 1882 /** 1883 * PSR control version. 1884 */ 1885 uint8_t cmd_version; 1886 /** 1887 * Panel Instance. 1888 * Panel isntance to identify which psr_state to use 1889 * Currently the support is only for 0 or 1 1890 */ 1891 uint8_t panel_inst; 1892 /** 1893 * Phy state to enter. 1894 * Values to use are defined in dmub_phy_fsm_state 1895 */ 1896 uint8_t phy_fsm_state; 1897 /** 1898 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1899 * Set this using enum phy_link_rate. 1900 * This does not support HDMI/DP2 for now. 1901 */ 1902 uint8_t phy_rate; 1903 }; 1904 1905 /** 1906 * Definition of a DMUB_CMD__PSR_ENABLE command. 1907 * PSR enable/disable is controlled using the sub_type. 1908 */ 1909 struct dmub_rb_cmd_psr_enable { 1910 /** 1911 * Command header. 1912 */ 1913 struct dmub_cmd_header header; 1914 1915 struct dmub_rb_cmd_psr_enable_data data; 1916 }; 1917 1918 /** 1919 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1920 */ 1921 struct dmub_cmd_psr_set_version_data { 1922 /** 1923 * PSR version that FW should implement. 1924 */ 1925 enum psr_version version; 1926 /** 1927 * PSR control version. 1928 */ 1929 uint8_t cmd_version; 1930 /** 1931 * Panel Instance. 1932 * Panel isntance to identify which psr_state to use 1933 * Currently the support is only for 0 or 1 1934 */ 1935 uint8_t panel_inst; 1936 /** 1937 * Explicit padding to 4 byte boundary. 1938 */ 1939 uint8_t pad[2]; 1940 }; 1941 1942 /** 1943 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1944 */ 1945 struct dmub_rb_cmd_psr_set_version { 1946 /** 1947 * Command header. 1948 */ 1949 struct dmub_cmd_header header; 1950 /** 1951 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1952 */ 1953 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1954 }; 1955 1956 struct dmub_cmd_psr_force_static_data { 1957 /** 1958 * PSR control version. 1959 */ 1960 uint8_t cmd_version; 1961 /** 1962 * Panel Instance. 1963 * Panel isntance to identify which psr_state to use 1964 * Currently the support is only for 0 or 1 1965 */ 1966 uint8_t panel_inst; 1967 /** 1968 * Explicit padding to 4 byte boundary. 1969 */ 1970 uint8_t pad[2]; 1971 }; 1972 1973 /** 1974 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1975 */ 1976 struct dmub_rb_cmd_psr_force_static { 1977 /** 1978 * Command header. 1979 */ 1980 struct dmub_cmd_header header; 1981 /** 1982 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1983 */ 1984 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1985 }; 1986 1987 /** 1988 * PSR SU debug flags. 1989 */ 1990 union dmub_psr_su_debug_flags { 1991 /** 1992 * PSR SU debug flags. 1993 */ 1994 struct { 1995 /** 1996 * Update dirty rect in SW only. 1997 */ 1998 uint8_t update_dirty_rect_only : 1; 1999 /** 2000 * Reset the cursor/plane state before processing the call. 2001 */ 2002 uint8_t reset_state : 1; 2003 } bitfields; 2004 2005 /** 2006 * Union for debug flags. 2007 */ 2008 uint32_t u32All; 2009 }; 2010 2011 /** 2012 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2013 * This triggers a selective update for PSR SU. 2014 */ 2015 struct dmub_cmd_update_dirty_rect_data { 2016 /** 2017 * Dirty rects from OS. 2018 */ 2019 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2020 /** 2021 * PSR SU debug flags. 2022 */ 2023 union dmub_psr_su_debug_flags debug_flags; 2024 /** 2025 * OTG HW instance. 2026 */ 2027 uint8_t pipe_idx; 2028 /** 2029 * Number of dirty rects. 2030 */ 2031 uint8_t dirty_rect_count; 2032 /** 2033 * PSR control version. 2034 */ 2035 uint8_t cmd_version; 2036 /** 2037 * Panel Instance. 2038 * Panel isntance to identify which psr_state to use 2039 * Currently the support is only for 0 or 1 2040 */ 2041 uint8_t panel_inst; 2042 }; 2043 2044 /** 2045 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2046 */ 2047 struct dmub_rb_cmd_update_dirty_rect { 2048 /** 2049 * Command header. 2050 */ 2051 struct dmub_cmd_header header; 2052 /** 2053 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2054 */ 2055 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2056 }; 2057 2058 /** 2059 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2060 */ 2061 struct dmub_cmd_update_cursor_info_data { 2062 /** 2063 * Cursor dirty rects. 2064 */ 2065 struct dmub_rect cursor_rect; 2066 /** 2067 * PSR SU debug flags. 2068 */ 2069 union dmub_psr_su_debug_flags debug_flags; 2070 /** 2071 * Cursor enable/disable. 2072 */ 2073 uint8_t enable; 2074 /** 2075 * OTG HW instance. 2076 */ 2077 uint8_t pipe_idx; 2078 /** 2079 * PSR control version. 2080 */ 2081 uint8_t cmd_version; 2082 /** 2083 * Panel Instance. 2084 * Panel isntance to identify which psr_state to use 2085 * Currently the support is only for 0 or 1 2086 */ 2087 uint8_t panel_inst; 2088 }; 2089 /** 2090 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2091 */ 2092 struct dmub_rb_cmd_update_cursor_info { 2093 /** 2094 * Command header. 2095 */ 2096 struct dmub_cmd_header header; 2097 /** 2098 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2099 */ 2100 struct dmub_cmd_update_cursor_info_data update_cursor_info_data; 2101 }; 2102 2103 /** 2104 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2105 */ 2106 struct dmub_cmd_psr_set_vtotal_data { 2107 /** 2108 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2109 */ 2110 uint16_t psr_vtotal_idle; 2111 /** 2112 * PSR control version. 2113 */ 2114 uint8_t cmd_version; 2115 /** 2116 * Panel Instance. 2117 * Panel isntance to identify which psr_state to use 2118 * Currently the support is only for 0 or 1 2119 */ 2120 uint8_t panel_inst; 2121 /* 2122 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2123 */ 2124 uint16_t psr_vtotal_su; 2125 /** 2126 * Explicit padding to 4 byte boundary. 2127 */ 2128 uint8_t pad2[2]; 2129 }; 2130 2131 /** 2132 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2133 */ 2134 struct dmub_rb_cmd_psr_set_vtotal { 2135 /** 2136 * Command header. 2137 */ 2138 struct dmub_cmd_header header; 2139 /** 2140 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2141 */ 2142 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2143 }; 2144 2145 /** 2146 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2147 */ 2148 struct dmub_cmd_psr_set_power_opt_data { 2149 /** 2150 * PSR control version. 2151 */ 2152 uint8_t cmd_version; 2153 /** 2154 * Panel Instance. 2155 * Panel isntance to identify which psr_state to use 2156 * Currently the support is only for 0 or 1 2157 */ 2158 uint8_t panel_inst; 2159 /** 2160 * Explicit padding to 4 byte boundary. 2161 */ 2162 uint8_t pad[2]; 2163 /** 2164 * PSR power option 2165 */ 2166 uint32_t power_opt; 2167 }; 2168 2169 /** 2170 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2171 */ 2172 struct dmub_rb_cmd_psr_set_power_opt { 2173 /** 2174 * Command header. 2175 */ 2176 struct dmub_cmd_header header; 2177 /** 2178 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2179 */ 2180 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2181 }; 2182 2183 /** 2184 * Set of HW components that can be locked. 2185 * 2186 * Note: If updating with more HW components, fields 2187 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2188 */ 2189 union dmub_hw_lock_flags { 2190 /** 2191 * Set of HW components that can be locked. 2192 */ 2193 struct { 2194 /** 2195 * Lock/unlock OTG master update lock. 2196 */ 2197 uint8_t lock_pipe : 1; 2198 /** 2199 * Lock/unlock cursor. 2200 */ 2201 uint8_t lock_cursor : 1; 2202 /** 2203 * Lock/unlock global update lock. 2204 */ 2205 uint8_t lock_dig : 1; 2206 /** 2207 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2208 */ 2209 uint8_t triple_buffer_lock : 1; 2210 } bits; 2211 2212 /** 2213 * Union for HW Lock flags. 2214 */ 2215 uint8_t u8All; 2216 }; 2217 2218 /** 2219 * Instances of HW to be locked. 2220 * 2221 * Note: If updating with more HW components, fields 2222 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2223 */ 2224 struct dmub_hw_lock_inst_flags { 2225 /** 2226 * OTG HW instance for OTG master update lock. 2227 */ 2228 uint8_t otg_inst; 2229 /** 2230 * OPP instance for cursor lock. 2231 */ 2232 uint8_t opp_inst; 2233 /** 2234 * OTG HW instance for global update lock. 2235 * TODO: Remove, and re-use otg_inst. 2236 */ 2237 uint8_t dig_inst; 2238 /** 2239 * Explicit pad to 4 byte boundary. 2240 */ 2241 uint8_t pad; 2242 }; 2243 2244 /** 2245 * Clients that can acquire the HW Lock Manager. 2246 * 2247 * Note: If updating with more clients, fields in 2248 * dmub_inbox0_cmd_lock_hw must be updated to match. 2249 */ 2250 enum hw_lock_client { 2251 /** 2252 * Driver is the client of HW Lock Manager. 2253 */ 2254 HW_LOCK_CLIENT_DRIVER = 0, 2255 /** 2256 * PSR SU is the client of HW Lock Manager. 2257 */ 2258 HW_LOCK_CLIENT_PSR_SU = 1, 2259 /** 2260 * Invalid client. 2261 */ 2262 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2263 }; 2264 2265 /** 2266 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2267 */ 2268 struct dmub_cmd_lock_hw_data { 2269 /** 2270 * Specifies the client accessing HW Lock Manager. 2271 */ 2272 enum hw_lock_client client; 2273 /** 2274 * HW instances to be locked. 2275 */ 2276 struct dmub_hw_lock_inst_flags inst_flags; 2277 /** 2278 * Which components to be locked. 2279 */ 2280 union dmub_hw_lock_flags hw_locks; 2281 /** 2282 * Specifies lock/unlock. 2283 */ 2284 uint8_t lock; 2285 /** 2286 * HW can be unlocked separately from releasing the HW Lock Mgr. 2287 * This flag is set if the client wishes to release the object. 2288 */ 2289 uint8_t should_release; 2290 /** 2291 * Explicit padding to 4 byte boundary. 2292 */ 2293 uint8_t pad; 2294 }; 2295 2296 /** 2297 * Definition of a DMUB_CMD__HW_LOCK command. 2298 * Command is used by driver and FW. 2299 */ 2300 struct dmub_rb_cmd_lock_hw { 2301 /** 2302 * Command header. 2303 */ 2304 struct dmub_cmd_header header; 2305 /** 2306 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2307 */ 2308 struct dmub_cmd_lock_hw_data lock_hw_data; 2309 }; 2310 2311 /** 2312 * ABM command sub-types. 2313 */ 2314 enum dmub_cmd_abm_type { 2315 /** 2316 * Initialize parameters for ABM algorithm. 2317 * Data is passed through an indirect buffer. 2318 */ 2319 DMUB_CMD__ABM_INIT_CONFIG = 0, 2320 /** 2321 * Set OTG and panel HW instance. 2322 */ 2323 DMUB_CMD__ABM_SET_PIPE = 1, 2324 /** 2325 * Set user requested backklight level. 2326 */ 2327 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2328 /** 2329 * Set ABM operating/aggression level. 2330 */ 2331 DMUB_CMD__ABM_SET_LEVEL = 3, 2332 /** 2333 * Set ambient light level. 2334 */ 2335 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2336 /** 2337 * Enable/disable fractional duty cycle for backlight PWM. 2338 */ 2339 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2340 2341 /** 2342 * unregister vertical interrupt after steady state is reached 2343 */ 2344 DMUB_CMD__ABM_PAUSE = 6, 2345 }; 2346 2347 /** 2348 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2349 * Requirements: 2350 * - Padded explicitly to 32-bit boundary. 2351 * - Must ensure this structure matches the one on driver-side, 2352 * otherwise it won't be aligned. 2353 */ 2354 struct abm_config_table { 2355 /** 2356 * Gamma curve thresholds, used for crgb conversion. 2357 */ 2358 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2359 /** 2360 * Gamma curve offsets, used for crgb conversion. 2361 */ 2362 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2363 /** 2364 * Gamma curve slopes, used for crgb conversion. 2365 */ 2366 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2367 /** 2368 * Custom backlight curve thresholds. 2369 */ 2370 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2371 /** 2372 * Custom backlight curve offsets. 2373 */ 2374 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2375 /** 2376 * Ambient light thresholds. 2377 */ 2378 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2379 /** 2380 * Minimum programmable backlight. 2381 */ 2382 uint16_t min_abm_backlight; // 122B 2383 /** 2384 * Minimum reduction values. 2385 */ 2386 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2387 /** 2388 * Maximum reduction values. 2389 */ 2390 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2391 /** 2392 * Bright positive gain. 2393 */ 2394 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2395 /** 2396 * Dark negative gain. 2397 */ 2398 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2399 /** 2400 * Hybrid factor. 2401 */ 2402 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2403 /** 2404 * Contrast factor. 2405 */ 2406 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2407 /** 2408 * Deviation gain. 2409 */ 2410 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2411 /** 2412 * Minimum knee. 2413 */ 2414 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2415 /** 2416 * Maximum knee. 2417 */ 2418 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2419 /** 2420 * Unused. 2421 */ 2422 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2423 /** 2424 * Explicit padding to 4 byte boundary. 2425 */ 2426 uint8_t pad3[3]; // 229B 2427 /** 2428 * Backlight ramp reduction. 2429 */ 2430 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2431 /** 2432 * Backlight ramp start. 2433 */ 2434 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2435 }; 2436 2437 /** 2438 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2439 */ 2440 struct dmub_cmd_abm_set_pipe_data { 2441 /** 2442 * OTG HW instance. 2443 */ 2444 uint8_t otg_inst; 2445 2446 /** 2447 * Panel Control HW instance. 2448 */ 2449 uint8_t panel_inst; 2450 2451 /** 2452 * Controls how ABM will interpret a set pipe or set level command. 2453 */ 2454 uint8_t set_pipe_option; 2455 2456 /** 2457 * Unused. 2458 * TODO: Remove. 2459 */ 2460 uint8_t ramping_boundary; 2461 }; 2462 2463 /** 2464 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2465 */ 2466 struct dmub_rb_cmd_abm_set_pipe { 2467 /** 2468 * Command header. 2469 */ 2470 struct dmub_cmd_header header; 2471 2472 /** 2473 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2474 */ 2475 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2476 }; 2477 2478 /** 2479 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2480 */ 2481 struct dmub_cmd_abm_set_backlight_data { 2482 /** 2483 * Number of frames to ramp to backlight user level. 2484 */ 2485 uint32_t frame_ramp; 2486 2487 /** 2488 * Requested backlight level from user. 2489 */ 2490 uint32_t backlight_user_level; 2491 2492 /** 2493 * ABM control version. 2494 */ 2495 uint8_t version; 2496 2497 /** 2498 * Panel Control HW instance mask. 2499 * Bit 0 is Panel Control HW instance 0. 2500 * Bit 1 is Panel Control HW instance 1. 2501 */ 2502 uint8_t panel_mask; 2503 2504 /** 2505 * Explicit padding to 4 byte boundary. 2506 */ 2507 uint8_t pad[2]; 2508 }; 2509 2510 /** 2511 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2512 */ 2513 struct dmub_rb_cmd_abm_set_backlight { 2514 /** 2515 * Command header. 2516 */ 2517 struct dmub_cmd_header header; 2518 2519 /** 2520 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2521 */ 2522 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2523 }; 2524 2525 /** 2526 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2527 */ 2528 struct dmub_cmd_abm_set_level_data { 2529 /** 2530 * Set current ABM operating/aggression level. 2531 */ 2532 uint32_t level; 2533 2534 /** 2535 * ABM control version. 2536 */ 2537 uint8_t version; 2538 2539 /** 2540 * Panel Control HW instance mask. 2541 * Bit 0 is Panel Control HW instance 0. 2542 * Bit 1 is Panel Control HW instance 1. 2543 */ 2544 uint8_t panel_mask; 2545 2546 /** 2547 * Explicit padding to 4 byte boundary. 2548 */ 2549 uint8_t pad[2]; 2550 }; 2551 2552 /** 2553 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2554 */ 2555 struct dmub_rb_cmd_abm_set_level { 2556 /** 2557 * Command header. 2558 */ 2559 struct dmub_cmd_header header; 2560 2561 /** 2562 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2563 */ 2564 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2565 }; 2566 2567 /** 2568 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2569 */ 2570 struct dmub_cmd_abm_set_ambient_level_data { 2571 /** 2572 * Ambient light sensor reading from OS. 2573 */ 2574 uint32_t ambient_lux; 2575 2576 /** 2577 * ABM control version. 2578 */ 2579 uint8_t version; 2580 2581 /** 2582 * Panel Control HW instance mask. 2583 * Bit 0 is Panel Control HW instance 0. 2584 * Bit 1 is Panel Control HW instance 1. 2585 */ 2586 uint8_t panel_mask; 2587 2588 /** 2589 * Explicit padding to 4 byte boundary. 2590 */ 2591 uint8_t pad[2]; 2592 }; 2593 2594 /** 2595 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2596 */ 2597 struct dmub_rb_cmd_abm_set_ambient_level { 2598 /** 2599 * Command header. 2600 */ 2601 struct dmub_cmd_header header; 2602 2603 /** 2604 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2605 */ 2606 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2607 }; 2608 2609 /** 2610 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2611 */ 2612 struct dmub_cmd_abm_set_pwm_frac_data { 2613 /** 2614 * Enable/disable fractional duty cycle for backlight PWM. 2615 * TODO: Convert to uint8_t. 2616 */ 2617 uint32_t fractional_pwm; 2618 2619 /** 2620 * ABM control version. 2621 */ 2622 uint8_t version; 2623 2624 /** 2625 * Panel Control HW instance mask. 2626 * Bit 0 is Panel Control HW instance 0. 2627 * Bit 1 is Panel Control HW instance 1. 2628 */ 2629 uint8_t panel_mask; 2630 2631 /** 2632 * Explicit padding to 4 byte boundary. 2633 */ 2634 uint8_t pad[2]; 2635 }; 2636 2637 /** 2638 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2639 */ 2640 struct dmub_rb_cmd_abm_set_pwm_frac { 2641 /** 2642 * Command header. 2643 */ 2644 struct dmub_cmd_header header; 2645 2646 /** 2647 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2648 */ 2649 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2650 }; 2651 2652 /** 2653 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2654 */ 2655 struct dmub_cmd_abm_init_config_data { 2656 /** 2657 * Location of indirect buffer used to pass init data to ABM. 2658 */ 2659 union dmub_addr src; 2660 2661 /** 2662 * Indirect buffer length. 2663 */ 2664 uint16_t bytes; 2665 2666 2667 /** 2668 * ABM control version. 2669 */ 2670 uint8_t version; 2671 2672 /** 2673 * Panel Control HW instance mask. 2674 * Bit 0 is Panel Control HW instance 0. 2675 * Bit 1 is Panel Control HW instance 1. 2676 */ 2677 uint8_t panel_mask; 2678 2679 /** 2680 * Explicit padding to 4 byte boundary. 2681 */ 2682 uint8_t pad[2]; 2683 }; 2684 2685 /** 2686 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2687 */ 2688 struct dmub_rb_cmd_abm_init_config { 2689 /** 2690 * Command header. 2691 */ 2692 struct dmub_cmd_header header; 2693 2694 /** 2695 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2696 */ 2697 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2698 }; 2699 2700 /** 2701 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2702 */ 2703 2704 struct dmub_cmd_abm_pause_data { 2705 2706 /** 2707 * Panel Control HW instance mask. 2708 * Bit 0 is Panel Control HW instance 0. 2709 * Bit 1 is Panel Control HW instance 1. 2710 */ 2711 uint8_t panel_mask; 2712 2713 /** 2714 * OTG hw instance 2715 */ 2716 uint8_t otg_inst; 2717 2718 /** 2719 * Enable or disable ABM pause 2720 */ 2721 uint8_t enable; 2722 2723 /** 2724 * Explicit padding to 4 byte boundary. 2725 */ 2726 uint8_t pad[1]; 2727 }; 2728 2729 /** 2730 * Definition of a DMUB_CMD__ABM_PAUSE command. 2731 */ 2732 struct dmub_rb_cmd_abm_pause { 2733 /** 2734 * Command header. 2735 */ 2736 struct dmub_cmd_header header; 2737 2738 /** 2739 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2740 */ 2741 struct dmub_cmd_abm_pause_data abm_pause_data; 2742 }; 2743 2744 /** 2745 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2746 */ 2747 struct dmub_cmd_query_feature_caps_data { 2748 /** 2749 * DMUB feature capabilities. 2750 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2751 */ 2752 struct dmub_feature_caps feature_caps; 2753 }; 2754 2755 /** 2756 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2757 */ 2758 struct dmub_rb_cmd_query_feature_caps { 2759 /** 2760 * Command header. 2761 */ 2762 struct dmub_cmd_header header; 2763 /** 2764 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2765 */ 2766 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2767 }; 2768 2769 struct dmub_optc_state { 2770 uint32_t v_total_max; 2771 uint32_t v_total_min; 2772 uint32_t v_total_mid; 2773 uint32_t v_total_mid_frame_num; 2774 uint32_t tg_inst; 2775 uint32_t enable_manual_trigger; 2776 uint32_t clear_force_vsync; 2777 }; 2778 2779 struct dmub_rb_cmd_drr_update { 2780 struct dmub_cmd_header header; 2781 struct dmub_optc_state dmub_optc_state_req; 2782 }; 2783 2784 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 2785 uint32_t pix_clk_100hz; 2786 uint8_t max_ramp_step; 2787 uint8_t pipes; 2788 uint8_t min_refresh_in_hz; 2789 uint8_t padding[1]; 2790 }; 2791 2792 struct dmub_cmd_fw_assisted_mclk_switch_config { 2793 uint8_t fams_enabled; 2794 uint8_t visual_confirm_enabled; 2795 uint8_t padding[2]; 2796 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 2797 }; 2798 2799 struct dmub_rb_cmd_fw_assisted_mclk_switch { 2800 struct dmub_cmd_header header; 2801 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 2802 }; 2803 2804 /** 2805 * enum dmub_cmd_panel_cntl_type - Panel control command. 2806 */ 2807 enum dmub_cmd_panel_cntl_type { 2808 /** 2809 * Initializes embedded panel hardware blocks. 2810 */ 2811 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2812 /** 2813 * Queries backlight info for the embedded panel. 2814 */ 2815 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2816 }; 2817 2818 /** 2819 * struct dmub_cmd_panel_cntl_data - Panel control data. 2820 */ 2821 struct dmub_cmd_panel_cntl_data { 2822 uint32_t inst; /**< panel instance */ 2823 uint32_t current_backlight; /* in/out */ 2824 uint32_t bl_pwm_cntl; /* in/out */ 2825 uint32_t bl_pwm_period_cntl; /* in/out */ 2826 uint32_t bl_pwm_ref_div1; /* in/out */ 2827 uint8_t is_backlight_on : 1; /* in/out */ 2828 uint8_t is_powered_on : 1; /* in/out */ 2829 uint8_t padding[3]; 2830 uint32_t bl_pwm_ref_div2; /* in/out */ 2831 uint8_t reserved[4]; 2832 }; 2833 2834 /** 2835 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2836 */ 2837 struct dmub_rb_cmd_panel_cntl { 2838 struct dmub_cmd_header header; /**< header */ 2839 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2840 }; 2841 2842 /** 2843 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2844 */ 2845 struct dmub_cmd_lvtma_control_data { 2846 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2847 uint8_t reserved_0[3]; /**< For future use */ 2848 uint8_t panel_inst; /**< LVTMA control instance */ 2849 uint8_t reserved_1[3]; /**< For future use */ 2850 }; 2851 2852 /** 2853 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2854 */ 2855 struct dmub_rb_cmd_lvtma_control { 2856 /** 2857 * Command header. 2858 */ 2859 struct dmub_cmd_header header; 2860 /** 2861 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2862 */ 2863 struct dmub_cmd_lvtma_control_data data; 2864 }; 2865 2866 /** 2867 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2868 */ 2869 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 2870 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2871 uint8_t is_usb; /**< is phy is usb */ 2872 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 2873 uint8_t is_dp4; /**< is dp in 4 lane */ 2874 }; 2875 2876 /** 2877 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2878 */ 2879 struct dmub_rb_cmd_transmitter_query_dp_alt { 2880 struct dmub_cmd_header header; /**< header */ 2881 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 2882 }; 2883 2884 /** 2885 * Maximum number of bytes a chunk sent to DMUB for parsing 2886 */ 2887 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2888 2889 /** 2890 * Represent a chunk of CEA blocks sent to DMUB for parsing 2891 */ 2892 struct dmub_cmd_send_edid_cea { 2893 uint16_t offset; /**< offset into the CEA block */ 2894 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2895 uint16_t cea_total_length; /**< total length of the CEA block */ 2896 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2897 uint8_t pad[3]; /**< padding and for future expansion */ 2898 }; 2899 2900 /** 2901 * Result of VSDB parsing from CEA block 2902 */ 2903 struct dmub_cmd_edid_cea_amd_vsdb { 2904 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2905 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2906 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2907 uint16_t min_frame_rate; /**< Maximum frame rate */ 2908 uint16_t max_frame_rate; /**< Minimum frame rate */ 2909 }; 2910 2911 /** 2912 * Result of sending a CEA chunk 2913 */ 2914 struct dmub_cmd_edid_cea_ack { 2915 uint16_t offset; /**< offset of the chunk into the CEA block */ 2916 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2917 uint8_t pad; /**< padding and for future expansion */ 2918 }; 2919 2920 /** 2921 * Specify whether the result is an ACK/NACK or the parsing has finished 2922 */ 2923 enum dmub_cmd_edid_cea_reply_type { 2924 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2925 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2926 }; 2927 2928 /** 2929 * Definition of a DMUB_CMD__EDID_CEA command. 2930 */ 2931 struct dmub_rb_cmd_edid_cea { 2932 struct dmub_cmd_header header; /**< Command header */ 2933 union dmub_cmd_edid_cea_data { 2934 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2935 struct dmub_cmd_edid_cea_output { /**< output with results */ 2936 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2937 union { 2938 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2939 struct dmub_cmd_edid_cea_ack ack; 2940 }; 2941 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2942 } data; /**< Command data */ 2943 2944 }; 2945 2946 /** 2947 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 2948 */ 2949 struct dmub_cmd_cable_id_input { 2950 uint8_t phy_inst; /**< phy inst for cable id data */ 2951 }; 2952 2953 /** 2954 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 2955 */ 2956 struct dmub_cmd_cable_id_output { 2957 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 2958 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 2959 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 2960 uint8_t RESERVED :2; /**< reserved means not defined */ 2961 }; 2962 2963 /** 2964 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 2965 */ 2966 struct dmub_rb_cmd_get_usbc_cable_id { 2967 struct dmub_cmd_header header; /**< Command header */ 2968 /** 2969 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 2970 */ 2971 union dmub_cmd_cable_id_data { 2972 struct dmub_cmd_cable_id_input input; /**< Input */ 2973 struct dmub_cmd_cable_id_output output; /**< Output */ 2974 uint8_t output_raw; /**< Raw data output */ 2975 } data; 2976 }; 2977 2978 /** 2979 * union dmub_rb_cmd - DMUB inbox command. 2980 */ 2981 union dmub_rb_cmd { 2982 /** 2983 * Elements shared with all commands. 2984 */ 2985 struct dmub_rb_cmd_common cmd_common; 2986 /** 2987 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2988 */ 2989 struct dmub_rb_cmd_read_modify_write read_modify_write; 2990 /** 2991 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2992 */ 2993 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2994 /** 2995 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2996 */ 2997 struct dmub_rb_cmd_burst_write burst_write; 2998 /** 2999 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3000 */ 3001 struct dmub_rb_cmd_reg_wait reg_wait; 3002 /** 3003 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3004 */ 3005 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3006 /** 3007 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3008 */ 3009 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3010 /** 3011 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3012 */ 3013 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3014 /** 3015 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3016 */ 3017 struct dmub_rb_cmd_dpphy_init dpphy_init; 3018 /** 3019 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3020 */ 3021 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3022 /** 3023 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3024 */ 3025 struct dmub_rb_cmd_psr_set_version psr_set_version; 3026 /** 3027 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3028 */ 3029 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3030 /** 3031 * Definition of a DMUB_CMD__PSR_ENABLE command. 3032 */ 3033 struct dmub_rb_cmd_psr_enable psr_enable; 3034 /** 3035 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3036 */ 3037 struct dmub_rb_cmd_psr_set_level psr_set_level; 3038 /** 3039 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3040 */ 3041 struct dmub_rb_cmd_psr_force_static psr_force_static; 3042 /** 3043 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3044 */ 3045 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3046 /** 3047 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3048 */ 3049 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3050 /** 3051 * Definition of a DMUB_CMD__HW_LOCK command. 3052 * Command is used by driver and FW. 3053 */ 3054 struct dmub_rb_cmd_lock_hw lock_hw; 3055 /** 3056 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3057 */ 3058 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3059 /** 3060 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3061 */ 3062 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3063 /** 3064 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3065 */ 3066 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3067 /** 3068 * Definition of a DMUB_CMD__MALL command. 3069 */ 3070 struct dmub_rb_cmd_mall mall; 3071 /** 3072 * Definition of a DMUB_CMD__CAB command. 3073 */ 3074 struct dmub_rb_cmd_cab_for_ss cab; 3075 3076 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3077 3078 /** 3079 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3080 */ 3081 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3082 3083 /** 3084 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3085 */ 3086 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3087 3088 /** 3089 * Definition of DMUB_CMD__PANEL_CNTL commands. 3090 */ 3091 struct dmub_rb_cmd_panel_cntl panel_cntl; 3092 /** 3093 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3094 */ 3095 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3096 3097 /** 3098 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3099 */ 3100 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3101 3102 /** 3103 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3104 */ 3105 struct dmub_rb_cmd_abm_set_level abm_set_level; 3106 3107 /** 3108 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3109 */ 3110 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3111 3112 /** 3113 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3114 */ 3115 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3116 3117 /** 3118 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3119 */ 3120 struct dmub_rb_cmd_abm_init_config abm_init_config; 3121 3122 /** 3123 * Definition of a DMUB_CMD__ABM_PAUSE command. 3124 */ 3125 struct dmub_rb_cmd_abm_pause abm_pause; 3126 3127 /** 3128 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3129 */ 3130 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3131 3132 /** 3133 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3134 */ 3135 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3136 3137 /** 3138 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3139 */ 3140 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3141 struct dmub_rb_cmd_drr_update drr_update; 3142 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3143 3144 /** 3145 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3146 */ 3147 struct dmub_rb_cmd_lvtma_control lvtma_control; 3148 /** 3149 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3150 */ 3151 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3152 /** 3153 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3154 */ 3155 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3156 /** 3157 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3158 */ 3159 struct dmub_rb_cmd_set_config_access set_config_access; 3160 /** 3161 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3162 */ 3163 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3164 /** 3165 * Definition of a DMUB_CMD__EDID_CEA command. 3166 */ 3167 struct dmub_rb_cmd_edid_cea edid_cea; 3168 /** 3169 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3170 */ 3171 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3172 3173 /** 3174 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3175 */ 3176 struct dmub_rb_cmd_query_hpd_state query_hpd; 3177 }; 3178 3179 /** 3180 * union dmub_rb_out_cmd - Outbox command 3181 */ 3182 union dmub_rb_out_cmd { 3183 /** 3184 * Parameters common to every command. 3185 */ 3186 struct dmub_rb_cmd_common cmd_common; 3187 /** 3188 * AUX reply command. 3189 */ 3190 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3191 /** 3192 * HPD notify command. 3193 */ 3194 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3195 /** 3196 * SET_CONFIG reply command. 3197 */ 3198 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3199 }; 3200 #pragma pack(pop) 3201 3202 3203 //============================================================================== 3204 //</DMUB_CMD>=================================================================== 3205 //============================================================================== 3206 //< DMUB_RB>==================================================================== 3207 //============================================================================== 3208 3209 #if defined(__cplusplus) 3210 extern "C" { 3211 #endif 3212 3213 /** 3214 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3215 */ 3216 struct dmub_rb_init_params { 3217 void *ctx; /**< Caller provided context pointer */ 3218 void *base_address; /**< CPU base address for ring's data */ 3219 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3220 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3221 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3222 }; 3223 3224 /** 3225 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3226 */ 3227 struct dmub_rb { 3228 void *base_address; /**< CPU address for the ring's data */ 3229 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3230 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3231 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3232 3233 void *ctx; /**< Caller provided context pointer */ 3234 void *dmub; /**< Pointer to the DMUB interface */ 3235 }; 3236 3237 /** 3238 * @brief Checks if the ringbuffer is empty. 3239 * 3240 * @param rb DMUB Ringbuffer 3241 * @return true if empty 3242 * @return false otherwise 3243 */ 3244 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3245 { 3246 return (rb->wrpt == rb->rptr); 3247 } 3248 3249 /** 3250 * @brief Checks if the ringbuffer is full 3251 * 3252 * @param rb DMUB Ringbuffer 3253 * @return true if full 3254 * @return false otherwise 3255 */ 3256 static inline bool dmub_rb_full(struct dmub_rb *rb) 3257 { 3258 uint32_t data_count; 3259 3260 if (rb->wrpt >= rb->rptr) 3261 data_count = rb->wrpt - rb->rptr; 3262 else 3263 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3264 3265 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3266 } 3267 3268 /** 3269 * @brief Pushes a command into the ringbuffer 3270 * 3271 * @param rb DMUB ringbuffer 3272 * @param cmd The command to push 3273 * @return true if the ringbuffer was not full 3274 * @return false otherwise 3275 */ 3276 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3277 const union dmub_rb_cmd *cmd) 3278 { 3279 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3280 const uint64_t *src = (const uint64_t *)cmd; 3281 uint8_t i; 3282 3283 if (dmub_rb_full(rb)) 3284 return false; 3285 3286 // copying data 3287 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3288 *dst++ = *src++; 3289 3290 rb->wrpt += DMUB_RB_CMD_SIZE; 3291 3292 if (rb->wrpt >= rb->capacity) 3293 rb->wrpt %= rb->capacity; 3294 3295 return true; 3296 } 3297 3298 /** 3299 * @brief Pushes a command into the DMUB outbox ringbuffer 3300 * 3301 * @param rb DMUB outbox ringbuffer 3302 * @param cmd Outbox command 3303 * @return true if not full 3304 * @return false otherwise 3305 */ 3306 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3307 const union dmub_rb_out_cmd *cmd) 3308 { 3309 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3310 const uint8_t *src = (const uint8_t *)cmd; 3311 3312 if (dmub_rb_full(rb)) 3313 return false; 3314 3315 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3316 3317 rb->wrpt += DMUB_RB_CMD_SIZE; 3318 3319 if (rb->wrpt >= rb->capacity) 3320 rb->wrpt %= rb->capacity; 3321 3322 return true; 3323 } 3324 3325 /** 3326 * @brief Returns the next unprocessed command in the ringbuffer. 3327 * 3328 * @param rb DMUB ringbuffer 3329 * @param cmd The command to return 3330 * @return true if not empty 3331 * @return false otherwise 3332 */ 3333 static inline bool dmub_rb_front(struct dmub_rb *rb, 3334 union dmub_rb_cmd **cmd) 3335 { 3336 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3337 3338 if (dmub_rb_empty(rb)) 3339 return false; 3340 3341 *cmd = (union dmub_rb_cmd *)rb_cmd; 3342 3343 return true; 3344 } 3345 3346 /** 3347 * @brief Determines the next ringbuffer offset. 3348 * 3349 * @param rb DMUB inbox ringbuffer 3350 * @param num_cmds Number of commands 3351 * @param next_rptr The next offset in the ringbuffer 3352 */ 3353 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3354 uint32_t num_cmds, 3355 uint32_t *next_rptr) 3356 { 3357 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3358 3359 if (*next_rptr >= rb->capacity) 3360 *next_rptr %= rb->capacity; 3361 } 3362 3363 /** 3364 * @brief Returns a pointer to a command in the inbox. 3365 * 3366 * @param rb DMUB inbox ringbuffer 3367 * @param cmd The inbox command to return 3368 * @param rptr The ringbuffer offset 3369 * @return true if not empty 3370 * @return false otherwise 3371 */ 3372 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3373 union dmub_rb_cmd **cmd, 3374 uint32_t rptr) 3375 { 3376 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3377 3378 if (dmub_rb_empty(rb)) 3379 return false; 3380 3381 *cmd = (union dmub_rb_cmd *)rb_cmd; 3382 3383 return true; 3384 } 3385 3386 /** 3387 * @brief Returns the next unprocessed command in the outbox. 3388 * 3389 * @param rb DMUB outbox ringbuffer 3390 * @param cmd The outbox command to return 3391 * @return true if not empty 3392 * @return false otherwise 3393 */ 3394 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3395 union dmub_rb_out_cmd *cmd) 3396 { 3397 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3398 uint64_t *dst = (uint64_t *)cmd; 3399 uint8_t i; 3400 3401 if (dmub_rb_empty(rb)) 3402 return false; 3403 3404 // copying data 3405 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3406 *dst++ = *src++; 3407 3408 return true; 3409 } 3410 3411 /** 3412 * @brief Removes the front entry in the ringbuffer. 3413 * 3414 * @param rb DMUB ringbuffer 3415 * @return true if the command was removed 3416 * @return false if there were no commands 3417 */ 3418 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3419 { 3420 if (dmub_rb_empty(rb)) 3421 return false; 3422 3423 rb->rptr += DMUB_RB_CMD_SIZE; 3424 3425 if (rb->rptr >= rb->capacity) 3426 rb->rptr %= rb->capacity; 3427 3428 return true; 3429 } 3430 3431 /** 3432 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3433 * 3434 * Avoids a race condition where DMCUB accesses memory while 3435 * there are still writes in flight to framebuffer. 3436 * 3437 * @param rb DMUB ringbuffer 3438 */ 3439 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3440 { 3441 uint32_t rptr = rb->rptr; 3442 uint32_t wptr = rb->wrpt; 3443 3444 while (rptr != wptr) { 3445 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3446 uint8_t i; 3447 3448 /* Don't remove this. 3449 * The contents need to actually be read from the ring buffer 3450 * for this function to be effective. 3451 */ 3452 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3453 (void)READ_ONCE(*data++); 3454 3455 rptr += DMUB_RB_CMD_SIZE; 3456 if (rptr >= rb->capacity) 3457 rptr %= rb->capacity; 3458 } 3459 } 3460 3461 /** 3462 * @brief Initializes a DMCUB ringbuffer 3463 * 3464 * @param rb DMUB ringbuffer 3465 * @param init_params initial configuration for the ringbuffer 3466 */ 3467 static inline void dmub_rb_init(struct dmub_rb *rb, 3468 struct dmub_rb_init_params *init_params) 3469 { 3470 rb->base_address = init_params->base_address; 3471 rb->capacity = init_params->capacity; 3472 rb->rptr = init_params->read_ptr; 3473 rb->wrpt = init_params->write_ptr; 3474 } 3475 3476 /** 3477 * @brief Copies output data from in/out commands into the given command. 3478 * 3479 * @param rb DMUB ringbuffer 3480 * @param cmd Command to copy data into 3481 */ 3482 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3483 union dmub_rb_cmd *cmd) 3484 { 3485 // Copy rb entry back into command 3486 uint8_t *rd_ptr = (rb->rptr == 0) ? 3487 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3488 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3489 3490 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3491 } 3492 3493 #if defined(__cplusplus) 3494 } 3495 #endif 3496 3497 //============================================================================== 3498 //</DMUB_RB>==================================================================== 3499 //============================================================================== 3500 3501 #endif /* _DMUB_CMD_H_ */ 3502