1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 #include <stdarg.h> 34 35 #include "atomfirmware.h" 36 37 /* Firmware versioning. */ 38 #ifdef DMUB_EXPOSE_VERSION 39 #define DMUB_FW_VERSION_GIT_HASH 0x9f0af34af 40 #define DMUB_FW_VERSION_MAJOR 0 41 #define DMUB_FW_VERSION_MINOR 0 42 #define DMUB_FW_VERSION_REVISION 40 43 #define DMUB_FW_VERSION_TEST 0 44 #define DMUB_FW_VERSION_VBIOS 0 45 #define DMUB_FW_VERSION_HOTFIX 0 46 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 47 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 48 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 49 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 50 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 51 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 52 53 #endif 54 55 //<DMUB_TYPES>================================================================== 56 /* Basic type definitions. */ 57 58 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 59 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 #define SET_ABM_PIPE_NORMAL 1 62 63 /* Maximum number of streams on any ASIC. */ 64 #define DMUB_MAX_STREAMS 6 65 66 /* Maximum number of planes on any ASIC. */ 67 #define DMUB_MAX_PLANES 6 68 69 #ifndef PHYSICAL_ADDRESS_LOC 70 #define PHYSICAL_ADDRESS_LOC union large_integer 71 #endif 72 73 #ifndef dmub_memcpy 74 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 75 #endif 76 77 #ifndef dmub_memset 78 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 79 #endif 80 81 #if defined(__cplusplus) 82 extern "C" { 83 #endif 84 85 #ifndef dmub_udelay 86 #define dmub_udelay(microseconds) udelay(microseconds) 87 #endif 88 89 union dmub_addr { 90 struct { 91 uint32_t low_part; 92 uint32_t high_part; 93 } u; 94 uint64_t quad_part; 95 }; 96 97 union dmub_psr_debug_flags { 98 struct { 99 uint32_t visual_confirm : 1; 100 uint32_t use_hw_lock_mgr : 1; 101 uint32_t log_line_nums : 1; 102 } bitfields; 103 104 uint32_t u32All; 105 }; 106 107 #if defined(__cplusplus) 108 } 109 #endif 110 111 112 113 //============================================================================== 114 //</DMUB_TYPES>================================================================= 115 //============================================================================== 116 //< DMUB_META>================================================================== 117 //============================================================================== 118 #pragma pack(push, 1) 119 120 /* Magic value for identifying dmub_fw_meta_info */ 121 #define DMUB_FW_META_MAGIC 0x444D5542 122 123 /* Offset from the end of the file to the dmub_fw_meta_info */ 124 #define DMUB_FW_META_OFFSET 0x24 125 126 /** 127 * struct dmub_fw_meta_info - metadata associated with fw binary 128 * 129 * NOTE: This should be considered a stable API. Fields should 130 * not be repurposed or reordered. New fields should be 131 * added instead to extend the structure. 132 * 133 * @magic_value: magic value identifying DMUB firmware meta info 134 * @fw_region_size: size of the firmware state region 135 * @trace_buffer_size: size of the tracebuffer region 136 * @fw_version: the firmware version information 137 * @dal_fw: 1 if the firmware is DAL 138 */ 139 struct dmub_fw_meta_info { 140 uint32_t magic_value; 141 uint32_t fw_region_size; 142 uint32_t trace_buffer_size; 143 uint32_t fw_version; 144 uint8_t dal_fw; 145 uint8_t reserved[3]; 146 }; 147 148 /* Ensure that the structure remains 64 bytes. */ 149 union dmub_fw_meta { 150 struct dmub_fw_meta_info info; 151 uint8_t reserved[64]; 152 }; 153 154 #pragma pack(pop) 155 156 //============================================================================== 157 //< DMUB_STATUS>================================================================ 158 //============================================================================== 159 160 /** 161 * DMCUB scratch registers can be used to determine firmware status. 162 * Current scratch register usage is as follows: 163 * 164 * SCRATCH0: FW Boot Status register 165 * SCRATCH15: FW Boot Options register 166 */ 167 168 /* Register bit definition for SCRATCH0 */ 169 union dmub_fw_boot_status { 170 struct { 171 uint32_t dal_fw : 1; 172 uint32_t mailbox_rdy : 1; 173 uint32_t optimized_init_done : 1; 174 uint32_t restore_required : 1; 175 } bits; 176 uint32_t all; 177 }; 178 179 enum dmub_fw_boot_status_bit { 180 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), 181 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), 182 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 183 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), 184 }; 185 186 /* Register bit definition for SCRATCH15 */ 187 union dmub_fw_boot_options { 188 struct { 189 uint32_t pemu_env : 1; 190 uint32_t fpga_env : 1; 191 uint32_t optimized_init : 1; 192 uint32_t skip_phy_access : 1; 193 uint32_t disable_clk_gate: 1; 194 uint32_t reserved : 27; 195 } bits; 196 uint32_t all; 197 }; 198 199 enum dmub_fw_boot_options_bit { 200 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), 201 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), 202 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 203 }; 204 205 //============================================================================== 206 //</DMUB_STATUS>================================================================ 207 //============================================================================== 208 //< DMUB_VBIOS>================================================================= 209 //============================================================================== 210 211 /* 212 * Command IDs should be treated as stable ABI. 213 * Do not reuse or modify IDs. 214 */ 215 216 enum dmub_cmd_vbios_type { 217 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 218 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 219 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 220 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 221 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 222 }; 223 224 //============================================================================== 225 //</DMUB_VBIOS>================================================================= 226 //============================================================================== 227 //< DMUB_GPINT>================================================================= 228 //============================================================================== 229 230 /** 231 * The shifts and masks below may alternatively be used to format and read 232 * the command register bits. 233 */ 234 235 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 236 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 237 238 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 239 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 240 241 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 242 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 243 244 /** 245 * Command responses. 246 */ 247 248 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 249 250 /** 251 * The register format for sending a command via the GPINT. 252 */ 253 union dmub_gpint_data_register { 254 struct { 255 uint32_t param : 16; 256 uint32_t command_code : 12; 257 uint32_t status : 4; 258 } bits; 259 uint32_t all; 260 }; 261 262 /* 263 * Command IDs should be treated as stable ABI. 264 * Do not reuse or modify IDs. 265 */ 266 267 enum dmub_gpint_command { 268 DMUB_GPINT__INVALID_COMMAND = 0, 269 DMUB_GPINT__GET_FW_VERSION = 1, 270 DMUB_GPINT__STOP_FW = 2, 271 DMUB_GPINT__GET_PSR_STATE = 7, 272 /** 273 * DESC: Notifies DMCUB of the currently active streams. 274 * ARGS: Stream mask, 1 bit per active stream index. 275 */ 276 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 277 DMUB_GPINT__PSR_RESIDENCY = 9, 278 }; 279 280 //============================================================================== 281 //</DMUB_GPINT>================================================================= 282 //============================================================================== 283 //< DMUB_CMD>=================================================================== 284 //============================================================================== 285 286 #define DMUB_RB_CMD_SIZE 64 287 #define DMUB_RB_MAX_ENTRY 128 288 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 289 #define REG_SET_MASK 0xFFFF 290 291 /* 292 * Command IDs should be treated as stable ABI. 293 * Do not reuse or modify IDs. 294 */ 295 296 enum dmub_cmd_type { 297 DMUB_CMD__NULL = 0, 298 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 299 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 300 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 301 DMUB_CMD__REG_REG_WAIT = 4, 302 DMUB_CMD__PLAT_54186_WA = 5, 303 DMUB_CMD__PSR = 64, 304 DMUB_CMD__MALL = 65, 305 DMUB_CMD__ABM = 66, 306 DMUB_CMD__HW_LOCK = 69, 307 DMUB_CMD__DP_AUX_ACCESS = 70, 308 DMUB_CMD__OUTBOX1_ENABLE = 71, 309 DMUB_CMD__VBIOS = 128, 310 }; 311 312 enum dmub_out_cmd_type { 313 DMUB_OUT_CMD__NULL = 0, 314 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 315 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 316 }; 317 318 #pragma pack(push, 1) 319 320 struct dmub_cmd_header { 321 unsigned int type : 8; 322 unsigned int sub_type : 8; 323 unsigned int reserved0 : 8; 324 unsigned int payload_bytes : 6; /* up to 60 bytes */ 325 unsigned int reserved1 : 2; 326 }; 327 328 /* 329 * Read modify write 330 * 331 * 60 payload bytes can hold up to 5 sets of read modify writes, 332 * each take 3 dwords. 333 * 334 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 335 * 336 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 337 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 338 */ 339 struct dmub_cmd_read_modify_write_sequence { 340 uint32_t addr; 341 uint32_t modify_mask; 342 uint32_t modify_value; 343 }; 344 345 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 346 struct dmub_rb_cmd_read_modify_write { 347 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 348 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 349 }; 350 351 /* 352 * Update a register with specified masks and values sequeunce 353 * 354 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 355 * 356 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 357 * 358 * 359 * USE CASE: 360 * 1. auto-increment register where additional read would update pointer and produce wrong result 361 * 2. toggle a bit without read in the middle 362 */ 363 364 struct dmub_cmd_reg_field_update_sequence { 365 uint32_t modify_mask; // 0xffff'ffff to skip initial read 366 uint32_t modify_value; 367 }; 368 369 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 370 struct dmub_rb_cmd_reg_field_update_sequence { 371 struct dmub_cmd_header header; 372 uint32_t addr; 373 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 374 }; 375 376 /* 377 * Burst write 378 * 379 * support use case such as writing out LUTs. 380 * 381 * 60 payload bytes can hold up to 14 values to write to given address 382 * 383 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 384 */ 385 #define DMUB_BURST_WRITE_VALUES__MAX 14 386 struct dmub_rb_cmd_burst_write { 387 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 388 uint32_t addr; 389 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 390 }; 391 392 393 struct dmub_rb_cmd_common { 394 struct dmub_cmd_header header; 395 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 396 }; 397 398 struct dmub_cmd_reg_wait_data { 399 uint32_t addr; 400 uint32_t mask; 401 uint32_t condition_field_value; 402 uint32_t time_out_us; 403 }; 404 405 struct dmub_rb_cmd_reg_wait { 406 struct dmub_cmd_header header; 407 struct dmub_cmd_reg_wait_data reg_wait; 408 }; 409 410 struct dmub_cmd_PLAT_54186_wa { 411 uint32_t DCSURF_SURFACE_CONTROL; 412 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 413 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 414 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 415 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 416 struct { 417 uint8_t hubp_inst : 4; 418 uint8_t tmz_surface : 1; 419 uint8_t immediate :1; 420 uint8_t vmid : 4; 421 uint8_t grph_stereo : 1; 422 uint32_t reserved : 21; 423 } flip_params; 424 uint32_t reserved[9]; 425 }; 426 427 struct dmub_rb_cmd_PLAT_54186_wa { 428 struct dmub_cmd_header header; 429 struct dmub_cmd_PLAT_54186_wa flip; 430 }; 431 432 struct dmub_rb_cmd_mall { 433 struct dmub_cmd_header header; 434 union dmub_addr cursor_copy_src; 435 union dmub_addr cursor_copy_dst; 436 uint32_t tmr_delay; 437 uint32_t tmr_scale; 438 uint16_t cursor_width; 439 uint16_t cursor_pitch; 440 uint16_t cursor_height; 441 uint8_t cursor_bpp; 442 }; 443 444 struct dmub_cmd_digx_encoder_control_data { 445 union dig_encoder_control_parameters_v1_5 dig; 446 }; 447 448 struct dmub_rb_cmd_digx_encoder_control { 449 struct dmub_cmd_header header; 450 struct dmub_cmd_digx_encoder_control_data encoder_control; 451 }; 452 453 struct dmub_cmd_set_pixel_clock_data { 454 struct set_pixel_clock_parameter_v1_7 clk; 455 }; 456 457 struct dmub_rb_cmd_set_pixel_clock { 458 struct dmub_cmd_header header; 459 struct dmub_cmd_set_pixel_clock_data pixel_clock; 460 }; 461 462 struct dmub_cmd_enable_disp_power_gating_data { 463 struct enable_disp_power_gating_parameters_v2_1 pwr; 464 }; 465 466 struct dmub_rb_cmd_enable_disp_power_gating { 467 struct dmub_cmd_header header; 468 struct dmub_cmd_enable_disp_power_gating_data power_gating; 469 }; 470 471 struct dmub_cmd_dig1_transmitter_control_data { 472 struct dig_transmitter_control_parameters_v1_6 dig; 473 }; 474 475 struct dmub_rb_cmd_dig1_transmitter_control { 476 struct dmub_cmd_header header; 477 struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 478 }; 479 480 struct dmub_rb_cmd_dpphy_init { 481 struct dmub_cmd_header header; 482 uint8_t reserved[60]; 483 }; 484 485 enum dp_aux_request_action { 486 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 487 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 488 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 489 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 490 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 491 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 492 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 493 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 494 }; 495 496 enum aux_return_code_type { 497 AUX_RET_SUCCESS = 0, 498 AUX_RET_ERROR_TIMEOUT, 499 AUX_RET_ERROR_NO_DATA, 500 AUX_RET_ERROR_INVALID_OPERATION, 501 AUX_RET_ERROR_PROTOCOL_ERROR, 502 }; 503 504 /* DP AUX command */ 505 struct aux_transaction_parameters { 506 uint8_t is_i2c_over_aux; 507 uint8_t action; 508 uint8_t length; 509 uint8_t pad; 510 uint32_t address; 511 uint8_t data[16]; 512 }; 513 514 struct dmub_cmd_dp_aux_control_data { 515 uint32_t handle; 516 uint8_t port_index; 517 uint8_t sw_crc_enabled; 518 uint16_t timeout; 519 struct aux_transaction_parameters dpaux; 520 }; 521 522 struct dmub_rb_cmd_dp_aux_access { 523 struct dmub_cmd_header header; 524 struct dmub_cmd_dp_aux_control_data aux_control; 525 }; 526 527 struct dmub_rb_cmd_outbox1_enable { 528 struct dmub_cmd_header header; 529 uint32_t enable; 530 }; 531 532 /* DP AUX Reply command - OutBox Cmd */ 533 struct aux_reply_data { 534 uint8_t command; 535 uint8_t length; 536 uint8_t pad[2]; 537 uint8_t data[16]; 538 }; 539 540 struct aux_reply_control_data { 541 uint32_t handle; 542 uint8_t phy_port_index; 543 uint8_t result; 544 uint16_t pad; 545 }; 546 547 struct dmub_rb_cmd_dp_aux_reply { 548 struct dmub_cmd_header header; 549 struct aux_reply_control_data control; 550 struct aux_reply_data reply_data; 551 }; 552 553 /* DP HPD Notify command - OutBox Cmd */ 554 enum dp_hpd_type { 555 DP_HPD = 0, 556 DP_IRQ 557 }; 558 559 enum dp_hpd_status { 560 DP_HPD_UNPLUG = 0, 561 DP_HPD_PLUG 562 }; 563 564 struct dp_hpd_data { 565 uint8_t phy_port_index; 566 uint8_t hpd_type; 567 uint8_t hpd_status; 568 uint8_t pad; 569 }; 570 571 struct dmub_rb_cmd_dp_hpd_notify { 572 struct dmub_cmd_header header; 573 struct dp_hpd_data hpd_data; 574 }; 575 576 /* 577 * Command IDs should be treated as stable ABI. 578 * Do not reuse or modify IDs. 579 */ 580 581 enum dmub_cmd_psr_type { 582 DMUB_CMD__PSR_SET_VERSION = 0, 583 DMUB_CMD__PSR_COPY_SETTINGS = 1, 584 DMUB_CMD__PSR_ENABLE = 2, 585 DMUB_CMD__PSR_DISABLE = 3, 586 DMUB_CMD__PSR_SET_LEVEL = 4, 587 DMUB_CMD__PSR_FORCE_STATIC = 5, 588 }; 589 590 enum psr_version { 591 PSR_VERSION_1 = 0, 592 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 593 }; 594 595 enum dmub_cmd_mall_type { 596 DMUB_CMD__MALL_ACTION_ALLOW = 0, 597 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 598 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 599 }; 600 601 struct dmub_cmd_psr_copy_settings_data { 602 union dmub_psr_debug_flags debug; 603 uint16_t psr_level; 604 uint8_t dpp_inst; 605 uint8_t mpcc_inst; 606 uint8_t opp_inst; 607 uint8_t otg_inst; 608 uint8_t digfe_inst; 609 uint8_t digbe_inst; 610 uint8_t dpphy_inst; 611 uint8_t aux_inst; 612 uint8_t smu_optimizations_en; 613 uint8_t frame_delay; 614 uint8_t frame_cap_ind; 615 uint8_t pad[3]; 616 uint16_t init_sdp_deadline; 617 uint16_t pad2; 618 }; 619 620 struct dmub_rb_cmd_psr_copy_settings { 621 struct dmub_cmd_header header; 622 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 623 }; 624 625 struct dmub_cmd_psr_set_level_data { 626 uint16_t psr_level; 627 uint8_t pad[2]; 628 }; 629 630 struct dmub_rb_cmd_psr_set_level { 631 struct dmub_cmd_header header; 632 struct dmub_cmd_psr_set_level_data psr_set_level_data; 633 }; 634 635 struct dmub_rb_cmd_psr_enable { 636 struct dmub_cmd_header header; 637 }; 638 639 struct dmub_cmd_psr_set_version_data { 640 enum psr_version version; // PSR version 1 or 2 641 }; 642 643 struct dmub_rb_cmd_psr_set_version { 644 struct dmub_cmd_header header; 645 struct dmub_cmd_psr_set_version_data psr_set_version_data; 646 }; 647 648 struct dmub_rb_cmd_psr_force_static { 649 struct dmub_cmd_header header; 650 }; 651 652 union dmub_hw_lock_flags { 653 struct { 654 uint8_t lock_pipe : 1; 655 uint8_t lock_cursor : 1; 656 uint8_t lock_dig : 1; 657 uint8_t triple_buffer_lock : 1; 658 } bits; 659 660 uint8_t u8All; 661 }; 662 663 struct dmub_hw_lock_inst_flags { 664 uint8_t otg_inst; 665 uint8_t opp_inst; 666 uint8_t dig_inst; 667 uint8_t pad; 668 }; 669 670 enum hw_lock_client { 671 HW_LOCK_CLIENT_DRIVER = 0, 672 HW_LOCK_CLIENT_FW, 673 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 674 }; 675 676 struct dmub_cmd_lock_hw_data { 677 enum hw_lock_client client; 678 struct dmub_hw_lock_inst_flags inst_flags; 679 union dmub_hw_lock_flags hw_locks; 680 uint8_t lock; 681 uint8_t should_release; 682 uint8_t pad; 683 }; 684 685 struct dmub_rb_cmd_lock_hw { 686 struct dmub_cmd_header header; 687 struct dmub_cmd_lock_hw_data lock_hw_data; 688 }; 689 690 enum dmub_cmd_abm_type { 691 DMUB_CMD__ABM_INIT_CONFIG = 0, 692 DMUB_CMD__ABM_SET_PIPE = 1, 693 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 694 DMUB_CMD__ABM_SET_LEVEL = 3, 695 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 696 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 697 }; 698 699 #define NUM_AMBI_LEVEL 5 700 #define NUM_AGGR_LEVEL 4 701 #define NUM_POWER_FN_SEGS 8 702 #define NUM_BL_CURVE_SEGS 16 703 704 /* 705 * Parameters for ABM2.4 algorithm. 706 * Padded explicitly to 32-bit boundary. 707 */ 708 struct abm_config_table { 709 /* Parameters for crgb conversion */ 710 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 711 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 15B 712 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 31B 713 714 /* Parameters for custom curve */ 715 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 47B 716 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 79B 717 718 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 111B 719 uint16_t min_abm_backlight; // 121B 720 721 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 123B 722 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 143B 723 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 163B 724 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 183B 725 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 203B 726 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 207B 727 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 211B 728 uint8_t min_knee[NUM_AGGR_LEVEL]; // 215B 729 uint8_t max_knee[NUM_AGGR_LEVEL]; // 219B 730 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 223B 731 uint8_t pad3[3]; // 228B 732 }; 733 734 struct dmub_cmd_abm_set_pipe_data { 735 uint8_t otg_inst; 736 uint8_t panel_inst; 737 uint8_t set_pipe_option; 738 uint8_t ramping_boundary; // TODO: Remove this 739 }; 740 741 struct dmub_rb_cmd_abm_set_pipe { 742 struct dmub_cmd_header header; 743 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 744 }; 745 746 struct dmub_cmd_abm_set_backlight_data { 747 uint32_t frame_ramp; 748 uint32_t backlight_user_level; 749 }; 750 751 struct dmub_rb_cmd_abm_set_backlight { 752 struct dmub_cmd_header header; 753 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 754 }; 755 756 struct dmub_cmd_abm_set_level_data { 757 uint32_t level; 758 }; 759 760 struct dmub_rb_cmd_abm_set_level { 761 struct dmub_cmd_header header; 762 struct dmub_cmd_abm_set_level_data abm_set_level_data; 763 }; 764 765 struct dmub_cmd_abm_set_ambient_level_data { 766 uint32_t ambient_lux; 767 }; 768 769 struct dmub_rb_cmd_abm_set_ambient_level { 770 struct dmub_cmd_header header; 771 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 772 }; 773 774 struct dmub_cmd_abm_set_pwm_frac_data { 775 uint32_t fractional_pwm; 776 }; 777 778 struct dmub_rb_cmd_abm_set_pwm_frac { 779 struct dmub_cmd_header header; 780 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 781 }; 782 783 struct dmub_cmd_abm_init_config_data { 784 union dmub_addr src; 785 uint16_t bytes; 786 }; 787 788 struct dmub_rb_cmd_abm_init_config { 789 struct dmub_cmd_header header; 790 struct dmub_cmd_abm_init_config_data abm_init_config_data; 791 }; 792 793 union dmub_rb_cmd { 794 struct dmub_rb_cmd_lock_hw lock_hw; 795 struct dmub_rb_cmd_read_modify_write read_modify_write; 796 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 797 struct dmub_rb_cmd_burst_write burst_write; 798 struct dmub_rb_cmd_reg_wait reg_wait; 799 struct dmub_rb_cmd_common cmd_common; 800 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 801 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 802 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 803 struct dmub_rb_cmd_dpphy_init dpphy_init; 804 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 805 struct dmub_rb_cmd_psr_set_version psr_set_version; 806 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 807 struct dmub_rb_cmd_psr_enable psr_enable; 808 struct dmub_rb_cmd_psr_set_level psr_set_level; 809 struct dmub_rb_cmd_psr_force_static psr_force_static; 810 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 811 struct dmub_rb_cmd_mall mall; 812 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 813 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 814 struct dmub_rb_cmd_abm_set_level abm_set_level; 815 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 816 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 817 struct dmub_rb_cmd_abm_init_config abm_init_config; 818 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 819 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 820 }; 821 822 union dmub_rb_out_cmd { 823 struct dmub_rb_cmd_common cmd_common; 824 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 825 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 826 }; 827 #pragma pack(pop) 828 829 830 //============================================================================== 831 //</DMUB_CMD>=================================================================== 832 //============================================================================== 833 //< DMUB_RB>==================================================================== 834 //============================================================================== 835 836 #if defined(__cplusplus) 837 extern "C" { 838 #endif 839 840 struct dmub_rb_init_params { 841 void *ctx; 842 void *base_address; 843 uint32_t capacity; 844 uint32_t read_ptr; 845 uint32_t write_ptr; 846 }; 847 848 struct dmub_rb { 849 void *base_address; 850 uint32_t data_count; 851 uint32_t rptr; 852 uint32_t wrpt; 853 uint32_t capacity; 854 855 void *ctx; 856 void *dmub; 857 }; 858 859 860 static inline bool dmub_rb_empty(struct dmub_rb *rb) 861 { 862 return (rb->wrpt == rb->rptr); 863 } 864 865 static inline bool dmub_rb_full(struct dmub_rb *rb) 866 { 867 uint32_t data_count; 868 869 if (rb->wrpt >= rb->rptr) 870 data_count = rb->wrpt - rb->rptr; 871 else 872 data_count = rb->capacity - (rb->rptr - rb->wrpt); 873 874 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 875 } 876 877 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 878 const union dmub_rb_cmd *cmd) 879 { 880 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 881 const uint64_t *src = (const uint64_t *)cmd; 882 int i; 883 884 if (dmub_rb_full(rb)) 885 return false; 886 887 // copying data 888 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 889 *dst++ = *src++; 890 891 rb->wrpt += DMUB_RB_CMD_SIZE; 892 893 if (rb->wrpt >= rb->capacity) 894 rb->wrpt %= rb->capacity; 895 896 return true; 897 } 898 899 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 900 const union dmub_rb_out_cmd *cmd) 901 { 902 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 903 const uint8_t *src = (uint8_t *)cmd; 904 905 if (dmub_rb_full(rb)) 906 return false; 907 908 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 909 910 rb->wrpt += DMUB_RB_CMD_SIZE; 911 912 if (rb->wrpt >= rb->capacity) 913 rb->wrpt %= rb->capacity; 914 915 return true; 916 } 917 918 static inline bool dmub_rb_front(struct dmub_rb *rb, 919 union dmub_rb_cmd *cmd) 920 { 921 uint8_t *rd_ptr = (uint8_t *)rb->base_address + rb->rptr; 922 923 if (dmub_rb_empty(rb)) 924 return false; 925 926 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 927 928 return true; 929 } 930 931 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 932 union dmub_rb_out_cmd *cmd) 933 { 934 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 935 uint64_t *dst = (uint64_t *)cmd; 936 int i; 937 938 if (dmub_rb_empty(rb)) 939 return false; 940 941 // copying data 942 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 943 *dst++ = *src++; 944 945 return true; 946 } 947 948 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 949 { 950 if (dmub_rb_empty(rb)) 951 return false; 952 953 rb->rptr += DMUB_RB_CMD_SIZE; 954 955 if (rb->rptr >= rb->capacity) 956 rb->rptr %= rb->capacity; 957 958 return true; 959 } 960 961 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 962 { 963 uint32_t rptr = rb->rptr; 964 uint32_t wptr = rb->wrpt; 965 966 while (rptr != wptr) { 967 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 968 int i; 969 970 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 971 *data++; 972 973 rptr += DMUB_RB_CMD_SIZE; 974 if (rptr >= rb->capacity) 975 rptr %= rb->capacity; 976 } 977 } 978 979 static inline void dmub_rb_init(struct dmub_rb *rb, 980 struct dmub_rb_init_params *init_params) 981 { 982 rb->base_address = init_params->base_address; 983 rb->capacity = init_params->capacity; 984 rb->rptr = init_params->read_ptr; 985 rb->wrpt = init_params->write_ptr; 986 } 987 988 #if defined(__cplusplus) 989 } 990 #endif 991 992 //============================================================================== 993 //</DMUB_RB>==================================================================== 994 //============================================================================== 995 996 #endif /* _DMUB_CMD_H_ */ 997