1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 #include <stdarg.h> 34 35 #include "atomfirmware.h" 36 37 /* Firmware versioning. */ 38 #ifdef DMUB_EXPOSE_VERSION 39 #define DMUB_FW_VERSION_GIT_HASH 0x685065427 40 #define DMUB_FW_VERSION_MAJOR 0 41 #define DMUB_FW_VERSION_MINOR 0 42 #define DMUB_FW_VERSION_REVISION 44 43 #define DMUB_FW_VERSION_TEST 0 44 #define DMUB_FW_VERSION_VBIOS 0 45 #define DMUB_FW_VERSION_HOTFIX 0 46 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 47 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 48 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 49 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 50 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 51 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 52 53 #endif 54 55 //<DMUB_TYPES>================================================================== 56 /* Basic type definitions. */ 57 58 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 59 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 #define SET_ABM_PIPE_NORMAL 1 62 63 /* Maximum number of streams on any ASIC. */ 64 #define DMUB_MAX_STREAMS 6 65 66 /* Maximum number of planes on any ASIC. */ 67 #define DMUB_MAX_PLANES 6 68 69 #ifndef PHYSICAL_ADDRESS_LOC 70 #define PHYSICAL_ADDRESS_LOC union large_integer 71 #endif 72 73 #ifndef dmub_memcpy 74 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 75 #endif 76 77 #ifndef dmub_memset 78 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 79 #endif 80 81 #if defined(__cplusplus) 82 extern "C" { 83 #endif 84 85 #ifndef dmub_udelay 86 #define dmub_udelay(microseconds) udelay(microseconds) 87 #endif 88 89 union dmub_addr { 90 struct { 91 uint32_t low_part; 92 uint32_t high_part; 93 } u; 94 uint64_t quad_part; 95 }; 96 97 union dmub_psr_debug_flags { 98 struct { 99 uint32_t visual_confirm : 1; 100 uint32_t use_hw_lock_mgr : 1; 101 uint32_t log_line_nums : 1; 102 } bitfields; 103 104 uint32_t u32All; 105 }; 106 107 struct dmub_feature_caps { 108 uint8_t psr; 109 uint8_t reserved[7]; 110 }; 111 112 #if defined(__cplusplus) 113 } 114 #endif 115 116 //============================================================================== 117 //</DMUB_TYPES>================================================================= 118 //============================================================================== 119 //< DMUB_META>================================================================== 120 //============================================================================== 121 #pragma pack(push, 1) 122 123 /* Magic value for identifying dmub_fw_meta_info */ 124 #define DMUB_FW_META_MAGIC 0x444D5542 125 126 /* Offset from the end of the file to the dmub_fw_meta_info */ 127 #define DMUB_FW_META_OFFSET 0x24 128 129 /** 130 * struct dmub_fw_meta_info - metadata associated with fw binary 131 * 132 * NOTE: This should be considered a stable API. Fields should 133 * not be repurposed or reordered. New fields should be 134 * added instead to extend the structure. 135 * 136 * @magic_value: magic value identifying DMUB firmware meta info 137 * @fw_region_size: size of the firmware state region 138 * @trace_buffer_size: size of the tracebuffer region 139 * @fw_version: the firmware version information 140 * @dal_fw: 1 if the firmware is DAL 141 */ 142 struct dmub_fw_meta_info { 143 uint32_t magic_value; 144 uint32_t fw_region_size; 145 uint32_t trace_buffer_size; 146 uint32_t fw_version; 147 uint8_t dal_fw; 148 uint8_t reserved[3]; 149 }; 150 151 /* Ensure that the structure remains 64 bytes. */ 152 union dmub_fw_meta { 153 struct dmub_fw_meta_info info; 154 uint8_t reserved[64]; 155 }; 156 157 #pragma pack(pop) 158 159 //============================================================================== 160 //< DMUB_STATUS>================================================================ 161 //============================================================================== 162 163 /** 164 * DMCUB scratch registers can be used to determine firmware status. 165 * Current scratch register usage is as follows: 166 * 167 * SCRATCH0: FW Boot Status register 168 * SCRATCH15: FW Boot Options register 169 */ 170 171 /* Register bit definition for SCRATCH0 */ 172 union dmub_fw_boot_status { 173 struct { 174 uint32_t dal_fw : 1; 175 uint32_t mailbox_rdy : 1; 176 uint32_t optimized_init_done : 1; 177 uint32_t restore_required : 1; 178 } bits; 179 uint32_t all; 180 }; 181 182 enum dmub_fw_boot_status_bit { 183 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), 184 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), 185 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 186 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), 187 }; 188 189 /* Register bit definition for SCRATCH15 */ 190 union dmub_fw_boot_options { 191 struct { 192 uint32_t pemu_env : 1; 193 uint32_t fpga_env : 1; 194 uint32_t optimized_init : 1; 195 uint32_t skip_phy_access : 1; 196 uint32_t disable_clk_gate: 1; 197 uint32_t skip_phy_init_panel_sequence: 1; 198 uint32_t reserved : 26; 199 } bits; 200 uint32_t all; 201 }; 202 203 enum dmub_fw_boot_options_bit { 204 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), 205 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), 206 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 207 }; 208 209 //============================================================================== 210 //</DMUB_STATUS>================================================================ 211 //============================================================================== 212 //< DMUB_VBIOS>================================================================= 213 //============================================================================== 214 215 /* 216 * Command IDs should be treated as stable ABI. 217 * Do not reuse or modify IDs. 218 */ 219 220 enum dmub_cmd_vbios_type { 221 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 222 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 223 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 224 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 225 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 226 }; 227 228 //============================================================================== 229 //</DMUB_VBIOS>================================================================= 230 //============================================================================== 231 //< DMUB_GPINT>================================================================= 232 //============================================================================== 233 234 /** 235 * The shifts and masks below may alternatively be used to format and read 236 * the command register bits. 237 */ 238 239 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 240 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 241 242 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 243 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 244 245 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 246 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 247 248 /** 249 * Command responses. 250 */ 251 252 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 253 254 /** 255 * The register format for sending a command via the GPINT. 256 */ 257 union dmub_gpint_data_register { 258 struct { 259 uint32_t param : 16; 260 uint32_t command_code : 12; 261 uint32_t status : 4; 262 } bits; 263 uint32_t all; 264 }; 265 266 /* 267 * Command IDs should be treated as stable ABI. 268 * Do not reuse or modify IDs. 269 */ 270 271 enum dmub_gpint_command { 272 DMUB_GPINT__INVALID_COMMAND = 0, 273 DMUB_GPINT__GET_FW_VERSION = 1, 274 DMUB_GPINT__STOP_FW = 2, 275 DMUB_GPINT__GET_PSR_STATE = 7, 276 /** 277 * DESC: Notifies DMCUB of the currently active streams. 278 * ARGS: Stream mask, 1 bit per active stream index. 279 */ 280 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 281 DMUB_GPINT__PSR_RESIDENCY = 9, 282 }; 283 284 //============================================================================== 285 //</DMUB_GPINT>================================================================= 286 //============================================================================== 287 //< DMUB_CMD>=================================================================== 288 //============================================================================== 289 290 #define DMUB_RB_CMD_SIZE 64 291 #define DMUB_RB_MAX_ENTRY 128 292 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 293 #define REG_SET_MASK 0xFFFF 294 295 /* 296 * Command IDs should be treated as stable ABI. 297 * Do not reuse or modify IDs. 298 */ 299 300 enum dmub_cmd_type { 301 DMUB_CMD__NULL = 0, 302 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 303 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 304 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 305 DMUB_CMD__REG_REG_WAIT = 4, 306 DMUB_CMD__PLAT_54186_WA = 5, 307 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 308 DMUB_CMD__PSR = 64, 309 DMUB_CMD__MALL = 65, 310 DMUB_CMD__ABM = 66, 311 DMUB_CMD__HW_LOCK = 69, 312 DMUB_CMD__DP_AUX_ACCESS = 70, 313 DMUB_CMD__OUTBOX1_ENABLE = 71, 314 DMUB_CMD__VBIOS = 128, 315 }; 316 317 enum dmub_out_cmd_type { 318 DMUB_OUT_CMD__NULL = 0, 319 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 320 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 321 }; 322 323 #pragma pack(push, 1) 324 325 struct dmub_cmd_header { 326 unsigned int type : 8; 327 unsigned int sub_type : 8; 328 unsigned int ret_status : 1; 329 unsigned int reserved0 : 7; 330 unsigned int payload_bytes : 6; /* up to 60 bytes */ 331 unsigned int reserved1 : 2; 332 }; 333 334 /* 335 * Read modify write 336 * 337 * 60 payload bytes can hold up to 5 sets of read modify writes, 338 * each take 3 dwords. 339 * 340 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 341 * 342 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 343 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 344 */ 345 struct dmub_cmd_read_modify_write_sequence { 346 uint32_t addr; 347 uint32_t modify_mask; 348 uint32_t modify_value; 349 }; 350 351 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 352 struct dmub_rb_cmd_read_modify_write { 353 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 354 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 355 }; 356 357 /* 358 * Update a register with specified masks and values sequeunce 359 * 360 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 361 * 362 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 363 * 364 * 365 * USE CASE: 366 * 1. auto-increment register where additional read would update pointer and produce wrong result 367 * 2. toggle a bit without read in the middle 368 */ 369 370 struct dmub_cmd_reg_field_update_sequence { 371 uint32_t modify_mask; // 0xffff'ffff to skip initial read 372 uint32_t modify_value; 373 }; 374 375 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 376 struct dmub_rb_cmd_reg_field_update_sequence { 377 struct dmub_cmd_header header; 378 uint32_t addr; 379 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 380 }; 381 382 /* 383 * Burst write 384 * 385 * support use case such as writing out LUTs. 386 * 387 * 60 payload bytes can hold up to 14 values to write to given address 388 * 389 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 390 */ 391 #define DMUB_BURST_WRITE_VALUES__MAX 14 392 struct dmub_rb_cmd_burst_write { 393 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 394 uint32_t addr; 395 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 396 }; 397 398 399 struct dmub_rb_cmd_common { 400 struct dmub_cmd_header header; 401 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 402 }; 403 404 struct dmub_cmd_reg_wait_data { 405 uint32_t addr; 406 uint32_t mask; 407 uint32_t condition_field_value; 408 uint32_t time_out_us; 409 }; 410 411 struct dmub_rb_cmd_reg_wait { 412 struct dmub_cmd_header header; 413 struct dmub_cmd_reg_wait_data reg_wait; 414 }; 415 416 struct dmub_cmd_PLAT_54186_wa { 417 uint32_t DCSURF_SURFACE_CONTROL; 418 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 419 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 420 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 421 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 422 struct { 423 uint8_t hubp_inst : 4; 424 uint8_t tmz_surface : 1; 425 uint8_t immediate :1; 426 uint8_t vmid : 4; 427 uint8_t grph_stereo : 1; 428 uint32_t reserved : 21; 429 } flip_params; 430 uint32_t reserved[9]; 431 }; 432 433 struct dmub_rb_cmd_PLAT_54186_wa { 434 struct dmub_cmd_header header; 435 struct dmub_cmd_PLAT_54186_wa flip; 436 }; 437 438 struct dmub_rb_cmd_mall { 439 struct dmub_cmd_header header; 440 union dmub_addr cursor_copy_src; 441 union dmub_addr cursor_copy_dst; 442 uint32_t tmr_delay; 443 uint32_t tmr_scale; 444 uint16_t cursor_width; 445 uint16_t cursor_pitch; 446 uint16_t cursor_height; 447 uint8_t cursor_bpp; 448 }; 449 450 struct dmub_cmd_digx_encoder_control_data { 451 union dig_encoder_control_parameters_v1_5 dig; 452 }; 453 454 struct dmub_rb_cmd_digx_encoder_control { 455 struct dmub_cmd_header header; 456 struct dmub_cmd_digx_encoder_control_data encoder_control; 457 }; 458 459 struct dmub_cmd_set_pixel_clock_data { 460 struct set_pixel_clock_parameter_v1_7 clk; 461 }; 462 463 struct dmub_rb_cmd_set_pixel_clock { 464 struct dmub_cmd_header header; 465 struct dmub_cmd_set_pixel_clock_data pixel_clock; 466 }; 467 468 struct dmub_cmd_enable_disp_power_gating_data { 469 struct enable_disp_power_gating_parameters_v2_1 pwr; 470 }; 471 472 struct dmub_rb_cmd_enable_disp_power_gating { 473 struct dmub_cmd_header header; 474 struct dmub_cmd_enable_disp_power_gating_data power_gating; 475 }; 476 477 struct dmub_cmd_dig1_transmitter_control_data { 478 struct dig_transmitter_control_parameters_v1_6 dig; 479 }; 480 481 struct dmub_rb_cmd_dig1_transmitter_control { 482 struct dmub_cmd_header header; 483 struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 484 }; 485 486 struct dmub_rb_cmd_dpphy_init { 487 struct dmub_cmd_header header; 488 uint8_t reserved[60]; 489 }; 490 491 enum dp_aux_request_action { 492 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 493 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 494 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 495 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 496 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 497 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 498 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 499 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 500 }; 501 502 enum aux_return_code_type { 503 AUX_RET_SUCCESS = 0, 504 AUX_RET_ERROR_TIMEOUT, 505 AUX_RET_ERROR_NO_DATA, 506 AUX_RET_ERROR_INVALID_OPERATION, 507 AUX_RET_ERROR_PROTOCOL_ERROR, 508 }; 509 510 /* DP AUX command */ 511 struct aux_transaction_parameters { 512 uint8_t is_i2c_over_aux; 513 uint8_t action; 514 uint8_t length; 515 uint8_t pad; 516 uint32_t address; 517 uint8_t data[16]; 518 }; 519 520 struct dmub_cmd_dp_aux_control_data { 521 uint32_t handle; 522 uint8_t port_index; 523 uint8_t sw_crc_enabled; 524 uint16_t timeout; 525 struct aux_transaction_parameters dpaux; 526 }; 527 528 struct dmub_rb_cmd_dp_aux_access { 529 struct dmub_cmd_header header; 530 struct dmub_cmd_dp_aux_control_data aux_control; 531 }; 532 533 struct dmub_rb_cmd_outbox1_enable { 534 struct dmub_cmd_header header; 535 uint32_t enable; 536 }; 537 538 /* DP AUX Reply command - OutBox Cmd */ 539 struct aux_reply_data { 540 uint8_t command; 541 uint8_t length; 542 uint8_t pad[2]; 543 uint8_t data[16]; 544 }; 545 546 struct aux_reply_control_data { 547 uint32_t handle; 548 uint8_t phy_port_index; 549 uint8_t result; 550 uint16_t pad; 551 }; 552 553 struct dmub_rb_cmd_dp_aux_reply { 554 struct dmub_cmd_header header; 555 struct aux_reply_control_data control; 556 struct aux_reply_data reply_data; 557 }; 558 559 /* DP HPD Notify command - OutBox Cmd */ 560 enum dp_hpd_type { 561 DP_HPD = 0, 562 DP_IRQ 563 }; 564 565 enum dp_hpd_status { 566 DP_HPD_UNPLUG = 0, 567 DP_HPD_PLUG 568 }; 569 570 struct dp_hpd_data { 571 uint8_t phy_port_index; 572 uint8_t hpd_type; 573 uint8_t hpd_status; 574 uint8_t pad; 575 }; 576 577 struct dmub_rb_cmd_dp_hpd_notify { 578 struct dmub_cmd_header header; 579 struct dp_hpd_data hpd_data; 580 }; 581 582 /* 583 * Command IDs should be treated as stable ABI. 584 * Do not reuse or modify IDs. 585 */ 586 587 enum dmub_cmd_psr_type { 588 DMUB_CMD__PSR_SET_VERSION = 0, 589 DMUB_CMD__PSR_COPY_SETTINGS = 1, 590 DMUB_CMD__PSR_ENABLE = 2, 591 DMUB_CMD__PSR_DISABLE = 3, 592 DMUB_CMD__PSR_SET_LEVEL = 4, 593 DMUB_CMD__PSR_FORCE_STATIC = 5, 594 }; 595 596 enum psr_version { 597 PSR_VERSION_1 = 0, 598 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 599 }; 600 601 enum dmub_cmd_mall_type { 602 DMUB_CMD__MALL_ACTION_ALLOW = 0, 603 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 604 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 605 }; 606 607 struct dmub_cmd_psr_copy_settings_data { 608 union dmub_psr_debug_flags debug; 609 uint16_t psr_level; 610 uint8_t dpp_inst; 611 /* opp_inst and mpcc_inst will not be used in dmub fw, 612 * dmub fw will get active opp by reading odm registers. 613 */ 614 uint8_t mpcc_inst; 615 uint8_t opp_inst; 616 617 uint8_t otg_inst; 618 uint8_t digfe_inst; 619 uint8_t digbe_inst; 620 uint8_t dpphy_inst; 621 uint8_t aux_inst; 622 uint8_t smu_optimizations_en; 623 uint8_t frame_delay; 624 uint8_t frame_cap_ind; 625 uint8_t pad[2]; 626 uint8_t multi_disp_optimizations_en; 627 uint16_t init_sdp_deadline; 628 uint16_t pad2; 629 }; 630 631 struct dmub_rb_cmd_psr_copy_settings { 632 struct dmub_cmd_header header; 633 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 634 }; 635 636 struct dmub_cmd_psr_set_level_data { 637 uint16_t psr_level; 638 uint8_t pad[2]; 639 }; 640 641 struct dmub_rb_cmd_psr_set_level { 642 struct dmub_cmd_header header; 643 struct dmub_cmd_psr_set_level_data psr_set_level_data; 644 }; 645 646 struct dmub_rb_cmd_psr_enable { 647 struct dmub_cmd_header header; 648 }; 649 650 struct dmub_cmd_psr_set_version_data { 651 enum psr_version version; // PSR version 1 or 2 652 }; 653 654 struct dmub_rb_cmd_psr_set_version { 655 struct dmub_cmd_header header; 656 struct dmub_cmd_psr_set_version_data psr_set_version_data; 657 }; 658 659 struct dmub_rb_cmd_psr_force_static { 660 struct dmub_cmd_header header; 661 }; 662 663 union dmub_hw_lock_flags { 664 struct { 665 uint8_t lock_pipe : 1; 666 uint8_t lock_cursor : 1; 667 uint8_t lock_dig : 1; 668 uint8_t triple_buffer_lock : 1; 669 } bits; 670 671 uint8_t u8All; 672 }; 673 674 struct dmub_hw_lock_inst_flags { 675 uint8_t otg_inst; 676 uint8_t opp_inst; 677 uint8_t dig_inst; 678 uint8_t pad; 679 }; 680 681 enum hw_lock_client { 682 HW_LOCK_CLIENT_DRIVER = 0, 683 HW_LOCK_CLIENT_FW, 684 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 685 }; 686 687 struct dmub_cmd_lock_hw_data { 688 enum hw_lock_client client; 689 struct dmub_hw_lock_inst_flags inst_flags; 690 union dmub_hw_lock_flags hw_locks; 691 uint8_t lock; 692 uint8_t should_release; 693 uint8_t pad; 694 }; 695 696 struct dmub_rb_cmd_lock_hw { 697 struct dmub_cmd_header header; 698 struct dmub_cmd_lock_hw_data lock_hw_data; 699 }; 700 701 enum dmub_cmd_abm_type { 702 DMUB_CMD__ABM_INIT_CONFIG = 0, 703 DMUB_CMD__ABM_SET_PIPE = 1, 704 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 705 DMUB_CMD__ABM_SET_LEVEL = 3, 706 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 707 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 708 }; 709 710 #define NUM_AMBI_LEVEL 5 711 #define NUM_AGGR_LEVEL 4 712 #define NUM_POWER_FN_SEGS 8 713 #define NUM_BL_CURVE_SEGS 16 714 715 /* 716 * Parameters for ABM2.4 algorithm. 717 * Padded explicitly to 32-bit boundary. 718 */ 719 struct abm_config_table { 720 /* Parameters for crgb conversion */ 721 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 722 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 15B 723 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 31B 724 725 /* Parameters for custom curve */ 726 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 47B 727 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 79B 728 729 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 111B 730 uint16_t min_abm_backlight; // 121B 731 732 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 123B 733 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 143B 734 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 163B 735 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 183B 736 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 203B 737 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 207B 738 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 211B 739 uint8_t min_knee[NUM_AGGR_LEVEL]; // 215B 740 uint8_t max_knee[NUM_AGGR_LEVEL]; // 219B 741 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 223B 742 uint8_t pad3[3]; // 228B 743 }; 744 745 struct dmub_cmd_abm_set_pipe_data { 746 uint8_t otg_inst; 747 uint8_t panel_inst; 748 uint8_t set_pipe_option; 749 uint8_t ramping_boundary; // TODO: Remove this 750 }; 751 752 struct dmub_rb_cmd_abm_set_pipe { 753 struct dmub_cmd_header header; 754 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 755 }; 756 757 struct dmub_cmd_abm_set_backlight_data { 758 uint32_t frame_ramp; 759 uint32_t backlight_user_level; 760 }; 761 762 struct dmub_rb_cmd_abm_set_backlight { 763 struct dmub_cmd_header header; 764 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 765 }; 766 767 struct dmub_cmd_abm_set_level_data { 768 uint32_t level; 769 }; 770 771 struct dmub_rb_cmd_abm_set_level { 772 struct dmub_cmd_header header; 773 struct dmub_cmd_abm_set_level_data abm_set_level_data; 774 }; 775 776 struct dmub_cmd_abm_set_ambient_level_data { 777 uint32_t ambient_lux; 778 }; 779 780 struct dmub_rb_cmd_abm_set_ambient_level { 781 struct dmub_cmd_header header; 782 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 783 }; 784 785 struct dmub_cmd_abm_set_pwm_frac_data { 786 uint32_t fractional_pwm; 787 }; 788 789 struct dmub_rb_cmd_abm_set_pwm_frac { 790 struct dmub_cmd_header header; 791 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 792 }; 793 794 struct dmub_cmd_abm_init_config_data { 795 union dmub_addr src; 796 uint16_t bytes; 797 }; 798 799 struct dmub_rb_cmd_abm_init_config { 800 struct dmub_cmd_header header; 801 struct dmub_cmd_abm_init_config_data abm_init_config_data; 802 }; 803 804 struct dmub_cmd_query_feature_caps_data { 805 struct dmub_feature_caps feature_caps; 806 }; 807 808 struct dmub_rb_cmd_query_feature_caps { 809 struct dmub_cmd_header header; 810 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 811 }; 812 813 union dmub_rb_cmd { 814 struct dmub_rb_cmd_lock_hw lock_hw; 815 struct dmub_rb_cmd_read_modify_write read_modify_write; 816 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 817 struct dmub_rb_cmd_burst_write burst_write; 818 struct dmub_rb_cmd_reg_wait reg_wait; 819 struct dmub_rb_cmd_common cmd_common; 820 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 821 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 822 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 823 struct dmub_rb_cmd_dpphy_init dpphy_init; 824 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 825 struct dmub_rb_cmd_psr_set_version psr_set_version; 826 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 827 struct dmub_rb_cmd_psr_enable psr_enable; 828 struct dmub_rb_cmd_psr_set_level psr_set_level; 829 struct dmub_rb_cmd_psr_force_static psr_force_static; 830 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 831 struct dmub_rb_cmd_mall mall; 832 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 833 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 834 struct dmub_rb_cmd_abm_set_level abm_set_level; 835 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 836 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 837 struct dmub_rb_cmd_abm_init_config abm_init_config; 838 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 839 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 840 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 841 }; 842 843 union dmub_rb_out_cmd { 844 struct dmub_rb_cmd_common cmd_common; 845 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 846 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 847 }; 848 #pragma pack(pop) 849 850 851 //============================================================================== 852 //</DMUB_CMD>=================================================================== 853 //============================================================================== 854 //< DMUB_RB>==================================================================== 855 //============================================================================== 856 857 #if defined(__cplusplus) 858 extern "C" { 859 #endif 860 861 struct dmub_rb_init_params { 862 void *ctx; 863 void *base_address; 864 uint32_t capacity; 865 uint32_t read_ptr; 866 uint32_t write_ptr; 867 }; 868 869 struct dmub_rb { 870 void *base_address; 871 uint32_t data_count; 872 uint32_t rptr; 873 uint32_t wrpt; 874 uint32_t capacity; 875 876 void *ctx; 877 void *dmub; 878 }; 879 880 881 static inline bool dmub_rb_empty(struct dmub_rb *rb) 882 { 883 return (rb->wrpt == rb->rptr); 884 } 885 886 static inline bool dmub_rb_full(struct dmub_rb *rb) 887 { 888 uint32_t data_count; 889 890 if (rb->wrpt >= rb->rptr) 891 data_count = rb->wrpt - rb->rptr; 892 else 893 data_count = rb->capacity - (rb->rptr - rb->wrpt); 894 895 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 896 } 897 898 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 899 const union dmub_rb_cmd *cmd) 900 { 901 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 902 const uint64_t *src = (const uint64_t *)cmd; 903 uint8_t i; 904 905 if (dmub_rb_full(rb)) 906 return false; 907 908 // copying data 909 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 910 *dst++ = *src++; 911 912 rb->wrpt += DMUB_RB_CMD_SIZE; 913 914 if (rb->wrpt >= rb->capacity) 915 rb->wrpt %= rb->capacity; 916 917 return true; 918 } 919 920 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 921 const union dmub_rb_out_cmd *cmd) 922 { 923 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 924 const uint8_t *src = (uint8_t *)cmd; 925 926 if (dmub_rb_full(rb)) 927 return false; 928 929 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 930 931 rb->wrpt += DMUB_RB_CMD_SIZE; 932 933 if (rb->wrpt >= rb->capacity) 934 rb->wrpt %= rb->capacity; 935 936 return true; 937 } 938 939 static inline bool dmub_rb_front(struct dmub_rb *rb, 940 union dmub_rb_cmd **cmd) 941 { 942 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 943 944 if (dmub_rb_empty(rb)) 945 return false; 946 947 *cmd = (union dmub_rb_cmd *)rb_cmd; 948 949 return true; 950 } 951 952 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 953 union dmub_rb_out_cmd *cmd) 954 { 955 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 956 uint64_t *dst = (uint64_t *)cmd; 957 uint8_t i; 958 959 if (dmub_rb_empty(rb)) 960 return false; 961 962 // copying data 963 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 964 *dst++ = *src++; 965 966 return true; 967 } 968 969 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 970 { 971 if (dmub_rb_empty(rb)) 972 return false; 973 974 rb->rptr += DMUB_RB_CMD_SIZE; 975 976 if (rb->rptr >= rb->capacity) 977 rb->rptr %= rb->capacity; 978 979 return true; 980 } 981 982 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 983 { 984 uint32_t rptr = rb->rptr; 985 uint32_t wptr = rb->wrpt; 986 987 while (rptr != wptr) { 988 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 989 uint8_t i; 990 991 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 992 *data++; 993 994 rptr += DMUB_RB_CMD_SIZE; 995 if (rptr >= rb->capacity) 996 rptr %= rb->capacity; 997 } 998 } 999 1000 static inline void dmub_rb_init(struct dmub_rb *rb, 1001 struct dmub_rb_init_params *init_params) 1002 { 1003 rb->base_address = init_params->base_address; 1004 rb->capacity = init_params->capacity; 1005 rb->rptr = init_params->read_ptr; 1006 rb->wrpt = init_params->write_ptr; 1007 } 1008 1009 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 1010 union dmub_rb_cmd *cmd) 1011 { 1012 // Copy rb entry back into command 1013 uint8_t *rd_ptr = (rb->rptr == 0) ? 1014 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 1015 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 1016 1017 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 1018 } 1019 1020 #if defined(__cplusplus) 1021 } 1022 #endif 1023 1024 //============================================================================== 1025 //</DMUB_RB>==================================================================== 1026 //============================================================================== 1027 1028 #endif /* _DMUB_CMD_H_ */ 1029