1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 #include <stdarg.h> 34 35 #include "atomfirmware.h" 36 37 /* Firmware versioning. */ 38 #ifdef DMUB_EXPOSE_VERSION 39 #define DMUB_FW_VERSION_GIT_HASH 0xf547f0b9d 40 #define DMUB_FW_VERSION_MAJOR 0 41 #define DMUB_FW_VERSION_MINOR 0 42 #define DMUB_FW_VERSION_REVISION 34 43 #define DMUB_FW_VERSION_TEST 0 44 #define DMUB_FW_VERSION_VBIOS 0 45 #define DMUB_FW_VERSION_HOTFIX 0 46 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 47 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 48 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 49 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 50 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 51 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 52 53 #endif 54 55 //<DMUB_TYPES>================================================================== 56 /* Basic type definitions. */ 57 58 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 59 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 60 #define SET_ABM_PIPE_NORMAL 1 61 62 /* Maximum number of streams on any ASIC. */ 63 #define DMUB_MAX_STREAMS 6 64 65 /* Maximum number of planes on any ASIC. */ 66 #define DMUB_MAX_PLANES 6 67 68 #ifndef PHYSICAL_ADDRESS_LOC 69 #define PHYSICAL_ADDRESS_LOC union large_integer 70 #endif 71 72 #if defined(__cplusplus) 73 extern "C" { 74 #endif 75 76 #ifndef dmub_memcpy 77 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 78 #endif 79 80 #ifndef dmub_memset 81 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 82 #endif 83 84 #ifndef dmub_udelay 85 #define dmub_udelay(microseconds) udelay(microseconds) 86 #endif 87 88 union dmub_addr { 89 struct { 90 uint32_t low_part; 91 uint32_t high_part; 92 } u; 93 uint64_t quad_part; 94 }; 95 96 union dmub_psr_debug_flags { 97 struct { 98 uint32_t visual_confirm : 1; 99 uint32_t use_hw_lock_mgr : 1; 100 uint32_t log_line_nums : 1; 101 } bitfields; 102 103 uint32_t u32All; 104 }; 105 106 #if defined(__cplusplus) 107 } 108 #endif 109 110 111 112 //============================================================================== 113 //</DMUB_TYPES>================================================================= 114 //============================================================================== 115 //< DMUB_META>================================================================== 116 //============================================================================== 117 #pragma pack(push, 1) 118 119 /* Magic value for identifying dmub_fw_meta_info */ 120 #define DMUB_FW_META_MAGIC 0x444D5542 121 122 /* Offset from the end of the file to the dmub_fw_meta_info */ 123 #define DMUB_FW_META_OFFSET 0x24 124 125 /** 126 * struct dmub_fw_meta_info - metadata associated with fw binary 127 * 128 * NOTE: This should be considered a stable API. Fields should 129 * not be repurposed or reordered. New fields should be 130 * added instead to extend the structure. 131 * 132 * @magic_value: magic value identifying DMUB firmware meta info 133 * @fw_region_size: size of the firmware state region 134 * @trace_buffer_size: size of the tracebuffer region 135 * @fw_version: the firmware version information 136 * @dal_fw: 1 if the firmware is DAL 137 */ 138 struct dmub_fw_meta_info { 139 uint32_t magic_value; 140 uint32_t fw_region_size; 141 uint32_t trace_buffer_size; 142 uint32_t fw_version; 143 uint8_t dal_fw; 144 uint8_t reserved[3]; 145 }; 146 147 /* Ensure that the structure remains 64 bytes. */ 148 union dmub_fw_meta { 149 struct dmub_fw_meta_info info; 150 uint8_t reserved[64]; 151 }; 152 153 #pragma pack(pop) 154 155 //============================================================================== 156 //< DMUB_STATUS>================================================================ 157 //============================================================================== 158 159 /** 160 * DMCUB scratch registers can be used to determine firmware status. 161 * Current scratch register usage is as follows: 162 * 163 * SCRATCH0: FW Boot Status register 164 * SCRATCH15: FW Boot Options register 165 */ 166 167 /* Register bit definition for SCRATCH0 */ 168 union dmub_fw_boot_status { 169 struct { 170 uint32_t dal_fw : 1; 171 uint32_t mailbox_rdy : 1; 172 uint32_t optimized_init_done : 1; 173 uint32_t restore_required : 1; 174 } bits; 175 uint32_t all; 176 }; 177 178 enum dmub_fw_boot_status_bit { 179 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), 180 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), 181 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 182 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), 183 }; 184 185 /* Register bit definition for SCRATCH15 */ 186 union dmub_fw_boot_options { 187 struct { 188 uint32_t pemu_env : 1; 189 uint32_t fpga_env : 1; 190 uint32_t optimized_init : 1; 191 uint32_t reserved : 29; 192 } bits; 193 uint32_t all; 194 }; 195 196 enum dmub_fw_boot_options_bit { 197 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), 198 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), 199 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 200 }; 201 202 //============================================================================== 203 //</DMUB_STATUS>================================================================ 204 //============================================================================== 205 //< DMUB_VBIOS>================================================================= 206 //============================================================================== 207 208 /* 209 * Command IDs should be treated as stable ABI. 210 * Do not reuse or modify IDs. 211 */ 212 213 enum dmub_cmd_vbios_type { 214 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 215 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 216 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 217 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 218 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 219 }; 220 221 //============================================================================== 222 //</DMUB_VBIOS>================================================================= 223 //============================================================================== 224 //< DMUB_GPINT>================================================================= 225 //============================================================================== 226 227 /** 228 * The shifts and masks below may alternatively be used to format and read 229 * the command register bits. 230 */ 231 232 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 233 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 234 235 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 236 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 237 238 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 239 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 240 241 /** 242 * Command responses. 243 */ 244 245 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 246 247 /** 248 * The register format for sending a command via the GPINT. 249 */ 250 union dmub_gpint_data_register { 251 struct { 252 uint32_t param : 16; 253 uint32_t command_code : 12; 254 uint32_t status : 4; 255 } bits; 256 uint32_t all; 257 }; 258 259 /* 260 * Command IDs should be treated as stable ABI. 261 * Do not reuse or modify IDs. 262 */ 263 264 enum dmub_gpint_command { 265 DMUB_GPINT__INVALID_COMMAND = 0, 266 DMUB_GPINT__GET_FW_VERSION = 1, 267 DMUB_GPINT__STOP_FW = 2, 268 DMUB_GPINT__GET_PSR_STATE = 7, 269 /** 270 * DESC: Notifies DMCUB of the currently active streams. 271 * ARGS: Stream mask, 1 bit per active stream index. 272 */ 273 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 274 }; 275 276 //============================================================================== 277 //</DMUB_GPINT>================================================================= 278 //============================================================================== 279 //< DMUB_CMD>=================================================================== 280 //============================================================================== 281 282 #define DMUB_RB_CMD_SIZE 64 283 #define DMUB_RB_MAX_ENTRY 128 284 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 285 #define REG_SET_MASK 0xFFFF 286 287 /* 288 * Command IDs should be treated as stable ABI. 289 * Do not reuse or modify IDs. 290 */ 291 292 enum dmub_cmd_type { 293 DMUB_CMD__NULL = 0, 294 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 295 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 296 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 297 DMUB_CMD__REG_REG_WAIT = 4, 298 DMUB_CMD__PLAT_54186_WA = 5, 299 DMUB_CMD__PSR = 64, 300 DMUB_CMD__ABM = 66, 301 DMUB_CMD__HW_LOCK = 69, 302 DMUB_CMD__VBIOS = 128, 303 }; 304 305 enum dmub_out_cmd_type { 306 DMUB_OUT_CMD__NULL = 0, 307 }; 308 309 #pragma pack(push, 1) 310 311 struct dmub_cmd_header { 312 unsigned int type : 8; 313 unsigned int sub_type : 8; 314 unsigned int reserved0 : 8; 315 unsigned int payload_bytes : 6; /* up to 60 bytes */ 316 unsigned int reserved1 : 2; 317 }; 318 319 /* 320 * Read modify write 321 * 322 * 60 payload bytes can hold up to 5 sets of read modify writes, 323 * each take 3 dwords. 324 * 325 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 326 * 327 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 328 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 329 */ 330 struct dmub_cmd_read_modify_write_sequence { 331 uint32_t addr; 332 uint32_t modify_mask; 333 uint32_t modify_value; 334 }; 335 336 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 337 struct dmub_rb_cmd_read_modify_write { 338 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 339 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 340 }; 341 342 /* 343 * Update a register with specified masks and values sequeunce 344 * 345 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 346 * 347 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 348 * 349 * 350 * USE CASE: 351 * 1. auto-increment register where additional read would update pointer and produce wrong result 352 * 2. toggle a bit without read in the middle 353 */ 354 355 struct dmub_cmd_reg_field_update_sequence { 356 uint32_t modify_mask; // 0xffff'ffff to skip initial read 357 uint32_t modify_value; 358 }; 359 360 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 361 struct dmub_rb_cmd_reg_field_update_sequence { 362 struct dmub_cmd_header header; 363 uint32_t addr; 364 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 365 }; 366 367 /* 368 * Burst write 369 * 370 * support use case such as writing out LUTs. 371 * 372 * 60 payload bytes can hold up to 14 values to write to given address 373 * 374 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 375 */ 376 #define DMUB_BURST_WRITE_VALUES__MAX 14 377 struct dmub_rb_cmd_burst_write { 378 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 379 uint32_t addr; 380 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 381 }; 382 383 384 struct dmub_rb_cmd_common { 385 struct dmub_cmd_header header; 386 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 387 }; 388 389 struct dmub_cmd_reg_wait_data { 390 uint32_t addr; 391 uint32_t mask; 392 uint32_t condition_field_value; 393 uint32_t time_out_us; 394 }; 395 396 struct dmub_rb_cmd_reg_wait { 397 struct dmub_cmd_header header; 398 struct dmub_cmd_reg_wait_data reg_wait; 399 }; 400 401 struct dmub_cmd_PLAT_54186_wa { 402 uint32_t DCSURF_SURFACE_CONTROL; 403 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 404 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 405 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 406 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 407 struct { 408 uint8_t hubp_inst : 4; 409 uint8_t tmz_surface : 1; 410 uint8_t immediate :1; 411 uint8_t vmid : 4; 412 uint8_t grph_stereo : 1; 413 uint32_t reserved : 21; 414 } flip_params; 415 uint32_t reserved[9]; 416 }; 417 418 struct dmub_rb_cmd_PLAT_54186_wa { 419 struct dmub_cmd_header header; 420 struct dmub_cmd_PLAT_54186_wa flip; 421 }; 422 423 struct dmub_cmd_digx_encoder_control_data { 424 union dig_encoder_control_parameters_v1_5 dig; 425 }; 426 427 struct dmub_rb_cmd_digx_encoder_control { 428 struct dmub_cmd_header header; 429 struct dmub_cmd_digx_encoder_control_data encoder_control; 430 }; 431 432 struct dmub_cmd_set_pixel_clock_data { 433 struct set_pixel_clock_parameter_v1_7 clk; 434 }; 435 436 struct dmub_rb_cmd_set_pixel_clock { 437 struct dmub_cmd_header header; 438 struct dmub_cmd_set_pixel_clock_data pixel_clock; 439 }; 440 441 struct dmub_cmd_enable_disp_power_gating_data { 442 struct enable_disp_power_gating_parameters_v2_1 pwr; 443 }; 444 445 struct dmub_rb_cmd_enable_disp_power_gating { 446 struct dmub_cmd_header header; 447 struct dmub_cmd_enable_disp_power_gating_data power_gating; 448 }; 449 450 struct dmub_cmd_dig1_transmitter_control_data { 451 struct dig_transmitter_control_parameters_v1_6 dig; 452 }; 453 454 struct dmub_rb_cmd_dig1_transmitter_control { 455 struct dmub_cmd_header header; 456 struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 457 }; 458 459 struct dmub_rb_cmd_dpphy_init { 460 struct dmub_cmd_header header; 461 uint8_t reserved[60]; 462 }; 463 464 /* 465 * Command IDs should be treated as stable ABI. 466 * Do not reuse or modify IDs. 467 */ 468 469 enum dmub_cmd_psr_type { 470 DMUB_CMD__PSR_SET_VERSION = 0, 471 DMUB_CMD__PSR_COPY_SETTINGS = 1, 472 DMUB_CMD__PSR_ENABLE = 2, 473 DMUB_CMD__PSR_DISABLE = 3, 474 DMUB_CMD__PSR_SET_LEVEL = 4, 475 }; 476 477 enum psr_version { 478 PSR_VERSION_1 = 0, 479 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 480 }; 481 482 struct dmub_cmd_psr_copy_settings_data { 483 union dmub_psr_debug_flags debug; 484 uint16_t psr_level; 485 uint8_t dpp_inst; 486 uint8_t mpcc_inst; 487 uint8_t opp_inst; 488 uint8_t otg_inst; 489 uint8_t digfe_inst; 490 uint8_t digbe_inst; 491 uint8_t dpphy_inst; 492 uint8_t aux_inst; 493 uint8_t smu_optimizations_en; 494 uint8_t frame_delay; 495 uint8_t frame_cap_ind; 496 uint8_t pad[3]; 497 uint16_t init_sdp_deadline; 498 uint16_t pad2; 499 }; 500 501 struct dmub_rb_cmd_psr_copy_settings { 502 struct dmub_cmd_header header; 503 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 504 }; 505 506 struct dmub_cmd_psr_set_level_data { 507 uint16_t psr_level; 508 uint8_t pad[2]; 509 }; 510 511 struct dmub_rb_cmd_psr_set_level { 512 struct dmub_cmd_header header; 513 struct dmub_cmd_psr_set_level_data psr_set_level_data; 514 }; 515 516 struct dmub_rb_cmd_psr_enable { 517 struct dmub_cmd_header header; 518 }; 519 520 struct dmub_cmd_psr_set_version_data { 521 enum psr_version version; // PSR version 1 or 2 522 }; 523 524 struct dmub_rb_cmd_psr_set_version { 525 struct dmub_cmd_header header; 526 struct dmub_cmd_psr_set_version_data psr_set_version_data; 527 }; 528 529 union dmub_hw_lock_flags { 530 struct { 531 uint8_t lock_pipe : 1; 532 uint8_t lock_cursor : 1; 533 uint8_t lock_dig : 1; 534 uint8_t triple_buffer_lock : 1; 535 } bits; 536 537 uint8_t u8All; 538 }; 539 540 struct dmub_hw_lock_inst_flags { 541 uint8_t otg_inst; 542 uint8_t opp_inst; 543 uint8_t dig_inst; 544 uint8_t pad; 545 }; 546 547 enum hw_lock_client { 548 HW_LOCK_CLIENT_DRIVER = 0, 549 HW_LOCK_CLIENT_FW, 550 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 551 }; 552 553 struct dmub_cmd_lock_hw_data { 554 enum hw_lock_client client; 555 struct dmub_hw_lock_inst_flags inst_flags; 556 union dmub_hw_lock_flags hw_locks; 557 uint8_t lock; 558 uint8_t should_release; 559 uint8_t pad; 560 }; 561 562 struct dmub_rb_cmd_lock_hw { 563 struct dmub_cmd_header header; 564 struct dmub_cmd_lock_hw_data lock_hw_data; 565 }; 566 567 enum dmub_cmd_abm_type { 568 DMUB_CMD__ABM_INIT_CONFIG = 0, 569 DMUB_CMD__ABM_SET_PIPE = 1, 570 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 571 DMUB_CMD__ABM_SET_LEVEL = 3, 572 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 573 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 574 }; 575 576 #define NUM_AMBI_LEVEL 5 577 #define NUM_AGGR_LEVEL 4 578 #define NUM_POWER_FN_SEGS 8 579 #define NUM_BL_CURVE_SEGS 16 580 581 /* 582 * Parameters for ABM2.4 algorithm. 583 * Padded explicitly to 32-bit boundary. 584 */ 585 struct abm_config_table { 586 /* Parameters for crgb conversion */ 587 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 588 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 15B 589 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 31B 590 591 /* Parameters for custom curve */ 592 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 47B 593 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 79B 594 595 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 111B 596 uint16_t min_abm_backlight; // 121B 597 598 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 123B 599 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 143B 600 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 163B 601 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 183B 602 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 203B 603 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 207B 604 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 211B 605 uint8_t min_knee[NUM_AGGR_LEVEL]; // 215B 606 uint8_t max_knee[NUM_AGGR_LEVEL]; // 219B 607 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 223B 608 uint8_t pad3[3]; // 228B 609 }; 610 611 struct dmub_cmd_abm_set_pipe_data { 612 uint8_t otg_inst; 613 uint8_t panel_inst; 614 uint8_t set_pipe_option; 615 uint8_t ramping_boundary; // TODO: Remove this 616 }; 617 618 struct dmub_rb_cmd_abm_set_pipe { 619 struct dmub_cmd_header header; 620 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 621 }; 622 623 struct dmub_cmd_abm_set_backlight_data { 624 uint32_t frame_ramp; 625 uint32_t backlight_user_level; 626 }; 627 628 struct dmub_rb_cmd_abm_set_backlight { 629 struct dmub_cmd_header header; 630 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 631 }; 632 633 struct dmub_cmd_abm_set_level_data { 634 uint32_t level; 635 }; 636 637 struct dmub_rb_cmd_abm_set_level { 638 struct dmub_cmd_header header; 639 struct dmub_cmd_abm_set_level_data abm_set_level_data; 640 }; 641 642 struct dmub_cmd_abm_set_ambient_level_data { 643 uint32_t ambient_lux; 644 }; 645 646 struct dmub_rb_cmd_abm_set_ambient_level { 647 struct dmub_cmd_header header; 648 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 649 }; 650 651 struct dmub_cmd_abm_set_pwm_frac_data { 652 uint32_t fractional_pwm; 653 }; 654 655 struct dmub_rb_cmd_abm_set_pwm_frac { 656 struct dmub_cmd_header header; 657 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 658 }; 659 660 struct dmub_cmd_abm_init_config_data { 661 union dmub_addr src; 662 uint16_t bytes; 663 }; 664 665 struct dmub_rb_cmd_abm_init_config { 666 struct dmub_cmd_header header; 667 struct dmub_cmd_abm_init_config_data abm_init_config_data; 668 }; 669 670 union dmub_rb_cmd { 671 struct dmub_rb_cmd_lock_hw lock_hw; 672 struct dmub_rb_cmd_read_modify_write read_modify_write; 673 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 674 struct dmub_rb_cmd_burst_write burst_write; 675 struct dmub_rb_cmd_reg_wait reg_wait; 676 struct dmub_rb_cmd_common cmd_common; 677 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 678 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 679 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 680 struct dmub_rb_cmd_dpphy_init dpphy_init; 681 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 682 struct dmub_rb_cmd_psr_set_version psr_set_version; 683 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 684 struct dmub_rb_cmd_psr_enable psr_enable; 685 struct dmub_rb_cmd_psr_set_level psr_set_level; 686 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 687 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 688 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 689 struct dmub_rb_cmd_abm_set_level abm_set_level; 690 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 691 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 692 struct dmub_rb_cmd_abm_init_config abm_init_config; 693 }; 694 695 #pragma pack(pop) 696 697 698 //============================================================================== 699 //</DMUB_CMD>=================================================================== 700 //============================================================================== 701 //< DMUB_RB>==================================================================== 702 //============================================================================== 703 704 #if defined(__cplusplus) 705 extern "C" { 706 #endif 707 708 struct dmub_rb_init_params { 709 void *ctx; 710 void *base_address; 711 uint32_t capacity; 712 uint32_t read_ptr; 713 uint32_t write_ptr; 714 }; 715 716 struct dmub_rb { 717 void *base_address; 718 uint32_t data_count; 719 uint32_t rptr; 720 uint32_t wrpt; 721 uint32_t capacity; 722 723 void *ctx; 724 void *dmub; 725 }; 726 727 728 static inline bool dmub_rb_empty(struct dmub_rb *rb) 729 { 730 return (rb->wrpt == rb->rptr); 731 } 732 733 static inline bool dmub_rb_full(struct dmub_rb *rb) 734 { 735 uint32_t data_count; 736 737 if (rb->wrpt >= rb->rptr) 738 data_count = rb->wrpt - rb->rptr; 739 else 740 data_count = rb->capacity - (rb->rptr - rb->wrpt); 741 742 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 743 } 744 745 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 746 const union dmub_rb_cmd *cmd) 747 { 748 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 749 const uint64_t *src = (const uint64_t *)cmd; 750 int i; 751 752 if (dmub_rb_full(rb)) 753 return false; 754 755 // copying data 756 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 757 *dst++ = *src++; 758 759 rb->wrpt += DMUB_RB_CMD_SIZE; 760 761 if (rb->wrpt >= rb->capacity) 762 rb->wrpt %= rb->capacity; 763 764 return true; 765 } 766 767 static inline bool dmub_rb_front(struct dmub_rb *rb, 768 union dmub_rb_cmd *cmd) 769 { 770 uint8_t *rd_ptr = (uint8_t *)rb->base_address + rb->rptr; 771 772 if (dmub_rb_empty(rb)) 773 return false; 774 775 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 776 777 return true; 778 } 779 780 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 781 { 782 if (dmub_rb_empty(rb)) 783 return false; 784 785 rb->rptr += DMUB_RB_CMD_SIZE; 786 787 if (rb->rptr >= rb->capacity) 788 rb->rptr %= rb->capacity; 789 790 return true; 791 } 792 793 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 794 { 795 uint32_t rptr = rb->rptr; 796 uint32_t wptr = rb->wrpt; 797 798 while (rptr != wptr) { 799 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 800 int i; 801 802 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 803 *data++; 804 805 rptr += DMUB_RB_CMD_SIZE; 806 if (rptr >= rb->capacity) 807 rptr %= rb->capacity; 808 } 809 } 810 811 static inline void dmub_rb_init(struct dmub_rb *rb, 812 struct dmub_rb_init_params *init_params) 813 { 814 rb->base_address = init_params->base_address; 815 rb->capacity = init_params->capacity; 816 rb->rptr = init_params->read_ptr; 817 rb->wrpt = init_params->write_ptr; 818 } 819 820 #if defined(__cplusplus) 821 } 822 #endif 823 824 //============================================================================== 825 //</DMUB_RB>==================================================================== 826 //============================================================================== 827 828 #endif /* _DMUB_CMD_H_ */ 829