1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of streams on any ASIC. */ 96 #define DMUB_MAX_STREAMS 6 97 98 /* Maximum number of planes on any ASIC. */ 99 #define DMUB_MAX_PLANES 6 100 101 /* Trace buffer offset for entry */ 102 #define TRACE_BUFFER_ENTRY_OFFSET 16 103 104 /** 105 * 106 * PSR control version legacy 107 */ 108 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 109 /** 110 * PSR control version with multi edp support 111 */ 112 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 113 114 115 /** 116 * ABM control version legacy 117 */ 118 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 119 120 /** 121 * ABM control version with multi edp support 122 */ 123 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 124 125 /** 126 * Physical framebuffer address location, 64-bit. 127 */ 128 #ifndef PHYSICAL_ADDRESS_LOC 129 #define PHYSICAL_ADDRESS_LOC union large_integer 130 #endif 131 132 /** 133 * OS/FW agnostic memcpy 134 */ 135 #ifndef dmub_memcpy 136 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 137 #endif 138 139 /** 140 * OS/FW agnostic memset 141 */ 142 #ifndef dmub_memset 143 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 144 #endif 145 146 #if defined(__cplusplus) 147 extern "C" { 148 #endif 149 150 /** 151 * OS/FW agnostic udelay 152 */ 153 #ifndef dmub_udelay 154 #define dmub_udelay(microseconds) udelay(microseconds) 155 #endif 156 157 /** 158 * union dmub_addr - DMUB physical/virtual 64-bit address. 159 */ 160 union dmub_addr { 161 struct { 162 uint32_t low_part; /**< Lower 32 bits */ 163 uint32_t high_part; /**< Upper 32 bits */ 164 } u; /*<< Low/high bit access */ 165 uint64_t quad_part; /*<< 64 bit address */ 166 }; 167 168 /** 169 * Flags that can be set by driver to change some PSR behaviour. 170 */ 171 union dmub_psr_debug_flags { 172 /** 173 * Debug flags. 174 */ 175 struct { 176 /** 177 * Enable visual confirm in FW. 178 */ 179 uint32_t visual_confirm : 1; 180 /** 181 * Use HW Lock Mgr object to do HW locking in FW. 182 */ 183 uint32_t use_hw_lock_mgr : 1; 184 185 /** 186 * Use TPS3 signal when restore main link. 187 */ 188 uint32_t force_wakeup_by_tps3 : 1; 189 } bitfields; 190 191 /** 192 * Union for debug flags. 193 */ 194 uint32_t u32All; 195 }; 196 197 /** 198 * DMUB feature capabilities. 199 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 200 */ 201 struct dmub_feature_caps { 202 /** 203 * Max PSR version supported by FW. 204 */ 205 uint8_t psr; 206 uint8_t reserved[7]; 207 }; 208 209 #if defined(__cplusplus) 210 } 211 #endif 212 213 //============================================================================== 214 //</DMUB_TYPES>================================================================= 215 //============================================================================== 216 //< DMUB_META>================================================================== 217 //============================================================================== 218 #pragma pack(push, 1) 219 220 /* Magic value for identifying dmub_fw_meta_info */ 221 #define DMUB_FW_META_MAGIC 0x444D5542 222 223 /* Offset from the end of the file to the dmub_fw_meta_info */ 224 #define DMUB_FW_META_OFFSET 0x24 225 226 /** 227 * struct dmub_fw_meta_info - metadata associated with fw binary 228 * 229 * NOTE: This should be considered a stable API. Fields should 230 * not be repurposed or reordered. New fields should be 231 * added instead to extend the structure. 232 * 233 * @magic_value: magic value identifying DMUB firmware meta info 234 * @fw_region_size: size of the firmware state region 235 * @trace_buffer_size: size of the tracebuffer region 236 * @fw_version: the firmware version information 237 * @dal_fw: 1 if the firmware is DAL 238 */ 239 struct dmub_fw_meta_info { 240 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 241 uint32_t fw_region_size; /**< size of the firmware state region */ 242 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 243 uint32_t fw_version; /**< the firmware version information */ 244 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 245 uint8_t reserved[3]; /**< padding bits */ 246 }; 247 248 /** 249 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 250 */ 251 union dmub_fw_meta { 252 struct dmub_fw_meta_info info; /**< metadata info */ 253 uint8_t reserved[64]; /**< padding bits */ 254 }; 255 256 #pragma pack(pop) 257 258 //============================================================================== 259 //< DMUB Trace Buffer>================================================================ 260 //============================================================================== 261 /** 262 * dmub_trace_code_t - firmware trace code, 32-bits 263 */ 264 typedef uint32_t dmub_trace_code_t; 265 266 /** 267 * struct dmcub_trace_buf_entry - Firmware trace entry 268 */ 269 struct dmcub_trace_buf_entry { 270 dmub_trace_code_t trace_code; /**< trace code for the event */ 271 uint32_t tick_count; /**< the tick count at time of trace */ 272 uint32_t param0; /**< trace defined parameter 0 */ 273 uint32_t param1; /**< trace defined parameter 1 */ 274 }; 275 276 //============================================================================== 277 //< DMUB_STATUS>================================================================ 278 //============================================================================== 279 280 /** 281 * DMCUB scratch registers can be used to determine firmware status. 282 * Current scratch register usage is as follows: 283 * 284 * SCRATCH0: FW Boot Status register 285 * SCRATCH5: LVTMA Status Register 286 * SCRATCH15: FW Boot Options register 287 */ 288 289 /** 290 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 291 */ 292 union dmub_fw_boot_status { 293 struct { 294 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 295 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 296 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 297 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 298 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 299 uint32_t reserved : 1; 300 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 301 302 } bits; /**< status bits */ 303 uint32_t all; /**< 32-bit access to status bits */ 304 }; 305 306 /** 307 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 308 */ 309 enum dmub_fw_boot_status_bit { 310 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 311 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 312 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 313 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 314 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 315 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 316 }; 317 318 /* Register bit definition for SCRATCH5 */ 319 union dmub_lvtma_status { 320 struct { 321 uint32_t psp_ok : 1; 322 uint32_t edp_on : 1; 323 uint32_t reserved : 30; 324 } bits; 325 uint32_t all; 326 }; 327 328 enum dmub_lvtma_status_bit { 329 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 330 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 331 }; 332 333 /** 334 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 335 */ 336 union dmub_fw_boot_options { 337 struct { 338 uint32_t pemu_env : 1; /**< 1 if PEMU */ 339 uint32_t fpga_env : 1; /**< 1 if FPGA */ 340 uint32_t optimized_init : 1; /**< 1 if optimized init */ 341 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 342 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 343 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 344 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 345 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 346 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 347 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 348 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 349 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 350 uint32_t power_optimization: 1; 351 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 352 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 353 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 354 355 uint32_t reserved : 17; /**< reserved */ 356 } bits; /**< boot bits */ 357 uint32_t all; /**< 32-bit access to bits */ 358 }; 359 360 enum dmub_fw_boot_options_bit { 361 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 362 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 363 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 364 }; 365 366 //============================================================================== 367 //</DMUB_STATUS>================================================================ 368 //============================================================================== 369 //< DMUB_VBIOS>================================================================= 370 //============================================================================== 371 372 /* 373 * enum dmub_cmd_vbios_type - VBIOS commands. 374 * 375 * Command IDs should be treated as stable ABI. 376 * Do not reuse or modify IDs. 377 */ 378 enum dmub_cmd_vbios_type { 379 /** 380 * Configures the DIG encoder. 381 */ 382 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 383 /** 384 * Controls the PHY. 385 */ 386 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 387 /** 388 * Sets the pixel clock/symbol clock. 389 */ 390 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 391 /** 392 * Enables or disables power gating. 393 */ 394 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 395 /** 396 * Controls embedded panels. 397 */ 398 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 399 /** 400 * Query DP alt status on a transmitter. 401 */ 402 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 403 }; 404 405 //============================================================================== 406 //</DMUB_VBIOS>================================================================= 407 //============================================================================== 408 //< DMUB_GPINT>================================================================= 409 //============================================================================== 410 411 /** 412 * The shifts and masks below may alternatively be used to format and read 413 * the command register bits. 414 */ 415 416 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 417 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 418 419 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 420 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 421 422 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 423 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 424 425 /** 426 * Command responses. 427 */ 428 429 /** 430 * Return response for DMUB_GPINT__STOP_FW command. 431 */ 432 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 433 434 /** 435 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 436 */ 437 union dmub_gpint_data_register { 438 struct { 439 uint32_t param : 16; /**< 16-bit parameter */ 440 uint32_t command_code : 12; /**< GPINT command */ 441 uint32_t status : 4; /**< Command status bit */ 442 } bits; /**< GPINT bit access */ 443 uint32_t all; /**< GPINT 32-bit access */ 444 }; 445 446 /* 447 * enum dmub_gpint_command - GPINT command to DMCUB FW 448 * 449 * Command IDs should be treated as stable ABI. 450 * Do not reuse or modify IDs. 451 */ 452 enum dmub_gpint_command { 453 /** 454 * Invalid command, ignored. 455 */ 456 DMUB_GPINT__INVALID_COMMAND = 0, 457 /** 458 * DESC: Queries the firmware version. 459 * RETURN: Firmware version. 460 */ 461 DMUB_GPINT__GET_FW_VERSION = 1, 462 /** 463 * DESC: Halts the firmware. 464 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 465 */ 466 DMUB_GPINT__STOP_FW = 2, 467 /** 468 * DESC: Get PSR state from FW. 469 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 470 */ 471 DMUB_GPINT__GET_PSR_STATE = 7, 472 /** 473 * DESC: Notifies DMCUB of the currently active streams. 474 * ARGS: Stream mask, 1 bit per active stream index. 475 */ 476 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 477 /** 478 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 479 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 480 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 481 * RETURN: PSR residency in milli-percent. 482 */ 483 DMUB_GPINT__PSR_RESIDENCY = 9, 484 485 /** 486 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 487 */ 488 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 489 }; 490 491 /** 492 * INBOX0 generic command definition 493 */ 494 union dmub_inbox0_cmd_common { 495 struct { 496 uint32_t command_code: 8; /**< INBOX0 command code */ 497 uint32_t param: 24; /**< 24-bit parameter */ 498 } bits; 499 uint32_t all; 500 }; 501 502 /** 503 * INBOX0 hw_lock command definition 504 */ 505 union dmub_inbox0_cmd_lock_hw { 506 struct { 507 uint32_t command_code: 8; 508 509 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 510 uint32_t hw_lock_client: 2; 511 512 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 513 uint32_t otg_inst: 3; 514 uint32_t opp_inst: 3; 515 uint32_t dig_inst: 3; 516 517 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 518 uint32_t lock_pipe: 1; 519 uint32_t lock_cursor: 1; 520 uint32_t lock_dig: 1; 521 uint32_t triple_buffer_lock: 1; 522 523 uint32_t lock: 1; /**< Lock */ 524 uint32_t should_release: 1; /**< Release */ 525 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 526 } bits; 527 uint32_t all; 528 }; 529 530 union dmub_inbox0_data_register { 531 union dmub_inbox0_cmd_common inbox0_cmd_common; 532 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 533 }; 534 535 enum dmub_inbox0_command { 536 /** 537 * DESC: Invalid command, ignored. 538 */ 539 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 540 /** 541 * DESC: Notification to acquire/release HW lock 542 * ARGS: 543 */ 544 DMUB_INBOX0_CMD__HW_LOCK = 1, 545 }; 546 //============================================================================== 547 //</DMUB_GPINT>================================================================= 548 //============================================================================== 549 //< DMUB_CMD>=================================================================== 550 //============================================================================== 551 552 /** 553 * Size in bytes of each DMUB command. 554 */ 555 #define DMUB_RB_CMD_SIZE 64 556 557 /** 558 * Maximum number of items in the DMUB ringbuffer. 559 */ 560 #define DMUB_RB_MAX_ENTRY 128 561 562 /** 563 * Ringbuffer size in bytes. 564 */ 565 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 566 567 /** 568 * REG_SET mask for reg offload. 569 */ 570 #define REG_SET_MASK 0xFFFF 571 572 /* 573 * enum dmub_cmd_type - DMUB inbox command. 574 * 575 * Command IDs should be treated as stable ABI. 576 * Do not reuse or modify IDs. 577 */ 578 enum dmub_cmd_type { 579 /** 580 * Invalid command. 581 */ 582 DMUB_CMD__NULL = 0, 583 /** 584 * Read modify write register sequence offload. 585 */ 586 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 587 /** 588 * Field update register sequence offload. 589 */ 590 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 591 /** 592 * Burst write sequence offload. 593 */ 594 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 595 /** 596 * Reg wait sequence offload. 597 */ 598 DMUB_CMD__REG_REG_WAIT = 4, 599 /** 600 * Workaround to avoid HUBP underflow during NV12 playback. 601 */ 602 DMUB_CMD__PLAT_54186_WA = 5, 603 /** 604 * Command type used to query FW feature caps. 605 */ 606 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 607 /** 608 * Command type used for all PSR commands. 609 */ 610 DMUB_CMD__PSR = 64, 611 /** 612 * Command type used for all MALL commands. 613 */ 614 DMUB_CMD__MALL = 65, 615 /** 616 * Command type used for all ABM commands. 617 */ 618 DMUB_CMD__ABM = 66, 619 /** 620 * Command type used for HW locking in FW. 621 */ 622 DMUB_CMD__HW_LOCK = 69, 623 /** 624 * Command type used to access DP AUX. 625 */ 626 DMUB_CMD__DP_AUX_ACCESS = 70, 627 /** 628 * Command type used for OUTBOX1 notification enable 629 */ 630 DMUB_CMD__OUTBOX1_ENABLE = 71, 631 632 /** 633 * Command type used for all idle optimization commands. 634 */ 635 DMUB_CMD__IDLE_OPT = 72, 636 /** 637 * Command type used for all clock manager commands. 638 */ 639 DMUB_CMD__CLK_MGR = 73, 640 /** 641 * Command type used for all panel control commands. 642 */ 643 DMUB_CMD__PANEL_CNTL = 74, 644 645 /** 646 * Command type used for interfacing with DPIA. 647 */ 648 DMUB_CMD__DPIA = 77, 649 /** 650 * Command type used for EDID CEA parsing 651 */ 652 DMUB_CMD__EDID_CEA = 79, 653 /** 654 * Command type used for getting usbc cable ID 655 */ 656 DMUB_CMD_GET_USBC_CABLE_ID = 81, 657 /** 658 * Command type used to query HPD state. 659 */ 660 DMUB_CMD__QUERY_HPD_STATE = 82, 661 /** 662 * Command type used for all VBIOS interface commands. 663 */ 664 DMUB_CMD__VBIOS = 128, 665 }; 666 667 /** 668 * enum dmub_out_cmd_type - DMUB outbox commands. 669 */ 670 enum dmub_out_cmd_type { 671 /** 672 * Invalid outbox command, ignored. 673 */ 674 DMUB_OUT_CMD__NULL = 0, 675 /** 676 * Command type used for DP AUX Reply data notification 677 */ 678 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 679 /** 680 * Command type used for DP HPD event notification 681 */ 682 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 683 /** 684 * Command type used for SET_CONFIG Reply notification 685 */ 686 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 687 }; 688 689 /* DMUB_CMD__DPIA command sub-types. */ 690 enum dmub_cmd_dpia_type { 691 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 692 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 693 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 694 }; 695 696 #pragma pack(push, 1) 697 698 /** 699 * struct dmub_cmd_header - Common command header fields. 700 */ 701 struct dmub_cmd_header { 702 unsigned int type : 8; /**< command type */ 703 unsigned int sub_type : 8; /**< command sub type */ 704 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 705 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 706 unsigned int reserved0 : 6; /**< reserved bits */ 707 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 708 unsigned int reserved1 : 2; /**< reserved bits */ 709 }; 710 711 /* 712 * struct dmub_cmd_read_modify_write_sequence - Read modify write 713 * 714 * 60 payload bytes can hold up to 5 sets of read modify writes, 715 * each take 3 dwords. 716 * 717 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 718 * 719 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 720 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 721 */ 722 struct dmub_cmd_read_modify_write_sequence { 723 uint32_t addr; /**< register address */ 724 uint32_t modify_mask; /**< modify mask */ 725 uint32_t modify_value; /**< modify value */ 726 }; 727 728 /** 729 * Maximum number of ops in read modify write sequence. 730 */ 731 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 732 733 /** 734 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 735 */ 736 struct dmub_rb_cmd_read_modify_write { 737 struct dmub_cmd_header header; /**< command header */ 738 /** 739 * Read modify write sequence. 740 */ 741 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 742 }; 743 744 /* 745 * Update a register with specified masks and values sequeunce 746 * 747 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 748 * 749 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 750 * 751 * 752 * USE CASE: 753 * 1. auto-increment register where additional read would update pointer and produce wrong result 754 * 2. toggle a bit without read in the middle 755 */ 756 757 struct dmub_cmd_reg_field_update_sequence { 758 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 759 uint32_t modify_value; /**< value to update with */ 760 }; 761 762 /** 763 * Maximum number of ops in field update sequence. 764 */ 765 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 766 767 /** 768 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 769 */ 770 struct dmub_rb_cmd_reg_field_update_sequence { 771 struct dmub_cmd_header header; /**< command header */ 772 uint32_t addr; /**< register address */ 773 /** 774 * Field update sequence. 775 */ 776 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 777 }; 778 779 780 /** 781 * Maximum number of burst write values. 782 */ 783 #define DMUB_BURST_WRITE_VALUES__MAX 14 784 785 /* 786 * struct dmub_rb_cmd_burst_write - Burst write 787 * 788 * support use case such as writing out LUTs. 789 * 790 * 60 payload bytes can hold up to 14 values to write to given address 791 * 792 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 793 */ 794 struct dmub_rb_cmd_burst_write { 795 struct dmub_cmd_header header; /**< command header */ 796 uint32_t addr; /**< register start address */ 797 /** 798 * Burst write register values. 799 */ 800 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 801 }; 802 803 /** 804 * struct dmub_rb_cmd_common - Common command header 805 */ 806 struct dmub_rb_cmd_common { 807 struct dmub_cmd_header header; /**< command header */ 808 /** 809 * Padding to RB_CMD_SIZE 810 */ 811 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 812 }; 813 814 /** 815 * struct dmub_cmd_reg_wait_data - Register wait data 816 */ 817 struct dmub_cmd_reg_wait_data { 818 uint32_t addr; /**< Register address */ 819 uint32_t mask; /**< Mask for register bits */ 820 uint32_t condition_field_value; /**< Value to wait for */ 821 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 822 }; 823 824 /** 825 * struct dmub_rb_cmd_reg_wait - Register wait command 826 */ 827 struct dmub_rb_cmd_reg_wait { 828 struct dmub_cmd_header header; /**< Command header */ 829 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 830 }; 831 832 /** 833 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 834 * 835 * Reprograms surface parameters to avoid underflow. 836 */ 837 struct dmub_cmd_PLAT_54186_wa { 838 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 839 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 840 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 841 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 842 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 843 struct { 844 uint8_t hubp_inst : 4; /**< HUBP instance */ 845 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 846 uint8_t immediate :1; /**< Immediate flip */ 847 uint8_t vmid : 4; /**< VMID */ 848 uint8_t grph_stereo : 1; /**< 1 if stereo */ 849 uint32_t reserved : 21; /**< Reserved */ 850 } flip_params; /**< Pageflip parameters */ 851 uint32_t reserved[9]; /**< Reserved bits */ 852 }; 853 854 /** 855 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 856 */ 857 struct dmub_rb_cmd_PLAT_54186_wa { 858 struct dmub_cmd_header header; /**< Command header */ 859 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 860 }; 861 862 /** 863 * struct dmub_rb_cmd_mall - MALL command data. 864 */ 865 struct dmub_rb_cmd_mall { 866 struct dmub_cmd_header header; /**< Common command header */ 867 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 868 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 869 uint32_t tmr_delay; /**< Timer delay */ 870 uint32_t tmr_scale; /**< Timer scale */ 871 uint16_t cursor_width; /**< Cursor width in pixels */ 872 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 873 uint16_t cursor_height; /**< Cursor height in pixels */ 874 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 875 uint8_t debug_bits; /**< Debug bits */ 876 877 uint8_t reserved1; /**< Reserved bits */ 878 uint8_t reserved2; /**< Reserved bits */ 879 }; 880 881 /** 882 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 883 */ 884 enum dmub_cmd_idle_opt_type { 885 /** 886 * DCN hardware restore. 887 */ 888 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 889 890 /** 891 * DCN hardware save. 892 */ 893 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 894 }; 895 896 /** 897 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 898 */ 899 struct dmub_rb_cmd_idle_opt_dcn_restore { 900 struct dmub_cmd_header header; /**< header */ 901 }; 902 903 /** 904 * struct dmub_clocks - Clock update notification. 905 */ 906 struct dmub_clocks { 907 uint32_t dispclk_khz; /**< dispclk kHz */ 908 uint32_t dppclk_khz; /**< dppclk kHz */ 909 uint32_t dcfclk_khz; /**< dcfclk kHz */ 910 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 911 }; 912 913 /** 914 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 915 */ 916 enum dmub_cmd_clk_mgr_type { 917 /** 918 * Notify DMCUB of clock update. 919 */ 920 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 921 }; 922 923 /** 924 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 925 */ 926 struct dmub_rb_cmd_clk_mgr_notify_clocks { 927 struct dmub_cmd_header header; /**< header */ 928 struct dmub_clocks clocks; /**< clock data */ 929 }; 930 931 /** 932 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 933 */ 934 struct dmub_cmd_digx_encoder_control_data { 935 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 936 }; 937 938 /** 939 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 940 */ 941 struct dmub_rb_cmd_digx_encoder_control { 942 struct dmub_cmd_header header; /**< header */ 943 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 944 }; 945 946 /** 947 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 948 */ 949 struct dmub_cmd_set_pixel_clock_data { 950 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 951 }; 952 953 /** 954 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 955 */ 956 struct dmub_rb_cmd_set_pixel_clock { 957 struct dmub_cmd_header header; /**< header */ 958 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 959 }; 960 961 /** 962 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 963 */ 964 struct dmub_cmd_enable_disp_power_gating_data { 965 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 966 }; 967 968 /** 969 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 970 */ 971 struct dmub_rb_cmd_enable_disp_power_gating { 972 struct dmub_cmd_header header; /**< header */ 973 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 974 }; 975 976 /** 977 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 978 */ 979 struct dmub_dig_transmitter_control_data_v1_7 { 980 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 981 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 982 union { 983 uint8_t digmode; /**< enum atom_encode_mode_def */ 984 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 985 } mode_laneset; 986 uint8_t lanenum; /**< Number of lanes */ 987 union { 988 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 989 } symclk_units; 990 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 991 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 992 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 993 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 994 uint8_t reserved1; /**< For future use */ 995 uint8_t reserved2[3]; /**< For future use */ 996 uint32_t reserved3[11]; /**< For future use */ 997 }; 998 999 /** 1000 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1001 */ 1002 union dmub_cmd_dig1_transmitter_control_data { 1003 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1004 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1005 }; 1006 1007 /** 1008 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1009 */ 1010 struct dmub_rb_cmd_dig1_transmitter_control { 1011 struct dmub_cmd_header header; /**< header */ 1012 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1013 }; 1014 1015 /** 1016 * DPIA tunnel command parameters. 1017 */ 1018 struct dmub_cmd_dig_dpia_control_data { 1019 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1020 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1021 union { 1022 uint8_t digmode; /** enum atom_encode_mode_def */ 1023 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1024 } mode_laneset; 1025 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1026 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1027 uint8_t hpdsel; /** =0: HPD is not assigned */ 1028 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1029 uint8_t dpia_id; /** Index of DPIA */ 1030 uint8_t fec_rdy : 1; 1031 uint8_t reserved : 7; 1032 uint32_t reserved1; 1033 }; 1034 1035 /** 1036 * DMUB command for DPIA tunnel control. 1037 */ 1038 struct dmub_rb_cmd_dig1_dpia_control { 1039 struct dmub_cmd_header header; 1040 struct dmub_cmd_dig_dpia_control_data dpia_control; 1041 }; 1042 1043 /** 1044 * SET_CONFIG Command Payload 1045 */ 1046 struct set_config_cmd_payload { 1047 uint8_t msg_type; /* set config message type */ 1048 uint8_t msg_data; /* set config message data */ 1049 }; 1050 1051 /** 1052 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1053 */ 1054 struct dmub_cmd_set_config_control_data { 1055 struct set_config_cmd_payload cmd_pkt; 1056 uint8_t instance; /* DPIA instance */ 1057 uint8_t immed_status; /* Immediate status returned in case of error */ 1058 }; 1059 1060 /** 1061 * DMUB command structure for SET_CONFIG command. 1062 */ 1063 struct dmub_rb_cmd_set_config_access { 1064 struct dmub_cmd_header header; /* header */ 1065 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1066 }; 1067 1068 /** 1069 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1070 */ 1071 struct dmub_cmd_mst_alloc_slots_control_data { 1072 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1073 uint8_t instance; /* DPIA instance */ 1074 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1075 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1076 }; 1077 1078 /** 1079 * DMUB command structure for SET_ command. 1080 */ 1081 struct dmub_rb_cmd_set_mst_alloc_slots { 1082 struct dmub_cmd_header header; /* header */ 1083 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1084 }; 1085 1086 /** 1087 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1088 */ 1089 struct dmub_rb_cmd_dpphy_init { 1090 struct dmub_cmd_header header; /**< header */ 1091 uint8_t reserved[60]; /**< reserved bits */ 1092 }; 1093 1094 /** 1095 * enum dp_aux_request_action - DP AUX request command listing. 1096 * 1097 * 4 AUX request command bits are shifted to high nibble. 1098 */ 1099 enum dp_aux_request_action { 1100 /** I2C-over-AUX write request */ 1101 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1102 /** I2C-over-AUX read request */ 1103 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1104 /** I2C-over-AUX write status request */ 1105 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1106 /** I2C-over-AUX write request with MOT=1 */ 1107 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1108 /** I2C-over-AUX read request with MOT=1 */ 1109 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1110 /** I2C-over-AUX write status request with MOT=1 */ 1111 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1112 /** Native AUX write request */ 1113 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1114 /** Native AUX read request */ 1115 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1116 }; 1117 1118 /** 1119 * enum aux_return_code_type - DP AUX process return code listing. 1120 */ 1121 enum aux_return_code_type { 1122 /** AUX process succeeded */ 1123 AUX_RET_SUCCESS = 0, 1124 /** AUX process failed with unknown reason */ 1125 AUX_RET_ERROR_UNKNOWN, 1126 /** AUX process completed with invalid reply */ 1127 AUX_RET_ERROR_INVALID_REPLY, 1128 /** AUX process timed out */ 1129 AUX_RET_ERROR_TIMEOUT, 1130 /** HPD was low during AUX process */ 1131 AUX_RET_ERROR_HPD_DISCON, 1132 /** Failed to acquire AUX engine */ 1133 AUX_RET_ERROR_ENGINE_ACQUIRE, 1134 /** AUX request not supported */ 1135 AUX_RET_ERROR_INVALID_OPERATION, 1136 /** AUX process not available */ 1137 AUX_RET_ERROR_PROTOCOL_ERROR, 1138 }; 1139 1140 /** 1141 * enum aux_channel_type - DP AUX channel type listing. 1142 */ 1143 enum aux_channel_type { 1144 /** AUX thru Legacy DP AUX */ 1145 AUX_CHANNEL_LEGACY_DDC, 1146 /** AUX thru DPIA DP tunneling */ 1147 AUX_CHANNEL_DPIA 1148 }; 1149 1150 /** 1151 * struct aux_transaction_parameters - DP AUX request transaction data 1152 */ 1153 struct aux_transaction_parameters { 1154 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1155 uint8_t action; /**< enum dp_aux_request_action */ 1156 uint8_t length; /**< DP AUX request data length */ 1157 uint8_t reserved; /**< For future use */ 1158 uint32_t address; /**< DP AUX address */ 1159 uint8_t data[16]; /**< DP AUX write data */ 1160 }; 1161 1162 /** 1163 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1164 */ 1165 struct dmub_cmd_dp_aux_control_data { 1166 uint8_t instance; /**< AUX instance or DPIA instance */ 1167 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1168 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1169 uint8_t reserved0; /**< For future use */ 1170 uint16_t timeout; /**< timeout time in us */ 1171 uint16_t reserved1; /**< For future use */ 1172 enum aux_channel_type type; /**< enum aux_channel_type */ 1173 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1174 }; 1175 1176 /** 1177 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1178 */ 1179 struct dmub_rb_cmd_dp_aux_access { 1180 /** 1181 * Command header. 1182 */ 1183 struct dmub_cmd_header header; 1184 /** 1185 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1186 */ 1187 struct dmub_cmd_dp_aux_control_data aux_control; 1188 }; 1189 1190 /** 1191 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1192 */ 1193 struct dmub_rb_cmd_outbox1_enable { 1194 /** 1195 * Command header. 1196 */ 1197 struct dmub_cmd_header header; 1198 /** 1199 * enable: 0x0 -> disable outbox1 notification (default value) 1200 * 0x1 -> enable outbox1 notification 1201 */ 1202 uint32_t enable; 1203 }; 1204 1205 /* DP AUX Reply command - OutBox Cmd */ 1206 /** 1207 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1208 */ 1209 struct aux_reply_data { 1210 /** 1211 * Aux cmd 1212 */ 1213 uint8_t command; 1214 /** 1215 * Aux reply data length (max: 16 bytes) 1216 */ 1217 uint8_t length; 1218 /** 1219 * Alignment only 1220 */ 1221 uint8_t pad[2]; 1222 /** 1223 * Aux reply data 1224 */ 1225 uint8_t data[16]; 1226 }; 1227 1228 /** 1229 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1230 */ 1231 struct aux_reply_control_data { 1232 /** 1233 * Reserved for future use 1234 */ 1235 uint32_t handle; 1236 /** 1237 * Aux Instance 1238 */ 1239 uint8_t instance; 1240 /** 1241 * Aux transaction result: definition in enum aux_return_code_type 1242 */ 1243 uint8_t result; 1244 /** 1245 * Alignment only 1246 */ 1247 uint16_t pad; 1248 }; 1249 1250 /** 1251 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1252 */ 1253 struct dmub_rb_cmd_dp_aux_reply { 1254 /** 1255 * Command header. 1256 */ 1257 struct dmub_cmd_header header; 1258 /** 1259 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1260 */ 1261 struct aux_reply_control_data control; 1262 /** 1263 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1264 */ 1265 struct aux_reply_data reply_data; 1266 }; 1267 1268 /* DP HPD Notify command - OutBox Cmd */ 1269 /** 1270 * DP HPD Type 1271 */ 1272 enum dp_hpd_type { 1273 /** 1274 * Normal DP HPD 1275 */ 1276 DP_HPD = 0, 1277 /** 1278 * DP HPD short pulse 1279 */ 1280 DP_IRQ 1281 }; 1282 1283 /** 1284 * DP HPD Status 1285 */ 1286 enum dp_hpd_status { 1287 /** 1288 * DP_HPD status low 1289 */ 1290 DP_HPD_UNPLUG = 0, 1291 /** 1292 * DP_HPD status high 1293 */ 1294 DP_HPD_PLUG 1295 }; 1296 1297 /** 1298 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1299 */ 1300 struct dp_hpd_data { 1301 /** 1302 * DP HPD instance 1303 */ 1304 uint8_t instance; 1305 /** 1306 * HPD type 1307 */ 1308 uint8_t hpd_type; 1309 /** 1310 * HPD status: only for type: DP_HPD to indicate status 1311 */ 1312 uint8_t hpd_status; 1313 /** 1314 * Alignment only 1315 */ 1316 uint8_t pad; 1317 }; 1318 1319 /** 1320 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1321 */ 1322 struct dmub_rb_cmd_dp_hpd_notify { 1323 /** 1324 * Command header. 1325 */ 1326 struct dmub_cmd_header header; 1327 /** 1328 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1329 */ 1330 struct dp_hpd_data hpd_data; 1331 }; 1332 1333 /** 1334 * Definition of a SET_CONFIG reply from DPOA. 1335 */ 1336 enum set_config_status { 1337 SET_CONFIG_PENDING = 0, 1338 SET_CONFIG_ACK_RECEIVED, 1339 SET_CONFIG_RX_TIMEOUT, 1340 SET_CONFIG_UNKNOWN_ERROR, 1341 }; 1342 1343 /** 1344 * Definition of a set_config reply 1345 */ 1346 struct set_config_reply_control_data { 1347 uint8_t instance; /* DPIA Instance */ 1348 uint8_t status; /* Set Config reply */ 1349 uint16_t pad; /* Alignment */ 1350 }; 1351 1352 /** 1353 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1354 */ 1355 struct dmub_rb_cmd_dp_set_config_reply { 1356 struct dmub_cmd_header header; 1357 struct set_config_reply_control_data set_config_reply_control; 1358 }; 1359 1360 /** 1361 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1362 */ 1363 struct dmub_cmd_hpd_state_query_data { 1364 uint8_t instance; /**< HPD instance or DPIA instance */ 1365 uint8_t result; /**< For returning HPD state */ 1366 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1367 enum aux_return_code_type status; /**< for returning the status of command */ 1368 }; 1369 1370 /** 1371 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1372 */ 1373 struct dmub_rb_cmd_query_hpd_state { 1374 /** 1375 * Command header. 1376 */ 1377 struct dmub_cmd_header header; 1378 /** 1379 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1380 */ 1381 struct dmub_cmd_hpd_state_query_data data; 1382 }; 1383 1384 /* 1385 * Command IDs should be treated as stable ABI. 1386 * Do not reuse or modify IDs. 1387 */ 1388 1389 /** 1390 * PSR command sub-types. 1391 */ 1392 enum dmub_cmd_psr_type { 1393 /** 1394 * Set PSR version support. 1395 */ 1396 DMUB_CMD__PSR_SET_VERSION = 0, 1397 /** 1398 * Copy driver-calculated parameters to PSR state. 1399 */ 1400 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1401 /** 1402 * Enable PSR. 1403 */ 1404 DMUB_CMD__PSR_ENABLE = 2, 1405 1406 /** 1407 * Disable PSR. 1408 */ 1409 DMUB_CMD__PSR_DISABLE = 3, 1410 1411 /** 1412 * Set PSR level. 1413 * PSR level is a 16-bit value dicated by driver that 1414 * will enable/disable different functionality. 1415 */ 1416 DMUB_CMD__PSR_SET_LEVEL = 4, 1417 1418 /** 1419 * Forces PSR enabled until an explicit PSR disable call. 1420 */ 1421 DMUB_CMD__PSR_FORCE_STATIC = 5, 1422 /** 1423 * Set PSR power option 1424 */ 1425 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1426 }; 1427 1428 /** 1429 * PSR versions. 1430 */ 1431 enum psr_version { 1432 /** 1433 * PSR version 1. 1434 */ 1435 PSR_VERSION_1 = 0, 1436 /** 1437 * PSR not supported. 1438 */ 1439 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1440 }; 1441 1442 /** 1443 * enum dmub_cmd_mall_type - MALL commands 1444 */ 1445 enum dmub_cmd_mall_type { 1446 /** 1447 * Allows display refresh from MALL. 1448 */ 1449 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1450 /** 1451 * Disallows display refresh from MALL. 1452 */ 1453 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1454 /** 1455 * Cursor copy for MALL. 1456 */ 1457 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1458 /** 1459 * Controls DF requests. 1460 */ 1461 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1462 }; 1463 1464 /** 1465 * PHY Link rate for DP. 1466 */ 1467 enum phy_link_rate { 1468 /** 1469 * not supported. 1470 */ 1471 PHY_RATE_UNKNOWN = 0, 1472 /** 1473 * Rate_1 (RBR) - 1.62 Gbps/Lane 1474 */ 1475 PHY_RATE_162 = 1, 1476 /** 1477 * Rate_2 - 2.16 Gbps/Lane 1478 */ 1479 PHY_RATE_216 = 2, 1480 /** 1481 * Rate_3 - 2.43 Gbps/Lane 1482 */ 1483 PHY_RATE_243 = 3, 1484 /** 1485 * Rate_4 (HBR) - 2.70 Gbps/Lane 1486 */ 1487 PHY_RATE_270 = 4, 1488 /** 1489 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1490 */ 1491 PHY_RATE_324 = 5, 1492 /** 1493 * Rate_6 - 4.32 Gbps/Lane 1494 */ 1495 PHY_RATE_432 = 6, 1496 /** 1497 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1498 */ 1499 PHY_RATE_540 = 7, 1500 /** 1501 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1502 */ 1503 PHY_RATE_810 = 8, 1504 /** 1505 * UHBR10 - 10.0 Gbps/Lane 1506 */ 1507 PHY_RATE_1000 = 9, 1508 /** 1509 * UHBR13.5 - 13.5 Gbps/Lane 1510 */ 1511 PHY_RATE_1350 = 10, 1512 /** 1513 * UHBR10 - 20.0 Gbps/Lane 1514 */ 1515 PHY_RATE_2000 = 11, 1516 }; 1517 1518 /** 1519 * enum dmub_phy_fsm_state - PHY FSM states. 1520 * PHY FSM state to transit to during PSR enable/disable. 1521 */ 1522 enum dmub_phy_fsm_state { 1523 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1524 DMUB_PHY_FSM_RESET, 1525 DMUB_PHY_FSM_RESET_RELEASED, 1526 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1527 DMUB_PHY_FSM_INITIALIZED, 1528 DMUB_PHY_FSM_CALIBRATED, 1529 DMUB_PHY_FSM_CALIBRATED_LP, 1530 DMUB_PHY_FSM_CALIBRATED_PG, 1531 DMUB_PHY_FSM_POWER_DOWN, 1532 DMUB_PHY_FSM_PLL_EN, 1533 DMUB_PHY_FSM_TX_EN, 1534 DMUB_PHY_FSM_FAST_LP, 1535 }; 1536 1537 /** 1538 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1539 */ 1540 struct dmub_cmd_psr_copy_settings_data { 1541 /** 1542 * Flags that can be set by driver to change some PSR behaviour. 1543 */ 1544 union dmub_psr_debug_flags debug; 1545 /** 1546 * 16-bit value dicated by driver that will enable/disable different functionality. 1547 */ 1548 uint16_t psr_level; 1549 /** 1550 * DPP HW instance. 1551 */ 1552 uint8_t dpp_inst; 1553 /** 1554 * MPCC HW instance. 1555 * Not used in dmub fw, 1556 * dmub fw will get active opp by reading odm registers. 1557 */ 1558 uint8_t mpcc_inst; 1559 /** 1560 * OPP HW instance. 1561 * Not used in dmub fw, 1562 * dmub fw will get active opp by reading odm registers. 1563 */ 1564 uint8_t opp_inst; 1565 /** 1566 * OTG HW instance. 1567 */ 1568 uint8_t otg_inst; 1569 /** 1570 * DIG FE HW instance. 1571 */ 1572 uint8_t digfe_inst; 1573 /** 1574 * DIG BE HW instance. 1575 */ 1576 uint8_t digbe_inst; 1577 /** 1578 * DP PHY HW instance. 1579 */ 1580 uint8_t dpphy_inst; 1581 /** 1582 * AUX HW instance. 1583 */ 1584 uint8_t aux_inst; 1585 /** 1586 * Determines if SMU optimzations are enabled/disabled. 1587 */ 1588 uint8_t smu_optimizations_en; 1589 /** 1590 * Unused. 1591 * TODO: Remove. 1592 */ 1593 uint8_t frame_delay; 1594 /** 1595 * If RFB setup time is greater than the total VBLANK time, 1596 * it is not possible for the sink to capture the video frame 1597 * in the same frame the SDP is sent. In this case, 1598 * the frame capture indication bit should be set and an extra 1599 * static frame should be transmitted to the sink. 1600 */ 1601 uint8_t frame_cap_ind; 1602 /** 1603 * Explicit padding to 4 byte boundary. 1604 */ 1605 uint8_t pad[2]; 1606 /** 1607 * Multi-display optimizations are implemented on certain ASICs. 1608 */ 1609 uint8_t multi_disp_optimizations_en; 1610 /** 1611 * The last possible line SDP may be transmitted without violating 1612 * the RFB setup time or entering the active video frame. 1613 */ 1614 uint16_t init_sdp_deadline; 1615 /** 1616 * Explicit padding to 4 byte boundary. 1617 */ 1618 uint16_t pad2; 1619 /** 1620 * Length of each horizontal line in us. 1621 */ 1622 uint32_t line_time_in_us; 1623 /** 1624 * FEC enable status in driver 1625 */ 1626 uint8_t fec_enable_status; 1627 /** 1628 * FEC re-enable delay when PSR exit. 1629 * unit is 100us, range form 0~255(0xFF). 1630 */ 1631 uint8_t fec_enable_delay_in100us; 1632 /** 1633 * PSR control version. 1634 */ 1635 uint8_t cmd_version; 1636 /** 1637 * Panel Instance. 1638 * Panel isntance to identify which psr_state to use 1639 * Currently the support is only for 0 or 1 1640 */ 1641 uint8_t panel_inst; 1642 /* 1643 * DSC enable status in driver 1644 */ 1645 uint8_t dsc_enable_status; 1646 /* 1647 * Use FSM state for PSR power up/down 1648 */ 1649 uint8_t use_phy_fsm; 1650 /** 1651 * Explicit padding to 2 byte boundary. 1652 */ 1653 uint8_t pad3[2]; 1654 }; 1655 1656 /** 1657 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1658 */ 1659 struct dmub_rb_cmd_psr_copy_settings { 1660 /** 1661 * Command header. 1662 */ 1663 struct dmub_cmd_header header; 1664 /** 1665 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1666 */ 1667 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1668 }; 1669 1670 /** 1671 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1672 */ 1673 struct dmub_cmd_psr_set_level_data { 1674 /** 1675 * 16-bit value dicated by driver that will enable/disable different functionality. 1676 */ 1677 uint16_t psr_level; 1678 /** 1679 * PSR control version. 1680 */ 1681 uint8_t cmd_version; 1682 /** 1683 * Panel Instance. 1684 * Panel isntance to identify which psr_state to use 1685 * Currently the support is only for 0 or 1 1686 */ 1687 uint8_t panel_inst; 1688 }; 1689 1690 /** 1691 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1692 */ 1693 struct dmub_rb_cmd_psr_set_level { 1694 /** 1695 * Command header. 1696 */ 1697 struct dmub_cmd_header header; 1698 /** 1699 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1700 */ 1701 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1702 }; 1703 1704 struct dmub_rb_cmd_psr_enable_data { 1705 /** 1706 * PSR control version. 1707 */ 1708 uint8_t cmd_version; 1709 /** 1710 * Panel Instance. 1711 * Panel isntance to identify which psr_state to use 1712 * Currently the support is only for 0 or 1 1713 */ 1714 uint8_t panel_inst; 1715 /** 1716 * Phy state to enter. 1717 * Values to use are defined in dmub_phy_fsm_state 1718 */ 1719 uint8_t phy_fsm_state; 1720 /** 1721 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1722 * Set this using enum phy_link_rate. 1723 * This does not support HDMI/DP2 for now. 1724 */ 1725 uint8_t phy_rate; 1726 }; 1727 1728 /** 1729 * Definition of a DMUB_CMD__PSR_ENABLE command. 1730 * PSR enable/disable is controlled using the sub_type. 1731 */ 1732 struct dmub_rb_cmd_psr_enable { 1733 /** 1734 * Command header. 1735 */ 1736 struct dmub_cmd_header header; 1737 1738 struct dmub_rb_cmd_psr_enable_data data; 1739 }; 1740 1741 /** 1742 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1743 */ 1744 struct dmub_cmd_psr_set_version_data { 1745 /** 1746 * PSR version that FW should implement. 1747 */ 1748 enum psr_version version; 1749 /** 1750 * PSR control version. 1751 */ 1752 uint8_t cmd_version; 1753 /** 1754 * Panel Instance. 1755 * Panel isntance to identify which psr_state to use 1756 * Currently the support is only for 0 or 1 1757 */ 1758 uint8_t panel_inst; 1759 /** 1760 * Explicit padding to 4 byte boundary. 1761 */ 1762 uint8_t pad[2]; 1763 }; 1764 1765 /** 1766 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1767 */ 1768 struct dmub_rb_cmd_psr_set_version { 1769 /** 1770 * Command header. 1771 */ 1772 struct dmub_cmd_header header; 1773 /** 1774 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1775 */ 1776 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1777 }; 1778 1779 struct dmub_cmd_psr_force_static_data { 1780 /** 1781 * PSR control version. 1782 */ 1783 uint8_t cmd_version; 1784 /** 1785 * Panel Instance. 1786 * Panel isntance to identify which psr_state to use 1787 * Currently the support is only for 0 or 1 1788 */ 1789 uint8_t panel_inst; 1790 /** 1791 * Explicit padding to 4 byte boundary. 1792 */ 1793 uint8_t pad[2]; 1794 }; 1795 1796 /** 1797 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1798 */ 1799 struct dmub_rb_cmd_psr_force_static { 1800 /** 1801 * Command header. 1802 */ 1803 struct dmub_cmd_header header; 1804 /** 1805 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1806 */ 1807 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1808 }; 1809 1810 /** 1811 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 1812 */ 1813 struct dmub_cmd_psr_set_power_opt_data { 1814 /** 1815 * PSR control version. 1816 */ 1817 uint8_t cmd_version; 1818 /** 1819 * Panel Instance. 1820 * Panel isntance to identify which psr_state to use 1821 * Currently the support is only for 0 or 1 1822 */ 1823 uint8_t panel_inst; 1824 /** 1825 * Explicit padding to 4 byte boundary. 1826 */ 1827 uint8_t pad[2]; 1828 /** 1829 * PSR power option 1830 */ 1831 uint32_t power_opt; 1832 }; 1833 1834 /** 1835 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1836 */ 1837 struct dmub_rb_cmd_psr_set_power_opt { 1838 /** 1839 * Command header. 1840 */ 1841 struct dmub_cmd_header header; 1842 /** 1843 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1844 */ 1845 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 1846 }; 1847 1848 /** 1849 * Set of HW components that can be locked. 1850 * 1851 * Note: If updating with more HW components, fields 1852 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1853 */ 1854 union dmub_hw_lock_flags { 1855 /** 1856 * Set of HW components that can be locked. 1857 */ 1858 struct { 1859 /** 1860 * Lock/unlock OTG master update lock. 1861 */ 1862 uint8_t lock_pipe : 1; 1863 /** 1864 * Lock/unlock cursor. 1865 */ 1866 uint8_t lock_cursor : 1; 1867 /** 1868 * Lock/unlock global update lock. 1869 */ 1870 uint8_t lock_dig : 1; 1871 /** 1872 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1873 */ 1874 uint8_t triple_buffer_lock : 1; 1875 } bits; 1876 1877 /** 1878 * Union for HW Lock flags. 1879 */ 1880 uint8_t u8All; 1881 }; 1882 1883 /** 1884 * Instances of HW to be locked. 1885 * 1886 * Note: If updating with more HW components, fields 1887 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1888 */ 1889 struct dmub_hw_lock_inst_flags { 1890 /** 1891 * OTG HW instance for OTG master update lock. 1892 */ 1893 uint8_t otg_inst; 1894 /** 1895 * OPP instance for cursor lock. 1896 */ 1897 uint8_t opp_inst; 1898 /** 1899 * OTG HW instance for global update lock. 1900 * TODO: Remove, and re-use otg_inst. 1901 */ 1902 uint8_t dig_inst; 1903 /** 1904 * Explicit pad to 4 byte boundary. 1905 */ 1906 uint8_t pad; 1907 }; 1908 1909 /** 1910 * Clients that can acquire the HW Lock Manager. 1911 * 1912 * Note: If updating with more clients, fields in 1913 * dmub_inbox0_cmd_lock_hw must be updated to match. 1914 */ 1915 enum hw_lock_client { 1916 /** 1917 * Driver is the client of HW Lock Manager. 1918 */ 1919 HW_LOCK_CLIENT_DRIVER = 0, 1920 /** 1921 * Invalid client. 1922 */ 1923 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1924 }; 1925 1926 /** 1927 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1928 */ 1929 struct dmub_cmd_lock_hw_data { 1930 /** 1931 * Specifies the client accessing HW Lock Manager. 1932 */ 1933 enum hw_lock_client client; 1934 /** 1935 * HW instances to be locked. 1936 */ 1937 struct dmub_hw_lock_inst_flags inst_flags; 1938 /** 1939 * Which components to be locked. 1940 */ 1941 union dmub_hw_lock_flags hw_locks; 1942 /** 1943 * Specifies lock/unlock. 1944 */ 1945 uint8_t lock; 1946 /** 1947 * HW can be unlocked separately from releasing the HW Lock Mgr. 1948 * This flag is set if the client wishes to release the object. 1949 */ 1950 uint8_t should_release; 1951 /** 1952 * Explicit padding to 4 byte boundary. 1953 */ 1954 uint8_t pad; 1955 }; 1956 1957 /** 1958 * Definition of a DMUB_CMD__HW_LOCK command. 1959 * Command is used by driver and FW. 1960 */ 1961 struct dmub_rb_cmd_lock_hw { 1962 /** 1963 * Command header. 1964 */ 1965 struct dmub_cmd_header header; 1966 /** 1967 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1968 */ 1969 struct dmub_cmd_lock_hw_data lock_hw_data; 1970 }; 1971 1972 /** 1973 * ABM command sub-types. 1974 */ 1975 enum dmub_cmd_abm_type { 1976 /** 1977 * Initialize parameters for ABM algorithm. 1978 * Data is passed through an indirect buffer. 1979 */ 1980 DMUB_CMD__ABM_INIT_CONFIG = 0, 1981 /** 1982 * Set OTG and panel HW instance. 1983 */ 1984 DMUB_CMD__ABM_SET_PIPE = 1, 1985 /** 1986 * Set user requested backklight level. 1987 */ 1988 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1989 /** 1990 * Set ABM operating/aggression level. 1991 */ 1992 DMUB_CMD__ABM_SET_LEVEL = 3, 1993 /** 1994 * Set ambient light level. 1995 */ 1996 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1997 /** 1998 * Enable/disable fractional duty cycle for backlight PWM. 1999 */ 2000 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2001 2002 /** 2003 * unregister vertical interrupt after steady state is reached 2004 */ 2005 DMUB_CMD__ABM_PAUSE = 6, 2006 }; 2007 2008 /** 2009 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2010 * Requirements: 2011 * - Padded explicitly to 32-bit boundary. 2012 * - Must ensure this structure matches the one on driver-side, 2013 * otherwise it won't be aligned. 2014 */ 2015 struct abm_config_table { 2016 /** 2017 * Gamma curve thresholds, used for crgb conversion. 2018 */ 2019 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2020 /** 2021 * Gamma curve offsets, used for crgb conversion. 2022 */ 2023 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2024 /** 2025 * Gamma curve slopes, used for crgb conversion. 2026 */ 2027 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2028 /** 2029 * Custom backlight curve thresholds. 2030 */ 2031 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2032 /** 2033 * Custom backlight curve offsets. 2034 */ 2035 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2036 /** 2037 * Ambient light thresholds. 2038 */ 2039 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2040 /** 2041 * Minimum programmable backlight. 2042 */ 2043 uint16_t min_abm_backlight; // 122B 2044 /** 2045 * Minimum reduction values. 2046 */ 2047 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2048 /** 2049 * Maximum reduction values. 2050 */ 2051 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2052 /** 2053 * Bright positive gain. 2054 */ 2055 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2056 /** 2057 * Dark negative gain. 2058 */ 2059 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2060 /** 2061 * Hybrid factor. 2062 */ 2063 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2064 /** 2065 * Contrast factor. 2066 */ 2067 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2068 /** 2069 * Deviation gain. 2070 */ 2071 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2072 /** 2073 * Minimum knee. 2074 */ 2075 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2076 /** 2077 * Maximum knee. 2078 */ 2079 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2080 /** 2081 * Unused. 2082 */ 2083 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2084 /** 2085 * Explicit padding to 4 byte boundary. 2086 */ 2087 uint8_t pad3[3]; // 229B 2088 /** 2089 * Backlight ramp reduction. 2090 */ 2091 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2092 /** 2093 * Backlight ramp start. 2094 */ 2095 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2096 }; 2097 2098 /** 2099 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2100 */ 2101 struct dmub_cmd_abm_set_pipe_data { 2102 /** 2103 * OTG HW instance. 2104 */ 2105 uint8_t otg_inst; 2106 2107 /** 2108 * Panel Control HW instance. 2109 */ 2110 uint8_t panel_inst; 2111 2112 /** 2113 * Controls how ABM will interpret a set pipe or set level command. 2114 */ 2115 uint8_t set_pipe_option; 2116 2117 /** 2118 * Unused. 2119 * TODO: Remove. 2120 */ 2121 uint8_t ramping_boundary; 2122 }; 2123 2124 /** 2125 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2126 */ 2127 struct dmub_rb_cmd_abm_set_pipe { 2128 /** 2129 * Command header. 2130 */ 2131 struct dmub_cmd_header header; 2132 2133 /** 2134 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2135 */ 2136 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2137 }; 2138 2139 /** 2140 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2141 */ 2142 struct dmub_cmd_abm_set_backlight_data { 2143 /** 2144 * Number of frames to ramp to backlight user level. 2145 */ 2146 uint32_t frame_ramp; 2147 2148 /** 2149 * Requested backlight level from user. 2150 */ 2151 uint32_t backlight_user_level; 2152 2153 /** 2154 * ABM control version. 2155 */ 2156 uint8_t version; 2157 2158 /** 2159 * Panel Control HW instance mask. 2160 * Bit 0 is Panel Control HW instance 0. 2161 * Bit 1 is Panel Control HW instance 1. 2162 */ 2163 uint8_t panel_mask; 2164 2165 /** 2166 * Explicit padding to 4 byte boundary. 2167 */ 2168 uint8_t pad[2]; 2169 }; 2170 2171 /** 2172 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2173 */ 2174 struct dmub_rb_cmd_abm_set_backlight { 2175 /** 2176 * Command header. 2177 */ 2178 struct dmub_cmd_header header; 2179 2180 /** 2181 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2182 */ 2183 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2184 }; 2185 2186 /** 2187 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2188 */ 2189 struct dmub_cmd_abm_set_level_data { 2190 /** 2191 * Set current ABM operating/aggression level. 2192 */ 2193 uint32_t level; 2194 2195 /** 2196 * ABM control version. 2197 */ 2198 uint8_t version; 2199 2200 /** 2201 * Panel Control HW instance mask. 2202 * Bit 0 is Panel Control HW instance 0. 2203 * Bit 1 is Panel Control HW instance 1. 2204 */ 2205 uint8_t panel_mask; 2206 2207 /** 2208 * Explicit padding to 4 byte boundary. 2209 */ 2210 uint8_t pad[2]; 2211 }; 2212 2213 /** 2214 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2215 */ 2216 struct dmub_rb_cmd_abm_set_level { 2217 /** 2218 * Command header. 2219 */ 2220 struct dmub_cmd_header header; 2221 2222 /** 2223 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2224 */ 2225 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2226 }; 2227 2228 /** 2229 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2230 */ 2231 struct dmub_cmd_abm_set_ambient_level_data { 2232 /** 2233 * Ambient light sensor reading from OS. 2234 */ 2235 uint32_t ambient_lux; 2236 2237 /** 2238 * ABM control version. 2239 */ 2240 uint8_t version; 2241 2242 /** 2243 * Panel Control HW instance mask. 2244 * Bit 0 is Panel Control HW instance 0. 2245 * Bit 1 is Panel Control HW instance 1. 2246 */ 2247 uint8_t panel_mask; 2248 2249 /** 2250 * Explicit padding to 4 byte boundary. 2251 */ 2252 uint8_t pad[2]; 2253 }; 2254 2255 /** 2256 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2257 */ 2258 struct dmub_rb_cmd_abm_set_ambient_level { 2259 /** 2260 * Command header. 2261 */ 2262 struct dmub_cmd_header header; 2263 2264 /** 2265 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2266 */ 2267 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2268 }; 2269 2270 /** 2271 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2272 */ 2273 struct dmub_cmd_abm_set_pwm_frac_data { 2274 /** 2275 * Enable/disable fractional duty cycle for backlight PWM. 2276 * TODO: Convert to uint8_t. 2277 */ 2278 uint32_t fractional_pwm; 2279 2280 /** 2281 * ABM control version. 2282 */ 2283 uint8_t version; 2284 2285 /** 2286 * Panel Control HW instance mask. 2287 * Bit 0 is Panel Control HW instance 0. 2288 * Bit 1 is Panel Control HW instance 1. 2289 */ 2290 uint8_t panel_mask; 2291 2292 /** 2293 * Explicit padding to 4 byte boundary. 2294 */ 2295 uint8_t pad[2]; 2296 }; 2297 2298 /** 2299 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2300 */ 2301 struct dmub_rb_cmd_abm_set_pwm_frac { 2302 /** 2303 * Command header. 2304 */ 2305 struct dmub_cmd_header header; 2306 2307 /** 2308 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2309 */ 2310 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2311 }; 2312 2313 /** 2314 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2315 */ 2316 struct dmub_cmd_abm_init_config_data { 2317 /** 2318 * Location of indirect buffer used to pass init data to ABM. 2319 */ 2320 union dmub_addr src; 2321 2322 /** 2323 * Indirect buffer length. 2324 */ 2325 uint16_t bytes; 2326 2327 2328 /** 2329 * ABM control version. 2330 */ 2331 uint8_t version; 2332 2333 /** 2334 * Panel Control HW instance mask. 2335 * Bit 0 is Panel Control HW instance 0. 2336 * Bit 1 is Panel Control HW instance 1. 2337 */ 2338 uint8_t panel_mask; 2339 2340 /** 2341 * Explicit padding to 4 byte boundary. 2342 */ 2343 uint8_t pad[2]; 2344 }; 2345 2346 /** 2347 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2348 */ 2349 struct dmub_rb_cmd_abm_init_config { 2350 /** 2351 * Command header. 2352 */ 2353 struct dmub_cmd_header header; 2354 2355 /** 2356 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2357 */ 2358 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2359 }; 2360 2361 /** 2362 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2363 */ 2364 2365 struct dmub_cmd_abm_pause_data { 2366 2367 /** 2368 * Panel Control HW instance mask. 2369 * Bit 0 is Panel Control HW instance 0. 2370 * Bit 1 is Panel Control HW instance 1. 2371 */ 2372 uint8_t panel_mask; 2373 2374 /** 2375 * OTG hw instance 2376 */ 2377 uint8_t otg_inst; 2378 2379 /** 2380 * Enable or disable ABM pause 2381 */ 2382 uint8_t enable; 2383 2384 /** 2385 * Explicit padding to 4 byte boundary. 2386 */ 2387 uint8_t pad[1]; 2388 }; 2389 2390 /** 2391 * Definition of a DMUB_CMD__ABM_PAUSE command. 2392 */ 2393 struct dmub_rb_cmd_abm_pause { 2394 /** 2395 * Command header. 2396 */ 2397 struct dmub_cmd_header header; 2398 2399 /** 2400 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2401 */ 2402 struct dmub_cmd_abm_pause_data abm_pause_data; 2403 }; 2404 2405 /** 2406 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2407 */ 2408 struct dmub_cmd_query_feature_caps_data { 2409 /** 2410 * DMUB feature capabilities. 2411 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2412 */ 2413 struct dmub_feature_caps feature_caps; 2414 }; 2415 2416 /** 2417 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2418 */ 2419 struct dmub_rb_cmd_query_feature_caps { 2420 /** 2421 * Command header. 2422 */ 2423 struct dmub_cmd_header header; 2424 /** 2425 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2426 */ 2427 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2428 }; 2429 2430 struct dmub_optc_state { 2431 uint32_t v_total_max; 2432 uint32_t v_total_min; 2433 uint32_t v_total_mid; 2434 uint32_t v_total_mid_frame_num; 2435 uint32_t tg_inst; 2436 uint32_t enable_manual_trigger; 2437 uint32_t clear_force_vsync; 2438 }; 2439 2440 struct dmub_rb_cmd_drr_update { 2441 struct dmub_cmd_header header; 2442 struct dmub_optc_state dmub_optc_state_req; 2443 }; 2444 2445 /** 2446 * enum dmub_cmd_panel_cntl_type - Panel control command. 2447 */ 2448 enum dmub_cmd_panel_cntl_type { 2449 /** 2450 * Initializes embedded panel hardware blocks. 2451 */ 2452 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2453 /** 2454 * Queries backlight info for the embedded panel. 2455 */ 2456 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2457 }; 2458 2459 /** 2460 * struct dmub_cmd_panel_cntl_data - Panel control data. 2461 */ 2462 struct dmub_cmd_panel_cntl_data { 2463 uint32_t inst; /**< panel instance */ 2464 uint32_t current_backlight; /* in/out */ 2465 uint32_t bl_pwm_cntl; /* in/out */ 2466 uint32_t bl_pwm_period_cntl; /* in/out */ 2467 uint32_t bl_pwm_ref_div1; /* in/out */ 2468 uint8_t is_backlight_on : 1; /* in/out */ 2469 uint8_t is_powered_on : 1; /* in/out */ 2470 uint8_t padding[3]; 2471 uint32_t bl_pwm_ref_div2; /* in/out */ 2472 uint8_t reserved[4]; 2473 }; 2474 2475 /** 2476 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2477 */ 2478 struct dmub_rb_cmd_panel_cntl { 2479 struct dmub_cmd_header header; /**< header */ 2480 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2481 }; 2482 2483 /** 2484 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2485 */ 2486 struct dmub_cmd_lvtma_control_data { 2487 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2488 uint8_t reserved_0[3]; /**< For future use */ 2489 uint8_t panel_inst; /**< LVTMA control instance */ 2490 uint8_t reserved_1[3]; /**< For future use */ 2491 }; 2492 2493 /** 2494 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2495 */ 2496 struct dmub_rb_cmd_lvtma_control { 2497 /** 2498 * Command header. 2499 */ 2500 struct dmub_cmd_header header; 2501 /** 2502 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2503 */ 2504 struct dmub_cmd_lvtma_control_data data; 2505 }; 2506 2507 /** 2508 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2509 */ 2510 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 2511 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2512 uint8_t is_usb; /**< is phy is usb */ 2513 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 2514 uint8_t is_dp4; /**< is dp in 4 lane */ 2515 }; 2516 2517 /** 2518 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2519 */ 2520 struct dmub_rb_cmd_transmitter_query_dp_alt { 2521 struct dmub_cmd_header header; /**< header */ 2522 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 2523 }; 2524 2525 /** 2526 * Maximum number of bytes a chunk sent to DMUB for parsing 2527 */ 2528 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2529 2530 /** 2531 * Represent a chunk of CEA blocks sent to DMUB for parsing 2532 */ 2533 struct dmub_cmd_send_edid_cea { 2534 uint16_t offset; /**< offset into the CEA block */ 2535 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2536 uint16_t cea_total_length; /**< total length of the CEA block */ 2537 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2538 uint8_t pad[3]; /**< padding and for future expansion */ 2539 }; 2540 2541 /** 2542 * Result of VSDB parsing from CEA block 2543 */ 2544 struct dmub_cmd_edid_cea_amd_vsdb { 2545 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2546 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2547 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2548 uint16_t min_frame_rate; /**< Maximum frame rate */ 2549 uint16_t max_frame_rate; /**< Minimum frame rate */ 2550 }; 2551 2552 /** 2553 * Result of sending a CEA chunk 2554 */ 2555 struct dmub_cmd_edid_cea_ack { 2556 uint16_t offset; /**< offset of the chunk into the CEA block */ 2557 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2558 uint8_t pad; /**< padding and for future expansion */ 2559 }; 2560 2561 /** 2562 * Specify whether the result is an ACK/NACK or the parsing has finished 2563 */ 2564 enum dmub_cmd_edid_cea_reply_type { 2565 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2566 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2567 }; 2568 2569 /** 2570 * Definition of a DMUB_CMD__EDID_CEA command. 2571 */ 2572 struct dmub_rb_cmd_edid_cea { 2573 struct dmub_cmd_header header; /**< Command header */ 2574 union dmub_cmd_edid_cea_data { 2575 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2576 struct dmub_cmd_edid_cea_output { /**< output with results */ 2577 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2578 union { 2579 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2580 struct dmub_cmd_edid_cea_ack ack; 2581 }; 2582 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2583 } data; /**< Command data */ 2584 2585 }; 2586 2587 /** 2588 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 2589 */ 2590 struct dmub_cmd_cable_id_input { 2591 uint8_t phy_inst; /**< phy inst for cable id data */ 2592 }; 2593 2594 /** 2595 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 2596 */ 2597 struct dmub_cmd_cable_id_output { 2598 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 2599 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 2600 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 2601 uint8_t RESERVED :2; /**< reserved means not defined */ 2602 }; 2603 2604 /** 2605 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 2606 */ 2607 struct dmub_rb_cmd_get_usbc_cable_id { 2608 struct dmub_cmd_header header; /**< Command header */ 2609 /** 2610 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 2611 */ 2612 union dmub_cmd_cable_id_data { 2613 struct dmub_cmd_cable_id_input input; /**< Input */ 2614 struct dmub_cmd_cable_id_output output; /**< Output */ 2615 uint8_t output_raw; /**< Raw data output */ 2616 } data; 2617 }; 2618 2619 /** 2620 * union dmub_rb_cmd - DMUB inbox command. 2621 */ 2622 union dmub_rb_cmd { 2623 struct dmub_rb_cmd_lock_hw lock_hw; 2624 /** 2625 * Elements shared with all commands. 2626 */ 2627 struct dmub_rb_cmd_common cmd_common; 2628 /** 2629 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2630 */ 2631 struct dmub_rb_cmd_read_modify_write read_modify_write; 2632 /** 2633 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2634 */ 2635 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2636 /** 2637 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2638 */ 2639 struct dmub_rb_cmd_burst_write burst_write; 2640 /** 2641 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2642 */ 2643 struct dmub_rb_cmd_reg_wait reg_wait; 2644 /** 2645 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2646 */ 2647 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2648 /** 2649 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2650 */ 2651 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2652 /** 2653 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2654 */ 2655 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2656 /** 2657 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2658 */ 2659 struct dmub_rb_cmd_dpphy_init dpphy_init; 2660 /** 2661 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2662 */ 2663 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2664 /** 2665 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2666 */ 2667 struct dmub_rb_cmd_psr_set_version psr_set_version; 2668 /** 2669 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2670 */ 2671 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2672 /** 2673 * Definition of a DMUB_CMD__PSR_ENABLE command. 2674 */ 2675 struct dmub_rb_cmd_psr_enable psr_enable; 2676 /** 2677 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2678 */ 2679 struct dmub_rb_cmd_psr_set_level psr_set_level; 2680 /** 2681 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2682 */ 2683 struct dmub_rb_cmd_psr_force_static psr_force_static; 2684 /** 2685 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2686 */ 2687 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 2688 /** 2689 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2690 */ 2691 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2692 /** 2693 * Definition of a DMUB_CMD__MALL command. 2694 */ 2695 struct dmub_rb_cmd_mall mall; 2696 /** 2697 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2698 */ 2699 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2700 2701 /** 2702 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2703 */ 2704 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2705 2706 /** 2707 * Definition of DMUB_CMD__PANEL_CNTL commands. 2708 */ 2709 struct dmub_rb_cmd_panel_cntl panel_cntl; 2710 /** 2711 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2712 */ 2713 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2714 2715 /** 2716 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2717 */ 2718 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2719 2720 /** 2721 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2722 */ 2723 struct dmub_rb_cmd_abm_set_level abm_set_level; 2724 2725 /** 2726 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2727 */ 2728 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2729 2730 /** 2731 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2732 */ 2733 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2734 2735 /** 2736 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2737 */ 2738 struct dmub_rb_cmd_abm_init_config abm_init_config; 2739 2740 /** 2741 * Definition of a DMUB_CMD__ABM_PAUSE command. 2742 */ 2743 struct dmub_rb_cmd_abm_pause abm_pause; 2744 2745 /** 2746 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2747 */ 2748 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2749 2750 /** 2751 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2752 */ 2753 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2754 2755 /** 2756 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2757 */ 2758 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2759 struct dmub_rb_cmd_drr_update drr_update; 2760 /** 2761 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2762 */ 2763 struct dmub_rb_cmd_lvtma_control lvtma_control; 2764 /** 2765 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2766 */ 2767 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 2768 /** 2769 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 2770 */ 2771 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 2772 /** 2773 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 2774 */ 2775 struct dmub_rb_cmd_set_config_access set_config_access; 2776 /** 2777 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2778 */ 2779 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 2780 /** 2781 * Definition of a DMUB_CMD__EDID_CEA command. 2782 */ 2783 struct dmub_rb_cmd_edid_cea edid_cea; 2784 /** 2785 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 2786 */ 2787 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 2788 2789 /** 2790 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2791 */ 2792 struct dmub_rb_cmd_query_hpd_state query_hpd; 2793 }; 2794 2795 /** 2796 * union dmub_rb_out_cmd - Outbox command 2797 */ 2798 union dmub_rb_out_cmd { 2799 /** 2800 * Parameters common to every command. 2801 */ 2802 struct dmub_rb_cmd_common cmd_common; 2803 /** 2804 * AUX reply command. 2805 */ 2806 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2807 /** 2808 * HPD notify command. 2809 */ 2810 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2811 /** 2812 * SET_CONFIG reply command. 2813 */ 2814 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 2815 }; 2816 #pragma pack(pop) 2817 2818 2819 //============================================================================== 2820 //</DMUB_CMD>=================================================================== 2821 //============================================================================== 2822 //< DMUB_RB>==================================================================== 2823 //============================================================================== 2824 2825 #if defined(__cplusplus) 2826 extern "C" { 2827 #endif 2828 2829 /** 2830 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2831 */ 2832 struct dmub_rb_init_params { 2833 void *ctx; /**< Caller provided context pointer */ 2834 void *base_address; /**< CPU base address for ring's data */ 2835 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2836 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2837 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2838 }; 2839 2840 /** 2841 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2842 */ 2843 struct dmub_rb { 2844 void *base_address; /**< CPU address for the ring's data */ 2845 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2846 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2847 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2848 2849 void *ctx; /**< Caller provided context pointer */ 2850 void *dmub; /**< Pointer to the DMUB interface */ 2851 }; 2852 2853 /** 2854 * @brief Checks if the ringbuffer is empty. 2855 * 2856 * @param rb DMUB Ringbuffer 2857 * @return true if empty 2858 * @return false otherwise 2859 */ 2860 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2861 { 2862 return (rb->wrpt == rb->rptr); 2863 } 2864 2865 /** 2866 * @brief Checks if the ringbuffer is full 2867 * 2868 * @param rb DMUB Ringbuffer 2869 * @return true if full 2870 * @return false otherwise 2871 */ 2872 static inline bool dmub_rb_full(struct dmub_rb *rb) 2873 { 2874 uint32_t data_count; 2875 2876 if (rb->wrpt >= rb->rptr) 2877 data_count = rb->wrpt - rb->rptr; 2878 else 2879 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2880 2881 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2882 } 2883 2884 /** 2885 * @brief Pushes a command into the ringbuffer 2886 * 2887 * @param rb DMUB ringbuffer 2888 * @param cmd The command to push 2889 * @return true if the ringbuffer was not full 2890 * @return false otherwise 2891 */ 2892 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2893 const union dmub_rb_cmd *cmd) 2894 { 2895 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 2896 const uint64_t *src = (const uint64_t *)cmd; 2897 uint8_t i; 2898 2899 if (dmub_rb_full(rb)) 2900 return false; 2901 2902 // copying data 2903 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2904 *dst++ = *src++; 2905 2906 rb->wrpt += DMUB_RB_CMD_SIZE; 2907 2908 if (rb->wrpt >= rb->capacity) 2909 rb->wrpt %= rb->capacity; 2910 2911 return true; 2912 } 2913 2914 /** 2915 * @brief Pushes a command into the DMUB outbox ringbuffer 2916 * 2917 * @param rb DMUB outbox ringbuffer 2918 * @param cmd Outbox command 2919 * @return true if not full 2920 * @return false otherwise 2921 */ 2922 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2923 const union dmub_rb_out_cmd *cmd) 2924 { 2925 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2926 const uint8_t *src = (const uint8_t *)cmd; 2927 2928 if (dmub_rb_full(rb)) 2929 return false; 2930 2931 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2932 2933 rb->wrpt += DMUB_RB_CMD_SIZE; 2934 2935 if (rb->wrpt >= rb->capacity) 2936 rb->wrpt %= rb->capacity; 2937 2938 return true; 2939 } 2940 2941 /** 2942 * @brief Returns the next unprocessed command in the ringbuffer. 2943 * 2944 * @param rb DMUB ringbuffer 2945 * @param cmd The command to return 2946 * @return true if not empty 2947 * @return false otherwise 2948 */ 2949 static inline bool dmub_rb_front(struct dmub_rb *rb, 2950 union dmub_rb_cmd **cmd) 2951 { 2952 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2953 2954 if (dmub_rb_empty(rb)) 2955 return false; 2956 2957 *cmd = (union dmub_rb_cmd *)rb_cmd; 2958 2959 return true; 2960 } 2961 2962 /** 2963 * @brief Determines the next ringbuffer offset. 2964 * 2965 * @param rb DMUB inbox ringbuffer 2966 * @param num_cmds Number of commands 2967 * @param next_rptr The next offset in the ringbuffer 2968 */ 2969 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2970 uint32_t num_cmds, 2971 uint32_t *next_rptr) 2972 { 2973 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2974 2975 if (*next_rptr >= rb->capacity) 2976 *next_rptr %= rb->capacity; 2977 } 2978 2979 /** 2980 * @brief Returns a pointer to a command in the inbox. 2981 * 2982 * @param rb DMUB inbox ringbuffer 2983 * @param cmd The inbox command to return 2984 * @param rptr The ringbuffer offset 2985 * @return true if not empty 2986 * @return false otherwise 2987 */ 2988 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 2989 union dmub_rb_cmd **cmd, 2990 uint32_t rptr) 2991 { 2992 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 2993 2994 if (dmub_rb_empty(rb)) 2995 return false; 2996 2997 *cmd = (union dmub_rb_cmd *)rb_cmd; 2998 2999 return true; 3000 } 3001 3002 /** 3003 * @brief Returns the next unprocessed command in the outbox. 3004 * 3005 * @param rb DMUB outbox ringbuffer 3006 * @param cmd The outbox command to return 3007 * @return true if not empty 3008 * @return false otherwise 3009 */ 3010 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3011 union dmub_rb_out_cmd *cmd) 3012 { 3013 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3014 uint64_t *dst = (uint64_t *)cmd; 3015 uint8_t i; 3016 3017 if (dmub_rb_empty(rb)) 3018 return false; 3019 3020 // copying data 3021 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3022 *dst++ = *src++; 3023 3024 return true; 3025 } 3026 3027 /** 3028 * @brief Removes the front entry in the ringbuffer. 3029 * 3030 * @param rb DMUB ringbuffer 3031 * @return true if the command was removed 3032 * @return false if there were no commands 3033 */ 3034 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3035 { 3036 if (dmub_rb_empty(rb)) 3037 return false; 3038 3039 rb->rptr += DMUB_RB_CMD_SIZE; 3040 3041 if (rb->rptr >= rb->capacity) 3042 rb->rptr %= rb->capacity; 3043 3044 return true; 3045 } 3046 3047 /** 3048 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3049 * 3050 * Avoids a race condition where DMCUB accesses memory while 3051 * there are still writes in flight to framebuffer. 3052 * 3053 * @param rb DMUB ringbuffer 3054 */ 3055 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3056 { 3057 uint32_t rptr = rb->rptr; 3058 uint32_t wptr = rb->wrpt; 3059 3060 while (rptr != wptr) { 3061 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3062 uint8_t i; 3063 3064 /* Don't remove this. 3065 * The contents need to actually be read from the ring buffer 3066 * for this function to be effective. 3067 */ 3068 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3069 (void)READ_ONCE(*data++); 3070 3071 rptr += DMUB_RB_CMD_SIZE; 3072 if (rptr >= rb->capacity) 3073 rptr %= rb->capacity; 3074 } 3075 } 3076 3077 /** 3078 * @brief Initializes a DMCUB ringbuffer 3079 * 3080 * @param rb DMUB ringbuffer 3081 * @param init_params initial configuration for the ringbuffer 3082 */ 3083 static inline void dmub_rb_init(struct dmub_rb *rb, 3084 struct dmub_rb_init_params *init_params) 3085 { 3086 rb->base_address = init_params->base_address; 3087 rb->capacity = init_params->capacity; 3088 rb->rptr = init_params->read_ptr; 3089 rb->wrpt = init_params->write_ptr; 3090 } 3091 3092 /** 3093 * @brief Copies output data from in/out commands into the given command. 3094 * 3095 * @param rb DMUB ringbuffer 3096 * @param cmd Command to copy data into 3097 */ 3098 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3099 union dmub_rb_cmd *cmd) 3100 { 3101 // Copy rb entry back into command 3102 uint8_t *rd_ptr = (rb->rptr == 0) ? 3103 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3104 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3105 3106 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3107 } 3108 3109 #if defined(__cplusplus) 3110 } 3111 #endif 3112 3113 //============================================================================== 3114 //</DMUB_RB>==================================================================== 3115 //============================================================================== 3116 3117 #endif /* _DMUB_CMD_H_ */ 3118