1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #include "dmub_types.h" 30 #include "atomfirmware.h" 31 32 #define DMUB_RB_CMD_SIZE 64 33 #define DMUB_RB_MAX_ENTRY 128 34 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 35 #define REG_SET_MASK 0xFFFF 36 37 enum dmub_cmd_type { 38 DMUB_CMD__NULL, 39 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE, 40 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ, 41 DMUB_CMD__REG_SEQ_BURST_WRITE, 42 DMUB_CMD__REG_REG_WAIT, 43 DMUB_CMD__DIGX_ENCODER_CONTROL, 44 DMUB_CMD__SET_PIXEL_CLOCK, 45 DMUB_CMD__ENABLE_DISP_POWER_GATING, 46 DMUB_CMD__DPPHY_INIT, 47 DMUB_CMD__DIG1_TRANSMITTER_CONTROL, 48 DMUB_CMD__SETUP_DISPLAY_MODE, 49 DMUB_CMD__BLANK_CRTC, 50 DMUB_CMD__ENABLE_DISPPATH, 51 DMUB_CMD__DISABLE_DISPPATH, 52 DMUB_CMD__DISABLE_DISPPATH_OUTPUT, 53 DMUB_CMD__READ_DISPPATH_EDID, 54 DMUB_CMD__DP_PRE_LINKTRAINING, 55 DMUB_CMD__INIT_CONTROLLER, 56 DMUB_CMD__RESET_CONTROLLER, 57 DMUB_CMD__SET_BRI_LEVEL, 58 DMUB_CMD__LVTMA_CONTROL, 59 60 // PSR 61 DMUB_CMD__PSR_ENABLE, 62 DMUB_CMD__PSR_DISABLE, 63 DMUB_CMD__PSR_COPY_SETTINGS, 64 DMUB_CMD__PSR_SET_LEVEL, 65 }; 66 67 #pragma pack(push, 1) 68 69 struct dmub_cmd_header { 70 enum dmub_cmd_type type : 8; 71 unsigned int reserved0 : 16; 72 unsigned int payload_bytes : 6; /* up to 60 bytes */ 73 unsigned int reserved : 2; 74 }; 75 76 /* 77 * Read modify write 78 * 79 * 60 payload bytes can hold up to 5 sets of read modify writes, 80 * each take 3 dwords. 81 * 82 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 83 * 84 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 85 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 86 */ 87 struct dmub_cmd_read_modify_write_sequence { 88 uint32_t addr; 89 uint32_t modify_mask; 90 uint32_t modify_value; 91 }; 92 93 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 94 struct dmub_rb_cmd_read_modify_write { 95 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 96 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 97 }; 98 99 /* 100 * Update a register with specified masks and values sequeunce 101 * 102 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 103 * 104 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 105 * 106 * 107 * USE CASE: 108 * 1. auto-increment register where additional read would update pointer and produce wrong result 109 * 2. toggle a bit without read in the middle 110 */ 111 112 struct dmub_cmd_reg_field_update_sequence { 113 uint32_t modify_mask; // 0xffff'ffff to skip initial read 114 uint32_t modify_value; 115 }; 116 117 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 118 119 struct dmub_rb_cmd_reg_field_update_sequence { 120 struct dmub_cmd_header header; 121 uint32_t addr; 122 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 123 }; 124 125 126 /* 127 * Burst write 128 * 129 * support use case such as writing out LUTs. 130 * 131 * 60 payload bytes can hold up to 14 values to write to given address 132 * 133 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 134 */ 135 #define DMUB_BURST_WRITE_VALUES__MAX 14 136 struct dmub_rb_cmd_burst_write { 137 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 138 uint32_t addr; 139 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 140 }; 141 142 143 struct dmub_rb_cmd_common { 144 struct dmub_cmd_header header; 145 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 146 }; 147 148 struct dmub_cmd_reg_wait_data { 149 uint32_t addr; 150 uint32_t mask; 151 uint32_t condition_field_value; 152 uint32_t time_out_us; 153 }; 154 155 struct dmub_rb_cmd_reg_wait { 156 struct dmub_cmd_header header; 157 struct dmub_cmd_reg_wait_data reg_wait; 158 }; 159 160 struct dmub_cmd_digx_encoder_control_data { 161 union dig_encoder_control_parameters_v1_5 dig; 162 }; 163 164 struct dmub_rb_cmd_digx_encoder_control { 165 struct dmub_cmd_header header; 166 struct dmub_cmd_digx_encoder_control_data encoder_control; 167 }; 168 169 struct dmub_cmd_set_pixel_clock_data { 170 struct set_pixel_clock_parameter_v1_7 clk; 171 }; 172 173 struct dmub_rb_cmd_set_pixel_clock { 174 struct dmub_cmd_header header; 175 struct dmub_cmd_set_pixel_clock_data pixel_clock; 176 }; 177 178 struct dmub_cmd_enable_disp_power_gating_data { 179 struct enable_disp_power_gating_parameters_v2_1 pwr; 180 }; 181 182 struct dmub_rb_cmd_enable_disp_power_gating { 183 struct dmub_cmd_header header; 184 struct dmub_cmd_enable_disp_power_gating_data power_gating; 185 }; 186 187 struct dmub_cmd_dig1_transmitter_control_data { 188 struct dig_transmitter_control_parameters_v1_6 dig; 189 }; 190 191 struct dmub_rb_cmd_dig1_transmitter_control { 192 struct dmub_cmd_header header; 193 struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 194 }; 195 196 struct dmub_rb_cmd_dpphy_init { 197 struct dmub_cmd_header header; 198 uint8_t reserved[60]; 199 }; 200 201 struct dmub_cmd_psr_copy_settings_data { 202 uint32_t reg1; 203 uint32_t reg2; 204 uint32_t reg3; 205 }; 206 207 struct dmub_rb_cmd_psr_copy_settings { 208 struct dmub_cmd_header header; 209 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 210 }; 211 212 struct dmub_cmd_psr_set_level_data { 213 uint16_t psr_level; 214 }; 215 216 struct dmub_rb_cmd_psr_set_level { 217 struct dmub_cmd_header header; 218 struct dmub_cmd_psr_set_level_data psr_set_level_data; 219 }; 220 221 struct dmub_rb_cmd_psr_disable { 222 struct dmub_cmd_header header; 223 }; 224 225 struct dmub_rb_cmd_psr_enable { 226 struct dmub_cmd_header header; 227 }; 228 229 struct dmub_cmd_psr_notify_vblank_data { 230 uint32_t vblank_int; // Which vblank interrupt was triggered 231 }; 232 233 struct dmub_rb_cmd_notify_vblank { 234 struct dmub_cmd_header header; 235 struct dmub_cmd_psr_notify_vblank_data psr_notify_vblank_data; 236 }; 237 238 struct dmub_cmd_psr_notify_static_state_data { 239 uint32_t ss_int; // Which static screen interrupt was triggered 240 uint32_t ss_enter; // Enter (1) or exit (0) static screen 241 }; 242 243 struct dmub_rb_cmd_psr_notify_static_state { 244 struct dmub_cmd_header header; 245 struct dmub_cmd_psr_notify_static_state_data psr_notify_static_state_data; 246 }; 247 248 union dmub_rb_cmd { 249 struct dmub_rb_cmd_read_modify_write read_modify_write; 250 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 251 struct dmub_rb_cmd_burst_write burst_write; 252 struct dmub_rb_cmd_reg_wait reg_wait; 253 struct dmub_rb_cmd_common cmd_common; 254 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 255 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 256 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 257 struct dmub_rb_cmd_dpphy_init dpphy_init; 258 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 259 struct dmub_rb_cmd_psr_enable psr_enable; 260 struct dmub_rb_cmd_psr_disable psr_disable; 261 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 262 struct dmub_rb_cmd_psr_set_level psr_set_level; 263 }; 264 265 #pragma pack(pop) 266 267 #endif /* _DMUB_CMD_H_ */ 268