1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 #include <stdarg.h> 34 35 #include "atomfirmware.h" 36 37 /* Firmware versioning. */ 38 #ifdef DMUB_EXPOSE_VERSION 39 #define DMUB_FW_VERSION_GIT_HASH 0x82f998da6 40 #define DMUB_FW_VERSION_MAJOR 0 41 #define DMUB_FW_VERSION_MINOR 0 42 #define DMUB_FW_VERSION_REVISION 32 43 #define DMUB_FW_VERSION_TEST 0 44 #define DMUB_FW_VERSION_VBIOS 0 45 #define DMUB_FW_VERSION_HOTFIX 0 46 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 47 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 48 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 49 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 50 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 51 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 52 53 #endif 54 55 //<DMUB_TYPES>================================================================== 56 /* Basic type definitions. */ 57 58 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 59 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 60 #define SET_ABM_PIPE_NORMAL 1 61 62 /* Maximum number of streams on any ASIC. */ 63 #define DMUB_MAX_STREAMS 6 64 65 /* Maximum number of planes on any ASIC. */ 66 #define DMUB_MAX_PLANES 6 67 68 #ifndef PHYSICAL_ADDRESS_LOC 69 #define PHYSICAL_ADDRESS_LOC union large_integer 70 #endif 71 72 #if defined(__cplusplus) 73 extern "C" { 74 #endif 75 76 #ifndef dmub_memcpy 77 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 78 #endif 79 80 #ifndef dmub_memset 81 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 82 #endif 83 84 #ifndef dmub_udelay 85 #define dmub_udelay(microseconds) udelay(microseconds) 86 #endif 87 88 union dmub_addr { 89 struct { 90 uint32_t low_part; 91 uint32_t high_part; 92 } u; 93 uint64_t quad_part; 94 }; 95 96 union dmub_psr_debug_flags { 97 struct { 98 uint32_t visual_confirm : 1; 99 uint32_t use_hw_lock_mgr : 1; 100 uint32_t log_line_nums : 1; 101 } bitfields; 102 103 uint32_t u32All; 104 }; 105 106 #if defined(__cplusplus) 107 } 108 #endif 109 110 111 112 //============================================================================== 113 //</DMUB_TYPES>================================================================= 114 //============================================================================== 115 //< DMUB_META>================================================================== 116 //============================================================================== 117 #pragma pack(push, 1) 118 119 /* Magic value for identifying dmub_fw_meta_info */ 120 #define DMUB_FW_META_MAGIC 0x444D5542 121 122 /* Offset from the end of the file to the dmub_fw_meta_info */ 123 #define DMUB_FW_META_OFFSET 0x24 124 125 /** 126 * struct dmub_fw_meta_info - metadata associated with fw binary 127 * 128 * NOTE: This should be considered a stable API. Fields should 129 * not be repurposed or reordered. New fields should be 130 * added instead to extend the structure. 131 * 132 * @magic_value: magic value identifying DMUB firmware meta info 133 * @fw_region_size: size of the firmware state region 134 * @trace_buffer_size: size of the tracebuffer region 135 * @fw_version: the firmware version information 136 * @dal_fw: 1 if the firmware is DAL 137 */ 138 struct dmub_fw_meta_info { 139 uint32_t magic_value; 140 uint32_t fw_region_size; 141 uint32_t trace_buffer_size; 142 uint32_t fw_version; 143 uint8_t dal_fw; 144 uint8_t reserved[3]; 145 }; 146 147 /* Ensure that the structure remains 64 bytes. */ 148 union dmub_fw_meta { 149 struct dmub_fw_meta_info info; 150 uint8_t reserved[64]; 151 }; 152 153 #pragma pack(pop) 154 155 //============================================================================== 156 //< DMUB_STATUS>================================================================ 157 //============================================================================== 158 159 /** 160 * DMCUB scratch registers can be used to determine firmware status. 161 * Current scratch register usage is as follows: 162 * 163 * SCRATCH0: FW Boot Status register 164 * SCRATCH15: FW Boot Options register 165 */ 166 167 /* Register bit definition for SCRATCH0 */ 168 union dmub_fw_boot_status { 169 struct { 170 uint32_t dal_fw : 1; 171 uint32_t mailbox_rdy : 1; 172 uint32_t optimized_init_done : 1; 173 uint32_t reserved : 29; 174 } bits; 175 uint32_t all; 176 }; 177 178 enum dmub_fw_boot_status_bit { 179 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), 180 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), 181 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 182 }; 183 184 /* Register bit definition for SCRATCH15 */ 185 union dmub_fw_boot_options { 186 struct { 187 uint32_t pemu_env : 1; 188 uint32_t fpga_env : 1; 189 uint32_t optimized_init : 1; 190 uint32_t reserved : 29; 191 } bits; 192 uint32_t all; 193 }; 194 195 enum dmub_fw_boot_options_bit { 196 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), 197 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), 198 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 199 }; 200 201 //============================================================================== 202 //</DMUB_STATUS>================================================================ 203 //============================================================================== 204 //< DMUB_VBIOS>================================================================= 205 //============================================================================== 206 207 /* 208 * Command IDs should be treated as stable ABI. 209 * Do not reuse or modify IDs. 210 */ 211 212 enum dmub_cmd_vbios_type { 213 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 214 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 215 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 216 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 217 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 218 }; 219 220 //============================================================================== 221 //</DMUB_VBIOS>================================================================= 222 //============================================================================== 223 //< DMUB_GPINT>================================================================= 224 //============================================================================== 225 226 /** 227 * The shifts and masks below may alternatively be used to format and read 228 * the command register bits. 229 */ 230 231 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 232 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 233 234 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 235 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 236 237 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 238 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 239 240 /** 241 * Command responses. 242 */ 243 244 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 245 246 /** 247 * The register format for sending a command via the GPINT. 248 */ 249 union dmub_gpint_data_register { 250 struct { 251 uint32_t param : 16; 252 uint32_t command_code : 12; 253 uint32_t status : 4; 254 } bits; 255 uint32_t all; 256 }; 257 258 /* 259 * Command IDs should be treated as stable ABI. 260 * Do not reuse or modify IDs. 261 */ 262 263 enum dmub_gpint_command { 264 DMUB_GPINT__INVALID_COMMAND = 0, 265 DMUB_GPINT__GET_FW_VERSION = 1, 266 DMUB_GPINT__STOP_FW = 2, 267 DMUB_GPINT__GET_PSR_STATE = 7, 268 /** 269 * DESC: Notifies DMCUB of the currently active streams. 270 * ARGS: Stream mask, 1 bit per active stream index. 271 */ 272 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 273 }; 274 275 //============================================================================== 276 //</DMUB_GPINT>================================================================= 277 //============================================================================== 278 //< DMUB_CMD>=================================================================== 279 //============================================================================== 280 281 #define DMUB_RB_CMD_SIZE 64 282 #define DMUB_RB_MAX_ENTRY 128 283 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 284 #define REG_SET_MASK 0xFFFF 285 286 /* 287 * Command IDs should be treated as stable ABI. 288 * Do not reuse or modify IDs. 289 */ 290 291 enum dmub_cmd_type { 292 DMUB_CMD__NULL = 0, 293 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 294 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 295 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 296 DMUB_CMD__REG_REG_WAIT = 4, 297 DMUB_CMD__PLAT_54186_WA = 5, 298 DMUB_CMD__PSR = 64, 299 DMUB_CMD__ABM = 66, 300 DMUB_CMD__HW_LOCK = 69, 301 DMUB_CMD__VBIOS = 128, 302 }; 303 304 #pragma pack(push, 1) 305 306 struct dmub_cmd_header { 307 unsigned int type : 8; 308 unsigned int sub_type : 8; 309 unsigned int reserved0 : 8; 310 unsigned int payload_bytes : 6; /* up to 60 bytes */ 311 unsigned int reserved1 : 2; 312 }; 313 314 /* 315 * Read modify write 316 * 317 * 60 payload bytes can hold up to 5 sets of read modify writes, 318 * each take 3 dwords. 319 * 320 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 321 * 322 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 323 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 324 */ 325 struct dmub_cmd_read_modify_write_sequence { 326 uint32_t addr; 327 uint32_t modify_mask; 328 uint32_t modify_value; 329 }; 330 331 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 332 struct dmub_rb_cmd_read_modify_write { 333 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 334 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 335 }; 336 337 /* 338 * Update a register with specified masks and values sequeunce 339 * 340 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 341 * 342 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 343 * 344 * 345 * USE CASE: 346 * 1. auto-increment register where additional read would update pointer and produce wrong result 347 * 2. toggle a bit without read in the middle 348 */ 349 350 struct dmub_cmd_reg_field_update_sequence { 351 uint32_t modify_mask; // 0xffff'ffff to skip initial read 352 uint32_t modify_value; 353 }; 354 355 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 356 struct dmub_rb_cmd_reg_field_update_sequence { 357 struct dmub_cmd_header header; 358 uint32_t addr; 359 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 360 }; 361 362 /* 363 * Burst write 364 * 365 * support use case such as writing out LUTs. 366 * 367 * 60 payload bytes can hold up to 14 values to write to given address 368 * 369 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 370 */ 371 #define DMUB_BURST_WRITE_VALUES__MAX 14 372 struct dmub_rb_cmd_burst_write { 373 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 374 uint32_t addr; 375 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 376 }; 377 378 379 struct dmub_rb_cmd_common { 380 struct dmub_cmd_header header; 381 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 382 }; 383 384 struct dmub_cmd_reg_wait_data { 385 uint32_t addr; 386 uint32_t mask; 387 uint32_t condition_field_value; 388 uint32_t time_out_us; 389 }; 390 391 struct dmub_rb_cmd_reg_wait { 392 struct dmub_cmd_header header; 393 struct dmub_cmd_reg_wait_data reg_wait; 394 }; 395 396 struct dmub_cmd_PLAT_54186_wa { 397 uint32_t DCSURF_SURFACE_CONTROL; 398 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 399 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 400 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 401 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 402 struct { 403 uint8_t hubp_inst : 4; 404 uint8_t tmz_surface : 1; 405 uint8_t immediate :1; 406 uint8_t vmid : 4; 407 uint8_t grph_stereo : 1; 408 uint32_t reserved : 21; 409 } flip_params; 410 uint32_t reserved[9]; 411 }; 412 413 struct dmub_rb_cmd_PLAT_54186_wa { 414 struct dmub_cmd_header header; 415 struct dmub_cmd_PLAT_54186_wa flip; 416 }; 417 418 struct dmub_cmd_digx_encoder_control_data { 419 union dig_encoder_control_parameters_v1_5 dig; 420 }; 421 422 struct dmub_rb_cmd_digx_encoder_control { 423 struct dmub_cmd_header header; 424 struct dmub_cmd_digx_encoder_control_data encoder_control; 425 }; 426 427 struct dmub_cmd_set_pixel_clock_data { 428 struct set_pixel_clock_parameter_v1_7 clk; 429 }; 430 431 struct dmub_rb_cmd_set_pixel_clock { 432 struct dmub_cmd_header header; 433 struct dmub_cmd_set_pixel_clock_data pixel_clock; 434 }; 435 436 struct dmub_cmd_enable_disp_power_gating_data { 437 struct enable_disp_power_gating_parameters_v2_1 pwr; 438 }; 439 440 struct dmub_rb_cmd_enable_disp_power_gating { 441 struct dmub_cmd_header header; 442 struct dmub_cmd_enable_disp_power_gating_data power_gating; 443 }; 444 445 struct dmub_cmd_dig1_transmitter_control_data { 446 struct dig_transmitter_control_parameters_v1_6 dig; 447 }; 448 449 struct dmub_rb_cmd_dig1_transmitter_control { 450 struct dmub_cmd_header header; 451 struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 452 }; 453 454 struct dmub_rb_cmd_dpphy_init { 455 struct dmub_cmd_header header; 456 uint8_t reserved[60]; 457 }; 458 459 /* 460 * Command IDs should be treated as stable ABI. 461 * Do not reuse or modify IDs. 462 */ 463 464 enum dmub_cmd_psr_type { 465 DMUB_CMD__PSR_SET_VERSION = 0, 466 DMUB_CMD__PSR_COPY_SETTINGS = 1, 467 DMUB_CMD__PSR_ENABLE = 2, 468 DMUB_CMD__PSR_DISABLE = 3, 469 DMUB_CMD__PSR_SET_LEVEL = 4, 470 }; 471 472 enum psr_version { 473 PSR_VERSION_1 = 0, 474 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 475 }; 476 477 struct dmub_cmd_psr_copy_settings_data { 478 union dmub_psr_debug_flags debug; 479 uint16_t psr_level; 480 uint8_t dpp_inst; 481 uint8_t mpcc_inst; 482 uint8_t opp_inst; 483 uint8_t otg_inst; 484 uint8_t digfe_inst; 485 uint8_t digbe_inst; 486 uint8_t dpphy_inst; 487 uint8_t aux_inst; 488 uint8_t smu_optimizations_en; 489 uint8_t frame_delay; 490 uint8_t frame_cap_ind; 491 uint8_t pad[3]; 492 uint16_t init_sdp_deadline; 493 uint16_t pad2; 494 }; 495 496 struct dmub_rb_cmd_psr_copy_settings { 497 struct dmub_cmd_header header; 498 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 499 }; 500 501 struct dmub_cmd_psr_set_level_data { 502 uint16_t psr_level; 503 uint8_t pad[2]; 504 }; 505 506 struct dmub_rb_cmd_psr_set_level { 507 struct dmub_cmd_header header; 508 struct dmub_cmd_psr_set_level_data psr_set_level_data; 509 }; 510 511 struct dmub_rb_cmd_psr_enable { 512 struct dmub_cmd_header header; 513 }; 514 515 struct dmub_cmd_psr_set_version_data { 516 enum psr_version version; // PSR version 1 or 2 517 }; 518 519 struct dmub_rb_cmd_psr_set_version { 520 struct dmub_cmd_header header; 521 struct dmub_cmd_psr_set_version_data psr_set_version_data; 522 }; 523 524 union dmub_hw_lock_flags { 525 struct { 526 uint8_t lock_pipe : 1; 527 uint8_t lock_cursor : 1; 528 uint8_t lock_dig : 1; 529 uint8_t triple_buffer_lock : 1; 530 } bits; 531 532 uint8_t u8All; 533 }; 534 535 struct dmub_hw_lock_inst_flags { 536 uint8_t otg_inst; 537 uint8_t opp_inst; 538 uint8_t dig_inst; 539 uint8_t pad; 540 }; 541 542 enum hw_lock_client { 543 HW_LOCK_CLIENT_DRIVER = 0, 544 HW_LOCK_CLIENT_FW, 545 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 546 }; 547 548 struct dmub_cmd_lock_hw_data { 549 enum hw_lock_client client; 550 struct dmub_hw_lock_inst_flags inst_flags; 551 union dmub_hw_lock_flags hw_locks; 552 uint8_t lock; 553 uint8_t should_release; 554 uint8_t pad; 555 }; 556 557 struct dmub_rb_cmd_lock_hw { 558 struct dmub_cmd_header header; 559 struct dmub_cmd_lock_hw_data lock_hw_data; 560 }; 561 562 enum dmub_cmd_abm_type { 563 DMUB_CMD__ABM_INIT_CONFIG = 0, 564 DMUB_CMD__ABM_SET_PIPE = 1, 565 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 566 DMUB_CMD__ABM_SET_LEVEL = 3, 567 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 568 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 569 }; 570 571 #define NUM_AMBI_LEVEL 5 572 #define NUM_AGGR_LEVEL 4 573 #define NUM_POWER_FN_SEGS 8 574 #define NUM_BL_CURVE_SEGS 16 575 576 /* 577 * Parameters for ABM2.4 algorithm. 578 * Padded explicitly to 32-bit boundary. 579 */ 580 struct abm_config_table { 581 /* Parameters for crgb conversion */ 582 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 583 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 15B 584 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 31B 585 586 /* Parameters for custom curve */ 587 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 47B 588 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 79B 589 590 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 111B 591 uint16_t min_abm_backlight; // 121B 592 593 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 123B 594 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 143B 595 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 163B 596 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 183B 597 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 203B 598 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 207B 599 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 211B 600 uint8_t min_knee[NUM_AGGR_LEVEL]; // 215B 601 uint8_t max_knee[NUM_AGGR_LEVEL]; // 219B 602 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 223B 603 uint8_t pad3[3]; // 228B 604 }; 605 606 struct dmub_cmd_abm_set_pipe_data { 607 uint8_t otg_inst; 608 uint8_t panel_inst; 609 uint8_t set_pipe_option; 610 uint8_t ramping_boundary; // TODO: Remove this 611 }; 612 613 struct dmub_rb_cmd_abm_set_pipe { 614 struct dmub_cmd_header header; 615 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 616 }; 617 618 struct dmub_cmd_abm_set_backlight_data { 619 uint32_t frame_ramp; 620 uint32_t backlight_user_level; 621 }; 622 623 struct dmub_rb_cmd_abm_set_backlight { 624 struct dmub_cmd_header header; 625 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 626 }; 627 628 struct dmub_cmd_abm_set_level_data { 629 uint32_t level; 630 }; 631 632 struct dmub_rb_cmd_abm_set_level { 633 struct dmub_cmd_header header; 634 struct dmub_cmd_abm_set_level_data abm_set_level_data; 635 }; 636 637 struct dmub_cmd_abm_set_ambient_level_data { 638 uint32_t ambient_lux; 639 }; 640 641 struct dmub_rb_cmd_abm_set_ambient_level { 642 struct dmub_cmd_header header; 643 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 644 }; 645 646 struct dmub_cmd_abm_set_pwm_frac_data { 647 uint32_t fractional_pwm; 648 }; 649 650 struct dmub_rb_cmd_abm_set_pwm_frac { 651 struct dmub_cmd_header header; 652 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 653 }; 654 655 struct dmub_cmd_abm_init_config_data { 656 union dmub_addr src; 657 uint16_t bytes; 658 }; 659 660 struct dmub_rb_cmd_abm_init_config { 661 struct dmub_cmd_header header; 662 struct dmub_cmd_abm_init_config_data abm_init_config_data; 663 }; 664 665 union dmub_rb_cmd { 666 struct dmub_rb_cmd_lock_hw lock_hw; 667 struct dmub_rb_cmd_read_modify_write read_modify_write; 668 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 669 struct dmub_rb_cmd_burst_write burst_write; 670 struct dmub_rb_cmd_reg_wait reg_wait; 671 struct dmub_rb_cmd_common cmd_common; 672 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 673 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 674 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 675 struct dmub_rb_cmd_dpphy_init dpphy_init; 676 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 677 struct dmub_rb_cmd_psr_set_version psr_set_version; 678 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 679 struct dmub_rb_cmd_psr_enable psr_enable; 680 struct dmub_rb_cmd_psr_set_level psr_set_level; 681 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 682 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 683 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 684 struct dmub_rb_cmd_abm_set_level abm_set_level; 685 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 686 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 687 struct dmub_rb_cmd_abm_init_config abm_init_config; 688 }; 689 690 #pragma pack(pop) 691 692 693 //============================================================================== 694 //</DMUB_CMD>=================================================================== 695 //============================================================================== 696 //< DMUB_RB>==================================================================== 697 //============================================================================== 698 699 #if defined(__cplusplus) 700 extern "C" { 701 #endif 702 703 struct dmub_rb_init_params { 704 void *ctx; 705 void *base_address; 706 uint32_t capacity; 707 uint32_t read_ptr; 708 uint32_t write_ptr; 709 }; 710 711 struct dmub_rb { 712 void *base_address; 713 uint32_t data_count; 714 uint32_t rptr; 715 uint32_t wrpt; 716 uint32_t capacity; 717 718 void *ctx; 719 void *dmub; 720 }; 721 722 723 static inline bool dmub_rb_empty(struct dmub_rb *rb) 724 { 725 return (rb->wrpt == rb->rptr); 726 } 727 728 static inline bool dmub_rb_full(struct dmub_rb *rb) 729 { 730 uint32_t data_count; 731 732 if (rb->wrpt >= rb->rptr) 733 data_count = rb->wrpt - rb->rptr; 734 else 735 data_count = rb->capacity - (rb->rptr - rb->wrpt); 736 737 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 738 } 739 740 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 741 const union dmub_rb_cmd *cmd) 742 { 743 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 744 const uint64_t *src = (const uint64_t *)cmd; 745 int i; 746 747 if (dmub_rb_full(rb)) 748 return false; 749 750 // copying data 751 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 752 *dst++ = *src++; 753 754 rb->wrpt += DMUB_RB_CMD_SIZE; 755 756 if (rb->wrpt >= rb->capacity) 757 rb->wrpt %= rb->capacity; 758 759 return true; 760 } 761 762 static inline bool dmub_rb_front(struct dmub_rb *rb, 763 union dmub_rb_cmd *cmd) 764 { 765 uint8_t *rd_ptr = (uint8_t *)rb->base_address + rb->rptr; 766 767 if (dmub_rb_empty(rb)) 768 return false; 769 770 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 771 772 return true; 773 } 774 775 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 776 { 777 if (dmub_rb_empty(rb)) 778 return false; 779 780 rb->rptr += DMUB_RB_CMD_SIZE; 781 782 if (rb->rptr >= rb->capacity) 783 rb->rptr %= rb->capacity; 784 785 return true; 786 } 787 788 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 789 { 790 uint32_t rptr = rb->rptr; 791 uint32_t wptr = rb->wrpt; 792 793 while (rptr != wptr) { 794 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 795 //uint64_t volatile *p = (uint64_t volatile *)data; 796 uint64_t temp; 797 int i; 798 799 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 800 temp = *data++; 801 802 rptr += DMUB_RB_CMD_SIZE; 803 if (rptr >= rb->capacity) 804 rptr %= rb->capacity; 805 } 806 } 807 808 static inline void dmub_rb_init(struct dmub_rb *rb, 809 struct dmub_rb_init_params *init_params) 810 { 811 rb->base_address = init_params->base_address; 812 rb->capacity = init_params->capacity; 813 rb->rptr = init_params->read_ptr; 814 rb->wrpt = init_params->write_ptr; 815 } 816 817 #if defined(__cplusplus) 818 } 819 #endif 820 821 //============================================================================== 822 //</DMUB_RB>==================================================================== 823 //============================================================================== 824 825 #endif /* _DMUB_CMD_H_ */ 826