1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_CMD_H_ 27 #define _DMUB_CMD_H_ 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 #include <stdarg.h> 34 35 #include "atomfirmware.h" 36 37 /* Firmware versioning. */ 38 #ifdef DMUB_EXPOSE_VERSION 39 #define DMUB_FW_VERSION_GIT_HASH 0x52d68b82f 40 #define DMUB_FW_VERSION_MAJOR 0 41 #define DMUB_FW_VERSION_MINOR 0 42 #define DMUB_FW_VERSION_REVISION 42 43 #define DMUB_FW_VERSION_TEST 0 44 #define DMUB_FW_VERSION_VBIOS 0 45 #define DMUB_FW_VERSION_HOTFIX 0 46 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 47 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 48 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 49 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 50 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 51 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 52 53 #endif 54 55 //<DMUB_TYPES>================================================================== 56 /* Basic type definitions. */ 57 58 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 59 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 #define SET_ABM_PIPE_NORMAL 1 62 63 /* Maximum number of streams on any ASIC. */ 64 #define DMUB_MAX_STREAMS 6 65 66 /* Maximum number of planes on any ASIC. */ 67 #define DMUB_MAX_PLANES 6 68 69 #ifndef PHYSICAL_ADDRESS_LOC 70 #define PHYSICAL_ADDRESS_LOC union large_integer 71 #endif 72 73 #ifndef dmub_memcpy 74 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 75 #endif 76 77 #ifndef dmub_memset 78 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 79 #endif 80 81 #if defined(__cplusplus) 82 extern "C" { 83 #endif 84 85 #ifndef dmub_udelay 86 #define dmub_udelay(microseconds) udelay(microseconds) 87 #endif 88 89 union dmub_addr { 90 struct { 91 uint32_t low_part; 92 uint32_t high_part; 93 } u; 94 uint64_t quad_part; 95 }; 96 97 union dmub_psr_debug_flags { 98 struct { 99 uint32_t visual_confirm : 1; 100 uint32_t use_hw_lock_mgr : 1; 101 uint32_t log_line_nums : 1; 102 } bitfields; 103 104 uint32_t u32All; 105 }; 106 107 #if defined(__cplusplus) 108 } 109 #endif 110 111 112 113 //============================================================================== 114 //</DMUB_TYPES>================================================================= 115 //============================================================================== 116 //< DMUB_META>================================================================== 117 //============================================================================== 118 #pragma pack(push, 1) 119 120 /* Magic value for identifying dmub_fw_meta_info */ 121 #define DMUB_FW_META_MAGIC 0x444D5542 122 123 /* Offset from the end of the file to the dmub_fw_meta_info */ 124 #define DMUB_FW_META_OFFSET 0x24 125 126 /** 127 * struct dmub_fw_meta_info - metadata associated with fw binary 128 * 129 * NOTE: This should be considered a stable API. Fields should 130 * not be repurposed or reordered. New fields should be 131 * added instead to extend the structure. 132 * 133 * @magic_value: magic value identifying DMUB firmware meta info 134 * @fw_region_size: size of the firmware state region 135 * @trace_buffer_size: size of the tracebuffer region 136 * @fw_version: the firmware version information 137 * @dal_fw: 1 if the firmware is DAL 138 */ 139 struct dmub_fw_meta_info { 140 uint32_t magic_value; 141 uint32_t fw_region_size; 142 uint32_t trace_buffer_size; 143 uint32_t fw_version; 144 uint8_t dal_fw; 145 uint8_t reserved[3]; 146 }; 147 148 /* Ensure that the structure remains 64 bytes. */ 149 union dmub_fw_meta { 150 struct dmub_fw_meta_info info; 151 uint8_t reserved[64]; 152 }; 153 154 #pragma pack(pop) 155 156 //============================================================================== 157 //< DMUB_STATUS>================================================================ 158 //============================================================================== 159 160 /** 161 * DMCUB scratch registers can be used to determine firmware status. 162 * Current scratch register usage is as follows: 163 * 164 * SCRATCH0: FW Boot Status register 165 * SCRATCH15: FW Boot Options register 166 */ 167 168 /* Register bit definition for SCRATCH0 */ 169 union dmub_fw_boot_status { 170 struct { 171 uint32_t dal_fw : 1; 172 uint32_t mailbox_rdy : 1; 173 uint32_t optimized_init_done : 1; 174 uint32_t restore_required : 1; 175 } bits; 176 uint32_t all; 177 }; 178 179 enum dmub_fw_boot_status_bit { 180 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), 181 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), 182 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 183 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), 184 }; 185 186 /* Register bit definition for SCRATCH15 */ 187 union dmub_fw_boot_options { 188 struct { 189 uint32_t pemu_env : 1; 190 uint32_t fpga_env : 1; 191 uint32_t optimized_init : 1; 192 uint32_t skip_phy_access : 1; 193 uint32_t disable_clk_gate: 1; 194 uint32_t skip_phy_init_panel_sequence: 1; 195 uint32_t reserved : 26; 196 } bits; 197 uint32_t all; 198 }; 199 200 enum dmub_fw_boot_options_bit { 201 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), 202 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), 203 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 204 }; 205 206 //============================================================================== 207 //</DMUB_STATUS>================================================================ 208 //============================================================================== 209 //< DMUB_VBIOS>================================================================= 210 //============================================================================== 211 212 /* 213 * Command IDs should be treated as stable ABI. 214 * Do not reuse or modify IDs. 215 */ 216 217 enum dmub_cmd_vbios_type { 218 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 219 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 220 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 221 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 222 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 223 }; 224 225 //============================================================================== 226 //</DMUB_VBIOS>================================================================= 227 //============================================================================== 228 //< DMUB_GPINT>================================================================= 229 //============================================================================== 230 231 /** 232 * The shifts and masks below may alternatively be used to format and read 233 * the command register bits. 234 */ 235 236 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 237 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 238 239 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 240 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 241 242 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 243 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 244 245 /** 246 * Command responses. 247 */ 248 249 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 250 251 /** 252 * The register format for sending a command via the GPINT. 253 */ 254 union dmub_gpint_data_register { 255 struct { 256 uint32_t param : 16; 257 uint32_t command_code : 12; 258 uint32_t status : 4; 259 } bits; 260 uint32_t all; 261 }; 262 263 /* 264 * Command IDs should be treated as stable ABI. 265 * Do not reuse or modify IDs. 266 */ 267 268 enum dmub_gpint_command { 269 DMUB_GPINT__INVALID_COMMAND = 0, 270 DMUB_GPINT__GET_FW_VERSION = 1, 271 DMUB_GPINT__STOP_FW = 2, 272 DMUB_GPINT__GET_PSR_STATE = 7, 273 /** 274 * DESC: Notifies DMCUB of the currently active streams. 275 * ARGS: Stream mask, 1 bit per active stream index. 276 */ 277 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 278 DMUB_GPINT__PSR_RESIDENCY = 9, 279 }; 280 281 //============================================================================== 282 //</DMUB_GPINT>================================================================= 283 //============================================================================== 284 //< DMUB_CMD>=================================================================== 285 //============================================================================== 286 287 #define DMUB_RB_CMD_SIZE 64 288 #define DMUB_RB_MAX_ENTRY 128 289 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 290 #define REG_SET_MASK 0xFFFF 291 292 /* 293 * Command IDs should be treated as stable ABI. 294 * Do not reuse or modify IDs. 295 */ 296 297 enum dmub_cmd_type { 298 DMUB_CMD__NULL = 0, 299 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 300 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 301 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 302 DMUB_CMD__REG_REG_WAIT = 4, 303 DMUB_CMD__PLAT_54186_WA = 5, 304 DMUB_CMD__PSR = 64, 305 DMUB_CMD__MALL = 65, 306 DMUB_CMD__ABM = 66, 307 DMUB_CMD__HW_LOCK = 69, 308 DMUB_CMD__DP_AUX_ACCESS = 70, 309 DMUB_CMD__OUTBOX1_ENABLE = 71, 310 DMUB_CMD__VBIOS = 128, 311 }; 312 313 enum dmub_out_cmd_type { 314 DMUB_OUT_CMD__NULL = 0, 315 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 316 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 317 }; 318 319 #pragma pack(push, 1) 320 321 struct dmub_cmd_header { 322 unsigned int type : 8; 323 unsigned int sub_type : 8; 324 unsigned int reserved0 : 8; 325 unsigned int payload_bytes : 6; /* up to 60 bytes */ 326 unsigned int reserved1 : 2; 327 }; 328 329 /* 330 * Read modify write 331 * 332 * 60 payload bytes can hold up to 5 sets of read modify writes, 333 * each take 3 dwords. 334 * 335 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 336 * 337 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 338 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 339 */ 340 struct dmub_cmd_read_modify_write_sequence { 341 uint32_t addr; 342 uint32_t modify_mask; 343 uint32_t modify_value; 344 }; 345 346 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 347 struct dmub_rb_cmd_read_modify_write { 348 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 349 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 350 }; 351 352 /* 353 * Update a register with specified masks and values sequeunce 354 * 355 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 356 * 357 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 358 * 359 * 360 * USE CASE: 361 * 1. auto-increment register where additional read would update pointer and produce wrong result 362 * 2. toggle a bit without read in the middle 363 */ 364 365 struct dmub_cmd_reg_field_update_sequence { 366 uint32_t modify_mask; // 0xffff'ffff to skip initial read 367 uint32_t modify_value; 368 }; 369 370 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 371 struct dmub_rb_cmd_reg_field_update_sequence { 372 struct dmub_cmd_header header; 373 uint32_t addr; 374 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 375 }; 376 377 /* 378 * Burst write 379 * 380 * support use case such as writing out LUTs. 381 * 382 * 60 payload bytes can hold up to 14 values to write to given address 383 * 384 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 385 */ 386 #define DMUB_BURST_WRITE_VALUES__MAX 14 387 struct dmub_rb_cmd_burst_write { 388 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 389 uint32_t addr; 390 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 391 }; 392 393 394 struct dmub_rb_cmd_common { 395 struct dmub_cmd_header header; 396 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 397 }; 398 399 struct dmub_cmd_reg_wait_data { 400 uint32_t addr; 401 uint32_t mask; 402 uint32_t condition_field_value; 403 uint32_t time_out_us; 404 }; 405 406 struct dmub_rb_cmd_reg_wait { 407 struct dmub_cmd_header header; 408 struct dmub_cmd_reg_wait_data reg_wait; 409 }; 410 411 struct dmub_cmd_PLAT_54186_wa { 412 uint32_t DCSURF_SURFACE_CONTROL; 413 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 414 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 415 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 416 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 417 struct { 418 uint8_t hubp_inst : 4; 419 uint8_t tmz_surface : 1; 420 uint8_t immediate :1; 421 uint8_t vmid : 4; 422 uint8_t grph_stereo : 1; 423 uint32_t reserved : 21; 424 } flip_params; 425 uint32_t reserved[9]; 426 }; 427 428 struct dmub_rb_cmd_PLAT_54186_wa { 429 struct dmub_cmd_header header; 430 struct dmub_cmd_PLAT_54186_wa flip; 431 }; 432 433 struct dmub_rb_cmd_mall { 434 struct dmub_cmd_header header; 435 union dmub_addr cursor_copy_src; 436 union dmub_addr cursor_copy_dst; 437 uint32_t tmr_delay; 438 uint32_t tmr_scale; 439 uint16_t cursor_width; 440 uint16_t cursor_pitch; 441 uint16_t cursor_height; 442 uint8_t cursor_bpp; 443 }; 444 445 struct dmub_cmd_digx_encoder_control_data { 446 union dig_encoder_control_parameters_v1_5 dig; 447 }; 448 449 struct dmub_rb_cmd_digx_encoder_control { 450 struct dmub_cmd_header header; 451 struct dmub_cmd_digx_encoder_control_data encoder_control; 452 }; 453 454 struct dmub_cmd_set_pixel_clock_data { 455 struct set_pixel_clock_parameter_v1_7 clk; 456 }; 457 458 struct dmub_rb_cmd_set_pixel_clock { 459 struct dmub_cmd_header header; 460 struct dmub_cmd_set_pixel_clock_data pixel_clock; 461 }; 462 463 struct dmub_cmd_enable_disp_power_gating_data { 464 struct enable_disp_power_gating_parameters_v2_1 pwr; 465 }; 466 467 struct dmub_rb_cmd_enable_disp_power_gating { 468 struct dmub_cmd_header header; 469 struct dmub_cmd_enable_disp_power_gating_data power_gating; 470 }; 471 472 struct dmub_cmd_dig1_transmitter_control_data { 473 struct dig_transmitter_control_parameters_v1_6 dig; 474 }; 475 476 struct dmub_rb_cmd_dig1_transmitter_control { 477 struct dmub_cmd_header header; 478 struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 479 }; 480 481 struct dmub_rb_cmd_dpphy_init { 482 struct dmub_cmd_header header; 483 uint8_t reserved[60]; 484 }; 485 486 enum dp_aux_request_action { 487 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 488 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 489 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 490 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 491 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 492 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 493 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 494 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 495 }; 496 497 enum aux_return_code_type { 498 AUX_RET_SUCCESS = 0, 499 AUX_RET_ERROR_TIMEOUT, 500 AUX_RET_ERROR_NO_DATA, 501 AUX_RET_ERROR_INVALID_OPERATION, 502 AUX_RET_ERROR_PROTOCOL_ERROR, 503 }; 504 505 /* DP AUX command */ 506 struct aux_transaction_parameters { 507 uint8_t is_i2c_over_aux; 508 uint8_t action; 509 uint8_t length; 510 uint8_t pad; 511 uint32_t address; 512 uint8_t data[16]; 513 }; 514 515 struct dmub_cmd_dp_aux_control_data { 516 uint32_t handle; 517 uint8_t port_index; 518 uint8_t sw_crc_enabled; 519 uint16_t timeout; 520 struct aux_transaction_parameters dpaux; 521 }; 522 523 struct dmub_rb_cmd_dp_aux_access { 524 struct dmub_cmd_header header; 525 struct dmub_cmd_dp_aux_control_data aux_control; 526 }; 527 528 struct dmub_rb_cmd_outbox1_enable { 529 struct dmub_cmd_header header; 530 uint32_t enable; 531 }; 532 533 /* DP AUX Reply command - OutBox Cmd */ 534 struct aux_reply_data { 535 uint8_t command; 536 uint8_t length; 537 uint8_t pad[2]; 538 uint8_t data[16]; 539 }; 540 541 struct aux_reply_control_data { 542 uint32_t handle; 543 uint8_t phy_port_index; 544 uint8_t result; 545 uint16_t pad; 546 }; 547 548 struct dmub_rb_cmd_dp_aux_reply { 549 struct dmub_cmd_header header; 550 struct aux_reply_control_data control; 551 struct aux_reply_data reply_data; 552 }; 553 554 /* DP HPD Notify command - OutBox Cmd */ 555 enum dp_hpd_type { 556 DP_HPD = 0, 557 DP_IRQ 558 }; 559 560 enum dp_hpd_status { 561 DP_HPD_UNPLUG = 0, 562 DP_HPD_PLUG 563 }; 564 565 struct dp_hpd_data { 566 uint8_t phy_port_index; 567 uint8_t hpd_type; 568 uint8_t hpd_status; 569 uint8_t pad; 570 }; 571 572 struct dmub_rb_cmd_dp_hpd_notify { 573 struct dmub_cmd_header header; 574 struct dp_hpd_data hpd_data; 575 }; 576 577 /* 578 * Command IDs should be treated as stable ABI. 579 * Do not reuse or modify IDs. 580 */ 581 582 enum dmub_cmd_psr_type { 583 DMUB_CMD__PSR_SET_VERSION = 0, 584 DMUB_CMD__PSR_COPY_SETTINGS = 1, 585 DMUB_CMD__PSR_ENABLE = 2, 586 DMUB_CMD__PSR_DISABLE = 3, 587 DMUB_CMD__PSR_SET_LEVEL = 4, 588 DMUB_CMD__PSR_FORCE_STATIC = 5, 589 }; 590 591 enum psr_version { 592 PSR_VERSION_1 = 0, 593 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 594 }; 595 596 enum dmub_cmd_mall_type { 597 DMUB_CMD__MALL_ACTION_ALLOW = 0, 598 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 599 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 600 }; 601 602 struct dmub_cmd_psr_copy_settings_data { 603 union dmub_psr_debug_flags debug; 604 uint16_t psr_level; 605 uint8_t dpp_inst; 606 uint8_t mpcc_inst; 607 uint8_t opp_inst; 608 uint8_t otg_inst; 609 uint8_t digfe_inst; 610 uint8_t digbe_inst; 611 uint8_t dpphy_inst; 612 uint8_t aux_inst; 613 uint8_t smu_optimizations_en; 614 uint8_t frame_delay; 615 uint8_t frame_cap_ind; 616 uint8_t pad[2]; 617 uint8_t multi_disp_optimizations_en; 618 uint16_t init_sdp_deadline; 619 uint16_t pad2; 620 }; 621 622 struct dmub_rb_cmd_psr_copy_settings { 623 struct dmub_cmd_header header; 624 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 625 }; 626 627 struct dmub_cmd_psr_set_level_data { 628 uint16_t psr_level; 629 uint8_t pad[2]; 630 }; 631 632 struct dmub_rb_cmd_psr_set_level { 633 struct dmub_cmd_header header; 634 struct dmub_cmd_psr_set_level_data psr_set_level_data; 635 }; 636 637 struct dmub_rb_cmd_psr_enable { 638 struct dmub_cmd_header header; 639 }; 640 641 struct dmub_cmd_psr_set_version_data { 642 enum psr_version version; // PSR version 1 or 2 643 }; 644 645 struct dmub_rb_cmd_psr_set_version { 646 struct dmub_cmd_header header; 647 struct dmub_cmd_psr_set_version_data psr_set_version_data; 648 }; 649 650 struct dmub_rb_cmd_psr_force_static { 651 struct dmub_cmd_header header; 652 }; 653 654 union dmub_hw_lock_flags { 655 struct { 656 uint8_t lock_pipe : 1; 657 uint8_t lock_cursor : 1; 658 uint8_t lock_dig : 1; 659 uint8_t triple_buffer_lock : 1; 660 } bits; 661 662 uint8_t u8All; 663 }; 664 665 struct dmub_hw_lock_inst_flags { 666 uint8_t otg_inst; 667 uint8_t opp_inst; 668 uint8_t dig_inst; 669 uint8_t pad; 670 }; 671 672 enum hw_lock_client { 673 HW_LOCK_CLIENT_DRIVER = 0, 674 HW_LOCK_CLIENT_FW, 675 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 676 }; 677 678 struct dmub_cmd_lock_hw_data { 679 enum hw_lock_client client; 680 struct dmub_hw_lock_inst_flags inst_flags; 681 union dmub_hw_lock_flags hw_locks; 682 uint8_t lock; 683 uint8_t should_release; 684 uint8_t pad; 685 }; 686 687 struct dmub_rb_cmd_lock_hw { 688 struct dmub_cmd_header header; 689 struct dmub_cmd_lock_hw_data lock_hw_data; 690 }; 691 692 enum dmub_cmd_abm_type { 693 DMUB_CMD__ABM_INIT_CONFIG = 0, 694 DMUB_CMD__ABM_SET_PIPE = 1, 695 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 696 DMUB_CMD__ABM_SET_LEVEL = 3, 697 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 698 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 699 }; 700 701 #define NUM_AMBI_LEVEL 5 702 #define NUM_AGGR_LEVEL 4 703 #define NUM_POWER_FN_SEGS 8 704 #define NUM_BL_CURVE_SEGS 16 705 706 /* 707 * Parameters for ABM2.4 algorithm. 708 * Padded explicitly to 32-bit boundary. 709 */ 710 struct abm_config_table { 711 /* Parameters for crgb conversion */ 712 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 713 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 15B 714 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 31B 715 716 /* Parameters for custom curve */ 717 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 47B 718 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 79B 719 720 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 111B 721 uint16_t min_abm_backlight; // 121B 722 723 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 123B 724 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 143B 725 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 163B 726 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 183B 727 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 203B 728 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 207B 729 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 211B 730 uint8_t min_knee[NUM_AGGR_LEVEL]; // 215B 731 uint8_t max_knee[NUM_AGGR_LEVEL]; // 219B 732 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 223B 733 uint8_t pad3[3]; // 228B 734 }; 735 736 struct dmub_cmd_abm_set_pipe_data { 737 uint8_t otg_inst; 738 uint8_t panel_inst; 739 uint8_t set_pipe_option; 740 uint8_t ramping_boundary; // TODO: Remove this 741 }; 742 743 struct dmub_rb_cmd_abm_set_pipe { 744 struct dmub_cmd_header header; 745 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 746 }; 747 748 struct dmub_cmd_abm_set_backlight_data { 749 uint32_t frame_ramp; 750 uint32_t backlight_user_level; 751 }; 752 753 struct dmub_rb_cmd_abm_set_backlight { 754 struct dmub_cmd_header header; 755 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 756 }; 757 758 struct dmub_cmd_abm_set_level_data { 759 uint32_t level; 760 }; 761 762 struct dmub_rb_cmd_abm_set_level { 763 struct dmub_cmd_header header; 764 struct dmub_cmd_abm_set_level_data abm_set_level_data; 765 }; 766 767 struct dmub_cmd_abm_set_ambient_level_data { 768 uint32_t ambient_lux; 769 }; 770 771 struct dmub_rb_cmd_abm_set_ambient_level { 772 struct dmub_cmd_header header; 773 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 774 }; 775 776 struct dmub_cmd_abm_set_pwm_frac_data { 777 uint32_t fractional_pwm; 778 }; 779 780 struct dmub_rb_cmd_abm_set_pwm_frac { 781 struct dmub_cmd_header header; 782 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 783 }; 784 785 struct dmub_cmd_abm_init_config_data { 786 union dmub_addr src; 787 uint16_t bytes; 788 }; 789 790 struct dmub_rb_cmd_abm_init_config { 791 struct dmub_cmd_header header; 792 struct dmub_cmd_abm_init_config_data abm_init_config_data; 793 }; 794 795 union dmub_rb_cmd { 796 struct dmub_rb_cmd_lock_hw lock_hw; 797 struct dmub_rb_cmd_read_modify_write read_modify_write; 798 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 799 struct dmub_rb_cmd_burst_write burst_write; 800 struct dmub_rb_cmd_reg_wait reg_wait; 801 struct dmub_rb_cmd_common cmd_common; 802 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 803 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 804 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 805 struct dmub_rb_cmd_dpphy_init dpphy_init; 806 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 807 struct dmub_rb_cmd_psr_set_version psr_set_version; 808 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 809 struct dmub_rb_cmd_psr_enable psr_enable; 810 struct dmub_rb_cmd_psr_set_level psr_set_level; 811 struct dmub_rb_cmd_psr_force_static psr_force_static; 812 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 813 struct dmub_rb_cmd_mall mall; 814 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 815 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 816 struct dmub_rb_cmd_abm_set_level abm_set_level; 817 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 818 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 819 struct dmub_rb_cmd_abm_init_config abm_init_config; 820 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 821 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 822 }; 823 824 union dmub_rb_out_cmd { 825 struct dmub_rb_cmd_common cmd_common; 826 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 827 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 828 }; 829 #pragma pack(pop) 830 831 832 //============================================================================== 833 //</DMUB_CMD>=================================================================== 834 //============================================================================== 835 //< DMUB_RB>==================================================================== 836 //============================================================================== 837 838 #if defined(__cplusplus) 839 extern "C" { 840 #endif 841 842 struct dmub_rb_init_params { 843 void *ctx; 844 void *base_address; 845 uint32_t capacity; 846 uint32_t read_ptr; 847 uint32_t write_ptr; 848 }; 849 850 struct dmub_rb { 851 void *base_address; 852 uint32_t data_count; 853 uint32_t rptr; 854 uint32_t wrpt; 855 uint32_t capacity; 856 857 void *ctx; 858 void *dmub; 859 }; 860 861 862 static inline bool dmub_rb_empty(struct dmub_rb *rb) 863 { 864 return (rb->wrpt == rb->rptr); 865 } 866 867 static inline bool dmub_rb_full(struct dmub_rb *rb) 868 { 869 uint32_t data_count; 870 871 if (rb->wrpt >= rb->rptr) 872 data_count = rb->wrpt - rb->rptr; 873 else 874 data_count = rb->capacity - (rb->rptr - rb->wrpt); 875 876 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 877 } 878 879 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 880 const union dmub_rb_cmd *cmd) 881 { 882 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 883 const uint64_t *src = (const uint64_t *)cmd; 884 int i; 885 886 if (dmub_rb_full(rb)) 887 return false; 888 889 // copying data 890 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 891 *dst++ = *src++; 892 893 rb->wrpt += DMUB_RB_CMD_SIZE; 894 895 if (rb->wrpt >= rb->capacity) 896 rb->wrpt %= rb->capacity; 897 898 return true; 899 } 900 901 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 902 const union dmub_rb_out_cmd *cmd) 903 { 904 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 905 const uint8_t *src = (uint8_t *)cmd; 906 907 if (dmub_rb_full(rb)) 908 return false; 909 910 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 911 912 rb->wrpt += DMUB_RB_CMD_SIZE; 913 914 if (rb->wrpt >= rb->capacity) 915 rb->wrpt %= rb->capacity; 916 917 return true; 918 } 919 920 static inline bool dmub_rb_front(struct dmub_rb *rb, 921 union dmub_rb_cmd *cmd) 922 { 923 uint8_t *rd_ptr = (uint8_t *)rb->base_address + rb->rptr; 924 925 if (dmub_rb_empty(rb)) 926 return false; 927 928 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 929 930 return true; 931 } 932 933 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 934 union dmub_rb_out_cmd *cmd) 935 { 936 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 937 uint64_t *dst = (uint64_t *)cmd; 938 int i; 939 940 if (dmub_rb_empty(rb)) 941 return false; 942 943 // copying data 944 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 945 *dst++ = *src++; 946 947 return true; 948 } 949 950 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 951 { 952 if (dmub_rb_empty(rb)) 953 return false; 954 955 rb->rptr += DMUB_RB_CMD_SIZE; 956 957 if (rb->rptr >= rb->capacity) 958 rb->rptr %= rb->capacity; 959 960 return true; 961 } 962 963 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 964 { 965 uint32_t rptr = rb->rptr; 966 uint32_t wptr = rb->wrpt; 967 968 while (rptr != wptr) { 969 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 970 int i; 971 972 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 973 *data++; 974 975 rptr += DMUB_RB_CMD_SIZE; 976 if (rptr >= rb->capacity) 977 rptr %= rb->capacity; 978 } 979 } 980 981 static inline void dmub_rb_init(struct dmub_rb *rb, 982 struct dmub_rb_init_params *init_params) 983 { 984 rb->base_address = init_params->base_address; 985 rb->capacity = init_params->capacity; 986 rb->rptr = init_params->read_ptr; 987 rb->wrpt = init_params->write_ptr; 988 } 989 990 #if defined(__cplusplus) 991 } 992 #endif 993 994 //============================================================================== 995 //</DMUB_RB>==================================================================== 996 //============================================================================== 997 998 #endif /* _DMUB_CMD_H_ */ 999