1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 /* Firmware versioning. */ 48 #ifdef DMUB_EXPOSE_VERSION 49 #define DMUB_FW_VERSION_GIT_HASH 0x1d82d23e 50 #define DMUB_FW_VERSION_MAJOR 0 51 #define DMUB_FW_VERSION_MINOR 0 52 #define DMUB_FW_VERSION_REVISION 91 53 #define DMUB_FW_VERSION_TEST 0 54 #define DMUB_FW_VERSION_VBIOS 0 55 #define DMUB_FW_VERSION_HOTFIX 0 56 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 57 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 58 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 59 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 60 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 61 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 62 63 #endif 64 65 //<DMUB_TYPES>================================================================== 66 /* Basic type definitions. */ 67 68 #define __forceinline inline 69 70 /** 71 * Flag from driver to indicate that ABM should be disabled gradually 72 * by slowly reversing all backlight programming and pixel compensation. 73 */ 74 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 75 76 /** 77 * Flag from driver to indicate that ABM should be disabled immediately 78 * and undo all backlight programming and pixel compensation. 79 */ 80 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 81 82 /** 83 * Flag from driver to indicate that ABM should be disabled immediately 84 * and keep the current backlight programming and pixel compensation. 85 */ 86 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 87 88 /** 89 * Flag from driver to set the current ABM pipe index or ABM operating level. 90 */ 91 #define SET_ABM_PIPE_NORMAL 1 92 93 /** 94 * Number of ambient light levels in ABM algorithm. 95 */ 96 #define NUM_AMBI_LEVEL 5 97 98 /** 99 * Number of operating/aggression levels in ABM algorithm. 100 */ 101 #define NUM_AGGR_LEVEL 4 102 103 /** 104 * Number of segments in the gamma curve. 105 */ 106 #define NUM_POWER_FN_SEGS 8 107 108 /** 109 * Number of segments in the backlight curve. 110 */ 111 #define NUM_BL_CURVE_SEGS 16 112 113 /* Maximum number of streams on any ASIC. */ 114 #define DMUB_MAX_STREAMS 6 115 116 /* Maximum number of planes on any ASIC. */ 117 #define DMUB_MAX_PLANES 6 118 119 /* Trace buffer offset for entry */ 120 #define TRACE_BUFFER_ENTRY_OFFSET 16 121 122 /** 123 * 124 * PSR control version legacy 125 */ 126 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 127 /** 128 * PSR control version with multi edp support 129 */ 130 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 131 132 133 /** 134 * ABM control version legacy 135 */ 136 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 137 138 /** 139 * ABM control version with multi edp support 140 */ 141 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 142 143 /** 144 * Physical framebuffer address location, 64-bit. 145 */ 146 #ifndef PHYSICAL_ADDRESS_LOC 147 #define PHYSICAL_ADDRESS_LOC union large_integer 148 #endif 149 150 /** 151 * OS/FW agnostic memcpy 152 */ 153 #ifndef dmub_memcpy 154 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 155 #endif 156 157 /** 158 * OS/FW agnostic memset 159 */ 160 #ifndef dmub_memset 161 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 162 #endif 163 164 #if defined(__cplusplus) 165 extern "C" { 166 #endif 167 168 /** 169 * OS/FW agnostic udelay 170 */ 171 #ifndef dmub_udelay 172 #define dmub_udelay(microseconds) udelay(microseconds) 173 #endif 174 175 /** 176 * Number of nanoseconds per DMUB tick. 177 * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default. 178 * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true. 179 */ 180 #define NS_PER_DMUB_TICK 10 181 182 /** 183 * union dmub_addr - DMUB physical/virtual 64-bit address. 184 */ 185 union dmub_addr { 186 struct { 187 uint32_t low_part; /**< Lower 32 bits */ 188 uint32_t high_part; /**< Upper 32 bits */ 189 } u; /*<< Low/high bit access */ 190 uint64_t quad_part; /*<< 64 bit address */ 191 }; 192 193 /** 194 * Flags that can be set by driver to change some PSR behaviour. 195 */ 196 union dmub_psr_debug_flags { 197 /** 198 * Debug flags. 199 */ 200 struct { 201 /** 202 * Enable visual confirm in FW. 203 */ 204 uint32_t visual_confirm : 1; 205 /** 206 * Use HW Lock Mgr object to do HW locking in FW. 207 */ 208 uint32_t use_hw_lock_mgr : 1; 209 210 /** 211 * Unused. 212 * TODO: Remove. 213 */ 214 uint32_t log_line_nums : 1; 215 } bitfields; 216 217 /** 218 * Union for debug flags. 219 */ 220 uint32_t u32All; 221 }; 222 223 /** 224 * DMUB feature capabilities. 225 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 226 */ 227 struct dmub_feature_caps { 228 /** 229 * Max PSR version supported by FW. 230 */ 231 uint8_t psr; 232 uint8_t reserved[7]; 233 }; 234 235 #if defined(__cplusplus) 236 } 237 #endif 238 239 //============================================================================== 240 //</DMUB_TYPES>================================================================= 241 //============================================================================== 242 //< DMUB_META>================================================================== 243 //============================================================================== 244 #pragma pack(push, 1) 245 246 /* Magic value for identifying dmub_fw_meta_info */ 247 #define DMUB_FW_META_MAGIC 0x444D5542 248 249 /* Offset from the end of the file to the dmub_fw_meta_info */ 250 #define DMUB_FW_META_OFFSET 0x24 251 252 /** 253 * struct dmub_fw_meta_info - metadata associated with fw binary 254 * 255 * NOTE: This should be considered a stable API. Fields should 256 * not be repurposed or reordered. New fields should be 257 * added instead to extend the structure. 258 * 259 * @magic_value: magic value identifying DMUB firmware meta info 260 * @fw_region_size: size of the firmware state region 261 * @trace_buffer_size: size of the tracebuffer region 262 * @fw_version: the firmware version information 263 * @dal_fw: 1 if the firmware is DAL 264 */ 265 struct dmub_fw_meta_info { 266 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 267 uint32_t fw_region_size; /**< size of the firmware state region */ 268 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 269 uint32_t fw_version; /**< the firmware version information */ 270 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 271 uint8_t reserved[3]; /**< padding bits */ 272 }; 273 274 /** 275 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 276 */ 277 union dmub_fw_meta { 278 struct dmub_fw_meta_info info; /**< metadata info */ 279 uint8_t reserved[64]; /**< padding bits */ 280 }; 281 282 #pragma pack(pop) 283 284 //============================================================================== 285 //< DMUB Trace Buffer>================================================================ 286 //============================================================================== 287 /** 288 * dmub_trace_code_t - firmware trace code, 32-bits 289 */ 290 typedef uint32_t dmub_trace_code_t; 291 292 /** 293 * struct dmcub_trace_buf_entry - Firmware trace entry 294 */ 295 struct dmcub_trace_buf_entry { 296 dmub_trace_code_t trace_code; /**< trace code for the event */ 297 uint32_t tick_count; /**< the tick count at time of trace */ 298 uint32_t param0; /**< trace defined parameter 0 */ 299 uint32_t param1; /**< trace defined parameter 1 */ 300 }; 301 302 //============================================================================== 303 //< DMUB_STATUS>================================================================ 304 //============================================================================== 305 306 /** 307 * DMCUB scratch registers can be used to determine firmware status. 308 * Current scratch register usage is as follows: 309 * 310 * SCRATCH0: FW Boot Status register 311 * SCRATCH5: LVTMA Status Register 312 * SCRATCH15: FW Boot Options register 313 */ 314 315 /** 316 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 317 */ 318 union dmub_fw_boot_status { 319 struct { 320 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 321 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 322 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 323 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 324 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 325 uint32_t reserved : 1; 326 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 327 328 } bits; /**< status bits */ 329 uint32_t all; /**< 32-bit access to status bits */ 330 }; 331 332 /** 333 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 334 */ 335 enum dmub_fw_boot_status_bit { 336 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 337 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 338 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 339 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 340 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 341 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 342 }; 343 344 /* Register bit definition for SCRATCH5 */ 345 union dmub_lvtma_status { 346 struct { 347 uint32_t psp_ok : 1; 348 uint32_t edp_on : 1; 349 uint32_t reserved : 30; 350 } bits; 351 uint32_t all; 352 }; 353 354 enum dmub_lvtma_status_bit { 355 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 356 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 357 }; 358 359 /** 360 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 361 */ 362 union dmub_fw_boot_options { 363 struct { 364 uint32_t pemu_env : 1; /**< 1 if PEMU */ 365 uint32_t fpga_env : 1; /**< 1 if FPGA */ 366 uint32_t optimized_init : 1; /**< 1 if optimized init */ 367 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 368 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 369 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 370 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 371 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 372 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 373 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 374 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 375 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 376 uint32_t power_optimization: 1; 377 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 378 379 uint32_t reserved : 19; /**< reserved */ 380 } bits; /**< boot bits */ 381 uint32_t all; /**< 32-bit access to bits */ 382 }; 383 384 enum dmub_fw_boot_options_bit { 385 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 386 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 387 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 388 }; 389 390 //============================================================================== 391 //</DMUB_STATUS>================================================================ 392 //============================================================================== 393 //< DMUB_VBIOS>================================================================= 394 //============================================================================== 395 396 /* 397 * enum dmub_cmd_vbios_type - VBIOS commands. 398 * 399 * Command IDs should be treated as stable ABI. 400 * Do not reuse or modify IDs. 401 */ 402 enum dmub_cmd_vbios_type { 403 /** 404 * Configures the DIG encoder. 405 */ 406 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 407 /** 408 * Controls the PHY. 409 */ 410 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 411 /** 412 * Sets the pixel clock/symbol clock. 413 */ 414 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 415 /** 416 * Enables or disables power gating. 417 */ 418 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 419 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 420 }; 421 422 //============================================================================== 423 //</DMUB_VBIOS>================================================================= 424 //============================================================================== 425 //< DMUB_GPINT>================================================================= 426 //============================================================================== 427 428 /** 429 * The shifts and masks below may alternatively be used to format and read 430 * the command register bits. 431 */ 432 433 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 434 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 435 436 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 437 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 438 439 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 440 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 441 442 /** 443 * Command responses. 444 */ 445 446 /** 447 * Return response for DMUB_GPINT__STOP_FW command. 448 */ 449 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 450 451 /** 452 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 453 */ 454 union dmub_gpint_data_register { 455 struct { 456 uint32_t param : 16; /**< 16-bit parameter */ 457 uint32_t command_code : 12; /**< GPINT command */ 458 uint32_t status : 4; /**< Command status bit */ 459 } bits; /**< GPINT bit access */ 460 uint32_t all; /**< GPINT 32-bit access */ 461 }; 462 463 /* 464 * enum dmub_gpint_command - GPINT command to DMCUB FW 465 * 466 * Command IDs should be treated as stable ABI. 467 * Do not reuse or modify IDs. 468 */ 469 enum dmub_gpint_command { 470 /** 471 * Invalid command, ignored. 472 */ 473 DMUB_GPINT__INVALID_COMMAND = 0, 474 /** 475 * DESC: Queries the firmware version. 476 * RETURN: Firmware version. 477 */ 478 DMUB_GPINT__GET_FW_VERSION = 1, 479 /** 480 * DESC: Halts the firmware. 481 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 482 */ 483 DMUB_GPINT__STOP_FW = 2, 484 /** 485 * DESC: Get PSR state from FW. 486 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 487 */ 488 DMUB_GPINT__GET_PSR_STATE = 7, 489 /** 490 * DESC: Notifies DMCUB of the currently active streams. 491 * ARGS: Stream mask, 1 bit per active stream index. 492 */ 493 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 494 /** 495 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 496 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 497 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 498 * RETURN: PSR residency in milli-percent. 499 */ 500 DMUB_GPINT__PSR_RESIDENCY = 9, 501 502 /** 503 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 504 */ 505 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 506 }; 507 508 /** 509 * INBOX0 generic command definition 510 */ 511 union dmub_inbox0_cmd_common { 512 struct { 513 uint32_t command_code: 8; /**< INBOX0 command code */ 514 uint32_t param: 24; /**< 24-bit parameter */ 515 } bits; 516 uint32_t all; 517 }; 518 519 /** 520 * INBOX0 hw_lock command definition 521 */ 522 union dmub_inbox0_cmd_lock_hw { 523 struct { 524 uint32_t command_code: 8; 525 526 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 527 uint32_t hw_lock_client: 1; 528 529 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 530 uint32_t otg_inst: 3; 531 uint32_t opp_inst: 3; 532 uint32_t dig_inst: 3; 533 534 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 535 uint32_t lock_pipe: 1; 536 uint32_t lock_cursor: 1; 537 uint32_t lock_dig: 1; 538 uint32_t triple_buffer_lock: 1; 539 540 uint32_t lock: 1; /**< Lock */ 541 uint32_t should_release: 1; /**< Release */ 542 uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ 543 } bits; 544 uint32_t all; 545 }; 546 547 union dmub_inbox0_data_register { 548 union dmub_inbox0_cmd_common inbox0_cmd_common; 549 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 550 }; 551 552 enum dmub_inbox0_command { 553 /** 554 * DESC: Invalid command, ignored. 555 */ 556 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 557 /** 558 * DESC: Notification to acquire/release HW lock 559 * ARGS: 560 */ 561 DMUB_INBOX0_CMD__HW_LOCK = 1, 562 }; 563 //============================================================================== 564 //</DMUB_GPINT>================================================================= 565 //============================================================================== 566 //< DMUB_CMD>=================================================================== 567 //============================================================================== 568 569 /** 570 * Size in bytes of each DMUB command. 571 */ 572 #define DMUB_RB_CMD_SIZE 64 573 574 /** 575 * Maximum number of items in the DMUB ringbuffer. 576 */ 577 #define DMUB_RB_MAX_ENTRY 128 578 579 /** 580 * Ringbuffer size in bytes. 581 */ 582 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 583 584 /** 585 * REG_SET mask for reg offload. 586 */ 587 #define REG_SET_MASK 0xFFFF 588 589 /* 590 * enum dmub_cmd_type - DMUB inbox command. 591 * 592 * Command IDs should be treated as stable ABI. 593 * Do not reuse or modify IDs. 594 */ 595 enum dmub_cmd_type { 596 /** 597 * Invalid command. 598 */ 599 DMUB_CMD__NULL = 0, 600 /** 601 * Read modify write register sequence offload. 602 */ 603 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 604 /** 605 * Field update register sequence offload. 606 */ 607 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 608 /** 609 * Burst write sequence offload. 610 */ 611 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 612 /** 613 * Reg wait sequence offload. 614 */ 615 DMUB_CMD__REG_REG_WAIT = 4, 616 /** 617 * Workaround to avoid HUBP underflow during NV12 playback. 618 */ 619 DMUB_CMD__PLAT_54186_WA = 5, 620 /** 621 * Command type used to query FW feature caps. 622 */ 623 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 624 /** 625 * Command type used for all PSR commands. 626 */ 627 DMUB_CMD__PSR = 64, 628 /** 629 * Command type used for all MALL commands. 630 */ 631 DMUB_CMD__MALL = 65, 632 /** 633 * Command type used for all ABM commands. 634 */ 635 DMUB_CMD__ABM = 66, 636 /** 637 * Command type used for HW locking in FW. 638 */ 639 DMUB_CMD__HW_LOCK = 69, 640 /** 641 * Command type used to access DP AUX. 642 */ 643 DMUB_CMD__DP_AUX_ACCESS = 70, 644 /** 645 * Command type used for OUTBOX1 notification enable 646 */ 647 DMUB_CMD__OUTBOX1_ENABLE = 71, 648 /** 649 * Command type used for all idle optimization commands. 650 */ 651 DMUB_CMD__IDLE_OPT = 72, 652 /** 653 * Command type used for all clock manager commands. 654 */ 655 DMUB_CMD__CLK_MGR = 73, 656 /** 657 * Command type used for all panel control commands. 658 */ 659 DMUB_CMD__PANEL_CNTL = 74, 660 /** 661 * Command type used for interfacing with DPIA. 662 */ 663 DMUB_CMD__DPIA = 77, 664 /** 665 * Command type used for EDID CEA parsing 666 */ 667 DMUB_CMD__EDID_CEA = 79, 668 /** 669 * Command type used for all VBIOS interface commands. 670 */ 671 DMUB_CMD__VBIOS = 128, 672 }; 673 674 /** 675 * enum dmub_out_cmd_type - DMUB outbox commands. 676 */ 677 enum dmub_out_cmd_type { 678 /** 679 * Invalid outbox command, ignored. 680 */ 681 DMUB_OUT_CMD__NULL = 0, 682 /** 683 * Command type used for DP AUX Reply data notification 684 */ 685 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 686 /** 687 * Command type used for DP HPD event notification 688 */ 689 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 690 /** 691 * Command type used for SET_CONFIG Reply notification 692 */ 693 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 694 }; 695 696 /* DMUB_CMD__DPIA command sub-types. */ 697 enum dmub_cmd_dpia_type { 698 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 699 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 700 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 701 }; 702 703 #pragma pack(push, 1) 704 705 /** 706 * struct dmub_cmd_header - Common command header fields. 707 */ 708 struct dmub_cmd_header { 709 unsigned int type : 8; /**< command type */ 710 unsigned int sub_type : 8; /**< command sub type */ 711 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 712 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 713 unsigned int reserved0 : 6; /**< reserved bits */ 714 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 715 unsigned int reserved1 : 2; /**< reserved bits */ 716 }; 717 718 /* 719 * struct dmub_cmd_read_modify_write_sequence - Read modify write 720 * 721 * 60 payload bytes can hold up to 5 sets of read modify writes, 722 * each take 3 dwords. 723 * 724 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 725 * 726 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 727 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 728 */ 729 struct dmub_cmd_read_modify_write_sequence { 730 uint32_t addr; /**< register address */ 731 uint32_t modify_mask; /**< modify mask */ 732 uint32_t modify_value; /**< modify value */ 733 }; 734 735 /** 736 * Maximum number of ops in read modify write sequence. 737 */ 738 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 739 740 /** 741 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 742 */ 743 struct dmub_rb_cmd_read_modify_write { 744 struct dmub_cmd_header header; /**< command header */ 745 /** 746 * Read modify write sequence. 747 */ 748 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 749 }; 750 751 /* 752 * Update a register with specified masks and values sequeunce 753 * 754 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 755 * 756 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 757 * 758 * 759 * USE CASE: 760 * 1. auto-increment register where additional read would update pointer and produce wrong result 761 * 2. toggle a bit without read in the middle 762 */ 763 764 struct dmub_cmd_reg_field_update_sequence { 765 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 766 uint32_t modify_value; /**< value to update with */ 767 }; 768 769 /** 770 * Maximum number of ops in field update sequence. 771 */ 772 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 773 774 /** 775 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 776 */ 777 struct dmub_rb_cmd_reg_field_update_sequence { 778 struct dmub_cmd_header header; /**< command header */ 779 uint32_t addr; /**< register address */ 780 /** 781 * Field update sequence. 782 */ 783 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 784 }; 785 786 787 /** 788 * Maximum number of burst write values. 789 */ 790 #define DMUB_BURST_WRITE_VALUES__MAX 14 791 792 /* 793 * struct dmub_rb_cmd_burst_write - Burst write 794 * 795 * support use case such as writing out LUTs. 796 * 797 * 60 payload bytes can hold up to 14 values to write to given address 798 * 799 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 800 */ 801 struct dmub_rb_cmd_burst_write { 802 struct dmub_cmd_header header; /**< command header */ 803 uint32_t addr; /**< register start address */ 804 /** 805 * Burst write register values. 806 */ 807 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 808 }; 809 810 /** 811 * struct dmub_rb_cmd_common - Common command header 812 */ 813 struct dmub_rb_cmd_common { 814 struct dmub_cmd_header header; /**< command header */ 815 /** 816 * Padding to RB_CMD_SIZE 817 */ 818 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 819 }; 820 821 /** 822 * struct dmub_cmd_reg_wait_data - Register wait data 823 */ 824 struct dmub_cmd_reg_wait_data { 825 uint32_t addr; /**< Register address */ 826 uint32_t mask; /**< Mask for register bits */ 827 uint32_t condition_field_value; /**< Value to wait for */ 828 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 829 }; 830 831 /** 832 * struct dmub_rb_cmd_reg_wait - Register wait command 833 */ 834 struct dmub_rb_cmd_reg_wait { 835 struct dmub_cmd_header header; /**< Command header */ 836 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 837 }; 838 839 /** 840 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 841 * 842 * Reprograms surface parameters to avoid underflow. 843 */ 844 struct dmub_cmd_PLAT_54186_wa { 845 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 846 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 847 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 848 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 849 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 850 struct { 851 uint8_t hubp_inst : 4; /**< HUBP instance */ 852 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 853 uint8_t immediate :1; /**< Immediate flip */ 854 uint8_t vmid : 4; /**< VMID */ 855 uint8_t grph_stereo : 1; /**< 1 if stereo */ 856 uint32_t reserved : 21; /**< Reserved */ 857 } flip_params; /**< Pageflip parameters */ 858 uint32_t reserved[9]; /**< Reserved bits */ 859 }; 860 861 /** 862 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 863 */ 864 struct dmub_rb_cmd_PLAT_54186_wa { 865 struct dmub_cmd_header header; /**< Command header */ 866 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 867 }; 868 869 /** 870 * struct dmub_rb_cmd_mall - MALL command data. 871 */ 872 struct dmub_rb_cmd_mall { 873 struct dmub_cmd_header header; /**< Common command header */ 874 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 875 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 876 uint32_t tmr_delay; /**< Timer delay */ 877 uint32_t tmr_scale; /**< Timer scale */ 878 uint16_t cursor_width; /**< Cursor width in pixels */ 879 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 880 uint16_t cursor_height; /**< Cursor height in pixels */ 881 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 882 uint8_t debug_bits; /**< Debug bits */ 883 884 uint8_t reserved1; /**< Reserved bits */ 885 uint8_t reserved2; /**< Reserved bits */ 886 }; 887 888 /** 889 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 890 */ 891 enum dmub_cmd_idle_opt_type { 892 /** 893 * DCN hardware restore. 894 */ 895 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 896 897 /** 898 * DCN hardware save. 899 */ 900 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 901 }; 902 903 /** 904 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 905 */ 906 struct dmub_rb_cmd_idle_opt_dcn_restore { 907 struct dmub_cmd_header header; /**< header */ 908 }; 909 910 /** 911 * struct dmub_clocks - Clock update notification. 912 */ 913 struct dmub_clocks { 914 uint32_t dispclk_khz; /**< dispclk kHz */ 915 uint32_t dppclk_khz; /**< dppclk kHz */ 916 uint32_t dcfclk_khz; /**< dcfclk kHz */ 917 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 918 }; 919 920 /** 921 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 922 */ 923 enum dmub_cmd_clk_mgr_type { 924 /** 925 * Notify DMCUB of clock update. 926 */ 927 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 928 }; 929 930 /** 931 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 932 */ 933 struct dmub_rb_cmd_clk_mgr_notify_clocks { 934 struct dmub_cmd_header header; /**< header */ 935 struct dmub_clocks clocks; /**< clock data */ 936 }; 937 938 /** 939 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 940 */ 941 struct dmub_cmd_digx_encoder_control_data { 942 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 943 }; 944 945 /** 946 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 947 */ 948 struct dmub_rb_cmd_digx_encoder_control { 949 struct dmub_cmd_header header; /**< header */ 950 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 951 }; 952 953 /** 954 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 955 */ 956 struct dmub_cmd_set_pixel_clock_data { 957 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 958 }; 959 960 /** 961 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 962 */ 963 struct dmub_rb_cmd_set_pixel_clock { 964 struct dmub_cmd_header header; /**< header */ 965 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 966 }; 967 968 /** 969 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 970 */ 971 struct dmub_cmd_enable_disp_power_gating_data { 972 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 973 }; 974 975 /** 976 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 977 */ 978 struct dmub_rb_cmd_enable_disp_power_gating { 979 struct dmub_cmd_header header; /**< header */ 980 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 981 }; 982 983 /** 984 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 985 */ 986 struct dmub_dig_transmitter_control_data_v1_7 { 987 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 988 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 989 union { 990 uint8_t digmode; /**< enum atom_encode_mode_def */ 991 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 992 } mode_laneset; 993 uint8_t lanenum; /**< Number of lanes */ 994 union { 995 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 996 } symclk_units; 997 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 998 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 999 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1000 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1001 uint8_t reserved1; /**< For future use */ 1002 uint8_t reserved2[3]; /**< For future use */ 1003 uint32_t reserved3[11]; /**< For future use */ 1004 }; 1005 1006 /** 1007 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1008 */ 1009 union dmub_cmd_dig1_transmitter_control_data { 1010 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1011 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1012 }; 1013 1014 /** 1015 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1016 */ 1017 struct dmub_rb_cmd_dig1_transmitter_control { 1018 struct dmub_cmd_header header; /**< header */ 1019 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1020 }; 1021 1022 /** 1023 * DPIA tunnel command parameters. 1024 */ 1025 struct dmub_cmd_dig_dpia_control_data { 1026 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1027 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1028 union { 1029 uint8_t digmode; /** enum atom_encode_mode_def */ 1030 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1031 } mode_laneset; 1032 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1033 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1034 uint8_t hpdsel; /** =0: HPD is not assigned */ 1035 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1036 uint8_t dpia_id; /** Index of DPIA */ 1037 uint8_t fec_rdy : 1; 1038 uint8_t reserved : 7; 1039 uint32_t reserved1; 1040 }; 1041 1042 /** 1043 * DMUB command for DPIA tunnel control. 1044 */ 1045 struct dmub_rb_cmd_dig1_dpia_control { 1046 struct dmub_cmd_header header; 1047 struct dmub_cmd_dig_dpia_control_data dpia_control; 1048 }; 1049 1050 /** 1051 * SET_CONFIG Command Payload 1052 */ 1053 struct set_config_cmd_payload { 1054 uint8_t msg_type; /* set config message type */ 1055 uint8_t msg_data; /* set config message data */ 1056 }; 1057 1058 /** 1059 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1060 */ 1061 struct dmub_cmd_set_config_control_data { 1062 struct set_config_cmd_payload cmd_pkt; 1063 uint8_t instance; /* DPIA instance */ 1064 uint8_t immed_status; /* Immediate status returned in case of error */ 1065 }; 1066 1067 /** 1068 * DMUB command structure for SET_CONFIG command. 1069 */ 1070 struct dmub_rb_cmd_set_config_access { 1071 struct dmub_cmd_header header; /* header */ 1072 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1073 }; 1074 1075 /** 1076 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1077 */ 1078 struct dmub_cmd_mst_alloc_slots_control_data { 1079 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1080 uint8_t instance; /* DPIA instance */ 1081 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1082 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1083 }; 1084 1085 /** 1086 * DMUB command structure for SET_ command. 1087 */ 1088 struct dmub_rb_cmd_set_mst_alloc_slots { 1089 struct dmub_cmd_header header; /* header */ 1090 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1091 }; 1092 1093 /** 1094 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1095 */ 1096 struct dmub_rb_cmd_dpphy_init { 1097 struct dmub_cmd_header header; /**< header */ 1098 uint8_t reserved[60]; /**< reserved bits */ 1099 }; 1100 1101 /** 1102 * enum dp_aux_request_action - DP AUX request command listing. 1103 * 1104 * 4 AUX request command bits are shifted to high nibble. 1105 */ 1106 enum dp_aux_request_action { 1107 /** I2C-over-AUX write request */ 1108 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1109 /** I2C-over-AUX read request */ 1110 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1111 /** I2C-over-AUX write status request */ 1112 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1113 /** I2C-over-AUX write request with MOT=1 */ 1114 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1115 /** I2C-over-AUX read request with MOT=1 */ 1116 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1117 /** I2C-over-AUX write status request with MOT=1 */ 1118 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1119 /** Native AUX write request */ 1120 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1121 /** Native AUX read request */ 1122 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1123 }; 1124 1125 /** 1126 * enum aux_return_code_type - DP AUX process return code listing. 1127 */ 1128 enum aux_return_code_type { 1129 /** AUX process succeeded */ 1130 AUX_RET_SUCCESS = 0, 1131 /** AUX process failed with unknown reason */ 1132 AUX_RET_ERROR_UNKNOWN, 1133 /** AUX process completed with invalid reply */ 1134 AUX_RET_ERROR_INVALID_REPLY, 1135 /** AUX process timed out */ 1136 AUX_RET_ERROR_TIMEOUT, 1137 /** HPD was low during AUX process */ 1138 AUX_RET_ERROR_HPD_DISCON, 1139 /** Failed to acquire AUX engine */ 1140 AUX_RET_ERROR_ENGINE_ACQUIRE, 1141 /** AUX request not supported */ 1142 AUX_RET_ERROR_INVALID_OPERATION, 1143 /** AUX process not available */ 1144 AUX_RET_ERROR_PROTOCOL_ERROR, 1145 }; 1146 1147 /** 1148 * enum aux_channel_type - DP AUX channel type listing. 1149 */ 1150 enum aux_channel_type { 1151 /** AUX thru Legacy DP AUX */ 1152 AUX_CHANNEL_LEGACY_DDC, 1153 /** AUX thru DPIA DP tunneling */ 1154 AUX_CHANNEL_DPIA 1155 }; 1156 1157 /** 1158 * struct aux_transaction_parameters - DP AUX request transaction data 1159 */ 1160 struct aux_transaction_parameters { 1161 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1162 uint8_t action; /**< enum dp_aux_request_action */ 1163 uint8_t length; /**< DP AUX request data length */ 1164 uint8_t reserved; /**< For future use */ 1165 uint32_t address; /**< DP AUX address */ 1166 uint8_t data[16]; /**< DP AUX write data */ 1167 }; 1168 1169 /** 1170 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1171 */ 1172 struct dmub_cmd_dp_aux_control_data { 1173 uint8_t instance; /**< AUX instance or DPIA instance */ 1174 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1175 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1176 uint8_t reserved0; /**< For future use */ 1177 uint16_t timeout; /**< timeout time in us */ 1178 uint16_t reserved1; /**< For future use */ 1179 enum aux_channel_type type; /**< enum aux_channel_type */ 1180 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1181 }; 1182 1183 /** 1184 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1185 */ 1186 struct dmub_rb_cmd_dp_aux_access { 1187 /** 1188 * Command header. 1189 */ 1190 struct dmub_cmd_header header; 1191 /** 1192 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1193 */ 1194 struct dmub_cmd_dp_aux_control_data aux_control; 1195 }; 1196 1197 /** 1198 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1199 */ 1200 struct dmub_rb_cmd_outbox1_enable { 1201 /** 1202 * Command header. 1203 */ 1204 struct dmub_cmd_header header; 1205 /** 1206 * enable: 0x0 -> disable outbox1 notification (default value) 1207 * 0x1 -> enable outbox1 notification 1208 */ 1209 uint32_t enable; 1210 }; 1211 1212 /* DP AUX Reply command - OutBox Cmd */ 1213 /** 1214 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1215 */ 1216 struct aux_reply_data { 1217 /** 1218 * Aux cmd 1219 */ 1220 uint8_t command; 1221 /** 1222 * Aux reply data length (max: 16 bytes) 1223 */ 1224 uint8_t length; 1225 /** 1226 * Alignment only 1227 */ 1228 uint8_t pad[2]; 1229 /** 1230 * Aux reply data 1231 */ 1232 uint8_t data[16]; 1233 }; 1234 1235 /** 1236 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1237 */ 1238 struct aux_reply_control_data { 1239 /** 1240 * Reserved for future use 1241 */ 1242 uint32_t handle; 1243 /** 1244 * Aux Instance 1245 */ 1246 uint8_t instance; 1247 /** 1248 * Aux transaction result: definition in enum aux_return_code_type 1249 */ 1250 uint8_t result; 1251 /** 1252 * Alignment only 1253 */ 1254 uint16_t pad; 1255 }; 1256 1257 /** 1258 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1259 */ 1260 struct dmub_rb_cmd_dp_aux_reply { 1261 /** 1262 * Command header. 1263 */ 1264 struct dmub_cmd_header header; 1265 /** 1266 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1267 */ 1268 struct aux_reply_control_data control; 1269 /** 1270 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1271 */ 1272 struct aux_reply_data reply_data; 1273 }; 1274 1275 /* DP HPD Notify command - OutBox Cmd */ 1276 /** 1277 * DP HPD Type 1278 */ 1279 enum dp_hpd_type { 1280 /** 1281 * Normal DP HPD 1282 */ 1283 DP_HPD = 0, 1284 /** 1285 * DP HPD short pulse 1286 */ 1287 DP_IRQ 1288 }; 1289 1290 /** 1291 * DP HPD Status 1292 */ 1293 enum dp_hpd_status { 1294 /** 1295 * DP_HPD status low 1296 */ 1297 DP_HPD_UNPLUG = 0, 1298 /** 1299 * DP_HPD status high 1300 */ 1301 DP_HPD_PLUG 1302 }; 1303 1304 /** 1305 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1306 */ 1307 struct dp_hpd_data { 1308 /** 1309 * DP HPD instance 1310 */ 1311 uint8_t instance; 1312 /** 1313 * HPD type 1314 */ 1315 uint8_t hpd_type; 1316 /** 1317 * HPD status: only for type: DP_HPD to indicate status 1318 */ 1319 uint8_t hpd_status; 1320 /** 1321 * Alignment only 1322 */ 1323 uint8_t pad; 1324 }; 1325 1326 /** 1327 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1328 */ 1329 struct dmub_rb_cmd_dp_hpd_notify { 1330 /** 1331 * Command header. 1332 */ 1333 struct dmub_cmd_header header; 1334 /** 1335 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1336 */ 1337 struct dp_hpd_data hpd_data; 1338 }; 1339 1340 /** 1341 * Definition of a SET_CONFIG reply from DPOA. 1342 */ 1343 enum set_config_status { 1344 SET_CONFIG_PENDING = 0, 1345 SET_CONFIG_ACK_RECEIVED, 1346 SET_CONFIG_RX_TIMEOUT, 1347 SET_CONFIG_UNKNOWN_ERROR, 1348 }; 1349 1350 /** 1351 * Definition of a set_config reply 1352 */ 1353 struct set_config_reply_control_data { 1354 uint8_t instance; /* DPIA Instance */ 1355 uint8_t status; /* Set Config reply */ 1356 uint16_t pad; /* Alignment */ 1357 }; 1358 1359 /** 1360 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1361 */ 1362 struct dmub_rb_cmd_dp_set_config_reply { 1363 struct dmub_cmd_header header; 1364 struct set_config_reply_control_data set_config_reply_control; 1365 }; 1366 1367 /* 1368 * Command IDs should be treated as stable ABI. 1369 * Do not reuse or modify IDs. 1370 */ 1371 1372 /** 1373 * PSR command sub-types. 1374 */ 1375 enum dmub_cmd_psr_type { 1376 /** 1377 * Set PSR version support. 1378 */ 1379 DMUB_CMD__PSR_SET_VERSION = 0, 1380 /** 1381 * Copy driver-calculated parameters to PSR state. 1382 */ 1383 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1384 /** 1385 * Enable PSR. 1386 */ 1387 DMUB_CMD__PSR_ENABLE = 2, 1388 1389 /** 1390 * Disable PSR. 1391 */ 1392 DMUB_CMD__PSR_DISABLE = 3, 1393 1394 /** 1395 * Set PSR level. 1396 * PSR level is a 16-bit value dicated by driver that 1397 * will enable/disable different functionality. 1398 */ 1399 DMUB_CMD__PSR_SET_LEVEL = 4, 1400 1401 /** 1402 * Forces PSR enabled until an explicit PSR disable call. 1403 */ 1404 DMUB_CMD__PSR_FORCE_STATIC = 5, 1405 /** 1406 * Set PSR power option 1407 */ 1408 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1409 }; 1410 1411 /** 1412 * PSR versions. 1413 */ 1414 enum psr_version { 1415 /** 1416 * PSR version 1. 1417 */ 1418 PSR_VERSION_1 = 0, 1419 /** 1420 * PSR not supported. 1421 */ 1422 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1423 }; 1424 1425 /** 1426 * enum dmub_cmd_mall_type - MALL commands 1427 */ 1428 enum dmub_cmd_mall_type { 1429 /** 1430 * Allows display refresh from MALL. 1431 */ 1432 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1433 /** 1434 * Disallows display refresh from MALL. 1435 */ 1436 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1437 /** 1438 * Cursor copy for MALL. 1439 */ 1440 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1441 /** 1442 * Controls DF requests. 1443 */ 1444 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1445 }; 1446 1447 1448 /** 1449 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1450 */ 1451 struct dmub_cmd_psr_copy_settings_data { 1452 /** 1453 * Flags that can be set by driver to change some PSR behaviour. 1454 */ 1455 union dmub_psr_debug_flags debug; 1456 /** 1457 * 16-bit value dicated by driver that will enable/disable different functionality. 1458 */ 1459 uint16_t psr_level; 1460 /** 1461 * DPP HW instance. 1462 */ 1463 uint8_t dpp_inst; 1464 /** 1465 * MPCC HW instance. 1466 * Not used in dmub fw, 1467 * dmub fw will get active opp by reading odm registers. 1468 */ 1469 uint8_t mpcc_inst; 1470 /** 1471 * OPP HW instance. 1472 * Not used in dmub fw, 1473 * dmub fw will get active opp by reading odm registers. 1474 */ 1475 uint8_t opp_inst; 1476 /** 1477 * OTG HW instance. 1478 */ 1479 uint8_t otg_inst; 1480 /** 1481 * DIG FE HW instance. 1482 */ 1483 uint8_t digfe_inst; 1484 /** 1485 * DIG BE HW instance. 1486 */ 1487 uint8_t digbe_inst; 1488 /** 1489 * DP PHY HW instance. 1490 */ 1491 uint8_t dpphy_inst; 1492 /** 1493 * AUX HW instance. 1494 */ 1495 uint8_t aux_inst; 1496 /** 1497 * Determines if SMU optimzations are enabled/disabled. 1498 */ 1499 uint8_t smu_optimizations_en; 1500 /** 1501 * Unused. 1502 * TODO: Remove. 1503 */ 1504 uint8_t frame_delay; 1505 /** 1506 * If RFB setup time is greater than the total VBLANK time, 1507 * it is not possible for the sink to capture the video frame 1508 * in the same frame the SDP is sent. In this case, 1509 * the frame capture indication bit should be set and an extra 1510 * static frame should be transmitted to the sink. 1511 */ 1512 uint8_t frame_cap_ind; 1513 /** 1514 * Explicit padding to 4 byte boundary. 1515 */ 1516 uint8_t pad[2]; 1517 /** 1518 * Multi-display optimizations are implemented on certain ASICs. 1519 */ 1520 uint8_t multi_disp_optimizations_en; 1521 /** 1522 * The last possible line SDP may be transmitted without violating 1523 * the RFB setup time or entering the active video frame. 1524 */ 1525 uint16_t init_sdp_deadline; 1526 /** 1527 * Explicit padding to 4 byte boundary. 1528 */ 1529 uint16_t pad2; 1530 /** 1531 * Length of each horizontal line in us. 1532 */ 1533 uint32_t line_time_in_us; 1534 /** 1535 * FEC enable status in driver 1536 */ 1537 uint8_t fec_enable_status; 1538 /** 1539 * FEC re-enable delay when PSR exit. 1540 * unit is 100us, range form 0~255(0xFF). 1541 */ 1542 uint8_t fec_enable_delay_in100us; 1543 /** 1544 * PSR control version. 1545 */ 1546 uint8_t cmd_version; 1547 /** 1548 * Panel Instance. 1549 * Panel isntance to identify which psr_state to use 1550 * Currently the support is only for 0 or 1 1551 */ 1552 uint8_t panel_inst; 1553 /** 1554 * Explicit padding to 4 byte boundary. 1555 */ 1556 uint8_t pad3[4]; 1557 }; 1558 1559 /** 1560 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1561 */ 1562 struct dmub_rb_cmd_psr_copy_settings { 1563 /** 1564 * Command header. 1565 */ 1566 struct dmub_cmd_header header; 1567 /** 1568 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1569 */ 1570 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1571 }; 1572 1573 /** 1574 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1575 */ 1576 struct dmub_cmd_psr_set_level_data { 1577 /** 1578 * 16-bit value dicated by driver that will enable/disable different functionality. 1579 */ 1580 uint16_t psr_level; 1581 /** 1582 * PSR control version. 1583 */ 1584 uint8_t cmd_version; 1585 /** 1586 * Panel Instance. 1587 * Panel isntance to identify which psr_state to use 1588 * Currently the support is only for 0 or 1 1589 */ 1590 uint8_t panel_inst; 1591 }; 1592 1593 /** 1594 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1595 */ 1596 struct dmub_rb_cmd_psr_set_level { 1597 /** 1598 * Command header. 1599 */ 1600 struct dmub_cmd_header header; 1601 /** 1602 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1603 */ 1604 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1605 }; 1606 1607 struct dmub_rb_cmd_psr_enable_data { 1608 /** 1609 * PSR control version. 1610 */ 1611 uint8_t cmd_version; 1612 /** 1613 * Panel Instance. 1614 * Panel isntance to identify which psr_state to use 1615 * Currently the support is only for 0 or 1 1616 */ 1617 uint8_t panel_inst; 1618 /** 1619 * Explicit padding to 4 byte boundary. 1620 */ 1621 uint8_t pad[2]; 1622 }; 1623 1624 /** 1625 * Definition of a DMUB_CMD__PSR_ENABLE command. 1626 * PSR enable/disable is controlled using the sub_type. 1627 */ 1628 struct dmub_rb_cmd_psr_enable { 1629 /** 1630 * Command header. 1631 */ 1632 struct dmub_cmd_header header; 1633 1634 struct dmub_rb_cmd_psr_enable_data data; 1635 }; 1636 1637 /** 1638 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1639 */ 1640 struct dmub_cmd_psr_set_version_data { 1641 /** 1642 * PSR version that FW should implement. 1643 */ 1644 enum psr_version version; 1645 /** 1646 * PSR control version. 1647 */ 1648 uint8_t cmd_version; 1649 /** 1650 * Panel Instance. 1651 * Panel isntance to identify which psr_state to use 1652 * Currently the support is only for 0 or 1 1653 */ 1654 uint8_t panel_inst; 1655 /** 1656 * Explicit padding to 4 byte boundary. 1657 */ 1658 uint8_t pad[2]; 1659 }; 1660 1661 /** 1662 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1663 */ 1664 struct dmub_rb_cmd_psr_set_version { 1665 /** 1666 * Command header. 1667 */ 1668 struct dmub_cmd_header header; 1669 /** 1670 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1671 */ 1672 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1673 }; 1674 1675 struct dmub_cmd_psr_force_static_data { 1676 /** 1677 * PSR control version. 1678 */ 1679 uint8_t cmd_version; 1680 /** 1681 * Panel Instance. 1682 * Panel isntance to identify which psr_state to use 1683 * Currently the support is only for 0 or 1 1684 */ 1685 uint8_t panel_inst; 1686 /** 1687 * Explicit padding to 4 byte boundary. 1688 */ 1689 uint8_t pad[2]; 1690 }; 1691 1692 /** 1693 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1694 */ 1695 struct dmub_rb_cmd_psr_force_static { 1696 /** 1697 * Command header. 1698 */ 1699 struct dmub_cmd_header header; 1700 /** 1701 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1702 */ 1703 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1704 }; 1705 1706 /** 1707 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 1708 */ 1709 struct dmub_cmd_psr_set_power_opt_data { 1710 /** 1711 * PSR control version. 1712 */ 1713 uint8_t cmd_version; 1714 /** 1715 * Panel Instance. 1716 * Panel isntance to identify which psr_state to use 1717 * Currently the support is only for 0 or 1 1718 */ 1719 uint8_t panel_inst; 1720 /** 1721 * Explicit padding to 4 byte boundary. 1722 */ 1723 uint8_t pad[2]; 1724 /** 1725 * PSR power option 1726 */ 1727 uint32_t power_opt; 1728 }; 1729 1730 /** 1731 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1732 */ 1733 struct dmub_rb_cmd_psr_set_power_opt { 1734 /** 1735 * Command header. 1736 */ 1737 struct dmub_cmd_header header; 1738 /** 1739 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1740 */ 1741 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 1742 }; 1743 1744 /** 1745 * Set of HW components that can be locked. 1746 * 1747 * Note: If updating with more HW components, fields 1748 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1749 */ 1750 union dmub_hw_lock_flags { 1751 /** 1752 * Set of HW components that can be locked. 1753 */ 1754 struct { 1755 /** 1756 * Lock/unlock OTG master update lock. 1757 */ 1758 uint8_t lock_pipe : 1; 1759 /** 1760 * Lock/unlock cursor. 1761 */ 1762 uint8_t lock_cursor : 1; 1763 /** 1764 * Lock/unlock global update lock. 1765 */ 1766 uint8_t lock_dig : 1; 1767 /** 1768 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1769 */ 1770 uint8_t triple_buffer_lock : 1; 1771 } bits; 1772 1773 /** 1774 * Union for HW Lock flags. 1775 */ 1776 uint8_t u8All; 1777 }; 1778 1779 /** 1780 * Instances of HW to be locked. 1781 * 1782 * Note: If updating with more HW components, fields 1783 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1784 */ 1785 struct dmub_hw_lock_inst_flags { 1786 /** 1787 * OTG HW instance for OTG master update lock. 1788 */ 1789 uint8_t otg_inst; 1790 /** 1791 * OPP instance for cursor lock. 1792 */ 1793 uint8_t opp_inst; 1794 /** 1795 * OTG HW instance for global update lock. 1796 * TODO: Remove, and re-use otg_inst. 1797 */ 1798 uint8_t dig_inst; 1799 /** 1800 * Explicit pad to 4 byte boundary. 1801 */ 1802 uint8_t pad; 1803 }; 1804 1805 /** 1806 * Clients that can acquire the HW Lock Manager. 1807 * 1808 * Note: If updating with more clients, fields in 1809 * dmub_inbox0_cmd_lock_hw must be updated to match. 1810 */ 1811 enum hw_lock_client { 1812 /** 1813 * Driver is the client of HW Lock Manager. 1814 */ 1815 HW_LOCK_CLIENT_DRIVER = 0, 1816 /** 1817 * Invalid client. 1818 */ 1819 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1820 }; 1821 1822 /** 1823 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1824 */ 1825 struct dmub_cmd_lock_hw_data { 1826 /** 1827 * Specifies the client accessing HW Lock Manager. 1828 */ 1829 enum hw_lock_client client; 1830 /** 1831 * HW instances to be locked. 1832 */ 1833 struct dmub_hw_lock_inst_flags inst_flags; 1834 /** 1835 * Which components to be locked. 1836 */ 1837 union dmub_hw_lock_flags hw_locks; 1838 /** 1839 * Specifies lock/unlock. 1840 */ 1841 uint8_t lock; 1842 /** 1843 * HW can be unlocked separately from releasing the HW Lock Mgr. 1844 * This flag is set if the client wishes to release the object. 1845 */ 1846 uint8_t should_release; 1847 /** 1848 * Explicit padding to 4 byte boundary. 1849 */ 1850 uint8_t pad; 1851 }; 1852 1853 /** 1854 * Definition of a DMUB_CMD__HW_LOCK command. 1855 * Command is used by driver and FW. 1856 */ 1857 struct dmub_rb_cmd_lock_hw { 1858 /** 1859 * Command header. 1860 */ 1861 struct dmub_cmd_header header; 1862 /** 1863 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1864 */ 1865 struct dmub_cmd_lock_hw_data lock_hw_data; 1866 }; 1867 1868 /** 1869 * ABM command sub-types. 1870 */ 1871 enum dmub_cmd_abm_type { 1872 /** 1873 * Initialize parameters for ABM algorithm. 1874 * Data is passed through an indirect buffer. 1875 */ 1876 DMUB_CMD__ABM_INIT_CONFIG = 0, 1877 /** 1878 * Set OTG and panel HW instance. 1879 */ 1880 DMUB_CMD__ABM_SET_PIPE = 1, 1881 /** 1882 * Set user requested backklight level. 1883 */ 1884 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1885 /** 1886 * Set ABM operating/aggression level. 1887 */ 1888 DMUB_CMD__ABM_SET_LEVEL = 3, 1889 /** 1890 * Set ambient light level. 1891 */ 1892 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1893 /** 1894 * Enable/disable fractional duty cycle for backlight PWM. 1895 */ 1896 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1897 1898 /** 1899 * unregister vertical interrupt after steady state is reached 1900 */ 1901 DMUB_CMD__ABM_PAUSE = 6, 1902 }; 1903 1904 /** 1905 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1906 * Requirements: 1907 * - Padded explicitly to 32-bit boundary. 1908 * - Must ensure this structure matches the one on driver-side, 1909 * otherwise it won't be aligned. 1910 */ 1911 struct abm_config_table { 1912 /** 1913 * Gamma curve thresholds, used for crgb conversion. 1914 */ 1915 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1916 /** 1917 * Gamma curve offsets, used for crgb conversion. 1918 */ 1919 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1920 /** 1921 * Gamma curve slopes, used for crgb conversion. 1922 */ 1923 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1924 /** 1925 * Custom backlight curve thresholds. 1926 */ 1927 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 1928 /** 1929 * Custom backlight curve offsets. 1930 */ 1931 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 1932 /** 1933 * Ambient light thresholds. 1934 */ 1935 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 1936 /** 1937 * Minimum programmable backlight. 1938 */ 1939 uint16_t min_abm_backlight; // 122B 1940 /** 1941 * Minimum reduction values. 1942 */ 1943 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 1944 /** 1945 * Maximum reduction values. 1946 */ 1947 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 1948 /** 1949 * Bright positive gain. 1950 */ 1951 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 1952 /** 1953 * Dark negative gain. 1954 */ 1955 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 1956 /** 1957 * Hybrid factor. 1958 */ 1959 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 1960 /** 1961 * Contrast factor. 1962 */ 1963 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 1964 /** 1965 * Deviation gain. 1966 */ 1967 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 1968 /** 1969 * Minimum knee. 1970 */ 1971 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 1972 /** 1973 * Maximum knee. 1974 */ 1975 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 1976 /** 1977 * Unused. 1978 */ 1979 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 1980 /** 1981 * Explicit padding to 4 byte boundary. 1982 */ 1983 uint8_t pad3[3]; // 229B 1984 /** 1985 * Backlight ramp reduction. 1986 */ 1987 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 1988 /** 1989 * Backlight ramp start. 1990 */ 1991 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 1992 }; 1993 1994 /** 1995 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1996 */ 1997 struct dmub_cmd_abm_set_pipe_data { 1998 /** 1999 * OTG HW instance. 2000 */ 2001 uint8_t otg_inst; 2002 2003 /** 2004 * Panel Control HW instance. 2005 */ 2006 uint8_t panel_inst; 2007 2008 /** 2009 * Controls how ABM will interpret a set pipe or set level command. 2010 */ 2011 uint8_t set_pipe_option; 2012 2013 /** 2014 * Unused. 2015 * TODO: Remove. 2016 */ 2017 uint8_t ramping_boundary; 2018 }; 2019 2020 /** 2021 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2022 */ 2023 struct dmub_rb_cmd_abm_set_pipe { 2024 /** 2025 * Command header. 2026 */ 2027 struct dmub_cmd_header header; 2028 2029 /** 2030 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2031 */ 2032 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2033 }; 2034 2035 /** 2036 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2037 */ 2038 struct dmub_cmd_abm_set_backlight_data { 2039 /** 2040 * Number of frames to ramp to backlight user level. 2041 */ 2042 uint32_t frame_ramp; 2043 2044 /** 2045 * Requested backlight level from user. 2046 */ 2047 uint32_t backlight_user_level; 2048 2049 /** 2050 * ABM control version. 2051 */ 2052 uint8_t version; 2053 2054 /** 2055 * Panel Control HW instance mask. 2056 * Bit 0 is Panel Control HW instance 0. 2057 * Bit 1 is Panel Control HW instance 1. 2058 */ 2059 uint8_t panel_mask; 2060 2061 /** 2062 * Explicit padding to 4 byte boundary. 2063 */ 2064 uint8_t pad[2]; 2065 }; 2066 2067 /** 2068 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2069 */ 2070 struct dmub_rb_cmd_abm_set_backlight { 2071 /** 2072 * Command header. 2073 */ 2074 struct dmub_cmd_header header; 2075 2076 /** 2077 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2078 */ 2079 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2080 }; 2081 2082 /** 2083 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2084 */ 2085 struct dmub_cmd_abm_set_level_data { 2086 /** 2087 * Set current ABM operating/aggression level. 2088 */ 2089 uint32_t level; 2090 2091 /** 2092 * ABM control version. 2093 */ 2094 uint8_t version; 2095 2096 /** 2097 * Panel Control HW instance mask. 2098 * Bit 0 is Panel Control HW instance 0. 2099 * Bit 1 is Panel Control HW instance 1. 2100 */ 2101 uint8_t panel_mask; 2102 2103 /** 2104 * Explicit padding to 4 byte boundary. 2105 */ 2106 uint8_t pad[2]; 2107 }; 2108 2109 /** 2110 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2111 */ 2112 struct dmub_rb_cmd_abm_set_level { 2113 /** 2114 * Command header. 2115 */ 2116 struct dmub_cmd_header header; 2117 2118 /** 2119 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2120 */ 2121 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2122 }; 2123 2124 /** 2125 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2126 */ 2127 struct dmub_cmd_abm_set_ambient_level_data { 2128 /** 2129 * Ambient light sensor reading from OS. 2130 */ 2131 uint32_t ambient_lux; 2132 2133 /** 2134 * ABM control version. 2135 */ 2136 uint8_t version; 2137 2138 /** 2139 * Panel Control HW instance mask. 2140 * Bit 0 is Panel Control HW instance 0. 2141 * Bit 1 is Panel Control HW instance 1. 2142 */ 2143 uint8_t panel_mask; 2144 2145 /** 2146 * Explicit padding to 4 byte boundary. 2147 */ 2148 uint8_t pad[2]; 2149 }; 2150 2151 /** 2152 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2153 */ 2154 struct dmub_rb_cmd_abm_set_ambient_level { 2155 /** 2156 * Command header. 2157 */ 2158 struct dmub_cmd_header header; 2159 2160 /** 2161 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2162 */ 2163 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2164 }; 2165 2166 /** 2167 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2168 */ 2169 struct dmub_cmd_abm_set_pwm_frac_data { 2170 /** 2171 * Enable/disable fractional duty cycle for backlight PWM. 2172 * TODO: Convert to uint8_t. 2173 */ 2174 uint32_t fractional_pwm; 2175 2176 /** 2177 * ABM control version. 2178 */ 2179 uint8_t version; 2180 2181 /** 2182 * Panel Control HW instance mask. 2183 * Bit 0 is Panel Control HW instance 0. 2184 * Bit 1 is Panel Control HW instance 1. 2185 */ 2186 uint8_t panel_mask; 2187 2188 /** 2189 * Explicit padding to 4 byte boundary. 2190 */ 2191 uint8_t pad[2]; 2192 }; 2193 2194 /** 2195 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2196 */ 2197 struct dmub_rb_cmd_abm_set_pwm_frac { 2198 /** 2199 * Command header. 2200 */ 2201 struct dmub_cmd_header header; 2202 2203 /** 2204 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2205 */ 2206 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2207 }; 2208 2209 /** 2210 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2211 */ 2212 struct dmub_cmd_abm_init_config_data { 2213 /** 2214 * Location of indirect buffer used to pass init data to ABM. 2215 */ 2216 union dmub_addr src; 2217 2218 /** 2219 * Indirect buffer length. 2220 */ 2221 uint16_t bytes; 2222 2223 2224 /** 2225 * ABM control version. 2226 */ 2227 uint8_t version; 2228 2229 /** 2230 * Panel Control HW instance mask. 2231 * Bit 0 is Panel Control HW instance 0. 2232 * Bit 1 is Panel Control HW instance 1. 2233 */ 2234 uint8_t panel_mask; 2235 2236 /** 2237 * Explicit padding to 4 byte boundary. 2238 */ 2239 uint8_t pad[2]; 2240 }; 2241 2242 /** 2243 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2244 */ 2245 struct dmub_rb_cmd_abm_init_config { 2246 /** 2247 * Command header. 2248 */ 2249 struct dmub_cmd_header header; 2250 2251 /** 2252 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2253 */ 2254 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2255 }; 2256 2257 /** 2258 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2259 */ 2260 2261 struct dmub_cmd_abm_pause_data { 2262 2263 /** 2264 * Panel Control HW instance mask. 2265 * Bit 0 is Panel Control HW instance 0. 2266 * Bit 1 is Panel Control HW instance 1. 2267 */ 2268 uint8_t panel_mask; 2269 2270 /** 2271 * OTG hw instance 2272 */ 2273 uint8_t otg_inst; 2274 2275 /** 2276 * Enable or disable ABM pause 2277 */ 2278 uint8_t enable; 2279 2280 /** 2281 * Explicit padding to 4 byte boundary. 2282 */ 2283 uint8_t pad[1]; 2284 }; 2285 2286 /** 2287 * Definition of a DMUB_CMD__ABM_PAUSE command. 2288 */ 2289 struct dmub_rb_cmd_abm_pause { 2290 /** 2291 * Command header. 2292 */ 2293 struct dmub_cmd_header header; 2294 2295 /** 2296 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2297 */ 2298 struct dmub_cmd_abm_pause_data abm_pause_data; 2299 }; 2300 2301 /** 2302 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2303 */ 2304 struct dmub_cmd_query_feature_caps_data { 2305 /** 2306 * DMUB feature capabilities. 2307 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2308 */ 2309 struct dmub_feature_caps feature_caps; 2310 }; 2311 2312 /** 2313 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2314 */ 2315 struct dmub_rb_cmd_query_feature_caps { 2316 /** 2317 * Command header. 2318 */ 2319 struct dmub_cmd_header header; 2320 /** 2321 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2322 */ 2323 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2324 }; 2325 2326 struct dmub_optc_state { 2327 uint32_t v_total_max; 2328 uint32_t v_total_min; 2329 uint32_t v_total_mid; 2330 uint32_t v_total_mid_frame_num; 2331 uint32_t tg_inst; 2332 uint32_t enable_manual_trigger; 2333 uint32_t clear_force_vsync; 2334 }; 2335 2336 struct dmub_rb_cmd_drr_update { 2337 struct dmub_cmd_header header; 2338 struct dmub_optc_state dmub_optc_state_req; 2339 }; 2340 2341 /** 2342 * enum dmub_cmd_panel_cntl_type - Panel control command. 2343 */ 2344 enum dmub_cmd_panel_cntl_type { 2345 /** 2346 * Initializes embedded panel hardware blocks. 2347 */ 2348 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2349 /** 2350 * Queries backlight info for the embedded panel. 2351 */ 2352 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2353 }; 2354 2355 /** 2356 * struct dmub_cmd_panel_cntl_data - Panel control data. 2357 */ 2358 struct dmub_cmd_panel_cntl_data { 2359 uint32_t inst; /**< panel instance */ 2360 uint32_t current_backlight; /* in/out */ 2361 uint32_t bl_pwm_cntl; /* in/out */ 2362 uint32_t bl_pwm_period_cntl; /* in/out */ 2363 uint32_t bl_pwm_ref_div1; /* in/out */ 2364 uint8_t is_backlight_on : 1; /* in/out */ 2365 uint8_t is_powered_on : 1; /* in/out */ 2366 }; 2367 2368 /** 2369 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2370 */ 2371 struct dmub_rb_cmd_panel_cntl { 2372 struct dmub_cmd_header header; /**< header */ 2373 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2374 }; 2375 2376 /** 2377 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2378 */ 2379 struct dmub_cmd_lvtma_control_data { 2380 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2381 uint8_t reserved_0[3]; /**< For future use */ 2382 uint8_t panel_inst; /**< LVTMA control instance */ 2383 uint8_t reserved_1[3]; /**< For future use */ 2384 }; 2385 2386 /** 2387 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2388 */ 2389 struct dmub_rb_cmd_lvtma_control { 2390 /** 2391 * Command header. 2392 */ 2393 struct dmub_cmd_header header; 2394 /** 2395 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2396 */ 2397 struct dmub_cmd_lvtma_control_data data; 2398 }; 2399 2400 /** 2401 * Maximum number of bytes a chunk sent to DMUB for parsing 2402 */ 2403 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2404 2405 /** 2406 * Represent a chunk of CEA blocks sent to DMUB for parsing 2407 */ 2408 struct dmub_cmd_send_edid_cea { 2409 uint16_t offset; /**< offset into the CEA block */ 2410 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2411 uint16_t total_length; /**< total length of the CEA block */ 2412 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2413 uint8_t pad[3]; /**< padding and for future expansion */ 2414 }; 2415 2416 /** 2417 * Result of VSDB parsing from CEA block 2418 */ 2419 struct dmub_cmd_edid_cea_amd_vsdb { 2420 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2421 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2422 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2423 uint16_t min_frame_rate; /**< Maximum frame rate */ 2424 uint16_t max_frame_rate; /**< Minimum frame rate */ 2425 }; 2426 2427 /** 2428 * Result of sending a CEA chunk 2429 */ 2430 struct dmub_cmd_edid_cea_ack { 2431 uint16_t offset; /**< offset of the chunk into the CEA block */ 2432 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2433 uint8_t pad; /**< padding and for future expansion */ 2434 }; 2435 2436 /** 2437 * Specify whether the result is an ACK/NACK or the parsing has finished 2438 */ 2439 enum dmub_cmd_edid_cea_reply_type { 2440 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2441 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2442 }; 2443 2444 /** 2445 * Definition of a DMUB_CMD__EDID_CEA command. 2446 */ 2447 struct dmub_rb_cmd_edid_cea { 2448 struct dmub_cmd_header header; /**< Command header */ 2449 union dmub_cmd_edid_cea_data { 2450 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2451 struct dmub_cmd_edid_cea_output { /**< output with results */ 2452 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2453 union { 2454 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2455 struct dmub_cmd_edid_cea_ack ack; 2456 }; 2457 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2458 } data; /**< Command data */ 2459 2460 }; 2461 2462 /** 2463 * union dmub_rb_cmd - DMUB inbox command. 2464 */ 2465 union dmub_rb_cmd { 2466 struct dmub_rb_cmd_lock_hw lock_hw; 2467 /** 2468 * Elements shared with all commands. 2469 */ 2470 struct dmub_rb_cmd_common cmd_common; 2471 /** 2472 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2473 */ 2474 struct dmub_rb_cmd_read_modify_write read_modify_write; 2475 /** 2476 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2477 */ 2478 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2479 /** 2480 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2481 */ 2482 struct dmub_rb_cmd_burst_write burst_write; 2483 /** 2484 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2485 */ 2486 struct dmub_rb_cmd_reg_wait reg_wait; 2487 /** 2488 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2489 */ 2490 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2491 /** 2492 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2493 */ 2494 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2495 /** 2496 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2497 */ 2498 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2499 /** 2500 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2501 */ 2502 struct dmub_rb_cmd_dpphy_init dpphy_init; 2503 /** 2504 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2505 */ 2506 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2507 /** 2508 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2509 */ 2510 struct dmub_rb_cmd_psr_set_version psr_set_version; 2511 /** 2512 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2513 */ 2514 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2515 /** 2516 * Definition of a DMUB_CMD__PSR_ENABLE command. 2517 */ 2518 struct dmub_rb_cmd_psr_enable psr_enable; 2519 /** 2520 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2521 */ 2522 struct dmub_rb_cmd_psr_set_level psr_set_level; 2523 /** 2524 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2525 */ 2526 struct dmub_rb_cmd_psr_force_static psr_force_static; 2527 /** 2528 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2529 */ 2530 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 2531 /** 2532 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2533 */ 2534 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2535 /** 2536 * Definition of a DMUB_CMD__MALL command. 2537 */ 2538 struct dmub_rb_cmd_mall mall; 2539 /** 2540 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2541 */ 2542 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2543 2544 /** 2545 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2546 */ 2547 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2548 2549 /** 2550 * Definition of DMUB_CMD__PANEL_CNTL commands. 2551 */ 2552 struct dmub_rb_cmd_panel_cntl panel_cntl; 2553 /** 2554 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2555 */ 2556 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2557 2558 /** 2559 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2560 */ 2561 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2562 2563 /** 2564 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2565 */ 2566 struct dmub_rb_cmd_abm_set_level abm_set_level; 2567 2568 /** 2569 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2570 */ 2571 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2572 2573 /** 2574 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2575 */ 2576 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2577 2578 /** 2579 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2580 */ 2581 struct dmub_rb_cmd_abm_init_config abm_init_config; 2582 2583 /** 2584 * Definition of a DMUB_CMD__ABM_PAUSE command. 2585 */ 2586 struct dmub_rb_cmd_abm_pause abm_pause; 2587 2588 /** 2589 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2590 */ 2591 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2592 2593 /** 2594 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2595 */ 2596 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2597 2598 /** 2599 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2600 */ 2601 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2602 struct dmub_rb_cmd_drr_update drr_update; 2603 /** 2604 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2605 */ 2606 struct dmub_rb_cmd_lvtma_control lvtma_control; 2607 /** 2608 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 2609 */ 2610 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 2611 /** 2612 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 2613 */ 2614 struct dmub_rb_cmd_set_config_access set_config_access; 2615 /** 2616 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2617 */ 2618 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 2619 /** 2620 * Definition of a DMUB_CMD__EDID_CEA command. 2621 */ 2622 struct dmub_rb_cmd_edid_cea edid_cea; 2623 }; 2624 2625 /** 2626 * union dmub_rb_out_cmd - Outbox command 2627 */ 2628 union dmub_rb_out_cmd { 2629 /** 2630 * Parameters common to every command. 2631 */ 2632 struct dmub_rb_cmd_common cmd_common; 2633 /** 2634 * AUX reply command. 2635 */ 2636 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2637 /** 2638 * HPD notify command. 2639 */ 2640 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2641 /** 2642 * SET_CONFIG reply command. 2643 */ 2644 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 2645 }; 2646 #pragma pack(pop) 2647 2648 2649 //============================================================================== 2650 //</DMUB_CMD>=================================================================== 2651 //============================================================================== 2652 //< DMUB_RB>==================================================================== 2653 //============================================================================== 2654 2655 #if defined(__cplusplus) 2656 extern "C" { 2657 #endif 2658 2659 /** 2660 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2661 */ 2662 struct dmub_rb_init_params { 2663 void *ctx; /**< Caller provided context pointer */ 2664 void *base_address; /**< CPU base address for ring's data */ 2665 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2666 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2667 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2668 }; 2669 2670 /** 2671 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2672 */ 2673 struct dmub_rb { 2674 void *base_address; /**< CPU address for the ring's data */ 2675 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2676 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2677 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2678 2679 void *ctx; /**< Caller provided context pointer */ 2680 void *dmub; /**< Pointer to the DMUB interface */ 2681 }; 2682 2683 /** 2684 * @brief Checks if the ringbuffer is empty. 2685 * 2686 * @param rb DMUB Ringbuffer 2687 * @return true if empty 2688 * @return false otherwise 2689 */ 2690 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2691 { 2692 return (rb->wrpt == rb->rptr); 2693 } 2694 2695 /** 2696 * @brief Checks if the ringbuffer is full 2697 * 2698 * @param rb DMUB Ringbuffer 2699 * @return true if full 2700 * @return false otherwise 2701 */ 2702 static inline bool dmub_rb_full(struct dmub_rb *rb) 2703 { 2704 uint32_t data_count; 2705 2706 if (rb->wrpt >= rb->rptr) 2707 data_count = rb->wrpt - rb->rptr; 2708 else 2709 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2710 2711 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2712 } 2713 2714 /** 2715 * @brief Pushes a command into the ringbuffer 2716 * 2717 * @param rb DMUB ringbuffer 2718 * @param cmd The command to push 2719 * @return true if the ringbuffer was not full 2720 * @return false otherwise 2721 */ 2722 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2723 const union dmub_rb_cmd *cmd) 2724 { 2725 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 2726 const uint64_t *src = (const uint64_t *)cmd; 2727 uint8_t i; 2728 2729 if (dmub_rb_full(rb)) 2730 return false; 2731 2732 // copying data 2733 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2734 *dst++ = *src++; 2735 2736 rb->wrpt += DMUB_RB_CMD_SIZE; 2737 2738 if (rb->wrpt >= rb->capacity) 2739 rb->wrpt %= rb->capacity; 2740 2741 return true; 2742 } 2743 2744 /** 2745 * @brief Pushes a command into the DMUB outbox ringbuffer 2746 * 2747 * @param rb DMUB outbox ringbuffer 2748 * @param cmd Outbox command 2749 * @return true if not full 2750 * @return false otherwise 2751 */ 2752 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2753 const union dmub_rb_out_cmd *cmd) 2754 { 2755 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2756 const uint8_t *src = (const uint8_t *)cmd; 2757 2758 if (dmub_rb_full(rb)) 2759 return false; 2760 2761 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2762 2763 rb->wrpt += DMUB_RB_CMD_SIZE; 2764 2765 if (rb->wrpt >= rb->capacity) 2766 rb->wrpt %= rb->capacity; 2767 2768 return true; 2769 } 2770 2771 /** 2772 * @brief Returns the next unprocessed command in the ringbuffer. 2773 * 2774 * @param rb DMUB ringbuffer 2775 * @param cmd The command to return 2776 * @return true if not empty 2777 * @return false otherwise 2778 */ 2779 static inline bool dmub_rb_front(struct dmub_rb *rb, 2780 union dmub_rb_cmd **cmd) 2781 { 2782 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2783 2784 if (dmub_rb_empty(rb)) 2785 return false; 2786 2787 *cmd = (union dmub_rb_cmd *)rb_cmd; 2788 2789 return true; 2790 } 2791 2792 /** 2793 * @brief Determines the next ringbuffer offset. 2794 * 2795 * @param rb DMUB inbox ringbuffer 2796 * @param num_cmds Number of commands 2797 * @param next_rptr The next offset in the ringbuffer 2798 */ 2799 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2800 uint32_t num_cmds, 2801 uint32_t *next_rptr) 2802 { 2803 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2804 2805 if (*next_rptr >= rb->capacity) 2806 *next_rptr %= rb->capacity; 2807 } 2808 2809 /** 2810 * @brief Returns a pointer to a command in the inbox. 2811 * 2812 * @param rb DMUB inbox ringbuffer 2813 * @param cmd The inbox command to return 2814 * @param rptr The ringbuffer offset 2815 * @return true if not empty 2816 * @return false otherwise 2817 */ 2818 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 2819 union dmub_rb_cmd **cmd, 2820 uint32_t rptr) 2821 { 2822 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 2823 2824 if (dmub_rb_empty(rb)) 2825 return false; 2826 2827 *cmd = (union dmub_rb_cmd *)rb_cmd; 2828 2829 return true; 2830 } 2831 2832 /** 2833 * @brief Returns the next unprocessed command in the outbox. 2834 * 2835 * @param rb DMUB outbox ringbuffer 2836 * @param cmd The outbox command to return 2837 * @return true if not empty 2838 * @return false otherwise 2839 */ 2840 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2841 union dmub_rb_out_cmd *cmd) 2842 { 2843 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 2844 uint64_t *dst = (uint64_t *)cmd; 2845 uint8_t i; 2846 2847 if (dmub_rb_empty(rb)) 2848 return false; 2849 2850 // copying data 2851 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2852 *dst++ = *src++; 2853 2854 return true; 2855 } 2856 2857 /** 2858 * @brief Removes the front entry in the ringbuffer. 2859 * 2860 * @param rb DMUB ringbuffer 2861 * @return true if the command was removed 2862 * @return false if there were no commands 2863 */ 2864 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 2865 { 2866 if (dmub_rb_empty(rb)) 2867 return false; 2868 2869 rb->rptr += DMUB_RB_CMD_SIZE; 2870 2871 if (rb->rptr >= rb->capacity) 2872 rb->rptr %= rb->capacity; 2873 2874 return true; 2875 } 2876 2877 /** 2878 * @brief Flushes commands in the ringbuffer to framebuffer memory. 2879 * 2880 * Avoids a race condition where DMCUB accesses memory while 2881 * there are still writes in flight to framebuffer. 2882 * 2883 * @param rb DMUB ringbuffer 2884 */ 2885 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 2886 { 2887 uint32_t rptr = rb->rptr; 2888 uint32_t wptr = rb->wrpt; 2889 2890 while (rptr != wptr) { 2891 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 2892 //uint64_t volatile *p = (uint64_t volatile *)data; 2893 uint64_t temp; 2894 uint8_t i; 2895 2896 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2897 temp = *data++; 2898 2899 rptr += DMUB_RB_CMD_SIZE; 2900 if (rptr >= rb->capacity) 2901 rptr %= rb->capacity; 2902 } 2903 } 2904 2905 /** 2906 * @brief Initializes a DMCUB ringbuffer 2907 * 2908 * @param rb DMUB ringbuffer 2909 * @param init_params initial configuration for the ringbuffer 2910 */ 2911 static inline void dmub_rb_init(struct dmub_rb *rb, 2912 struct dmub_rb_init_params *init_params) 2913 { 2914 rb->base_address = init_params->base_address; 2915 rb->capacity = init_params->capacity; 2916 rb->rptr = init_params->read_ptr; 2917 rb->wrpt = init_params->write_ptr; 2918 } 2919 2920 /** 2921 * @brief Copies output data from in/out commands into the given command. 2922 * 2923 * @param rb DMUB ringbuffer 2924 * @param cmd Command to copy data into 2925 */ 2926 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 2927 union dmub_rb_cmd *cmd) 2928 { 2929 // Copy rb entry back into command 2930 uint8_t *rd_ptr = (rb->rptr == 0) ? 2931 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 2932 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 2933 2934 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 2935 } 2936 2937 #if defined(__cplusplus) 2938 } 2939 #endif 2940 2941 //============================================================================== 2942 //</DMUB_RB>==================================================================== 2943 //============================================================================== 2944 2945 #endif /* _DMUB_CMD_H_ */ 2946