1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of streams on any ASIC. */ 96 #define DMUB_MAX_STREAMS 6 97 98 /* Maximum number of planes on any ASIC. */ 99 #define DMUB_MAX_PLANES 6 100 101 /* Trace buffer offset for entry */ 102 #define TRACE_BUFFER_ENTRY_OFFSET 16 103 104 /** 105 * 106 * PSR control version legacy 107 */ 108 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 109 /** 110 * PSR control version with multi edp support 111 */ 112 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 113 114 115 /** 116 * ABM control version legacy 117 */ 118 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 119 120 /** 121 * ABM control version with multi edp support 122 */ 123 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 124 125 /** 126 * Physical framebuffer address location, 64-bit. 127 */ 128 #ifndef PHYSICAL_ADDRESS_LOC 129 #define PHYSICAL_ADDRESS_LOC union large_integer 130 #endif 131 132 /** 133 * OS/FW agnostic memcpy 134 */ 135 #ifndef dmub_memcpy 136 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 137 #endif 138 139 /** 140 * OS/FW agnostic memset 141 */ 142 #ifndef dmub_memset 143 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 144 #endif 145 146 #if defined(__cplusplus) 147 extern "C" { 148 #endif 149 150 /** 151 * OS/FW agnostic udelay 152 */ 153 #ifndef dmub_udelay 154 #define dmub_udelay(microseconds) udelay(microseconds) 155 #endif 156 157 /** 158 * union dmub_addr - DMUB physical/virtual 64-bit address. 159 */ 160 union dmub_addr { 161 struct { 162 uint32_t low_part; /**< Lower 32 bits */ 163 uint32_t high_part; /**< Upper 32 bits */ 164 } u; /*<< Low/high bit access */ 165 uint64_t quad_part; /*<< 64 bit address */ 166 }; 167 168 /** 169 * Flags that can be set by driver to change some PSR behaviour. 170 */ 171 union dmub_psr_debug_flags { 172 /** 173 * Debug flags. 174 */ 175 struct { 176 /** 177 * Enable visual confirm in FW. 178 */ 179 uint32_t visual_confirm : 1; 180 /** 181 * Use HW Lock Mgr object to do HW locking in FW. 182 */ 183 uint32_t use_hw_lock_mgr : 1; 184 185 /** 186 * Use TPS3 signal when restore main link. 187 */ 188 uint32_t force_wakeup_by_tps3 : 1; 189 } bitfields; 190 191 /** 192 * Union for debug flags. 193 */ 194 uint32_t u32All; 195 }; 196 197 /** 198 * DMUB feature capabilities. 199 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 200 */ 201 struct dmub_feature_caps { 202 /** 203 * Max PSR version supported by FW. 204 */ 205 uint8_t psr; 206 uint8_t reserved[7]; 207 }; 208 209 #if defined(__cplusplus) 210 } 211 #endif 212 213 //============================================================================== 214 //</DMUB_TYPES>================================================================= 215 //============================================================================== 216 //< DMUB_META>================================================================== 217 //============================================================================== 218 #pragma pack(push, 1) 219 220 /* Magic value for identifying dmub_fw_meta_info */ 221 #define DMUB_FW_META_MAGIC 0x444D5542 222 223 /* Offset from the end of the file to the dmub_fw_meta_info */ 224 #define DMUB_FW_META_OFFSET 0x24 225 226 /** 227 * struct dmub_fw_meta_info - metadata associated with fw binary 228 * 229 * NOTE: This should be considered a stable API. Fields should 230 * not be repurposed or reordered. New fields should be 231 * added instead to extend the structure. 232 * 233 * @magic_value: magic value identifying DMUB firmware meta info 234 * @fw_region_size: size of the firmware state region 235 * @trace_buffer_size: size of the tracebuffer region 236 * @fw_version: the firmware version information 237 * @dal_fw: 1 if the firmware is DAL 238 */ 239 struct dmub_fw_meta_info { 240 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 241 uint32_t fw_region_size; /**< size of the firmware state region */ 242 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 243 uint32_t fw_version; /**< the firmware version information */ 244 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 245 uint8_t reserved[3]; /**< padding bits */ 246 }; 247 248 /** 249 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 250 */ 251 union dmub_fw_meta { 252 struct dmub_fw_meta_info info; /**< metadata info */ 253 uint8_t reserved[64]; /**< padding bits */ 254 }; 255 256 #pragma pack(pop) 257 258 //============================================================================== 259 //< DMUB Trace Buffer>================================================================ 260 //============================================================================== 261 /** 262 * dmub_trace_code_t - firmware trace code, 32-bits 263 */ 264 typedef uint32_t dmub_trace_code_t; 265 266 /** 267 * struct dmcub_trace_buf_entry - Firmware trace entry 268 */ 269 struct dmcub_trace_buf_entry { 270 dmub_trace_code_t trace_code; /**< trace code for the event */ 271 uint32_t tick_count; /**< the tick count at time of trace */ 272 uint32_t param0; /**< trace defined parameter 0 */ 273 uint32_t param1; /**< trace defined parameter 1 */ 274 }; 275 276 //============================================================================== 277 //< DMUB_STATUS>================================================================ 278 //============================================================================== 279 280 /** 281 * DMCUB scratch registers can be used to determine firmware status. 282 * Current scratch register usage is as follows: 283 * 284 * SCRATCH0: FW Boot Status register 285 * SCRATCH5: LVTMA Status Register 286 * SCRATCH15: FW Boot Options register 287 */ 288 289 /** 290 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 291 */ 292 union dmub_fw_boot_status { 293 struct { 294 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 295 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 296 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 297 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 298 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 299 uint32_t reserved : 1; 300 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 301 302 } bits; /**< status bits */ 303 uint32_t all; /**< 32-bit access to status bits */ 304 }; 305 306 /** 307 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 308 */ 309 enum dmub_fw_boot_status_bit { 310 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 311 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 312 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 313 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 314 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 315 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 316 }; 317 318 /* Register bit definition for SCRATCH5 */ 319 union dmub_lvtma_status { 320 struct { 321 uint32_t psp_ok : 1; 322 uint32_t edp_on : 1; 323 uint32_t reserved : 30; 324 } bits; 325 uint32_t all; 326 }; 327 328 enum dmub_lvtma_status_bit { 329 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 330 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 331 }; 332 333 /** 334 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 335 */ 336 union dmub_fw_boot_options { 337 struct { 338 uint32_t pemu_env : 1; /**< 1 if PEMU */ 339 uint32_t fpga_env : 1; /**< 1 if FPGA */ 340 uint32_t optimized_init : 1; /**< 1 if optimized init */ 341 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 342 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 343 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 344 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 345 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 346 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 347 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 348 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 349 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 350 uint32_t power_optimization: 1; 351 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 352 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 353 354 uint32_t reserved : 18; /**< reserved */ 355 } bits; /**< boot bits */ 356 uint32_t all; /**< 32-bit access to bits */ 357 }; 358 359 enum dmub_fw_boot_options_bit { 360 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 361 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 362 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 363 }; 364 365 //============================================================================== 366 //</DMUB_STATUS>================================================================ 367 //============================================================================== 368 //< DMUB_VBIOS>================================================================= 369 //============================================================================== 370 371 /* 372 * enum dmub_cmd_vbios_type - VBIOS commands. 373 * 374 * Command IDs should be treated as stable ABI. 375 * Do not reuse or modify IDs. 376 */ 377 enum dmub_cmd_vbios_type { 378 /** 379 * Configures the DIG encoder. 380 */ 381 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 382 /** 383 * Controls the PHY. 384 */ 385 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 386 /** 387 * Sets the pixel clock/symbol clock. 388 */ 389 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 390 /** 391 * Enables or disables power gating. 392 */ 393 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 394 /** 395 * Controls embedded panels. 396 */ 397 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 398 /** 399 * Query DP alt status on a transmitter. 400 */ 401 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 402 }; 403 404 //============================================================================== 405 //</DMUB_VBIOS>================================================================= 406 //============================================================================== 407 //< DMUB_GPINT>================================================================= 408 //============================================================================== 409 410 /** 411 * The shifts and masks below may alternatively be used to format and read 412 * the command register bits. 413 */ 414 415 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 416 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 417 418 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 419 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 420 421 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 422 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 423 424 /** 425 * Command responses. 426 */ 427 428 /** 429 * Return response for DMUB_GPINT__STOP_FW command. 430 */ 431 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 432 433 /** 434 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 435 */ 436 union dmub_gpint_data_register { 437 struct { 438 uint32_t param : 16; /**< 16-bit parameter */ 439 uint32_t command_code : 12; /**< GPINT command */ 440 uint32_t status : 4; /**< Command status bit */ 441 } bits; /**< GPINT bit access */ 442 uint32_t all; /**< GPINT 32-bit access */ 443 }; 444 445 /* 446 * enum dmub_gpint_command - GPINT command to DMCUB FW 447 * 448 * Command IDs should be treated as stable ABI. 449 * Do not reuse or modify IDs. 450 */ 451 enum dmub_gpint_command { 452 /** 453 * Invalid command, ignored. 454 */ 455 DMUB_GPINT__INVALID_COMMAND = 0, 456 /** 457 * DESC: Queries the firmware version. 458 * RETURN: Firmware version. 459 */ 460 DMUB_GPINT__GET_FW_VERSION = 1, 461 /** 462 * DESC: Halts the firmware. 463 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 464 */ 465 DMUB_GPINT__STOP_FW = 2, 466 /** 467 * DESC: Get PSR state from FW. 468 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 469 */ 470 DMUB_GPINT__GET_PSR_STATE = 7, 471 /** 472 * DESC: Notifies DMCUB of the currently active streams. 473 * ARGS: Stream mask, 1 bit per active stream index. 474 */ 475 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 476 /** 477 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 478 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 479 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 480 * RETURN: PSR residency in milli-percent. 481 */ 482 DMUB_GPINT__PSR_RESIDENCY = 9, 483 484 /** 485 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 486 */ 487 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 488 }; 489 490 /** 491 * INBOX0 generic command definition 492 */ 493 union dmub_inbox0_cmd_common { 494 struct { 495 uint32_t command_code: 8; /**< INBOX0 command code */ 496 uint32_t param: 24; /**< 24-bit parameter */ 497 } bits; 498 uint32_t all; 499 }; 500 501 /** 502 * INBOX0 hw_lock command definition 503 */ 504 union dmub_inbox0_cmd_lock_hw { 505 struct { 506 uint32_t command_code: 8; 507 508 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 509 uint32_t hw_lock_client: 2; 510 511 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 512 uint32_t otg_inst: 3; 513 uint32_t opp_inst: 3; 514 uint32_t dig_inst: 3; 515 516 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 517 uint32_t lock_pipe: 1; 518 uint32_t lock_cursor: 1; 519 uint32_t lock_dig: 1; 520 uint32_t triple_buffer_lock: 1; 521 522 uint32_t lock: 1; /**< Lock */ 523 uint32_t should_release: 1; /**< Release */ 524 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 525 } bits; 526 uint32_t all; 527 }; 528 529 union dmub_inbox0_data_register { 530 union dmub_inbox0_cmd_common inbox0_cmd_common; 531 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 532 }; 533 534 enum dmub_inbox0_command { 535 /** 536 * DESC: Invalid command, ignored. 537 */ 538 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 539 /** 540 * DESC: Notification to acquire/release HW lock 541 * ARGS: 542 */ 543 DMUB_INBOX0_CMD__HW_LOCK = 1, 544 }; 545 //============================================================================== 546 //</DMUB_GPINT>================================================================= 547 //============================================================================== 548 //< DMUB_CMD>=================================================================== 549 //============================================================================== 550 551 /** 552 * Size in bytes of each DMUB command. 553 */ 554 #define DMUB_RB_CMD_SIZE 64 555 556 /** 557 * Maximum number of items in the DMUB ringbuffer. 558 */ 559 #define DMUB_RB_MAX_ENTRY 128 560 561 /** 562 * Ringbuffer size in bytes. 563 */ 564 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 565 566 /** 567 * REG_SET mask for reg offload. 568 */ 569 #define REG_SET_MASK 0xFFFF 570 571 /* 572 * enum dmub_cmd_type - DMUB inbox command. 573 * 574 * Command IDs should be treated as stable ABI. 575 * Do not reuse or modify IDs. 576 */ 577 enum dmub_cmd_type { 578 /** 579 * Invalid command. 580 */ 581 DMUB_CMD__NULL = 0, 582 /** 583 * Read modify write register sequence offload. 584 */ 585 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 586 /** 587 * Field update register sequence offload. 588 */ 589 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 590 /** 591 * Burst write sequence offload. 592 */ 593 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 594 /** 595 * Reg wait sequence offload. 596 */ 597 DMUB_CMD__REG_REG_WAIT = 4, 598 /** 599 * Workaround to avoid HUBP underflow during NV12 playback. 600 */ 601 DMUB_CMD__PLAT_54186_WA = 5, 602 /** 603 * Command type used to query FW feature caps. 604 */ 605 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 606 /** 607 * Command type used for all PSR commands. 608 */ 609 DMUB_CMD__PSR = 64, 610 /** 611 * Command type used for all MALL commands. 612 */ 613 DMUB_CMD__MALL = 65, 614 /** 615 * Command type used for all ABM commands. 616 */ 617 DMUB_CMD__ABM = 66, 618 /** 619 * Command type used for HW locking in FW. 620 */ 621 DMUB_CMD__HW_LOCK = 69, 622 /** 623 * Command type used to access DP AUX. 624 */ 625 DMUB_CMD__DP_AUX_ACCESS = 70, 626 /** 627 * Command type used for OUTBOX1 notification enable 628 */ 629 DMUB_CMD__OUTBOX1_ENABLE = 71, 630 631 /** 632 * Command type used for all idle optimization commands. 633 */ 634 DMUB_CMD__IDLE_OPT = 72, 635 /** 636 * Command type used for all clock manager commands. 637 */ 638 DMUB_CMD__CLK_MGR = 73, 639 /** 640 * Command type used for all panel control commands. 641 */ 642 DMUB_CMD__PANEL_CNTL = 74, 643 644 /** 645 * Command type used for interfacing with DPIA. 646 */ 647 DMUB_CMD__DPIA = 77, 648 /** 649 * Command type used for EDID CEA parsing 650 */ 651 DMUB_CMD__EDID_CEA = 79, 652 /** 653 * Command type used for getting usbc cable ID 654 */ 655 DMUB_CMD_GET_USBC_CABLE_ID = 81, 656 /** 657 * Command type used for all VBIOS interface commands. 658 */ 659 DMUB_CMD__VBIOS = 128, 660 }; 661 662 /** 663 * enum dmub_out_cmd_type - DMUB outbox commands. 664 */ 665 enum dmub_out_cmd_type { 666 /** 667 * Invalid outbox command, ignored. 668 */ 669 DMUB_OUT_CMD__NULL = 0, 670 /** 671 * Command type used for DP AUX Reply data notification 672 */ 673 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 674 /** 675 * Command type used for DP HPD event notification 676 */ 677 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 678 /** 679 * Command type used for SET_CONFIG Reply notification 680 */ 681 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 682 }; 683 684 /* DMUB_CMD__DPIA command sub-types. */ 685 enum dmub_cmd_dpia_type { 686 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 687 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 688 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 689 }; 690 691 #pragma pack(push, 1) 692 693 /** 694 * struct dmub_cmd_header - Common command header fields. 695 */ 696 struct dmub_cmd_header { 697 unsigned int type : 8; /**< command type */ 698 unsigned int sub_type : 8; /**< command sub type */ 699 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 700 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 701 unsigned int reserved0 : 6; /**< reserved bits */ 702 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 703 unsigned int reserved1 : 2; /**< reserved bits */ 704 }; 705 706 /* 707 * struct dmub_cmd_read_modify_write_sequence - Read modify write 708 * 709 * 60 payload bytes can hold up to 5 sets of read modify writes, 710 * each take 3 dwords. 711 * 712 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 713 * 714 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 715 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 716 */ 717 struct dmub_cmd_read_modify_write_sequence { 718 uint32_t addr; /**< register address */ 719 uint32_t modify_mask; /**< modify mask */ 720 uint32_t modify_value; /**< modify value */ 721 }; 722 723 /** 724 * Maximum number of ops in read modify write sequence. 725 */ 726 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 727 728 /** 729 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 730 */ 731 struct dmub_rb_cmd_read_modify_write { 732 struct dmub_cmd_header header; /**< command header */ 733 /** 734 * Read modify write sequence. 735 */ 736 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 737 }; 738 739 /* 740 * Update a register with specified masks and values sequeunce 741 * 742 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 743 * 744 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 745 * 746 * 747 * USE CASE: 748 * 1. auto-increment register where additional read would update pointer and produce wrong result 749 * 2. toggle a bit without read in the middle 750 */ 751 752 struct dmub_cmd_reg_field_update_sequence { 753 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 754 uint32_t modify_value; /**< value to update with */ 755 }; 756 757 /** 758 * Maximum number of ops in field update sequence. 759 */ 760 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 761 762 /** 763 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 764 */ 765 struct dmub_rb_cmd_reg_field_update_sequence { 766 struct dmub_cmd_header header; /**< command header */ 767 uint32_t addr; /**< register address */ 768 /** 769 * Field update sequence. 770 */ 771 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 772 }; 773 774 775 /** 776 * Maximum number of burst write values. 777 */ 778 #define DMUB_BURST_WRITE_VALUES__MAX 14 779 780 /* 781 * struct dmub_rb_cmd_burst_write - Burst write 782 * 783 * support use case such as writing out LUTs. 784 * 785 * 60 payload bytes can hold up to 14 values to write to given address 786 * 787 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 788 */ 789 struct dmub_rb_cmd_burst_write { 790 struct dmub_cmd_header header; /**< command header */ 791 uint32_t addr; /**< register start address */ 792 /** 793 * Burst write register values. 794 */ 795 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 796 }; 797 798 /** 799 * struct dmub_rb_cmd_common - Common command header 800 */ 801 struct dmub_rb_cmd_common { 802 struct dmub_cmd_header header; /**< command header */ 803 /** 804 * Padding to RB_CMD_SIZE 805 */ 806 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 807 }; 808 809 /** 810 * struct dmub_cmd_reg_wait_data - Register wait data 811 */ 812 struct dmub_cmd_reg_wait_data { 813 uint32_t addr; /**< Register address */ 814 uint32_t mask; /**< Mask for register bits */ 815 uint32_t condition_field_value; /**< Value to wait for */ 816 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 817 }; 818 819 /** 820 * struct dmub_rb_cmd_reg_wait - Register wait command 821 */ 822 struct dmub_rb_cmd_reg_wait { 823 struct dmub_cmd_header header; /**< Command header */ 824 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 825 }; 826 827 /** 828 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 829 * 830 * Reprograms surface parameters to avoid underflow. 831 */ 832 struct dmub_cmd_PLAT_54186_wa { 833 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 834 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 835 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 836 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 837 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 838 struct { 839 uint8_t hubp_inst : 4; /**< HUBP instance */ 840 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 841 uint8_t immediate :1; /**< Immediate flip */ 842 uint8_t vmid : 4; /**< VMID */ 843 uint8_t grph_stereo : 1; /**< 1 if stereo */ 844 uint32_t reserved : 21; /**< Reserved */ 845 } flip_params; /**< Pageflip parameters */ 846 uint32_t reserved[9]; /**< Reserved bits */ 847 }; 848 849 /** 850 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 851 */ 852 struct dmub_rb_cmd_PLAT_54186_wa { 853 struct dmub_cmd_header header; /**< Command header */ 854 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 855 }; 856 857 /** 858 * struct dmub_rb_cmd_mall - MALL command data. 859 */ 860 struct dmub_rb_cmd_mall { 861 struct dmub_cmd_header header; /**< Common command header */ 862 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 863 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 864 uint32_t tmr_delay; /**< Timer delay */ 865 uint32_t tmr_scale; /**< Timer scale */ 866 uint16_t cursor_width; /**< Cursor width in pixels */ 867 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 868 uint16_t cursor_height; /**< Cursor height in pixels */ 869 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 870 uint8_t debug_bits; /**< Debug bits */ 871 872 uint8_t reserved1; /**< Reserved bits */ 873 uint8_t reserved2; /**< Reserved bits */ 874 }; 875 876 /** 877 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 878 */ 879 enum dmub_cmd_idle_opt_type { 880 /** 881 * DCN hardware restore. 882 */ 883 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 884 885 /** 886 * DCN hardware save. 887 */ 888 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 889 }; 890 891 /** 892 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 893 */ 894 struct dmub_rb_cmd_idle_opt_dcn_restore { 895 struct dmub_cmd_header header; /**< header */ 896 }; 897 898 /** 899 * struct dmub_clocks - Clock update notification. 900 */ 901 struct dmub_clocks { 902 uint32_t dispclk_khz; /**< dispclk kHz */ 903 uint32_t dppclk_khz; /**< dppclk kHz */ 904 uint32_t dcfclk_khz; /**< dcfclk kHz */ 905 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 906 }; 907 908 /** 909 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 910 */ 911 enum dmub_cmd_clk_mgr_type { 912 /** 913 * Notify DMCUB of clock update. 914 */ 915 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 916 }; 917 918 /** 919 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 920 */ 921 struct dmub_rb_cmd_clk_mgr_notify_clocks { 922 struct dmub_cmd_header header; /**< header */ 923 struct dmub_clocks clocks; /**< clock data */ 924 }; 925 926 /** 927 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 928 */ 929 struct dmub_cmd_digx_encoder_control_data { 930 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 931 }; 932 933 /** 934 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 935 */ 936 struct dmub_rb_cmd_digx_encoder_control { 937 struct dmub_cmd_header header; /**< header */ 938 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 939 }; 940 941 /** 942 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 943 */ 944 struct dmub_cmd_set_pixel_clock_data { 945 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 946 }; 947 948 /** 949 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 950 */ 951 struct dmub_rb_cmd_set_pixel_clock { 952 struct dmub_cmd_header header; /**< header */ 953 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 954 }; 955 956 /** 957 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 958 */ 959 struct dmub_cmd_enable_disp_power_gating_data { 960 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 961 }; 962 963 /** 964 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 965 */ 966 struct dmub_rb_cmd_enable_disp_power_gating { 967 struct dmub_cmd_header header; /**< header */ 968 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 969 }; 970 971 /** 972 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 973 */ 974 struct dmub_dig_transmitter_control_data_v1_7 { 975 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 976 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 977 union { 978 uint8_t digmode; /**< enum atom_encode_mode_def */ 979 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 980 } mode_laneset; 981 uint8_t lanenum; /**< Number of lanes */ 982 union { 983 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 984 } symclk_units; 985 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 986 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 987 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 988 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 989 uint8_t reserved1; /**< For future use */ 990 uint8_t reserved2[3]; /**< For future use */ 991 uint32_t reserved3[11]; /**< For future use */ 992 }; 993 994 /** 995 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 996 */ 997 union dmub_cmd_dig1_transmitter_control_data { 998 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 999 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1000 }; 1001 1002 /** 1003 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1004 */ 1005 struct dmub_rb_cmd_dig1_transmitter_control { 1006 struct dmub_cmd_header header; /**< header */ 1007 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1008 }; 1009 1010 /** 1011 * DPIA tunnel command parameters. 1012 */ 1013 struct dmub_cmd_dig_dpia_control_data { 1014 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1015 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1016 union { 1017 uint8_t digmode; /** enum atom_encode_mode_def */ 1018 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1019 } mode_laneset; 1020 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1021 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1022 uint8_t hpdsel; /** =0: HPD is not assigned */ 1023 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1024 uint8_t dpia_id; /** Index of DPIA */ 1025 uint8_t fec_rdy : 1; 1026 uint8_t reserved : 7; 1027 uint32_t reserved1; 1028 }; 1029 1030 /** 1031 * DMUB command for DPIA tunnel control. 1032 */ 1033 struct dmub_rb_cmd_dig1_dpia_control { 1034 struct dmub_cmd_header header; 1035 struct dmub_cmd_dig_dpia_control_data dpia_control; 1036 }; 1037 1038 /** 1039 * SET_CONFIG Command Payload 1040 */ 1041 struct set_config_cmd_payload { 1042 uint8_t msg_type; /* set config message type */ 1043 uint8_t msg_data; /* set config message data */ 1044 }; 1045 1046 /** 1047 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1048 */ 1049 struct dmub_cmd_set_config_control_data { 1050 struct set_config_cmd_payload cmd_pkt; 1051 uint8_t instance; /* DPIA instance */ 1052 uint8_t immed_status; /* Immediate status returned in case of error */ 1053 }; 1054 1055 /** 1056 * DMUB command structure for SET_CONFIG command. 1057 */ 1058 struct dmub_rb_cmd_set_config_access { 1059 struct dmub_cmd_header header; /* header */ 1060 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1061 }; 1062 1063 /** 1064 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1065 */ 1066 struct dmub_cmd_mst_alloc_slots_control_data { 1067 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1068 uint8_t instance; /* DPIA instance */ 1069 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1070 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1071 }; 1072 1073 /** 1074 * DMUB command structure for SET_ command. 1075 */ 1076 struct dmub_rb_cmd_set_mst_alloc_slots { 1077 struct dmub_cmd_header header; /* header */ 1078 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1079 }; 1080 1081 /** 1082 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1083 */ 1084 struct dmub_rb_cmd_dpphy_init { 1085 struct dmub_cmd_header header; /**< header */ 1086 uint8_t reserved[60]; /**< reserved bits */ 1087 }; 1088 1089 /** 1090 * enum dp_aux_request_action - DP AUX request command listing. 1091 * 1092 * 4 AUX request command bits are shifted to high nibble. 1093 */ 1094 enum dp_aux_request_action { 1095 /** I2C-over-AUX write request */ 1096 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1097 /** I2C-over-AUX read request */ 1098 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1099 /** I2C-over-AUX write status request */ 1100 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1101 /** I2C-over-AUX write request with MOT=1 */ 1102 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1103 /** I2C-over-AUX read request with MOT=1 */ 1104 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1105 /** I2C-over-AUX write status request with MOT=1 */ 1106 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1107 /** Native AUX write request */ 1108 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1109 /** Native AUX read request */ 1110 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1111 }; 1112 1113 /** 1114 * enum aux_return_code_type - DP AUX process return code listing. 1115 */ 1116 enum aux_return_code_type { 1117 /** AUX process succeeded */ 1118 AUX_RET_SUCCESS = 0, 1119 /** AUX process failed with unknown reason */ 1120 AUX_RET_ERROR_UNKNOWN, 1121 /** AUX process completed with invalid reply */ 1122 AUX_RET_ERROR_INVALID_REPLY, 1123 /** AUX process timed out */ 1124 AUX_RET_ERROR_TIMEOUT, 1125 /** HPD was low during AUX process */ 1126 AUX_RET_ERROR_HPD_DISCON, 1127 /** Failed to acquire AUX engine */ 1128 AUX_RET_ERROR_ENGINE_ACQUIRE, 1129 /** AUX request not supported */ 1130 AUX_RET_ERROR_INVALID_OPERATION, 1131 /** AUX process not available */ 1132 AUX_RET_ERROR_PROTOCOL_ERROR, 1133 }; 1134 1135 /** 1136 * enum aux_channel_type - DP AUX channel type listing. 1137 */ 1138 enum aux_channel_type { 1139 /** AUX thru Legacy DP AUX */ 1140 AUX_CHANNEL_LEGACY_DDC, 1141 /** AUX thru DPIA DP tunneling */ 1142 AUX_CHANNEL_DPIA 1143 }; 1144 1145 /** 1146 * struct aux_transaction_parameters - DP AUX request transaction data 1147 */ 1148 struct aux_transaction_parameters { 1149 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1150 uint8_t action; /**< enum dp_aux_request_action */ 1151 uint8_t length; /**< DP AUX request data length */ 1152 uint8_t reserved; /**< For future use */ 1153 uint32_t address; /**< DP AUX address */ 1154 uint8_t data[16]; /**< DP AUX write data */ 1155 }; 1156 1157 /** 1158 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1159 */ 1160 struct dmub_cmd_dp_aux_control_data { 1161 uint8_t instance; /**< AUX instance or DPIA instance */ 1162 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1163 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1164 uint8_t reserved0; /**< For future use */ 1165 uint16_t timeout; /**< timeout time in us */ 1166 uint16_t reserved1; /**< For future use */ 1167 enum aux_channel_type type; /**< enum aux_channel_type */ 1168 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1169 }; 1170 1171 /** 1172 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1173 */ 1174 struct dmub_rb_cmd_dp_aux_access { 1175 /** 1176 * Command header. 1177 */ 1178 struct dmub_cmd_header header; 1179 /** 1180 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1181 */ 1182 struct dmub_cmd_dp_aux_control_data aux_control; 1183 }; 1184 1185 /** 1186 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1187 */ 1188 struct dmub_rb_cmd_outbox1_enable { 1189 /** 1190 * Command header. 1191 */ 1192 struct dmub_cmd_header header; 1193 /** 1194 * enable: 0x0 -> disable outbox1 notification (default value) 1195 * 0x1 -> enable outbox1 notification 1196 */ 1197 uint32_t enable; 1198 }; 1199 1200 /* DP AUX Reply command - OutBox Cmd */ 1201 /** 1202 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1203 */ 1204 struct aux_reply_data { 1205 /** 1206 * Aux cmd 1207 */ 1208 uint8_t command; 1209 /** 1210 * Aux reply data length (max: 16 bytes) 1211 */ 1212 uint8_t length; 1213 /** 1214 * Alignment only 1215 */ 1216 uint8_t pad[2]; 1217 /** 1218 * Aux reply data 1219 */ 1220 uint8_t data[16]; 1221 }; 1222 1223 /** 1224 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1225 */ 1226 struct aux_reply_control_data { 1227 /** 1228 * Reserved for future use 1229 */ 1230 uint32_t handle; 1231 /** 1232 * Aux Instance 1233 */ 1234 uint8_t instance; 1235 /** 1236 * Aux transaction result: definition in enum aux_return_code_type 1237 */ 1238 uint8_t result; 1239 /** 1240 * Alignment only 1241 */ 1242 uint16_t pad; 1243 }; 1244 1245 /** 1246 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1247 */ 1248 struct dmub_rb_cmd_dp_aux_reply { 1249 /** 1250 * Command header. 1251 */ 1252 struct dmub_cmd_header header; 1253 /** 1254 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1255 */ 1256 struct aux_reply_control_data control; 1257 /** 1258 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1259 */ 1260 struct aux_reply_data reply_data; 1261 }; 1262 1263 /* DP HPD Notify command - OutBox Cmd */ 1264 /** 1265 * DP HPD Type 1266 */ 1267 enum dp_hpd_type { 1268 /** 1269 * Normal DP HPD 1270 */ 1271 DP_HPD = 0, 1272 /** 1273 * DP HPD short pulse 1274 */ 1275 DP_IRQ 1276 }; 1277 1278 /** 1279 * DP HPD Status 1280 */ 1281 enum dp_hpd_status { 1282 /** 1283 * DP_HPD status low 1284 */ 1285 DP_HPD_UNPLUG = 0, 1286 /** 1287 * DP_HPD status high 1288 */ 1289 DP_HPD_PLUG 1290 }; 1291 1292 /** 1293 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1294 */ 1295 struct dp_hpd_data { 1296 /** 1297 * DP HPD instance 1298 */ 1299 uint8_t instance; 1300 /** 1301 * HPD type 1302 */ 1303 uint8_t hpd_type; 1304 /** 1305 * HPD status: only for type: DP_HPD to indicate status 1306 */ 1307 uint8_t hpd_status; 1308 /** 1309 * Alignment only 1310 */ 1311 uint8_t pad; 1312 }; 1313 1314 /** 1315 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1316 */ 1317 struct dmub_rb_cmd_dp_hpd_notify { 1318 /** 1319 * Command header. 1320 */ 1321 struct dmub_cmd_header header; 1322 /** 1323 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1324 */ 1325 struct dp_hpd_data hpd_data; 1326 }; 1327 1328 /** 1329 * Definition of a SET_CONFIG reply from DPOA. 1330 */ 1331 enum set_config_status { 1332 SET_CONFIG_PENDING = 0, 1333 SET_CONFIG_ACK_RECEIVED, 1334 SET_CONFIG_RX_TIMEOUT, 1335 SET_CONFIG_UNKNOWN_ERROR, 1336 }; 1337 1338 /** 1339 * Definition of a set_config reply 1340 */ 1341 struct set_config_reply_control_data { 1342 uint8_t instance; /* DPIA Instance */ 1343 uint8_t status; /* Set Config reply */ 1344 uint16_t pad; /* Alignment */ 1345 }; 1346 1347 /** 1348 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1349 */ 1350 struct dmub_rb_cmd_dp_set_config_reply { 1351 struct dmub_cmd_header header; 1352 struct set_config_reply_control_data set_config_reply_control; 1353 }; 1354 1355 /* 1356 * Command IDs should be treated as stable ABI. 1357 * Do not reuse or modify IDs. 1358 */ 1359 1360 /** 1361 * PSR command sub-types. 1362 */ 1363 enum dmub_cmd_psr_type { 1364 /** 1365 * Set PSR version support. 1366 */ 1367 DMUB_CMD__PSR_SET_VERSION = 0, 1368 /** 1369 * Copy driver-calculated parameters to PSR state. 1370 */ 1371 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1372 /** 1373 * Enable PSR. 1374 */ 1375 DMUB_CMD__PSR_ENABLE = 2, 1376 1377 /** 1378 * Disable PSR. 1379 */ 1380 DMUB_CMD__PSR_DISABLE = 3, 1381 1382 /** 1383 * Set PSR level. 1384 * PSR level is a 16-bit value dicated by driver that 1385 * will enable/disable different functionality. 1386 */ 1387 DMUB_CMD__PSR_SET_LEVEL = 4, 1388 1389 /** 1390 * Forces PSR enabled until an explicit PSR disable call. 1391 */ 1392 DMUB_CMD__PSR_FORCE_STATIC = 5, 1393 /** 1394 * Set PSR power option 1395 */ 1396 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1397 }; 1398 1399 /** 1400 * PSR versions. 1401 */ 1402 enum psr_version { 1403 /** 1404 * PSR version 1. 1405 */ 1406 PSR_VERSION_1 = 0, 1407 /** 1408 * PSR not supported. 1409 */ 1410 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1411 }; 1412 1413 /** 1414 * enum dmub_cmd_mall_type - MALL commands 1415 */ 1416 enum dmub_cmd_mall_type { 1417 /** 1418 * Allows display refresh from MALL. 1419 */ 1420 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1421 /** 1422 * Disallows display refresh from MALL. 1423 */ 1424 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1425 /** 1426 * Cursor copy for MALL. 1427 */ 1428 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1429 /** 1430 * Controls DF requests. 1431 */ 1432 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1433 }; 1434 1435 /** 1436 * PHY Link rate for DP. 1437 */ 1438 enum phy_link_rate { 1439 /** 1440 * not supported. 1441 */ 1442 PHY_RATE_UNKNOWN = 0, 1443 /** 1444 * Rate_1 (RBR) - 1.62 Gbps/Lane 1445 */ 1446 PHY_RATE_162 = 1, 1447 /** 1448 * Rate_2 - 2.16 Gbps/Lane 1449 */ 1450 PHY_RATE_216 = 2, 1451 /** 1452 * Rate_3 - 2.43 Gbps/Lane 1453 */ 1454 PHY_RATE_243 = 3, 1455 /** 1456 * Rate_4 (HBR) - 2.70 Gbps/Lane 1457 */ 1458 PHY_RATE_270 = 4, 1459 /** 1460 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1461 */ 1462 PHY_RATE_324 = 5, 1463 /** 1464 * Rate_6 - 4.32 Gbps/Lane 1465 */ 1466 PHY_RATE_432 = 6, 1467 /** 1468 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1469 */ 1470 PHY_RATE_540 = 7, 1471 /** 1472 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1473 */ 1474 PHY_RATE_810 = 8, 1475 /** 1476 * UHBR10 - 10.0 Gbps/Lane 1477 */ 1478 PHY_RATE_1000 = 9, 1479 /** 1480 * UHBR13.5 - 13.5 Gbps/Lane 1481 */ 1482 PHY_RATE_1350 = 10, 1483 /** 1484 * UHBR10 - 20.0 Gbps/Lane 1485 */ 1486 PHY_RATE_2000 = 11, 1487 }; 1488 1489 /** 1490 * enum dmub_phy_fsm_state - PHY FSM states. 1491 * PHY FSM state to transit to during PSR enable/disable. 1492 */ 1493 enum dmub_phy_fsm_state { 1494 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1495 DMUB_PHY_FSM_RESET, 1496 DMUB_PHY_FSM_RESET_RELEASED, 1497 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1498 DMUB_PHY_FSM_INITIALIZED, 1499 DMUB_PHY_FSM_CALIBRATED, 1500 DMUB_PHY_FSM_CALIBRATED_LP, 1501 DMUB_PHY_FSM_CALIBRATED_PG, 1502 DMUB_PHY_FSM_POWER_DOWN, 1503 DMUB_PHY_FSM_PLL_EN, 1504 DMUB_PHY_FSM_TX_EN, 1505 DMUB_PHY_FSM_FAST_LP, 1506 }; 1507 1508 /** 1509 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1510 */ 1511 struct dmub_cmd_psr_copy_settings_data { 1512 /** 1513 * Flags that can be set by driver to change some PSR behaviour. 1514 */ 1515 union dmub_psr_debug_flags debug; 1516 /** 1517 * 16-bit value dicated by driver that will enable/disable different functionality. 1518 */ 1519 uint16_t psr_level; 1520 /** 1521 * DPP HW instance. 1522 */ 1523 uint8_t dpp_inst; 1524 /** 1525 * MPCC HW instance. 1526 * Not used in dmub fw, 1527 * dmub fw will get active opp by reading odm registers. 1528 */ 1529 uint8_t mpcc_inst; 1530 /** 1531 * OPP HW instance. 1532 * Not used in dmub fw, 1533 * dmub fw will get active opp by reading odm registers. 1534 */ 1535 uint8_t opp_inst; 1536 /** 1537 * OTG HW instance. 1538 */ 1539 uint8_t otg_inst; 1540 /** 1541 * DIG FE HW instance. 1542 */ 1543 uint8_t digfe_inst; 1544 /** 1545 * DIG BE HW instance. 1546 */ 1547 uint8_t digbe_inst; 1548 /** 1549 * DP PHY HW instance. 1550 */ 1551 uint8_t dpphy_inst; 1552 /** 1553 * AUX HW instance. 1554 */ 1555 uint8_t aux_inst; 1556 /** 1557 * Determines if SMU optimzations are enabled/disabled. 1558 */ 1559 uint8_t smu_optimizations_en; 1560 /** 1561 * Unused. 1562 * TODO: Remove. 1563 */ 1564 uint8_t frame_delay; 1565 /** 1566 * If RFB setup time is greater than the total VBLANK time, 1567 * it is not possible for the sink to capture the video frame 1568 * in the same frame the SDP is sent. In this case, 1569 * the frame capture indication bit should be set and an extra 1570 * static frame should be transmitted to the sink. 1571 */ 1572 uint8_t frame_cap_ind; 1573 /** 1574 * Explicit padding to 4 byte boundary. 1575 */ 1576 uint8_t pad[2]; 1577 /** 1578 * Multi-display optimizations are implemented on certain ASICs. 1579 */ 1580 uint8_t multi_disp_optimizations_en; 1581 /** 1582 * The last possible line SDP may be transmitted without violating 1583 * the RFB setup time or entering the active video frame. 1584 */ 1585 uint16_t init_sdp_deadline; 1586 /** 1587 * Explicit padding to 4 byte boundary. 1588 */ 1589 uint16_t pad2; 1590 /** 1591 * Length of each horizontal line in us. 1592 */ 1593 uint32_t line_time_in_us; 1594 /** 1595 * FEC enable status in driver 1596 */ 1597 uint8_t fec_enable_status; 1598 /** 1599 * FEC re-enable delay when PSR exit. 1600 * unit is 100us, range form 0~255(0xFF). 1601 */ 1602 uint8_t fec_enable_delay_in100us; 1603 /** 1604 * PSR control version. 1605 */ 1606 uint8_t cmd_version; 1607 /** 1608 * Panel Instance. 1609 * Panel isntance to identify which psr_state to use 1610 * Currently the support is only for 0 or 1 1611 */ 1612 uint8_t panel_inst; 1613 /* 1614 * DSC enable status in driver 1615 */ 1616 uint8_t dsc_enable_status; 1617 /* 1618 * Use FSM state for PSR power up/down 1619 */ 1620 uint8_t use_phy_fsm; 1621 /** 1622 * Explicit padding to 2 byte boundary. 1623 */ 1624 uint8_t pad3[2]; 1625 }; 1626 1627 /** 1628 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1629 */ 1630 struct dmub_rb_cmd_psr_copy_settings { 1631 /** 1632 * Command header. 1633 */ 1634 struct dmub_cmd_header header; 1635 /** 1636 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1637 */ 1638 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1639 }; 1640 1641 /** 1642 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1643 */ 1644 struct dmub_cmd_psr_set_level_data { 1645 /** 1646 * 16-bit value dicated by driver that will enable/disable different functionality. 1647 */ 1648 uint16_t psr_level; 1649 /** 1650 * PSR control version. 1651 */ 1652 uint8_t cmd_version; 1653 /** 1654 * Panel Instance. 1655 * Panel isntance to identify which psr_state to use 1656 * Currently the support is only for 0 or 1 1657 */ 1658 uint8_t panel_inst; 1659 }; 1660 1661 /** 1662 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1663 */ 1664 struct dmub_rb_cmd_psr_set_level { 1665 /** 1666 * Command header. 1667 */ 1668 struct dmub_cmd_header header; 1669 /** 1670 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1671 */ 1672 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1673 }; 1674 1675 struct dmub_rb_cmd_psr_enable_data { 1676 /** 1677 * PSR control version. 1678 */ 1679 uint8_t cmd_version; 1680 /** 1681 * Panel Instance. 1682 * Panel isntance to identify which psr_state to use 1683 * Currently the support is only for 0 or 1 1684 */ 1685 uint8_t panel_inst; 1686 /** 1687 * Phy state to enter. 1688 * Values to use are defined in dmub_phy_fsm_state 1689 */ 1690 uint8_t phy_fsm_state; 1691 /** 1692 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1693 * Set this using enum phy_link_rate. 1694 * This does not support HDMI/DP2 for now. 1695 */ 1696 uint8_t phy_rate; 1697 }; 1698 1699 /** 1700 * Definition of a DMUB_CMD__PSR_ENABLE command. 1701 * PSR enable/disable is controlled using the sub_type. 1702 */ 1703 struct dmub_rb_cmd_psr_enable { 1704 /** 1705 * Command header. 1706 */ 1707 struct dmub_cmd_header header; 1708 1709 struct dmub_rb_cmd_psr_enable_data data; 1710 }; 1711 1712 /** 1713 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1714 */ 1715 struct dmub_cmd_psr_set_version_data { 1716 /** 1717 * PSR version that FW should implement. 1718 */ 1719 enum psr_version version; 1720 /** 1721 * PSR control version. 1722 */ 1723 uint8_t cmd_version; 1724 /** 1725 * Panel Instance. 1726 * Panel isntance to identify which psr_state to use 1727 * Currently the support is only for 0 or 1 1728 */ 1729 uint8_t panel_inst; 1730 /** 1731 * Explicit padding to 4 byte boundary. 1732 */ 1733 uint8_t pad[2]; 1734 }; 1735 1736 /** 1737 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1738 */ 1739 struct dmub_rb_cmd_psr_set_version { 1740 /** 1741 * Command header. 1742 */ 1743 struct dmub_cmd_header header; 1744 /** 1745 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1746 */ 1747 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1748 }; 1749 1750 struct dmub_cmd_psr_force_static_data { 1751 /** 1752 * PSR control version. 1753 */ 1754 uint8_t cmd_version; 1755 /** 1756 * Panel Instance. 1757 * Panel isntance to identify which psr_state to use 1758 * Currently the support is only for 0 or 1 1759 */ 1760 uint8_t panel_inst; 1761 /** 1762 * Explicit padding to 4 byte boundary. 1763 */ 1764 uint8_t pad[2]; 1765 }; 1766 1767 /** 1768 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1769 */ 1770 struct dmub_rb_cmd_psr_force_static { 1771 /** 1772 * Command header. 1773 */ 1774 struct dmub_cmd_header header; 1775 /** 1776 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1777 */ 1778 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1779 }; 1780 1781 /** 1782 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 1783 */ 1784 struct dmub_cmd_psr_set_power_opt_data { 1785 /** 1786 * PSR control version. 1787 */ 1788 uint8_t cmd_version; 1789 /** 1790 * Panel Instance. 1791 * Panel isntance to identify which psr_state to use 1792 * Currently the support is only for 0 or 1 1793 */ 1794 uint8_t panel_inst; 1795 /** 1796 * Explicit padding to 4 byte boundary. 1797 */ 1798 uint8_t pad[2]; 1799 /** 1800 * PSR power option 1801 */ 1802 uint32_t power_opt; 1803 }; 1804 1805 /** 1806 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1807 */ 1808 struct dmub_rb_cmd_psr_set_power_opt { 1809 /** 1810 * Command header. 1811 */ 1812 struct dmub_cmd_header header; 1813 /** 1814 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1815 */ 1816 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 1817 }; 1818 1819 /** 1820 * Set of HW components that can be locked. 1821 * 1822 * Note: If updating with more HW components, fields 1823 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1824 */ 1825 union dmub_hw_lock_flags { 1826 /** 1827 * Set of HW components that can be locked. 1828 */ 1829 struct { 1830 /** 1831 * Lock/unlock OTG master update lock. 1832 */ 1833 uint8_t lock_pipe : 1; 1834 /** 1835 * Lock/unlock cursor. 1836 */ 1837 uint8_t lock_cursor : 1; 1838 /** 1839 * Lock/unlock global update lock. 1840 */ 1841 uint8_t lock_dig : 1; 1842 /** 1843 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1844 */ 1845 uint8_t triple_buffer_lock : 1; 1846 } bits; 1847 1848 /** 1849 * Union for HW Lock flags. 1850 */ 1851 uint8_t u8All; 1852 }; 1853 1854 /** 1855 * Instances of HW to be locked. 1856 * 1857 * Note: If updating with more HW components, fields 1858 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1859 */ 1860 struct dmub_hw_lock_inst_flags { 1861 /** 1862 * OTG HW instance for OTG master update lock. 1863 */ 1864 uint8_t otg_inst; 1865 /** 1866 * OPP instance for cursor lock. 1867 */ 1868 uint8_t opp_inst; 1869 /** 1870 * OTG HW instance for global update lock. 1871 * TODO: Remove, and re-use otg_inst. 1872 */ 1873 uint8_t dig_inst; 1874 /** 1875 * Explicit pad to 4 byte boundary. 1876 */ 1877 uint8_t pad; 1878 }; 1879 1880 /** 1881 * Clients that can acquire the HW Lock Manager. 1882 * 1883 * Note: If updating with more clients, fields in 1884 * dmub_inbox0_cmd_lock_hw must be updated to match. 1885 */ 1886 enum hw_lock_client { 1887 /** 1888 * Driver is the client of HW Lock Manager. 1889 */ 1890 HW_LOCK_CLIENT_DRIVER = 0, 1891 /** 1892 * Invalid client. 1893 */ 1894 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1895 }; 1896 1897 /** 1898 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1899 */ 1900 struct dmub_cmd_lock_hw_data { 1901 /** 1902 * Specifies the client accessing HW Lock Manager. 1903 */ 1904 enum hw_lock_client client; 1905 /** 1906 * HW instances to be locked. 1907 */ 1908 struct dmub_hw_lock_inst_flags inst_flags; 1909 /** 1910 * Which components to be locked. 1911 */ 1912 union dmub_hw_lock_flags hw_locks; 1913 /** 1914 * Specifies lock/unlock. 1915 */ 1916 uint8_t lock; 1917 /** 1918 * HW can be unlocked separately from releasing the HW Lock Mgr. 1919 * This flag is set if the client wishes to release the object. 1920 */ 1921 uint8_t should_release; 1922 /** 1923 * Explicit padding to 4 byte boundary. 1924 */ 1925 uint8_t pad; 1926 }; 1927 1928 /** 1929 * Definition of a DMUB_CMD__HW_LOCK command. 1930 * Command is used by driver and FW. 1931 */ 1932 struct dmub_rb_cmd_lock_hw { 1933 /** 1934 * Command header. 1935 */ 1936 struct dmub_cmd_header header; 1937 /** 1938 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1939 */ 1940 struct dmub_cmd_lock_hw_data lock_hw_data; 1941 }; 1942 1943 /** 1944 * ABM command sub-types. 1945 */ 1946 enum dmub_cmd_abm_type { 1947 /** 1948 * Initialize parameters for ABM algorithm. 1949 * Data is passed through an indirect buffer. 1950 */ 1951 DMUB_CMD__ABM_INIT_CONFIG = 0, 1952 /** 1953 * Set OTG and panel HW instance. 1954 */ 1955 DMUB_CMD__ABM_SET_PIPE = 1, 1956 /** 1957 * Set user requested backklight level. 1958 */ 1959 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1960 /** 1961 * Set ABM operating/aggression level. 1962 */ 1963 DMUB_CMD__ABM_SET_LEVEL = 3, 1964 /** 1965 * Set ambient light level. 1966 */ 1967 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1968 /** 1969 * Enable/disable fractional duty cycle for backlight PWM. 1970 */ 1971 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1972 1973 /** 1974 * unregister vertical interrupt after steady state is reached 1975 */ 1976 DMUB_CMD__ABM_PAUSE = 6, 1977 }; 1978 1979 /** 1980 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1981 * Requirements: 1982 * - Padded explicitly to 32-bit boundary. 1983 * - Must ensure this structure matches the one on driver-side, 1984 * otherwise it won't be aligned. 1985 */ 1986 struct abm_config_table { 1987 /** 1988 * Gamma curve thresholds, used for crgb conversion. 1989 */ 1990 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1991 /** 1992 * Gamma curve offsets, used for crgb conversion. 1993 */ 1994 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1995 /** 1996 * Gamma curve slopes, used for crgb conversion. 1997 */ 1998 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1999 /** 2000 * Custom backlight curve thresholds. 2001 */ 2002 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2003 /** 2004 * Custom backlight curve offsets. 2005 */ 2006 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2007 /** 2008 * Ambient light thresholds. 2009 */ 2010 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2011 /** 2012 * Minimum programmable backlight. 2013 */ 2014 uint16_t min_abm_backlight; // 122B 2015 /** 2016 * Minimum reduction values. 2017 */ 2018 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2019 /** 2020 * Maximum reduction values. 2021 */ 2022 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2023 /** 2024 * Bright positive gain. 2025 */ 2026 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2027 /** 2028 * Dark negative gain. 2029 */ 2030 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2031 /** 2032 * Hybrid factor. 2033 */ 2034 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2035 /** 2036 * Contrast factor. 2037 */ 2038 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2039 /** 2040 * Deviation gain. 2041 */ 2042 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2043 /** 2044 * Minimum knee. 2045 */ 2046 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2047 /** 2048 * Maximum knee. 2049 */ 2050 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2051 /** 2052 * Unused. 2053 */ 2054 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2055 /** 2056 * Explicit padding to 4 byte boundary. 2057 */ 2058 uint8_t pad3[3]; // 229B 2059 /** 2060 * Backlight ramp reduction. 2061 */ 2062 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2063 /** 2064 * Backlight ramp start. 2065 */ 2066 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2067 }; 2068 2069 /** 2070 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2071 */ 2072 struct dmub_cmd_abm_set_pipe_data { 2073 /** 2074 * OTG HW instance. 2075 */ 2076 uint8_t otg_inst; 2077 2078 /** 2079 * Panel Control HW instance. 2080 */ 2081 uint8_t panel_inst; 2082 2083 /** 2084 * Controls how ABM will interpret a set pipe or set level command. 2085 */ 2086 uint8_t set_pipe_option; 2087 2088 /** 2089 * Unused. 2090 * TODO: Remove. 2091 */ 2092 uint8_t ramping_boundary; 2093 }; 2094 2095 /** 2096 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2097 */ 2098 struct dmub_rb_cmd_abm_set_pipe { 2099 /** 2100 * Command header. 2101 */ 2102 struct dmub_cmd_header header; 2103 2104 /** 2105 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2106 */ 2107 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2108 }; 2109 2110 /** 2111 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2112 */ 2113 struct dmub_cmd_abm_set_backlight_data { 2114 /** 2115 * Number of frames to ramp to backlight user level. 2116 */ 2117 uint32_t frame_ramp; 2118 2119 /** 2120 * Requested backlight level from user. 2121 */ 2122 uint32_t backlight_user_level; 2123 2124 /** 2125 * ABM control version. 2126 */ 2127 uint8_t version; 2128 2129 /** 2130 * Panel Control HW instance mask. 2131 * Bit 0 is Panel Control HW instance 0. 2132 * Bit 1 is Panel Control HW instance 1. 2133 */ 2134 uint8_t panel_mask; 2135 2136 /** 2137 * Explicit padding to 4 byte boundary. 2138 */ 2139 uint8_t pad[2]; 2140 }; 2141 2142 /** 2143 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2144 */ 2145 struct dmub_rb_cmd_abm_set_backlight { 2146 /** 2147 * Command header. 2148 */ 2149 struct dmub_cmd_header header; 2150 2151 /** 2152 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2153 */ 2154 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2155 }; 2156 2157 /** 2158 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2159 */ 2160 struct dmub_cmd_abm_set_level_data { 2161 /** 2162 * Set current ABM operating/aggression level. 2163 */ 2164 uint32_t level; 2165 2166 /** 2167 * ABM control version. 2168 */ 2169 uint8_t version; 2170 2171 /** 2172 * Panel Control HW instance mask. 2173 * Bit 0 is Panel Control HW instance 0. 2174 * Bit 1 is Panel Control HW instance 1. 2175 */ 2176 uint8_t panel_mask; 2177 2178 /** 2179 * Explicit padding to 4 byte boundary. 2180 */ 2181 uint8_t pad[2]; 2182 }; 2183 2184 /** 2185 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2186 */ 2187 struct dmub_rb_cmd_abm_set_level { 2188 /** 2189 * Command header. 2190 */ 2191 struct dmub_cmd_header header; 2192 2193 /** 2194 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2195 */ 2196 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2197 }; 2198 2199 /** 2200 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2201 */ 2202 struct dmub_cmd_abm_set_ambient_level_data { 2203 /** 2204 * Ambient light sensor reading from OS. 2205 */ 2206 uint32_t ambient_lux; 2207 2208 /** 2209 * ABM control version. 2210 */ 2211 uint8_t version; 2212 2213 /** 2214 * Panel Control HW instance mask. 2215 * Bit 0 is Panel Control HW instance 0. 2216 * Bit 1 is Panel Control HW instance 1. 2217 */ 2218 uint8_t panel_mask; 2219 2220 /** 2221 * Explicit padding to 4 byte boundary. 2222 */ 2223 uint8_t pad[2]; 2224 }; 2225 2226 /** 2227 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2228 */ 2229 struct dmub_rb_cmd_abm_set_ambient_level { 2230 /** 2231 * Command header. 2232 */ 2233 struct dmub_cmd_header header; 2234 2235 /** 2236 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2237 */ 2238 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2239 }; 2240 2241 /** 2242 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2243 */ 2244 struct dmub_cmd_abm_set_pwm_frac_data { 2245 /** 2246 * Enable/disable fractional duty cycle for backlight PWM. 2247 * TODO: Convert to uint8_t. 2248 */ 2249 uint32_t fractional_pwm; 2250 2251 /** 2252 * ABM control version. 2253 */ 2254 uint8_t version; 2255 2256 /** 2257 * Panel Control HW instance mask. 2258 * Bit 0 is Panel Control HW instance 0. 2259 * Bit 1 is Panel Control HW instance 1. 2260 */ 2261 uint8_t panel_mask; 2262 2263 /** 2264 * Explicit padding to 4 byte boundary. 2265 */ 2266 uint8_t pad[2]; 2267 }; 2268 2269 /** 2270 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2271 */ 2272 struct dmub_rb_cmd_abm_set_pwm_frac { 2273 /** 2274 * Command header. 2275 */ 2276 struct dmub_cmd_header header; 2277 2278 /** 2279 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2280 */ 2281 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2282 }; 2283 2284 /** 2285 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2286 */ 2287 struct dmub_cmd_abm_init_config_data { 2288 /** 2289 * Location of indirect buffer used to pass init data to ABM. 2290 */ 2291 union dmub_addr src; 2292 2293 /** 2294 * Indirect buffer length. 2295 */ 2296 uint16_t bytes; 2297 2298 2299 /** 2300 * ABM control version. 2301 */ 2302 uint8_t version; 2303 2304 /** 2305 * Panel Control HW instance mask. 2306 * Bit 0 is Panel Control HW instance 0. 2307 * Bit 1 is Panel Control HW instance 1. 2308 */ 2309 uint8_t panel_mask; 2310 2311 /** 2312 * Explicit padding to 4 byte boundary. 2313 */ 2314 uint8_t pad[2]; 2315 }; 2316 2317 /** 2318 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2319 */ 2320 struct dmub_rb_cmd_abm_init_config { 2321 /** 2322 * Command header. 2323 */ 2324 struct dmub_cmd_header header; 2325 2326 /** 2327 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2328 */ 2329 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2330 }; 2331 2332 /** 2333 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2334 */ 2335 2336 struct dmub_cmd_abm_pause_data { 2337 2338 /** 2339 * Panel Control HW instance mask. 2340 * Bit 0 is Panel Control HW instance 0. 2341 * Bit 1 is Panel Control HW instance 1. 2342 */ 2343 uint8_t panel_mask; 2344 2345 /** 2346 * OTG hw instance 2347 */ 2348 uint8_t otg_inst; 2349 2350 /** 2351 * Enable or disable ABM pause 2352 */ 2353 uint8_t enable; 2354 2355 /** 2356 * Explicit padding to 4 byte boundary. 2357 */ 2358 uint8_t pad[1]; 2359 }; 2360 2361 /** 2362 * Definition of a DMUB_CMD__ABM_PAUSE command. 2363 */ 2364 struct dmub_rb_cmd_abm_pause { 2365 /** 2366 * Command header. 2367 */ 2368 struct dmub_cmd_header header; 2369 2370 /** 2371 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2372 */ 2373 struct dmub_cmd_abm_pause_data abm_pause_data; 2374 }; 2375 2376 /** 2377 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2378 */ 2379 struct dmub_cmd_query_feature_caps_data { 2380 /** 2381 * DMUB feature capabilities. 2382 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2383 */ 2384 struct dmub_feature_caps feature_caps; 2385 }; 2386 2387 /** 2388 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2389 */ 2390 struct dmub_rb_cmd_query_feature_caps { 2391 /** 2392 * Command header. 2393 */ 2394 struct dmub_cmd_header header; 2395 /** 2396 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2397 */ 2398 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2399 }; 2400 2401 struct dmub_optc_state { 2402 uint32_t v_total_max; 2403 uint32_t v_total_min; 2404 uint32_t v_total_mid; 2405 uint32_t v_total_mid_frame_num; 2406 uint32_t tg_inst; 2407 uint32_t enable_manual_trigger; 2408 uint32_t clear_force_vsync; 2409 }; 2410 2411 struct dmub_rb_cmd_drr_update { 2412 struct dmub_cmd_header header; 2413 struct dmub_optc_state dmub_optc_state_req; 2414 }; 2415 2416 /** 2417 * enum dmub_cmd_panel_cntl_type - Panel control command. 2418 */ 2419 enum dmub_cmd_panel_cntl_type { 2420 /** 2421 * Initializes embedded panel hardware blocks. 2422 */ 2423 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2424 /** 2425 * Queries backlight info for the embedded panel. 2426 */ 2427 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2428 }; 2429 2430 /** 2431 * struct dmub_cmd_panel_cntl_data - Panel control data. 2432 */ 2433 struct dmub_cmd_panel_cntl_data { 2434 uint32_t inst; /**< panel instance */ 2435 uint32_t current_backlight; /* in/out */ 2436 uint32_t bl_pwm_cntl; /* in/out */ 2437 uint32_t bl_pwm_period_cntl; /* in/out */ 2438 uint32_t bl_pwm_ref_div1; /* in/out */ 2439 uint8_t is_backlight_on : 1; /* in/out */ 2440 uint8_t is_powered_on : 1; /* in/out */ 2441 uint8_t padding[3]; 2442 uint32_t bl_pwm_ref_div2; /* in/out */ 2443 uint8_t reserved[4]; 2444 }; 2445 2446 /** 2447 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2448 */ 2449 struct dmub_rb_cmd_panel_cntl { 2450 struct dmub_cmd_header header; /**< header */ 2451 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2452 }; 2453 2454 /** 2455 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2456 */ 2457 struct dmub_cmd_lvtma_control_data { 2458 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2459 uint8_t reserved_0[3]; /**< For future use */ 2460 uint8_t panel_inst; /**< LVTMA control instance */ 2461 uint8_t reserved_1[3]; /**< For future use */ 2462 }; 2463 2464 /** 2465 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2466 */ 2467 struct dmub_rb_cmd_lvtma_control { 2468 /** 2469 * Command header. 2470 */ 2471 struct dmub_cmd_header header; 2472 /** 2473 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2474 */ 2475 struct dmub_cmd_lvtma_control_data data; 2476 }; 2477 2478 /** 2479 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2480 */ 2481 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 2482 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2483 uint8_t is_usb; /**< is phy is usb */ 2484 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 2485 uint8_t is_dp4; /**< is dp in 4 lane */ 2486 }; 2487 2488 /** 2489 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2490 */ 2491 struct dmub_rb_cmd_transmitter_query_dp_alt { 2492 struct dmub_cmd_header header; /**< header */ 2493 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 2494 }; 2495 2496 /** 2497 * Maximum number of bytes a chunk sent to DMUB for parsing 2498 */ 2499 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2500 2501 /** 2502 * Represent a chunk of CEA blocks sent to DMUB for parsing 2503 */ 2504 struct dmub_cmd_send_edid_cea { 2505 uint16_t offset; /**< offset into the CEA block */ 2506 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2507 uint16_t cea_total_length; /**< total length of the CEA block */ 2508 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2509 uint8_t pad[3]; /**< padding and for future expansion */ 2510 }; 2511 2512 /** 2513 * Result of VSDB parsing from CEA block 2514 */ 2515 struct dmub_cmd_edid_cea_amd_vsdb { 2516 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2517 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2518 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2519 uint16_t min_frame_rate; /**< Maximum frame rate */ 2520 uint16_t max_frame_rate; /**< Minimum frame rate */ 2521 }; 2522 2523 /** 2524 * Result of sending a CEA chunk 2525 */ 2526 struct dmub_cmd_edid_cea_ack { 2527 uint16_t offset; /**< offset of the chunk into the CEA block */ 2528 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2529 uint8_t pad; /**< padding and for future expansion */ 2530 }; 2531 2532 /** 2533 * Specify whether the result is an ACK/NACK or the parsing has finished 2534 */ 2535 enum dmub_cmd_edid_cea_reply_type { 2536 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2537 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2538 }; 2539 2540 /** 2541 * Definition of a DMUB_CMD__EDID_CEA command. 2542 */ 2543 struct dmub_rb_cmd_edid_cea { 2544 struct dmub_cmd_header header; /**< Command header */ 2545 union dmub_cmd_edid_cea_data { 2546 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2547 struct dmub_cmd_edid_cea_output { /**< output with results */ 2548 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2549 union { 2550 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2551 struct dmub_cmd_edid_cea_ack ack; 2552 }; 2553 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2554 } data; /**< Command data */ 2555 2556 }; 2557 2558 /** 2559 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 2560 */ 2561 struct dmub_cmd_cable_id_input { 2562 uint8_t phy_inst; /**< phy inst for cable id data */ 2563 }; 2564 2565 /** 2566 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 2567 */ 2568 struct dmub_cmd_cable_id_output { 2569 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 2570 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 2571 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 2572 uint8_t RESERVED :2; /**< reserved means not defined */ 2573 }; 2574 2575 /** 2576 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 2577 */ 2578 struct dmub_rb_cmd_get_usbc_cable_id { 2579 struct dmub_cmd_header header; /**< Command header */ 2580 /** 2581 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 2582 */ 2583 union dmub_cmd_cable_id_data { 2584 struct dmub_cmd_cable_id_input input; /**< Input */ 2585 struct dmub_cmd_cable_id_output output; /**< Output */ 2586 uint8_t output_raw; /**< Raw data output */ 2587 } data; 2588 }; 2589 2590 /** 2591 * union dmub_rb_cmd - DMUB inbox command. 2592 */ 2593 union dmub_rb_cmd { 2594 struct dmub_rb_cmd_lock_hw lock_hw; 2595 /** 2596 * Elements shared with all commands. 2597 */ 2598 struct dmub_rb_cmd_common cmd_common; 2599 /** 2600 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2601 */ 2602 struct dmub_rb_cmd_read_modify_write read_modify_write; 2603 /** 2604 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2605 */ 2606 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2607 /** 2608 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2609 */ 2610 struct dmub_rb_cmd_burst_write burst_write; 2611 /** 2612 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2613 */ 2614 struct dmub_rb_cmd_reg_wait reg_wait; 2615 /** 2616 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2617 */ 2618 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2619 /** 2620 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2621 */ 2622 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2623 /** 2624 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2625 */ 2626 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2627 /** 2628 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2629 */ 2630 struct dmub_rb_cmd_dpphy_init dpphy_init; 2631 /** 2632 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2633 */ 2634 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2635 /** 2636 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2637 */ 2638 struct dmub_rb_cmd_psr_set_version psr_set_version; 2639 /** 2640 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2641 */ 2642 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2643 /** 2644 * Definition of a DMUB_CMD__PSR_ENABLE command. 2645 */ 2646 struct dmub_rb_cmd_psr_enable psr_enable; 2647 /** 2648 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2649 */ 2650 struct dmub_rb_cmd_psr_set_level psr_set_level; 2651 /** 2652 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2653 */ 2654 struct dmub_rb_cmd_psr_force_static psr_force_static; 2655 /** 2656 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2657 */ 2658 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 2659 /** 2660 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2661 */ 2662 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2663 /** 2664 * Definition of a DMUB_CMD__MALL command. 2665 */ 2666 struct dmub_rb_cmd_mall mall; 2667 /** 2668 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2669 */ 2670 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2671 2672 /** 2673 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2674 */ 2675 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2676 2677 /** 2678 * Definition of DMUB_CMD__PANEL_CNTL commands. 2679 */ 2680 struct dmub_rb_cmd_panel_cntl panel_cntl; 2681 /** 2682 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2683 */ 2684 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2685 2686 /** 2687 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2688 */ 2689 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2690 2691 /** 2692 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2693 */ 2694 struct dmub_rb_cmd_abm_set_level abm_set_level; 2695 2696 /** 2697 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2698 */ 2699 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2700 2701 /** 2702 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2703 */ 2704 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2705 2706 /** 2707 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2708 */ 2709 struct dmub_rb_cmd_abm_init_config abm_init_config; 2710 2711 /** 2712 * Definition of a DMUB_CMD__ABM_PAUSE command. 2713 */ 2714 struct dmub_rb_cmd_abm_pause abm_pause; 2715 2716 /** 2717 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2718 */ 2719 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2720 2721 /** 2722 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2723 */ 2724 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2725 2726 /** 2727 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2728 */ 2729 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2730 struct dmub_rb_cmd_drr_update drr_update; 2731 /** 2732 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2733 */ 2734 struct dmub_rb_cmd_lvtma_control lvtma_control; 2735 /** 2736 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2737 */ 2738 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 2739 /** 2740 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 2741 */ 2742 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 2743 /** 2744 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 2745 */ 2746 struct dmub_rb_cmd_set_config_access set_config_access; 2747 /** 2748 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2749 */ 2750 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 2751 /** 2752 * Definition of a DMUB_CMD__EDID_CEA command. 2753 */ 2754 struct dmub_rb_cmd_edid_cea edid_cea; 2755 /** 2756 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 2757 */ 2758 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 2759 }; 2760 2761 /** 2762 * union dmub_rb_out_cmd - Outbox command 2763 */ 2764 union dmub_rb_out_cmd { 2765 /** 2766 * Parameters common to every command. 2767 */ 2768 struct dmub_rb_cmd_common cmd_common; 2769 /** 2770 * AUX reply command. 2771 */ 2772 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2773 /** 2774 * HPD notify command. 2775 */ 2776 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2777 /** 2778 * SET_CONFIG reply command. 2779 */ 2780 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 2781 }; 2782 #pragma pack(pop) 2783 2784 2785 //============================================================================== 2786 //</DMUB_CMD>=================================================================== 2787 //============================================================================== 2788 //< DMUB_RB>==================================================================== 2789 //============================================================================== 2790 2791 #if defined(__cplusplus) 2792 extern "C" { 2793 #endif 2794 2795 /** 2796 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2797 */ 2798 struct dmub_rb_init_params { 2799 void *ctx; /**< Caller provided context pointer */ 2800 void *base_address; /**< CPU base address for ring's data */ 2801 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2802 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2803 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2804 }; 2805 2806 /** 2807 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2808 */ 2809 struct dmub_rb { 2810 void *base_address; /**< CPU address for the ring's data */ 2811 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2812 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2813 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2814 2815 void *ctx; /**< Caller provided context pointer */ 2816 void *dmub; /**< Pointer to the DMUB interface */ 2817 }; 2818 2819 /** 2820 * @brief Checks if the ringbuffer is empty. 2821 * 2822 * @param rb DMUB Ringbuffer 2823 * @return true if empty 2824 * @return false otherwise 2825 */ 2826 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2827 { 2828 return (rb->wrpt == rb->rptr); 2829 } 2830 2831 /** 2832 * @brief Checks if the ringbuffer is full 2833 * 2834 * @param rb DMUB Ringbuffer 2835 * @return true if full 2836 * @return false otherwise 2837 */ 2838 static inline bool dmub_rb_full(struct dmub_rb *rb) 2839 { 2840 uint32_t data_count; 2841 2842 if (rb->wrpt >= rb->rptr) 2843 data_count = rb->wrpt - rb->rptr; 2844 else 2845 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2846 2847 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2848 } 2849 2850 /** 2851 * @brief Pushes a command into the ringbuffer 2852 * 2853 * @param rb DMUB ringbuffer 2854 * @param cmd The command to push 2855 * @return true if the ringbuffer was not full 2856 * @return false otherwise 2857 */ 2858 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2859 const union dmub_rb_cmd *cmd) 2860 { 2861 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 2862 const uint64_t *src = (const uint64_t *)cmd; 2863 uint8_t i; 2864 2865 if (dmub_rb_full(rb)) 2866 return false; 2867 2868 // copying data 2869 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2870 *dst++ = *src++; 2871 2872 rb->wrpt += DMUB_RB_CMD_SIZE; 2873 2874 if (rb->wrpt >= rb->capacity) 2875 rb->wrpt %= rb->capacity; 2876 2877 return true; 2878 } 2879 2880 /** 2881 * @brief Pushes a command into the DMUB outbox ringbuffer 2882 * 2883 * @param rb DMUB outbox ringbuffer 2884 * @param cmd Outbox command 2885 * @return true if not full 2886 * @return false otherwise 2887 */ 2888 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2889 const union dmub_rb_out_cmd *cmd) 2890 { 2891 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2892 const uint8_t *src = (const uint8_t *)cmd; 2893 2894 if (dmub_rb_full(rb)) 2895 return false; 2896 2897 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2898 2899 rb->wrpt += DMUB_RB_CMD_SIZE; 2900 2901 if (rb->wrpt >= rb->capacity) 2902 rb->wrpt %= rb->capacity; 2903 2904 return true; 2905 } 2906 2907 /** 2908 * @brief Returns the next unprocessed command in the ringbuffer. 2909 * 2910 * @param rb DMUB ringbuffer 2911 * @param cmd The command to return 2912 * @return true if not empty 2913 * @return false otherwise 2914 */ 2915 static inline bool dmub_rb_front(struct dmub_rb *rb, 2916 union dmub_rb_cmd **cmd) 2917 { 2918 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2919 2920 if (dmub_rb_empty(rb)) 2921 return false; 2922 2923 *cmd = (union dmub_rb_cmd *)rb_cmd; 2924 2925 return true; 2926 } 2927 2928 /** 2929 * @brief Determines the next ringbuffer offset. 2930 * 2931 * @param rb DMUB inbox ringbuffer 2932 * @param num_cmds Number of commands 2933 * @param next_rptr The next offset in the ringbuffer 2934 */ 2935 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2936 uint32_t num_cmds, 2937 uint32_t *next_rptr) 2938 { 2939 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2940 2941 if (*next_rptr >= rb->capacity) 2942 *next_rptr %= rb->capacity; 2943 } 2944 2945 /** 2946 * @brief Returns a pointer to a command in the inbox. 2947 * 2948 * @param rb DMUB inbox ringbuffer 2949 * @param cmd The inbox command to return 2950 * @param rptr The ringbuffer offset 2951 * @return true if not empty 2952 * @return false otherwise 2953 */ 2954 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 2955 union dmub_rb_cmd **cmd, 2956 uint32_t rptr) 2957 { 2958 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 2959 2960 if (dmub_rb_empty(rb)) 2961 return false; 2962 2963 *cmd = (union dmub_rb_cmd *)rb_cmd; 2964 2965 return true; 2966 } 2967 2968 /** 2969 * @brief Returns the next unprocessed command in the outbox. 2970 * 2971 * @param rb DMUB outbox ringbuffer 2972 * @param cmd The outbox command to return 2973 * @return true if not empty 2974 * @return false otherwise 2975 */ 2976 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2977 union dmub_rb_out_cmd *cmd) 2978 { 2979 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 2980 uint64_t *dst = (uint64_t *)cmd; 2981 uint8_t i; 2982 2983 if (dmub_rb_empty(rb)) 2984 return false; 2985 2986 // copying data 2987 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2988 *dst++ = *src++; 2989 2990 return true; 2991 } 2992 2993 /** 2994 * @brief Removes the front entry in the ringbuffer. 2995 * 2996 * @param rb DMUB ringbuffer 2997 * @return true if the command was removed 2998 * @return false if there were no commands 2999 */ 3000 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3001 { 3002 if (dmub_rb_empty(rb)) 3003 return false; 3004 3005 rb->rptr += DMUB_RB_CMD_SIZE; 3006 3007 if (rb->rptr >= rb->capacity) 3008 rb->rptr %= rb->capacity; 3009 3010 return true; 3011 } 3012 3013 /** 3014 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3015 * 3016 * Avoids a race condition where DMCUB accesses memory while 3017 * there are still writes in flight to framebuffer. 3018 * 3019 * @param rb DMUB ringbuffer 3020 */ 3021 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3022 { 3023 uint32_t rptr = rb->rptr; 3024 uint32_t wptr = rb->wrpt; 3025 3026 while (rptr != wptr) { 3027 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3028 uint8_t i; 3029 3030 /* Don't remove this. 3031 * The contents need to actually be read from the ring buffer 3032 * for this function to be effective. 3033 */ 3034 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3035 (void)READ_ONCE(*data++); 3036 3037 rptr += DMUB_RB_CMD_SIZE; 3038 if (rptr >= rb->capacity) 3039 rptr %= rb->capacity; 3040 } 3041 } 3042 3043 /** 3044 * @brief Initializes a DMCUB ringbuffer 3045 * 3046 * @param rb DMUB ringbuffer 3047 * @param init_params initial configuration for the ringbuffer 3048 */ 3049 static inline void dmub_rb_init(struct dmub_rb *rb, 3050 struct dmub_rb_init_params *init_params) 3051 { 3052 rb->base_address = init_params->base_address; 3053 rb->capacity = init_params->capacity; 3054 rb->rptr = init_params->read_ptr; 3055 rb->wrpt = init_params->write_ptr; 3056 } 3057 3058 /** 3059 * @brief Copies output data from in/out commands into the given command. 3060 * 3061 * @param rb DMUB ringbuffer 3062 * @param cmd Command to copy data into 3063 */ 3064 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3065 union dmub_rb_cmd *cmd) 3066 { 3067 // Copy rb entry back into command 3068 uint8_t *rd_ptr = (rb->rptr == 0) ? 3069 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3070 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3071 3072 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3073 } 3074 3075 #if defined(__cplusplus) 3076 } 3077 #endif 3078 3079 //============================================================================== 3080 //</DMUB_RB>==================================================================== 3081 //============================================================================== 3082 3083 #endif /* _DMUB_CMD_H_ */ 3084