1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Define max FPO streams as 4 for now. Current implementation today 99 * only supports 1, but could be more in the future. Reduce array 100 * size to ensure the command size remains less than 64 bytes if 101 * adding new fields. 102 */ 103 #define DMUB_MAX_FPO_STREAMS 4 104 105 /* Maximum number of streams on any ASIC. */ 106 #define DMUB_MAX_STREAMS 6 107 108 /* Maximum number of planes on any ASIC. */ 109 #define DMUB_MAX_PLANES 6 110 111 /* Trace buffer offset for entry */ 112 #define TRACE_BUFFER_ENTRY_OFFSET 16 113 114 /** 115 * Maximum number of dirty rects supported by FW. 116 */ 117 #define DMUB_MAX_DIRTY_RECTS 3 118 119 /** 120 * 121 * PSR control version legacy 122 */ 123 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 124 /** 125 * PSR control version with multi edp support 126 */ 127 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 128 129 130 /** 131 * ABM control version legacy 132 */ 133 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 134 135 /** 136 * ABM control version with multi edp support 137 */ 138 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 139 140 /** 141 * Physical framebuffer address location, 64-bit. 142 */ 143 #ifndef PHYSICAL_ADDRESS_LOC 144 #define PHYSICAL_ADDRESS_LOC union large_integer 145 #endif 146 147 /** 148 * OS/FW agnostic memcpy 149 */ 150 #ifndef dmub_memcpy 151 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 152 #endif 153 154 /** 155 * OS/FW agnostic memset 156 */ 157 #ifndef dmub_memset 158 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 159 #endif 160 161 #if defined(__cplusplus) 162 extern "C" { 163 #endif 164 165 /** 166 * OS/FW agnostic udelay 167 */ 168 #ifndef dmub_udelay 169 #define dmub_udelay(microseconds) udelay(microseconds) 170 #endif 171 172 #pragma pack(push, 1) 173 /** 174 * union dmub_addr - DMUB physical/virtual 64-bit address. 175 */ 176 union dmub_addr { 177 struct { 178 uint32_t low_part; /**< Lower 32 bits */ 179 uint32_t high_part; /**< Upper 32 bits */ 180 } u; /*<< Low/high bit access */ 181 uint64_t quad_part; /*<< 64 bit address */ 182 }; 183 #pragma pack(pop) 184 185 /** 186 * Dirty rect definition. 187 */ 188 struct dmub_rect { 189 /** 190 * Dirty rect x offset. 191 */ 192 uint32_t x; 193 194 /** 195 * Dirty rect y offset. 196 */ 197 uint32_t y; 198 199 /** 200 * Dirty rect width. 201 */ 202 uint32_t width; 203 204 /** 205 * Dirty rect height. 206 */ 207 uint32_t height; 208 }; 209 210 /** 211 * Flags that can be set by driver to change some PSR behaviour. 212 */ 213 union dmub_psr_debug_flags { 214 /** 215 * Debug flags. 216 */ 217 struct { 218 /** 219 * Enable visual confirm in FW. 220 */ 221 uint32_t visual_confirm : 1; 222 223 /** 224 * Force all selective updates to bw full frame updates. 225 */ 226 uint32_t force_full_frame_update : 1; 227 228 /** 229 * Use HW Lock Mgr object to do HW locking in FW. 230 */ 231 uint32_t use_hw_lock_mgr : 1; 232 233 /** 234 * Use TPS3 signal when restore main link. 235 */ 236 uint32_t force_wakeup_by_tps3 : 1; 237 238 /** 239 * Back to back flip, therefore cannot power down PHY 240 */ 241 uint32_t back_to_back_flip : 1; 242 243 } bitfields; 244 245 /** 246 * Union for debug flags. 247 */ 248 uint32_t u32All; 249 }; 250 251 /** 252 * DMUB visual confirm color 253 */ 254 struct dmub_feature_caps { 255 /** 256 * Max PSR version supported by FW. 257 */ 258 uint8_t psr; 259 uint8_t fw_assisted_mclk_switch; 260 uint8_t reserved[6]; 261 }; 262 263 struct dmub_visual_confirm_color { 264 /** 265 * Maximum 10 bits color value 266 */ 267 uint16_t color_r_cr; 268 uint16_t color_g_y; 269 uint16_t color_b_cb; 270 uint16_t panel_inst; 271 }; 272 273 #if defined(__cplusplus) 274 } 275 #endif 276 277 //============================================================================== 278 //</DMUB_TYPES>================================================================= 279 //============================================================================== 280 //< DMUB_META>================================================================== 281 //============================================================================== 282 #pragma pack(push, 1) 283 284 /* Magic value for identifying dmub_fw_meta_info */ 285 #define DMUB_FW_META_MAGIC 0x444D5542 286 287 /* Offset from the end of the file to the dmub_fw_meta_info */ 288 #define DMUB_FW_META_OFFSET 0x24 289 290 /** 291 * struct dmub_fw_meta_info - metadata associated with fw binary 292 * 293 * NOTE: This should be considered a stable API. Fields should 294 * not be repurposed or reordered. New fields should be 295 * added instead to extend the structure. 296 * 297 * @magic_value: magic value identifying DMUB firmware meta info 298 * @fw_region_size: size of the firmware state region 299 * @trace_buffer_size: size of the tracebuffer region 300 * @fw_version: the firmware version information 301 * @dal_fw: 1 if the firmware is DAL 302 */ 303 struct dmub_fw_meta_info { 304 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 305 uint32_t fw_region_size; /**< size of the firmware state region */ 306 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 307 uint32_t fw_version; /**< the firmware version information */ 308 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 309 uint8_t reserved[3]; /**< padding bits */ 310 }; 311 312 /** 313 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 314 */ 315 union dmub_fw_meta { 316 struct dmub_fw_meta_info info; /**< metadata info */ 317 uint8_t reserved[64]; /**< padding bits */ 318 }; 319 320 #pragma pack(pop) 321 322 //============================================================================== 323 //< DMUB Trace Buffer>================================================================ 324 //============================================================================== 325 /** 326 * dmub_trace_code_t - firmware trace code, 32-bits 327 */ 328 typedef uint32_t dmub_trace_code_t; 329 330 /** 331 * struct dmcub_trace_buf_entry - Firmware trace entry 332 */ 333 struct dmcub_trace_buf_entry { 334 dmub_trace_code_t trace_code; /**< trace code for the event */ 335 uint32_t tick_count; /**< the tick count at time of trace */ 336 uint32_t param0; /**< trace defined parameter 0 */ 337 uint32_t param1; /**< trace defined parameter 1 */ 338 }; 339 340 //============================================================================== 341 //< DMUB_STATUS>================================================================ 342 //============================================================================== 343 344 /** 345 * DMCUB scratch registers can be used to determine firmware status. 346 * Current scratch register usage is as follows: 347 * 348 * SCRATCH0: FW Boot Status register 349 * SCRATCH5: LVTMA Status Register 350 * SCRATCH15: FW Boot Options register 351 */ 352 353 /** 354 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 355 */ 356 union dmub_fw_boot_status { 357 struct { 358 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 359 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 360 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 361 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 362 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 363 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 364 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 365 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 366 } bits; /**< status bits */ 367 uint32_t all; /**< 32-bit access to status bits */ 368 }; 369 370 /** 371 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 372 */ 373 enum dmub_fw_boot_status_bit { 374 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 375 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 376 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 377 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 378 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 379 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 380 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 381 }; 382 383 /* Register bit definition for SCRATCH5 */ 384 union dmub_lvtma_status { 385 struct { 386 uint32_t psp_ok : 1; 387 uint32_t edp_on : 1; 388 uint32_t reserved : 30; 389 } bits; 390 uint32_t all; 391 }; 392 393 enum dmub_lvtma_status_bit { 394 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 395 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 396 }; 397 398 /** 399 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 400 */ 401 union dmub_fw_boot_options { 402 struct { 403 uint32_t pemu_env : 1; /**< 1 if PEMU */ 404 uint32_t fpga_env : 1; /**< 1 if FPGA */ 405 uint32_t optimized_init : 1; /**< 1 if optimized init */ 406 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 407 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 408 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 409 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 410 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 411 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 412 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 413 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 414 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 415 uint32_t power_optimization: 1; 416 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 417 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 418 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 419 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 420 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 421 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 422 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 423 uint32_t reserved : 13; /**< reserved */ 424 } bits; /**< boot bits */ 425 uint32_t all; /**< 32-bit access to bits */ 426 }; 427 428 enum dmub_fw_boot_options_bit { 429 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 430 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 431 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 432 }; 433 434 //============================================================================== 435 //</DMUB_STATUS>================================================================ 436 //============================================================================== 437 //< DMUB_VBIOS>================================================================= 438 //============================================================================== 439 440 /* 441 * enum dmub_cmd_vbios_type - VBIOS commands. 442 * 443 * Command IDs should be treated as stable ABI. 444 * Do not reuse or modify IDs. 445 */ 446 enum dmub_cmd_vbios_type { 447 /** 448 * Configures the DIG encoder. 449 */ 450 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 451 /** 452 * Controls the PHY. 453 */ 454 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 455 /** 456 * Sets the pixel clock/symbol clock. 457 */ 458 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 459 /** 460 * Enables or disables power gating. 461 */ 462 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 463 /** 464 * Controls embedded panels. 465 */ 466 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 467 /** 468 * Query DP alt status on a transmitter. 469 */ 470 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 471 /** 472 * Controls domain power gating 473 */ 474 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 475 }; 476 477 //============================================================================== 478 //</DMUB_VBIOS>================================================================= 479 //============================================================================== 480 //< DMUB_GPINT>================================================================= 481 //============================================================================== 482 483 /** 484 * The shifts and masks below may alternatively be used to format and read 485 * the command register bits. 486 */ 487 488 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 489 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 490 491 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 492 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 493 494 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 495 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 496 497 /** 498 * Command responses. 499 */ 500 501 /** 502 * Return response for DMUB_GPINT__STOP_FW command. 503 */ 504 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 505 506 /** 507 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 508 */ 509 union dmub_gpint_data_register { 510 struct { 511 uint32_t param : 16; /**< 16-bit parameter */ 512 uint32_t command_code : 12; /**< GPINT command */ 513 uint32_t status : 4; /**< Command status bit */ 514 } bits; /**< GPINT bit access */ 515 uint32_t all; /**< GPINT 32-bit access */ 516 }; 517 518 /* 519 * enum dmub_gpint_command - GPINT command to DMCUB FW 520 * 521 * Command IDs should be treated as stable ABI. 522 * Do not reuse or modify IDs. 523 */ 524 enum dmub_gpint_command { 525 /** 526 * Invalid command, ignored. 527 */ 528 DMUB_GPINT__INVALID_COMMAND = 0, 529 /** 530 * DESC: Queries the firmware version. 531 * RETURN: Firmware version. 532 */ 533 DMUB_GPINT__GET_FW_VERSION = 1, 534 /** 535 * DESC: Halts the firmware. 536 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 537 */ 538 DMUB_GPINT__STOP_FW = 2, 539 /** 540 * DESC: Get PSR state from FW. 541 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 542 */ 543 DMUB_GPINT__GET_PSR_STATE = 7, 544 /** 545 * DESC: Notifies DMCUB of the currently active streams. 546 * ARGS: Stream mask, 1 bit per active stream index. 547 */ 548 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 549 /** 550 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 551 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 552 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 553 * RETURN: PSR residency in milli-percent. 554 */ 555 DMUB_GPINT__PSR_RESIDENCY = 9, 556 557 /** 558 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 559 */ 560 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 561 }; 562 563 /** 564 * INBOX0 generic command definition 565 */ 566 union dmub_inbox0_cmd_common { 567 struct { 568 uint32_t command_code: 8; /**< INBOX0 command code */ 569 uint32_t param: 24; /**< 24-bit parameter */ 570 } bits; 571 uint32_t all; 572 }; 573 574 /** 575 * INBOX0 hw_lock command definition 576 */ 577 union dmub_inbox0_cmd_lock_hw { 578 struct { 579 uint32_t command_code: 8; 580 581 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 582 uint32_t hw_lock_client: 2; 583 584 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 585 uint32_t otg_inst: 3; 586 uint32_t opp_inst: 3; 587 uint32_t dig_inst: 3; 588 589 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 590 uint32_t lock_pipe: 1; 591 uint32_t lock_cursor: 1; 592 uint32_t lock_dig: 1; 593 uint32_t triple_buffer_lock: 1; 594 595 uint32_t lock: 1; /**< Lock */ 596 uint32_t should_release: 1; /**< Release */ 597 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 598 } bits; 599 uint32_t all; 600 }; 601 602 union dmub_inbox0_data_register { 603 union dmub_inbox0_cmd_common inbox0_cmd_common; 604 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 605 }; 606 607 enum dmub_inbox0_command { 608 /** 609 * DESC: Invalid command, ignored. 610 */ 611 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 612 /** 613 * DESC: Notification to acquire/release HW lock 614 * ARGS: 615 */ 616 DMUB_INBOX0_CMD__HW_LOCK = 1, 617 }; 618 //============================================================================== 619 //</DMUB_GPINT>================================================================= 620 //============================================================================== 621 //< DMUB_CMD>=================================================================== 622 //============================================================================== 623 624 /** 625 * Size in bytes of each DMUB command. 626 */ 627 #define DMUB_RB_CMD_SIZE 64 628 629 /** 630 * Maximum number of items in the DMUB ringbuffer. 631 */ 632 #define DMUB_RB_MAX_ENTRY 128 633 634 /** 635 * Ringbuffer size in bytes. 636 */ 637 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 638 639 /** 640 * REG_SET mask for reg offload. 641 */ 642 #define REG_SET_MASK 0xFFFF 643 644 /* 645 * enum dmub_cmd_type - DMUB inbox command. 646 * 647 * Command IDs should be treated as stable ABI. 648 * Do not reuse or modify IDs. 649 */ 650 enum dmub_cmd_type { 651 /** 652 * Invalid command. 653 */ 654 DMUB_CMD__NULL = 0, 655 /** 656 * Read modify write register sequence offload. 657 */ 658 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 659 /** 660 * Field update register sequence offload. 661 */ 662 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 663 /** 664 * Burst write sequence offload. 665 */ 666 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 667 /** 668 * Reg wait sequence offload. 669 */ 670 DMUB_CMD__REG_REG_WAIT = 4, 671 /** 672 * Workaround to avoid HUBP underflow during NV12 playback. 673 */ 674 DMUB_CMD__PLAT_54186_WA = 5, 675 /** 676 * Command type used to query FW feature caps. 677 */ 678 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 679 /** 680 * Command type used to get visual confirm color. 681 */ 682 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 683 /** 684 * Command type used for all PSR commands. 685 */ 686 DMUB_CMD__PSR = 64, 687 /** 688 * Command type used for all MALL commands. 689 */ 690 DMUB_CMD__MALL = 65, 691 /** 692 * Command type used for all ABM commands. 693 */ 694 DMUB_CMD__ABM = 66, 695 /** 696 * Command type used to update dirty rects in FW. 697 */ 698 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 699 /** 700 * Command type used to update cursor info in FW. 701 */ 702 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 703 /** 704 * Command type used for HW locking in FW. 705 */ 706 DMUB_CMD__HW_LOCK = 69, 707 /** 708 * Command type used to access DP AUX. 709 */ 710 DMUB_CMD__DP_AUX_ACCESS = 70, 711 /** 712 * Command type used for OUTBOX1 notification enable 713 */ 714 DMUB_CMD__OUTBOX1_ENABLE = 71, 715 716 /** 717 * Command type used for all idle optimization commands. 718 */ 719 DMUB_CMD__IDLE_OPT = 72, 720 /** 721 * Command type used for all clock manager commands. 722 */ 723 DMUB_CMD__CLK_MGR = 73, 724 /** 725 * Command type used for all panel control commands. 726 */ 727 DMUB_CMD__PANEL_CNTL = 74, 728 /** 729 * Command type used for <TODO:description> 730 */ 731 DMUB_CMD__CAB_FOR_SS = 75, 732 733 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 734 735 /** 736 * Command type used for interfacing with DPIA. 737 */ 738 DMUB_CMD__DPIA = 77, 739 /** 740 * Command type used for EDID CEA parsing 741 */ 742 DMUB_CMD__EDID_CEA = 79, 743 /** 744 * Command type used for getting usbc cable ID 745 */ 746 DMUB_CMD_GET_USBC_CABLE_ID = 81, 747 /** 748 * Command type used to query HPD state. 749 */ 750 DMUB_CMD__QUERY_HPD_STATE = 82, 751 /** 752 * Command type used for all VBIOS interface commands. 753 */ 754 755 /** 756 * Command type used for all SECURE_DISPLAY commands. 757 */ 758 DMUB_CMD__SECURE_DISPLAY = 85, 759 760 /** 761 * Command type used to set DPIA HPD interrupt state 762 */ 763 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 764 765 DMUB_CMD__VBIOS = 128, 766 }; 767 768 /** 769 * enum dmub_out_cmd_type - DMUB outbox commands. 770 */ 771 enum dmub_out_cmd_type { 772 /** 773 * Invalid outbox command, ignored. 774 */ 775 DMUB_OUT_CMD__NULL = 0, 776 /** 777 * Command type used for DP AUX Reply data notification 778 */ 779 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 780 /** 781 * Command type used for DP HPD event notification 782 */ 783 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 784 /** 785 * Command type used for SET_CONFIG Reply notification 786 */ 787 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 788 /** 789 * Command type used for USB4 DPIA notification 790 */ 791 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 792 }; 793 794 /* DMUB_CMD__DPIA command sub-types. */ 795 enum dmub_cmd_dpia_type { 796 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 797 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 798 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 799 }; 800 801 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 802 enum dmub_cmd_dpia_notification_type { 803 DPIA_NOTIFY__BW_ALLOCATION = 0, 804 }; 805 806 #pragma pack(push, 1) 807 808 /** 809 * struct dmub_cmd_header - Common command header fields. 810 */ 811 struct dmub_cmd_header { 812 unsigned int type : 8; /**< command type */ 813 unsigned int sub_type : 8; /**< command sub type */ 814 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 815 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 816 unsigned int reserved0 : 6; /**< reserved bits */ 817 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 818 unsigned int reserved1 : 2; /**< reserved bits */ 819 }; 820 821 /* 822 * struct dmub_cmd_read_modify_write_sequence - Read modify write 823 * 824 * 60 payload bytes can hold up to 5 sets of read modify writes, 825 * each take 3 dwords. 826 * 827 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 828 * 829 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 830 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 831 */ 832 struct dmub_cmd_read_modify_write_sequence { 833 uint32_t addr; /**< register address */ 834 uint32_t modify_mask; /**< modify mask */ 835 uint32_t modify_value; /**< modify value */ 836 }; 837 838 /** 839 * Maximum number of ops in read modify write sequence. 840 */ 841 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 842 843 /** 844 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 845 */ 846 struct dmub_rb_cmd_read_modify_write { 847 struct dmub_cmd_header header; /**< command header */ 848 /** 849 * Read modify write sequence. 850 */ 851 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 852 }; 853 854 /* 855 * Update a register with specified masks and values sequeunce 856 * 857 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 858 * 859 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 860 * 861 * 862 * USE CASE: 863 * 1. auto-increment register where additional read would update pointer and produce wrong result 864 * 2. toggle a bit without read in the middle 865 */ 866 867 struct dmub_cmd_reg_field_update_sequence { 868 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 869 uint32_t modify_value; /**< value to update with */ 870 }; 871 872 /** 873 * Maximum number of ops in field update sequence. 874 */ 875 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 876 877 /** 878 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 879 */ 880 struct dmub_rb_cmd_reg_field_update_sequence { 881 struct dmub_cmd_header header; /**< command header */ 882 uint32_t addr; /**< register address */ 883 /** 884 * Field update sequence. 885 */ 886 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 887 }; 888 889 890 /** 891 * Maximum number of burst write values. 892 */ 893 #define DMUB_BURST_WRITE_VALUES__MAX 14 894 895 /* 896 * struct dmub_rb_cmd_burst_write - Burst write 897 * 898 * support use case such as writing out LUTs. 899 * 900 * 60 payload bytes can hold up to 14 values to write to given address 901 * 902 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 903 */ 904 struct dmub_rb_cmd_burst_write { 905 struct dmub_cmd_header header; /**< command header */ 906 uint32_t addr; /**< register start address */ 907 /** 908 * Burst write register values. 909 */ 910 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 911 }; 912 913 /** 914 * struct dmub_rb_cmd_common - Common command header 915 */ 916 struct dmub_rb_cmd_common { 917 struct dmub_cmd_header header; /**< command header */ 918 /** 919 * Padding to RB_CMD_SIZE 920 */ 921 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 922 }; 923 924 /** 925 * struct dmub_cmd_reg_wait_data - Register wait data 926 */ 927 struct dmub_cmd_reg_wait_data { 928 uint32_t addr; /**< Register address */ 929 uint32_t mask; /**< Mask for register bits */ 930 uint32_t condition_field_value; /**< Value to wait for */ 931 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 932 }; 933 934 /** 935 * struct dmub_rb_cmd_reg_wait - Register wait command 936 */ 937 struct dmub_rb_cmd_reg_wait { 938 struct dmub_cmd_header header; /**< Command header */ 939 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 940 }; 941 942 /** 943 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 944 * 945 * Reprograms surface parameters to avoid underflow. 946 */ 947 struct dmub_cmd_PLAT_54186_wa { 948 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 949 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 950 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 951 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 952 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 953 struct { 954 uint8_t hubp_inst : 4; /**< HUBP instance */ 955 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 956 uint8_t immediate :1; /**< Immediate flip */ 957 uint8_t vmid : 4; /**< VMID */ 958 uint8_t grph_stereo : 1; /**< 1 if stereo */ 959 uint32_t reserved : 21; /**< Reserved */ 960 } flip_params; /**< Pageflip parameters */ 961 uint32_t reserved[9]; /**< Reserved bits */ 962 }; 963 964 /** 965 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 966 */ 967 struct dmub_rb_cmd_PLAT_54186_wa { 968 struct dmub_cmd_header header; /**< Command header */ 969 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 970 }; 971 972 /** 973 * struct dmub_rb_cmd_mall - MALL command data. 974 */ 975 struct dmub_rb_cmd_mall { 976 struct dmub_cmd_header header; /**< Common command header */ 977 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 978 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 979 uint32_t tmr_delay; /**< Timer delay */ 980 uint32_t tmr_scale; /**< Timer scale */ 981 uint16_t cursor_width; /**< Cursor width in pixels */ 982 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 983 uint16_t cursor_height; /**< Cursor height in pixels */ 984 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 985 uint8_t debug_bits; /**< Debug bits */ 986 987 uint8_t reserved1; /**< Reserved bits */ 988 uint8_t reserved2; /**< Reserved bits */ 989 }; 990 991 /** 992 * enum dmub_cmd_cab_type - TODO: 993 */ 994 enum dmub_cmd_cab_type { 995 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 996 DMUB_CMD__CAB_NO_DCN_REQ = 1, 997 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 998 }; 999 1000 /** 1001 * struct dmub_rb_cmd_cab_for_ss - TODO: 1002 */ 1003 struct dmub_rb_cmd_cab_for_ss { 1004 struct dmub_cmd_header header; 1005 uint8_t cab_alloc_ways; /* total number of ways */ 1006 uint8_t debug_bits; /* debug bits */ 1007 }; 1008 1009 enum mclk_switch_mode { 1010 NONE = 0, 1011 FPO = 1, 1012 SUBVP = 2, 1013 VBLANK = 3, 1014 }; 1015 1016 /* Per pipe struct which stores the MCLK switch mode 1017 * data to be sent to DMUB. 1018 * Named "v2" for now -- once FPO and SUBVP are fully merged 1019 * the type name can be updated 1020 */ 1021 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1022 union { 1023 struct { 1024 uint32_t pix_clk_100hz; 1025 uint16_t main_vblank_start; 1026 uint16_t main_vblank_end; 1027 uint16_t mall_region_lines; 1028 uint16_t prefetch_lines; 1029 uint16_t prefetch_to_mall_start_lines; 1030 uint16_t processing_delay_lines; 1031 uint16_t htotal; // required to calculate line time for multi-display cases 1032 uint16_t vtotal; 1033 uint8_t main_pipe_index; 1034 uint8_t phantom_pipe_index; 1035 /* Since the microschedule is calculated in terms of OTG lines, 1036 * include any scaling factors to make sure when we get accurate 1037 * conversion when programming MALL_START_LINE (which is in terms 1038 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1039 * is 1/2 (numerator = 1, denominator = 2). 1040 */ 1041 uint8_t scale_factor_numerator; 1042 uint8_t scale_factor_denominator; 1043 uint8_t is_drr; 1044 uint8_t main_split_pipe_index; 1045 uint8_t phantom_split_pipe_index; 1046 } subvp_data; 1047 1048 struct { 1049 uint32_t pix_clk_100hz; 1050 uint16_t vblank_start; 1051 uint16_t vblank_end; 1052 uint16_t vstartup_start; 1053 uint16_t vtotal; 1054 uint16_t htotal; 1055 uint8_t vblank_pipe_index; 1056 uint8_t padding[1]; 1057 struct { 1058 uint8_t drr_in_use; 1059 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1060 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1061 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1062 uint8_t use_ramping; // Use ramping or not 1063 uint8_t drr_vblank_start_margin; 1064 } drr_info; // DRR considered as part of SubVP + VBLANK case 1065 } vblank_data; 1066 } pipe_config; 1067 1068 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1069 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1070 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1071 */ 1072 uint8_t mode; // enum mclk_switch_mode 1073 }; 1074 1075 /** 1076 * Config data for Sub-VP and FPO 1077 * Named "v2" for now -- once FPO and SUBVP are fully merged 1078 * the type name can be updated 1079 */ 1080 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1081 uint16_t watermark_a_cache; 1082 uint8_t vertical_int_margin_us; 1083 uint8_t pstate_allow_width_us; 1084 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1085 }; 1086 1087 /** 1088 * DMUB rb command definition for Sub-VP and FPO 1089 * Named "v2" for now -- once FPO and SUBVP are fully merged 1090 * the type name can be updated 1091 */ 1092 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1093 struct dmub_cmd_header header; 1094 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1095 }; 1096 1097 /** 1098 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1099 */ 1100 enum dmub_cmd_idle_opt_type { 1101 /** 1102 * DCN hardware restore. 1103 */ 1104 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1105 1106 /** 1107 * DCN hardware save. 1108 */ 1109 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1110 1111 /** 1112 * DCN hardware notify idle. 1113 */ 1114 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1115 }; 1116 1117 /** 1118 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1119 */ 1120 struct dmub_rb_cmd_idle_opt_dcn_restore { 1121 struct dmub_cmd_header header; /**< header */ 1122 }; 1123 1124 /** 1125 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1126 */ 1127 struct dmub_dcn_notify_idle_cntl_data { 1128 uint8_t driver_idle; 1129 uint8_t pad[1]; 1130 }; 1131 1132 /** 1133 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1134 */ 1135 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1136 struct dmub_cmd_header header; /**< header */ 1137 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1138 }; 1139 1140 /** 1141 * struct dmub_clocks - Clock update notification. 1142 */ 1143 struct dmub_clocks { 1144 uint32_t dispclk_khz; /**< dispclk kHz */ 1145 uint32_t dppclk_khz; /**< dppclk kHz */ 1146 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1147 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1148 }; 1149 1150 /** 1151 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1152 */ 1153 enum dmub_cmd_clk_mgr_type { 1154 /** 1155 * Notify DMCUB of clock update. 1156 */ 1157 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1158 }; 1159 1160 /** 1161 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1162 */ 1163 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1164 struct dmub_cmd_header header; /**< header */ 1165 struct dmub_clocks clocks; /**< clock data */ 1166 }; 1167 1168 /** 1169 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1170 */ 1171 struct dmub_cmd_digx_encoder_control_data { 1172 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1173 }; 1174 1175 /** 1176 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1177 */ 1178 struct dmub_rb_cmd_digx_encoder_control { 1179 struct dmub_cmd_header header; /**< header */ 1180 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1181 }; 1182 1183 /** 1184 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1185 */ 1186 struct dmub_cmd_set_pixel_clock_data { 1187 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1188 }; 1189 1190 /** 1191 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1192 */ 1193 struct dmub_rb_cmd_set_pixel_clock { 1194 struct dmub_cmd_header header; /**< header */ 1195 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1196 }; 1197 1198 /** 1199 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1200 */ 1201 struct dmub_cmd_enable_disp_power_gating_data { 1202 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1203 }; 1204 1205 /** 1206 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1207 */ 1208 struct dmub_rb_cmd_enable_disp_power_gating { 1209 struct dmub_cmd_header header; /**< header */ 1210 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1211 }; 1212 1213 /** 1214 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1215 */ 1216 struct dmub_dig_transmitter_control_data_v1_7 { 1217 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1218 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1219 union { 1220 uint8_t digmode; /**< enum atom_encode_mode_def */ 1221 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1222 } mode_laneset; 1223 uint8_t lanenum; /**< Number of lanes */ 1224 union { 1225 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1226 } symclk_units; 1227 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1228 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1229 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1230 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1231 uint8_t reserved1; /**< For future use */ 1232 uint8_t reserved2[3]; /**< For future use */ 1233 uint32_t reserved3[11]; /**< For future use */ 1234 }; 1235 1236 /** 1237 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1238 */ 1239 union dmub_cmd_dig1_transmitter_control_data { 1240 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1241 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1242 }; 1243 1244 /** 1245 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1246 */ 1247 struct dmub_rb_cmd_dig1_transmitter_control { 1248 struct dmub_cmd_header header; /**< header */ 1249 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1250 }; 1251 1252 /** 1253 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1254 */ 1255 struct dmub_rb_cmd_domain_control_data { 1256 uint8_t inst : 6; /**< DOMAIN instance to control */ 1257 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1258 uint8_t reserved[3]; /**< Reserved for future use */ 1259 }; 1260 1261 /** 1262 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1263 */ 1264 struct dmub_rb_cmd_domain_control { 1265 struct dmub_cmd_header header; /**< header */ 1266 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1267 }; 1268 1269 /** 1270 * DPIA tunnel command parameters. 1271 */ 1272 struct dmub_cmd_dig_dpia_control_data { 1273 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1274 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1275 union { 1276 uint8_t digmode; /** enum atom_encode_mode_def */ 1277 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1278 } mode_laneset; 1279 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1280 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1281 uint8_t hpdsel; /** =0: HPD is not assigned */ 1282 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1283 uint8_t dpia_id; /** Index of DPIA */ 1284 uint8_t fec_rdy : 1; 1285 uint8_t reserved : 7; 1286 uint32_t reserved1; 1287 }; 1288 1289 /** 1290 * DMUB command for DPIA tunnel control. 1291 */ 1292 struct dmub_rb_cmd_dig1_dpia_control { 1293 struct dmub_cmd_header header; 1294 struct dmub_cmd_dig_dpia_control_data dpia_control; 1295 }; 1296 1297 /** 1298 * SET_CONFIG Command Payload 1299 */ 1300 struct set_config_cmd_payload { 1301 uint8_t msg_type; /* set config message type */ 1302 uint8_t msg_data; /* set config message data */ 1303 }; 1304 1305 /** 1306 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1307 */ 1308 struct dmub_cmd_set_config_control_data { 1309 struct set_config_cmd_payload cmd_pkt; 1310 uint8_t instance; /* DPIA instance */ 1311 uint8_t immed_status; /* Immediate status returned in case of error */ 1312 }; 1313 1314 /** 1315 * DMUB command structure for SET_CONFIG command. 1316 */ 1317 struct dmub_rb_cmd_set_config_access { 1318 struct dmub_cmd_header header; /* header */ 1319 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1320 }; 1321 1322 /** 1323 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1324 */ 1325 struct dmub_cmd_mst_alloc_slots_control_data { 1326 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1327 uint8_t instance; /* DPIA instance */ 1328 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1329 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1330 }; 1331 1332 /** 1333 * DMUB command structure for SET_ command. 1334 */ 1335 struct dmub_rb_cmd_set_mst_alloc_slots { 1336 struct dmub_cmd_header header; /* header */ 1337 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1338 }; 1339 1340 /** 1341 * DMUB command structure for DPIA HPD int enable control. 1342 */ 1343 struct dmub_rb_cmd_dpia_hpd_int_enable { 1344 struct dmub_cmd_header header; /* header */ 1345 uint32_t enable; /* dpia hpd interrupt enable */ 1346 }; 1347 1348 /** 1349 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1350 */ 1351 struct dmub_rb_cmd_dpphy_init { 1352 struct dmub_cmd_header header; /**< header */ 1353 uint8_t reserved[60]; /**< reserved bits */ 1354 }; 1355 1356 /** 1357 * enum dp_aux_request_action - DP AUX request command listing. 1358 * 1359 * 4 AUX request command bits are shifted to high nibble. 1360 */ 1361 enum dp_aux_request_action { 1362 /** I2C-over-AUX write request */ 1363 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1364 /** I2C-over-AUX read request */ 1365 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1366 /** I2C-over-AUX write status request */ 1367 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1368 /** I2C-over-AUX write request with MOT=1 */ 1369 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1370 /** I2C-over-AUX read request with MOT=1 */ 1371 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1372 /** I2C-over-AUX write status request with MOT=1 */ 1373 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1374 /** Native AUX write request */ 1375 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1376 /** Native AUX read request */ 1377 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1378 }; 1379 1380 /** 1381 * enum aux_return_code_type - DP AUX process return code listing. 1382 */ 1383 enum aux_return_code_type { 1384 /** AUX process succeeded */ 1385 AUX_RET_SUCCESS = 0, 1386 /** AUX process failed with unknown reason */ 1387 AUX_RET_ERROR_UNKNOWN, 1388 /** AUX process completed with invalid reply */ 1389 AUX_RET_ERROR_INVALID_REPLY, 1390 /** AUX process timed out */ 1391 AUX_RET_ERROR_TIMEOUT, 1392 /** HPD was low during AUX process */ 1393 AUX_RET_ERROR_HPD_DISCON, 1394 /** Failed to acquire AUX engine */ 1395 AUX_RET_ERROR_ENGINE_ACQUIRE, 1396 /** AUX request not supported */ 1397 AUX_RET_ERROR_INVALID_OPERATION, 1398 /** AUX process not available */ 1399 AUX_RET_ERROR_PROTOCOL_ERROR, 1400 }; 1401 1402 /** 1403 * enum aux_channel_type - DP AUX channel type listing. 1404 */ 1405 enum aux_channel_type { 1406 /** AUX thru Legacy DP AUX */ 1407 AUX_CHANNEL_LEGACY_DDC, 1408 /** AUX thru DPIA DP tunneling */ 1409 AUX_CHANNEL_DPIA 1410 }; 1411 1412 /** 1413 * struct aux_transaction_parameters - DP AUX request transaction data 1414 */ 1415 struct aux_transaction_parameters { 1416 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1417 uint8_t action; /**< enum dp_aux_request_action */ 1418 uint8_t length; /**< DP AUX request data length */ 1419 uint8_t reserved; /**< For future use */ 1420 uint32_t address; /**< DP AUX address */ 1421 uint8_t data[16]; /**< DP AUX write data */ 1422 }; 1423 1424 /** 1425 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1426 */ 1427 struct dmub_cmd_dp_aux_control_data { 1428 uint8_t instance; /**< AUX instance or DPIA instance */ 1429 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1430 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1431 uint8_t reserved0; /**< For future use */ 1432 uint16_t timeout; /**< timeout time in us */ 1433 uint16_t reserved1; /**< For future use */ 1434 enum aux_channel_type type; /**< enum aux_channel_type */ 1435 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1436 }; 1437 1438 /** 1439 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1440 */ 1441 struct dmub_rb_cmd_dp_aux_access { 1442 /** 1443 * Command header. 1444 */ 1445 struct dmub_cmd_header header; 1446 /** 1447 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1448 */ 1449 struct dmub_cmd_dp_aux_control_data aux_control; 1450 }; 1451 1452 /** 1453 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1454 */ 1455 struct dmub_rb_cmd_outbox1_enable { 1456 /** 1457 * Command header. 1458 */ 1459 struct dmub_cmd_header header; 1460 /** 1461 * enable: 0x0 -> disable outbox1 notification (default value) 1462 * 0x1 -> enable outbox1 notification 1463 */ 1464 uint32_t enable; 1465 }; 1466 1467 /* DP AUX Reply command - OutBox Cmd */ 1468 /** 1469 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1470 */ 1471 struct aux_reply_data { 1472 /** 1473 * Aux cmd 1474 */ 1475 uint8_t command; 1476 /** 1477 * Aux reply data length (max: 16 bytes) 1478 */ 1479 uint8_t length; 1480 /** 1481 * Alignment only 1482 */ 1483 uint8_t pad[2]; 1484 /** 1485 * Aux reply data 1486 */ 1487 uint8_t data[16]; 1488 }; 1489 1490 /** 1491 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1492 */ 1493 struct aux_reply_control_data { 1494 /** 1495 * Reserved for future use 1496 */ 1497 uint32_t handle; 1498 /** 1499 * Aux Instance 1500 */ 1501 uint8_t instance; 1502 /** 1503 * Aux transaction result: definition in enum aux_return_code_type 1504 */ 1505 uint8_t result; 1506 /** 1507 * Alignment only 1508 */ 1509 uint16_t pad; 1510 }; 1511 1512 /** 1513 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1514 */ 1515 struct dmub_rb_cmd_dp_aux_reply { 1516 /** 1517 * Command header. 1518 */ 1519 struct dmub_cmd_header header; 1520 /** 1521 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1522 */ 1523 struct aux_reply_control_data control; 1524 /** 1525 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1526 */ 1527 struct aux_reply_data reply_data; 1528 }; 1529 1530 /* DP HPD Notify command - OutBox Cmd */ 1531 /** 1532 * DP HPD Type 1533 */ 1534 enum dp_hpd_type { 1535 /** 1536 * Normal DP HPD 1537 */ 1538 DP_HPD = 0, 1539 /** 1540 * DP HPD short pulse 1541 */ 1542 DP_IRQ 1543 }; 1544 1545 /** 1546 * DP HPD Status 1547 */ 1548 enum dp_hpd_status { 1549 /** 1550 * DP_HPD status low 1551 */ 1552 DP_HPD_UNPLUG = 0, 1553 /** 1554 * DP_HPD status high 1555 */ 1556 DP_HPD_PLUG 1557 }; 1558 1559 /** 1560 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1561 */ 1562 struct dp_hpd_data { 1563 /** 1564 * DP HPD instance 1565 */ 1566 uint8_t instance; 1567 /** 1568 * HPD type 1569 */ 1570 uint8_t hpd_type; 1571 /** 1572 * HPD status: only for type: DP_HPD to indicate status 1573 */ 1574 uint8_t hpd_status; 1575 /** 1576 * Alignment only 1577 */ 1578 uint8_t pad; 1579 }; 1580 1581 /** 1582 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1583 */ 1584 struct dmub_rb_cmd_dp_hpd_notify { 1585 /** 1586 * Command header. 1587 */ 1588 struct dmub_cmd_header header; 1589 /** 1590 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1591 */ 1592 struct dp_hpd_data hpd_data; 1593 }; 1594 1595 /** 1596 * Definition of a SET_CONFIG reply from DPOA. 1597 */ 1598 enum set_config_status { 1599 SET_CONFIG_PENDING = 0, 1600 SET_CONFIG_ACK_RECEIVED, 1601 SET_CONFIG_RX_TIMEOUT, 1602 SET_CONFIG_UNKNOWN_ERROR, 1603 }; 1604 1605 /** 1606 * Definition of a set_config reply 1607 */ 1608 struct set_config_reply_control_data { 1609 uint8_t instance; /* DPIA Instance */ 1610 uint8_t status; /* Set Config reply */ 1611 uint16_t pad; /* Alignment */ 1612 }; 1613 1614 /** 1615 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1616 */ 1617 struct dmub_rb_cmd_dp_set_config_reply { 1618 struct dmub_cmd_header header; 1619 struct set_config_reply_control_data set_config_reply_control; 1620 }; 1621 1622 /** 1623 * Definition of a DPIA notification header 1624 */ 1625 struct dpia_notification_header { 1626 uint8_t instance; /**< DPIA Instance */ 1627 uint8_t reserved[3]; 1628 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 1629 }; 1630 1631 /** 1632 * Definition of the common data struct of DPIA notification 1633 */ 1634 struct dpia_notification_common { 1635 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 1636 - sizeof(struct dpia_notification_header)]; 1637 }; 1638 1639 /** 1640 * Definition of a DPIA notification data 1641 */ 1642 struct dpia_bw_allocation_notify_data { 1643 union { 1644 struct { 1645 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 1646 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 1647 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 1648 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 1649 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 1650 uint16_t reserved: 11; /**< Reserved */ 1651 } bits; 1652 1653 uint16_t flags; 1654 }; 1655 1656 uint8_t cm_id; /**< CM ID */ 1657 uint8_t group_id; /**< Group ID */ 1658 uint8_t granularity; /**< BW Allocation Granularity */ 1659 uint8_t estimated_bw; /**< Estimated_BW */ 1660 uint8_t allocated_bw; /**< Allocated_BW */ 1661 uint8_t reserved; 1662 }; 1663 1664 /** 1665 * union dpia_notify_data_type - DPIA Notification in Outbox command 1666 */ 1667 union dpia_notification_data { 1668 /** 1669 * DPIA Notification for common data struct 1670 */ 1671 struct dpia_notification_common common_data; 1672 1673 /** 1674 * DPIA Notification for DP BW Allocation support 1675 */ 1676 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 1677 }; 1678 1679 /** 1680 * Definition of a DPIA notification payload 1681 */ 1682 struct dpia_notification_payload { 1683 struct dpia_notification_header header; 1684 union dpia_notification_data data; /**< DPIA notification payload data */ 1685 }; 1686 1687 /** 1688 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 1689 */ 1690 struct dmub_rb_cmd_dpia_notification { 1691 struct dmub_cmd_header header; /**< DPIA notification header */ 1692 struct dpia_notification_payload payload; /**< DPIA notification payload */ 1693 }; 1694 1695 /** 1696 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1697 */ 1698 struct dmub_cmd_hpd_state_query_data { 1699 uint8_t instance; /**< HPD instance or DPIA instance */ 1700 uint8_t result; /**< For returning HPD state */ 1701 uint16_t pad; /** < Alignment */ 1702 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1703 enum aux_return_code_type status; /**< for returning the status of command */ 1704 }; 1705 1706 /** 1707 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1708 */ 1709 struct dmub_rb_cmd_query_hpd_state { 1710 /** 1711 * Command header. 1712 */ 1713 struct dmub_cmd_header header; 1714 /** 1715 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1716 */ 1717 struct dmub_cmd_hpd_state_query_data data; 1718 }; 1719 1720 /* 1721 * Command IDs should be treated as stable ABI. 1722 * Do not reuse or modify IDs. 1723 */ 1724 1725 /** 1726 * PSR command sub-types. 1727 */ 1728 enum dmub_cmd_psr_type { 1729 /** 1730 * Set PSR version support. 1731 */ 1732 DMUB_CMD__PSR_SET_VERSION = 0, 1733 /** 1734 * Copy driver-calculated parameters to PSR state. 1735 */ 1736 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1737 /** 1738 * Enable PSR. 1739 */ 1740 DMUB_CMD__PSR_ENABLE = 2, 1741 1742 /** 1743 * Disable PSR. 1744 */ 1745 DMUB_CMD__PSR_DISABLE = 3, 1746 1747 /** 1748 * Set PSR level. 1749 * PSR level is a 16-bit value dicated by driver that 1750 * will enable/disable different functionality. 1751 */ 1752 DMUB_CMD__PSR_SET_LEVEL = 4, 1753 1754 /** 1755 * Forces PSR enabled until an explicit PSR disable call. 1756 */ 1757 DMUB_CMD__PSR_FORCE_STATIC = 5, 1758 /** 1759 * Set vtotal in psr active for FreeSync PSR. 1760 */ 1761 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1762 /** 1763 * Set PSR power option 1764 */ 1765 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1766 }; 1767 1768 enum dmub_cmd_fams_type { 1769 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1770 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1771 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1772 /** 1773 * For SubVP set manual trigger in FW because it 1774 * triggers DRR_UPDATE_PENDING which SubVP relies 1775 * on (for any SubVP cases that use a DRR display) 1776 */ 1777 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1778 }; 1779 1780 /** 1781 * PSR versions. 1782 */ 1783 enum psr_version { 1784 /** 1785 * PSR version 1. 1786 */ 1787 PSR_VERSION_1 = 0, 1788 /** 1789 * Freesync PSR SU. 1790 */ 1791 PSR_VERSION_SU_1 = 1, 1792 /** 1793 * PSR not supported. 1794 */ 1795 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1796 }; 1797 1798 /** 1799 * enum dmub_cmd_mall_type - MALL commands 1800 */ 1801 enum dmub_cmd_mall_type { 1802 /** 1803 * Allows display refresh from MALL. 1804 */ 1805 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1806 /** 1807 * Disallows display refresh from MALL. 1808 */ 1809 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1810 /** 1811 * Cursor copy for MALL. 1812 */ 1813 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1814 /** 1815 * Controls DF requests. 1816 */ 1817 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1818 }; 1819 1820 /** 1821 * PHY Link rate for DP. 1822 */ 1823 enum phy_link_rate { 1824 /** 1825 * not supported. 1826 */ 1827 PHY_RATE_UNKNOWN = 0, 1828 /** 1829 * Rate_1 (RBR) - 1.62 Gbps/Lane 1830 */ 1831 PHY_RATE_162 = 1, 1832 /** 1833 * Rate_2 - 2.16 Gbps/Lane 1834 */ 1835 PHY_RATE_216 = 2, 1836 /** 1837 * Rate_3 - 2.43 Gbps/Lane 1838 */ 1839 PHY_RATE_243 = 3, 1840 /** 1841 * Rate_4 (HBR) - 2.70 Gbps/Lane 1842 */ 1843 PHY_RATE_270 = 4, 1844 /** 1845 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1846 */ 1847 PHY_RATE_324 = 5, 1848 /** 1849 * Rate_6 - 4.32 Gbps/Lane 1850 */ 1851 PHY_RATE_432 = 6, 1852 /** 1853 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1854 */ 1855 PHY_RATE_540 = 7, 1856 /** 1857 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1858 */ 1859 PHY_RATE_810 = 8, 1860 /** 1861 * UHBR10 - 10.0 Gbps/Lane 1862 */ 1863 PHY_RATE_1000 = 9, 1864 /** 1865 * UHBR13.5 - 13.5 Gbps/Lane 1866 */ 1867 PHY_RATE_1350 = 10, 1868 /** 1869 * UHBR10 - 20.0 Gbps/Lane 1870 */ 1871 PHY_RATE_2000 = 11, 1872 }; 1873 1874 /** 1875 * enum dmub_phy_fsm_state - PHY FSM states. 1876 * PHY FSM state to transit to during PSR enable/disable. 1877 */ 1878 enum dmub_phy_fsm_state { 1879 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1880 DMUB_PHY_FSM_RESET, 1881 DMUB_PHY_FSM_RESET_RELEASED, 1882 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1883 DMUB_PHY_FSM_INITIALIZED, 1884 DMUB_PHY_FSM_CALIBRATED, 1885 DMUB_PHY_FSM_CALIBRATED_LP, 1886 DMUB_PHY_FSM_CALIBRATED_PG, 1887 DMUB_PHY_FSM_POWER_DOWN, 1888 DMUB_PHY_FSM_PLL_EN, 1889 DMUB_PHY_FSM_TX_EN, 1890 DMUB_PHY_FSM_FAST_LP, 1891 }; 1892 1893 /** 1894 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1895 */ 1896 struct dmub_cmd_psr_copy_settings_data { 1897 /** 1898 * Flags that can be set by driver to change some PSR behaviour. 1899 */ 1900 union dmub_psr_debug_flags debug; 1901 /** 1902 * 16-bit value dicated by driver that will enable/disable different functionality. 1903 */ 1904 uint16_t psr_level; 1905 /** 1906 * DPP HW instance. 1907 */ 1908 uint8_t dpp_inst; 1909 /** 1910 * MPCC HW instance. 1911 * Not used in dmub fw, 1912 * dmub fw will get active opp by reading odm registers. 1913 */ 1914 uint8_t mpcc_inst; 1915 /** 1916 * OPP HW instance. 1917 * Not used in dmub fw, 1918 * dmub fw will get active opp by reading odm registers. 1919 */ 1920 uint8_t opp_inst; 1921 /** 1922 * OTG HW instance. 1923 */ 1924 uint8_t otg_inst; 1925 /** 1926 * DIG FE HW instance. 1927 */ 1928 uint8_t digfe_inst; 1929 /** 1930 * DIG BE HW instance. 1931 */ 1932 uint8_t digbe_inst; 1933 /** 1934 * DP PHY HW instance. 1935 */ 1936 uint8_t dpphy_inst; 1937 /** 1938 * AUX HW instance. 1939 */ 1940 uint8_t aux_inst; 1941 /** 1942 * Determines if SMU optimzations are enabled/disabled. 1943 */ 1944 uint8_t smu_optimizations_en; 1945 /** 1946 * Unused. 1947 * TODO: Remove. 1948 */ 1949 uint8_t frame_delay; 1950 /** 1951 * If RFB setup time is greater than the total VBLANK time, 1952 * it is not possible for the sink to capture the video frame 1953 * in the same frame the SDP is sent. In this case, 1954 * the frame capture indication bit should be set and an extra 1955 * static frame should be transmitted to the sink. 1956 */ 1957 uint8_t frame_cap_ind; 1958 /** 1959 * Granularity of Y offset supported by sink. 1960 */ 1961 uint8_t su_y_granularity; 1962 /** 1963 * Indicates whether sink should start capturing 1964 * immediately following active scan line, 1965 * or starting with the 2nd active scan line. 1966 */ 1967 uint8_t line_capture_indication; 1968 /** 1969 * Multi-display optimizations are implemented on certain ASICs. 1970 */ 1971 uint8_t multi_disp_optimizations_en; 1972 /** 1973 * The last possible line SDP may be transmitted without violating 1974 * the RFB setup time or entering the active video frame. 1975 */ 1976 uint16_t init_sdp_deadline; 1977 /** 1978 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1979 */ 1980 uint8_t rate_control_caps ; 1981 /* 1982 * Force PSRSU always doing full frame update 1983 */ 1984 uint8_t force_ffu_mode; 1985 /** 1986 * Length of each horizontal line in us. 1987 */ 1988 uint32_t line_time_in_us; 1989 /** 1990 * FEC enable status in driver 1991 */ 1992 uint8_t fec_enable_status; 1993 /** 1994 * FEC re-enable delay when PSR exit. 1995 * unit is 100us, range form 0~255(0xFF). 1996 */ 1997 uint8_t fec_enable_delay_in100us; 1998 /** 1999 * PSR control version. 2000 */ 2001 uint8_t cmd_version; 2002 /** 2003 * Panel Instance. 2004 * Panel instance to identify which psr_state to use 2005 * Currently the support is only for 0 or 1 2006 */ 2007 uint8_t panel_inst; 2008 /* 2009 * DSC enable status in driver 2010 */ 2011 uint8_t dsc_enable_status; 2012 /* 2013 * Use FSM state for PSR power up/down 2014 */ 2015 uint8_t use_phy_fsm; 2016 /** 2017 * frame delay for frame re-lock 2018 */ 2019 uint8_t relock_delay_frame_cnt; 2020 /** 2021 * Explicit padding to 2 byte boundary. 2022 */ 2023 uint8_t pad3; 2024 /** 2025 * DSC Slice height. 2026 */ 2027 uint16_t dsc_slice_height; 2028 /** 2029 * Explicit padding to 4 byte boundary. 2030 */ 2031 uint16_t pad; 2032 }; 2033 2034 /** 2035 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2036 */ 2037 struct dmub_rb_cmd_psr_copy_settings { 2038 /** 2039 * Command header. 2040 */ 2041 struct dmub_cmd_header header; 2042 /** 2043 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2044 */ 2045 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2046 }; 2047 2048 /** 2049 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2050 */ 2051 struct dmub_cmd_psr_set_level_data { 2052 /** 2053 * 16-bit value dicated by driver that will enable/disable different functionality. 2054 */ 2055 uint16_t psr_level; 2056 /** 2057 * PSR control version. 2058 */ 2059 uint8_t cmd_version; 2060 /** 2061 * Panel Instance. 2062 * Panel instance to identify which psr_state to use 2063 * Currently the support is only for 0 or 1 2064 */ 2065 uint8_t panel_inst; 2066 }; 2067 2068 /** 2069 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2070 */ 2071 struct dmub_rb_cmd_psr_set_level { 2072 /** 2073 * Command header. 2074 */ 2075 struct dmub_cmd_header header; 2076 /** 2077 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2078 */ 2079 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2080 }; 2081 2082 struct dmub_rb_cmd_psr_enable_data { 2083 /** 2084 * PSR control version. 2085 */ 2086 uint8_t cmd_version; 2087 /** 2088 * Panel Instance. 2089 * Panel instance to identify which psr_state to use 2090 * Currently the support is only for 0 or 1 2091 */ 2092 uint8_t panel_inst; 2093 /** 2094 * Phy state to enter. 2095 * Values to use are defined in dmub_phy_fsm_state 2096 */ 2097 uint8_t phy_fsm_state; 2098 /** 2099 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2100 * Set this using enum phy_link_rate. 2101 * This does not support HDMI/DP2 for now. 2102 */ 2103 uint8_t phy_rate; 2104 }; 2105 2106 /** 2107 * Definition of a DMUB_CMD__PSR_ENABLE command. 2108 * PSR enable/disable is controlled using the sub_type. 2109 */ 2110 struct dmub_rb_cmd_psr_enable { 2111 /** 2112 * Command header. 2113 */ 2114 struct dmub_cmd_header header; 2115 2116 struct dmub_rb_cmd_psr_enable_data data; 2117 }; 2118 2119 /** 2120 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2121 */ 2122 struct dmub_cmd_psr_set_version_data { 2123 /** 2124 * PSR version that FW should implement. 2125 */ 2126 enum psr_version version; 2127 /** 2128 * PSR control version. 2129 */ 2130 uint8_t cmd_version; 2131 /** 2132 * Panel Instance. 2133 * Panel instance to identify which psr_state to use 2134 * Currently the support is only for 0 or 1 2135 */ 2136 uint8_t panel_inst; 2137 /** 2138 * Explicit padding to 4 byte boundary. 2139 */ 2140 uint8_t pad[2]; 2141 }; 2142 2143 /** 2144 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2145 */ 2146 struct dmub_rb_cmd_psr_set_version { 2147 /** 2148 * Command header. 2149 */ 2150 struct dmub_cmd_header header; 2151 /** 2152 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2153 */ 2154 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2155 }; 2156 2157 struct dmub_cmd_psr_force_static_data { 2158 /** 2159 * PSR control version. 2160 */ 2161 uint8_t cmd_version; 2162 /** 2163 * Panel Instance. 2164 * Panel instance to identify which psr_state to use 2165 * Currently the support is only for 0 or 1 2166 */ 2167 uint8_t panel_inst; 2168 /** 2169 * Explicit padding to 4 byte boundary. 2170 */ 2171 uint8_t pad[2]; 2172 }; 2173 2174 /** 2175 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2176 */ 2177 struct dmub_rb_cmd_psr_force_static { 2178 /** 2179 * Command header. 2180 */ 2181 struct dmub_cmd_header header; 2182 /** 2183 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2184 */ 2185 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2186 }; 2187 2188 /** 2189 * PSR SU debug flags. 2190 */ 2191 union dmub_psr_su_debug_flags { 2192 /** 2193 * PSR SU debug flags. 2194 */ 2195 struct { 2196 /** 2197 * Update dirty rect in SW only. 2198 */ 2199 uint8_t update_dirty_rect_only : 1; 2200 /** 2201 * Reset the cursor/plane state before processing the call. 2202 */ 2203 uint8_t reset_state : 1; 2204 } bitfields; 2205 2206 /** 2207 * Union for debug flags. 2208 */ 2209 uint32_t u32All; 2210 }; 2211 2212 /** 2213 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2214 * This triggers a selective update for PSR SU. 2215 */ 2216 struct dmub_cmd_update_dirty_rect_data { 2217 /** 2218 * Dirty rects from OS. 2219 */ 2220 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2221 /** 2222 * PSR SU debug flags. 2223 */ 2224 union dmub_psr_su_debug_flags debug_flags; 2225 /** 2226 * OTG HW instance. 2227 */ 2228 uint8_t pipe_idx; 2229 /** 2230 * Number of dirty rects. 2231 */ 2232 uint8_t dirty_rect_count; 2233 /** 2234 * PSR control version. 2235 */ 2236 uint8_t cmd_version; 2237 /** 2238 * Panel Instance. 2239 * Panel instance to identify which psr_state to use 2240 * Currently the support is only for 0 or 1 2241 */ 2242 uint8_t panel_inst; 2243 }; 2244 2245 /** 2246 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2247 */ 2248 struct dmub_rb_cmd_update_dirty_rect { 2249 /** 2250 * Command header. 2251 */ 2252 struct dmub_cmd_header header; 2253 /** 2254 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2255 */ 2256 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2257 }; 2258 2259 /** 2260 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2261 */ 2262 union dmub_reg_cursor_control_cfg { 2263 struct { 2264 uint32_t cur_enable: 1; 2265 uint32_t reser0: 3; 2266 uint32_t cur_2x_magnify: 1; 2267 uint32_t reser1: 3; 2268 uint32_t mode: 3; 2269 uint32_t reser2: 5; 2270 uint32_t pitch: 2; 2271 uint32_t reser3: 6; 2272 uint32_t line_per_chunk: 5; 2273 uint32_t reser4: 3; 2274 } bits; 2275 uint32_t raw; 2276 }; 2277 struct dmub_cursor_position_cache_hubp { 2278 union dmub_reg_cursor_control_cfg cur_ctl; 2279 union dmub_reg_position_cfg { 2280 struct { 2281 uint32_t cur_x_pos: 16; 2282 uint32_t cur_y_pos: 16; 2283 } bits; 2284 uint32_t raw; 2285 } position; 2286 union dmub_reg_hot_spot_cfg { 2287 struct { 2288 uint32_t hot_x: 16; 2289 uint32_t hot_y: 16; 2290 } bits; 2291 uint32_t raw; 2292 } hot_spot; 2293 union dmub_reg_dst_offset_cfg { 2294 struct { 2295 uint32_t dst_x_offset: 13; 2296 uint32_t reserved: 19; 2297 } bits; 2298 uint32_t raw; 2299 } dst_offset; 2300 }; 2301 2302 union dmub_reg_cur0_control_cfg { 2303 struct { 2304 uint32_t cur0_enable: 1; 2305 uint32_t expansion_mode: 1; 2306 uint32_t reser0: 1; 2307 uint32_t cur0_rom_en: 1; 2308 uint32_t mode: 3; 2309 uint32_t reserved: 25; 2310 } bits; 2311 uint32_t raw; 2312 }; 2313 struct dmub_cursor_position_cache_dpp { 2314 union dmub_reg_cur0_control_cfg cur0_ctl; 2315 }; 2316 struct dmub_cursor_position_cfg { 2317 struct dmub_cursor_position_cache_hubp pHubp; 2318 struct dmub_cursor_position_cache_dpp pDpp; 2319 uint8_t pipe_idx; 2320 /* 2321 * Padding is required. To be 4 Bytes Aligned. 2322 */ 2323 uint8_t padding[3]; 2324 }; 2325 2326 struct dmub_cursor_attribute_cache_hubp { 2327 uint32_t SURFACE_ADDR_HIGH; 2328 uint32_t SURFACE_ADDR; 2329 union dmub_reg_cursor_control_cfg cur_ctl; 2330 union dmub_reg_cursor_size_cfg { 2331 struct { 2332 uint32_t width: 16; 2333 uint32_t height: 16; 2334 } bits; 2335 uint32_t raw; 2336 } size; 2337 union dmub_reg_cursor_settings_cfg { 2338 struct { 2339 uint32_t dst_y_offset: 8; 2340 uint32_t chunk_hdl_adjust: 2; 2341 uint32_t reserved: 22; 2342 } bits; 2343 uint32_t raw; 2344 } settings; 2345 }; 2346 struct dmub_cursor_attribute_cache_dpp { 2347 union dmub_reg_cur0_control_cfg cur0_ctl; 2348 }; 2349 struct dmub_cursor_attributes_cfg { 2350 struct dmub_cursor_attribute_cache_hubp aHubp; 2351 struct dmub_cursor_attribute_cache_dpp aDpp; 2352 }; 2353 2354 struct dmub_cmd_update_cursor_payload0 { 2355 /** 2356 * Cursor dirty rects. 2357 */ 2358 struct dmub_rect cursor_rect; 2359 /** 2360 * PSR SU debug flags. 2361 */ 2362 union dmub_psr_su_debug_flags debug_flags; 2363 /** 2364 * Cursor enable/disable. 2365 */ 2366 uint8_t enable; 2367 /** 2368 * OTG HW instance. 2369 */ 2370 uint8_t pipe_idx; 2371 /** 2372 * PSR control version. 2373 */ 2374 uint8_t cmd_version; 2375 /** 2376 * Panel Instance. 2377 * Panel instance to identify which psr_state to use 2378 * Currently the support is only for 0 or 1 2379 */ 2380 uint8_t panel_inst; 2381 /** 2382 * Cursor Position Register. 2383 * Registers contains Hubp & Dpp modules 2384 */ 2385 struct dmub_cursor_position_cfg position_cfg; 2386 }; 2387 2388 struct dmub_cmd_update_cursor_payload1 { 2389 struct dmub_cursor_attributes_cfg attribute_cfg; 2390 }; 2391 2392 union dmub_cmd_update_cursor_info_data { 2393 struct dmub_cmd_update_cursor_payload0 payload0; 2394 struct dmub_cmd_update_cursor_payload1 payload1; 2395 }; 2396 /** 2397 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2398 */ 2399 struct dmub_rb_cmd_update_cursor_info { 2400 /** 2401 * Command header. 2402 */ 2403 struct dmub_cmd_header header; 2404 /** 2405 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2406 */ 2407 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2408 }; 2409 2410 /** 2411 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2412 */ 2413 struct dmub_cmd_psr_set_vtotal_data { 2414 /** 2415 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2416 */ 2417 uint16_t psr_vtotal_idle; 2418 /** 2419 * PSR control version. 2420 */ 2421 uint8_t cmd_version; 2422 /** 2423 * Panel Instance. 2424 * Panel instance to identify which psr_state to use 2425 * Currently the support is only for 0 or 1 2426 */ 2427 uint8_t panel_inst; 2428 /* 2429 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2430 */ 2431 uint16_t psr_vtotal_su; 2432 /** 2433 * Explicit padding to 4 byte boundary. 2434 */ 2435 uint8_t pad2[2]; 2436 }; 2437 2438 /** 2439 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2440 */ 2441 struct dmub_rb_cmd_psr_set_vtotal { 2442 /** 2443 * Command header. 2444 */ 2445 struct dmub_cmd_header header; 2446 /** 2447 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2448 */ 2449 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2450 }; 2451 2452 /** 2453 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2454 */ 2455 struct dmub_cmd_psr_set_power_opt_data { 2456 /** 2457 * PSR control version. 2458 */ 2459 uint8_t cmd_version; 2460 /** 2461 * Panel Instance. 2462 * Panel instance to identify which psr_state to use 2463 * Currently the support is only for 0 or 1 2464 */ 2465 uint8_t panel_inst; 2466 /** 2467 * Explicit padding to 4 byte boundary. 2468 */ 2469 uint8_t pad[2]; 2470 /** 2471 * PSR power option 2472 */ 2473 uint32_t power_opt; 2474 }; 2475 2476 /** 2477 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2478 */ 2479 struct dmub_rb_cmd_psr_set_power_opt { 2480 /** 2481 * Command header. 2482 */ 2483 struct dmub_cmd_header header; 2484 /** 2485 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2486 */ 2487 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2488 }; 2489 2490 /** 2491 * Set of HW components that can be locked. 2492 * 2493 * Note: If updating with more HW components, fields 2494 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2495 */ 2496 union dmub_hw_lock_flags { 2497 /** 2498 * Set of HW components that can be locked. 2499 */ 2500 struct { 2501 /** 2502 * Lock/unlock OTG master update lock. 2503 */ 2504 uint8_t lock_pipe : 1; 2505 /** 2506 * Lock/unlock cursor. 2507 */ 2508 uint8_t lock_cursor : 1; 2509 /** 2510 * Lock/unlock global update lock. 2511 */ 2512 uint8_t lock_dig : 1; 2513 /** 2514 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2515 */ 2516 uint8_t triple_buffer_lock : 1; 2517 } bits; 2518 2519 /** 2520 * Union for HW Lock flags. 2521 */ 2522 uint8_t u8All; 2523 }; 2524 2525 /** 2526 * Instances of HW to be locked. 2527 * 2528 * Note: If updating with more HW components, fields 2529 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2530 */ 2531 struct dmub_hw_lock_inst_flags { 2532 /** 2533 * OTG HW instance for OTG master update lock. 2534 */ 2535 uint8_t otg_inst; 2536 /** 2537 * OPP instance for cursor lock. 2538 */ 2539 uint8_t opp_inst; 2540 /** 2541 * OTG HW instance for global update lock. 2542 * TODO: Remove, and re-use otg_inst. 2543 */ 2544 uint8_t dig_inst; 2545 /** 2546 * Explicit pad to 4 byte boundary. 2547 */ 2548 uint8_t pad; 2549 }; 2550 2551 /** 2552 * Clients that can acquire the HW Lock Manager. 2553 * 2554 * Note: If updating with more clients, fields in 2555 * dmub_inbox0_cmd_lock_hw must be updated to match. 2556 */ 2557 enum hw_lock_client { 2558 /** 2559 * Driver is the client of HW Lock Manager. 2560 */ 2561 HW_LOCK_CLIENT_DRIVER = 0, 2562 /** 2563 * PSR SU is the client of HW Lock Manager. 2564 */ 2565 HW_LOCK_CLIENT_PSR_SU = 1, 2566 /** 2567 * Invalid client. 2568 */ 2569 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2570 }; 2571 2572 /** 2573 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2574 */ 2575 struct dmub_cmd_lock_hw_data { 2576 /** 2577 * Specifies the client accessing HW Lock Manager. 2578 */ 2579 enum hw_lock_client client; 2580 /** 2581 * HW instances to be locked. 2582 */ 2583 struct dmub_hw_lock_inst_flags inst_flags; 2584 /** 2585 * Which components to be locked. 2586 */ 2587 union dmub_hw_lock_flags hw_locks; 2588 /** 2589 * Specifies lock/unlock. 2590 */ 2591 uint8_t lock; 2592 /** 2593 * HW can be unlocked separately from releasing the HW Lock Mgr. 2594 * This flag is set if the client wishes to release the object. 2595 */ 2596 uint8_t should_release; 2597 /** 2598 * Explicit padding to 4 byte boundary. 2599 */ 2600 uint8_t pad; 2601 }; 2602 2603 /** 2604 * Definition of a DMUB_CMD__HW_LOCK command. 2605 * Command is used by driver and FW. 2606 */ 2607 struct dmub_rb_cmd_lock_hw { 2608 /** 2609 * Command header. 2610 */ 2611 struct dmub_cmd_header header; 2612 /** 2613 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2614 */ 2615 struct dmub_cmd_lock_hw_data lock_hw_data; 2616 }; 2617 2618 /** 2619 * ABM command sub-types. 2620 */ 2621 enum dmub_cmd_abm_type { 2622 /** 2623 * Initialize parameters for ABM algorithm. 2624 * Data is passed through an indirect buffer. 2625 */ 2626 DMUB_CMD__ABM_INIT_CONFIG = 0, 2627 /** 2628 * Set OTG and panel HW instance. 2629 */ 2630 DMUB_CMD__ABM_SET_PIPE = 1, 2631 /** 2632 * Set user requested backklight level. 2633 */ 2634 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2635 /** 2636 * Set ABM operating/aggression level. 2637 */ 2638 DMUB_CMD__ABM_SET_LEVEL = 3, 2639 /** 2640 * Set ambient light level. 2641 */ 2642 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2643 /** 2644 * Enable/disable fractional duty cycle for backlight PWM. 2645 */ 2646 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2647 2648 /** 2649 * unregister vertical interrupt after steady state is reached 2650 */ 2651 DMUB_CMD__ABM_PAUSE = 6, 2652 }; 2653 2654 /** 2655 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2656 * Requirements: 2657 * - Padded explicitly to 32-bit boundary. 2658 * - Must ensure this structure matches the one on driver-side, 2659 * otherwise it won't be aligned. 2660 */ 2661 struct abm_config_table { 2662 /** 2663 * Gamma curve thresholds, used for crgb conversion. 2664 */ 2665 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2666 /** 2667 * Gamma curve offsets, used for crgb conversion. 2668 */ 2669 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2670 /** 2671 * Gamma curve slopes, used for crgb conversion. 2672 */ 2673 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2674 /** 2675 * Custom backlight curve thresholds. 2676 */ 2677 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2678 /** 2679 * Custom backlight curve offsets. 2680 */ 2681 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2682 /** 2683 * Ambient light thresholds. 2684 */ 2685 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2686 /** 2687 * Minimum programmable backlight. 2688 */ 2689 uint16_t min_abm_backlight; // 122B 2690 /** 2691 * Minimum reduction values. 2692 */ 2693 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2694 /** 2695 * Maximum reduction values. 2696 */ 2697 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2698 /** 2699 * Bright positive gain. 2700 */ 2701 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2702 /** 2703 * Dark negative gain. 2704 */ 2705 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2706 /** 2707 * Hybrid factor. 2708 */ 2709 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2710 /** 2711 * Contrast factor. 2712 */ 2713 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2714 /** 2715 * Deviation gain. 2716 */ 2717 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2718 /** 2719 * Minimum knee. 2720 */ 2721 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2722 /** 2723 * Maximum knee. 2724 */ 2725 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2726 /** 2727 * Unused. 2728 */ 2729 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2730 /** 2731 * Explicit padding to 4 byte boundary. 2732 */ 2733 uint8_t pad3[3]; // 229B 2734 /** 2735 * Backlight ramp reduction. 2736 */ 2737 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2738 /** 2739 * Backlight ramp start. 2740 */ 2741 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2742 }; 2743 2744 /** 2745 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2746 */ 2747 struct dmub_cmd_abm_set_pipe_data { 2748 /** 2749 * OTG HW instance. 2750 */ 2751 uint8_t otg_inst; 2752 2753 /** 2754 * Panel Control HW instance. 2755 */ 2756 uint8_t panel_inst; 2757 2758 /** 2759 * Controls how ABM will interpret a set pipe or set level command. 2760 */ 2761 uint8_t set_pipe_option; 2762 2763 /** 2764 * Unused. 2765 * TODO: Remove. 2766 */ 2767 uint8_t ramping_boundary; 2768 }; 2769 2770 /** 2771 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2772 */ 2773 struct dmub_rb_cmd_abm_set_pipe { 2774 /** 2775 * Command header. 2776 */ 2777 struct dmub_cmd_header header; 2778 2779 /** 2780 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2781 */ 2782 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2783 }; 2784 2785 /** 2786 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2787 */ 2788 struct dmub_cmd_abm_set_backlight_data { 2789 /** 2790 * Number of frames to ramp to backlight user level. 2791 */ 2792 uint32_t frame_ramp; 2793 2794 /** 2795 * Requested backlight level from user. 2796 */ 2797 uint32_t backlight_user_level; 2798 2799 /** 2800 * ABM control version. 2801 */ 2802 uint8_t version; 2803 2804 /** 2805 * Panel Control HW instance mask. 2806 * Bit 0 is Panel Control HW instance 0. 2807 * Bit 1 is Panel Control HW instance 1. 2808 */ 2809 uint8_t panel_mask; 2810 2811 /** 2812 * Explicit padding to 4 byte boundary. 2813 */ 2814 uint8_t pad[2]; 2815 }; 2816 2817 /** 2818 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2819 */ 2820 struct dmub_rb_cmd_abm_set_backlight { 2821 /** 2822 * Command header. 2823 */ 2824 struct dmub_cmd_header header; 2825 2826 /** 2827 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2828 */ 2829 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2830 }; 2831 2832 /** 2833 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2834 */ 2835 struct dmub_cmd_abm_set_level_data { 2836 /** 2837 * Set current ABM operating/aggression level. 2838 */ 2839 uint32_t level; 2840 2841 /** 2842 * ABM control version. 2843 */ 2844 uint8_t version; 2845 2846 /** 2847 * Panel Control HW instance mask. 2848 * Bit 0 is Panel Control HW instance 0. 2849 * Bit 1 is Panel Control HW instance 1. 2850 */ 2851 uint8_t panel_mask; 2852 2853 /** 2854 * Explicit padding to 4 byte boundary. 2855 */ 2856 uint8_t pad[2]; 2857 }; 2858 2859 /** 2860 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2861 */ 2862 struct dmub_rb_cmd_abm_set_level { 2863 /** 2864 * Command header. 2865 */ 2866 struct dmub_cmd_header header; 2867 2868 /** 2869 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2870 */ 2871 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2872 }; 2873 2874 /** 2875 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2876 */ 2877 struct dmub_cmd_abm_set_ambient_level_data { 2878 /** 2879 * Ambient light sensor reading from OS. 2880 */ 2881 uint32_t ambient_lux; 2882 2883 /** 2884 * ABM control version. 2885 */ 2886 uint8_t version; 2887 2888 /** 2889 * Panel Control HW instance mask. 2890 * Bit 0 is Panel Control HW instance 0. 2891 * Bit 1 is Panel Control HW instance 1. 2892 */ 2893 uint8_t panel_mask; 2894 2895 /** 2896 * Explicit padding to 4 byte boundary. 2897 */ 2898 uint8_t pad[2]; 2899 }; 2900 2901 /** 2902 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2903 */ 2904 struct dmub_rb_cmd_abm_set_ambient_level { 2905 /** 2906 * Command header. 2907 */ 2908 struct dmub_cmd_header header; 2909 2910 /** 2911 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2912 */ 2913 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2914 }; 2915 2916 /** 2917 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2918 */ 2919 struct dmub_cmd_abm_set_pwm_frac_data { 2920 /** 2921 * Enable/disable fractional duty cycle for backlight PWM. 2922 * TODO: Convert to uint8_t. 2923 */ 2924 uint32_t fractional_pwm; 2925 2926 /** 2927 * ABM control version. 2928 */ 2929 uint8_t version; 2930 2931 /** 2932 * Panel Control HW instance mask. 2933 * Bit 0 is Panel Control HW instance 0. 2934 * Bit 1 is Panel Control HW instance 1. 2935 */ 2936 uint8_t panel_mask; 2937 2938 /** 2939 * Explicit padding to 4 byte boundary. 2940 */ 2941 uint8_t pad[2]; 2942 }; 2943 2944 /** 2945 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2946 */ 2947 struct dmub_rb_cmd_abm_set_pwm_frac { 2948 /** 2949 * Command header. 2950 */ 2951 struct dmub_cmd_header header; 2952 2953 /** 2954 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2955 */ 2956 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2957 }; 2958 2959 /** 2960 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2961 */ 2962 struct dmub_cmd_abm_init_config_data { 2963 /** 2964 * Location of indirect buffer used to pass init data to ABM. 2965 */ 2966 union dmub_addr src; 2967 2968 /** 2969 * Indirect buffer length. 2970 */ 2971 uint16_t bytes; 2972 2973 2974 /** 2975 * ABM control version. 2976 */ 2977 uint8_t version; 2978 2979 /** 2980 * Panel Control HW instance mask. 2981 * Bit 0 is Panel Control HW instance 0. 2982 * Bit 1 is Panel Control HW instance 1. 2983 */ 2984 uint8_t panel_mask; 2985 2986 /** 2987 * Explicit padding to 4 byte boundary. 2988 */ 2989 uint8_t pad[2]; 2990 }; 2991 2992 /** 2993 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2994 */ 2995 struct dmub_rb_cmd_abm_init_config { 2996 /** 2997 * Command header. 2998 */ 2999 struct dmub_cmd_header header; 3000 3001 /** 3002 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3003 */ 3004 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3005 }; 3006 3007 /** 3008 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3009 */ 3010 3011 struct dmub_cmd_abm_pause_data { 3012 3013 /** 3014 * Panel Control HW instance mask. 3015 * Bit 0 is Panel Control HW instance 0. 3016 * Bit 1 is Panel Control HW instance 1. 3017 */ 3018 uint8_t panel_mask; 3019 3020 /** 3021 * OTG hw instance 3022 */ 3023 uint8_t otg_inst; 3024 3025 /** 3026 * Enable or disable ABM pause 3027 */ 3028 uint8_t enable; 3029 3030 /** 3031 * Explicit padding to 4 byte boundary. 3032 */ 3033 uint8_t pad[1]; 3034 }; 3035 3036 /** 3037 * Definition of a DMUB_CMD__ABM_PAUSE command. 3038 */ 3039 struct dmub_rb_cmd_abm_pause { 3040 /** 3041 * Command header. 3042 */ 3043 struct dmub_cmd_header header; 3044 3045 /** 3046 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3047 */ 3048 struct dmub_cmd_abm_pause_data abm_pause_data; 3049 }; 3050 3051 /** 3052 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3053 */ 3054 struct dmub_cmd_query_feature_caps_data { 3055 /** 3056 * DMUB feature capabilities. 3057 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3058 */ 3059 struct dmub_feature_caps feature_caps; 3060 }; 3061 3062 /** 3063 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3064 */ 3065 struct dmub_rb_cmd_query_feature_caps { 3066 /** 3067 * Command header. 3068 */ 3069 struct dmub_cmd_header header; 3070 /** 3071 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3072 */ 3073 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 3074 }; 3075 3076 /** 3077 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3078 */ 3079 struct dmub_cmd_visual_confirm_color_data { 3080 /** 3081 * DMUB feature capabilities. 3082 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3083 */ 3084 struct dmub_visual_confirm_color visual_confirm_color; 3085 }; 3086 3087 /** 3088 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3089 */ 3090 struct dmub_rb_cmd_get_visual_confirm_color { 3091 /** 3092 * Command header. 3093 */ 3094 struct dmub_cmd_header header; 3095 /** 3096 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3097 */ 3098 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3099 }; 3100 3101 struct dmub_optc_state { 3102 uint32_t v_total_max; 3103 uint32_t v_total_min; 3104 uint32_t tg_inst; 3105 }; 3106 3107 struct dmub_rb_cmd_drr_update { 3108 struct dmub_cmd_header header; 3109 struct dmub_optc_state dmub_optc_state_req; 3110 }; 3111 3112 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 3113 uint32_t pix_clk_100hz; 3114 uint8_t max_ramp_step; 3115 uint8_t pipes; 3116 uint8_t min_refresh_in_hz; 3117 uint8_t pipe_count; 3118 uint8_t pipe_index[4]; 3119 }; 3120 3121 struct dmub_cmd_fw_assisted_mclk_switch_config { 3122 uint8_t fams_enabled; 3123 uint8_t visual_confirm_enabled; 3124 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 3125 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 3126 }; 3127 3128 struct dmub_rb_cmd_fw_assisted_mclk_switch { 3129 struct dmub_cmd_header header; 3130 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 3131 }; 3132 3133 /** 3134 * enum dmub_cmd_panel_cntl_type - Panel control command. 3135 */ 3136 enum dmub_cmd_panel_cntl_type { 3137 /** 3138 * Initializes embedded panel hardware blocks. 3139 */ 3140 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3141 /** 3142 * Queries backlight info for the embedded panel. 3143 */ 3144 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3145 }; 3146 3147 /** 3148 * struct dmub_cmd_panel_cntl_data - Panel control data. 3149 */ 3150 struct dmub_cmd_panel_cntl_data { 3151 uint32_t inst; /**< panel instance */ 3152 uint32_t current_backlight; /* in/out */ 3153 uint32_t bl_pwm_cntl; /* in/out */ 3154 uint32_t bl_pwm_period_cntl; /* in/out */ 3155 uint32_t bl_pwm_ref_div1; /* in/out */ 3156 uint8_t is_backlight_on : 1; /* in/out */ 3157 uint8_t is_powered_on : 1; /* in/out */ 3158 uint8_t padding[3]; 3159 uint32_t bl_pwm_ref_div2; /* in/out */ 3160 uint8_t reserved[4]; 3161 }; 3162 3163 /** 3164 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3165 */ 3166 struct dmub_rb_cmd_panel_cntl { 3167 struct dmub_cmd_header header; /**< header */ 3168 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3169 }; 3170 3171 /** 3172 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3173 */ 3174 struct dmub_cmd_lvtma_control_data { 3175 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3176 uint8_t bypass_panel_control_wait; 3177 uint8_t reserved_0[2]; /**< For future use */ 3178 uint8_t panel_inst; /**< LVTMA control instance */ 3179 uint8_t reserved_1[3]; /**< For future use */ 3180 }; 3181 3182 /** 3183 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3184 */ 3185 struct dmub_rb_cmd_lvtma_control { 3186 /** 3187 * Command header. 3188 */ 3189 struct dmub_cmd_header header; 3190 /** 3191 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3192 */ 3193 struct dmub_cmd_lvtma_control_data data; 3194 }; 3195 3196 /** 3197 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3198 */ 3199 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3200 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3201 uint8_t is_usb; /**< is phy is usb */ 3202 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3203 uint8_t is_dp4; /**< is dp in 4 lane */ 3204 }; 3205 3206 /** 3207 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3208 */ 3209 struct dmub_rb_cmd_transmitter_query_dp_alt { 3210 struct dmub_cmd_header header; /**< header */ 3211 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3212 }; 3213 3214 /** 3215 * Maximum number of bytes a chunk sent to DMUB for parsing 3216 */ 3217 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3218 3219 /** 3220 * Represent a chunk of CEA blocks sent to DMUB for parsing 3221 */ 3222 struct dmub_cmd_send_edid_cea { 3223 uint16_t offset; /**< offset into the CEA block */ 3224 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3225 uint16_t cea_total_length; /**< total length of the CEA block */ 3226 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3227 uint8_t pad[3]; /**< padding and for future expansion */ 3228 }; 3229 3230 /** 3231 * Result of VSDB parsing from CEA block 3232 */ 3233 struct dmub_cmd_edid_cea_amd_vsdb { 3234 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3235 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3236 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3237 uint16_t min_frame_rate; /**< Maximum frame rate */ 3238 uint16_t max_frame_rate; /**< Minimum frame rate */ 3239 }; 3240 3241 /** 3242 * Result of sending a CEA chunk 3243 */ 3244 struct dmub_cmd_edid_cea_ack { 3245 uint16_t offset; /**< offset of the chunk into the CEA block */ 3246 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3247 uint8_t pad; /**< padding and for future expansion */ 3248 }; 3249 3250 /** 3251 * Specify whether the result is an ACK/NACK or the parsing has finished 3252 */ 3253 enum dmub_cmd_edid_cea_reply_type { 3254 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3255 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3256 }; 3257 3258 /** 3259 * Definition of a DMUB_CMD__EDID_CEA command. 3260 */ 3261 struct dmub_rb_cmd_edid_cea { 3262 struct dmub_cmd_header header; /**< Command header */ 3263 union dmub_cmd_edid_cea_data { 3264 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3265 struct dmub_cmd_edid_cea_output { /**< output with results */ 3266 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3267 union { 3268 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3269 struct dmub_cmd_edid_cea_ack ack; 3270 }; 3271 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3272 } data; /**< Command data */ 3273 3274 }; 3275 3276 /** 3277 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3278 */ 3279 struct dmub_cmd_cable_id_input { 3280 uint8_t phy_inst; /**< phy inst for cable id data */ 3281 }; 3282 3283 /** 3284 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3285 */ 3286 struct dmub_cmd_cable_id_output { 3287 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3288 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3289 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3290 uint8_t RESERVED :2; /**< reserved means not defined */ 3291 }; 3292 3293 /** 3294 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3295 */ 3296 struct dmub_rb_cmd_get_usbc_cable_id { 3297 struct dmub_cmd_header header; /**< Command header */ 3298 /** 3299 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3300 */ 3301 union dmub_cmd_cable_id_data { 3302 struct dmub_cmd_cable_id_input input; /**< Input */ 3303 struct dmub_cmd_cable_id_output output; /**< Output */ 3304 uint8_t output_raw; /**< Raw data output */ 3305 } data; 3306 }; 3307 3308 /** 3309 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3310 */ 3311 enum dmub_cmd_secure_display_type { 3312 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3313 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3314 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3315 }; 3316 3317 /** 3318 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3319 */ 3320 struct dmub_rb_cmd_secure_display { 3321 struct dmub_cmd_header header; 3322 /** 3323 * Data passed from driver to dmub firmware. 3324 */ 3325 struct dmub_cmd_roi_info { 3326 uint16_t x_start; 3327 uint16_t x_end; 3328 uint16_t y_start; 3329 uint16_t y_end; 3330 uint8_t otg_id; 3331 uint8_t phy_id; 3332 } roi_info; 3333 }; 3334 3335 /** 3336 * union dmub_rb_cmd - DMUB inbox command. 3337 */ 3338 union dmub_rb_cmd { 3339 /** 3340 * Elements shared with all commands. 3341 */ 3342 struct dmub_rb_cmd_common cmd_common; 3343 /** 3344 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3345 */ 3346 struct dmub_rb_cmd_read_modify_write read_modify_write; 3347 /** 3348 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3349 */ 3350 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3351 /** 3352 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3353 */ 3354 struct dmub_rb_cmd_burst_write burst_write; 3355 /** 3356 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3357 */ 3358 struct dmub_rb_cmd_reg_wait reg_wait; 3359 /** 3360 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3361 */ 3362 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3363 /** 3364 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3365 */ 3366 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3367 /** 3368 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3369 */ 3370 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3371 /** 3372 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3373 */ 3374 struct dmub_rb_cmd_dpphy_init dpphy_init; 3375 /** 3376 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3377 */ 3378 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3379 /** 3380 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3381 */ 3382 struct dmub_rb_cmd_domain_control domain_control; 3383 /** 3384 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3385 */ 3386 struct dmub_rb_cmd_psr_set_version psr_set_version; 3387 /** 3388 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3389 */ 3390 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3391 /** 3392 * Definition of a DMUB_CMD__PSR_ENABLE command. 3393 */ 3394 struct dmub_rb_cmd_psr_enable psr_enable; 3395 /** 3396 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3397 */ 3398 struct dmub_rb_cmd_psr_set_level psr_set_level; 3399 /** 3400 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3401 */ 3402 struct dmub_rb_cmd_psr_force_static psr_force_static; 3403 /** 3404 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3405 */ 3406 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3407 /** 3408 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3409 */ 3410 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3411 /** 3412 * Definition of a DMUB_CMD__HW_LOCK command. 3413 * Command is used by driver and FW. 3414 */ 3415 struct dmub_rb_cmd_lock_hw lock_hw; 3416 /** 3417 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3418 */ 3419 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3420 /** 3421 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3422 */ 3423 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3424 /** 3425 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3426 */ 3427 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3428 /** 3429 * Definition of a DMUB_CMD__MALL command. 3430 */ 3431 struct dmub_rb_cmd_mall mall; 3432 /** 3433 * Definition of a DMUB_CMD__CAB command. 3434 */ 3435 struct dmub_rb_cmd_cab_for_ss cab; 3436 3437 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3438 3439 /** 3440 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3441 */ 3442 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3443 3444 /** 3445 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3446 */ 3447 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3448 3449 /** 3450 * Definition of DMUB_CMD__PANEL_CNTL commands. 3451 */ 3452 struct dmub_rb_cmd_panel_cntl panel_cntl; 3453 /** 3454 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3455 */ 3456 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3457 3458 /** 3459 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3460 */ 3461 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3462 3463 /** 3464 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3465 */ 3466 struct dmub_rb_cmd_abm_set_level abm_set_level; 3467 3468 /** 3469 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3470 */ 3471 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3472 3473 /** 3474 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3475 */ 3476 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3477 3478 /** 3479 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3480 */ 3481 struct dmub_rb_cmd_abm_init_config abm_init_config; 3482 3483 /** 3484 * Definition of a DMUB_CMD__ABM_PAUSE command. 3485 */ 3486 struct dmub_rb_cmd_abm_pause abm_pause; 3487 3488 /** 3489 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3490 */ 3491 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3492 3493 /** 3494 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3495 */ 3496 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3497 3498 /** 3499 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3500 */ 3501 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3502 3503 /** 3504 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3505 */ 3506 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3507 struct dmub_rb_cmd_drr_update drr_update; 3508 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3509 3510 /** 3511 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3512 */ 3513 struct dmub_rb_cmd_lvtma_control lvtma_control; 3514 /** 3515 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3516 */ 3517 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3518 /** 3519 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3520 */ 3521 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3522 /** 3523 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3524 */ 3525 struct dmub_rb_cmd_set_config_access set_config_access; 3526 /** 3527 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3528 */ 3529 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3530 /** 3531 * Definition of a DMUB_CMD__EDID_CEA command. 3532 */ 3533 struct dmub_rb_cmd_edid_cea edid_cea; 3534 /** 3535 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3536 */ 3537 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3538 3539 /** 3540 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3541 */ 3542 struct dmub_rb_cmd_query_hpd_state query_hpd; 3543 /** 3544 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3545 */ 3546 struct dmub_rb_cmd_secure_display secure_display; 3547 3548 /** 3549 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3550 */ 3551 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3552 /** 3553 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 3554 */ 3555 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 3556 }; 3557 3558 /** 3559 * union dmub_rb_out_cmd - Outbox command 3560 */ 3561 union dmub_rb_out_cmd { 3562 /** 3563 * Parameters common to every command. 3564 */ 3565 struct dmub_rb_cmd_common cmd_common; 3566 /** 3567 * AUX reply command. 3568 */ 3569 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3570 /** 3571 * HPD notify command. 3572 */ 3573 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3574 /** 3575 * SET_CONFIG reply command. 3576 */ 3577 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3578 /** 3579 * DPIA notification command. 3580 */ 3581 struct dmub_rb_cmd_dpia_notification dpia_notification; 3582 }; 3583 #pragma pack(pop) 3584 3585 3586 //============================================================================== 3587 //</DMUB_CMD>=================================================================== 3588 //============================================================================== 3589 //< DMUB_RB>==================================================================== 3590 //============================================================================== 3591 3592 #if defined(__cplusplus) 3593 extern "C" { 3594 #endif 3595 3596 /** 3597 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3598 */ 3599 struct dmub_rb_init_params { 3600 void *ctx; /**< Caller provided context pointer */ 3601 void *base_address; /**< CPU base address for ring's data */ 3602 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3603 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3604 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3605 }; 3606 3607 /** 3608 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3609 */ 3610 struct dmub_rb { 3611 void *base_address; /**< CPU address for the ring's data */ 3612 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3613 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3614 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3615 3616 void *ctx; /**< Caller provided context pointer */ 3617 void *dmub; /**< Pointer to the DMUB interface */ 3618 }; 3619 3620 /** 3621 * @brief Checks if the ringbuffer is empty. 3622 * 3623 * @param rb DMUB Ringbuffer 3624 * @return true if empty 3625 * @return false otherwise 3626 */ 3627 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3628 { 3629 return (rb->wrpt == rb->rptr); 3630 } 3631 3632 /** 3633 * @brief Checks if the ringbuffer is full 3634 * 3635 * @param rb DMUB Ringbuffer 3636 * @return true if full 3637 * @return false otherwise 3638 */ 3639 static inline bool dmub_rb_full(struct dmub_rb *rb) 3640 { 3641 uint32_t data_count; 3642 3643 if (rb->wrpt >= rb->rptr) 3644 data_count = rb->wrpt - rb->rptr; 3645 else 3646 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3647 3648 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3649 } 3650 3651 /** 3652 * @brief Pushes a command into the ringbuffer 3653 * 3654 * @param rb DMUB ringbuffer 3655 * @param cmd The command to push 3656 * @return true if the ringbuffer was not full 3657 * @return false otherwise 3658 */ 3659 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3660 const union dmub_rb_cmd *cmd) 3661 { 3662 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3663 const uint64_t *src = (const uint64_t *)cmd; 3664 uint8_t i; 3665 3666 if (dmub_rb_full(rb)) 3667 return false; 3668 3669 // copying data 3670 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3671 *dst++ = *src++; 3672 3673 rb->wrpt += DMUB_RB_CMD_SIZE; 3674 3675 if (rb->wrpt >= rb->capacity) 3676 rb->wrpt %= rb->capacity; 3677 3678 return true; 3679 } 3680 3681 /** 3682 * @brief Pushes a command into the DMUB outbox ringbuffer 3683 * 3684 * @param rb DMUB outbox ringbuffer 3685 * @param cmd Outbox command 3686 * @return true if not full 3687 * @return false otherwise 3688 */ 3689 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3690 const union dmub_rb_out_cmd *cmd) 3691 { 3692 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3693 const uint8_t *src = (const uint8_t *)cmd; 3694 3695 if (dmub_rb_full(rb)) 3696 return false; 3697 3698 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3699 3700 rb->wrpt += DMUB_RB_CMD_SIZE; 3701 3702 if (rb->wrpt >= rb->capacity) 3703 rb->wrpt %= rb->capacity; 3704 3705 return true; 3706 } 3707 3708 /** 3709 * @brief Returns the next unprocessed command in the ringbuffer. 3710 * 3711 * @param rb DMUB ringbuffer 3712 * @param cmd The command to return 3713 * @return true if not empty 3714 * @return false otherwise 3715 */ 3716 static inline bool dmub_rb_front(struct dmub_rb *rb, 3717 union dmub_rb_cmd **cmd) 3718 { 3719 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3720 3721 if (dmub_rb_empty(rb)) 3722 return false; 3723 3724 *cmd = (union dmub_rb_cmd *)rb_cmd; 3725 3726 return true; 3727 } 3728 3729 /** 3730 * @brief Determines the next ringbuffer offset. 3731 * 3732 * @param rb DMUB inbox ringbuffer 3733 * @param num_cmds Number of commands 3734 * @param next_rptr The next offset in the ringbuffer 3735 */ 3736 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3737 uint32_t num_cmds, 3738 uint32_t *next_rptr) 3739 { 3740 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3741 3742 if (*next_rptr >= rb->capacity) 3743 *next_rptr %= rb->capacity; 3744 } 3745 3746 /** 3747 * @brief Returns a pointer to a command in the inbox. 3748 * 3749 * @param rb DMUB inbox ringbuffer 3750 * @param cmd The inbox command to return 3751 * @param rptr The ringbuffer offset 3752 * @return true if not empty 3753 * @return false otherwise 3754 */ 3755 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3756 union dmub_rb_cmd **cmd, 3757 uint32_t rptr) 3758 { 3759 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3760 3761 if (dmub_rb_empty(rb)) 3762 return false; 3763 3764 *cmd = (union dmub_rb_cmd *)rb_cmd; 3765 3766 return true; 3767 } 3768 3769 /** 3770 * @brief Returns the next unprocessed command in the outbox. 3771 * 3772 * @param rb DMUB outbox ringbuffer 3773 * @param cmd The outbox command to return 3774 * @return true if not empty 3775 * @return false otherwise 3776 */ 3777 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3778 union dmub_rb_out_cmd *cmd) 3779 { 3780 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3781 uint64_t *dst = (uint64_t *)cmd; 3782 uint8_t i; 3783 3784 if (dmub_rb_empty(rb)) 3785 return false; 3786 3787 // copying data 3788 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3789 *dst++ = *src++; 3790 3791 return true; 3792 } 3793 3794 /** 3795 * @brief Removes the front entry in the ringbuffer. 3796 * 3797 * @param rb DMUB ringbuffer 3798 * @return true if the command was removed 3799 * @return false if there were no commands 3800 */ 3801 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3802 { 3803 if (dmub_rb_empty(rb)) 3804 return false; 3805 3806 rb->rptr += DMUB_RB_CMD_SIZE; 3807 3808 if (rb->rptr >= rb->capacity) 3809 rb->rptr %= rb->capacity; 3810 3811 return true; 3812 } 3813 3814 /** 3815 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3816 * 3817 * Avoids a race condition where DMCUB accesses memory while 3818 * there are still writes in flight to framebuffer. 3819 * 3820 * @param rb DMUB ringbuffer 3821 */ 3822 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3823 { 3824 uint32_t rptr = rb->rptr; 3825 uint32_t wptr = rb->wrpt; 3826 3827 while (rptr != wptr) { 3828 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3829 uint8_t i; 3830 3831 /* Don't remove this. 3832 * The contents need to actually be read from the ring buffer 3833 * for this function to be effective. 3834 */ 3835 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3836 (void)READ_ONCE(*data++); 3837 3838 rptr += DMUB_RB_CMD_SIZE; 3839 if (rptr >= rb->capacity) 3840 rptr %= rb->capacity; 3841 } 3842 } 3843 3844 /** 3845 * @brief Initializes a DMCUB ringbuffer 3846 * 3847 * @param rb DMUB ringbuffer 3848 * @param init_params initial configuration for the ringbuffer 3849 */ 3850 static inline void dmub_rb_init(struct dmub_rb *rb, 3851 struct dmub_rb_init_params *init_params) 3852 { 3853 rb->base_address = init_params->base_address; 3854 rb->capacity = init_params->capacity; 3855 rb->rptr = init_params->read_ptr; 3856 rb->wrpt = init_params->write_ptr; 3857 } 3858 3859 /** 3860 * @brief Copies output data from in/out commands into the given command. 3861 * 3862 * @param rb DMUB ringbuffer 3863 * @param cmd Command to copy data into 3864 */ 3865 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3866 union dmub_rb_cmd *cmd) 3867 { 3868 // Copy rb entry back into command 3869 uint8_t *rd_ptr = (rb->rptr == 0) ? 3870 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3871 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3872 3873 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3874 } 3875 3876 #if defined(__cplusplus) 3877 } 3878 #endif 3879 3880 //============================================================================== 3881 //</DMUB_RB>==================================================================== 3882 //============================================================================== 3883 3884 #endif /* _DMUB_CMD_H_ */ 3885