1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 /* Firmware versioning. */ 48 #ifdef DMUB_EXPOSE_VERSION 49 #define DMUB_FW_VERSION_GIT_HASH 0x42c0e74b 50 #define DMUB_FW_VERSION_MAJOR 0 51 #define DMUB_FW_VERSION_MINOR 0 52 #define DMUB_FW_VERSION_REVISION 86 53 #define DMUB_FW_VERSION_TEST 0 54 #define DMUB_FW_VERSION_VBIOS 0 55 #define DMUB_FW_VERSION_HOTFIX 0 56 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 57 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 58 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 59 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 60 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 61 (DMUB_FW_VERSION_HOTFIX & 0x3F)) 62 63 #endif 64 65 //<DMUB_TYPES>================================================================== 66 /* Basic type definitions. */ 67 68 #define __forceinline inline 69 70 /** 71 * Flag from driver to indicate that ABM should be disabled gradually 72 * by slowly reversing all backlight programming and pixel compensation. 73 */ 74 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 75 76 /** 77 * Flag from driver to indicate that ABM should be disabled immediately 78 * and undo all backlight programming and pixel compensation. 79 */ 80 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 81 82 /** 83 * Flag from driver to indicate that ABM should be disabled immediately 84 * and keep the current backlight programming and pixel compensation. 85 */ 86 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 87 88 /** 89 * Flag from driver to set the current ABM pipe index or ABM operating level. 90 */ 91 #define SET_ABM_PIPE_NORMAL 1 92 93 /** 94 * Number of ambient light levels in ABM algorithm. 95 */ 96 #define NUM_AMBI_LEVEL 5 97 98 /** 99 * Number of operating/aggression levels in ABM algorithm. 100 */ 101 #define NUM_AGGR_LEVEL 4 102 103 /** 104 * Number of segments in the gamma curve. 105 */ 106 #define NUM_POWER_FN_SEGS 8 107 108 /** 109 * Number of segments in the backlight curve. 110 */ 111 #define NUM_BL_CURVE_SEGS 16 112 113 /* Maximum number of streams on any ASIC. */ 114 #define DMUB_MAX_STREAMS 6 115 116 /* Maximum number of planes on any ASIC. */ 117 #define DMUB_MAX_PLANES 6 118 119 /* Trace buffer offset for entry */ 120 #define TRACE_BUFFER_ENTRY_OFFSET 16 121 122 /** 123 * 124 * PSR control version legacy 125 */ 126 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 127 /** 128 * PSR control version with multi edp support 129 */ 130 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 131 132 133 /** 134 * ABM control version legacy 135 */ 136 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 137 138 /** 139 * ABM control version with multi edp support 140 */ 141 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 142 143 /** 144 * Physical framebuffer address location, 64-bit. 145 */ 146 #ifndef PHYSICAL_ADDRESS_LOC 147 #define PHYSICAL_ADDRESS_LOC union large_integer 148 #endif 149 150 /** 151 * OS/FW agnostic memcpy 152 */ 153 #ifndef dmub_memcpy 154 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 155 #endif 156 157 /** 158 * OS/FW agnostic memset 159 */ 160 #ifndef dmub_memset 161 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 162 #endif 163 164 #if defined(__cplusplus) 165 extern "C" { 166 #endif 167 168 /** 169 * OS/FW agnostic udelay 170 */ 171 #ifndef dmub_udelay 172 #define dmub_udelay(microseconds) udelay(microseconds) 173 #endif 174 175 /** 176 * Number of nanoseconds per DMUB tick. 177 * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default. 178 * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true. 179 */ 180 #define NS_PER_DMUB_TICK 10 181 182 /** 183 * union dmub_addr - DMUB physical/virtual 64-bit address. 184 */ 185 union dmub_addr { 186 struct { 187 uint32_t low_part; /**< Lower 32 bits */ 188 uint32_t high_part; /**< Upper 32 bits */ 189 } u; /*<< Low/high bit access */ 190 uint64_t quad_part; /*<< 64 bit address */ 191 }; 192 193 /** 194 * Flags that can be set by driver to change some PSR behaviour. 195 */ 196 union dmub_psr_debug_flags { 197 /** 198 * Debug flags. 199 */ 200 struct { 201 /** 202 * Enable visual confirm in FW. 203 */ 204 uint32_t visual_confirm : 1; 205 /** 206 * Use HW Lock Mgr object to do HW locking in FW. 207 */ 208 uint32_t use_hw_lock_mgr : 1; 209 210 /** 211 * Unused. 212 * TODO: Remove. 213 */ 214 uint32_t log_line_nums : 1; 215 } bitfields; 216 217 /** 218 * Union for debug flags. 219 */ 220 uint32_t u32All; 221 }; 222 223 /** 224 * DMUB feature capabilities. 225 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 226 */ 227 struct dmub_feature_caps { 228 /** 229 * Max PSR version supported by FW. 230 */ 231 uint8_t psr; 232 uint8_t reserved[7]; 233 }; 234 235 #if defined(__cplusplus) 236 } 237 #endif 238 239 //============================================================================== 240 //</DMUB_TYPES>================================================================= 241 //============================================================================== 242 //< DMUB_META>================================================================== 243 //============================================================================== 244 #pragma pack(push, 1) 245 246 /* Magic value for identifying dmub_fw_meta_info */ 247 #define DMUB_FW_META_MAGIC 0x444D5542 248 249 /* Offset from the end of the file to the dmub_fw_meta_info */ 250 #define DMUB_FW_META_OFFSET 0x24 251 252 /** 253 * struct dmub_fw_meta_info - metadata associated with fw binary 254 * 255 * NOTE: This should be considered a stable API. Fields should 256 * not be repurposed or reordered. New fields should be 257 * added instead to extend the structure. 258 * 259 * @magic_value: magic value identifying DMUB firmware meta info 260 * @fw_region_size: size of the firmware state region 261 * @trace_buffer_size: size of the tracebuffer region 262 * @fw_version: the firmware version information 263 * @dal_fw: 1 if the firmware is DAL 264 */ 265 struct dmub_fw_meta_info { 266 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 267 uint32_t fw_region_size; /**< size of the firmware state region */ 268 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 269 uint32_t fw_version; /**< the firmware version information */ 270 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 271 uint8_t reserved[3]; /**< padding bits */ 272 }; 273 274 /** 275 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 276 */ 277 union dmub_fw_meta { 278 struct dmub_fw_meta_info info; /**< metadata info */ 279 uint8_t reserved[64]; /**< padding bits */ 280 }; 281 282 #pragma pack(pop) 283 284 //============================================================================== 285 //< DMUB Trace Buffer>================================================================ 286 //============================================================================== 287 /** 288 * dmub_trace_code_t - firmware trace code, 32-bits 289 */ 290 typedef uint32_t dmub_trace_code_t; 291 292 /** 293 * struct dmcub_trace_buf_entry - Firmware trace entry 294 */ 295 struct dmcub_trace_buf_entry { 296 dmub_trace_code_t trace_code; /**< trace code for the event */ 297 uint32_t tick_count; /**< the tick count at time of trace */ 298 uint32_t param0; /**< trace defined parameter 0 */ 299 uint32_t param1; /**< trace defined parameter 1 */ 300 }; 301 302 //============================================================================== 303 //< DMUB_STATUS>================================================================ 304 //============================================================================== 305 306 /** 307 * DMCUB scratch registers can be used to determine firmware status. 308 * Current scratch register usage is as follows: 309 * 310 * SCRATCH0: FW Boot Status register 311 * SCRATCH5: LVTMA Status Register 312 * SCRATCH15: FW Boot Options register 313 */ 314 315 /** 316 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 317 */ 318 union dmub_fw_boot_status { 319 struct { 320 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 321 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 322 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 323 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 324 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 325 uint32_t reserved : 1; 326 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 327 328 } bits; /**< status bits */ 329 uint32_t all; /**< 32-bit access to status bits */ 330 }; 331 332 /** 333 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 334 */ 335 enum dmub_fw_boot_status_bit { 336 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 337 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 338 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 339 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 340 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 341 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 342 }; 343 344 /* Register bit definition for SCRATCH5 */ 345 union dmub_lvtma_status { 346 struct { 347 uint32_t psp_ok : 1; 348 uint32_t edp_on : 1; 349 uint32_t reserved : 30; 350 } bits; 351 uint32_t all; 352 }; 353 354 enum dmub_lvtma_status_bit { 355 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 356 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 357 }; 358 359 /** 360 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 361 */ 362 union dmub_fw_boot_options { 363 struct { 364 uint32_t pemu_env : 1; /**< 1 if PEMU */ 365 uint32_t fpga_env : 1; /**< 1 if FPGA */ 366 uint32_t optimized_init : 1; /**< 1 if optimized init */ 367 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 368 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 369 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 370 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 371 uint32_t reserved2: 1; /**< reserved for an unreleased feature */ 372 uint32_t reserved_unreleased1: 1; /**< reserved for an unreleased feature */ 373 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 374 uint32_t reserved_unreleased2: 1; /**< reserved for an unreleased feature */ 375 uint32_t reserved : 22; /**< reserved */ 376 } bits; /**< boot bits */ 377 uint32_t all; /**< 32-bit access to bits */ 378 }; 379 380 enum dmub_fw_boot_options_bit { 381 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 382 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 383 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 384 }; 385 386 //============================================================================== 387 //</DMUB_STATUS>================================================================ 388 //============================================================================== 389 //< DMUB_VBIOS>================================================================= 390 //============================================================================== 391 392 /* 393 * enum dmub_cmd_vbios_type - VBIOS commands. 394 * 395 * Command IDs should be treated as stable ABI. 396 * Do not reuse or modify IDs. 397 */ 398 enum dmub_cmd_vbios_type { 399 /** 400 * Configures the DIG encoder. 401 */ 402 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 403 /** 404 * Controls the PHY. 405 */ 406 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 407 /** 408 * Sets the pixel clock/symbol clock. 409 */ 410 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 411 /** 412 * Enables or disables power gating. 413 */ 414 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 415 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 416 }; 417 418 //============================================================================== 419 //</DMUB_VBIOS>================================================================= 420 //============================================================================== 421 //< DMUB_GPINT>================================================================= 422 //============================================================================== 423 424 /** 425 * The shifts and masks below may alternatively be used to format and read 426 * the command register bits. 427 */ 428 429 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 430 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 431 432 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 433 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 434 435 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 436 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 437 438 /** 439 * Command responses. 440 */ 441 442 /** 443 * Return response for DMUB_GPINT__STOP_FW command. 444 */ 445 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 446 447 /** 448 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 449 */ 450 union dmub_gpint_data_register { 451 struct { 452 uint32_t param : 16; /**< 16-bit parameter */ 453 uint32_t command_code : 12; /**< GPINT command */ 454 uint32_t status : 4; /**< Command status bit */ 455 } bits; /**< GPINT bit access */ 456 uint32_t all; /**< GPINT 32-bit access */ 457 }; 458 459 /* 460 * enum dmub_gpint_command - GPINT command to DMCUB FW 461 * 462 * Command IDs should be treated as stable ABI. 463 * Do not reuse or modify IDs. 464 */ 465 enum dmub_gpint_command { 466 /** 467 * Invalid command, ignored. 468 */ 469 DMUB_GPINT__INVALID_COMMAND = 0, 470 /** 471 * DESC: Queries the firmware version. 472 * RETURN: Firmware version. 473 */ 474 DMUB_GPINT__GET_FW_VERSION = 1, 475 /** 476 * DESC: Halts the firmware. 477 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 478 */ 479 DMUB_GPINT__STOP_FW = 2, 480 /** 481 * DESC: Get PSR state from FW. 482 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 483 */ 484 DMUB_GPINT__GET_PSR_STATE = 7, 485 /** 486 * DESC: Notifies DMCUB of the currently active streams. 487 * ARGS: Stream mask, 1 bit per active stream index. 488 */ 489 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 490 /** 491 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 492 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 493 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 494 * RETURN: PSR residency in milli-percent. 495 */ 496 DMUB_GPINT__PSR_RESIDENCY = 9, 497 498 /** 499 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 500 */ 501 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 502 }; 503 504 /** 505 * INBOX0 generic command definition 506 */ 507 union dmub_inbox0_cmd_common { 508 struct { 509 uint32_t command_code: 8; /**< INBOX0 command code */ 510 uint32_t param: 24; /**< 24-bit parameter */ 511 } bits; 512 uint32_t all; 513 }; 514 515 /** 516 * INBOX0 hw_lock command definition 517 */ 518 union dmub_inbox0_cmd_lock_hw { 519 struct { 520 uint32_t command_code: 8; 521 522 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 523 uint32_t hw_lock_client: 1; 524 525 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 526 uint32_t otg_inst: 3; 527 uint32_t opp_inst: 3; 528 uint32_t dig_inst: 3; 529 530 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 531 uint32_t lock_pipe: 1; 532 uint32_t lock_cursor: 1; 533 uint32_t lock_dig: 1; 534 uint32_t triple_buffer_lock: 1; 535 536 uint32_t lock: 1; /**< Lock */ 537 uint32_t should_release: 1; /**< Release */ 538 uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ 539 } bits; 540 uint32_t all; 541 }; 542 543 union dmub_inbox0_data_register { 544 union dmub_inbox0_cmd_common inbox0_cmd_common; 545 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 546 }; 547 548 enum dmub_inbox0_command { 549 /** 550 * DESC: Invalid command, ignored. 551 */ 552 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 553 /** 554 * DESC: Notification to acquire/release HW lock 555 * ARGS: 556 */ 557 DMUB_INBOX0_CMD__HW_LOCK = 1, 558 }; 559 //============================================================================== 560 //</DMUB_GPINT>================================================================= 561 //============================================================================== 562 //< DMUB_CMD>=================================================================== 563 //============================================================================== 564 565 /** 566 * Size in bytes of each DMUB command. 567 */ 568 #define DMUB_RB_CMD_SIZE 64 569 570 /** 571 * Maximum number of items in the DMUB ringbuffer. 572 */ 573 #define DMUB_RB_MAX_ENTRY 128 574 575 /** 576 * Ringbuffer size in bytes. 577 */ 578 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 579 580 /** 581 * REG_SET mask for reg offload. 582 */ 583 #define REG_SET_MASK 0xFFFF 584 585 /* 586 * enum dmub_cmd_type - DMUB inbox command. 587 * 588 * Command IDs should be treated as stable ABI. 589 * Do not reuse or modify IDs. 590 */ 591 enum dmub_cmd_type { 592 /** 593 * Invalid command. 594 */ 595 DMUB_CMD__NULL = 0, 596 /** 597 * Read modify write register sequence offload. 598 */ 599 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 600 /** 601 * Field update register sequence offload. 602 */ 603 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 604 /** 605 * Burst write sequence offload. 606 */ 607 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 608 /** 609 * Reg wait sequence offload. 610 */ 611 DMUB_CMD__REG_REG_WAIT = 4, 612 /** 613 * Workaround to avoid HUBP underflow during NV12 playback. 614 */ 615 DMUB_CMD__PLAT_54186_WA = 5, 616 /** 617 * Command type used to query FW feature caps. 618 */ 619 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 620 /** 621 * Command type used for all PSR commands. 622 */ 623 DMUB_CMD__PSR = 64, 624 /** 625 * Command type used for all MALL commands. 626 */ 627 DMUB_CMD__MALL = 65, 628 /** 629 * Command type used for all ABM commands. 630 */ 631 DMUB_CMD__ABM = 66, 632 /** 633 * Command type used for HW locking in FW. 634 */ 635 DMUB_CMD__HW_LOCK = 69, 636 /** 637 * Command type used to access DP AUX. 638 */ 639 DMUB_CMD__DP_AUX_ACCESS = 70, 640 /** 641 * Command type used for OUTBOX1 notification enable 642 */ 643 DMUB_CMD__OUTBOX1_ENABLE = 71, 644 /** 645 * Command type used for all idle optimization commands. 646 */ 647 DMUB_CMD__IDLE_OPT = 72, 648 /** 649 * Command type used for all clock manager commands. 650 */ 651 DMUB_CMD__CLK_MGR = 73, 652 /** 653 * Command type used for all panel control commands. 654 */ 655 DMUB_CMD__PANEL_CNTL = 74, 656 /** 657 * Command type used for EDID CEA parsing 658 */ 659 DMUB_CMD__EDID_CEA = 79, 660 /** 661 * Command type used for all VBIOS interface commands. 662 */ 663 DMUB_CMD__VBIOS = 128, 664 }; 665 666 /** 667 * enum dmub_out_cmd_type - DMUB outbox commands. 668 */ 669 enum dmub_out_cmd_type { 670 /** 671 * Invalid outbox command, ignored. 672 */ 673 DMUB_OUT_CMD__NULL = 0, 674 /** 675 * Command type used for DP AUX Reply data notification 676 */ 677 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 678 }; 679 680 #pragma pack(push, 1) 681 682 /** 683 * struct dmub_cmd_header - Common command header fields. 684 */ 685 struct dmub_cmd_header { 686 unsigned int type : 8; /**< command type */ 687 unsigned int sub_type : 8; /**< command sub type */ 688 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 689 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 690 unsigned int reserved0 : 6; /**< reserved bits */ 691 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 692 unsigned int reserved1 : 2; /**< reserved bits */ 693 }; 694 695 /* 696 * struct dmub_cmd_read_modify_write_sequence - Read modify write 697 * 698 * 60 payload bytes can hold up to 5 sets of read modify writes, 699 * each take 3 dwords. 700 * 701 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 702 * 703 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 704 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 705 */ 706 struct dmub_cmd_read_modify_write_sequence { 707 uint32_t addr; /**< register address */ 708 uint32_t modify_mask; /**< modify mask */ 709 uint32_t modify_value; /**< modify value */ 710 }; 711 712 /** 713 * Maximum number of ops in read modify write sequence. 714 */ 715 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 716 717 /** 718 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 719 */ 720 struct dmub_rb_cmd_read_modify_write { 721 struct dmub_cmd_header header; /**< command header */ 722 /** 723 * Read modify write sequence. 724 */ 725 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 726 }; 727 728 /* 729 * Update a register with specified masks and values sequeunce 730 * 731 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 732 * 733 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 734 * 735 * 736 * USE CASE: 737 * 1. auto-increment register where additional read would update pointer and produce wrong result 738 * 2. toggle a bit without read in the middle 739 */ 740 741 struct dmub_cmd_reg_field_update_sequence { 742 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 743 uint32_t modify_value; /**< value to update with */ 744 }; 745 746 /** 747 * Maximum number of ops in field update sequence. 748 */ 749 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 750 751 /** 752 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 753 */ 754 struct dmub_rb_cmd_reg_field_update_sequence { 755 struct dmub_cmd_header header; /**< command header */ 756 uint32_t addr; /**< register address */ 757 /** 758 * Field update sequence. 759 */ 760 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 761 }; 762 763 764 /** 765 * Maximum number of burst write values. 766 */ 767 #define DMUB_BURST_WRITE_VALUES__MAX 14 768 769 /* 770 * struct dmub_rb_cmd_burst_write - Burst write 771 * 772 * support use case such as writing out LUTs. 773 * 774 * 60 payload bytes can hold up to 14 values to write to given address 775 * 776 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 777 */ 778 struct dmub_rb_cmd_burst_write { 779 struct dmub_cmd_header header; /**< command header */ 780 uint32_t addr; /**< register start address */ 781 /** 782 * Burst write register values. 783 */ 784 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 785 }; 786 787 /** 788 * struct dmub_rb_cmd_common - Common command header 789 */ 790 struct dmub_rb_cmd_common { 791 struct dmub_cmd_header header; /**< command header */ 792 /** 793 * Padding to RB_CMD_SIZE 794 */ 795 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 796 }; 797 798 /** 799 * struct dmub_cmd_reg_wait_data - Register wait data 800 */ 801 struct dmub_cmd_reg_wait_data { 802 uint32_t addr; /**< Register address */ 803 uint32_t mask; /**< Mask for register bits */ 804 uint32_t condition_field_value; /**< Value to wait for */ 805 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 806 }; 807 808 /** 809 * struct dmub_rb_cmd_reg_wait - Register wait command 810 */ 811 struct dmub_rb_cmd_reg_wait { 812 struct dmub_cmd_header header; /**< Command header */ 813 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 814 }; 815 816 /** 817 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 818 * 819 * Reprograms surface parameters to avoid underflow. 820 */ 821 struct dmub_cmd_PLAT_54186_wa { 822 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 823 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 824 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 825 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 826 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 827 struct { 828 uint8_t hubp_inst : 4; /**< HUBP instance */ 829 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 830 uint8_t immediate :1; /**< Immediate flip */ 831 uint8_t vmid : 4; /**< VMID */ 832 uint8_t grph_stereo : 1; /**< 1 if stereo */ 833 uint32_t reserved : 21; /**< Reserved */ 834 } flip_params; /**< Pageflip parameters */ 835 uint32_t reserved[9]; /**< Reserved bits */ 836 }; 837 838 /** 839 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 840 */ 841 struct dmub_rb_cmd_PLAT_54186_wa { 842 struct dmub_cmd_header header; /**< Command header */ 843 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 844 }; 845 846 /** 847 * struct dmub_rb_cmd_mall - MALL command data. 848 */ 849 struct dmub_rb_cmd_mall { 850 struct dmub_cmd_header header; /**< Common command header */ 851 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 852 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 853 uint32_t tmr_delay; /**< Timer delay */ 854 uint32_t tmr_scale; /**< Timer scale */ 855 uint16_t cursor_width; /**< Cursor width in pixels */ 856 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 857 uint16_t cursor_height; /**< Cursor height in pixels */ 858 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 859 uint8_t debug_bits; /**< Debug bits */ 860 861 uint8_t reserved1; /**< Reserved bits */ 862 uint8_t reserved2; /**< Reserved bits */ 863 }; 864 865 /** 866 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 867 */ 868 enum dmub_cmd_idle_opt_type { 869 /** 870 * DCN hardware restore. 871 */ 872 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 873 874 /** 875 * DCN hardware save. 876 */ 877 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 878 }; 879 880 /** 881 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 882 */ 883 struct dmub_rb_cmd_idle_opt_dcn_restore { 884 struct dmub_cmd_header header; /**< header */ 885 }; 886 887 /** 888 * struct dmub_clocks - Clock update notification. 889 */ 890 struct dmub_clocks { 891 uint32_t dispclk_khz; /**< dispclk kHz */ 892 uint32_t dppclk_khz; /**< dppclk kHz */ 893 uint32_t dcfclk_khz; /**< dcfclk kHz */ 894 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 895 }; 896 897 /** 898 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 899 */ 900 enum dmub_cmd_clk_mgr_type { 901 /** 902 * Notify DMCUB of clock update. 903 */ 904 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 905 }; 906 907 /** 908 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 909 */ 910 struct dmub_rb_cmd_clk_mgr_notify_clocks { 911 struct dmub_cmd_header header; /**< header */ 912 struct dmub_clocks clocks; /**< clock data */ 913 }; 914 915 /** 916 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 917 */ 918 struct dmub_cmd_digx_encoder_control_data { 919 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 920 }; 921 922 /** 923 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 924 */ 925 struct dmub_rb_cmd_digx_encoder_control { 926 struct dmub_cmd_header header; /**< header */ 927 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 928 }; 929 930 /** 931 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 932 */ 933 struct dmub_cmd_set_pixel_clock_data { 934 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 935 }; 936 937 /** 938 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 939 */ 940 struct dmub_rb_cmd_set_pixel_clock { 941 struct dmub_cmd_header header; /**< header */ 942 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 943 }; 944 945 /** 946 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 947 */ 948 struct dmub_cmd_enable_disp_power_gating_data { 949 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 950 }; 951 952 /** 953 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 954 */ 955 struct dmub_rb_cmd_enable_disp_power_gating { 956 struct dmub_cmd_header header; /**< header */ 957 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 958 }; 959 960 /** 961 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 962 */ 963 struct dmub_dig_transmitter_control_data_v1_7 { 964 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 965 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 966 union { 967 uint8_t digmode; /**< enum atom_encode_mode_def */ 968 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 969 } mode_laneset; 970 uint8_t lanenum; /**< Number of lanes */ 971 union { 972 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 973 } symclk_units; 974 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 975 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 976 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 977 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 978 uint8_t reserved1; /**< For future use */ 979 uint8_t reserved2[3]; /**< For future use */ 980 uint32_t reserved3[11]; /**< For future use */ 981 }; 982 983 /** 984 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 985 */ 986 union dmub_cmd_dig1_transmitter_control_data { 987 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 988 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 989 }; 990 991 /** 992 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 993 */ 994 struct dmub_rb_cmd_dig1_transmitter_control { 995 struct dmub_cmd_header header; /**< header */ 996 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 997 }; 998 999 /** 1000 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1001 */ 1002 struct dmub_rb_cmd_dpphy_init { 1003 struct dmub_cmd_header header; /**< header */ 1004 uint8_t reserved[60]; /**< reserved bits */ 1005 }; 1006 1007 /** 1008 * enum dp_aux_request_action - DP AUX request command listing. 1009 * 1010 * 4 AUX request command bits are shifted to high nibble. 1011 */ 1012 enum dp_aux_request_action { 1013 /** I2C-over-AUX write request */ 1014 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1015 /** I2C-over-AUX read request */ 1016 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1017 /** I2C-over-AUX write status request */ 1018 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1019 /** I2C-over-AUX write request with MOT=1 */ 1020 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1021 /** I2C-over-AUX read request with MOT=1 */ 1022 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1023 /** I2C-over-AUX write status request with MOT=1 */ 1024 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1025 /** Native AUX write request */ 1026 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1027 /** Native AUX read request */ 1028 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1029 }; 1030 1031 /** 1032 * enum aux_return_code_type - DP AUX process return code listing. 1033 */ 1034 enum aux_return_code_type { 1035 /** AUX process succeeded */ 1036 AUX_RET_SUCCESS = 0, 1037 /** AUX process failed with unknown reason */ 1038 AUX_RET_ERROR_UNKNOWN, 1039 /** AUX process completed with invalid reply */ 1040 AUX_RET_ERROR_INVALID_REPLY, 1041 /** AUX process timed out */ 1042 AUX_RET_ERROR_TIMEOUT, 1043 /** HPD was low during AUX process */ 1044 AUX_RET_ERROR_HPD_DISCON, 1045 /** Failed to acquire AUX engine */ 1046 AUX_RET_ERROR_ENGINE_ACQUIRE, 1047 /** AUX request not supported */ 1048 AUX_RET_ERROR_INVALID_OPERATION, 1049 /** AUX process not available */ 1050 AUX_RET_ERROR_PROTOCOL_ERROR, 1051 }; 1052 1053 /** 1054 * enum aux_channel_type - DP AUX channel type listing. 1055 */ 1056 enum aux_channel_type { 1057 /** AUX thru Legacy DP AUX */ 1058 AUX_CHANNEL_LEGACY_DDC, 1059 /** AUX thru DPIA DP tunneling */ 1060 AUX_CHANNEL_DPIA 1061 }; 1062 1063 /** 1064 * struct aux_transaction_parameters - DP AUX request transaction data 1065 */ 1066 struct aux_transaction_parameters { 1067 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1068 uint8_t action; /**< enum dp_aux_request_action */ 1069 uint8_t length; /**< DP AUX request data length */ 1070 uint8_t reserved; /**< For future use */ 1071 uint32_t address; /**< DP AUX address */ 1072 uint8_t data[16]; /**< DP AUX write data */ 1073 }; 1074 1075 /** 1076 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1077 */ 1078 struct dmub_cmd_dp_aux_control_data { 1079 uint8_t instance; /**< AUX instance or DPIA instance */ 1080 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1081 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1082 uint8_t reserved0; /**< For future use */ 1083 uint16_t timeout; /**< timeout time in us */ 1084 uint16_t reserved1; /**< For future use */ 1085 enum aux_channel_type type; /**< enum aux_channel_type */ 1086 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1087 }; 1088 1089 /** 1090 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1091 */ 1092 struct dmub_rb_cmd_dp_aux_access { 1093 /** 1094 * Command header. 1095 */ 1096 struct dmub_cmd_header header; 1097 /** 1098 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1099 */ 1100 struct dmub_cmd_dp_aux_control_data aux_control; 1101 }; 1102 1103 /** 1104 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1105 */ 1106 struct dmub_rb_cmd_outbox1_enable { 1107 /** 1108 * Command header. 1109 */ 1110 struct dmub_cmd_header header; 1111 /** 1112 * enable: 0x0 -> disable outbox1 notification (default value) 1113 * 0x1 -> enable outbox1 notification 1114 */ 1115 uint32_t enable; 1116 }; 1117 1118 /* DP AUX Reply command - OutBox Cmd */ 1119 /** 1120 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1121 */ 1122 struct aux_reply_data { 1123 /** 1124 * Aux cmd 1125 */ 1126 uint8_t command; 1127 /** 1128 * Aux reply data length (max: 16 bytes) 1129 */ 1130 uint8_t length; 1131 /** 1132 * Alignment only 1133 */ 1134 uint8_t pad[2]; 1135 /** 1136 * Aux reply data 1137 */ 1138 uint8_t data[16]; 1139 }; 1140 1141 /** 1142 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1143 */ 1144 struct aux_reply_control_data { 1145 /** 1146 * Reserved for future use 1147 */ 1148 uint32_t handle; 1149 /** 1150 * Aux Instance 1151 */ 1152 uint8_t instance; 1153 /** 1154 * Aux transaction result: definition in enum aux_return_code_type 1155 */ 1156 uint8_t result; 1157 /** 1158 * Alignment only 1159 */ 1160 uint16_t pad; 1161 }; 1162 1163 /** 1164 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1165 */ 1166 struct dmub_rb_cmd_dp_aux_reply { 1167 /** 1168 * Command header. 1169 */ 1170 struct dmub_cmd_header header; 1171 /** 1172 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1173 */ 1174 struct aux_reply_control_data control; 1175 /** 1176 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1177 */ 1178 struct aux_reply_data reply_data; 1179 }; 1180 1181 /* DP HPD Notify command - OutBox Cmd */ 1182 /** 1183 * DP HPD Type 1184 */ 1185 enum dp_hpd_type { 1186 /** 1187 * Normal DP HPD 1188 */ 1189 DP_HPD = 0, 1190 /** 1191 * DP HPD short pulse 1192 */ 1193 DP_IRQ 1194 }; 1195 1196 /** 1197 * DP HPD Status 1198 */ 1199 enum dp_hpd_status { 1200 /** 1201 * DP_HPD status low 1202 */ 1203 DP_HPD_UNPLUG = 0, 1204 /** 1205 * DP_HPD status high 1206 */ 1207 DP_HPD_PLUG 1208 }; 1209 1210 /** 1211 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1212 */ 1213 struct dp_hpd_data { 1214 /** 1215 * DP HPD instance 1216 */ 1217 uint8_t instance; 1218 /** 1219 * HPD type 1220 */ 1221 uint8_t hpd_type; 1222 /** 1223 * HPD status: only for type: DP_HPD to indicate status 1224 */ 1225 uint8_t hpd_status; 1226 /** 1227 * Alignment only 1228 */ 1229 uint8_t pad; 1230 }; 1231 1232 /** 1233 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1234 */ 1235 struct dmub_rb_cmd_dp_hpd_notify { 1236 /** 1237 * Command header. 1238 */ 1239 struct dmub_cmd_header header; 1240 /** 1241 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1242 */ 1243 struct dp_hpd_data hpd_data; 1244 }; 1245 1246 /* 1247 * Command IDs should be treated as stable ABI. 1248 * Do not reuse or modify IDs. 1249 */ 1250 1251 /** 1252 * PSR command sub-types. 1253 */ 1254 enum dmub_cmd_psr_type { 1255 /** 1256 * Set PSR version support. 1257 */ 1258 DMUB_CMD__PSR_SET_VERSION = 0, 1259 /** 1260 * Copy driver-calculated parameters to PSR state. 1261 */ 1262 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1263 /** 1264 * Enable PSR. 1265 */ 1266 DMUB_CMD__PSR_ENABLE = 2, 1267 1268 /** 1269 * Disable PSR. 1270 */ 1271 DMUB_CMD__PSR_DISABLE = 3, 1272 1273 /** 1274 * Set PSR level. 1275 * PSR level is a 16-bit value dicated by driver that 1276 * will enable/disable different functionality. 1277 */ 1278 DMUB_CMD__PSR_SET_LEVEL = 4, 1279 1280 /** 1281 * Forces PSR enabled until an explicit PSR disable call. 1282 */ 1283 DMUB_CMD__PSR_FORCE_STATIC = 5, 1284 }; 1285 1286 /** 1287 * PSR versions. 1288 */ 1289 enum psr_version { 1290 /** 1291 * PSR version 1. 1292 */ 1293 PSR_VERSION_1 = 0, 1294 /** 1295 * PSR not supported. 1296 */ 1297 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1298 }; 1299 1300 /** 1301 * enum dmub_cmd_mall_type - MALL commands 1302 */ 1303 enum dmub_cmd_mall_type { 1304 /** 1305 * Allows display refresh from MALL. 1306 */ 1307 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1308 /** 1309 * Disallows display refresh from MALL. 1310 */ 1311 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1312 /** 1313 * Cursor copy for MALL. 1314 */ 1315 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1316 /** 1317 * Controls DF requests. 1318 */ 1319 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1320 }; 1321 1322 1323 /** 1324 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1325 */ 1326 struct dmub_cmd_psr_copy_settings_data { 1327 /** 1328 * Flags that can be set by driver to change some PSR behaviour. 1329 */ 1330 union dmub_psr_debug_flags debug; 1331 /** 1332 * 16-bit value dicated by driver that will enable/disable different functionality. 1333 */ 1334 uint16_t psr_level; 1335 /** 1336 * DPP HW instance. 1337 */ 1338 uint8_t dpp_inst; 1339 /** 1340 * MPCC HW instance. 1341 * Not used in dmub fw, 1342 * dmub fw will get active opp by reading odm registers. 1343 */ 1344 uint8_t mpcc_inst; 1345 /** 1346 * OPP HW instance. 1347 * Not used in dmub fw, 1348 * dmub fw will get active opp by reading odm registers. 1349 */ 1350 uint8_t opp_inst; 1351 /** 1352 * OTG HW instance. 1353 */ 1354 uint8_t otg_inst; 1355 /** 1356 * DIG FE HW instance. 1357 */ 1358 uint8_t digfe_inst; 1359 /** 1360 * DIG BE HW instance. 1361 */ 1362 uint8_t digbe_inst; 1363 /** 1364 * DP PHY HW instance. 1365 */ 1366 uint8_t dpphy_inst; 1367 /** 1368 * AUX HW instance. 1369 */ 1370 uint8_t aux_inst; 1371 /** 1372 * Determines if SMU optimzations are enabled/disabled. 1373 */ 1374 uint8_t smu_optimizations_en; 1375 /** 1376 * Unused. 1377 * TODO: Remove. 1378 */ 1379 uint8_t frame_delay; 1380 /** 1381 * If RFB setup time is greater than the total VBLANK time, 1382 * it is not possible for the sink to capture the video frame 1383 * in the same frame the SDP is sent. In this case, 1384 * the frame capture indication bit should be set and an extra 1385 * static frame should be transmitted to the sink. 1386 */ 1387 uint8_t frame_cap_ind; 1388 /** 1389 * Explicit padding to 4 byte boundary. 1390 */ 1391 uint8_t pad[2]; 1392 /** 1393 * Multi-display optimizations are implemented on certain ASICs. 1394 */ 1395 uint8_t multi_disp_optimizations_en; 1396 /** 1397 * The last possible line SDP may be transmitted without violating 1398 * the RFB setup time or entering the active video frame. 1399 */ 1400 uint16_t init_sdp_deadline; 1401 /** 1402 * Explicit padding to 4 byte boundary. 1403 */ 1404 uint16_t pad2; 1405 /** 1406 * Length of each horizontal line in us. 1407 */ 1408 uint32_t line_time_in_us; 1409 /** 1410 * FEC enable status in driver 1411 */ 1412 uint8_t fec_enable_status; 1413 /** 1414 * FEC re-enable delay when PSR exit. 1415 * unit is 100us, range form 0~255(0xFF). 1416 */ 1417 uint8_t fec_enable_delay_in100us; 1418 /** 1419 * PSR control version. 1420 */ 1421 uint8_t cmd_version; 1422 /** 1423 * Panel Instance. 1424 * Panel isntance to identify which psr_state to use 1425 * Currently the support is only for 0 or 1 1426 */ 1427 uint8_t panel_inst; 1428 /** 1429 * Explicit padding to 4 byte boundary. 1430 */ 1431 uint8_t pad3[4]; 1432 }; 1433 1434 /** 1435 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1436 */ 1437 struct dmub_rb_cmd_psr_copy_settings { 1438 /** 1439 * Command header. 1440 */ 1441 struct dmub_cmd_header header; 1442 /** 1443 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1444 */ 1445 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1446 }; 1447 1448 /** 1449 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1450 */ 1451 struct dmub_cmd_psr_set_level_data { 1452 /** 1453 * 16-bit value dicated by driver that will enable/disable different functionality. 1454 */ 1455 uint16_t psr_level; 1456 /** 1457 * PSR control version. 1458 */ 1459 uint8_t cmd_version; 1460 /** 1461 * Panel Instance. 1462 * Panel isntance to identify which psr_state to use 1463 * Currently the support is only for 0 or 1 1464 */ 1465 uint8_t panel_inst; 1466 }; 1467 1468 /** 1469 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1470 */ 1471 struct dmub_rb_cmd_psr_set_level { 1472 /** 1473 * Command header. 1474 */ 1475 struct dmub_cmd_header header; 1476 /** 1477 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1478 */ 1479 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1480 }; 1481 1482 struct dmub_rb_cmd_psr_enable_data { 1483 /** 1484 * PSR control version. 1485 */ 1486 uint8_t cmd_version; 1487 /** 1488 * Panel Instance. 1489 * Panel isntance to identify which psr_state to use 1490 * Currently the support is only for 0 or 1 1491 */ 1492 uint8_t panel_inst; 1493 /** 1494 * Explicit padding to 4 byte boundary. 1495 */ 1496 uint8_t pad[2]; 1497 }; 1498 1499 /** 1500 * Definition of a DMUB_CMD__PSR_ENABLE command. 1501 * PSR enable/disable is controlled using the sub_type. 1502 */ 1503 struct dmub_rb_cmd_psr_enable { 1504 /** 1505 * Command header. 1506 */ 1507 struct dmub_cmd_header header; 1508 1509 struct dmub_rb_cmd_psr_enable_data data; 1510 }; 1511 1512 /** 1513 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1514 */ 1515 struct dmub_cmd_psr_set_version_data { 1516 /** 1517 * PSR version that FW should implement. 1518 */ 1519 enum psr_version version; 1520 /** 1521 * PSR control version. 1522 */ 1523 uint8_t cmd_version; 1524 /** 1525 * Panel Instance. 1526 * Panel isntance to identify which psr_state to use 1527 * Currently the support is only for 0 or 1 1528 */ 1529 uint8_t panel_inst; 1530 /** 1531 * Explicit padding to 4 byte boundary. 1532 */ 1533 uint8_t pad[2]; 1534 }; 1535 1536 /** 1537 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1538 */ 1539 struct dmub_rb_cmd_psr_set_version { 1540 /** 1541 * Command header. 1542 */ 1543 struct dmub_cmd_header header; 1544 /** 1545 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1546 */ 1547 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1548 }; 1549 1550 struct dmub_cmd_psr_force_static_data { 1551 /** 1552 * PSR control version. 1553 */ 1554 uint8_t cmd_version; 1555 /** 1556 * Panel Instance. 1557 * Panel isntance to identify which psr_state to use 1558 * Currently the support is only for 0 or 1 1559 */ 1560 uint8_t panel_inst; 1561 /** 1562 * Explicit padding to 4 byte boundary. 1563 */ 1564 uint8_t pad[2]; 1565 }; 1566 1567 /** 1568 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1569 */ 1570 struct dmub_rb_cmd_psr_force_static { 1571 /** 1572 * Command header. 1573 */ 1574 struct dmub_cmd_header header; 1575 /** 1576 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1577 */ 1578 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1579 }; 1580 1581 /** 1582 * Set of HW components that can be locked. 1583 * 1584 * Note: If updating with more HW components, fields 1585 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1586 */ 1587 union dmub_hw_lock_flags { 1588 /** 1589 * Set of HW components that can be locked. 1590 */ 1591 struct { 1592 /** 1593 * Lock/unlock OTG master update lock. 1594 */ 1595 uint8_t lock_pipe : 1; 1596 /** 1597 * Lock/unlock cursor. 1598 */ 1599 uint8_t lock_cursor : 1; 1600 /** 1601 * Lock/unlock global update lock. 1602 */ 1603 uint8_t lock_dig : 1; 1604 /** 1605 * Triple buffer lock requires additional hw programming to usual OTG master lock. 1606 */ 1607 uint8_t triple_buffer_lock : 1; 1608 } bits; 1609 1610 /** 1611 * Union for HW Lock flags. 1612 */ 1613 uint8_t u8All; 1614 }; 1615 1616 /** 1617 * Instances of HW to be locked. 1618 * 1619 * Note: If updating with more HW components, fields 1620 * in dmub_inbox0_cmd_lock_hw must be updated to match. 1621 */ 1622 struct dmub_hw_lock_inst_flags { 1623 /** 1624 * OTG HW instance for OTG master update lock. 1625 */ 1626 uint8_t otg_inst; 1627 /** 1628 * OPP instance for cursor lock. 1629 */ 1630 uint8_t opp_inst; 1631 /** 1632 * OTG HW instance for global update lock. 1633 * TODO: Remove, and re-use otg_inst. 1634 */ 1635 uint8_t dig_inst; 1636 /** 1637 * Explicit pad to 4 byte boundary. 1638 */ 1639 uint8_t pad; 1640 }; 1641 1642 /** 1643 * Clients that can acquire the HW Lock Manager. 1644 * 1645 * Note: If updating with more clients, fields in 1646 * dmub_inbox0_cmd_lock_hw must be updated to match. 1647 */ 1648 enum hw_lock_client { 1649 /** 1650 * Driver is the client of HW Lock Manager. 1651 */ 1652 HW_LOCK_CLIENT_DRIVER = 0, 1653 /** 1654 * Invalid client. 1655 */ 1656 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1657 }; 1658 1659 /** 1660 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1661 */ 1662 struct dmub_cmd_lock_hw_data { 1663 /** 1664 * Specifies the client accessing HW Lock Manager. 1665 */ 1666 enum hw_lock_client client; 1667 /** 1668 * HW instances to be locked. 1669 */ 1670 struct dmub_hw_lock_inst_flags inst_flags; 1671 /** 1672 * Which components to be locked. 1673 */ 1674 union dmub_hw_lock_flags hw_locks; 1675 /** 1676 * Specifies lock/unlock. 1677 */ 1678 uint8_t lock; 1679 /** 1680 * HW can be unlocked separately from releasing the HW Lock Mgr. 1681 * This flag is set if the client wishes to release the object. 1682 */ 1683 uint8_t should_release; 1684 /** 1685 * Explicit padding to 4 byte boundary. 1686 */ 1687 uint8_t pad; 1688 }; 1689 1690 /** 1691 * Definition of a DMUB_CMD__HW_LOCK command. 1692 * Command is used by driver and FW. 1693 */ 1694 struct dmub_rb_cmd_lock_hw { 1695 /** 1696 * Command header. 1697 */ 1698 struct dmub_cmd_header header; 1699 /** 1700 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 1701 */ 1702 struct dmub_cmd_lock_hw_data lock_hw_data; 1703 }; 1704 1705 /** 1706 * ABM command sub-types. 1707 */ 1708 enum dmub_cmd_abm_type { 1709 /** 1710 * Initialize parameters for ABM algorithm. 1711 * Data is passed through an indirect buffer. 1712 */ 1713 DMUB_CMD__ABM_INIT_CONFIG = 0, 1714 /** 1715 * Set OTG and panel HW instance. 1716 */ 1717 DMUB_CMD__ABM_SET_PIPE = 1, 1718 /** 1719 * Set user requested backklight level. 1720 */ 1721 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 1722 /** 1723 * Set ABM operating/aggression level. 1724 */ 1725 DMUB_CMD__ABM_SET_LEVEL = 3, 1726 /** 1727 * Set ambient light level. 1728 */ 1729 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 1730 /** 1731 * Enable/disable fractional duty cycle for backlight PWM. 1732 */ 1733 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1734 1735 /** 1736 * unregister vertical interrupt after steady state is reached 1737 */ 1738 DMUB_CMD__ABM_PAUSE = 6, 1739 }; 1740 1741 /** 1742 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 1743 * Requirements: 1744 * - Padded explicitly to 32-bit boundary. 1745 * - Must ensure this structure matches the one on driver-side, 1746 * otherwise it won't be aligned. 1747 */ 1748 struct abm_config_table { 1749 /** 1750 * Gamma curve thresholds, used for crgb conversion. 1751 */ 1752 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 1753 /** 1754 * Gamma curve offsets, used for crgb conversion. 1755 */ 1756 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 1757 /** 1758 * Gamma curve slopes, used for crgb conversion. 1759 */ 1760 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 1761 /** 1762 * Custom backlight curve thresholds. 1763 */ 1764 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 1765 /** 1766 * Custom backlight curve offsets. 1767 */ 1768 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 1769 /** 1770 * Ambient light thresholds. 1771 */ 1772 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 1773 /** 1774 * Minimum programmable backlight. 1775 */ 1776 uint16_t min_abm_backlight; // 122B 1777 /** 1778 * Minimum reduction values. 1779 */ 1780 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 1781 /** 1782 * Maximum reduction values. 1783 */ 1784 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 1785 /** 1786 * Bright positive gain. 1787 */ 1788 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 1789 /** 1790 * Dark negative gain. 1791 */ 1792 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 1793 /** 1794 * Hybrid factor. 1795 */ 1796 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 1797 /** 1798 * Contrast factor. 1799 */ 1800 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 1801 /** 1802 * Deviation gain. 1803 */ 1804 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 1805 /** 1806 * Minimum knee. 1807 */ 1808 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 1809 /** 1810 * Maximum knee. 1811 */ 1812 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 1813 /** 1814 * Unused. 1815 */ 1816 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 1817 /** 1818 * Explicit padding to 4 byte boundary. 1819 */ 1820 uint8_t pad3[3]; // 229B 1821 /** 1822 * Backlight ramp reduction. 1823 */ 1824 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 1825 /** 1826 * Backlight ramp start. 1827 */ 1828 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 1829 }; 1830 1831 /** 1832 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1833 */ 1834 struct dmub_cmd_abm_set_pipe_data { 1835 /** 1836 * OTG HW instance. 1837 */ 1838 uint8_t otg_inst; 1839 1840 /** 1841 * Panel Control HW instance. 1842 */ 1843 uint8_t panel_inst; 1844 1845 /** 1846 * Controls how ABM will interpret a set pipe or set level command. 1847 */ 1848 uint8_t set_pipe_option; 1849 1850 /** 1851 * Unused. 1852 * TODO: Remove. 1853 */ 1854 uint8_t ramping_boundary; 1855 }; 1856 1857 /** 1858 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 1859 */ 1860 struct dmub_rb_cmd_abm_set_pipe { 1861 /** 1862 * Command header. 1863 */ 1864 struct dmub_cmd_header header; 1865 1866 /** 1867 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 1868 */ 1869 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 1870 }; 1871 1872 /** 1873 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1874 */ 1875 struct dmub_cmd_abm_set_backlight_data { 1876 /** 1877 * Number of frames to ramp to backlight user level. 1878 */ 1879 uint32_t frame_ramp; 1880 1881 /** 1882 * Requested backlight level from user. 1883 */ 1884 uint32_t backlight_user_level; 1885 1886 /** 1887 * ABM control version. 1888 */ 1889 uint8_t version; 1890 1891 /** 1892 * Panel Control HW instance mask. 1893 * Bit 0 is Panel Control HW instance 0. 1894 * Bit 1 is Panel Control HW instance 1. 1895 */ 1896 uint8_t panel_mask; 1897 1898 /** 1899 * Explicit padding to 4 byte boundary. 1900 */ 1901 uint8_t pad[2]; 1902 }; 1903 1904 /** 1905 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 1906 */ 1907 struct dmub_rb_cmd_abm_set_backlight { 1908 /** 1909 * Command header. 1910 */ 1911 struct dmub_cmd_header header; 1912 1913 /** 1914 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 1915 */ 1916 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 1917 }; 1918 1919 /** 1920 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1921 */ 1922 struct dmub_cmd_abm_set_level_data { 1923 /** 1924 * Set current ABM operating/aggression level. 1925 */ 1926 uint32_t level; 1927 1928 /** 1929 * ABM control version. 1930 */ 1931 uint8_t version; 1932 1933 /** 1934 * Panel Control HW instance mask. 1935 * Bit 0 is Panel Control HW instance 0. 1936 * Bit 1 is Panel Control HW instance 1. 1937 */ 1938 uint8_t panel_mask; 1939 1940 /** 1941 * Explicit padding to 4 byte boundary. 1942 */ 1943 uint8_t pad[2]; 1944 }; 1945 1946 /** 1947 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 1948 */ 1949 struct dmub_rb_cmd_abm_set_level { 1950 /** 1951 * Command header. 1952 */ 1953 struct dmub_cmd_header header; 1954 1955 /** 1956 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 1957 */ 1958 struct dmub_cmd_abm_set_level_data abm_set_level_data; 1959 }; 1960 1961 /** 1962 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1963 */ 1964 struct dmub_cmd_abm_set_ambient_level_data { 1965 /** 1966 * Ambient light sensor reading from OS. 1967 */ 1968 uint32_t ambient_lux; 1969 1970 /** 1971 * ABM control version. 1972 */ 1973 uint8_t version; 1974 1975 /** 1976 * Panel Control HW instance mask. 1977 * Bit 0 is Panel Control HW instance 0. 1978 * Bit 1 is Panel Control HW instance 1. 1979 */ 1980 uint8_t panel_mask; 1981 1982 /** 1983 * Explicit padding to 4 byte boundary. 1984 */ 1985 uint8_t pad[2]; 1986 }; 1987 1988 /** 1989 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1990 */ 1991 struct dmub_rb_cmd_abm_set_ambient_level { 1992 /** 1993 * Command header. 1994 */ 1995 struct dmub_cmd_header header; 1996 1997 /** 1998 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 1999 */ 2000 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2001 }; 2002 2003 /** 2004 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2005 */ 2006 struct dmub_cmd_abm_set_pwm_frac_data { 2007 /** 2008 * Enable/disable fractional duty cycle for backlight PWM. 2009 * TODO: Convert to uint8_t. 2010 */ 2011 uint32_t fractional_pwm; 2012 2013 /** 2014 * ABM control version. 2015 */ 2016 uint8_t version; 2017 2018 /** 2019 * Panel Control HW instance mask. 2020 * Bit 0 is Panel Control HW instance 0. 2021 * Bit 1 is Panel Control HW instance 1. 2022 */ 2023 uint8_t panel_mask; 2024 2025 /** 2026 * Explicit padding to 4 byte boundary. 2027 */ 2028 uint8_t pad[2]; 2029 }; 2030 2031 /** 2032 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2033 */ 2034 struct dmub_rb_cmd_abm_set_pwm_frac { 2035 /** 2036 * Command header. 2037 */ 2038 struct dmub_cmd_header header; 2039 2040 /** 2041 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2042 */ 2043 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2044 }; 2045 2046 /** 2047 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2048 */ 2049 struct dmub_cmd_abm_init_config_data { 2050 /** 2051 * Location of indirect buffer used to pass init data to ABM. 2052 */ 2053 union dmub_addr src; 2054 2055 /** 2056 * Indirect buffer length. 2057 */ 2058 uint16_t bytes; 2059 2060 2061 /** 2062 * ABM control version. 2063 */ 2064 uint8_t version; 2065 2066 /** 2067 * Panel Control HW instance mask. 2068 * Bit 0 is Panel Control HW instance 0. 2069 * Bit 1 is Panel Control HW instance 1. 2070 */ 2071 uint8_t panel_mask; 2072 2073 /** 2074 * Explicit padding to 4 byte boundary. 2075 */ 2076 uint8_t pad[2]; 2077 }; 2078 2079 /** 2080 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2081 */ 2082 struct dmub_rb_cmd_abm_init_config { 2083 /** 2084 * Command header. 2085 */ 2086 struct dmub_cmd_header header; 2087 2088 /** 2089 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2090 */ 2091 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2092 }; 2093 2094 /** 2095 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2096 */ 2097 2098 struct dmub_cmd_abm_pause_data { 2099 2100 /** 2101 * Panel Control HW instance mask. 2102 * Bit 0 is Panel Control HW instance 0. 2103 * Bit 1 is Panel Control HW instance 1. 2104 */ 2105 uint8_t panel_mask; 2106 2107 /** 2108 * OTG hw instance 2109 */ 2110 uint8_t otg_inst; 2111 2112 /** 2113 * Enable or disable ABM pause 2114 */ 2115 uint8_t enable; 2116 2117 /** 2118 * Explicit padding to 4 byte boundary. 2119 */ 2120 uint8_t pad[1]; 2121 }; 2122 2123 /** 2124 * Definition of a DMUB_CMD__ABM_PAUSE command. 2125 */ 2126 struct dmub_rb_cmd_abm_pause { 2127 /** 2128 * Command header. 2129 */ 2130 struct dmub_cmd_header header; 2131 2132 /** 2133 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2134 */ 2135 struct dmub_cmd_abm_pause_data abm_pause_data; 2136 }; 2137 2138 /** 2139 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2140 */ 2141 struct dmub_cmd_query_feature_caps_data { 2142 /** 2143 * DMUB feature capabilities. 2144 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2145 */ 2146 struct dmub_feature_caps feature_caps; 2147 }; 2148 2149 /** 2150 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2151 */ 2152 struct dmub_rb_cmd_query_feature_caps { 2153 /** 2154 * Command header. 2155 */ 2156 struct dmub_cmd_header header; 2157 /** 2158 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2159 */ 2160 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2161 }; 2162 2163 struct dmub_optc_state { 2164 uint32_t v_total_max; 2165 uint32_t v_total_min; 2166 uint32_t v_total_mid; 2167 uint32_t v_total_mid_frame_num; 2168 uint32_t tg_inst; 2169 uint32_t enable_manual_trigger; 2170 uint32_t clear_force_vsync; 2171 }; 2172 2173 struct dmub_rb_cmd_drr_update { 2174 struct dmub_cmd_header header; 2175 struct dmub_optc_state dmub_optc_state_req; 2176 }; 2177 2178 /** 2179 * enum dmub_cmd_panel_cntl_type - Panel control command. 2180 */ 2181 enum dmub_cmd_panel_cntl_type { 2182 /** 2183 * Initializes embedded panel hardware blocks. 2184 */ 2185 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2186 /** 2187 * Queries backlight info for the embedded panel. 2188 */ 2189 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2190 }; 2191 2192 /** 2193 * struct dmub_cmd_panel_cntl_data - Panel control data. 2194 */ 2195 struct dmub_cmd_panel_cntl_data { 2196 uint32_t inst; /**< panel instance */ 2197 uint32_t current_backlight; /* in/out */ 2198 uint32_t bl_pwm_cntl; /* in/out */ 2199 uint32_t bl_pwm_period_cntl; /* in/out */ 2200 uint32_t bl_pwm_ref_div1; /* in/out */ 2201 uint8_t is_backlight_on : 1; /* in/out */ 2202 uint8_t is_powered_on : 1; /* in/out */ 2203 }; 2204 2205 /** 2206 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2207 */ 2208 struct dmub_rb_cmd_panel_cntl { 2209 struct dmub_cmd_header header; /**< header */ 2210 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2211 }; 2212 2213 /** 2214 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2215 */ 2216 struct dmub_cmd_lvtma_control_data { 2217 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2218 uint8_t reserved_0[3]; /**< For future use */ 2219 uint8_t panel_inst; /**< LVTMA control instance */ 2220 uint8_t reserved_1[3]; /**< For future use */ 2221 }; 2222 2223 /** 2224 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2225 */ 2226 struct dmub_rb_cmd_lvtma_control { 2227 /** 2228 * Command header. 2229 */ 2230 struct dmub_cmd_header header; 2231 /** 2232 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2233 */ 2234 struct dmub_cmd_lvtma_control_data data; 2235 }; 2236 2237 /** 2238 * Maximum number of bytes a chunk sent to DMUB for parsing 2239 */ 2240 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2241 2242 /** 2243 * Represent a chunk of CEA blocks sent to DMUB for parsing 2244 */ 2245 struct dmub_cmd_send_edid_cea { 2246 uint16_t offset; /**< offset into the CEA block */ 2247 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2248 uint16_t total_length; /**< total length of the CEA block */ 2249 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2250 uint8_t pad[3]; /**< padding and for future expansion */ 2251 }; 2252 2253 /** 2254 * Result of VSDB parsing from CEA block 2255 */ 2256 struct dmub_cmd_edid_cea_amd_vsdb { 2257 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2258 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2259 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2260 uint16_t min_frame_rate; /**< Maximum frame rate */ 2261 uint16_t max_frame_rate; /**< Minimum frame rate */ 2262 }; 2263 2264 /** 2265 * Result of sending a CEA chunk 2266 */ 2267 struct dmub_cmd_edid_cea_ack { 2268 uint16_t offset; /**< offset of the chunk into the CEA block */ 2269 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2270 uint8_t pad; /**< padding and for future expansion */ 2271 }; 2272 2273 /** 2274 * Specify whether the result is an ACK/NACK or the parsing has finished 2275 */ 2276 enum dmub_cmd_edid_cea_reply_type { 2277 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2278 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2279 }; 2280 2281 /** 2282 * Definition of a DMUB_CMD__EDID_CEA command. 2283 */ 2284 struct dmub_rb_cmd_edid_cea { 2285 struct dmub_cmd_header header; /**< Command header */ 2286 union dmub_cmd_edid_cea_data { 2287 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2288 struct dmub_cmd_edid_cea_output { /**< output with results */ 2289 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2290 union { 2291 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2292 struct dmub_cmd_edid_cea_ack ack; 2293 }; 2294 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2295 } data; /**< Command data */ 2296 2297 }; 2298 2299 /** 2300 * union dmub_rb_cmd - DMUB inbox command. 2301 */ 2302 union dmub_rb_cmd { 2303 struct dmub_rb_cmd_lock_hw lock_hw; 2304 /** 2305 * Elements shared with all commands. 2306 */ 2307 struct dmub_rb_cmd_common cmd_common; 2308 /** 2309 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2310 */ 2311 struct dmub_rb_cmd_read_modify_write read_modify_write; 2312 /** 2313 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2314 */ 2315 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2316 /** 2317 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2318 */ 2319 struct dmub_rb_cmd_burst_write burst_write; 2320 /** 2321 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2322 */ 2323 struct dmub_rb_cmd_reg_wait reg_wait; 2324 /** 2325 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2326 */ 2327 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2328 /** 2329 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2330 */ 2331 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2332 /** 2333 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2334 */ 2335 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2336 /** 2337 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2338 */ 2339 struct dmub_rb_cmd_dpphy_init dpphy_init; 2340 /** 2341 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2342 */ 2343 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 2344 /** 2345 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2346 */ 2347 struct dmub_rb_cmd_psr_set_version psr_set_version; 2348 /** 2349 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2350 */ 2351 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 2352 /** 2353 * Definition of a DMUB_CMD__PSR_ENABLE command. 2354 */ 2355 struct dmub_rb_cmd_psr_enable psr_enable; 2356 /** 2357 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2358 */ 2359 struct dmub_rb_cmd_psr_set_level psr_set_level; 2360 /** 2361 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2362 */ 2363 struct dmub_rb_cmd_psr_force_static psr_force_static; 2364 /** 2365 * Definition of a DMUB_CMD__PLAT_54186_WA command. 2366 */ 2367 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2368 /** 2369 * Definition of a DMUB_CMD__MALL command. 2370 */ 2371 struct dmub_rb_cmd_mall mall; 2372 /** 2373 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2374 */ 2375 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2376 2377 /** 2378 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2379 */ 2380 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2381 2382 /** 2383 * Definition of DMUB_CMD__PANEL_CNTL commands. 2384 */ 2385 struct dmub_rb_cmd_panel_cntl panel_cntl; 2386 /** 2387 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2388 */ 2389 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 2390 2391 /** 2392 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2393 */ 2394 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 2395 2396 /** 2397 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2398 */ 2399 struct dmub_rb_cmd_abm_set_level abm_set_level; 2400 2401 /** 2402 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2403 */ 2404 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 2405 2406 /** 2407 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2408 */ 2409 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 2410 2411 /** 2412 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2413 */ 2414 struct dmub_rb_cmd_abm_init_config abm_init_config; 2415 2416 /** 2417 * Definition of a DMUB_CMD__ABM_PAUSE command. 2418 */ 2419 struct dmub_rb_cmd_abm_pause abm_pause; 2420 2421 /** 2422 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2423 */ 2424 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 2425 2426 /** 2427 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2428 */ 2429 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2430 2431 /** 2432 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2433 */ 2434 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2435 struct dmub_rb_cmd_drr_update drr_update; 2436 /** 2437 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2438 */ 2439 struct dmub_rb_cmd_lvtma_control lvtma_control; 2440 /** 2441 * Definition of a DMUB_CMD__EDID_CEA command. 2442 */ 2443 struct dmub_rb_cmd_edid_cea edid_cea; 2444 }; 2445 2446 /** 2447 * union dmub_rb_out_cmd - Outbox command 2448 */ 2449 union dmub_rb_out_cmd { 2450 /** 2451 * Parameters common to every command. 2452 */ 2453 struct dmub_rb_cmd_common cmd_common; 2454 /** 2455 * AUX reply command. 2456 */ 2457 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2458 /** 2459 * HPD notify command. 2460 */ 2461 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2462 }; 2463 #pragma pack(pop) 2464 2465 2466 //============================================================================== 2467 //</DMUB_CMD>=================================================================== 2468 //============================================================================== 2469 //< DMUB_RB>==================================================================== 2470 //============================================================================== 2471 2472 #if defined(__cplusplus) 2473 extern "C" { 2474 #endif 2475 2476 /** 2477 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2478 */ 2479 struct dmub_rb_init_params { 2480 void *ctx; /**< Caller provided context pointer */ 2481 void *base_address; /**< CPU base address for ring's data */ 2482 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2483 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2484 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 2485 }; 2486 2487 /** 2488 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2489 */ 2490 struct dmub_rb { 2491 void *base_address; /**< CPU address for the ring's data */ 2492 uint32_t rptr; /**< Read pointer for consumer in bytes */ 2493 uint32_t wrpt; /**< Write pointer for producer in bytes */ 2494 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2495 2496 void *ctx; /**< Caller provided context pointer */ 2497 void *dmub; /**< Pointer to the DMUB interface */ 2498 }; 2499 2500 /** 2501 * @brief Checks if the ringbuffer is empty. 2502 * 2503 * @param rb DMUB Ringbuffer 2504 * @return true if empty 2505 * @return false otherwise 2506 */ 2507 static inline bool dmub_rb_empty(struct dmub_rb *rb) 2508 { 2509 return (rb->wrpt == rb->rptr); 2510 } 2511 2512 /** 2513 * @brief Checks if the ringbuffer is full 2514 * 2515 * @param rb DMUB Ringbuffer 2516 * @return true if full 2517 * @return false otherwise 2518 */ 2519 static inline bool dmub_rb_full(struct dmub_rb *rb) 2520 { 2521 uint32_t data_count; 2522 2523 if (rb->wrpt >= rb->rptr) 2524 data_count = rb->wrpt - rb->rptr; 2525 else 2526 data_count = rb->capacity - (rb->rptr - rb->wrpt); 2527 2528 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 2529 } 2530 2531 /** 2532 * @brief Pushes a command into the ringbuffer 2533 * 2534 * @param rb DMUB ringbuffer 2535 * @param cmd The command to push 2536 * @return true if the ringbuffer was not full 2537 * @return false otherwise 2538 */ 2539 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 2540 const union dmub_rb_cmd *cmd) 2541 { 2542 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 2543 const uint64_t *src = (const uint64_t *)cmd; 2544 uint8_t i; 2545 2546 if (dmub_rb_full(rb)) 2547 return false; 2548 2549 // copying data 2550 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2551 *dst++ = *src++; 2552 2553 rb->wrpt += DMUB_RB_CMD_SIZE; 2554 2555 if (rb->wrpt >= rb->capacity) 2556 rb->wrpt %= rb->capacity; 2557 2558 return true; 2559 } 2560 2561 /** 2562 * @brief Pushes a command into the DMUB outbox ringbuffer 2563 * 2564 * @param rb DMUB outbox ringbuffer 2565 * @param cmd Outbox command 2566 * @return true if not full 2567 * @return false otherwise 2568 */ 2569 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2570 const union dmub_rb_out_cmd *cmd) 2571 { 2572 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2573 const uint8_t *src = (const uint8_t *)cmd; 2574 2575 if (dmub_rb_full(rb)) 2576 return false; 2577 2578 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2579 2580 rb->wrpt += DMUB_RB_CMD_SIZE; 2581 2582 if (rb->wrpt >= rb->capacity) 2583 rb->wrpt %= rb->capacity; 2584 2585 return true; 2586 } 2587 2588 /** 2589 * @brief Returns the next unprocessed command in the ringbuffer. 2590 * 2591 * @param rb DMUB ringbuffer 2592 * @param cmd The command to return 2593 * @return true if not empty 2594 * @return false otherwise 2595 */ 2596 static inline bool dmub_rb_front(struct dmub_rb *rb, 2597 union dmub_rb_cmd **cmd) 2598 { 2599 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 2600 2601 if (dmub_rb_empty(rb)) 2602 return false; 2603 2604 *cmd = (union dmub_rb_cmd *)rb_cmd; 2605 2606 return true; 2607 } 2608 2609 /** 2610 * @brief Determines the next ringbuffer offset. 2611 * 2612 * @param rb DMUB inbox ringbuffer 2613 * @param num_cmds Number of commands 2614 * @param next_rptr The next offset in the ringbuffer 2615 */ 2616 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 2617 uint32_t num_cmds, 2618 uint32_t *next_rptr) 2619 { 2620 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 2621 2622 if (*next_rptr >= rb->capacity) 2623 *next_rptr %= rb->capacity; 2624 } 2625 2626 /** 2627 * @brief Returns a pointer to a command in the inbox. 2628 * 2629 * @param rb DMUB inbox ringbuffer 2630 * @param cmd The inbox command to return 2631 * @param rptr The ringbuffer offset 2632 * @return true if not empty 2633 * @return false otherwise 2634 */ 2635 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 2636 union dmub_rb_cmd **cmd, 2637 uint32_t rptr) 2638 { 2639 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 2640 2641 if (dmub_rb_empty(rb)) 2642 return false; 2643 2644 *cmd = (union dmub_rb_cmd *)rb_cmd; 2645 2646 return true; 2647 } 2648 2649 /** 2650 * @brief Returns the next unprocessed command in the outbox. 2651 * 2652 * @param rb DMUB outbox ringbuffer 2653 * @param cmd The outbox command to return 2654 * @return true if not empty 2655 * @return false otherwise 2656 */ 2657 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2658 union dmub_rb_out_cmd *cmd) 2659 { 2660 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 2661 uint64_t *dst = (uint64_t *)cmd; 2662 uint8_t i; 2663 2664 if (dmub_rb_empty(rb)) 2665 return false; 2666 2667 // copying data 2668 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2669 *dst++ = *src++; 2670 2671 return true; 2672 } 2673 2674 /** 2675 * @brief Removes the front entry in the ringbuffer. 2676 * 2677 * @param rb DMUB ringbuffer 2678 * @return true if the command was removed 2679 * @return false if there were no commands 2680 */ 2681 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 2682 { 2683 if (dmub_rb_empty(rb)) 2684 return false; 2685 2686 rb->rptr += DMUB_RB_CMD_SIZE; 2687 2688 if (rb->rptr >= rb->capacity) 2689 rb->rptr %= rb->capacity; 2690 2691 return true; 2692 } 2693 2694 /** 2695 * @brief Flushes commands in the ringbuffer to framebuffer memory. 2696 * 2697 * Avoids a race condition where DMCUB accesses memory while 2698 * there are still writes in flight to framebuffer. 2699 * 2700 * @param rb DMUB ringbuffer 2701 */ 2702 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 2703 { 2704 uint32_t rptr = rb->rptr; 2705 uint32_t wptr = rb->wrpt; 2706 2707 while (rptr != wptr) { 2708 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 2709 //uint64_t volatile *p = (uint64_t volatile *)data; 2710 uint64_t temp; 2711 uint8_t i; 2712 2713 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2714 temp = *data++; 2715 2716 rptr += DMUB_RB_CMD_SIZE; 2717 if (rptr >= rb->capacity) 2718 rptr %= rb->capacity; 2719 } 2720 } 2721 2722 /** 2723 * @brief Initializes a DMCUB ringbuffer 2724 * 2725 * @param rb DMUB ringbuffer 2726 * @param init_params initial configuration for the ringbuffer 2727 */ 2728 static inline void dmub_rb_init(struct dmub_rb *rb, 2729 struct dmub_rb_init_params *init_params) 2730 { 2731 rb->base_address = init_params->base_address; 2732 rb->capacity = init_params->capacity; 2733 rb->rptr = init_params->read_ptr; 2734 rb->wrpt = init_params->write_ptr; 2735 } 2736 2737 /** 2738 * @brief Copies output data from in/out commands into the given command. 2739 * 2740 * @param rb DMUB ringbuffer 2741 * @param cmd Command to copy data into 2742 */ 2743 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 2744 union dmub_rb_cmd *cmd) 2745 { 2746 // Copy rb entry back into command 2747 uint8_t *rd_ptr = (rb->rptr == 0) ? 2748 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 2749 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 2750 2751 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 2752 } 2753 2754 #if defined(__cplusplus) 2755 } 2756 #endif 2757 2758 //============================================================================== 2759 //</DMUB_RB>==================================================================== 2760 //============================================================================== 2761 2762 #endif /* _DMUB_CMD_H_ */ 2763