1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Maximum number of streams on any ASIC. */ 99 #define DMUB_MAX_STREAMS 6 100 101 /* Maximum number of planes on any ASIC. */ 102 #define DMUB_MAX_PLANES 6 103 104 /* Trace buffer offset for entry */ 105 #define TRACE_BUFFER_ENTRY_OFFSET 16 106 107 /** 108 * Maximum number of dirty rects supported by FW. 109 */ 110 #define DMUB_MAX_DIRTY_RECTS 3 111 112 /** 113 * 114 * PSR control version legacy 115 */ 116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117 /** 118 * PSR control version with multi edp support 119 */ 120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121 122 123 /** 124 * ABM control version legacy 125 */ 126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127 128 /** 129 * ABM control version with multi edp support 130 */ 131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132 133 /** 134 * Physical framebuffer address location, 64-bit. 135 */ 136 #ifndef PHYSICAL_ADDRESS_LOC 137 #define PHYSICAL_ADDRESS_LOC union large_integer 138 #endif 139 140 /** 141 * OS/FW agnostic memcpy 142 */ 143 #ifndef dmub_memcpy 144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 145 #endif 146 147 /** 148 * OS/FW agnostic memset 149 */ 150 #ifndef dmub_memset 151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 152 #endif 153 154 #if defined(__cplusplus) 155 extern "C" { 156 #endif 157 158 /** 159 * OS/FW agnostic udelay 160 */ 161 #ifndef dmub_udelay 162 #define dmub_udelay(microseconds) udelay(microseconds) 163 #endif 164 165 /** 166 * union dmub_addr - DMUB physical/virtual 64-bit address. 167 */ 168 union dmub_addr { 169 struct { 170 uint32_t low_part; /**< Lower 32 bits */ 171 uint32_t high_part; /**< Upper 32 bits */ 172 } u; /*<< Low/high bit access */ 173 uint64_t quad_part; /*<< 64 bit address */ 174 }; 175 176 /** 177 * Dirty rect definition. 178 */ 179 struct dmub_rect { 180 /** 181 * Dirty rect x offset. 182 */ 183 uint32_t x; 184 185 /** 186 * Dirty rect y offset. 187 */ 188 uint32_t y; 189 190 /** 191 * Dirty rect width. 192 */ 193 uint32_t width; 194 195 /** 196 * Dirty rect height. 197 */ 198 uint32_t height; 199 }; 200 201 /** 202 * Flags that can be set by driver to change some PSR behaviour. 203 */ 204 union dmub_psr_debug_flags { 205 /** 206 * Debug flags. 207 */ 208 struct { 209 /** 210 * Enable visual confirm in FW. 211 */ 212 uint32_t visual_confirm : 1; 213 214 /** 215 * Force all selective updates to bw full frame updates. 216 */ 217 uint32_t force_full_frame_update : 1; 218 219 /** 220 * Use HW Lock Mgr object to do HW locking in FW. 221 */ 222 uint32_t use_hw_lock_mgr : 1; 223 224 /** 225 * Use TPS3 signal when restore main link. 226 */ 227 uint32_t force_wakeup_by_tps3 : 1; 228 } bitfields; 229 230 /** 231 * Union for debug flags. 232 */ 233 uint32_t u32All; 234 }; 235 236 /** 237 * DMUB feature capabilities. 238 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 239 */ 240 struct dmub_feature_caps { 241 /** 242 * Max PSR version supported by FW. 243 */ 244 uint8_t psr; 245 uint8_t fw_assisted_mclk_switch; 246 uint8_t reserved[6]; 247 }; 248 249 #if defined(__cplusplus) 250 } 251 #endif 252 253 //============================================================================== 254 //</DMUB_TYPES>================================================================= 255 //============================================================================== 256 //< DMUB_META>================================================================== 257 //============================================================================== 258 #pragma pack(push, 1) 259 260 /* Magic value for identifying dmub_fw_meta_info */ 261 #define DMUB_FW_META_MAGIC 0x444D5542 262 263 /* Offset from the end of the file to the dmub_fw_meta_info */ 264 #define DMUB_FW_META_OFFSET 0x24 265 266 /** 267 * struct dmub_fw_meta_info - metadata associated with fw binary 268 * 269 * NOTE: This should be considered a stable API. Fields should 270 * not be repurposed or reordered. New fields should be 271 * added instead to extend the structure. 272 * 273 * @magic_value: magic value identifying DMUB firmware meta info 274 * @fw_region_size: size of the firmware state region 275 * @trace_buffer_size: size of the tracebuffer region 276 * @fw_version: the firmware version information 277 * @dal_fw: 1 if the firmware is DAL 278 */ 279 struct dmub_fw_meta_info { 280 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 281 uint32_t fw_region_size; /**< size of the firmware state region */ 282 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 283 uint32_t fw_version; /**< the firmware version information */ 284 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 285 uint8_t reserved[3]; /**< padding bits */ 286 }; 287 288 /** 289 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 290 */ 291 union dmub_fw_meta { 292 struct dmub_fw_meta_info info; /**< metadata info */ 293 uint8_t reserved[64]; /**< padding bits */ 294 }; 295 296 #pragma pack(pop) 297 298 //============================================================================== 299 //< DMUB Trace Buffer>================================================================ 300 //============================================================================== 301 /** 302 * dmub_trace_code_t - firmware trace code, 32-bits 303 */ 304 typedef uint32_t dmub_trace_code_t; 305 306 /** 307 * struct dmcub_trace_buf_entry - Firmware trace entry 308 */ 309 struct dmcub_trace_buf_entry { 310 dmub_trace_code_t trace_code; /**< trace code for the event */ 311 uint32_t tick_count; /**< the tick count at time of trace */ 312 uint32_t param0; /**< trace defined parameter 0 */ 313 uint32_t param1; /**< trace defined parameter 1 */ 314 }; 315 316 //============================================================================== 317 //< DMUB_STATUS>================================================================ 318 //============================================================================== 319 320 /** 321 * DMCUB scratch registers can be used to determine firmware status. 322 * Current scratch register usage is as follows: 323 * 324 * SCRATCH0: FW Boot Status register 325 * SCRATCH5: LVTMA Status Register 326 * SCRATCH15: FW Boot Options register 327 */ 328 329 /** 330 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 331 */ 332 union dmub_fw_boot_status { 333 struct { 334 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 335 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 336 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 337 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 338 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 339 uint32_t reserved : 1; 340 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 341 342 } bits; /**< status bits */ 343 uint32_t all; /**< 32-bit access to status bits */ 344 }; 345 346 /** 347 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 348 */ 349 enum dmub_fw_boot_status_bit { 350 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 351 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 352 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 353 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 354 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 355 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 356 }; 357 358 /* Register bit definition for SCRATCH5 */ 359 union dmub_lvtma_status { 360 struct { 361 uint32_t psp_ok : 1; 362 uint32_t edp_on : 1; 363 uint32_t reserved : 30; 364 } bits; 365 uint32_t all; 366 }; 367 368 enum dmub_lvtma_status_bit { 369 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 370 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 371 }; 372 373 /** 374 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 375 */ 376 union dmub_fw_boot_options { 377 struct { 378 uint32_t pemu_env : 1; /**< 1 if PEMU */ 379 uint32_t fpga_env : 1; /**< 1 if FPGA */ 380 uint32_t optimized_init : 1; /**< 1 if optimized init */ 381 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 382 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 383 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 384 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 385 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 386 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 387 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 388 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 389 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 390 uint32_t power_optimization: 1; 391 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 392 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 393 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 394 395 uint32_t reserved : 17; /**< reserved */ 396 } bits; /**< boot bits */ 397 uint32_t all; /**< 32-bit access to bits */ 398 }; 399 400 enum dmub_fw_boot_options_bit { 401 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 402 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 403 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 404 }; 405 406 //============================================================================== 407 //</DMUB_STATUS>================================================================ 408 //============================================================================== 409 //< DMUB_VBIOS>================================================================= 410 //============================================================================== 411 412 /* 413 * enum dmub_cmd_vbios_type - VBIOS commands. 414 * 415 * Command IDs should be treated as stable ABI. 416 * Do not reuse or modify IDs. 417 */ 418 enum dmub_cmd_vbios_type { 419 /** 420 * Configures the DIG encoder. 421 */ 422 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 423 /** 424 * Controls the PHY. 425 */ 426 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 427 /** 428 * Sets the pixel clock/symbol clock. 429 */ 430 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 431 /** 432 * Enables or disables power gating. 433 */ 434 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 435 /** 436 * Controls embedded panels. 437 */ 438 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 439 /** 440 * Query DP alt status on a transmitter. 441 */ 442 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 443 }; 444 445 //============================================================================== 446 //</DMUB_VBIOS>================================================================= 447 //============================================================================== 448 //< DMUB_GPINT>================================================================= 449 //============================================================================== 450 451 /** 452 * The shifts and masks below may alternatively be used to format and read 453 * the command register bits. 454 */ 455 456 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 457 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 458 459 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 460 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 461 462 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 463 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 464 465 /** 466 * Command responses. 467 */ 468 469 /** 470 * Return response for DMUB_GPINT__STOP_FW command. 471 */ 472 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 473 474 /** 475 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 476 */ 477 union dmub_gpint_data_register { 478 struct { 479 uint32_t param : 16; /**< 16-bit parameter */ 480 uint32_t command_code : 12; /**< GPINT command */ 481 uint32_t status : 4; /**< Command status bit */ 482 } bits; /**< GPINT bit access */ 483 uint32_t all; /**< GPINT 32-bit access */ 484 }; 485 486 /* 487 * enum dmub_gpint_command - GPINT command to DMCUB FW 488 * 489 * Command IDs should be treated as stable ABI. 490 * Do not reuse or modify IDs. 491 */ 492 enum dmub_gpint_command { 493 /** 494 * Invalid command, ignored. 495 */ 496 DMUB_GPINT__INVALID_COMMAND = 0, 497 /** 498 * DESC: Queries the firmware version. 499 * RETURN: Firmware version. 500 */ 501 DMUB_GPINT__GET_FW_VERSION = 1, 502 /** 503 * DESC: Halts the firmware. 504 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 505 */ 506 DMUB_GPINT__STOP_FW = 2, 507 /** 508 * DESC: Get PSR state from FW. 509 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 510 */ 511 DMUB_GPINT__GET_PSR_STATE = 7, 512 /** 513 * DESC: Notifies DMCUB of the currently active streams. 514 * ARGS: Stream mask, 1 bit per active stream index. 515 */ 516 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 517 /** 518 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 519 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 520 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 521 * RETURN: PSR residency in milli-percent. 522 */ 523 DMUB_GPINT__PSR_RESIDENCY = 9, 524 525 /** 526 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 527 */ 528 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 529 }; 530 531 /** 532 * INBOX0 generic command definition 533 */ 534 union dmub_inbox0_cmd_common { 535 struct { 536 uint32_t command_code: 8; /**< INBOX0 command code */ 537 uint32_t param: 24; /**< 24-bit parameter */ 538 } bits; 539 uint32_t all; 540 }; 541 542 /** 543 * INBOX0 hw_lock command definition 544 */ 545 union dmub_inbox0_cmd_lock_hw { 546 struct { 547 uint32_t command_code: 8; 548 549 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 550 uint32_t hw_lock_client: 2; 551 552 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 553 uint32_t otg_inst: 3; 554 uint32_t opp_inst: 3; 555 uint32_t dig_inst: 3; 556 557 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 558 uint32_t lock_pipe: 1; 559 uint32_t lock_cursor: 1; 560 uint32_t lock_dig: 1; 561 uint32_t triple_buffer_lock: 1; 562 563 uint32_t lock: 1; /**< Lock */ 564 uint32_t should_release: 1; /**< Release */ 565 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 566 } bits; 567 uint32_t all; 568 }; 569 570 union dmub_inbox0_data_register { 571 union dmub_inbox0_cmd_common inbox0_cmd_common; 572 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 573 }; 574 575 enum dmub_inbox0_command { 576 /** 577 * DESC: Invalid command, ignored. 578 */ 579 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 580 /** 581 * DESC: Notification to acquire/release HW lock 582 * ARGS: 583 */ 584 DMUB_INBOX0_CMD__HW_LOCK = 1, 585 }; 586 //============================================================================== 587 //</DMUB_GPINT>================================================================= 588 //============================================================================== 589 //< DMUB_CMD>=================================================================== 590 //============================================================================== 591 592 /** 593 * Size in bytes of each DMUB command. 594 */ 595 #define DMUB_RB_CMD_SIZE 64 596 597 /** 598 * Maximum number of items in the DMUB ringbuffer. 599 */ 600 #define DMUB_RB_MAX_ENTRY 128 601 602 /** 603 * Ringbuffer size in bytes. 604 */ 605 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 606 607 /** 608 * REG_SET mask for reg offload. 609 */ 610 #define REG_SET_MASK 0xFFFF 611 612 /* 613 * enum dmub_cmd_type - DMUB inbox command. 614 * 615 * Command IDs should be treated as stable ABI. 616 * Do not reuse or modify IDs. 617 */ 618 enum dmub_cmd_type { 619 /** 620 * Invalid command. 621 */ 622 DMUB_CMD__NULL = 0, 623 /** 624 * Read modify write register sequence offload. 625 */ 626 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 627 /** 628 * Field update register sequence offload. 629 */ 630 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 631 /** 632 * Burst write sequence offload. 633 */ 634 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 635 /** 636 * Reg wait sequence offload. 637 */ 638 DMUB_CMD__REG_REG_WAIT = 4, 639 /** 640 * Workaround to avoid HUBP underflow during NV12 playback. 641 */ 642 DMUB_CMD__PLAT_54186_WA = 5, 643 /** 644 * Command type used to query FW feature caps. 645 */ 646 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 647 /** 648 * Command type used for all PSR commands. 649 */ 650 DMUB_CMD__PSR = 64, 651 /** 652 * Command type used for all MALL commands. 653 */ 654 DMUB_CMD__MALL = 65, 655 /** 656 * Command type used for all ABM commands. 657 */ 658 DMUB_CMD__ABM = 66, 659 /** 660 * Command type used to update dirty rects in FW. 661 */ 662 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 663 /** 664 * Command type used to update cursor info in FW. 665 */ 666 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 667 /** 668 * Command type used for HW locking in FW. 669 */ 670 DMUB_CMD__HW_LOCK = 69, 671 /** 672 * Command type used to access DP AUX. 673 */ 674 DMUB_CMD__DP_AUX_ACCESS = 70, 675 /** 676 * Command type used for OUTBOX1 notification enable 677 */ 678 DMUB_CMD__OUTBOX1_ENABLE = 71, 679 680 /** 681 * Command type used for all idle optimization commands. 682 */ 683 DMUB_CMD__IDLE_OPT = 72, 684 /** 685 * Command type used for all clock manager commands. 686 */ 687 DMUB_CMD__CLK_MGR = 73, 688 /** 689 * Command type used for all panel control commands. 690 */ 691 DMUB_CMD__PANEL_CNTL = 74, 692 /** 693 * Command type used for <TODO:description> 694 */ 695 DMUB_CMD__CAB_FOR_SS = 75, 696 697 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 698 699 /** 700 * Command type used for interfacing with DPIA. 701 */ 702 DMUB_CMD__DPIA = 77, 703 /** 704 * Command type used for EDID CEA parsing 705 */ 706 DMUB_CMD__EDID_CEA = 79, 707 /** 708 * Command type used for getting usbc cable ID 709 */ 710 DMUB_CMD_GET_USBC_CABLE_ID = 81, 711 /** 712 * Command type used to query HPD state. 713 */ 714 DMUB_CMD__QUERY_HPD_STATE = 82, 715 /** 716 * Command type used for all VBIOS interface commands. 717 */ 718 DMUB_CMD__VBIOS = 128, 719 }; 720 721 /** 722 * enum dmub_out_cmd_type - DMUB outbox commands. 723 */ 724 enum dmub_out_cmd_type { 725 /** 726 * Invalid outbox command, ignored. 727 */ 728 DMUB_OUT_CMD__NULL = 0, 729 /** 730 * Command type used for DP AUX Reply data notification 731 */ 732 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 733 /** 734 * Command type used for DP HPD event notification 735 */ 736 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 737 /** 738 * Command type used for SET_CONFIG Reply notification 739 */ 740 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 741 }; 742 743 /* DMUB_CMD__DPIA command sub-types. */ 744 enum dmub_cmd_dpia_type { 745 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 746 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 747 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 748 }; 749 750 #pragma pack(push, 1) 751 752 /** 753 * struct dmub_cmd_header - Common command header fields. 754 */ 755 struct dmub_cmd_header { 756 unsigned int type : 8; /**< command type */ 757 unsigned int sub_type : 8; /**< command sub type */ 758 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 759 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 760 unsigned int reserved0 : 6; /**< reserved bits */ 761 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 762 unsigned int reserved1 : 2; /**< reserved bits */ 763 }; 764 765 /* 766 * struct dmub_cmd_read_modify_write_sequence - Read modify write 767 * 768 * 60 payload bytes can hold up to 5 sets of read modify writes, 769 * each take 3 dwords. 770 * 771 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 772 * 773 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 774 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 775 */ 776 struct dmub_cmd_read_modify_write_sequence { 777 uint32_t addr; /**< register address */ 778 uint32_t modify_mask; /**< modify mask */ 779 uint32_t modify_value; /**< modify value */ 780 }; 781 782 /** 783 * Maximum number of ops in read modify write sequence. 784 */ 785 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 786 787 /** 788 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 789 */ 790 struct dmub_rb_cmd_read_modify_write { 791 struct dmub_cmd_header header; /**< command header */ 792 /** 793 * Read modify write sequence. 794 */ 795 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 796 }; 797 798 /* 799 * Update a register with specified masks and values sequeunce 800 * 801 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 802 * 803 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 804 * 805 * 806 * USE CASE: 807 * 1. auto-increment register where additional read would update pointer and produce wrong result 808 * 2. toggle a bit without read in the middle 809 */ 810 811 struct dmub_cmd_reg_field_update_sequence { 812 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 813 uint32_t modify_value; /**< value to update with */ 814 }; 815 816 /** 817 * Maximum number of ops in field update sequence. 818 */ 819 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 820 821 /** 822 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 823 */ 824 struct dmub_rb_cmd_reg_field_update_sequence { 825 struct dmub_cmd_header header; /**< command header */ 826 uint32_t addr; /**< register address */ 827 /** 828 * Field update sequence. 829 */ 830 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 831 }; 832 833 834 /** 835 * Maximum number of burst write values. 836 */ 837 #define DMUB_BURST_WRITE_VALUES__MAX 14 838 839 /* 840 * struct dmub_rb_cmd_burst_write - Burst write 841 * 842 * support use case such as writing out LUTs. 843 * 844 * 60 payload bytes can hold up to 14 values to write to given address 845 * 846 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 847 */ 848 struct dmub_rb_cmd_burst_write { 849 struct dmub_cmd_header header; /**< command header */ 850 uint32_t addr; /**< register start address */ 851 /** 852 * Burst write register values. 853 */ 854 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 855 }; 856 857 /** 858 * struct dmub_rb_cmd_common - Common command header 859 */ 860 struct dmub_rb_cmd_common { 861 struct dmub_cmd_header header; /**< command header */ 862 /** 863 * Padding to RB_CMD_SIZE 864 */ 865 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 866 }; 867 868 /** 869 * struct dmub_cmd_reg_wait_data - Register wait data 870 */ 871 struct dmub_cmd_reg_wait_data { 872 uint32_t addr; /**< Register address */ 873 uint32_t mask; /**< Mask for register bits */ 874 uint32_t condition_field_value; /**< Value to wait for */ 875 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 876 }; 877 878 /** 879 * struct dmub_rb_cmd_reg_wait - Register wait command 880 */ 881 struct dmub_rb_cmd_reg_wait { 882 struct dmub_cmd_header header; /**< Command header */ 883 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 884 }; 885 886 /** 887 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 888 * 889 * Reprograms surface parameters to avoid underflow. 890 */ 891 struct dmub_cmd_PLAT_54186_wa { 892 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 893 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 894 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 895 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 896 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 897 struct { 898 uint8_t hubp_inst : 4; /**< HUBP instance */ 899 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 900 uint8_t immediate :1; /**< Immediate flip */ 901 uint8_t vmid : 4; /**< VMID */ 902 uint8_t grph_stereo : 1; /**< 1 if stereo */ 903 uint32_t reserved : 21; /**< Reserved */ 904 } flip_params; /**< Pageflip parameters */ 905 uint32_t reserved[9]; /**< Reserved bits */ 906 }; 907 908 /** 909 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 910 */ 911 struct dmub_rb_cmd_PLAT_54186_wa { 912 struct dmub_cmd_header header; /**< Command header */ 913 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 914 }; 915 916 /** 917 * struct dmub_rb_cmd_mall - MALL command data. 918 */ 919 struct dmub_rb_cmd_mall { 920 struct dmub_cmd_header header; /**< Common command header */ 921 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 922 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 923 uint32_t tmr_delay; /**< Timer delay */ 924 uint32_t tmr_scale; /**< Timer scale */ 925 uint16_t cursor_width; /**< Cursor width in pixels */ 926 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 927 uint16_t cursor_height; /**< Cursor height in pixels */ 928 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 929 uint8_t debug_bits; /**< Debug bits */ 930 931 uint8_t reserved1; /**< Reserved bits */ 932 uint8_t reserved2; /**< Reserved bits */ 933 }; 934 935 /** 936 * enum dmub_cmd_cab_type - TODO: 937 */ 938 enum dmub_cmd_cab_type { 939 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 940 DMUB_CMD__CAB_NO_DCN_REQ = 1, 941 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 942 }; 943 944 /** 945 * struct dmub_rb_cmd_cab_for_ss - TODO: 946 */ 947 struct dmub_rb_cmd_cab_for_ss { 948 struct dmub_cmd_header header; 949 uint8_t cab_alloc_ways; /* total number of ways */ 950 uint8_t debug_bits; /* debug bits */ 951 }; 952 953 enum mclk_switch_mode { 954 NONE = 0, 955 FPO = 1, 956 SUBVP = 2, 957 VBLANK = 3, 958 }; 959 960 /* Per pipe struct which stores the MCLK switch mode 961 * data to be sent to DMUB. 962 * Named "v2" for now -- once FPO and SUBVP are fully merged 963 * the type name can be updated 964 */ 965 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 966 union { 967 struct { 968 uint32_t pix_clk_100hz; 969 uint16_t main_vblank_start; 970 uint16_t main_vblank_end; 971 uint16_t mall_region_lines; 972 uint16_t prefetch_lines; 973 uint16_t prefetch_to_mall_start_lines; 974 uint16_t processing_delay_lines; 975 uint16_t htotal; // required to calculate line time for multi-display cases 976 uint16_t vtotal; 977 uint8_t main_pipe_index; 978 uint8_t phantom_pipe_index; 979 uint8_t padding[2]; 980 } subvp_data; 981 982 struct { 983 uint32_t pix_clk_100hz; 984 uint16_t vblank_start; 985 uint16_t vblank_end; 986 uint16_t vstartup_start; 987 uint16_t vtotal; 988 uint16_t htotal; 989 uint8_t vblank_pipe_index; 990 uint8_t padding[2]; 991 struct { 992 uint8_t drr_in_use; 993 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 994 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 995 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 996 uint8_t use_ramping; // Use ramping or not 997 } drr_info; // DRR considered as part of SubVP + VBLANK case 998 } vblank_data; 999 } pipe_config; 1000 1001 enum mclk_switch_mode mode; 1002 }; 1003 1004 /** 1005 * Config data for Sub-VP and FPO 1006 * Named "v2" for now -- once FPO and SUBVP are fully merged 1007 * the type name can be updated 1008 */ 1009 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1010 uint16_t watermark_a_cache; 1011 uint8_t vertical_int_margin_us; 1012 uint8_t pstate_allow_width_us; 1013 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1014 }; 1015 1016 /** 1017 * DMUB rb command definition for Sub-VP and FPO 1018 * Named "v2" for now -- once FPO and SUBVP are fully merged 1019 * the type name can be updated 1020 */ 1021 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1022 struct dmub_cmd_header header; 1023 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1024 }; 1025 1026 /** 1027 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1028 */ 1029 enum dmub_cmd_idle_opt_type { 1030 /** 1031 * DCN hardware restore. 1032 */ 1033 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1034 1035 /** 1036 * DCN hardware save. 1037 */ 1038 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1039 }; 1040 1041 /** 1042 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1043 */ 1044 struct dmub_rb_cmd_idle_opt_dcn_restore { 1045 struct dmub_cmd_header header; /**< header */ 1046 }; 1047 1048 /** 1049 * struct dmub_clocks - Clock update notification. 1050 */ 1051 struct dmub_clocks { 1052 uint32_t dispclk_khz; /**< dispclk kHz */ 1053 uint32_t dppclk_khz; /**< dppclk kHz */ 1054 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1055 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1056 }; 1057 1058 /** 1059 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1060 */ 1061 enum dmub_cmd_clk_mgr_type { 1062 /** 1063 * Notify DMCUB of clock update. 1064 */ 1065 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1066 }; 1067 1068 /** 1069 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1070 */ 1071 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1072 struct dmub_cmd_header header; /**< header */ 1073 struct dmub_clocks clocks; /**< clock data */ 1074 }; 1075 1076 /** 1077 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1078 */ 1079 struct dmub_cmd_digx_encoder_control_data { 1080 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1081 }; 1082 1083 /** 1084 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1085 */ 1086 struct dmub_rb_cmd_digx_encoder_control { 1087 struct dmub_cmd_header header; /**< header */ 1088 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1089 }; 1090 1091 /** 1092 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1093 */ 1094 struct dmub_cmd_set_pixel_clock_data { 1095 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1096 }; 1097 1098 /** 1099 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1100 */ 1101 struct dmub_rb_cmd_set_pixel_clock { 1102 struct dmub_cmd_header header; /**< header */ 1103 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1104 }; 1105 1106 /** 1107 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1108 */ 1109 struct dmub_cmd_enable_disp_power_gating_data { 1110 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1111 }; 1112 1113 /** 1114 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1115 */ 1116 struct dmub_rb_cmd_enable_disp_power_gating { 1117 struct dmub_cmd_header header; /**< header */ 1118 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1119 }; 1120 1121 /** 1122 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1123 */ 1124 struct dmub_dig_transmitter_control_data_v1_7 { 1125 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1126 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1127 union { 1128 uint8_t digmode; /**< enum atom_encode_mode_def */ 1129 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1130 } mode_laneset; 1131 uint8_t lanenum; /**< Number of lanes */ 1132 union { 1133 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1134 } symclk_units; 1135 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1136 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1137 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1138 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1139 uint8_t reserved1; /**< For future use */ 1140 uint8_t reserved2[3]; /**< For future use */ 1141 uint32_t reserved3[11]; /**< For future use */ 1142 }; 1143 1144 /** 1145 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1146 */ 1147 union dmub_cmd_dig1_transmitter_control_data { 1148 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1149 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1150 }; 1151 1152 /** 1153 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1154 */ 1155 struct dmub_rb_cmd_dig1_transmitter_control { 1156 struct dmub_cmd_header header; /**< header */ 1157 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1158 }; 1159 1160 /** 1161 * DPIA tunnel command parameters. 1162 */ 1163 struct dmub_cmd_dig_dpia_control_data { 1164 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1165 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1166 union { 1167 uint8_t digmode; /** enum atom_encode_mode_def */ 1168 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1169 } mode_laneset; 1170 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1171 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1172 uint8_t hpdsel; /** =0: HPD is not assigned */ 1173 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1174 uint8_t dpia_id; /** Index of DPIA */ 1175 uint8_t fec_rdy : 1; 1176 uint8_t reserved : 7; 1177 uint32_t reserved1; 1178 }; 1179 1180 /** 1181 * DMUB command for DPIA tunnel control. 1182 */ 1183 struct dmub_rb_cmd_dig1_dpia_control { 1184 struct dmub_cmd_header header; 1185 struct dmub_cmd_dig_dpia_control_data dpia_control; 1186 }; 1187 1188 /** 1189 * SET_CONFIG Command Payload 1190 */ 1191 struct set_config_cmd_payload { 1192 uint8_t msg_type; /* set config message type */ 1193 uint8_t msg_data; /* set config message data */ 1194 }; 1195 1196 /** 1197 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1198 */ 1199 struct dmub_cmd_set_config_control_data { 1200 struct set_config_cmd_payload cmd_pkt; 1201 uint8_t instance; /* DPIA instance */ 1202 uint8_t immed_status; /* Immediate status returned in case of error */ 1203 }; 1204 1205 /** 1206 * DMUB command structure for SET_CONFIG command. 1207 */ 1208 struct dmub_rb_cmd_set_config_access { 1209 struct dmub_cmd_header header; /* header */ 1210 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1211 }; 1212 1213 /** 1214 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1215 */ 1216 struct dmub_cmd_mst_alloc_slots_control_data { 1217 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1218 uint8_t instance; /* DPIA instance */ 1219 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1220 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1221 }; 1222 1223 /** 1224 * DMUB command structure for SET_ command. 1225 */ 1226 struct dmub_rb_cmd_set_mst_alloc_slots { 1227 struct dmub_cmd_header header; /* header */ 1228 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1229 }; 1230 1231 /** 1232 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1233 */ 1234 struct dmub_rb_cmd_dpphy_init { 1235 struct dmub_cmd_header header; /**< header */ 1236 uint8_t reserved[60]; /**< reserved bits */ 1237 }; 1238 1239 /** 1240 * enum dp_aux_request_action - DP AUX request command listing. 1241 * 1242 * 4 AUX request command bits are shifted to high nibble. 1243 */ 1244 enum dp_aux_request_action { 1245 /** I2C-over-AUX write request */ 1246 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1247 /** I2C-over-AUX read request */ 1248 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1249 /** I2C-over-AUX write status request */ 1250 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1251 /** I2C-over-AUX write request with MOT=1 */ 1252 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1253 /** I2C-over-AUX read request with MOT=1 */ 1254 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1255 /** I2C-over-AUX write status request with MOT=1 */ 1256 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1257 /** Native AUX write request */ 1258 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1259 /** Native AUX read request */ 1260 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1261 }; 1262 1263 /** 1264 * enum aux_return_code_type - DP AUX process return code listing. 1265 */ 1266 enum aux_return_code_type { 1267 /** AUX process succeeded */ 1268 AUX_RET_SUCCESS = 0, 1269 /** AUX process failed with unknown reason */ 1270 AUX_RET_ERROR_UNKNOWN, 1271 /** AUX process completed with invalid reply */ 1272 AUX_RET_ERROR_INVALID_REPLY, 1273 /** AUX process timed out */ 1274 AUX_RET_ERROR_TIMEOUT, 1275 /** HPD was low during AUX process */ 1276 AUX_RET_ERROR_HPD_DISCON, 1277 /** Failed to acquire AUX engine */ 1278 AUX_RET_ERROR_ENGINE_ACQUIRE, 1279 /** AUX request not supported */ 1280 AUX_RET_ERROR_INVALID_OPERATION, 1281 /** AUX process not available */ 1282 AUX_RET_ERROR_PROTOCOL_ERROR, 1283 }; 1284 1285 /** 1286 * enum aux_channel_type - DP AUX channel type listing. 1287 */ 1288 enum aux_channel_type { 1289 /** AUX thru Legacy DP AUX */ 1290 AUX_CHANNEL_LEGACY_DDC, 1291 /** AUX thru DPIA DP tunneling */ 1292 AUX_CHANNEL_DPIA 1293 }; 1294 1295 /** 1296 * struct aux_transaction_parameters - DP AUX request transaction data 1297 */ 1298 struct aux_transaction_parameters { 1299 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1300 uint8_t action; /**< enum dp_aux_request_action */ 1301 uint8_t length; /**< DP AUX request data length */ 1302 uint8_t reserved; /**< For future use */ 1303 uint32_t address; /**< DP AUX address */ 1304 uint8_t data[16]; /**< DP AUX write data */ 1305 }; 1306 1307 /** 1308 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1309 */ 1310 struct dmub_cmd_dp_aux_control_data { 1311 uint8_t instance; /**< AUX instance or DPIA instance */ 1312 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1313 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1314 uint8_t reserved0; /**< For future use */ 1315 uint16_t timeout; /**< timeout time in us */ 1316 uint16_t reserved1; /**< For future use */ 1317 enum aux_channel_type type; /**< enum aux_channel_type */ 1318 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1319 }; 1320 1321 /** 1322 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1323 */ 1324 struct dmub_rb_cmd_dp_aux_access { 1325 /** 1326 * Command header. 1327 */ 1328 struct dmub_cmd_header header; 1329 /** 1330 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1331 */ 1332 struct dmub_cmd_dp_aux_control_data aux_control; 1333 }; 1334 1335 /** 1336 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1337 */ 1338 struct dmub_rb_cmd_outbox1_enable { 1339 /** 1340 * Command header. 1341 */ 1342 struct dmub_cmd_header header; 1343 /** 1344 * enable: 0x0 -> disable outbox1 notification (default value) 1345 * 0x1 -> enable outbox1 notification 1346 */ 1347 uint32_t enable; 1348 }; 1349 1350 /* DP AUX Reply command - OutBox Cmd */ 1351 /** 1352 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1353 */ 1354 struct aux_reply_data { 1355 /** 1356 * Aux cmd 1357 */ 1358 uint8_t command; 1359 /** 1360 * Aux reply data length (max: 16 bytes) 1361 */ 1362 uint8_t length; 1363 /** 1364 * Alignment only 1365 */ 1366 uint8_t pad[2]; 1367 /** 1368 * Aux reply data 1369 */ 1370 uint8_t data[16]; 1371 }; 1372 1373 /** 1374 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1375 */ 1376 struct aux_reply_control_data { 1377 /** 1378 * Reserved for future use 1379 */ 1380 uint32_t handle; 1381 /** 1382 * Aux Instance 1383 */ 1384 uint8_t instance; 1385 /** 1386 * Aux transaction result: definition in enum aux_return_code_type 1387 */ 1388 uint8_t result; 1389 /** 1390 * Alignment only 1391 */ 1392 uint16_t pad; 1393 }; 1394 1395 /** 1396 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1397 */ 1398 struct dmub_rb_cmd_dp_aux_reply { 1399 /** 1400 * Command header. 1401 */ 1402 struct dmub_cmd_header header; 1403 /** 1404 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1405 */ 1406 struct aux_reply_control_data control; 1407 /** 1408 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1409 */ 1410 struct aux_reply_data reply_data; 1411 }; 1412 1413 /* DP HPD Notify command - OutBox Cmd */ 1414 /** 1415 * DP HPD Type 1416 */ 1417 enum dp_hpd_type { 1418 /** 1419 * Normal DP HPD 1420 */ 1421 DP_HPD = 0, 1422 /** 1423 * DP HPD short pulse 1424 */ 1425 DP_IRQ 1426 }; 1427 1428 /** 1429 * DP HPD Status 1430 */ 1431 enum dp_hpd_status { 1432 /** 1433 * DP_HPD status low 1434 */ 1435 DP_HPD_UNPLUG = 0, 1436 /** 1437 * DP_HPD status high 1438 */ 1439 DP_HPD_PLUG 1440 }; 1441 1442 /** 1443 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1444 */ 1445 struct dp_hpd_data { 1446 /** 1447 * DP HPD instance 1448 */ 1449 uint8_t instance; 1450 /** 1451 * HPD type 1452 */ 1453 uint8_t hpd_type; 1454 /** 1455 * HPD status: only for type: DP_HPD to indicate status 1456 */ 1457 uint8_t hpd_status; 1458 /** 1459 * Alignment only 1460 */ 1461 uint8_t pad; 1462 }; 1463 1464 /** 1465 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1466 */ 1467 struct dmub_rb_cmd_dp_hpd_notify { 1468 /** 1469 * Command header. 1470 */ 1471 struct dmub_cmd_header header; 1472 /** 1473 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1474 */ 1475 struct dp_hpd_data hpd_data; 1476 }; 1477 1478 /** 1479 * Definition of a SET_CONFIG reply from DPOA. 1480 */ 1481 enum set_config_status { 1482 SET_CONFIG_PENDING = 0, 1483 SET_CONFIG_ACK_RECEIVED, 1484 SET_CONFIG_RX_TIMEOUT, 1485 SET_CONFIG_UNKNOWN_ERROR, 1486 }; 1487 1488 /** 1489 * Definition of a set_config reply 1490 */ 1491 struct set_config_reply_control_data { 1492 uint8_t instance; /* DPIA Instance */ 1493 uint8_t status; /* Set Config reply */ 1494 uint16_t pad; /* Alignment */ 1495 }; 1496 1497 /** 1498 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1499 */ 1500 struct dmub_rb_cmd_dp_set_config_reply { 1501 struct dmub_cmd_header header; 1502 struct set_config_reply_control_data set_config_reply_control; 1503 }; 1504 1505 /** 1506 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1507 */ 1508 struct dmub_cmd_hpd_state_query_data { 1509 uint8_t instance; /**< HPD instance or DPIA instance */ 1510 uint8_t result; /**< For returning HPD state */ 1511 uint16_t pad; /** < Alignment */ 1512 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1513 enum aux_return_code_type status; /**< for returning the status of command */ 1514 }; 1515 1516 /** 1517 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1518 */ 1519 struct dmub_rb_cmd_query_hpd_state { 1520 /** 1521 * Command header. 1522 */ 1523 struct dmub_cmd_header header; 1524 /** 1525 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1526 */ 1527 struct dmub_cmd_hpd_state_query_data data; 1528 }; 1529 1530 /* 1531 * Command IDs should be treated as stable ABI. 1532 * Do not reuse or modify IDs. 1533 */ 1534 1535 /** 1536 * PSR command sub-types. 1537 */ 1538 enum dmub_cmd_psr_type { 1539 /** 1540 * Set PSR version support. 1541 */ 1542 DMUB_CMD__PSR_SET_VERSION = 0, 1543 /** 1544 * Copy driver-calculated parameters to PSR state. 1545 */ 1546 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1547 /** 1548 * Enable PSR. 1549 */ 1550 DMUB_CMD__PSR_ENABLE = 2, 1551 1552 /** 1553 * Disable PSR. 1554 */ 1555 DMUB_CMD__PSR_DISABLE = 3, 1556 1557 /** 1558 * Set PSR level. 1559 * PSR level is a 16-bit value dicated by driver that 1560 * will enable/disable different functionality. 1561 */ 1562 DMUB_CMD__PSR_SET_LEVEL = 4, 1563 1564 /** 1565 * Forces PSR enabled until an explicit PSR disable call. 1566 */ 1567 DMUB_CMD__PSR_FORCE_STATIC = 5, 1568 /** 1569 * Set vtotal in psr active for FreeSync PSR. 1570 */ 1571 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1572 /** 1573 * Set PSR power option 1574 */ 1575 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1576 }; 1577 1578 enum dmub_cmd_fams_type { 1579 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1580 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1581 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1582 }; 1583 1584 /** 1585 * PSR versions. 1586 */ 1587 enum psr_version { 1588 /** 1589 * PSR version 1. 1590 */ 1591 PSR_VERSION_1 = 0, 1592 /** 1593 * Freesync PSR SU. 1594 */ 1595 PSR_VERSION_SU_1 = 1, 1596 /** 1597 * PSR not supported. 1598 */ 1599 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1600 }; 1601 1602 /** 1603 * enum dmub_cmd_mall_type - MALL commands 1604 */ 1605 enum dmub_cmd_mall_type { 1606 /** 1607 * Allows display refresh from MALL. 1608 */ 1609 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1610 /** 1611 * Disallows display refresh from MALL. 1612 */ 1613 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1614 /** 1615 * Cursor copy for MALL. 1616 */ 1617 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1618 /** 1619 * Controls DF requests. 1620 */ 1621 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1622 }; 1623 1624 /** 1625 * PHY Link rate for DP. 1626 */ 1627 enum phy_link_rate { 1628 /** 1629 * not supported. 1630 */ 1631 PHY_RATE_UNKNOWN = 0, 1632 /** 1633 * Rate_1 (RBR) - 1.62 Gbps/Lane 1634 */ 1635 PHY_RATE_162 = 1, 1636 /** 1637 * Rate_2 - 2.16 Gbps/Lane 1638 */ 1639 PHY_RATE_216 = 2, 1640 /** 1641 * Rate_3 - 2.43 Gbps/Lane 1642 */ 1643 PHY_RATE_243 = 3, 1644 /** 1645 * Rate_4 (HBR) - 2.70 Gbps/Lane 1646 */ 1647 PHY_RATE_270 = 4, 1648 /** 1649 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1650 */ 1651 PHY_RATE_324 = 5, 1652 /** 1653 * Rate_6 - 4.32 Gbps/Lane 1654 */ 1655 PHY_RATE_432 = 6, 1656 /** 1657 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1658 */ 1659 PHY_RATE_540 = 7, 1660 /** 1661 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1662 */ 1663 PHY_RATE_810 = 8, 1664 /** 1665 * UHBR10 - 10.0 Gbps/Lane 1666 */ 1667 PHY_RATE_1000 = 9, 1668 /** 1669 * UHBR13.5 - 13.5 Gbps/Lane 1670 */ 1671 PHY_RATE_1350 = 10, 1672 /** 1673 * UHBR10 - 20.0 Gbps/Lane 1674 */ 1675 PHY_RATE_2000 = 11, 1676 }; 1677 1678 /** 1679 * enum dmub_phy_fsm_state - PHY FSM states. 1680 * PHY FSM state to transit to during PSR enable/disable. 1681 */ 1682 enum dmub_phy_fsm_state { 1683 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1684 DMUB_PHY_FSM_RESET, 1685 DMUB_PHY_FSM_RESET_RELEASED, 1686 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1687 DMUB_PHY_FSM_INITIALIZED, 1688 DMUB_PHY_FSM_CALIBRATED, 1689 DMUB_PHY_FSM_CALIBRATED_LP, 1690 DMUB_PHY_FSM_CALIBRATED_PG, 1691 DMUB_PHY_FSM_POWER_DOWN, 1692 DMUB_PHY_FSM_PLL_EN, 1693 DMUB_PHY_FSM_TX_EN, 1694 DMUB_PHY_FSM_FAST_LP, 1695 }; 1696 1697 /** 1698 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1699 */ 1700 struct dmub_cmd_psr_copy_settings_data { 1701 /** 1702 * Flags that can be set by driver to change some PSR behaviour. 1703 */ 1704 union dmub_psr_debug_flags debug; 1705 /** 1706 * 16-bit value dicated by driver that will enable/disable different functionality. 1707 */ 1708 uint16_t psr_level; 1709 /** 1710 * DPP HW instance. 1711 */ 1712 uint8_t dpp_inst; 1713 /** 1714 * MPCC HW instance. 1715 * Not used in dmub fw, 1716 * dmub fw will get active opp by reading odm registers. 1717 */ 1718 uint8_t mpcc_inst; 1719 /** 1720 * OPP HW instance. 1721 * Not used in dmub fw, 1722 * dmub fw will get active opp by reading odm registers. 1723 */ 1724 uint8_t opp_inst; 1725 /** 1726 * OTG HW instance. 1727 */ 1728 uint8_t otg_inst; 1729 /** 1730 * DIG FE HW instance. 1731 */ 1732 uint8_t digfe_inst; 1733 /** 1734 * DIG BE HW instance. 1735 */ 1736 uint8_t digbe_inst; 1737 /** 1738 * DP PHY HW instance. 1739 */ 1740 uint8_t dpphy_inst; 1741 /** 1742 * AUX HW instance. 1743 */ 1744 uint8_t aux_inst; 1745 /** 1746 * Determines if SMU optimzations are enabled/disabled. 1747 */ 1748 uint8_t smu_optimizations_en; 1749 /** 1750 * Unused. 1751 * TODO: Remove. 1752 */ 1753 uint8_t frame_delay; 1754 /** 1755 * If RFB setup time is greater than the total VBLANK time, 1756 * it is not possible for the sink to capture the video frame 1757 * in the same frame the SDP is sent. In this case, 1758 * the frame capture indication bit should be set and an extra 1759 * static frame should be transmitted to the sink. 1760 */ 1761 uint8_t frame_cap_ind; 1762 /** 1763 * Granularity of Y offset supported by sink. 1764 */ 1765 uint8_t su_y_granularity; 1766 /** 1767 * Indicates whether sink should start capturing 1768 * immediately following active scan line, 1769 * or starting with the 2nd active scan line. 1770 */ 1771 uint8_t line_capture_indication; 1772 /** 1773 * Multi-display optimizations are implemented on certain ASICs. 1774 */ 1775 uint8_t multi_disp_optimizations_en; 1776 /** 1777 * The last possible line SDP may be transmitted without violating 1778 * the RFB setup time or entering the active video frame. 1779 */ 1780 uint16_t init_sdp_deadline; 1781 /** 1782 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1783 */ 1784 uint8_t rate_control_caps ; 1785 /* 1786 * Force PSRSU always doing full frame update 1787 */ 1788 uint8_t force_ffu_mode; 1789 /** 1790 * Length of each horizontal line in us. 1791 */ 1792 uint32_t line_time_in_us; 1793 /** 1794 * FEC enable status in driver 1795 */ 1796 uint8_t fec_enable_status; 1797 /** 1798 * FEC re-enable delay when PSR exit. 1799 * unit is 100us, range form 0~255(0xFF). 1800 */ 1801 uint8_t fec_enable_delay_in100us; 1802 /** 1803 * PSR control version. 1804 */ 1805 uint8_t cmd_version; 1806 /** 1807 * Panel Instance. 1808 * Panel isntance to identify which psr_state to use 1809 * Currently the support is only for 0 or 1 1810 */ 1811 uint8_t panel_inst; 1812 /* 1813 * DSC enable status in driver 1814 */ 1815 uint8_t dsc_enable_status; 1816 /* 1817 * Use FSM state for PSR power up/down 1818 */ 1819 uint8_t use_phy_fsm; 1820 /** 1821 * Explicit padding to 2 byte boundary. 1822 */ 1823 uint8_t pad3[2]; 1824 }; 1825 1826 /** 1827 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1828 */ 1829 struct dmub_rb_cmd_psr_copy_settings { 1830 /** 1831 * Command header. 1832 */ 1833 struct dmub_cmd_header header; 1834 /** 1835 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1836 */ 1837 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1838 }; 1839 1840 /** 1841 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1842 */ 1843 struct dmub_cmd_psr_set_level_data { 1844 /** 1845 * 16-bit value dicated by driver that will enable/disable different functionality. 1846 */ 1847 uint16_t psr_level; 1848 /** 1849 * PSR control version. 1850 */ 1851 uint8_t cmd_version; 1852 /** 1853 * Panel Instance. 1854 * Panel isntance to identify which psr_state to use 1855 * Currently the support is only for 0 or 1 1856 */ 1857 uint8_t panel_inst; 1858 }; 1859 1860 /** 1861 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1862 */ 1863 struct dmub_rb_cmd_psr_set_level { 1864 /** 1865 * Command header. 1866 */ 1867 struct dmub_cmd_header header; 1868 /** 1869 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1870 */ 1871 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1872 }; 1873 1874 struct dmub_rb_cmd_psr_enable_data { 1875 /** 1876 * PSR control version. 1877 */ 1878 uint8_t cmd_version; 1879 /** 1880 * Panel Instance. 1881 * Panel isntance to identify which psr_state to use 1882 * Currently the support is only for 0 or 1 1883 */ 1884 uint8_t panel_inst; 1885 /** 1886 * Phy state to enter. 1887 * Values to use are defined in dmub_phy_fsm_state 1888 */ 1889 uint8_t phy_fsm_state; 1890 /** 1891 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1892 * Set this using enum phy_link_rate. 1893 * This does not support HDMI/DP2 for now. 1894 */ 1895 uint8_t phy_rate; 1896 }; 1897 1898 /** 1899 * Definition of a DMUB_CMD__PSR_ENABLE command. 1900 * PSR enable/disable is controlled using the sub_type. 1901 */ 1902 struct dmub_rb_cmd_psr_enable { 1903 /** 1904 * Command header. 1905 */ 1906 struct dmub_cmd_header header; 1907 1908 struct dmub_rb_cmd_psr_enable_data data; 1909 }; 1910 1911 /** 1912 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1913 */ 1914 struct dmub_cmd_psr_set_version_data { 1915 /** 1916 * PSR version that FW should implement. 1917 */ 1918 enum psr_version version; 1919 /** 1920 * PSR control version. 1921 */ 1922 uint8_t cmd_version; 1923 /** 1924 * Panel Instance. 1925 * Panel isntance to identify which psr_state to use 1926 * Currently the support is only for 0 or 1 1927 */ 1928 uint8_t panel_inst; 1929 /** 1930 * Explicit padding to 4 byte boundary. 1931 */ 1932 uint8_t pad[2]; 1933 }; 1934 1935 /** 1936 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1937 */ 1938 struct dmub_rb_cmd_psr_set_version { 1939 /** 1940 * Command header. 1941 */ 1942 struct dmub_cmd_header header; 1943 /** 1944 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1945 */ 1946 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1947 }; 1948 1949 struct dmub_cmd_psr_force_static_data { 1950 /** 1951 * PSR control version. 1952 */ 1953 uint8_t cmd_version; 1954 /** 1955 * Panel Instance. 1956 * Panel isntance to identify which psr_state to use 1957 * Currently the support is only for 0 or 1 1958 */ 1959 uint8_t panel_inst; 1960 /** 1961 * Explicit padding to 4 byte boundary. 1962 */ 1963 uint8_t pad[2]; 1964 }; 1965 1966 /** 1967 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 1968 */ 1969 struct dmub_rb_cmd_psr_force_static { 1970 /** 1971 * Command header. 1972 */ 1973 struct dmub_cmd_header header; 1974 /** 1975 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1976 */ 1977 struct dmub_cmd_psr_force_static_data psr_force_static_data; 1978 }; 1979 1980 /** 1981 * PSR SU debug flags. 1982 */ 1983 union dmub_psr_su_debug_flags { 1984 /** 1985 * PSR SU debug flags. 1986 */ 1987 struct { 1988 /** 1989 * Update dirty rect in SW only. 1990 */ 1991 uint8_t update_dirty_rect_only : 1; 1992 /** 1993 * Reset the cursor/plane state before processing the call. 1994 */ 1995 uint8_t reset_state : 1; 1996 } bitfields; 1997 1998 /** 1999 * Union for debug flags. 2000 */ 2001 uint32_t u32All; 2002 }; 2003 2004 /** 2005 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2006 * This triggers a selective update for PSR SU. 2007 */ 2008 struct dmub_cmd_update_dirty_rect_data { 2009 /** 2010 * Dirty rects from OS. 2011 */ 2012 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2013 /** 2014 * PSR SU debug flags. 2015 */ 2016 union dmub_psr_su_debug_flags debug_flags; 2017 /** 2018 * OTG HW instance. 2019 */ 2020 uint8_t pipe_idx; 2021 /** 2022 * Number of dirty rects. 2023 */ 2024 uint8_t dirty_rect_count; 2025 /** 2026 * PSR control version. 2027 */ 2028 uint8_t cmd_version; 2029 /** 2030 * Panel Instance. 2031 * Panel isntance to identify which psr_state to use 2032 * Currently the support is only for 0 or 1 2033 */ 2034 uint8_t panel_inst; 2035 }; 2036 2037 /** 2038 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2039 */ 2040 struct dmub_rb_cmd_update_dirty_rect { 2041 /** 2042 * Command header. 2043 */ 2044 struct dmub_cmd_header header; 2045 /** 2046 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2047 */ 2048 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2049 }; 2050 2051 /** 2052 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2053 */ 2054 struct dmub_cmd_update_cursor_info_data { 2055 /** 2056 * Cursor dirty rects. 2057 */ 2058 struct dmub_rect cursor_rect; 2059 /** 2060 * PSR SU debug flags. 2061 */ 2062 union dmub_psr_su_debug_flags debug_flags; 2063 /** 2064 * Cursor enable/disable. 2065 */ 2066 uint8_t enable; 2067 /** 2068 * OTG HW instance. 2069 */ 2070 uint8_t pipe_idx; 2071 /** 2072 * PSR control version. 2073 */ 2074 uint8_t cmd_version; 2075 /** 2076 * Panel Instance. 2077 * Panel isntance to identify which psr_state to use 2078 * Currently the support is only for 0 or 1 2079 */ 2080 uint8_t panel_inst; 2081 }; 2082 /** 2083 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2084 */ 2085 struct dmub_rb_cmd_update_cursor_info { 2086 /** 2087 * Command header. 2088 */ 2089 struct dmub_cmd_header header; 2090 /** 2091 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2092 */ 2093 struct dmub_cmd_update_cursor_info_data update_cursor_info_data; 2094 }; 2095 2096 /** 2097 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2098 */ 2099 struct dmub_cmd_psr_set_vtotal_data { 2100 /** 2101 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2102 */ 2103 uint16_t psr_vtotal_idle; 2104 /** 2105 * PSR control version. 2106 */ 2107 uint8_t cmd_version; 2108 /** 2109 * Panel Instance. 2110 * Panel isntance to identify which psr_state to use 2111 * Currently the support is only for 0 or 1 2112 */ 2113 uint8_t panel_inst; 2114 /* 2115 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2116 */ 2117 uint16_t psr_vtotal_su; 2118 /** 2119 * Explicit padding to 4 byte boundary. 2120 */ 2121 uint8_t pad2[2]; 2122 }; 2123 2124 /** 2125 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2126 */ 2127 struct dmub_rb_cmd_psr_set_vtotal { 2128 /** 2129 * Command header. 2130 */ 2131 struct dmub_cmd_header header; 2132 /** 2133 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2134 */ 2135 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2136 }; 2137 2138 /** 2139 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2140 */ 2141 struct dmub_cmd_psr_set_power_opt_data { 2142 /** 2143 * PSR control version. 2144 */ 2145 uint8_t cmd_version; 2146 /** 2147 * Panel Instance. 2148 * Panel isntance to identify which psr_state to use 2149 * Currently the support is only for 0 or 1 2150 */ 2151 uint8_t panel_inst; 2152 /** 2153 * Explicit padding to 4 byte boundary. 2154 */ 2155 uint8_t pad[2]; 2156 /** 2157 * PSR power option 2158 */ 2159 uint32_t power_opt; 2160 }; 2161 2162 /** 2163 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2164 */ 2165 struct dmub_rb_cmd_psr_set_power_opt { 2166 /** 2167 * Command header. 2168 */ 2169 struct dmub_cmd_header header; 2170 /** 2171 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2172 */ 2173 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2174 }; 2175 2176 /** 2177 * Set of HW components that can be locked. 2178 * 2179 * Note: If updating with more HW components, fields 2180 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2181 */ 2182 union dmub_hw_lock_flags { 2183 /** 2184 * Set of HW components that can be locked. 2185 */ 2186 struct { 2187 /** 2188 * Lock/unlock OTG master update lock. 2189 */ 2190 uint8_t lock_pipe : 1; 2191 /** 2192 * Lock/unlock cursor. 2193 */ 2194 uint8_t lock_cursor : 1; 2195 /** 2196 * Lock/unlock global update lock. 2197 */ 2198 uint8_t lock_dig : 1; 2199 /** 2200 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2201 */ 2202 uint8_t triple_buffer_lock : 1; 2203 } bits; 2204 2205 /** 2206 * Union for HW Lock flags. 2207 */ 2208 uint8_t u8All; 2209 }; 2210 2211 /** 2212 * Instances of HW to be locked. 2213 * 2214 * Note: If updating with more HW components, fields 2215 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2216 */ 2217 struct dmub_hw_lock_inst_flags { 2218 /** 2219 * OTG HW instance for OTG master update lock. 2220 */ 2221 uint8_t otg_inst; 2222 /** 2223 * OPP instance for cursor lock. 2224 */ 2225 uint8_t opp_inst; 2226 /** 2227 * OTG HW instance for global update lock. 2228 * TODO: Remove, and re-use otg_inst. 2229 */ 2230 uint8_t dig_inst; 2231 /** 2232 * Explicit pad to 4 byte boundary. 2233 */ 2234 uint8_t pad; 2235 }; 2236 2237 /** 2238 * Clients that can acquire the HW Lock Manager. 2239 * 2240 * Note: If updating with more clients, fields in 2241 * dmub_inbox0_cmd_lock_hw must be updated to match. 2242 */ 2243 enum hw_lock_client { 2244 /** 2245 * Driver is the client of HW Lock Manager. 2246 */ 2247 HW_LOCK_CLIENT_DRIVER = 0, 2248 /** 2249 * PSR SU is the client of HW Lock Manager. 2250 */ 2251 HW_LOCK_CLIENT_PSR_SU = 1, 2252 /** 2253 * Invalid client. 2254 */ 2255 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2256 }; 2257 2258 /** 2259 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2260 */ 2261 struct dmub_cmd_lock_hw_data { 2262 /** 2263 * Specifies the client accessing HW Lock Manager. 2264 */ 2265 enum hw_lock_client client; 2266 /** 2267 * HW instances to be locked. 2268 */ 2269 struct dmub_hw_lock_inst_flags inst_flags; 2270 /** 2271 * Which components to be locked. 2272 */ 2273 union dmub_hw_lock_flags hw_locks; 2274 /** 2275 * Specifies lock/unlock. 2276 */ 2277 uint8_t lock; 2278 /** 2279 * HW can be unlocked separately from releasing the HW Lock Mgr. 2280 * This flag is set if the client wishes to release the object. 2281 */ 2282 uint8_t should_release; 2283 /** 2284 * Explicit padding to 4 byte boundary. 2285 */ 2286 uint8_t pad; 2287 }; 2288 2289 /** 2290 * Definition of a DMUB_CMD__HW_LOCK command. 2291 * Command is used by driver and FW. 2292 */ 2293 struct dmub_rb_cmd_lock_hw { 2294 /** 2295 * Command header. 2296 */ 2297 struct dmub_cmd_header header; 2298 /** 2299 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2300 */ 2301 struct dmub_cmd_lock_hw_data lock_hw_data; 2302 }; 2303 2304 /** 2305 * ABM command sub-types. 2306 */ 2307 enum dmub_cmd_abm_type { 2308 /** 2309 * Initialize parameters for ABM algorithm. 2310 * Data is passed through an indirect buffer. 2311 */ 2312 DMUB_CMD__ABM_INIT_CONFIG = 0, 2313 /** 2314 * Set OTG and panel HW instance. 2315 */ 2316 DMUB_CMD__ABM_SET_PIPE = 1, 2317 /** 2318 * Set user requested backklight level. 2319 */ 2320 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2321 /** 2322 * Set ABM operating/aggression level. 2323 */ 2324 DMUB_CMD__ABM_SET_LEVEL = 3, 2325 /** 2326 * Set ambient light level. 2327 */ 2328 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2329 /** 2330 * Enable/disable fractional duty cycle for backlight PWM. 2331 */ 2332 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2333 2334 /** 2335 * unregister vertical interrupt after steady state is reached 2336 */ 2337 DMUB_CMD__ABM_PAUSE = 6, 2338 }; 2339 2340 /** 2341 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2342 * Requirements: 2343 * - Padded explicitly to 32-bit boundary. 2344 * - Must ensure this structure matches the one on driver-side, 2345 * otherwise it won't be aligned. 2346 */ 2347 struct abm_config_table { 2348 /** 2349 * Gamma curve thresholds, used for crgb conversion. 2350 */ 2351 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2352 /** 2353 * Gamma curve offsets, used for crgb conversion. 2354 */ 2355 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2356 /** 2357 * Gamma curve slopes, used for crgb conversion. 2358 */ 2359 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2360 /** 2361 * Custom backlight curve thresholds. 2362 */ 2363 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2364 /** 2365 * Custom backlight curve offsets. 2366 */ 2367 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2368 /** 2369 * Ambient light thresholds. 2370 */ 2371 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2372 /** 2373 * Minimum programmable backlight. 2374 */ 2375 uint16_t min_abm_backlight; // 122B 2376 /** 2377 * Minimum reduction values. 2378 */ 2379 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2380 /** 2381 * Maximum reduction values. 2382 */ 2383 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2384 /** 2385 * Bright positive gain. 2386 */ 2387 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2388 /** 2389 * Dark negative gain. 2390 */ 2391 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2392 /** 2393 * Hybrid factor. 2394 */ 2395 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2396 /** 2397 * Contrast factor. 2398 */ 2399 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2400 /** 2401 * Deviation gain. 2402 */ 2403 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2404 /** 2405 * Minimum knee. 2406 */ 2407 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2408 /** 2409 * Maximum knee. 2410 */ 2411 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2412 /** 2413 * Unused. 2414 */ 2415 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2416 /** 2417 * Explicit padding to 4 byte boundary. 2418 */ 2419 uint8_t pad3[3]; // 229B 2420 /** 2421 * Backlight ramp reduction. 2422 */ 2423 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2424 /** 2425 * Backlight ramp start. 2426 */ 2427 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2428 }; 2429 2430 /** 2431 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2432 */ 2433 struct dmub_cmd_abm_set_pipe_data { 2434 /** 2435 * OTG HW instance. 2436 */ 2437 uint8_t otg_inst; 2438 2439 /** 2440 * Panel Control HW instance. 2441 */ 2442 uint8_t panel_inst; 2443 2444 /** 2445 * Controls how ABM will interpret a set pipe or set level command. 2446 */ 2447 uint8_t set_pipe_option; 2448 2449 /** 2450 * Unused. 2451 * TODO: Remove. 2452 */ 2453 uint8_t ramping_boundary; 2454 }; 2455 2456 /** 2457 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2458 */ 2459 struct dmub_rb_cmd_abm_set_pipe { 2460 /** 2461 * Command header. 2462 */ 2463 struct dmub_cmd_header header; 2464 2465 /** 2466 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2467 */ 2468 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2469 }; 2470 2471 /** 2472 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2473 */ 2474 struct dmub_cmd_abm_set_backlight_data { 2475 /** 2476 * Number of frames to ramp to backlight user level. 2477 */ 2478 uint32_t frame_ramp; 2479 2480 /** 2481 * Requested backlight level from user. 2482 */ 2483 uint32_t backlight_user_level; 2484 2485 /** 2486 * ABM control version. 2487 */ 2488 uint8_t version; 2489 2490 /** 2491 * Panel Control HW instance mask. 2492 * Bit 0 is Panel Control HW instance 0. 2493 * Bit 1 is Panel Control HW instance 1. 2494 */ 2495 uint8_t panel_mask; 2496 2497 /** 2498 * Explicit padding to 4 byte boundary. 2499 */ 2500 uint8_t pad[2]; 2501 }; 2502 2503 /** 2504 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2505 */ 2506 struct dmub_rb_cmd_abm_set_backlight { 2507 /** 2508 * Command header. 2509 */ 2510 struct dmub_cmd_header header; 2511 2512 /** 2513 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2514 */ 2515 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2516 }; 2517 2518 /** 2519 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2520 */ 2521 struct dmub_cmd_abm_set_level_data { 2522 /** 2523 * Set current ABM operating/aggression level. 2524 */ 2525 uint32_t level; 2526 2527 /** 2528 * ABM control version. 2529 */ 2530 uint8_t version; 2531 2532 /** 2533 * Panel Control HW instance mask. 2534 * Bit 0 is Panel Control HW instance 0. 2535 * Bit 1 is Panel Control HW instance 1. 2536 */ 2537 uint8_t panel_mask; 2538 2539 /** 2540 * Explicit padding to 4 byte boundary. 2541 */ 2542 uint8_t pad[2]; 2543 }; 2544 2545 /** 2546 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2547 */ 2548 struct dmub_rb_cmd_abm_set_level { 2549 /** 2550 * Command header. 2551 */ 2552 struct dmub_cmd_header header; 2553 2554 /** 2555 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2556 */ 2557 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2558 }; 2559 2560 /** 2561 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2562 */ 2563 struct dmub_cmd_abm_set_ambient_level_data { 2564 /** 2565 * Ambient light sensor reading from OS. 2566 */ 2567 uint32_t ambient_lux; 2568 2569 /** 2570 * ABM control version. 2571 */ 2572 uint8_t version; 2573 2574 /** 2575 * Panel Control HW instance mask. 2576 * Bit 0 is Panel Control HW instance 0. 2577 * Bit 1 is Panel Control HW instance 1. 2578 */ 2579 uint8_t panel_mask; 2580 2581 /** 2582 * Explicit padding to 4 byte boundary. 2583 */ 2584 uint8_t pad[2]; 2585 }; 2586 2587 /** 2588 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2589 */ 2590 struct dmub_rb_cmd_abm_set_ambient_level { 2591 /** 2592 * Command header. 2593 */ 2594 struct dmub_cmd_header header; 2595 2596 /** 2597 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2598 */ 2599 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2600 }; 2601 2602 /** 2603 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2604 */ 2605 struct dmub_cmd_abm_set_pwm_frac_data { 2606 /** 2607 * Enable/disable fractional duty cycle for backlight PWM. 2608 * TODO: Convert to uint8_t. 2609 */ 2610 uint32_t fractional_pwm; 2611 2612 /** 2613 * ABM control version. 2614 */ 2615 uint8_t version; 2616 2617 /** 2618 * Panel Control HW instance mask. 2619 * Bit 0 is Panel Control HW instance 0. 2620 * Bit 1 is Panel Control HW instance 1. 2621 */ 2622 uint8_t panel_mask; 2623 2624 /** 2625 * Explicit padding to 4 byte boundary. 2626 */ 2627 uint8_t pad[2]; 2628 }; 2629 2630 /** 2631 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2632 */ 2633 struct dmub_rb_cmd_abm_set_pwm_frac { 2634 /** 2635 * Command header. 2636 */ 2637 struct dmub_cmd_header header; 2638 2639 /** 2640 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2641 */ 2642 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2643 }; 2644 2645 /** 2646 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2647 */ 2648 struct dmub_cmd_abm_init_config_data { 2649 /** 2650 * Location of indirect buffer used to pass init data to ABM. 2651 */ 2652 union dmub_addr src; 2653 2654 /** 2655 * Indirect buffer length. 2656 */ 2657 uint16_t bytes; 2658 2659 2660 /** 2661 * ABM control version. 2662 */ 2663 uint8_t version; 2664 2665 /** 2666 * Panel Control HW instance mask. 2667 * Bit 0 is Panel Control HW instance 0. 2668 * Bit 1 is Panel Control HW instance 1. 2669 */ 2670 uint8_t panel_mask; 2671 2672 /** 2673 * Explicit padding to 4 byte boundary. 2674 */ 2675 uint8_t pad[2]; 2676 }; 2677 2678 /** 2679 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2680 */ 2681 struct dmub_rb_cmd_abm_init_config { 2682 /** 2683 * Command header. 2684 */ 2685 struct dmub_cmd_header header; 2686 2687 /** 2688 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2689 */ 2690 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2691 }; 2692 2693 /** 2694 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2695 */ 2696 2697 struct dmub_cmd_abm_pause_data { 2698 2699 /** 2700 * Panel Control HW instance mask. 2701 * Bit 0 is Panel Control HW instance 0. 2702 * Bit 1 is Panel Control HW instance 1. 2703 */ 2704 uint8_t panel_mask; 2705 2706 /** 2707 * OTG hw instance 2708 */ 2709 uint8_t otg_inst; 2710 2711 /** 2712 * Enable or disable ABM pause 2713 */ 2714 uint8_t enable; 2715 2716 /** 2717 * Explicit padding to 4 byte boundary. 2718 */ 2719 uint8_t pad[1]; 2720 }; 2721 2722 /** 2723 * Definition of a DMUB_CMD__ABM_PAUSE command. 2724 */ 2725 struct dmub_rb_cmd_abm_pause { 2726 /** 2727 * Command header. 2728 */ 2729 struct dmub_cmd_header header; 2730 2731 /** 2732 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2733 */ 2734 struct dmub_cmd_abm_pause_data abm_pause_data; 2735 }; 2736 2737 /** 2738 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2739 */ 2740 struct dmub_cmd_query_feature_caps_data { 2741 /** 2742 * DMUB feature capabilities. 2743 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2744 */ 2745 struct dmub_feature_caps feature_caps; 2746 }; 2747 2748 /** 2749 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2750 */ 2751 struct dmub_rb_cmd_query_feature_caps { 2752 /** 2753 * Command header. 2754 */ 2755 struct dmub_cmd_header header; 2756 /** 2757 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2758 */ 2759 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2760 }; 2761 2762 struct dmub_optc_state { 2763 uint32_t v_total_max; 2764 uint32_t v_total_min; 2765 uint32_t v_total_mid; 2766 uint32_t v_total_mid_frame_num; 2767 uint32_t tg_inst; 2768 uint32_t enable_manual_trigger; 2769 uint32_t clear_force_vsync; 2770 }; 2771 2772 struct dmub_rb_cmd_drr_update { 2773 struct dmub_cmd_header header; 2774 struct dmub_optc_state dmub_optc_state_req; 2775 }; 2776 2777 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 2778 uint32_t pix_clk_100hz; 2779 uint8_t max_ramp_step; 2780 uint8_t pipes; 2781 uint8_t min_refresh_in_hz; 2782 uint8_t padding[1]; 2783 }; 2784 2785 struct dmub_cmd_fw_assisted_mclk_switch_config { 2786 uint8_t fams_enabled; 2787 uint8_t visual_confirm_enabled; 2788 uint8_t padding[2]; 2789 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 2790 }; 2791 2792 struct dmub_rb_cmd_fw_assisted_mclk_switch { 2793 struct dmub_cmd_header header; 2794 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 2795 }; 2796 2797 /** 2798 * enum dmub_cmd_panel_cntl_type - Panel control command. 2799 */ 2800 enum dmub_cmd_panel_cntl_type { 2801 /** 2802 * Initializes embedded panel hardware blocks. 2803 */ 2804 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2805 /** 2806 * Queries backlight info for the embedded panel. 2807 */ 2808 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2809 }; 2810 2811 /** 2812 * struct dmub_cmd_panel_cntl_data - Panel control data. 2813 */ 2814 struct dmub_cmd_panel_cntl_data { 2815 uint32_t inst; /**< panel instance */ 2816 uint32_t current_backlight; /* in/out */ 2817 uint32_t bl_pwm_cntl; /* in/out */ 2818 uint32_t bl_pwm_period_cntl; /* in/out */ 2819 uint32_t bl_pwm_ref_div1; /* in/out */ 2820 uint8_t is_backlight_on : 1; /* in/out */ 2821 uint8_t is_powered_on : 1; /* in/out */ 2822 uint8_t padding[3]; 2823 uint32_t bl_pwm_ref_div2; /* in/out */ 2824 uint8_t reserved[4]; 2825 }; 2826 2827 /** 2828 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2829 */ 2830 struct dmub_rb_cmd_panel_cntl { 2831 struct dmub_cmd_header header; /**< header */ 2832 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2833 }; 2834 2835 /** 2836 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2837 */ 2838 struct dmub_cmd_lvtma_control_data { 2839 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2840 uint8_t reserved_0[3]; /**< For future use */ 2841 uint8_t panel_inst; /**< LVTMA control instance */ 2842 uint8_t reserved_1[3]; /**< For future use */ 2843 }; 2844 2845 /** 2846 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2847 */ 2848 struct dmub_rb_cmd_lvtma_control { 2849 /** 2850 * Command header. 2851 */ 2852 struct dmub_cmd_header header; 2853 /** 2854 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2855 */ 2856 struct dmub_cmd_lvtma_control_data data; 2857 }; 2858 2859 /** 2860 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2861 */ 2862 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 2863 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2864 uint8_t is_usb; /**< is phy is usb */ 2865 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 2866 uint8_t is_dp4; /**< is dp in 4 lane */ 2867 }; 2868 2869 /** 2870 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2871 */ 2872 struct dmub_rb_cmd_transmitter_query_dp_alt { 2873 struct dmub_cmd_header header; /**< header */ 2874 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 2875 }; 2876 2877 /** 2878 * Maximum number of bytes a chunk sent to DMUB for parsing 2879 */ 2880 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2881 2882 /** 2883 * Represent a chunk of CEA blocks sent to DMUB for parsing 2884 */ 2885 struct dmub_cmd_send_edid_cea { 2886 uint16_t offset; /**< offset into the CEA block */ 2887 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2888 uint16_t cea_total_length; /**< total length of the CEA block */ 2889 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2890 uint8_t pad[3]; /**< padding and for future expansion */ 2891 }; 2892 2893 /** 2894 * Result of VSDB parsing from CEA block 2895 */ 2896 struct dmub_cmd_edid_cea_amd_vsdb { 2897 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2898 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2899 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2900 uint16_t min_frame_rate; /**< Maximum frame rate */ 2901 uint16_t max_frame_rate; /**< Minimum frame rate */ 2902 }; 2903 2904 /** 2905 * Result of sending a CEA chunk 2906 */ 2907 struct dmub_cmd_edid_cea_ack { 2908 uint16_t offset; /**< offset of the chunk into the CEA block */ 2909 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2910 uint8_t pad; /**< padding and for future expansion */ 2911 }; 2912 2913 /** 2914 * Specify whether the result is an ACK/NACK or the parsing has finished 2915 */ 2916 enum dmub_cmd_edid_cea_reply_type { 2917 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2918 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2919 }; 2920 2921 /** 2922 * Definition of a DMUB_CMD__EDID_CEA command. 2923 */ 2924 struct dmub_rb_cmd_edid_cea { 2925 struct dmub_cmd_header header; /**< Command header */ 2926 union dmub_cmd_edid_cea_data { 2927 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2928 struct dmub_cmd_edid_cea_output { /**< output with results */ 2929 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2930 union { 2931 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2932 struct dmub_cmd_edid_cea_ack ack; 2933 }; 2934 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2935 } data; /**< Command data */ 2936 2937 }; 2938 2939 /** 2940 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 2941 */ 2942 struct dmub_cmd_cable_id_input { 2943 uint8_t phy_inst; /**< phy inst for cable id data */ 2944 }; 2945 2946 /** 2947 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 2948 */ 2949 struct dmub_cmd_cable_id_output { 2950 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 2951 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 2952 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 2953 uint8_t RESERVED :2; /**< reserved means not defined */ 2954 }; 2955 2956 /** 2957 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 2958 */ 2959 struct dmub_rb_cmd_get_usbc_cable_id { 2960 struct dmub_cmd_header header; /**< Command header */ 2961 /** 2962 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 2963 */ 2964 union dmub_cmd_cable_id_data { 2965 struct dmub_cmd_cable_id_input input; /**< Input */ 2966 struct dmub_cmd_cable_id_output output; /**< Output */ 2967 uint8_t output_raw; /**< Raw data output */ 2968 } data; 2969 }; 2970 2971 /** 2972 * union dmub_rb_cmd - DMUB inbox command. 2973 */ 2974 union dmub_rb_cmd { 2975 /** 2976 * Elements shared with all commands. 2977 */ 2978 struct dmub_rb_cmd_common cmd_common; 2979 /** 2980 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2981 */ 2982 struct dmub_rb_cmd_read_modify_write read_modify_write; 2983 /** 2984 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2985 */ 2986 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2987 /** 2988 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2989 */ 2990 struct dmub_rb_cmd_burst_write burst_write; 2991 /** 2992 * Definition of a DMUB_CMD__REG_REG_WAIT command. 2993 */ 2994 struct dmub_rb_cmd_reg_wait reg_wait; 2995 /** 2996 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2997 */ 2998 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2999 /** 3000 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3001 */ 3002 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3003 /** 3004 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3005 */ 3006 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3007 /** 3008 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3009 */ 3010 struct dmub_rb_cmd_dpphy_init dpphy_init; 3011 /** 3012 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3013 */ 3014 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3015 /** 3016 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3017 */ 3018 struct dmub_rb_cmd_psr_set_version psr_set_version; 3019 /** 3020 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3021 */ 3022 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3023 /** 3024 * Definition of a DMUB_CMD__PSR_ENABLE command. 3025 */ 3026 struct dmub_rb_cmd_psr_enable psr_enable; 3027 /** 3028 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3029 */ 3030 struct dmub_rb_cmd_psr_set_level psr_set_level; 3031 /** 3032 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3033 */ 3034 struct dmub_rb_cmd_psr_force_static psr_force_static; 3035 /** 3036 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3037 */ 3038 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3039 /** 3040 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3041 */ 3042 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3043 /** 3044 * Definition of a DMUB_CMD__HW_LOCK command. 3045 * Command is used by driver and FW. 3046 */ 3047 struct dmub_rb_cmd_lock_hw lock_hw; 3048 /** 3049 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3050 */ 3051 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3052 /** 3053 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3054 */ 3055 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3056 /** 3057 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3058 */ 3059 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3060 /** 3061 * Definition of a DMUB_CMD__MALL command. 3062 */ 3063 struct dmub_rb_cmd_mall mall; 3064 /** 3065 * Definition of a DMUB_CMD__CAB command. 3066 */ 3067 struct dmub_rb_cmd_cab_for_ss cab; 3068 3069 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3070 3071 /** 3072 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3073 */ 3074 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3075 3076 /** 3077 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3078 */ 3079 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3080 3081 /** 3082 * Definition of DMUB_CMD__PANEL_CNTL commands. 3083 */ 3084 struct dmub_rb_cmd_panel_cntl panel_cntl; 3085 /** 3086 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3087 */ 3088 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3089 3090 /** 3091 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3092 */ 3093 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3094 3095 /** 3096 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3097 */ 3098 struct dmub_rb_cmd_abm_set_level abm_set_level; 3099 3100 /** 3101 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3102 */ 3103 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3104 3105 /** 3106 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3107 */ 3108 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3109 3110 /** 3111 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3112 */ 3113 struct dmub_rb_cmd_abm_init_config abm_init_config; 3114 3115 /** 3116 * Definition of a DMUB_CMD__ABM_PAUSE command. 3117 */ 3118 struct dmub_rb_cmd_abm_pause abm_pause; 3119 3120 /** 3121 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3122 */ 3123 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3124 3125 /** 3126 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3127 */ 3128 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3129 3130 /** 3131 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3132 */ 3133 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3134 struct dmub_rb_cmd_drr_update drr_update; 3135 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3136 3137 /** 3138 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3139 */ 3140 struct dmub_rb_cmd_lvtma_control lvtma_control; 3141 /** 3142 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3143 */ 3144 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3145 /** 3146 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3147 */ 3148 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3149 /** 3150 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3151 */ 3152 struct dmub_rb_cmd_set_config_access set_config_access; 3153 /** 3154 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3155 */ 3156 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3157 /** 3158 * Definition of a DMUB_CMD__EDID_CEA command. 3159 */ 3160 struct dmub_rb_cmd_edid_cea edid_cea; 3161 /** 3162 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3163 */ 3164 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3165 3166 /** 3167 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3168 */ 3169 struct dmub_rb_cmd_query_hpd_state query_hpd; 3170 }; 3171 3172 /** 3173 * union dmub_rb_out_cmd - Outbox command 3174 */ 3175 union dmub_rb_out_cmd { 3176 /** 3177 * Parameters common to every command. 3178 */ 3179 struct dmub_rb_cmd_common cmd_common; 3180 /** 3181 * AUX reply command. 3182 */ 3183 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3184 /** 3185 * HPD notify command. 3186 */ 3187 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3188 /** 3189 * SET_CONFIG reply command. 3190 */ 3191 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3192 }; 3193 #pragma pack(pop) 3194 3195 3196 //============================================================================== 3197 //</DMUB_CMD>=================================================================== 3198 //============================================================================== 3199 //< DMUB_RB>==================================================================== 3200 //============================================================================== 3201 3202 #if defined(__cplusplus) 3203 extern "C" { 3204 #endif 3205 3206 /** 3207 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3208 */ 3209 struct dmub_rb_init_params { 3210 void *ctx; /**< Caller provided context pointer */ 3211 void *base_address; /**< CPU base address for ring's data */ 3212 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3213 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3214 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3215 }; 3216 3217 /** 3218 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3219 */ 3220 struct dmub_rb { 3221 void *base_address; /**< CPU address for the ring's data */ 3222 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3223 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3224 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3225 3226 void *ctx; /**< Caller provided context pointer */ 3227 void *dmub; /**< Pointer to the DMUB interface */ 3228 }; 3229 3230 /** 3231 * @brief Checks if the ringbuffer is empty. 3232 * 3233 * @param rb DMUB Ringbuffer 3234 * @return true if empty 3235 * @return false otherwise 3236 */ 3237 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3238 { 3239 return (rb->wrpt == rb->rptr); 3240 } 3241 3242 /** 3243 * @brief Checks if the ringbuffer is full 3244 * 3245 * @param rb DMUB Ringbuffer 3246 * @return true if full 3247 * @return false otherwise 3248 */ 3249 static inline bool dmub_rb_full(struct dmub_rb *rb) 3250 { 3251 uint32_t data_count; 3252 3253 if (rb->wrpt >= rb->rptr) 3254 data_count = rb->wrpt - rb->rptr; 3255 else 3256 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3257 3258 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3259 } 3260 3261 /** 3262 * @brief Pushes a command into the ringbuffer 3263 * 3264 * @param rb DMUB ringbuffer 3265 * @param cmd The command to push 3266 * @return true if the ringbuffer was not full 3267 * @return false otherwise 3268 */ 3269 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3270 const union dmub_rb_cmd *cmd) 3271 { 3272 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3273 const uint64_t *src = (const uint64_t *)cmd; 3274 uint8_t i; 3275 3276 if (dmub_rb_full(rb)) 3277 return false; 3278 3279 // copying data 3280 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3281 *dst++ = *src++; 3282 3283 rb->wrpt += DMUB_RB_CMD_SIZE; 3284 3285 if (rb->wrpt >= rb->capacity) 3286 rb->wrpt %= rb->capacity; 3287 3288 return true; 3289 } 3290 3291 /** 3292 * @brief Pushes a command into the DMUB outbox ringbuffer 3293 * 3294 * @param rb DMUB outbox ringbuffer 3295 * @param cmd Outbox command 3296 * @return true if not full 3297 * @return false otherwise 3298 */ 3299 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3300 const union dmub_rb_out_cmd *cmd) 3301 { 3302 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3303 const uint8_t *src = (const uint8_t *)cmd; 3304 3305 if (dmub_rb_full(rb)) 3306 return false; 3307 3308 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3309 3310 rb->wrpt += DMUB_RB_CMD_SIZE; 3311 3312 if (rb->wrpt >= rb->capacity) 3313 rb->wrpt %= rb->capacity; 3314 3315 return true; 3316 } 3317 3318 /** 3319 * @brief Returns the next unprocessed command in the ringbuffer. 3320 * 3321 * @param rb DMUB ringbuffer 3322 * @param cmd The command to return 3323 * @return true if not empty 3324 * @return false otherwise 3325 */ 3326 static inline bool dmub_rb_front(struct dmub_rb *rb, 3327 union dmub_rb_cmd **cmd) 3328 { 3329 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3330 3331 if (dmub_rb_empty(rb)) 3332 return false; 3333 3334 *cmd = (union dmub_rb_cmd *)rb_cmd; 3335 3336 return true; 3337 } 3338 3339 /** 3340 * @brief Determines the next ringbuffer offset. 3341 * 3342 * @param rb DMUB inbox ringbuffer 3343 * @param num_cmds Number of commands 3344 * @param next_rptr The next offset in the ringbuffer 3345 */ 3346 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3347 uint32_t num_cmds, 3348 uint32_t *next_rptr) 3349 { 3350 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3351 3352 if (*next_rptr >= rb->capacity) 3353 *next_rptr %= rb->capacity; 3354 } 3355 3356 /** 3357 * @brief Returns a pointer to a command in the inbox. 3358 * 3359 * @param rb DMUB inbox ringbuffer 3360 * @param cmd The inbox command to return 3361 * @param rptr The ringbuffer offset 3362 * @return true if not empty 3363 * @return false otherwise 3364 */ 3365 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3366 union dmub_rb_cmd **cmd, 3367 uint32_t rptr) 3368 { 3369 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3370 3371 if (dmub_rb_empty(rb)) 3372 return false; 3373 3374 *cmd = (union dmub_rb_cmd *)rb_cmd; 3375 3376 return true; 3377 } 3378 3379 /** 3380 * @brief Returns the next unprocessed command in the outbox. 3381 * 3382 * @param rb DMUB outbox ringbuffer 3383 * @param cmd The outbox command to return 3384 * @return true if not empty 3385 * @return false otherwise 3386 */ 3387 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3388 union dmub_rb_out_cmd *cmd) 3389 { 3390 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3391 uint64_t *dst = (uint64_t *)cmd; 3392 uint8_t i; 3393 3394 if (dmub_rb_empty(rb)) 3395 return false; 3396 3397 // copying data 3398 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3399 *dst++ = *src++; 3400 3401 return true; 3402 } 3403 3404 /** 3405 * @brief Removes the front entry in the ringbuffer. 3406 * 3407 * @param rb DMUB ringbuffer 3408 * @return true if the command was removed 3409 * @return false if there were no commands 3410 */ 3411 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3412 { 3413 if (dmub_rb_empty(rb)) 3414 return false; 3415 3416 rb->rptr += DMUB_RB_CMD_SIZE; 3417 3418 if (rb->rptr >= rb->capacity) 3419 rb->rptr %= rb->capacity; 3420 3421 return true; 3422 } 3423 3424 /** 3425 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3426 * 3427 * Avoids a race condition where DMCUB accesses memory while 3428 * there are still writes in flight to framebuffer. 3429 * 3430 * @param rb DMUB ringbuffer 3431 */ 3432 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3433 { 3434 uint32_t rptr = rb->rptr; 3435 uint32_t wptr = rb->wrpt; 3436 3437 while (rptr != wptr) { 3438 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3439 uint8_t i; 3440 3441 /* Don't remove this. 3442 * The contents need to actually be read from the ring buffer 3443 * for this function to be effective. 3444 */ 3445 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3446 (void)READ_ONCE(*data++); 3447 3448 rptr += DMUB_RB_CMD_SIZE; 3449 if (rptr >= rb->capacity) 3450 rptr %= rb->capacity; 3451 } 3452 } 3453 3454 /** 3455 * @brief Initializes a DMCUB ringbuffer 3456 * 3457 * @param rb DMUB ringbuffer 3458 * @param init_params initial configuration for the ringbuffer 3459 */ 3460 static inline void dmub_rb_init(struct dmub_rb *rb, 3461 struct dmub_rb_init_params *init_params) 3462 { 3463 rb->base_address = init_params->base_address; 3464 rb->capacity = init_params->capacity; 3465 rb->rptr = init_params->read_ptr; 3466 rb->wrpt = init_params->write_ptr; 3467 } 3468 3469 /** 3470 * @brief Copies output data from in/out commands into the given command. 3471 * 3472 * @param rb DMUB ringbuffer 3473 * @param cmd Command to copy data into 3474 */ 3475 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3476 union dmub_rb_cmd *cmd) 3477 { 3478 // Copy rb entry back into command 3479 uint8_t *rd_ptr = (rb->rptr == 0) ? 3480 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3481 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3482 3483 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3484 } 3485 3486 #if defined(__cplusplus) 3487 } 3488 #endif 3489 3490 //============================================================================== 3491 //</DMUB_RB>==================================================================== 3492 //============================================================================== 3493 3494 #endif /* _DMUB_CMD_H_ */ 3495