17c008829SNicholas Kazlauskas /* 27c008829SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 37c008829SNicholas Kazlauskas * 47c008829SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 57c008829SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 67c008829SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 77c008829SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87c008829SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 97c008829SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 107c008829SNicholas Kazlauskas * 117c008829SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 127c008829SNicholas Kazlauskas * all copies or substantial portions of the Software. 137c008829SNicholas Kazlauskas * 147c008829SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157c008829SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167c008829SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177c008829SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187c008829SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197c008829SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207c008829SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 217c008829SNicholas Kazlauskas * 227c008829SNicholas Kazlauskas * Authors: AMD 237c008829SNicholas Kazlauskas * 247c008829SNicholas Kazlauskas */ 257c008829SNicholas Kazlauskas 267c008829SNicholas Kazlauskas #ifndef _DMUB_CMD_H_ 277c008829SNicholas Kazlauskas #define _DMUB_CMD_H_ 287c008829SNicholas Kazlauskas 2984034ad4SAnthony Koo #include <asm/byteorder.h> 3084034ad4SAnthony Koo #include <linux/types.h> 3184034ad4SAnthony Koo #include <linux/string.h> 3284034ad4SAnthony Koo #include <linux/delay.h> 3384034ad4SAnthony Koo #include <stdarg.h> 3484034ad4SAnthony Koo 357c008829SNicholas Kazlauskas #include "atomfirmware.h" 3622aa5614SYongqiang Sun 378598a722SAnthony Koo /* Firmware versioning. */ 388598a722SAnthony Koo #ifdef DMUB_EXPOSE_VERSION 39*fd0f1d21SAnthony Koo #define DMUB_FW_VERSION_GIT_HASH 0x8aafc9acc 40b2265774SAnthony Koo #define DMUB_FW_VERSION_MAJOR 0 418598a722SAnthony Koo #define DMUB_FW_VERSION_MINOR 0 42*fd0f1d21SAnthony Koo #define DMUB_FW_VERSION_REVISION 38 43ded750e6SAnthony Koo #define DMUB_FW_VERSION_TEST 0 44ded750e6SAnthony Koo #define DMUB_FW_VERSION_VBIOS 0 45ded750e6SAnthony Koo #define DMUB_FW_VERSION_HOTFIX 0 46ded750e6SAnthony Koo #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 47ded750e6SAnthony Koo ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 48ded750e6SAnthony Koo ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 49ded750e6SAnthony Koo ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 50ded750e6SAnthony Koo ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 51ded750e6SAnthony Koo (DMUB_FW_VERSION_HOTFIX & 0x3F)) 52ded750e6SAnthony Koo 538598a722SAnthony Koo #endif 5484034ad4SAnthony Koo 5584034ad4SAnthony Koo //<DMUB_TYPES>================================================================== 5684034ad4SAnthony Koo /* Basic type definitions. */ 5784034ad4SAnthony Koo 5884034ad4SAnthony Koo #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 5984034ad4SAnthony Koo #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 60d9beecfcSAnthony Koo #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 6184034ad4SAnthony Koo #define SET_ABM_PIPE_NORMAL 1 6284034ad4SAnthony Koo 6384034ad4SAnthony Koo /* Maximum number of streams on any ASIC. */ 6484034ad4SAnthony Koo #define DMUB_MAX_STREAMS 6 6584034ad4SAnthony Koo 6684034ad4SAnthony Koo /* Maximum number of planes on any ASIC. */ 6784034ad4SAnthony Koo #define DMUB_MAX_PLANES 6 6884034ad4SAnthony Koo 6984034ad4SAnthony Koo #ifndef PHYSICAL_ADDRESS_LOC 7084034ad4SAnthony Koo #define PHYSICAL_ADDRESS_LOC union large_integer 7184034ad4SAnthony Koo #endif 7284034ad4SAnthony Koo 7384034ad4SAnthony Koo #ifndef dmub_memcpy 7484034ad4SAnthony Koo #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 7584034ad4SAnthony Koo #endif 7684034ad4SAnthony Koo 7784034ad4SAnthony Koo #ifndef dmub_memset 7884034ad4SAnthony Koo #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 7984034ad4SAnthony Koo #endif 8084034ad4SAnthony Koo 81d9beecfcSAnthony Koo #if defined(__cplusplus) 82d9beecfcSAnthony Koo extern "C" { 83d9beecfcSAnthony Koo #endif 84d9beecfcSAnthony Koo 8584034ad4SAnthony Koo #ifndef dmub_udelay 8684034ad4SAnthony Koo #define dmub_udelay(microseconds) udelay(microseconds) 8784034ad4SAnthony Koo #endif 8884034ad4SAnthony Koo 8984034ad4SAnthony Koo union dmub_addr { 9084034ad4SAnthony Koo struct { 9184034ad4SAnthony Koo uint32_t low_part; 9284034ad4SAnthony Koo uint32_t high_part; 9384034ad4SAnthony Koo } u; 9484034ad4SAnthony Koo uint64_t quad_part; 9584034ad4SAnthony Koo }; 9684034ad4SAnthony Koo 9784034ad4SAnthony Koo union dmub_psr_debug_flags { 9884034ad4SAnthony Koo struct { 99447f3d0fSAnthony Koo uint32_t visual_confirm : 1; 100447f3d0fSAnthony Koo uint32_t use_hw_lock_mgr : 1; 1018b3f6b98SAnthony Koo uint32_t log_line_nums : 1; 10284034ad4SAnthony Koo } bitfields; 10384034ad4SAnthony Koo 104447f3d0fSAnthony Koo uint32_t u32All; 10584034ad4SAnthony Koo }; 10684034ad4SAnthony Koo 10784034ad4SAnthony Koo #if defined(__cplusplus) 10884034ad4SAnthony Koo } 10984034ad4SAnthony Koo #endif 11084034ad4SAnthony Koo 11184034ad4SAnthony Koo 11284034ad4SAnthony Koo 11384034ad4SAnthony Koo //============================================================================== 11484034ad4SAnthony Koo //</DMUB_TYPES>================================================================= 11584034ad4SAnthony Koo //============================================================================== 11684034ad4SAnthony Koo //< DMUB_META>================================================================== 11784034ad4SAnthony Koo //============================================================================== 11884034ad4SAnthony Koo #pragma pack(push, 1) 11984034ad4SAnthony Koo 12084034ad4SAnthony Koo /* Magic value for identifying dmub_fw_meta_info */ 12184034ad4SAnthony Koo #define DMUB_FW_META_MAGIC 0x444D5542 12284034ad4SAnthony Koo 12384034ad4SAnthony Koo /* Offset from the end of the file to the dmub_fw_meta_info */ 12484034ad4SAnthony Koo #define DMUB_FW_META_OFFSET 0x24 12584034ad4SAnthony Koo 12684034ad4SAnthony Koo /** 12784034ad4SAnthony Koo * struct dmub_fw_meta_info - metadata associated with fw binary 12884034ad4SAnthony Koo * 12984034ad4SAnthony Koo * NOTE: This should be considered a stable API. Fields should 13084034ad4SAnthony Koo * not be repurposed or reordered. New fields should be 13184034ad4SAnthony Koo * added instead to extend the structure. 13284034ad4SAnthony Koo * 13384034ad4SAnthony Koo * @magic_value: magic value identifying DMUB firmware meta info 13484034ad4SAnthony Koo * @fw_region_size: size of the firmware state region 13584034ad4SAnthony Koo * @trace_buffer_size: size of the tracebuffer region 13684034ad4SAnthony Koo * @fw_version: the firmware version information 137b2265774SAnthony Koo * @dal_fw: 1 if the firmware is DAL 13884034ad4SAnthony Koo */ 13984034ad4SAnthony Koo struct dmub_fw_meta_info { 14084034ad4SAnthony Koo uint32_t magic_value; 14184034ad4SAnthony Koo uint32_t fw_region_size; 14284034ad4SAnthony Koo uint32_t trace_buffer_size; 14384034ad4SAnthony Koo uint32_t fw_version; 144b2265774SAnthony Koo uint8_t dal_fw; 145b2265774SAnthony Koo uint8_t reserved[3]; 14684034ad4SAnthony Koo }; 14784034ad4SAnthony Koo 14884034ad4SAnthony Koo /* Ensure that the structure remains 64 bytes. */ 14984034ad4SAnthony Koo union dmub_fw_meta { 15084034ad4SAnthony Koo struct dmub_fw_meta_info info; 15184034ad4SAnthony Koo uint8_t reserved[64]; 15284034ad4SAnthony Koo }; 15384034ad4SAnthony Koo 15484034ad4SAnthony Koo #pragma pack(pop) 155788408b7SAnthony Koo 15684034ad4SAnthony Koo //============================================================================== 157788408b7SAnthony Koo //< DMUB_STATUS>================================================================ 158788408b7SAnthony Koo //============================================================================== 159788408b7SAnthony Koo 160788408b7SAnthony Koo /** 161788408b7SAnthony Koo * DMCUB scratch registers can be used to determine firmware status. 162788408b7SAnthony Koo * Current scratch register usage is as follows: 163788408b7SAnthony Koo * 164492dd8a8SAnthony Koo * SCRATCH0: FW Boot Status register 165492dd8a8SAnthony Koo * SCRATCH15: FW Boot Options register 166788408b7SAnthony Koo */ 167788408b7SAnthony Koo 168492dd8a8SAnthony Koo /* Register bit definition for SCRATCH0 */ 169492dd8a8SAnthony Koo union dmub_fw_boot_status { 170492dd8a8SAnthony Koo struct { 171492dd8a8SAnthony Koo uint32_t dal_fw : 1; 172492dd8a8SAnthony Koo uint32_t mailbox_rdy : 1; 173492dd8a8SAnthony Koo uint32_t optimized_init_done : 1; 1743b37260bSAnthony Koo uint32_t restore_required : 1; 175492dd8a8SAnthony Koo } bits; 176492dd8a8SAnthony Koo uint32_t all; 177492dd8a8SAnthony Koo }; 178492dd8a8SAnthony Koo 179492dd8a8SAnthony Koo enum dmub_fw_boot_status_bit { 180492dd8a8SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), 181492dd8a8SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), 182492dd8a8SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 1833b37260bSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), 184492dd8a8SAnthony Koo }; 185492dd8a8SAnthony Koo 186492dd8a8SAnthony Koo /* Register bit definition for SCRATCH15 */ 187492dd8a8SAnthony Koo union dmub_fw_boot_options { 188492dd8a8SAnthony Koo struct { 189492dd8a8SAnthony Koo uint32_t pemu_env : 1; 190492dd8a8SAnthony Koo uint32_t fpga_env : 1; 191492dd8a8SAnthony Koo uint32_t optimized_init : 1; 192*fd0f1d21SAnthony Koo uint32_t skip_phy_access : 1; 193*fd0f1d21SAnthony Koo uint32_t disable_clk_gate: 1; 194*fd0f1d21SAnthony Koo uint32_t reserved : 27; 195492dd8a8SAnthony Koo } bits; 196492dd8a8SAnthony Koo uint32_t all; 197492dd8a8SAnthony Koo }; 198492dd8a8SAnthony Koo 199492dd8a8SAnthony Koo enum dmub_fw_boot_options_bit { 200492dd8a8SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), 201492dd8a8SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), 202492dd8a8SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 203492dd8a8SAnthony Koo }; 204492dd8a8SAnthony Koo 205788408b7SAnthony Koo //============================================================================== 206788408b7SAnthony Koo //</DMUB_STATUS>================================================================ 20784034ad4SAnthony Koo //============================================================================== 20884034ad4SAnthony Koo //< DMUB_VBIOS>================================================================= 20984034ad4SAnthony Koo //============================================================================== 21084034ad4SAnthony Koo 21184034ad4SAnthony Koo /* 21284034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 21384034ad4SAnthony Koo * Do not reuse or modify IDs. 21484034ad4SAnthony Koo */ 21584034ad4SAnthony Koo 21684034ad4SAnthony Koo enum dmub_cmd_vbios_type { 21784034ad4SAnthony Koo DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 21884034ad4SAnthony Koo DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 21984034ad4SAnthony Koo DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 22084034ad4SAnthony Koo DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 2212ac685bfSAnthony Koo DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 22284034ad4SAnthony Koo }; 22384034ad4SAnthony Koo 22484034ad4SAnthony Koo //============================================================================== 22584034ad4SAnthony Koo //</DMUB_VBIOS>================================================================= 22684034ad4SAnthony Koo //============================================================================== 22784034ad4SAnthony Koo //< DMUB_GPINT>================================================================= 22884034ad4SAnthony Koo //============================================================================== 22984034ad4SAnthony Koo 23084034ad4SAnthony Koo /** 23184034ad4SAnthony Koo * The shifts and masks below may alternatively be used to format and read 23284034ad4SAnthony Koo * the command register bits. 23384034ad4SAnthony Koo */ 23484034ad4SAnthony Koo 23584034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 23684034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_SHIFT 0 23784034ad4SAnthony Koo 23884034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 23984034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 24084034ad4SAnthony Koo 24184034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_MASK 0xF 24284034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_SHIFT 28 24384034ad4SAnthony Koo 24484034ad4SAnthony Koo /** 24584034ad4SAnthony Koo * Command responses. 24684034ad4SAnthony Koo */ 24784034ad4SAnthony Koo 24884034ad4SAnthony Koo #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 24984034ad4SAnthony Koo 25084034ad4SAnthony Koo /** 25184034ad4SAnthony Koo * The register format for sending a command via the GPINT. 25284034ad4SAnthony Koo */ 25384034ad4SAnthony Koo union dmub_gpint_data_register { 25484034ad4SAnthony Koo struct { 25584034ad4SAnthony Koo uint32_t param : 16; 25684034ad4SAnthony Koo uint32_t command_code : 12; 25784034ad4SAnthony Koo uint32_t status : 4; 25884034ad4SAnthony Koo } bits; 25984034ad4SAnthony Koo uint32_t all; 26084034ad4SAnthony Koo }; 26184034ad4SAnthony Koo 26284034ad4SAnthony Koo /* 26384034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 26484034ad4SAnthony Koo * Do not reuse or modify IDs. 26584034ad4SAnthony Koo */ 26684034ad4SAnthony Koo 26784034ad4SAnthony Koo enum dmub_gpint_command { 26884034ad4SAnthony Koo DMUB_GPINT__INVALID_COMMAND = 0, 26984034ad4SAnthony Koo DMUB_GPINT__GET_FW_VERSION = 1, 27084034ad4SAnthony Koo DMUB_GPINT__STOP_FW = 2, 27184034ad4SAnthony Koo DMUB_GPINT__GET_PSR_STATE = 7, 27280eba958SAnthony Koo /** 27380eba958SAnthony Koo * DESC: Notifies DMCUB of the currently active streams. 27480eba958SAnthony Koo * ARGS: Stream mask, 1 bit per active stream index. 27580eba958SAnthony Koo */ 27680eba958SAnthony Koo DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 27784034ad4SAnthony Koo }; 27884034ad4SAnthony Koo 27984034ad4SAnthony Koo //============================================================================== 28084034ad4SAnthony Koo //</DMUB_GPINT>================================================================= 28184034ad4SAnthony Koo //============================================================================== 28284034ad4SAnthony Koo //< DMUB_CMD>=================================================================== 28384034ad4SAnthony Koo //============================================================================== 28484034ad4SAnthony Koo 2857c008829SNicholas Kazlauskas #define DMUB_RB_CMD_SIZE 64 2867c008829SNicholas Kazlauskas #define DMUB_RB_MAX_ENTRY 128 2877c008829SNicholas Kazlauskas #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 2887c008829SNicholas Kazlauskas #define REG_SET_MASK 0xFFFF 2897c008829SNicholas Kazlauskas 290d4bbcecbSNicholas Kazlauskas /* 291d4bbcecbSNicholas Kazlauskas * Command IDs should be treated as stable ABI. 292d4bbcecbSNicholas Kazlauskas * Do not reuse or modify IDs. 293d4bbcecbSNicholas Kazlauskas */ 2947c008829SNicholas Kazlauskas 295d4bbcecbSNicholas Kazlauskas enum dmub_cmd_type { 296d4bbcecbSNicholas Kazlauskas DMUB_CMD__NULL = 0, 297d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 298d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 299d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 300d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_REG_WAIT = 4, 301bae9c49bSYongqiang Sun DMUB_CMD__PLAT_54186_WA = 5, 302d4bbcecbSNicholas Kazlauskas DMUB_CMD__PSR = 64, 30352f2e83eSBhawanpreet Lakha DMUB_CMD__MALL = 65, 304e6ea8c34SWyatt Wood DMUB_CMD__ABM = 66, 305788408b7SAnthony Koo DMUB_CMD__HW_LOCK = 69, 306d9beecfcSAnthony Koo DMUB_CMD__DP_AUX_ACCESS = 70, 307d9beecfcSAnthony Koo DMUB_CMD__OUTBOX1_ENABLE = 71, 308d4bbcecbSNicholas Kazlauskas DMUB_CMD__VBIOS = 128, 3097c008829SNicholas Kazlauskas }; 3107c008829SNicholas Kazlauskas 3113b37260bSAnthony Koo enum dmub_out_cmd_type { 3123b37260bSAnthony Koo DMUB_OUT_CMD__NULL = 0, 313d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_AUX_REPLY = 1, 314d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 3153b37260bSAnthony Koo }; 3163b37260bSAnthony Koo 3177c008829SNicholas Kazlauskas #pragma pack(push, 1) 3187c008829SNicholas Kazlauskas 3197c008829SNicholas Kazlauskas struct dmub_cmd_header { 320d4bbcecbSNicholas Kazlauskas unsigned int type : 8; 321d4bbcecbSNicholas Kazlauskas unsigned int sub_type : 8; 322d4bbcecbSNicholas Kazlauskas unsigned int reserved0 : 8; 3237c008829SNicholas Kazlauskas unsigned int payload_bytes : 6; /* up to 60 bytes */ 324d4bbcecbSNicholas Kazlauskas unsigned int reserved1 : 2; 3257c008829SNicholas Kazlauskas }; 3267c008829SNicholas Kazlauskas 3277c008829SNicholas Kazlauskas /* 3287c008829SNicholas Kazlauskas * Read modify write 3297c008829SNicholas Kazlauskas * 3307c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 5 sets of read modify writes, 3317c008829SNicholas Kazlauskas * each take 3 dwords. 3327c008829SNicholas Kazlauskas * 3337c008829SNicholas Kazlauskas * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 3347c008829SNicholas Kazlauskas * 3357c008829SNicholas Kazlauskas * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 3367c008829SNicholas Kazlauskas * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 3377c008829SNicholas Kazlauskas */ 3387c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence { 3397c008829SNicholas Kazlauskas uint32_t addr; 3407c008829SNicholas Kazlauskas uint32_t modify_mask; 3417c008829SNicholas Kazlauskas uint32_t modify_value; 3427c008829SNicholas Kazlauskas }; 3437c008829SNicholas Kazlauskas 3447c008829SNicholas Kazlauskas #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 3457c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write { 3467c008829SNicholas Kazlauskas struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 3477c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 3487c008829SNicholas Kazlauskas }; 3497c008829SNicholas Kazlauskas 3507c008829SNicholas Kazlauskas /* 3517c008829SNicholas Kazlauskas * Update a register with specified masks and values sequeunce 3527c008829SNicholas Kazlauskas * 3537c008829SNicholas Kazlauskas * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 3547c008829SNicholas Kazlauskas * 3557c008829SNicholas Kazlauskas * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 3567c008829SNicholas Kazlauskas * 3577c008829SNicholas Kazlauskas * 3587c008829SNicholas Kazlauskas * USE CASE: 3597c008829SNicholas Kazlauskas * 1. auto-increment register where additional read would update pointer and produce wrong result 3607c008829SNicholas Kazlauskas * 2. toggle a bit without read in the middle 3617c008829SNicholas Kazlauskas */ 3627c008829SNicholas Kazlauskas 3637c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence { 3647c008829SNicholas Kazlauskas uint32_t modify_mask; // 0xffff'ffff to skip initial read 3657c008829SNicholas Kazlauskas uint32_t modify_value; 3667c008829SNicholas Kazlauskas }; 3677c008829SNicholas Kazlauskas 3687c008829SNicholas Kazlauskas #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 3697c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence { 3707c008829SNicholas Kazlauskas struct dmub_cmd_header header; 3717c008829SNicholas Kazlauskas uint32_t addr; 3727c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 3737c008829SNicholas Kazlauskas }; 3747c008829SNicholas Kazlauskas 3757c008829SNicholas Kazlauskas /* 3767c008829SNicholas Kazlauskas * Burst write 3777c008829SNicholas Kazlauskas * 3787c008829SNicholas Kazlauskas * support use case such as writing out LUTs. 3797c008829SNicholas Kazlauskas * 3807c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 14 values to write to given address 3817c008829SNicholas Kazlauskas * 3827c008829SNicholas Kazlauskas * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 3837c008829SNicholas Kazlauskas */ 3847c008829SNicholas Kazlauskas #define DMUB_BURST_WRITE_VALUES__MAX 14 3857c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write { 3867c008829SNicholas Kazlauskas struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 3877c008829SNicholas Kazlauskas uint32_t addr; 3887c008829SNicholas Kazlauskas uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 3897c008829SNicholas Kazlauskas }; 3907c008829SNicholas Kazlauskas 3917c008829SNicholas Kazlauskas 3927c008829SNicholas Kazlauskas struct dmub_rb_cmd_common { 3937c008829SNicholas Kazlauskas struct dmub_cmd_header header; 3947c008829SNicholas Kazlauskas uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 3957c008829SNicholas Kazlauskas }; 3967c008829SNicholas Kazlauskas 3977c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data { 3987c008829SNicholas Kazlauskas uint32_t addr; 3997c008829SNicholas Kazlauskas uint32_t mask; 4007c008829SNicholas Kazlauskas uint32_t condition_field_value; 4017c008829SNicholas Kazlauskas uint32_t time_out_us; 4027c008829SNicholas Kazlauskas }; 4037c008829SNicholas Kazlauskas 4047c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait { 4057c008829SNicholas Kazlauskas struct dmub_cmd_header header; 4067c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data reg_wait; 4077c008829SNicholas Kazlauskas }; 4087c008829SNicholas Kazlauskas 409bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa { 4108c019253SYongqiang Sun uint32_t DCSURF_SURFACE_CONTROL; 4118c019253SYongqiang Sun uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 4128c019253SYongqiang Sun uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 4138c019253SYongqiang Sun uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 4148c019253SYongqiang Sun uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 41522aa5614SYongqiang Sun struct { 41622aa5614SYongqiang Sun uint8_t hubp_inst : 4; 41722aa5614SYongqiang Sun uint8_t tmz_surface : 1; 41822aa5614SYongqiang Sun uint8_t immediate :1; 41922aa5614SYongqiang Sun uint8_t vmid : 4; 42022aa5614SYongqiang Sun uint8_t grph_stereo : 1; 42122aa5614SYongqiang Sun uint32_t reserved : 21; 42222aa5614SYongqiang Sun } flip_params; 423bae9c49bSYongqiang Sun uint32_t reserved[9]; 4248c019253SYongqiang Sun }; 4258c019253SYongqiang Sun 426bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa { 4278c019253SYongqiang Sun struct dmub_cmd_header header; 428bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa flip; 4298c019253SYongqiang Sun }; 4308c019253SYongqiang Sun 43152f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall { 43252f2e83eSBhawanpreet Lakha struct dmub_cmd_header header; 43352f2e83eSBhawanpreet Lakha union dmub_addr cursor_copy_src; 43452f2e83eSBhawanpreet Lakha union dmub_addr cursor_copy_dst; 43552f2e83eSBhawanpreet Lakha uint32_t tmr_delay; 43652f2e83eSBhawanpreet Lakha uint32_t tmr_scale; 43752f2e83eSBhawanpreet Lakha uint16_t cursor_width; 43852f2e83eSBhawanpreet Lakha uint16_t cursor_pitch; 43952f2e83eSBhawanpreet Lakha uint16_t cursor_height; 44052f2e83eSBhawanpreet Lakha uint8_t cursor_bpp; 44152f2e83eSBhawanpreet Lakha }; 44252f2e83eSBhawanpreet Lakha 4437c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data { 4447c008829SNicholas Kazlauskas union dig_encoder_control_parameters_v1_5 dig; 4457c008829SNicholas Kazlauskas }; 4467c008829SNicholas Kazlauskas 4477c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control { 4487c008829SNicholas Kazlauskas struct dmub_cmd_header header; 4497c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data encoder_control; 4507c008829SNicholas Kazlauskas }; 4517c008829SNicholas Kazlauskas 4527c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data { 4537c008829SNicholas Kazlauskas struct set_pixel_clock_parameter_v1_7 clk; 4547c008829SNicholas Kazlauskas }; 4557c008829SNicholas Kazlauskas 4567c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock { 4577c008829SNicholas Kazlauskas struct dmub_cmd_header header; 4587c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data pixel_clock; 4597c008829SNicholas Kazlauskas }; 4607c008829SNicholas Kazlauskas 4617c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data { 4627c008829SNicholas Kazlauskas struct enable_disp_power_gating_parameters_v2_1 pwr; 4637c008829SNicholas Kazlauskas }; 4647c008829SNicholas Kazlauskas 4657c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating { 4667c008829SNicholas Kazlauskas struct dmub_cmd_header header; 4677c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data power_gating; 4687c008829SNicholas Kazlauskas }; 4697c008829SNicholas Kazlauskas 4707c008829SNicholas Kazlauskas struct dmub_cmd_dig1_transmitter_control_data { 4717c008829SNicholas Kazlauskas struct dig_transmitter_control_parameters_v1_6 dig; 4727c008829SNicholas Kazlauskas }; 4737c008829SNicholas Kazlauskas 4747c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control { 4757c008829SNicholas Kazlauskas struct dmub_cmd_header header; 4767c008829SNicholas Kazlauskas struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 4777c008829SNicholas Kazlauskas }; 4787c008829SNicholas Kazlauskas 4797c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init { 4807c008829SNicholas Kazlauskas struct dmub_cmd_header header; 4817c008829SNicholas Kazlauskas uint8_t reserved[60]; 4827c008829SNicholas Kazlauskas }; 4837c008829SNicholas Kazlauskas 484d9beecfcSAnthony Koo enum dp_aux_request_action { 485d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 486d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ = 0x10, 487d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 488d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 489d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 490d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 491d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 492d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_READ = 0x90 493d9beecfcSAnthony Koo }; 494d9beecfcSAnthony Koo 495*fd0f1d21SAnthony Koo enum aux_return_code_type { 496*fd0f1d21SAnthony Koo AUX_RET_SUCCESS = 0, 497*fd0f1d21SAnthony Koo AUX_RET_ERROR_TIMEOUT, 498*fd0f1d21SAnthony Koo AUX_RET_ERROR_NO_DATA, 499*fd0f1d21SAnthony Koo AUX_RET_ERROR_INVALID_OPERATION, 500*fd0f1d21SAnthony Koo AUX_RET_ERROR_PROTOCOL_ERROR, 501*fd0f1d21SAnthony Koo }; 502*fd0f1d21SAnthony Koo 503d9beecfcSAnthony Koo /* DP AUX command */ 504d9beecfcSAnthony Koo struct aux_transaction_parameters { 505d9beecfcSAnthony Koo uint8_t is_i2c_over_aux; 506d9beecfcSAnthony Koo uint8_t action; 507d9beecfcSAnthony Koo uint8_t length; 508d9beecfcSAnthony Koo uint8_t pad; 509d9beecfcSAnthony Koo uint32_t address; 510d9beecfcSAnthony Koo uint8_t data[16]; 511d9beecfcSAnthony Koo }; 512d9beecfcSAnthony Koo 513d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data { 514d9beecfcSAnthony Koo uint32_t handle; 515d9beecfcSAnthony Koo uint8_t port_index; 516d9beecfcSAnthony Koo uint8_t sw_crc_enabled; 517d9beecfcSAnthony Koo uint16_t timeout; 518d9beecfcSAnthony Koo struct aux_transaction_parameters dpaux; 519d9beecfcSAnthony Koo }; 520d9beecfcSAnthony Koo 521d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access { 522d9beecfcSAnthony Koo struct dmub_cmd_header header; 523d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data aux_control; 524d9beecfcSAnthony Koo }; 525d9beecfcSAnthony Koo 526d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable { 527d9beecfcSAnthony Koo struct dmub_cmd_header header; 528d9beecfcSAnthony Koo uint32_t enable; 529d9beecfcSAnthony Koo }; 530d9beecfcSAnthony Koo 531d9beecfcSAnthony Koo /* DP AUX Reply command - OutBox Cmd */ 532d9beecfcSAnthony Koo struct aux_reply_data { 533d9beecfcSAnthony Koo uint8_t command; 534d9beecfcSAnthony Koo uint8_t length; 535d9beecfcSAnthony Koo uint8_t pad[2]; 536d9beecfcSAnthony Koo uint8_t data[16]; 537d9beecfcSAnthony Koo }; 538d9beecfcSAnthony Koo 539d9beecfcSAnthony Koo struct aux_reply_control_data { 540d9beecfcSAnthony Koo uint32_t handle; 541d9beecfcSAnthony Koo uint8_t phy_port_index; 542d9beecfcSAnthony Koo uint8_t result; 543d9beecfcSAnthony Koo uint16_t pad; 544d9beecfcSAnthony Koo }; 545d9beecfcSAnthony Koo 546d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply { 547d9beecfcSAnthony Koo struct dmub_cmd_header header; 548d9beecfcSAnthony Koo struct aux_reply_control_data control; 549d9beecfcSAnthony Koo struct aux_reply_data reply_data; 550d9beecfcSAnthony Koo }; 551d9beecfcSAnthony Koo 552*fd0f1d21SAnthony Koo /* DP HPD Notify command - OutBox Cmd */ 553*fd0f1d21SAnthony Koo enum dp_hpd_type { 554*fd0f1d21SAnthony Koo DP_HPD = 0, 555*fd0f1d21SAnthony Koo DP_IRQ 556*fd0f1d21SAnthony Koo }; 557*fd0f1d21SAnthony Koo 558*fd0f1d21SAnthony Koo enum dp_hpd_status { 559*fd0f1d21SAnthony Koo DP_HPD_UNPLUG = 0, 560*fd0f1d21SAnthony Koo DP_HPD_PLUG 561*fd0f1d21SAnthony Koo }; 562*fd0f1d21SAnthony Koo 563d9beecfcSAnthony Koo struct dp_hpd_data { 564d9beecfcSAnthony Koo uint8_t phy_port_index; 565d9beecfcSAnthony Koo uint8_t hpd_type; 566d9beecfcSAnthony Koo uint8_t hpd_status; 567d9beecfcSAnthony Koo uint8_t pad; 568d9beecfcSAnthony Koo }; 569d9beecfcSAnthony Koo 570d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify { 571d9beecfcSAnthony Koo struct dmub_cmd_header header; 572d9beecfcSAnthony Koo struct dp_hpd_data hpd_data; 573d9beecfcSAnthony Koo }; 574d9beecfcSAnthony Koo 57584034ad4SAnthony Koo /* 57684034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 57784034ad4SAnthony Koo * Do not reuse or modify IDs. 57884034ad4SAnthony Koo */ 57984034ad4SAnthony Koo 58084034ad4SAnthony Koo enum dmub_cmd_psr_type { 58184034ad4SAnthony Koo DMUB_CMD__PSR_SET_VERSION = 0, 58284034ad4SAnthony Koo DMUB_CMD__PSR_COPY_SETTINGS = 1, 58384034ad4SAnthony Koo DMUB_CMD__PSR_ENABLE = 2, 58484034ad4SAnthony Koo DMUB_CMD__PSR_DISABLE = 3, 58584034ad4SAnthony Koo DMUB_CMD__PSR_SET_LEVEL = 4, 58684034ad4SAnthony Koo }; 58784034ad4SAnthony Koo 58884034ad4SAnthony Koo enum psr_version { 58984034ad4SAnthony Koo PSR_VERSION_1 = 0, 59084034ad4SAnthony Koo PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 59184034ad4SAnthony Koo }; 59284034ad4SAnthony Koo 59352f2e83eSBhawanpreet Lakha enum dmub_cmd_mall_type { 59452f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_ALLOW = 0, 59552f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_DISALLOW = 1, 59652f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 59752f2e83eSBhawanpreet Lakha }; 59852f2e83eSBhawanpreet Lakha 5997c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data { 6007b8a6362SAnthony Koo union dmub_psr_debug_flags debug; 6014c1a1335SWyatt Wood uint16_t psr_level; 6024c1a1335SWyatt Wood uint8_t dpp_inst; 6034c1a1335SWyatt Wood uint8_t mpcc_inst; 6044c1a1335SWyatt Wood uint8_t opp_inst; 6054c1a1335SWyatt Wood uint8_t otg_inst; 6064c1a1335SWyatt Wood uint8_t digfe_inst; 6074c1a1335SWyatt Wood uint8_t digbe_inst; 6084c1a1335SWyatt Wood uint8_t dpphy_inst; 6094c1a1335SWyatt Wood uint8_t aux_inst; 6104c1a1335SWyatt Wood uint8_t smu_optimizations_en; 6114c1a1335SWyatt Wood uint8_t frame_delay; 6124c1a1335SWyatt Wood uint8_t frame_cap_ind; 6137b8a6362SAnthony Koo uint8_t pad[3]; 61478ead771SAnthony Koo uint16_t init_sdp_deadline; 61578ead771SAnthony Koo uint16_t pad2; 6167c008829SNicholas Kazlauskas }; 6177c008829SNicholas Kazlauskas 6187c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings { 6197c008829SNicholas Kazlauskas struct dmub_cmd_header header; 6207c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 6217c008829SNicholas Kazlauskas }; 6227c008829SNicholas Kazlauskas 6237c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data { 6247c008829SNicholas Kazlauskas uint16_t psr_level; 6257b8a6362SAnthony Koo uint8_t pad[2]; 6267c008829SNicholas Kazlauskas }; 6277c008829SNicholas Kazlauskas 6287c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level { 6297c008829SNicholas Kazlauskas struct dmub_cmd_header header; 6307c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data psr_set_level_data; 6317c008829SNicholas Kazlauskas }; 6327c008829SNicholas Kazlauskas 6337c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_enable { 6347c008829SNicholas Kazlauskas struct dmub_cmd_header header; 6357c008829SNicholas Kazlauskas }; 6367c008829SNicholas Kazlauskas 637d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data { 638ec256f44SWyatt Wood enum psr_version version; // PSR version 1 or 2 6397c008829SNicholas Kazlauskas }; 6407c008829SNicholas Kazlauskas 641d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version { 6427c008829SNicholas Kazlauskas struct dmub_cmd_header header; 643d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data psr_set_version_data; 6447c008829SNicholas Kazlauskas }; 6457c008829SNicholas Kazlauskas 646788408b7SAnthony Koo union dmub_hw_lock_flags { 647788408b7SAnthony Koo struct { 648788408b7SAnthony Koo uint8_t lock_pipe : 1; 649788408b7SAnthony Koo uint8_t lock_cursor : 1; 650788408b7SAnthony Koo uint8_t lock_dig : 1; 651788408b7SAnthony Koo uint8_t triple_buffer_lock : 1; 652788408b7SAnthony Koo } bits; 653788408b7SAnthony Koo 654788408b7SAnthony Koo uint8_t u8All; 655788408b7SAnthony Koo }; 656788408b7SAnthony Koo 657788408b7SAnthony Koo struct dmub_hw_lock_inst_flags { 658788408b7SAnthony Koo uint8_t otg_inst; 659788408b7SAnthony Koo uint8_t opp_inst; 660788408b7SAnthony Koo uint8_t dig_inst; 661788408b7SAnthony Koo uint8_t pad; 662788408b7SAnthony Koo }; 663788408b7SAnthony Koo 664788408b7SAnthony Koo enum hw_lock_client { 665788408b7SAnthony Koo HW_LOCK_CLIENT_DRIVER = 0, 666788408b7SAnthony Koo HW_LOCK_CLIENT_FW, 667788408b7SAnthony Koo HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 668788408b7SAnthony Koo }; 669788408b7SAnthony Koo 670788408b7SAnthony Koo struct dmub_cmd_lock_hw_data { 671788408b7SAnthony Koo enum hw_lock_client client; 672788408b7SAnthony Koo struct dmub_hw_lock_inst_flags inst_flags; 673788408b7SAnthony Koo union dmub_hw_lock_flags hw_locks; 674788408b7SAnthony Koo uint8_t lock; 675788408b7SAnthony Koo uint8_t should_release; 676788408b7SAnthony Koo uint8_t pad; 677788408b7SAnthony Koo }; 678788408b7SAnthony Koo 679788408b7SAnthony Koo struct dmub_rb_cmd_lock_hw { 680788408b7SAnthony Koo struct dmub_cmd_header header; 681788408b7SAnthony Koo struct dmub_cmd_lock_hw_data lock_hw_data; 682788408b7SAnthony Koo }; 683788408b7SAnthony Koo 68484034ad4SAnthony Koo enum dmub_cmd_abm_type { 68584034ad4SAnthony Koo DMUB_CMD__ABM_INIT_CONFIG = 0, 68684034ad4SAnthony Koo DMUB_CMD__ABM_SET_PIPE = 1, 68784034ad4SAnthony Koo DMUB_CMD__ABM_SET_BACKLIGHT = 2, 68884034ad4SAnthony Koo DMUB_CMD__ABM_SET_LEVEL = 3, 68984034ad4SAnthony Koo DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 69084034ad4SAnthony Koo DMUB_CMD__ABM_SET_PWM_FRAC = 5, 69184034ad4SAnthony Koo }; 69284034ad4SAnthony Koo 69384034ad4SAnthony Koo #define NUM_AMBI_LEVEL 5 69484034ad4SAnthony Koo #define NUM_AGGR_LEVEL 4 69584034ad4SAnthony Koo #define NUM_POWER_FN_SEGS 8 69684034ad4SAnthony Koo #define NUM_BL_CURVE_SEGS 16 69784034ad4SAnthony Koo 69884034ad4SAnthony Koo /* 69984034ad4SAnthony Koo * Parameters for ABM2.4 algorithm. 70084034ad4SAnthony Koo * Padded explicitly to 32-bit boundary. 70184034ad4SAnthony Koo */ 70284034ad4SAnthony Koo struct abm_config_table { 70384034ad4SAnthony Koo /* Parameters for crgb conversion */ 70484034ad4SAnthony Koo uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 70584034ad4SAnthony Koo uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 15B 70684034ad4SAnthony Koo uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 31B 70784034ad4SAnthony Koo 70884034ad4SAnthony Koo /* Parameters for custom curve */ 70984034ad4SAnthony Koo uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 47B 71084034ad4SAnthony Koo uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 79B 71184034ad4SAnthony Koo 71284034ad4SAnthony Koo uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 111B 71384034ad4SAnthony Koo uint16_t min_abm_backlight; // 121B 71484034ad4SAnthony Koo 71584034ad4SAnthony Koo uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 123B 71684034ad4SAnthony Koo uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 143B 71784034ad4SAnthony Koo uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 163B 71884034ad4SAnthony Koo uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 183B 71984034ad4SAnthony Koo uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 203B 72084034ad4SAnthony Koo uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 207B 72184034ad4SAnthony Koo uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 211B 72284034ad4SAnthony Koo uint8_t min_knee[NUM_AGGR_LEVEL]; // 215B 72384034ad4SAnthony Koo uint8_t max_knee[NUM_AGGR_LEVEL]; // 219B 72484034ad4SAnthony Koo uint8_t iir_curve[NUM_AMBI_LEVEL]; // 223B 72584034ad4SAnthony Koo uint8_t pad3[3]; // 228B 72684034ad4SAnthony Koo }; 72784034ad4SAnthony Koo 728e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data { 7297b8a6362SAnthony Koo uint8_t otg_inst; 7307b8a6362SAnthony Koo uint8_t panel_inst; 7317b8a6362SAnthony Koo uint8_t set_pipe_option; 7327b8a6362SAnthony Koo uint8_t ramping_boundary; // TODO: Remove this 733e6ea8c34SWyatt Wood }; 734e6ea8c34SWyatt Wood 735e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe { 736e6ea8c34SWyatt Wood struct dmub_cmd_header header; 737e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 738e6ea8c34SWyatt Wood }; 739e6ea8c34SWyatt Wood 740e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data { 741e6ea8c34SWyatt Wood uint32_t frame_ramp; 742474ac4a8SYongqiang Sun uint32_t backlight_user_level; 743e6ea8c34SWyatt Wood }; 744e6ea8c34SWyatt Wood 745e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight { 746e6ea8c34SWyatt Wood struct dmub_cmd_header header; 747e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 748e6ea8c34SWyatt Wood }; 749e6ea8c34SWyatt Wood 750e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data { 751e6ea8c34SWyatt Wood uint32_t level; 752e6ea8c34SWyatt Wood }; 753e6ea8c34SWyatt Wood 754e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level { 755e6ea8c34SWyatt Wood struct dmub_cmd_header header; 756e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data abm_set_level_data; 757e6ea8c34SWyatt Wood }; 758e6ea8c34SWyatt Wood 759e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data { 760e6ea8c34SWyatt Wood uint32_t ambient_lux; 761e6ea8c34SWyatt Wood }; 762e6ea8c34SWyatt Wood 763e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level { 764e6ea8c34SWyatt Wood struct dmub_cmd_header header; 765e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 766e6ea8c34SWyatt Wood }; 767e6ea8c34SWyatt Wood 768e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data { 769e6ea8c34SWyatt Wood uint32_t fractional_pwm; 770e6ea8c34SWyatt Wood }; 771e6ea8c34SWyatt Wood 772e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac { 773e6ea8c34SWyatt Wood struct dmub_cmd_header header; 774e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 775e6ea8c34SWyatt Wood }; 776e6ea8c34SWyatt Wood 77716012806SWyatt Wood struct dmub_cmd_abm_init_config_data { 77816012806SWyatt Wood union dmub_addr src; 77916012806SWyatt Wood uint16_t bytes; 78016012806SWyatt Wood }; 78116012806SWyatt Wood 78216012806SWyatt Wood struct dmub_rb_cmd_abm_init_config { 78316012806SWyatt Wood struct dmub_cmd_header header; 78416012806SWyatt Wood struct dmub_cmd_abm_init_config_data abm_init_config_data; 78516012806SWyatt Wood }; 78616012806SWyatt Wood 7877c008829SNicholas Kazlauskas union dmub_rb_cmd { 788dc6e2448SWyatt Wood struct dmub_rb_cmd_lock_hw lock_hw; 7897c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write read_modify_write; 7907c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 7917c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write burst_write; 7927c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait reg_wait; 7937c008829SNicholas Kazlauskas struct dmub_rb_cmd_common cmd_common; 7947c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 7957c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 7967c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 7977c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init dpphy_init; 7987c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 799d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version psr_set_version; 8007c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 801d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_enable psr_enable; 8027c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level psr_set_level; 803bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 80452f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall mall; 805e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 806e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 807e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level abm_set_level; 808e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 809e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 81016012806SWyatt Wood struct dmub_rb_cmd_abm_init_config abm_init_config; 811d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access dp_aux_access; 812d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable outbox1_enable; 8137c008829SNicholas Kazlauskas }; 8147c008829SNicholas Kazlauskas 815d9beecfcSAnthony Koo union dmub_rb_out_cmd { 816d9beecfcSAnthony Koo struct dmub_rb_cmd_common cmd_common; 817d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 818d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 819d9beecfcSAnthony Koo }; 8207c008829SNicholas Kazlauskas #pragma pack(pop) 8217c008829SNicholas Kazlauskas 82284034ad4SAnthony Koo 82384034ad4SAnthony Koo //============================================================================== 82484034ad4SAnthony Koo //</DMUB_CMD>=================================================================== 82584034ad4SAnthony Koo //============================================================================== 82684034ad4SAnthony Koo //< DMUB_RB>==================================================================== 82784034ad4SAnthony Koo //============================================================================== 82884034ad4SAnthony Koo 82984034ad4SAnthony Koo #if defined(__cplusplus) 83084034ad4SAnthony Koo extern "C" { 83184034ad4SAnthony Koo #endif 83284034ad4SAnthony Koo 83384034ad4SAnthony Koo struct dmub_rb_init_params { 83484034ad4SAnthony Koo void *ctx; 83584034ad4SAnthony Koo void *base_address; 83684034ad4SAnthony Koo uint32_t capacity; 83784034ad4SAnthony Koo uint32_t read_ptr; 83884034ad4SAnthony Koo uint32_t write_ptr; 83984034ad4SAnthony Koo }; 84084034ad4SAnthony Koo 84184034ad4SAnthony Koo struct dmub_rb { 84284034ad4SAnthony Koo void *base_address; 84384034ad4SAnthony Koo uint32_t data_count; 84484034ad4SAnthony Koo uint32_t rptr; 84584034ad4SAnthony Koo uint32_t wrpt; 84684034ad4SAnthony Koo uint32_t capacity; 84784034ad4SAnthony Koo 84884034ad4SAnthony Koo void *ctx; 84984034ad4SAnthony Koo void *dmub; 85084034ad4SAnthony Koo }; 85184034ad4SAnthony Koo 85284034ad4SAnthony Koo 85384034ad4SAnthony Koo static inline bool dmub_rb_empty(struct dmub_rb *rb) 85484034ad4SAnthony Koo { 85584034ad4SAnthony Koo return (rb->wrpt == rb->rptr); 85684034ad4SAnthony Koo } 85784034ad4SAnthony Koo 85884034ad4SAnthony Koo static inline bool dmub_rb_full(struct dmub_rb *rb) 85984034ad4SAnthony Koo { 86084034ad4SAnthony Koo uint32_t data_count; 86184034ad4SAnthony Koo 86284034ad4SAnthony Koo if (rb->wrpt >= rb->rptr) 86384034ad4SAnthony Koo data_count = rb->wrpt - rb->rptr; 86484034ad4SAnthony Koo else 86584034ad4SAnthony Koo data_count = rb->capacity - (rb->rptr - rb->wrpt); 86684034ad4SAnthony Koo 86784034ad4SAnthony Koo return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 86884034ad4SAnthony Koo } 86984034ad4SAnthony Koo 87084034ad4SAnthony Koo static inline bool dmub_rb_push_front(struct dmub_rb *rb, 87184034ad4SAnthony Koo const union dmub_rb_cmd *cmd) 87284034ad4SAnthony Koo { 87384034ad4SAnthony Koo uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 87484034ad4SAnthony Koo const uint64_t *src = (const uint64_t *)cmd; 87584034ad4SAnthony Koo int i; 87684034ad4SAnthony Koo 87784034ad4SAnthony Koo if (dmub_rb_full(rb)) 87884034ad4SAnthony Koo return false; 87984034ad4SAnthony Koo 88084034ad4SAnthony Koo // copying data 88184034ad4SAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 88284034ad4SAnthony Koo *dst++ = *src++; 88384034ad4SAnthony Koo 88484034ad4SAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 88584034ad4SAnthony Koo 88684034ad4SAnthony Koo if (rb->wrpt >= rb->capacity) 88784034ad4SAnthony Koo rb->wrpt %= rb->capacity; 88884034ad4SAnthony Koo 88984034ad4SAnthony Koo return true; 89084034ad4SAnthony Koo } 89184034ad4SAnthony Koo 892d9beecfcSAnthony Koo static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 893d9beecfcSAnthony Koo const union dmub_rb_out_cmd *cmd) 894d9beecfcSAnthony Koo { 895d9beecfcSAnthony Koo uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 896d9beecfcSAnthony Koo const uint8_t *src = (uint8_t *)cmd; 897d9beecfcSAnthony Koo 898d9beecfcSAnthony Koo if (dmub_rb_full(rb)) 899d9beecfcSAnthony Koo return false; 900d9beecfcSAnthony Koo 901d9beecfcSAnthony Koo dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 902d9beecfcSAnthony Koo 903d9beecfcSAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 904d9beecfcSAnthony Koo 905d9beecfcSAnthony Koo if (rb->wrpt >= rb->capacity) 906d9beecfcSAnthony Koo rb->wrpt %= rb->capacity; 907d9beecfcSAnthony Koo 908d9beecfcSAnthony Koo return true; 909d9beecfcSAnthony Koo } 910d9beecfcSAnthony Koo 91184034ad4SAnthony Koo static inline bool dmub_rb_front(struct dmub_rb *rb, 91284034ad4SAnthony Koo union dmub_rb_cmd *cmd) 91384034ad4SAnthony Koo { 91484034ad4SAnthony Koo uint8_t *rd_ptr = (uint8_t *)rb->base_address + rb->rptr; 91584034ad4SAnthony Koo 91684034ad4SAnthony Koo if (dmub_rb_empty(rb)) 91784034ad4SAnthony Koo return false; 91884034ad4SAnthony Koo 91984034ad4SAnthony Koo dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 92084034ad4SAnthony Koo 92184034ad4SAnthony Koo return true; 92284034ad4SAnthony Koo } 92384034ad4SAnthony Koo 924d9beecfcSAnthony Koo static inline bool dmub_rb_out_front(struct dmub_rb *rb, 925d9beecfcSAnthony Koo union dmub_rb_out_cmd *cmd) 926d9beecfcSAnthony Koo { 927d9beecfcSAnthony Koo const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 928d9beecfcSAnthony Koo uint64_t *dst = (uint64_t *)cmd; 929d9beecfcSAnthony Koo int i; 930d9beecfcSAnthony Koo 931d9beecfcSAnthony Koo if (dmub_rb_empty(rb)) 932d9beecfcSAnthony Koo return false; 933d9beecfcSAnthony Koo 934d9beecfcSAnthony Koo // copying data 935d9beecfcSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 936d9beecfcSAnthony Koo *dst++ = *src++; 937d9beecfcSAnthony Koo 938d9beecfcSAnthony Koo return true; 939d9beecfcSAnthony Koo } 940d9beecfcSAnthony Koo 94184034ad4SAnthony Koo static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 94284034ad4SAnthony Koo { 94384034ad4SAnthony Koo if (dmub_rb_empty(rb)) 94484034ad4SAnthony Koo return false; 94584034ad4SAnthony Koo 94684034ad4SAnthony Koo rb->rptr += DMUB_RB_CMD_SIZE; 94784034ad4SAnthony Koo 94884034ad4SAnthony Koo if (rb->rptr >= rb->capacity) 94984034ad4SAnthony Koo rb->rptr %= rb->capacity; 95084034ad4SAnthony Koo 95184034ad4SAnthony Koo return true; 95284034ad4SAnthony Koo } 95384034ad4SAnthony Koo 95484034ad4SAnthony Koo static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 95584034ad4SAnthony Koo { 95684034ad4SAnthony Koo uint32_t rptr = rb->rptr; 95784034ad4SAnthony Koo uint32_t wptr = rb->wrpt; 95884034ad4SAnthony Koo 95984034ad4SAnthony Koo while (rptr != wptr) { 96084034ad4SAnthony Koo uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 96184034ad4SAnthony Koo int i; 96284034ad4SAnthony Koo 96384034ad4SAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 9648906e5bcSYe Bin *data++; 96584034ad4SAnthony Koo 96684034ad4SAnthony Koo rptr += DMUB_RB_CMD_SIZE; 96784034ad4SAnthony Koo if (rptr >= rb->capacity) 96884034ad4SAnthony Koo rptr %= rb->capacity; 96984034ad4SAnthony Koo } 97084034ad4SAnthony Koo } 97184034ad4SAnthony Koo 97284034ad4SAnthony Koo static inline void dmub_rb_init(struct dmub_rb *rb, 97384034ad4SAnthony Koo struct dmub_rb_init_params *init_params) 97484034ad4SAnthony Koo { 97584034ad4SAnthony Koo rb->base_address = init_params->base_address; 97684034ad4SAnthony Koo rb->capacity = init_params->capacity; 97784034ad4SAnthony Koo rb->rptr = init_params->read_ptr; 97884034ad4SAnthony Koo rb->wrpt = init_params->write_ptr; 97984034ad4SAnthony Koo } 98084034ad4SAnthony Koo 98184034ad4SAnthony Koo #if defined(__cplusplus) 98284034ad4SAnthony Koo } 98384034ad4SAnthony Koo #endif 98484034ad4SAnthony Koo 98584034ad4SAnthony Koo //============================================================================== 98684034ad4SAnthony Koo //</DMUB_RB>==================================================================== 98784034ad4SAnthony Koo //============================================================================== 98884034ad4SAnthony Koo 9897c008829SNicholas Kazlauskas #endif /* _DMUB_CMD_H_ */ 990