17c008829SNicholas Kazlauskas /* 27c008829SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 37c008829SNicholas Kazlauskas * 47c008829SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 57c008829SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 67c008829SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 77c008829SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87c008829SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 97c008829SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 107c008829SNicholas Kazlauskas * 117c008829SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 127c008829SNicholas Kazlauskas * all copies or substantial portions of the Software. 137c008829SNicholas Kazlauskas * 147c008829SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157c008829SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167c008829SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177c008829SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187c008829SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197c008829SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207c008829SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 217c008829SNicholas Kazlauskas * 227c008829SNicholas Kazlauskas * Authors: AMD 237c008829SNicholas Kazlauskas * 247c008829SNicholas Kazlauskas */ 257c008829SNicholas Kazlauskas 265624c345SAnthony Koo #ifndef DMUB_CMD_H 275624c345SAnthony Koo #define DMUB_CMD_H 287c008829SNicholas Kazlauskas 298b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 308b19a4e3SAnthony Koo #include "dmub_fw_types.h" 318b19a4e3SAnthony Koo #include "include_legacy/atomfirmware.h" 328b19a4e3SAnthony Koo 338b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) 348b19a4e3SAnthony Koo #include <string.h> 358b19a4e3SAnthony Koo #endif 368b19a4e3SAnthony Koo #else 378b19a4e3SAnthony Koo 3884034ad4SAnthony Koo #include <asm/byteorder.h> 3984034ad4SAnthony Koo #include <linux/types.h> 4084034ad4SAnthony Koo #include <linux/string.h> 4184034ad4SAnthony Koo #include <linux/delay.h> 4284034ad4SAnthony Koo 437c008829SNicholas Kazlauskas #include "atomfirmware.h" 4422aa5614SYongqiang Sun 458b19a4e3SAnthony Koo #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 468b19a4e3SAnthony Koo 4784034ad4SAnthony Koo //<DMUB_TYPES>================================================================== 4884034ad4SAnthony Koo /* Basic type definitions. */ 4984034ad4SAnthony Koo 508b19a4e3SAnthony Koo #define __forceinline inline 518b19a4e3SAnthony Koo 521a595f28SAnthony Koo /** 531a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled gradually 541a595f28SAnthony Koo * by slowly reversing all backlight programming and pixel compensation. 551a595f28SAnthony Koo */ 5684034ad4SAnthony Koo #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 571a595f28SAnthony Koo 581a595f28SAnthony Koo /** 591a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 601a595f28SAnthony Koo * and undo all backlight programming and pixel compensation. 611a595f28SAnthony Koo */ 6284034ad4SAnthony Koo #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 631a595f28SAnthony Koo 641a595f28SAnthony Koo /** 651a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 661a595f28SAnthony Koo * and keep the current backlight programming and pixel compensation. 671a595f28SAnthony Koo */ 68d9beecfcSAnthony Koo #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 691a595f28SAnthony Koo 701a595f28SAnthony Koo /** 711a595f28SAnthony Koo * Flag from driver to set the current ABM pipe index or ABM operating level. 721a595f28SAnthony Koo */ 7384034ad4SAnthony Koo #define SET_ABM_PIPE_NORMAL 1 7484034ad4SAnthony Koo 751a595f28SAnthony Koo /** 761a595f28SAnthony Koo * Number of ambient light levels in ABM algorithm. 771a595f28SAnthony Koo */ 781a595f28SAnthony Koo #define NUM_AMBI_LEVEL 5 791a595f28SAnthony Koo 801a595f28SAnthony Koo /** 811a595f28SAnthony Koo * Number of operating/aggression levels in ABM algorithm. 821a595f28SAnthony Koo */ 831a595f28SAnthony Koo #define NUM_AGGR_LEVEL 4 841a595f28SAnthony Koo 851a595f28SAnthony Koo /** 861a595f28SAnthony Koo * Number of segments in the gamma curve. 871a595f28SAnthony Koo */ 881a595f28SAnthony Koo #define NUM_POWER_FN_SEGS 8 891a595f28SAnthony Koo 901a595f28SAnthony Koo /** 911a595f28SAnthony Koo * Number of segments in the backlight curve. 921a595f28SAnthony Koo */ 931a595f28SAnthony Koo #define NUM_BL_CURVE_SEGS 16 941a595f28SAnthony Koo 9585f4bc0cSAlvin Lee /* Maximum number of SubVP streams */ 9685f4bc0cSAlvin Lee #define DMUB_MAX_SUBVP_STREAMS 2 9785f4bc0cSAlvin Lee 9884034ad4SAnthony Koo /* Maximum number of streams on any ASIC. */ 9984034ad4SAnthony Koo #define DMUB_MAX_STREAMS 6 10084034ad4SAnthony Koo 10184034ad4SAnthony Koo /* Maximum number of planes on any ASIC. */ 10284034ad4SAnthony Koo #define DMUB_MAX_PLANES 6 10384034ad4SAnthony Koo 10470732504SYongqiang Sun /* Trace buffer offset for entry */ 10570732504SYongqiang Sun #define TRACE_BUFFER_ENTRY_OFFSET 16 10670732504SYongqiang Sun 107592a6318SAnthony Koo /** 10883eb5385SDavid Zhang * Maximum number of dirty rects supported by FW. 10983eb5385SDavid Zhang */ 11083eb5385SDavid Zhang #define DMUB_MAX_DIRTY_RECTS 3 11183eb5385SDavid Zhang 11283eb5385SDavid Zhang /** 113f56c837aSMikita Lipski * 114f56c837aSMikita Lipski * PSR control version legacy 115f56c837aSMikita Lipski */ 116f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117f56c837aSMikita Lipski /** 118f56c837aSMikita Lipski * PSR control version with multi edp support 119f56c837aSMikita Lipski */ 120f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121f56c837aSMikita Lipski 122f56c837aSMikita Lipski 123f56c837aSMikita Lipski /** 12463de4f04SJake Wang * ABM control version legacy 125e922057bSJake Wang */ 12663de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127e922057bSJake Wang 128e922057bSJake Wang /** 12963de4f04SJake Wang * ABM control version with multi edp support 130e922057bSJake Wang */ 13163de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132e922057bSJake Wang 133e922057bSJake Wang /** 134592a6318SAnthony Koo * Physical framebuffer address location, 64-bit. 135592a6318SAnthony Koo */ 13684034ad4SAnthony Koo #ifndef PHYSICAL_ADDRESS_LOC 13784034ad4SAnthony Koo #define PHYSICAL_ADDRESS_LOC union large_integer 13884034ad4SAnthony Koo #endif 13984034ad4SAnthony Koo 140592a6318SAnthony Koo /** 141592a6318SAnthony Koo * OS/FW agnostic memcpy 142592a6318SAnthony Koo */ 14384034ad4SAnthony Koo #ifndef dmub_memcpy 14484034ad4SAnthony Koo #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 14584034ad4SAnthony Koo #endif 14684034ad4SAnthony Koo 147592a6318SAnthony Koo /** 148592a6318SAnthony Koo * OS/FW agnostic memset 149592a6318SAnthony Koo */ 15084034ad4SAnthony Koo #ifndef dmub_memset 15184034ad4SAnthony Koo #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 15284034ad4SAnthony Koo #endif 15384034ad4SAnthony Koo 154d9beecfcSAnthony Koo #if defined(__cplusplus) 155d9beecfcSAnthony Koo extern "C" { 156d9beecfcSAnthony Koo #endif 157d9beecfcSAnthony Koo 158592a6318SAnthony Koo /** 159592a6318SAnthony Koo * OS/FW agnostic udelay 160592a6318SAnthony Koo */ 16184034ad4SAnthony Koo #ifndef dmub_udelay 16284034ad4SAnthony Koo #define dmub_udelay(microseconds) udelay(microseconds) 16384034ad4SAnthony Koo #endif 16484034ad4SAnthony Koo 165592a6318SAnthony Koo /** 166592a6318SAnthony Koo * union dmub_addr - DMUB physical/virtual 64-bit address. 167592a6318SAnthony Koo */ 16884034ad4SAnthony Koo union dmub_addr { 16984034ad4SAnthony Koo struct { 170592a6318SAnthony Koo uint32_t low_part; /**< Lower 32 bits */ 171592a6318SAnthony Koo uint32_t high_part; /**< Upper 32 bits */ 172592a6318SAnthony Koo } u; /*<< Low/high bit access */ 173592a6318SAnthony Koo uint64_t quad_part; /*<< 64 bit address */ 17484034ad4SAnthony Koo }; 17584034ad4SAnthony Koo 1761a595f28SAnthony Koo /** 17783eb5385SDavid Zhang * Dirty rect definition. 17883eb5385SDavid Zhang */ 17983eb5385SDavid Zhang struct dmub_rect { 18083eb5385SDavid Zhang /** 18183eb5385SDavid Zhang * Dirty rect x offset. 18283eb5385SDavid Zhang */ 18383eb5385SDavid Zhang uint32_t x; 18483eb5385SDavid Zhang 18583eb5385SDavid Zhang /** 18683eb5385SDavid Zhang * Dirty rect y offset. 18783eb5385SDavid Zhang */ 18883eb5385SDavid Zhang uint32_t y; 18983eb5385SDavid Zhang 19083eb5385SDavid Zhang /** 19183eb5385SDavid Zhang * Dirty rect width. 19283eb5385SDavid Zhang */ 19383eb5385SDavid Zhang uint32_t width; 19483eb5385SDavid Zhang 19583eb5385SDavid Zhang /** 19683eb5385SDavid Zhang * Dirty rect height. 19783eb5385SDavid Zhang */ 19883eb5385SDavid Zhang uint32_t height; 19983eb5385SDavid Zhang }; 20083eb5385SDavid Zhang 20183eb5385SDavid Zhang /** 2021a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 2031a595f28SAnthony Koo */ 20484034ad4SAnthony Koo union dmub_psr_debug_flags { 2051a595f28SAnthony Koo /** 2061a595f28SAnthony Koo * Debug flags. 2071a595f28SAnthony Koo */ 20884034ad4SAnthony Koo struct { 2091a595f28SAnthony Koo /** 2101a595f28SAnthony Koo * Enable visual confirm in FW. 2111a595f28SAnthony Koo */ 212447f3d0fSAnthony Koo uint32_t visual_confirm : 1; 21383eb5385SDavid Zhang 21483eb5385SDavid Zhang /** 21583eb5385SDavid Zhang * Force all selective updates to bw full frame updates. 21683eb5385SDavid Zhang */ 21783eb5385SDavid Zhang uint32_t force_full_frame_update : 1; 21883eb5385SDavid Zhang 2191a595f28SAnthony Koo /** 2201a595f28SAnthony Koo * Use HW Lock Mgr object to do HW locking in FW. 2211a595f28SAnthony Koo */ 222447f3d0fSAnthony Koo uint32_t use_hw_lock_mgr : 1; 2231a595f28SAnthony Koo 2241a595f28SAnthony Koo /** 225548f2125SRobin Chen * Use TPS3 signal when restore main link. 2261a595f28SAnthony Koo */ 227548f2125SRobin Chen uint32_t force_wakeup_by_tps3 : 1; 228cf472dbdSAnthony Koo 229cf472dbdSAnthony Koo /** 230cf472dbdSAnthony Koo * Back to back flip, therefore cannot power down PHY 231cf472dbdSAnthony Koo */ 232cf472dbdSAnthony Koo uint32_t back_to_back_flip : 1; 233cf472dbdSAnthony Koo 23484034ad4SAnthony Koo } bitfields; 23584034ad4SAnthony Koo 2361a595f28SAnthony Koo /** 2371a595f28SAnthony Koo * Union for debug flags. 2381a595f28SAnthony Koo */ 239447f3d0fSAnthony Koo uint32_t u32All; 24084034ad4SAnthony Koo }; 24184034ad4SAnthony Koo 2421a595f28SAnthony Koo /** 2430991f44cSAnthony Koo * DMUB visual confirm color 2441a595f28SAnthony Koo */ 24534ba432cSAnthony Koo struct dmub_feature_caps { 2461a595f28SAnthony Koo /** 2471a595f28SAnthony Koo * Max PSR version supported by FW. 2481a595f28SAnthony Koo */ 24934ba432cSAnthony Koo uint8_t psr; 25000fa7f03SRodrigo Siqueira uint8_t fw_assisted_mclk_switch; 25100fa7f03SRodrigo Siqueira uint8_t reserved[6]; 25234ba432cSAnthony Koo }; 25334ba432cSAnthony Koo 254b09c1fffSLeo (Hanghong) Ma struct dmub_visual_confirm_color { 255b09c1fffSLeo (Hanghong) Ma /** 256b09c1fffSLeo (Hanghong) Ma * Maximum 10 bits color value 257b09c1fffSLeo (Hanghong) Ma */ 258b09c1fffSLeo (Hanghong) Ma uint16_t color_r_cr; 259b09c1fffSLeo (Hanghong) Ma uint16_t color_g_y; 260b09c1fffSLeo (Hanghong) Ma uint16_t color_b_cb; 261b09c1fffSLeo (Hanghong) Ma uint16_t panel_inst; 262b09c1fffSLeo (Hanghong) Ma }; 263b09c1fffSLeo (Hanghong) Ma 26484034ad4SAnthony Koo #if defined(__cplusplus) 26584034ad4SAnthony Koo } 26684034ad4SAnthony Koo #endif 26784034ad4SAnthony Koo 26884034ad4SAnthony Koo //============================================================================== 26984034ad4SAnthony Koo //</DMUB_TYPES>================================================================= 27084034ad4SAnthony Koo //============================================================================== 27184034ad4SAnthony Koo //< DMUB_META>================================================================== 27284034ad4SAnthony Koo //============================================================================== 27384034ad4SAnthony Koo #pragma pack(push, 1) 27484034ad4SAnthony Koo 27584034ad4SAnthony Koo /* Magic value for identifying dmub_fw_meta_info */ 27684034ad4SAnthony Koo #define DMUB_FW_META_MAGIC 0x444D5542 27784034ad4SAnthony Koo 27884034ad4SAnthony Koo /* Offset from the end of the file to the dmub_fw_meta_info */ 27984034ad4SAnthony Koo #define DMUB_FW_META_OFFSET 0x24 28084034ad4SAnthony Koo 28184034ad4SAnthony Koo /** 28284034ad4SAnthony Koo * struct dmub_fw_meta_info - metadata associated with fw binary 28384034ad4SAnthony Koo * 28484034ad4SAnthony Koo * NOTE: This should be considered a stable API. Fields should 28584034ad4SAnthony Koo * not be repurposed or reordered. New fields should be 28684034ad4SAnthony Koo * added instead to extend the structure. 28784034ad4SAnthony Koo * 28884034ad4SAnthony Koo * @magic_value: magic value identifying DMUB firmware meta info 28984034ad4SAnthony Koo * @fw_region_size: size of the firmware state region 29084034ad4SAnthony Koo * @trace_buffer_size: size of the tracebuffer region 29184034ad4SAnthony Koo * @fw_version: the firmware version information 292b2265774SAnthony Koo * @dal_fw: 1 if the firmware is DAL 29384034ad4SAnthony Koo */ 29484034ad4SAnthony Koo struct dmub_fw_meta_info { 295592a6318SAnthony Koo uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 296592a6318SAnthony Koo uint32_t fw_region_size; /**< size of the firmware state region */ 297592a6318SAnthony Koo uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 298592a6318SAnthony Koo uint32_t fw_version; /**< the firmware version information */ 299592a6318SAnthony Koo uint8_t dal_fw; /**< 1 if the firmware is DAL */ 300592a6318SAnthony Koo uint8_t reserved[3]; /**< padding bits */ 30184034ad4SAnthony Koo }; 30284034ad4SAnthony Koo 303592a6318SAnthony Koo /** 304592a6318SAnthony Koo * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 305592a6318SAnthony Koo */ 30684034ad4SAnthony Koo union dmub_fw_meta { 307592a6318SAnthony Koo struct dmub_fw_meta_info info; /**< metadata info */ 308592a6318SAnthony Koo uint8_t reserved[64]; /**< padding bits */ 30984034ad4SAnthony Koo }; 31084034ad4SAnthony Koo 31184034ad4SAnthony Koo #pragma pack(pop) 312788408b7SAnthony Koo 31384034ad4SAnthony Koo //============================================================================== 3146b66208fSYongqiang Sun //< DMUB Trace Buffer>================================================================ 3156b66208fSYongqiang Sun //============================================================================== 316592a6318SAnthony Koo /** 317592a6318SAnthony Koo * dmub_trace_code_t - firmware trace code, 32-bits 318592a6318SAnthony Koo */ 3196b66208fSYongqiang Sun typedef uint32_t dmub_trace_code_t; 3206b66208fSYongqiang Sun 321592a6318SAnthony Koo /** 322592a6318SAnthony Koo * struct dmcub_trace_buf_entry - Firmware trace entry 323592a6318SAnthony Koo */ 3246b66208fSYongqiang Sun struct dmcub_trace_buf_entry { 325592a6318SAnthony Koo dmub_trace_code_t trace_code; /**< trace code for the event */ 326592a6318SAnthony Koo uint32_t tick_count; /**< the tick count at time of trace */ 327592a6318SAnthony Koo uint32_t param0; /**< trace defined parameter 0 */ 328592a6318SAnthony Koo uint32_t param1; /**< trace defined parameter 1 */ 3296b66208fSYongqiang Sun }; 3306b66208fSYongqiang Sun 3316b66208fSYongqiang Sun //============================================================================== 332788408b7SAnthony Koo //< DMUB_STATUS>================================================================ 333788408b7SAnthony Koo //============================================================================== 334788408b7SAnthony Koo 335788408b7SAnthony Koo /** 336788408b7SAnthony Koo * DMCUB scratch registers can be used to determine firmware status. 337788408b7SAnthony Koo * Current scratch register usage is as follows: 338788408b7SAnthony Koo * 339492dd8a8SAnthony Koo * SCRATCH0: FW Boot Status register 340021eaef8SAnthony Koo * SCRATCH5: LVTMA Status Register 341492dd8a8SAnthony Koo * SCRATCH15: FW Boot Options register 342788408b7SAnthony Koo */ 343788408b7SAnthony Koo 344592a6318SAnthony Koo /** 345592a6318SAnthony Koo * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 346592a6318SAnthony Koo */ 347492dd8a8SAnthony Koo union dmub_fw_boot_status { 348492dd8a8SAnthony Koo struct { 349592a6318SAnthony Koo uint32_t dal_fw : 1; /**< 1 if DAL FW */ 350592a6318SAnthony Koo uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 351592a6318SAnthony Koo uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 352592a6318SAnthony Koo uint32_t restore_required : 1; /**< 1 if driver should call restore */ 35301934c30SAnthony Koo uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 35401934c30SAnthony Koo uint32_t reserved : 1; 35501934c30SAnthony Koo uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 35601934c30SAnthony Koo 357592a6318SAnthony Koo } bits; /**< status bits */ 358592a6318SAnthony Koo uint32_t all; /**< 32-bit access to status bits */ 359492dd8a8SAnthony Koo }; 360492dd8a8SAnthony Koo 361592a6318SAnthony Koo /** 362592a6318SAnthony Koo * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 363592a6318SAnthony Koo */ 364492dd8a8SAnthony Koo enum dmub_fw_boot_status_bit { 365592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 366592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 367592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 368592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 3691e0958bbSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 37001934c30SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 371492dd8a8SAnthony Koo }; 372492dd8a8SAnthony Koo 373021eaef8SAnthony Koo /* Register bit definition for SCRATCH5 */ 374021eaef8SAnthony Koo union dmub_lvtma_status { 375021eaef8SAnthony Koo struct { 376021eaef8SAnthony Koo uint32_t psp_ok : 1; 377021eaef8SAnthony Koo uint32_t edp_on : 1; 378021eaef8SAnthony Koo uint32_t reserved : 30; 379021eaef8SAnthony Koo } bits; 380021eaef8SAnthony Koo uint32_t all; 381021eaef8SAnthony Koo }; 382021eaef8SAnthony Koo 383021eaef8SAnthony Koo enum dmub_lvtma_status_bit { 384021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 385021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 386021eaef8SAnthony Koo }; 387021eaef8SAnthony Koo 388592a6318SAnthony Koo /** 3891e0958bbSAnthony Koo * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 390592a6318SAnthony Koo */ 391492dd8a8SAnthony Koo union dmub_fw_boot_options { 392492dd8a8SAnthony Koo struct { 393592a6318SAnthony Koo uint32_t pemu_env : 1; /**< 1 if PEMU */ 394592a6318SAnthony Koo uint32_t fpga_env : 1; /**< 1 if FPGA */ 395592a6318SAnthony Koo uint32_t optimized_init : 1; /**< 1 if optimized init */ 396592a6318SAnthony Koo uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 397592a6318SAnthony Koo uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 398592a6318SAnthony Koo uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 399b04cb192SNicholas Kazlauskas uint32_t z10_disable: 1; /**< 1 to disable z10 */ 400b0ce6272SMeenakshikumar Somasundaram uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 4011e0958bbSAnthony Koo uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 4023137f792SHansen uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 4033137f792SHansen uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 4043137f792SHansen /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 4053137f792SHansen uint32_t power_optimization: 1; 406b129c94eSAnthony Koo uint32_t diag_env: 1; /* 1 if diagnostic environment */ 4075cef7e8eSAnthony Koo uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 408ea5a4db9SAnthony Koo uint32_t usb4_cm_version: 1; /**< 1 CM support */ 4096f4f8ff5SMeenakshikumar Somasundaram uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 41073f73741SAnthony Koo uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 411b129c94eSAnthony Koo 41273f73741SAnthony Koo uint32_t reserved : 15; /**< reserved */ 413592a6318SAnthony Koo } bits; /**< boot bits */ 414592a6318SAnthony Koo uint32_t all; /**< 32-bit access to bits */ 415492dd8a8SAnthony Koo }; 416492dd8a8SAnthony Koo 417492dd8a8SAnthony Koo enum dmub_fw_boot_options_bit { 418592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 419592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 420592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 421492dd8a8SAnthony Koo }; 422492dd8a8SAnthony Koo 423788408b7SAnthony Koo //============================================================================== 424788408b7SAnthony Koo //</DMUB_STATUS>================================================================ 42584034ad4SAnthony Koo //============================================================================== 42684034ad4SAnthony Koo //< DMUB_VBIOS>================================================================= 42784034ad4SAnthony Koo //============================================================================== 42884034ad4SAnthony Koo 42984034ad4SAnthony Koo /* 430592a6318SAnthony Koo * enum dmub_cmd_vbios_type - VBIOS commands. 431592a6318SAnthony Koo * 43284034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 43384034ad4SAnthony Koo * Do not reuse or modify IDs. 43484034ad4SAnthony Koo */ 43584034ad4SAnthony Koo enum dmub_cmd_vbios_type { 436592a6318SAnthony Koo /** 437592a6318SAnthony Koo * Configures the DIG encoder. 438592a6318SAnthony Koo */ 43984034ad4SAnthony Koo DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 440592a6318SAnthony Koo /** 441592a6318SAnthony Koo * Controls the PHY. 442592a6318SAnthony Koo */ 44384034ad4SAnthony Koo DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 444592a6318SAnthony Koo /** 445592a6318SAnthony Koo * Sets the pixel clock/symbol clock. 446592a6318SAnthony Koo */ 44784034ad4SAnthony Koo DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 448592a6318SAnthony Koo /** 449592a6318SAnthony Koo * Enables or disables power gating. 450592a6318SAnthony Koo */ 45184034ad4SAnthony Koo DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 45241f91315SNicholas Kazlauskas /** 45341f91315SNicholas Kazlauskas * Controls embedded panels. 45441f91315SNicholas Kazlauskas */ 4552ac685bfSAnthony Koo DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 45641f91315SNicholas Kazlauskas /** 45741f91315SNicholas Kazlauskas * Query DP alt status on a transmitter. 45841f91315SNicholas Kazlauskas */ 45941f91315SNicholas Kazlauskas DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 460*e383b127SNicholas Kazlauskas /** 461*e383b127SNicholas Kazlauskas * Controls domain power gating 462*e383b127SNicholas Kazlauskas */ 463*e383b127SNicholas Kazlauskas DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 46484034ad4SAnthony Koo }; 46584034ad4SAnthony Koo 46684034ad4SAnthony Koo //============================================================================== 46784034ad4SAnthony Koo //</DMUB_VBIOS>================================================================= 46884034ad4SAnthony Koo //============================================================================== 46984034ad4SAnthony Koo //< DMUB_GPINT>================================================================= 47084034ad4SAnthony Koo //============================================================================== 47184034ad4SAnthony Koo 47284034ad4SAnthony Koo /** 47384034ad4SAnthony Koo * The shifts and masks below may alternatively be used to format and read 47484034ad4SAnthony Koo * the command register bits. 47584034ad4SAnthony Koo */ 47684034ad4SAnthony Koo 47784034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 47884034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_SHIFT 0 47984034ad4SAnthony Koo 48084034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 48184034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 48284034ad4SAnthony Koo 48384034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_MASK 0xF 48484034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_SHIFT 28 48584034ad4SAnthony Koo 48684034ad4SAnthony Koo /** 48784034ad4SAnthony Koo * Command responses. 48884034ad4SAnthony Koo */ 48984034ad4SAnthony Koo 490592a6318SAnthony Koo /** 491592a6318SAnthony Koo * Return response for DMUB_GPINT__STOP_FW command. 492592a6318SAnthony Koo */ 49384034ad4SAnthony Koo #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 49484034ad4SAnthony Koo 49584034ad4SAnthony Koo /** 496592a6318SAnthony Koo * union dmub_gpint_data_register - Format for sending a command via the GPINT. 49784034ad4SAnthony Koo */ 49884034ad4SAnthony Koo union dmub_gpint_data_register { 49984034ad4SAnthony Koo struct { 500592a6318SAnthony Koo uint32_t param : 16; /**< 16-bit parameter */ 501592a6318SAnthony Koo uint32_t command_code : 12; /**< GPINT command */ 502592a6318SAnthony Koo uint32_t status : 4; /**< Command status bit */ 503592a6318SAnthony Koo } bits; /**< GPINT bit access */ 504592a6318SAnthony Koo uint32_t all; /**< GPINT 32-bit access */ 50584034ad4SAnthony Koo }; 50684034ad4SAnthony Koo 50784034ad4SAnthony Koo /* 508592a6318SAnthony Koo * enum dmub_gpint_command - GPINT command to DMCUB FW 509592a6318SAnthony Koo * 51084034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 51184034ad4SAnthony Koo * Do not reuse or modify IDs. 51284034ad4SAnthony Koo */ 51384034ad4SAnthony Koo enum dmub_gpint_command { 514592a6318SAnthony Koo /** 515592a6318SAnthony Koo * Invalid command, ignored. 516592a6318SAnthony Koo */ 51784034ad4SAnthony Koo DMUB_GPINT__INVALID_COMMAND = 0, 518592a6318SAnthony Koo /** 519592a6318SAnthony Koo * DESC: Queries the firmware version. 520592a6318SAnthony Koo * RETURN: Firmware version. 521592a6318SAnthony Koo */ 52284034ad4SAnthony Koo DMUB_GPINT__GET_FW_VERSION = 1, 523592a6318SAnthony Koo /** 524592a6318SAnthony Koo * DESC: Halts the firmware. 525592a6318SAnthony Koo * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 526592a6318SAnthony Koo */ 52784034ad4SAnthony Koo DMUB_GPINT__STOP_FW = 2, 5281a595f28SAnthony Koo /** 5291a595f28SAnthony Koo * DESC: Get PSR state from FW. 5301a595f28SAnthony Koo * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 5311a595f28SAnthony Koo */ 53284034ad4SAnthony Koo DMUB_GPINT__GET_PSR_STATE = 7, 53380eba958SAnthony Koo /** 53480eba958SAnthony Koo * DESC: Notifies DMCUB of the currently active streams. 53580eba958SAnthony Koo * ARGS: Stream mask, 1 bit per active stream index. 53680eba958SAnthony Koo */ 53780eba958SAnthony Koo DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 5381a595f28SAnthony Koo /** 5391a595f28SAnthony Koo * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 5401a595f28SAnthony Koo * ARGS: We can measure residency from various points. The argument will specify the residency mode. 5411a595f28SAnthony Koo * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 5421a595f28SAnthony Koo * RETURN: PSR residency in milli-percent. 5431a595f28SAnthony Koo */ 544672251b2SAnthony Koo DMUB_GPINT__PSR_RESIDENCY = 9, 54501934c30SAnthony Koo 54601934c30SAnthony Koo /** 54701934c30SAnthony Koo * DESC: Notifies DMCUB detection is done so detection required can be cleared. 54801934c30SAnthony Koo */ 54901934c30SAnthony Koo DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 55084034ad4SAnthony Koo }; 55184034ad4SAnthony Koo 5520b51e7e8SAnthony Koo /** 5530b51e7e8SAnthony Koo * INBOX0 generic command definition 5540b51e7e8SAnthony Koo */ 5550b51e7e8SAnthony Koo union dmub_inbox0_cmd_common { 5560b51e7e8SAnthony Koo struct { 5570b51e7e8SAnthony Koo uint32_t command_code: 8; /**< INBOX0 command code */ 5580b51e7e8SAnthony Koo uint32_t param: 24; /**< 24-bit parameter */ 5590b51e7e8SAnthony Koo } bits; 5600b51e7e8SAnthony Koo uint32_t all; 5610b51e7e8SAnthony Koo }; 5620b51e7e8SAnthony Koo 5630b51e7e8SAnthony Koo /** 5640b51e7e8SAnthony Koo * INBOX0 hw_lock command definition 5650b51e7e8SAnthony Koo */ 5660b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw { 5670b51e7e8SAnthony Koo struct { 5680b51e7e8SAnthony Koo uint32_t command_code: 8; 5690b51e7e8SAnthony Koo 5700b51e7e8SAnthony Koo /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 5712412d339SAnthony Koo uint32_t hw_lock_client: 2; 5720b51e7e8SAnthony Koo 5730b51e7e8SAnthony Koo /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 5740b51e7e8SAnthony Koo uint32_t otg_inst: 3; 5750b51e7e8SAnthony Koo uint32_t opp_inst: 3; 5760b51e7e8SAnthony Koo uint32_t dig_inst: 3; 5770b51e7e8SAnthony Koo 5780b51e7e8SAnthony Koo /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 5790b51e7e8SAnthony Koo uint32_t lock_pipe: 1; 5800b51e7e8SAnthony Koo uint32_t lock_cursor: 1; 5810b51e7e8SAnthony Koo uint32_t lock_dig: 1; 5820b51e7e8SAnthony Koo uint32_t triple_buffer_lock: 1; 5830b51e7e8SAnthony Koo 5840b51e7e8SAnthony Koo uint32_t lock: 1; /**< Lock */ 5850b51e7e8SAnthony Koo uint32_t should_release: 1; /**< Release */ 5862412d339SAnthony Koo uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 5870b51e7e8SAnthony Koo } bits; 5880b51e7e8SAnthony Koo uint32_t all; 5890b51e7e8SAnthony Koo }; 5900b51e7e8SAnthony Koo 5910b51e7e8SAnthony Koo union dmub_inbox0_data_register { 5920b51e7e8SAnthony Koo union dmub_inbox0_cmd_common inbox0_cmd_common; 5930b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 5940b51e7e8SAnthony Koo }; 5950b51e7e8SAnthony Koo 5960b51e7e8SAnthony Koo enum dmub_inbox0_command { 5970b51e7e8SAnthony Koo /** 5980b51e7e8SAnthony Koo * DESC: Invalid command, ignored. 5990b51e7e8SAnthony Koo */ 6000b51e7e8SAnthony Koo DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 6010b51e7e8SAnthony Koo /** 6020b51e7e8SAnthony Koo * DESC: Notification to acquire/release HW lock 6030b51e7e8SAnthony Koo * ARGS: 6040b51e7e8SAnthony Koo */ 6050b51e7e8SAnthony Koo DMUB_INBOX0_CMD__HW_LOCK = 1, 6060b51e7e8SAnthony Koo }; 60784034ad4SAnthony Koo //============================================================================== 60884034ad4SAnthony Koo //</DMUB_GPINT>================================================================= 60984034ad4SAnthony Koo //============================================================================== 61084034ad4SAnthony Koo //< DMUB_CMD>=================================================================== 61184034ad4SAnthony Koo //============================================================================== 61284034ad4SAnthony Koo 613592a6318SAnthony Koo /** 614592a6318SAnthony Koo * Size in bytes of each DMUB command. 615592a6318SAnthony Koo */ 6167c008829SNicholas Kazlauskas #define DMUB_RB_CMD_SIZE 64 617592a6318SAnthony Koo 618592a6318SAnthony Koo /** 619592a6318SAnthony Koo * Maximum number of items in the DMUB ringbuffer. 620592a6318SAnthony Koo */ 6217c008829SNicholas Kazlauskas #define DMUB_RB_MAX_ENTRY 128 622592a6318SAnthony Koo 623592a6318SAnthony Koo /** 624592a6318SAnthony Koo * Ringbuffer size in bytes. 625592a6318SAnthony Koo */ 6267c008829SNicholas Kazlauskas #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 627592a6318SAnthony Koo 628592a6318SAnthony Koo /** 629592a6318SAnthony Koo * REG_SET mask for reg offload. 630592a6318SAnthony Koo */ 6317c008829SNicholas Kazlauskas #define REG_SET_MASK 0xFFFF 6327c008829SNicholas Kazlauskas 633d4bbcecbSNicholas Kazlauskas /* 634592a6318SAnthony Koo * enum dmub_cmd_type - DMUB inbox command. 635592a6318SAnthony Koo * 636d4bbcecbSNicholas Kazlauskas * Command IDs should be treated as stable ABI. 637d4bbcecbSNicholas Kazlauskas * Do not reuse or modify IDs. 638d4bbcecbSNicholas Kazlauskas */ 639d4bbcecbSNicholas Kazlauskas enum dmub_cmd_type { 640592a6318SAnthony Koo /** 641592a6318SAnthony Koo * Invalid command. 642592a6318SAnthony Koo */ 643d4bbcecbSNicholas Kazlauskas DMUB_CMD__NULL = 0, 644592a6318SAnthony Koo /** 645592a6318SAnthony Koo * Read modify write register sequence offload. 646592a6318SAnthony Koo */ 647d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 648592a6318SAnthony Koo /** 649592a6318SAnthony Koo * Field update register sequence offload. 650592a6318SAnthony Koo */ 651d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 652592a6318SAnthony Koo /** 653592a6318SAnthony Koo * Burst write sequence offload. 654592a6318SAnthony Koo */ 655d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 656592a6318SAnthony Koo /** 657592a6318SAnthony Koo * Reg wait sequence offload. 658592a6318SAnthony Koo */ 659d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_REG_WAIT = 4, 660592a6318SAnthony Koo /** 661592a6318SAnthony Koo * Workaround to avoid HUBP underflow during NV12 playback. 662592a6318SAnthony Koo */ 663bae9c49bSYongqiang Sun DMUB_CMD__PLAT_54186_WA = 5, 6641a595f28SAnthony Koo /** 6651a595f28SAnthony Koo * Command type used to query FW feature caps. 6661a595f28SAnthony Koo */ 66734ba432cSAnthony Koo DMUB_CMD__QUERY_FEATURE_CAPS = 6, 6681a595f28SAnthony Koo /** 669b09c1fffSLeo (Hanghong) Ma * Command type used to get visual confirm color. 670b09c1fffSLeo (Hanghong) Ma */ 671b09c1fffSLeo (Hanghong) Ma DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 672b09c1fffSLeo (Hanghong) Ma /** 6731a595f28SAnthony Koo * Command type used for all PSR commands. 6741a595f28SAnthony Koo */ 675d4bbcecbSNicholas Kazlauskas DMUB_CMD__PSR = 64, 676592a6318SAnthony Koo /** 677592a6318SAnthony Koo * Command type used for all MALL commands. 678592a6318SAnthony Koo */ 67952f2e83eSBhawanpreet Lakha DMUB_CMD__MALL = 65, 6801a595f28SAnthony Koo /** 6811a595f28SAnthony Koo * Command type used for all ABM commands. 6821a595f28SAnthony Koo */ 683e6ea8c34SWyatt Wood DMUB_CMD__ABM = 66, 6841a595f28SAnthony Koo /** 68583eb5385SDavid Zhang * Command type used to update dirty rects in FW. 68683eb5385SDavid Zhang */ 68783eb5385SDavid Zhang DMUB_CMD__UPDATE_DIRTY_RECT = 67, 68883eb5385SDavid Zhang /** 68983eb5385SDavid Zhang * Command type used to update cursor info in FW. 69083eb5385SDavid Zhang */ 69183eb5385SDavid Zhang DMUB_CMD__UPDATE_CURSOR_INFO = 68, 69283eb5385SDavid Zhang /** 6931a595f28SAnthony Koo * Command type used for HW locking in FW. 6941a595f28SAnthony Koo */ 695788408b7SAnthony Koo DMUB_CMD__HW_LOCK = 69, 6961a595f28SAnthony Koo /** 6971a595f28SAnthony Koo * Command type used to access DP AUX. 6981a595f28SAnthony Koo */ 699d9beecfcSAnthony Koo DMUB_CMD__DP_AUX_ACCESS = 70, 7001a595f28SAnthony Koo /** 7011a595f28SAnthony Koo * Command type used for OUTBOX1 notification enable 7021a595f28SAnthony Koo */ 703d9beecfcSAnthony Koo DMUB_CMD__OUTBOX1_ENABLE = 71, 7045cef7e8eSAnthony Koo 705b04cb192SNicholas Kazlauskas /** 706b04cb192SNicholas Kazlauskas * Command type used for all idle optimization commands. 707b04cb192SNicholas Kazlauskas */ 708b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT = 72, 709b04cb192SNicholas Kazlauskas /** 710b04cb192SNicholas Kazlauskas * Command type used for all clock manager commands. 711b04cb192SNicholas Kazlauskas */ 712b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR = 73, 713b04cb192SNicholas Kazlauskas /** 714b04cb192SNicholas Kazlauskas * Command type used for all panel control commands. 715b04cb192SNicholas Kazlauskas */ 716b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL = 74, 717ac2e555eSAurabindo Pillai /** 718ac2e555eSAurabindo Pillai * Command type used for <TODO:description> 719ac2e555eSAurabindo Pillai */ 720ac2e555eSAurabindo Pillai DMUB_CMD__CAB_FOR_SS = 75, 72185f4bc0cSAlvin Lee 72285f4bc0cSAlvin Lee DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 72385f4bc0cSAlvin Lee 724592a6318SAnthony Koo /** 72576724b76SJimmy Kizito * Command type used for interfacing with DPIA. 72676724b76SJimmy Kizito */ 72776724b76SJimmy Kizito DMUB_CMD__DPIA = 77, 72876724b76SJimmy Kizito /** 729021eaef8SAnthony Koo * Command type used for EDID CEA parsing 730021eaef8SAnthony Koo */ 731021eaef8SAnthony Koo DMUB_CMD__EDID_CEA = 79, 732021eaef8SAnthony Koo /** 733c595fb05SWenjing Liu * Command type used for getting usbc cable ID 734c595fb05SWenjing Liu */ 735c595fb05SWenjing Liu DMUB_CMD_GET_USBC_CABLE_ID = 81, 736c595fb05SWenjing Liu /** 737ea5a4db9SAnthony Koo * Command type used to query HPD state. 738ea5a4db9SAnthony Koo */ 739ea5a4db9SAnthony Koo DMUB_CMD__QUERY_HPD_STATE = 82, 740ea5a4db9SAnthony Koo /** 741592a6318SAnthony Koo * Command type used for all VBIOS interface commands. 742592a6318SAnthony Koo */ 7431fb695d9SAnthony Koo 744c0459bddSAlan Liu /** 745c0459bddSAlan Liu * Command type used for all SECURE_DISPLAY commands. 746c0459bddSAlan Liu */ 747c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY = 85, 7486f4f8ff5SMeenakshikumar Somasundaram 7496f4f8ff5SMeenakshikumar Somasundaram /** 7506f4f8ff5SMeenakshikumar Somasundaram * Command type used to set DPIA HPD interrupt state 7516f4f8ff5SMeenakshikumar Somasundaram */ 7526f4f8ff5SMeenakshikumar Somasundaram DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 7536f4f8ff5SMeenakshikumar Somasundaram 754d4bbcecbSNicholas Kazlauskas DMUB_CMD__VBIOS = 128, 7557c008829SNicholas Kazlauskas }; 7567c008829SNicholas Kazlauskas 757592a6318SAnthony Koo /** 758592a6318SAnthony Koo * enum dmub_out_cmd_type - DMUB outbox commands. 759592a6318SAnthony Koo */ 7603b37260bSAnthony Koo enum dmub_out_cmd_type { 761592a6318SAnthony Koo /** 762592a6318SAnthony Koo * Invalid outbox command, ignored. 763592a6318SAnthony Koo */ 7643b37260bSAnthony Koo DMUB_OUT_CMD__NULL = 0, 7651a595f28SAnthony Koo /** 7661a595f28SAnthony Koo * Command type used for DP AUX Reply data notification 7671a595f28SAnthony Koo */ 768d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_AUX_REPLY = 1, 769892b74a6SMeenakshikumar Somasundaram /** 770892b74a6SMeenakshikumar Somasundaram * Command type used for DP HPD event notification 771892b74a6SMeenakshikumar Somasundaram */ 772892b74a6SMeenakshikumar Somasundaram DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 77371af9d46SMeenakshikumar Somasundaram /** 77471af9d46SMeenakshikumar Somasundaram * Command type used for SET_CONFIG Reply notification 77571af9d46SMeenakshikumar Somasundaram */ 77671af9d46SMeenakshikumar Somasundaram DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 7778af54c61SMustapha Ghaddar /** 7788af54c61SMustapha Ghaddar * Command type used for USB4 DPIA notification 7798af54c61SMustapha Ghaddar */ 7808af54c61SMustapha Ghaddar DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 7813b37260bSAnthony Koo }; 7823b37260bSAnthony Koo 78376724b76SJimmy Kizito /* DMUB_CMD__DPIA command sub-types. */ 78476724b76SJimmy Kizito enum dmub_cmd_dpia_type { 78576724b76SJimmy Kizito DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 78671af9d46SMeenakshikumar Somasundaram DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 787139a3311SMeenakshikumar Somasundaram DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 78876724b76SJimmy Kizito }; 78976724b76SJimmy Kizito 7908af54c61SMustapha Ghaddar /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 7918af54c61SMustapha Ghaddar enum dmub_cmd_dpia_notification_type { 7928af54c61SMustapha Ghaddar DPIA_NOTIFY__BW_ALLOCATION = 0, 7938af54c61SMustapha Ghaddar }; 7948af54c61SMustapha Ghaddar 7957c008829SNicholas Kazlauskas #pragma pack(push, 1) 7967c008829SNicholas Kazlauskas 797592a6318SAnthony Koo /** 798592a6318SAnthony Koo * struct dmub_cmd_header - Common command header fields. 799592a6318SAnthony Koo */ 8007c008829SNicholas Kazlauskas struct dmub_cmd_header { 801592a6318SAnthony Koo unsigned int type : 8; /**< command type */ 802592a6318SAnthony Koo unsigned int sub_type : 8; /**< command sub type */ 803592a6318SAnthony Koo unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 8040b51e7e8SAnthony Koo unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 8050b51e7e8SAnthony Koo unsigned int reserved0 : 6; /**< reserved bits */ 806592a6318SAnthony Koo unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 807592a6318SAnthony Koo unsigned int reserved1 : 2; /**< reserved bits */ 8087c008829SNicholas Kazlauskas }; 8097c008829SNicholas Kazlauskas 8107c008829SNicholas Kazlauskas /* 811592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write 8127c008829SNicholas Kazlauskas * 8137c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 5 sets of read modify writes, 8147c008829SNicholas Kazlauskas * each take 3 dwords. 8157c008829SNicholas Kazlauskas * 8167c008829SNicholas Kazlauskas * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 8177c008829SNicholas Kazlauskas * 8187c008829SNicholas Kazlauskas * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 8197c008829SNicholas Kazlauskas * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 8207c008829SNicholas Kazlauskas */ 8217c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence { 822592a6318SAnthony Koo uint32_t addr; /**< register address */ 823592a6318SAnthony Koo uint32_t modify_mask; /**< modify mask */ 824592a6318SAnthony Koo uint32_t modify_value; /**< modify value */ 8257c008829SNicholas Kazlauskas }; 8267c008829SNicholas Kazlauskas 827592a6318SAnthony Koo /** 828592a6318SAnthony Koo * Maximum number of ops in read modify write sequence. 829592a6318SAnthony Koo */ 8307c008829SNicholas Kazlauskas #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 831592a6318SAnthony Koo 832592a6318SAnthony Koo /** 833592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 834592a6318SAnthony Koo */ 8357c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write { 836592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 837592a6318SAnthony Koo /** 838592a6318SAnthony Koo * Read modify write sequence. 839592a6318SAnthony Koo */ 8407c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 8417c008829SNicholas Kazlauskas }; 8427c008829SNicholas Kazlauskas 8437c008829SNicholas Kazlauskas /* 8447c008829SNicholas Kazlauskas * Update a register with specified masks and values sequeunce 8457c008829SNicholas Kazlauskas * 8467c008829SNicholas Kazlauskas * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 8477c008829SNicholas Kazlauskas * 8487c008829SNicholas Kazlauskas * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 8497c008829SNicholas Kazlauskas * 8507c008829SNicholas Kazlauskas * 8517c008829SNicholas Kazlauskas * USE CASE: 8527c008829SNicholas Kazlauskas * 1. auto-increment register where additional read would update pointer and produce wrong result 8537c008829SNicholas Kazlauskas * 2. toggle a bit without read in the middle 8547c008829SNicholas Kazlauskas */ 8557c008829SNicholas Kazlauskas 8567c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence { 857592a6318SAnthony Koo uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 858592a6318SAnthony Koo uint32_t modify_value; /**< value to update with */ 8597c008829SNicholas Kazlauskas }; 8607c008829SNicholas Kazlauskas 861592a6318SAnthony Koo /** 862592a6318SAnthony Koo * Maximum number of ops in field update sequence. 863592a6318SAnthony Koo */ 8647c008829SNicholas Kazlauskas #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 865592a6318SAnthony Koo 866592a6318SAnthony Koo /** 867592a6318SAnthony Koo * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 868592a6318SAnthony Koo */ 8697c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence { 870592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 871592a6318SAnthony Koo uint32_t addr; /**< register address */ 872592a6318SAnthony Koo /** 873592a6318SAnthony Koo * Field update sequence. 874592a6318SAnthony Koo */ 8757c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 8767c008829SNicholas Kazlauskas }; 8777c008829SNicholas Kazlauskas 878592a6318SAnthony Koo 879592a6318SAnthony Koo /** 880592a6318SAnthony Koo * Maximum number of burst write values. 881592a6318SAnthony Koo */ 882592a6318SAnthony Koo #define DMUB_BURST_WRITE_VALUES__MAX 14 883592a6318SAnthony Koo 8847c008829SNicholas Kazlauskas /* 885592a6318SAnthony Koo * struct dmub_rb_cmd_burst_write - Burst write 8867c008829SNicholas Kazlauskas * 8877c008829SNicholas Kazlauskas * support use case such as writing out LUTs. 8887c008829SNicholas Kazlauskas * 8897c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 14 values to write to given address 8907c008829SNicholas Kazlauskas * 8917c008829SNicholas Kazlauskas * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 8927c008829SNicholas Kazlauskas */ 8937c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write { 894592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 895592a6318SAnthony Koo uint32_t addr; /**< register start address */ 896592a6318SAnthony Koo /** 897592a6318SAnthony Koo * Burst write register values. 898592a6318SAnthony Koo */ 8997c008829SNicholas Kazlauskas uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 9007c008829SNicholas Kazlauskas }; 9017c008829SNicholas Kazlauskas 902592a6318SAnthony Koo /** 903592a6318SAnthony Koo * struct dmub_rb_cmd_common - Common command header 904592a6318SAnthony Koo */ 9057c008829SNicholas Kazlauskas struct dmub_rb_cmd_common { 906592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 907592a6318SAnthony Koo /** 908592a6318SAnthony Koo * Padding to RB_CMD_SIZE 909592a6318SAnthony Koo */ 9107c008829SNicholas Kazlauskas uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 9117c008829SNicholas Kazlauskas }; 9127c008829SNicholas Kazlauskas 913592a6318SAnthony Koo /** 914592a6318SAnthony Koo * struct dmub_cmd_reg_wait_data - Register wait data 915592a6318SAnthony Koo */ 9167c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data { 917592a6318SAnthony Koo uint32_t addr; /**< Register address */ 918592a6318SAnthony Koo uint32_t mask; /**< Mask for register bits */ 919592a6318SAnthony Koo uint32_t condition_field_value; /**< Value to wait for */ 920592a6318SAnthony Koo uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 9217c008829SNicholas Kazlauskas }; 9227c008829SNicholas Kazlauskas 923592a6318SAnthony Koo /** 924592a6318SAnthony Koo * struct dmub_rb_cmd_reg_wait - Register wait command 925592a6318SAnthony Koo */ 9267c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait { 927592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 928592a6318SAnthony Koo struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 9297c008829SNicholas Kazlauskas }; 9307c008829SNicholas Kazlauskas 931592a6318SAnthony Koo /** 932592a6318SAnthony Koo * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 933592a6318SAnthony Koo * 934592a6318SAnthony Koo * Reprograms surface parameters to avoid underflow. 935592a6318SAnthony Koo */ 936bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa { 937592a6318SAnthony Koo uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 938592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 939592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 940592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 941592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 94222aa5614SYongqiang Sun struct { 943592a6318SAnthony Koo uint8_t hubp_inst : 4; /**< HUBP instance */ 944592a6318SAnthony Koo uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 945592a6318SAnthony Koo uint8_t immediate :1; /**< Immediate flip */ 946592a6318SAnthony Koo uint8_t vmid : 4; /**< VMID */ 947592a6318SAnthony Koo uint8_t grph_stereo : 1; /**< 1 if stereo */ 948592a6318SAnthony Koo uint32_t reserved : 21; /**< Reserved */ 949592a6318SAnthony Koo } flip_params; /**< Pageflip parameters */ 950826e7ffaSAnthony Koo uint32_t reserved[8]; /**< Reserved bits */ 9518c019253SYongqiang Sun }; 9528c019253SYongqiang Sun 953592a6318SAnthony Koo /** 954592a6318SAnthony Koo * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 955592a6318SAnthony Koo */ 956bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa { 957592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 958592a6318SAnthony Koo struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 9598c019253SYongqiang Sun }; 9608c019253SYongqiang Sun 961592a6318SAnthony Koo /** 962592a6318SAnthony Koo * struct dmub_rb_cmd_mall - MALL command data. 963592a6318SAnthony Koo */ 96452f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall { 965592a6318SAnthony Koo struct dmub_cmd_header header; /**< Common command header */ 966592a6318SAnthony Koo union dmub_addr cursor_copy_src; /**< Cursor copy address */ 967592a6318SAnthony Koo union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 968592a6318SAnthony Koo uint32_t tmr_delay; /**< Timer delay */ 969592a6318SAnthony Koo uint32_t tmr_scale; /**< Timer scale */ 970592a6318SAnthony Koo uint16_t cursor_width; /**< Cursor width in pixels */ 971592a6318SAnthony Koo uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 972592a6318SAnthony Koo uint16_t cursor_height; /**< Cursor height in pixels */ 973592a6318SAnthony Koo uint8_t cursor_bpp; /**< Cursor bits per pixel */ 974592a6318SAnthony Koo uint8_t debug_bits; /**< Debug bits */ 975ea7154d8SBhawanpreet Lakha 976592a6318SAnthony Koo uint8_t reserved1; /**< Reserved bits */ 977592a6318SAnthony Koo uint8_t reserved2; /**< Reserved bits */ 97852f2e83eSBhawanpreet Lakha }; 97952f2e83eSBhawanpreet Lakha 980b04cb192SNicholas Kazlauskas /** 981ac2e555eSAurabindo Pillai * enum dmub_cmd_cab_type - TODO: 982ac2e555eSAurabindo Pillai */ 983ac2e555eSAurabindo Pillai enum dmub_cmd_cab_type { 984ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 985ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_DCN_REQ = 1, 986ac2e555eSAurabindo Pillai DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 987ac2e555eSAurabindo Pillai }; 988ac2e555eSAurabindo Pillai 989ac2e555eSAurabindo Pillai /** 990ac2e555eSAurabindo Pillai * struct dmub_rb_cmd_cab_for_ss - TODO: 991ac2e555eSAurabindo Pillai */ 992ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss { 993ac2e555eSAurabindo Pillai struct dmub_cmd_header header; 994ac2e555eSAurabindo Pillai uint8_t cab_alloc_ways; /* total number of ways */ 995ac2e555eSAurabindo Pillai uint8_t debug_bits; /* debug bits */ 996ac2e555eSAurabindo Pillai }; 99785f4bc0cSAlvin Lee 99885f4bc0cSAlvin Lee enum mclk_switch_mode { 99985f4bc0cSAlvin Lee NONE = 0, 100085f4bc0cSAlvin Lee FPO = 1, 100185f4bc0cSAlvin Lee SUBVP = 2, 100285f4bc0cSAlvin Lee VBLANK = 3, 100385f4bc0cSAlvin Lee }; 100485f4bc0cSAlvin Lee 100585f4bc0cSAlvin Lee /* Per pipe struct which stores the MCLK switch mode 100685f4bc0cSAlvin Lee * data to be sent to DMUB. 100785f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 100885f4bc0cSAlvin Lee * the type name can be updated 100985f4bc0cSAlvin Lee */ 101085f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 101185f4bc0cSAlvin Lee union { 101285f4bc0cSAlvin Lee struct { 101385f4bc0cSAlvin Lee uint32_t pix_clk_100hz; 101485f4bc0cSAlvin Lee uint16_t main_vblank_start; 101585f4bc0cSAlvin Lee uint16_t main_vblank_end; 101685f4bc0cSAlvin Lee uint16_t mall_region_lines; 101785f4bc0cSAlvin Lee uint16_t prefetch_lines; 101885f4bc0cSAlvin Lee uint16_t prefetch_to_mall_start_lines; 101985f4bc0cSAlvin Lee uint16_t processing_delay_lines; 102085f4bc0cSAlvin Lee uint16_t htotal; // required to calculate line time for multi-display cases 102185f4bc0cSAlvin Lee uint16_t vtotal; 102285f4bc0cSAlvin Lee uint8_t main_pipe_index; 102385f4bc0cSAlvin Lee uint8_t phantom_pipe_index; 10240acc5b06SAnthony Koo /* Since the microschedule is calculated in terms of OTG lines, 10250acc5b06SAnthony Koo * include any scaling factors to make sure when we get accurate 10260acc5b06SAnthony Koo * conversion when programming MALL_START_LINE (which is in terms 10270acc5b06SAnthony Koo * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 10280acc5b06SAnthony Koo * is 1/2 (numerator = 1, denominator = 2). 10290acc5b06SAnthony Koo */ 10300acc5b06SAnthony Koo uint8_t scale_factor_numerator; 10310acc5b06SAnthony Koo uint8_t scale_factor_denominator; 103281f776b6SAnthony Koo uint8_t is_drr; 10331591a647SAnthony Koo uint8_t main_split_pipe_index; 10341591a647SAnthony Koo uint8_t phantom_split_pipe_index; 103585f4bc0cSAlvin Lee } subvp_data; 103685f4bc0cSAlvin Lee 103785f4bc0cSAlvin Lee struct { 103885f4bc0cSAlvin Lee uint32_t pix_clk_100hz; 103985f4bc0cSAlvin Lee uint16_t vblank_start; 104085f4bc0cSAlvin Lee uint16_t vblank_end; 104185f4bc0cSAlvin Lee uint16_t vstartup_start; 104285f4bc0cSAlvin Lee uint16_t vtotal; 104385f4bc0cSAlvin Lee uint16_t htotal; 104485f4bc0cSAlvin Lee uint8_t vblank_pipe_index; 1045ae7169a9SAlvin Lee uint8_t padding[1]; 104685f4bc0cSAlvin Lee struct { 104785f4bc0cSAlvin Lee uint8_t drr_in_use; 104885f4bc0cSAlvin Lee uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 104985f4bc0cSAlvin Lee uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 105085f4bc0cSAlvin Lee uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 105185f4bc0cSAlvin Lee uint8_t use_ramping; // Use ramping or not 1052ae7169a9SAlvin Lee uint8_t drr_vblank_start_margin; 105385f4bc0cSAlvin Lee } drr_info; // DRR considered as part of SubVP + VBLANK case 105485f4bc0cSAlvin Lee } vblank_data; 105585f4bc0cSAlvin Lee } pipe_config; 105685f4bc0cSAlvin Lee 10570acc5b06SAnthony Koo /* - subvp_data in the union (pipe_config) takes up 27 bytes. 10580acc5b06SAnthony Koo * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 10590acc5b06SAnthony Koo * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 10600acc5b06SAnthony Koo */ 10610acc5b06SAnthony Koo uint8_t mode; // enum mclk_switch_mode 106285f4bc0cSAlvin Lee }; 106385f4bc0cSAlvin Lee 106485f4bc0cSAlvin Lee /** 106585f4bc0cSAlvin Lee * Config data for Sub-VP and FPO 106685f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 106785f4bc0cSAlvin Lee * the type name can be updated 106885f4bc0cSAlvin Lee */ 106985f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 107085f4bc0cSAlvin Lee uint16_t watermark_a_cache; 107185f4bc0cSAlvin Lee uint8_t vertical_int_margin_us; 107285f4bc0cSAlvin Lee uint8_t pstate_allow_width_us; 107385f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 107485f4bc0cSAlvin Lee }; 107585f4bc0cSAlvin Lee 107685f4bc0cSAlvin Lee /** 107785f4bc0cSAlvin Lee * DMUB rb command definition for Sub-VP and FPO 107885f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 107985f4bc0cSAlvin Lee * the type name can be updated 108085f4bc0cSAlvin Lee */ 108185f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 108285f4bc0cSAlvin Lee struct dmub_cmd_header header; 108385f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 108485f4bc0cSAlvin Lee }; 108585f4bc0cSAlvin Lee 1086ac2e555eSAurabindo Pillai /** 1087b04cb192SNicholas Kazlauskas * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1088b04cb192SNicholas Kazlauskas */ 1089b04cb192SNicholas Kazlauskas enum dmub_cmd_idle_opt_type { 1090b04cb192SNicholas Kazlauskas /** 1091b04cb192SNicholas Kazlauskas * DCN hardware restore. 1092b04cb192SNicholas Kazlauskas */ 1093b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1094f586fea8SJake Wang 1095f586fea8SJake Wang /** 1096f586fea8SJake Wang * DCN hardware save. 1097f586fea8SJake Wang */ 1098f586fea8SJake Wang DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1099b04cb192SNicholas Kazlauskas }; 1100b04cb192SNicholas Kazlauskas 1101b04cb192SNicholas Kazlauskas /** 1102b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1103b04cb192SNicholas Kazlauskas */ 1104b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore { 1105b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1106b04cb192SNicholas Kazlauskas }; 1107b04cb192SNicholas Kazlauskas 1108b04cb192SNicholas Kazlauskas /** 1109b04cb192SNicholas Kazlauskas * struct dmub_clocks - Clock update notification. 1110b04cb192SNicholas Kazlauskas */ 1111b04cb192SNicholas Kazlauskas struct dmub_clocks { 1112b04cb192SNicholas Kazlauskas uint32_t dispclk_khz; /**< dispclk kHz */ 1113b04cb192SNicholas Kazlauskas uint32_t dppclk_khz; /**< dppclk kHz */ 1114b04cb192SNicholas Kazlauskas uint32_t dcfclk_khz; /**< dcfclk kHz */ 1115b04cb192SNicholas Kazlauskas uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1116b04cb192SNicholas Kazlauskas }; 1117b04cb192SNicholas Kazlauskas 1118b04cb192SNicholas Kazlauskas /** 1119b04cb192SNicholas Kazlauskas * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1120b04cb192SNicholas Kazlauskas */ 1121b04cb192SNicholas Kazlauskas enum dmub_cmd_clk_mgr_type { 1122b04cb192SNicholas Kazlauskas /** 1123b04cb192SNicholas Kazlauskas * Notify DMCUB of clock update. 1124b04cb192SNicholas Kazlauskas */ 1125b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1126b04cb192SNicholas Kazlauskas }; 1127b04cb192SNicholas Kazlauskas 1128b04cb192SNicholas Kazlauskas /** 1129b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1130b04cb192SNicholas Kazlauskas */ 1131b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks { 1132b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1133b04cb192SNicholas Kazlauskas struct dmub_clocks clocks; /**< clock data */ 1134b04cb192SNicholas Kazlauskas }; 11358fe44c08SAlex Deucher 1136592a6318SAnthony Koo /** 1137592a6318SAnthony Koo * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1138592a6318SAnthony Koo */ 11397c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data { 1140592a6318SAnthony Koo union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 11417c008829SNicholas Kazlauskas }; 11427c008829SNicholas Kazlauskas 1143592a6318SAnthony Koo /** 1144592a6318SAnthony Koo * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1145592a6318SAnthony Koo */ 11467c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control { 1147592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1148592a6318SAnthony Koo struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 11497c008829SNicholas Kazlauskas }; 11507c008829SNicholas Kazlauskas 1151592a6318SAnthony Koo /** 1152592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1153592a6318SAnthony Koo */ 11547c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data { 1155592a6318SAnthony Koo struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 11567c008829SNicholas Kazlauskas }; 11577c008829SNicholas Kazlauskas 1158592a6318SAnthony Koo /** 1159592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1160592a6318SAnthony Koo */ 11617c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock { 1162592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1163592a6318SAnthony Koo struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 11647c008829SNicholas Kazlauskas }; 11657c008829SNicholas Kazlauskas 1166592a6318SAnthony Koo /** 1167592a6318SAnthony Koo * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1168592a6318SAnthony Koo */ 11697c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data { 1170592a6318SAnthony Koo struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 11717c008829SNicholas Kazlauskas }; 11727c008829SNicholas Kazlauskas 1173592a6318SAnthony Koo /** 1174592a6318SAnthony Koo * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1175592a6318SAnthony Koo */ 11767c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating { 1177592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1178592a6318SAnthony Koo struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 11797c008829SNicholas Kazlauskas }; 11807c008829SNicholas Kazlauskas 1181592a6318SAnthony Koo /** 1182592a6318SAnthony Koo * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1183592a6318SAnthony Koo */ 1184d448521eSAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 { 1185d448521eSAnthony Koo uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1186d448521eSAnthony Koo uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1187d448521eSAnthony Koo union { 1188d448521eSAnthony Koo uint8_t digmode; /**< enum atom_encode_mode_def */ 1189d448521eSAnthony Koo uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1190d448521eSAnthony Koo } mode_laneset; 1191d448521eSAnthony Koo uint8_t lanenum; /**< Number of lanes */ 1192d448521eSAnthony Koo union { 1193d448521eSAnthony Koo uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1194d448521eSAnthony Koo } symclk_units; 1195d448521eSAnthony Koo uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1196d448521eSAnthony Koo uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1197d448521eSAnthony Koo uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 11985a2730fcSFangzhi Zuo uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1199d448521eSAnthony Koo uint8_t reserved1; /**< For future use */ 1200d448521eSAnthony Koo uint8_t reserved2[3]; /**< For future use */ 1201d448521eSAnthony Koo uint32_t reserved3[11]; /**< For future use */ 1202d448521eSAnthony Koo }; 1203d448521eSAnthony Koo 1204592a6318SAnthony Koo /** 1205592a6318SAnthony Koo * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1206592a6318SAnthony Koo */ 1207d448521eSAnthony Koo union dmub_cmd_dig1_transmitter_control_data { 1208592a6318SAnthony Koo struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1209592a6318SAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 12107c008829SNicholas Kazlauskas }; 12117c008829SNicholas Kazlauskas 1212592a6318SAnthony Koo /** 1213592a6318SAnthony Koo * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1214592a6318SAnthony Koo */ 12157c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control { 1216592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1217592a6318SAnthony Koo union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 12187c008829SNicholas Kazlauskas }; 12197c008829SNicholas Kazlauskas 1220592a6318SAnthony Koo /** 1221*e383b127SNicholas Kazlauskas * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1222*e383b127SNicholas Kazlauskas */ 1223*e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control_data { 1224*e383b127SNicholas Kazlauskas uint8_t inst : 6; /**< DOMAIN instance to control */ 1225*e383b127SNicholas Kazlauskas uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1226*e383b127SNicholas Kazlauskas uint8_t reserved[3]; /**< Reserved for future use */ 1227*e383b127SNicholas Kazlauskas }; 1228*e383b127SNicholas Kazlauskas 1229*e383b127SNicholas Kazlauskas /** 1230*e383b127SNicholas Kazlauskas * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1231*e383b127SNicholas Kazlauskas */ 1232*e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control { 1233*e383b127SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1234*e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1235*e383b127SNicholas Kazlauskas }; 1236*e383b127SNicholas Kazlauskas 1237*e383b127SNicholas Kazlauskas /** 123876724b76SJimmy Kizito * DPIA tunnel command parameters. 123976724b76SJimmy Kizito */ 124076724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data { 124176724b76SJimmy Kizito uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 124276724b76SJimmy Kizito uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 124376724b76SJimmy Kizito union { 124476724b76SJimmy Kizito uint8_t digmode; /** enum atom_encode_mode_def */ 124576724b76SJimmy Kizito uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 124676724b76SJimmy Kizito } mode_laneset; 124776724b76SJimmy Kizito uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 124876724b76SJimmy Kizito uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 124976724b76SJimmy Kizito uint8_t hpdsel; /** =0: HPD is not assigned */ 125076724b76SJimmy Kizito uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 125176724b76SJimmy Kizito uint8_t dpia_id; /** Index of DPIA */ 125276724b76SJimmy Kizito uint8_t fec_rdy : 1; 125376724b76SJimmy Kizito uint8_t reserved : 7; 125476724b76SJimmy Kizito uint32_t reserved1; 125576724b76SJimmy Kizito }; 125676724b76SJimmy Kizito 125776724b76SJimmy Kizito /** 125876724b76SJimmy Kizito * DMUB command for DPIA tunnel control. 125976724b76SJimmy Kizito */ 126076724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control { 126176724b76SJimmy Kizito struct dmub_cmd_header header; 126276724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data dpia_control; 126376724b76SJimmy Kizito }; 126476724b76SJimmy Kizito 126576724b76SJimmy Kizito /** 126671af9d46SMeenakshikumar Somasundaram * SET_CONFIG Command Payload 126771af9d46SMeenakshikumar Somasundaram */ 126871af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload { 126971af9d46SMeenakshikumar Somasundaram uint8_t msg_type; /* set config message type */ 127071af9d46SMeenakshikumar Somasundaram uint8_t msg_data; /* set config message data */ 127171af9d46SMeenakshikumar Somasundaram }; 127271af9d46SMeenakshikumar Somasundaram 127371af9d46SMeenakshikumar Somasundaram /** 127471af9d46SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 127571af9d46SMeenakshikumar Somasundaram */ 127671af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data { 127771af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload cmd_pkt; 127871af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */ 127971af9d46SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned in case of error */ 128071af9d46SMeenakshikumar Somasundaram }; 128171af9d46SMeenakshikumar Somasundaram 128271af9d46SMeenakshikumar Somasundaram /** 128371af9d46SMeenakshikumar Somasundaram * DMUB command structure for SET_CONFIG command. 128471af9d46SMeenakshikumar Somasundaram */ 128571af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access { 128671af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 128771af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 128871af9d46SMeenakshikumar Somasundaram }; 128971af9d46SMeenakshikumar Somasundaram 129071af9d46SMeenakshikumar Somasundaram /** 1291139a3311SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1292139a3311SMeenakshikumar Somasundaram */ 1293139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data { 1294139a3311SMeenakshikumar Somasundaram uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1295139a3311SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */ 1296139a3311SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1297139a3311SMeenakshikumar Somasundaram uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1298139a3311SMeenakshikumar Somasundaram }; 1299139a3311SMeenakshikumar Somasundaram 1300139a3311SMeenakshikumar Somasundaram /** 1301139a3311SMeenakshikumar Somasundaram * DMUB command structure for SET_ command. 1302139a3311SMeenakshikumar Somasundaram */ 1303139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots { 1304139a3311SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 1305139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1306139a3311SMeenakshikumar Somasundaram }; 1307139a3311SMeenakshikumar Somasundaram 1308139a3311SMeenakshikumar Somasundaram /** 13096f4f8ff5SMeenakshikumar Somasundaram * DMUB command structure for DPIA HPD int enable control. 13106f4f8ff5SMeenakshikumar Somasundaram */ 13116f4f8ff5SMeenakshikumar Somasundaram struct dmub_rb_cmd_dpia_hpd_int_enable { 13126f4f8ff5SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 13136f4f8ff5SMeenakshikumar Somasundaram uint32_t enable; /* dpia hpd interrupt enable */ 13146f4f8ff5SMeenakshikumar Somasundaram }; 13156f4f8ff5SMeenakshikumar Somasundaram 13166f4f8ff5SMeenakshikumar Somasundaram /** 1317592a6318SAnthony Koo * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1318592a6318SAnthony Koo */ 13197c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init { 1320592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1321592a6318SAnthony Koo uint8_t reserved[60]; /**< reserved bits */ 13227c008829SNicholas Kazlauskas }; 13237c008829SNicholas Kazlauskas 13241a595f28SAnthony Koo /** 13251a595f28SAnthony Koo * enum dp_aux_request_action - DP AUX request command listing. 13261a595f28SAnthony Koo * 13271a595f28SAnthony Koo * 4 AUX request command bits are shifted to high nibble. 13281a595f28SAnthony Koo */ 1329d9beecfcSAnthony Koo enum dp_aux_request_action { 13301a595f28SAnthony Koo /** I2C-over-AUX write request */ 1331d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 13321a595f28SAnthony Koo /** I2C-over-AUX read request */ 1333d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ = 0x10, 13341a595f28SAnthony Koo /** I2C-over-AUX write status request */ 1335d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 13361a595f28SAnthony Koo /** I2C-over-AUX write request with MOT=1 */ 1337d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 13381a595f28SAnthony Koo /** I2C-over-AUX read request with MOT=1 */ 1339d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 13401a595f28SAnthony Koo /** I2C-over-AUX write status request with MOT=1 */ 1341d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 13421a595f28SAnthony Koo /** Native AUX write request */ 1343d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 13441a595f28SAnthony Koo /** Native AUX read request */ 1345d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1346d9beecfcSAnthony Koo }; 1347d9beecfcSAnthony Koo 13481a595f28SAnthony Koo /** 13491a595f28SAnthony Koo * enum aux_return_code_type - DP AUX process return code listing. 13501a595f28SAnthony Koo */ 1351fd0f1d21SAnthony Koo enum aux_return_code_type { 13521a595f28SAnthony Koo /** AUX process succeeded */ 1353fd0f1d21SAnthony Koo AUX_RET_SUCCESS = 0, 13541a595f28SAnthony Koo /** AUX process failed with unknown reason */ 1355b6402afeSAnthony Koo AUX_RET_ERROR_UNKNOWN, 13561a595f28SAnthony Koo /** AUX process completed with invalid reply */ 1357b6402afeSAnthony Koo AUX_RET_ERROR_INVALID_REPLY, 13581a595f28SAnthony Koo /** AUX process timed out */ 1359fd0f1d21SAnthony Koo AUX_RET_ERROR_TIMEOUT, 13601a595f28SAnthony Koo /** HPD was low during AUX process */ 1361b6402afeSAnthony Koo AUX_RET_ERROR_HPD_DISCON, 13621a595f28SAnthony Koo /** Failed to acquire AUX engine */ 1363b6402afeSAnthony Koo AUX_RET_ERROR_ENGINE_ACQUIRE, 13641a595f28SAnthony Koo /** AUX request not supported */ 1365fd0f1d21SAnthony Koo AUX_RET_ERROR_INVALID_OPERATION, 13661a595f28SAnthony Koo /** AUX process not available */ 1367fd0f1d21SAnthony Koo AUX_RET_ERROR_PROTOCOL_ERROR, 1368fd0f1d21SAnthony Koo }; 1369fd0f1d21SAnthony Koo 13701a595f28SAnthony Koo /** 13711a595f28SAnthony Koo * enum aux_channel_type - DP AUX channel type listing. 13721a595f28SAnthony Koo */ 1373b6402afeSAnthony Koo enum aux_channel_type { 13741a595f28SAnthony Koo /** AUX thru Legacy DP AUX */ 1375b6402afeSAnthony Koo AUX_CHANNEL_LEGACY_DDC, 13761a595f28SAnthony Koo /** AUX thru DPIA DP tunneling */ 1377b6402afeSAnthony Koo AUX_CHANNEL_DPIA 1378b6402afeSAnthony Koo }; 1379b6402afeSAnthony Koo 13801a595f28SAnthony Koo /** 13811a595f28SAnthony Koo * struct aux_transaction_parameters - DP AUX request transaction data 13821a595f28SAnthony Koo */ 1383d9beecfcSAnthony Koo struct aux_transaction_parameters { 13841a595f28SAnthony Koo uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 13851a595f28SAnthony Koo uint8_t action; /**< enum dp_aux_request_action */ 13861a595f28SAnthony Koo uint8_t length; /**< DP AUX request data length */ 13871a595f28SAnthony Koo uint8_t reserved; /**< For future use */ 13881a595f28SAnthony Koo uint32_t address; /**< DP AUX address */ 13891a595f28SAnthony Koo uint8_t data[16]; /**< DP AUX write data */ 1390d9beecfcSAnthony Koo }; 1391d9beecfcSAnthony Koo 13921a595f28SAnthony Koo /** 13931a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 13941a595f28SAnthony Koo */ 1395d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data { 13961a595f28SAnthony Koo uint8_t instance; /**< AUX instance or DPIA instance */ 13971a595f28SAnthony Koo uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 13981a595f28SAnthony Koo uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 13991a595f28SAnthony Koo uint8_t reserved0; /**< For future use */ 14001a595f28SAnthony Koo uint16_t timeout; /**< timeout time in us */ 14011a595f28SAnthony Koo uint16_t reserved1; /**< For future use */ 14021a595f28SAnthony Koo enum aux_channel_type type; /**< enum aux_channel_type */ 14031a595f28SAnthony Koo struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1404d9beecfcSAnthony Koo }; 1405d9beecfcSAnthony Koo 14061a595f28SAnthony Koo /** 14071a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 14081a595f28SAnthony Koo */ 1409d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access { 14101a595f28SAnthony Koo /** 14111a595f28SAnthony Koo * Command header. 14121a595f28SAnthony Koo */ 1413d9beecfcSAnthony Koo struct dmub_cmd_header header; 14141a595f28SAnthony Koo /** 14151a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 14161a595f28SAnthony Koo */ 1417d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data aux_control; 1418d9beecfcSAnthony Koo }; 1419d9beecfcSAnthony Koo 14201a595f28SAnthony Koo /** 14211a595f28SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 14221a595f28SAnthony Koo */ 1423d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable { 14241a595f28SAnthony Koo /** 14251a595f28SAnthony Koo * Command header. 14261a595f28SAnthony Koo */ 1427d9beecfcSAnthony Koo struct dmub_cmd_header header; 14281a595f28SAnthony Koo /** 14291a595f28SAnthony Koo * enable: 0x0 -> disable outbox1 notification (default value) 14301a595f28SAnthony Koo * 0x1 -> enable outbox1 notification 14311a595f28SAnthony Koo */ 1432d9beecfcSAnthony Koo uint32_t enable; 1433d9beecfcSAnthony Koo }; 1434d9beecfcSAnthony Koo 1435d9beecfcSAnthony Koo /* DP AUX Reply command - OutBox Cmd */ 14361a595f28SAnthony Koo /** 14371a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14381a595f28SAnthony Koo */ 1439d9beecfcSAnthony Koo struct aux_reply_data { 14401a595f28SAnthony Koo /** 14411a595f28SAnthony Koo * Aux cmd 14421a595f28SAnthony Koo */ 1443d9beecfcSAnthony Koo uint8_t command; 14441a595f28SAnthony Koo /** 14451a595f28SAnthony Koo * Aux reply data length (max: 16 bytes) 14461a595f28SAnthony Koo */ 1447d9beecfcSAnthony Koo uint8_t length; 14481a595f28SAnthony Koo /** 14491a595f28SAnthony Koo * Alignment only 14501a595f28SAnthony Koo */ 1451d9beecfcSAnthony Koo uint8_t pad[2]; 14521a595f28SAnthony Koo /** 14531a595f28SAnthony Koo * Aux reply data 14541a595f28SAnthony Koo */ 1455d9beecfcSAnthony Koo uint8_t data[16]; 1456d9beecfcSAnthony Koo }; 1457d9beecfcSAnthony Koo 14581a595f28SAnthony Koo /** 14591a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14601a595f28SAnthony Koo */ 1461d9beecfcSAnthony Koo struct aux_reply_control_data { 14621a595f28SAnthony Koo /** 14631a595f28SAnthony Koo * Reserved for future use 14641a595f28SAnthony Koo */ 1465d9beecfcSAnthony Koo uint32_t handle; 14661a595f28SAnthony Koo /** 14671a595f28SAnthony Koo * Aux Instance 14681a595f28SAnthony Koo */ 1469b6402afeSAnthony Koo uint8_t instance; 14701a595f28SAnthony Koo /** 14711a595f28SAnthony Koo * Aux transaction result: definition in enum aux_return_code_type 14721a595f28SAnthony Koo */ 1473d9beecfcSAnthony Koo uint8_t result; 14741a595f28SAnthony Koo /** 14751a595f28SAnthony Koo * Alignment only 14761a595f28SAnthony Koo */ 1477d9beecfcSAnthony Koo uint16_t pad; 1478d9beecfcSAnthony Koo }; 1479d9beecfcSAnthony Koo 14801a595f28SAnthony Koo /** 14811a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 14821a595f28SAnthony Koo */ 1483d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply { 14841a595f28SAnthony Koo /** 14851a595f28SAnthony Koo * Command header. 14861a595f28SAnthony Koo */ 1487d9beecfcSAnthony Koo struct dmub_cmd_header header; 14881a595f28SAnthony Koo /** 14891a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14901a595f28SAnthony Koo */ 1491d9beecfcSAnthony Koo struct aux_reply_control_data control; 14921a595f28SAnthony Koo /** 14931a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14941a595f28SAnthony Koo */ 1495d9beecfcSAnthony Koo struct aux_reply_data reply_data; 1496d9beecfcSAnthony Koo }; 1497d9beecfcSAnthony Koo 1498fd0f1d21SAnthony Koo /* DP HPD Notify command - OutBox Cmd */ 14991a595f28SAnthony Koo /** 15001a595f28SAnthony Koo * DP HPD Type 15011a595f28SAnthony Koo */ 1502fd0f1d21SAnthony Koo enum dp_hpd_type { 15031a595f28SAnthony Koo /** 15041a595f28SAnthony Koo * Normal DP HPD 15051a595f28SAnthony Koo */ 1506fd0f1d21SAnthony Koo DP_HPD = 0, 15071a595f28SAnthony Koo /** 15081a595f28SAnthony Koo * DP HPD short pulse 15091a595f28SAnthony Koo */ 1510fd0f1d21SAnthony Koo DP_IRQ 1511fd0f1d21SAnthony Koo }; 1512fd0f1d21SAnthony Koo 15131a595f28SAnthony Koo /** 15141a595f28SAnthony Koo * DP HPD Status 15151a595f28SAnthony Koo */ 1516fd0f1d21SAnthony Koo enum dp_hpd_status { 15171a595f28SAnthony Koo /** 15181a595f28SAnthony Koo * DP_HPD status low 15191a595f28SAnthony Koo */ 1520fd0f1d21SAnthony Koo DP_HPD_UNPLUG = 0, 15211a595f28SAnthony Koo /** 15221a595f28SAnthony Koo * DP_HPD status high 15231a595f28SAnthony Koo */ 1524fd0f1d21SAnthony Koo DP_HPD_PLUG 1525fd0f1d21SAnthony Koo }; 1526fd0f1d21SAnthony Koo 15271a595f28SAnthony Koo /** 15281a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 15291a595f28SAnthony Koo */ 1530d9beecfcSAnthony Koo struct dp_hpd_data { 15311a595f28SAnthony Koo /** 15321a595f28SAnthony Koo * DP HPD instance 15331a595f28SAnthony Koo */ 1534b6402afeSAnthony Koo uint8_t instance; 15351a595f28SAnthony Koo /** 15361a595f28SAnthony Koo * HPD type 15371a595f28SAnthony Koo */ 1538d9beecfcSAnthony Koo uint8_t hpd_type; 15391a595f28SAnthony Koo /** 15401a595f28SAnthony Koo * HPD status: only for type: DP_HPD to indicate status 15411a595f28SAnthony Koo */ 1542d9beecfcSAnthony Koo uint8_t hpd_status; 15431a595f28SAnthony Koo /** 15441a595f28SAnthony Koo * Alignment only 15451a595f28SAnthony Koo */ 1546d9beecfcSAnthony Koo uint8_t pad; 1547d9beecfcSAnthony Koo }; 1548d9beecfcSAnthony Koo 15491a595f28SAnthony Koo /** 15501a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 15511a595f28SAnthony Koo */ 1552d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify { 15531a595f28SAnthony Koo /** 15541a595f28SAnthony Koo * Command header. 15551a595f28SAnthony Koo */ 1556d9beecfcSAnthony Koo struct dmub_cmd_header header; 15571a595f28SAnthony Koo /** 15581a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 15591a595f28SAnthony Koo */ 1560d9beecfcSAnthony Koo struct dp_hpd_data hpd_data; 1561d9beecfcSAnthony Koo }; 1562d9beecfcSAnthony Koo 156371af9d46SMeenakshikumar Somasundaram /** 156471af9d46SMeenakshikumar Somasundaram * Definition of a SET_CONFIG reply from DPOA. 156571af9d46SMeenakshikumar Somasundaram */ 156671af9d46SMeenakshikumar Somasundaram enum set_config_status { 156771af9d46SMeenakshikumar Somasundaram SET_CONFIG_PENDING = 0, 156871af9d46SMeenakshikumar Somasundaram SET_CONFIG_ACK_RECEIVED, 156971af9d46SMeenakshikumar Somasundaram SET_CONFIG_RX_TIMEOUT, 157071af9d46SMeenakshikumar Somasundaram SET_CONFIG_UNKNOWN_ERROR, 157171af9d46SMeenakshikumar Somasundaram }; 157271af9d46SMeenakshikumar Somasundaram 157371af9d46SMeenakshikumar Somasundaram /** 157471af9d46SMeenakshikumar Somasundaram * Definition of a set_config reply 157571af9d46SMeenakshikumar Somasundaram */ 157671af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data { 157771af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA Instance */ 157871af9d46SMeenakshikumar Somasundaram uint8_t status; /* Set Config reply */ 157971af9d46SMeenakshikumar Somasundaram uint16_t pad; /* Alignment */ 158071af9d46SMeenakshikumar Somasundaram }; 158171af9d46SMeenakshikumar Somasundaram 158271af9d46SMeenakshikumar Somasundaram /** 158371af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 158471af9d46SMeenakshikumar Somasundaram */ 158571af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply { 158671af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; 158771af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data set_config_reply_control; 158871af9d46SMeenakshikumar Somasundaram }; 158971af9d46SMeenakshikumar Somasundaram 1590ea5a4db9SAnthony Koo /** 15918af54c61SMustapha Ghaddar * Definition of a DPIA notification header 15928af54c61SMustapha Ghaddar */ 15938af54c61SMustapha Ghaddar struct dpia_notification_header { 15948af54c61SMustapha Ghaddar uint8_t instance; /**< DPIA Instance */ 15958af54c61SMustapha Ghaddar uint8_t reserved[3]; 15968af54c61SMustapha Ghaddar enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 15978af54c61SMustapha Ghaddar }; 15988af54c61SMustapha Ghaddar 15998af54c61SMustapha Ghaddar /** 16008af54c61SMustapha Ghaddar * Definition of the common data struct of DPIA notification 16018af54c61SMustapha Ghaddar */ 16028af54c61SMustapha Ghaddar struct dpia_notification_common { 16038af54c61SMustapha Ghaddar uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 16048af54c61SMustapha Ghaddar - sizeof(struct dpia_notification_header)]; 16058af54c61SMustapha Ghaddar }; 16068af54c61SMustapha Ghaddar 16078af54c61SMustapha Ghaddar /** 16088af54c61SMustapha Ghaddar * Definition of a DPIA notification data 16098af54c61SMustapha Ghaddar */ 16108af54c61SMustapha Ghaddar struct dpia_bw_allocation_notify_data { 16118af54c61SMustapha Ghaddar union { 16128af54c61SMustapha Ghaddar struct { 16138af54c61SMustapha Ghaddar uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 16148af54c61SMustapha Ghaddar uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 16158af54c61SMustapha Ghaddar uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 16168af54c61SMustapha Ghaddar uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 16178af54c61SMustapha Ghaddar uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 16188af54c61SMustapha Ghaddar uint16_t reserved: 11; /**< Reserved */ 16198af54c61SMustapha Ghaddar } bits; 16208af54c61SMustapha Ghaddar 16218af54c61SMustapha Ghaddar uint16_t flags; 16228af54c61SMustapha Ghaddar }; 16238af54c61SMustapha Ghaddar 16248af54c61SMustapha Ghaddar uint8_t cm_id; /**< CM ID */ 16258af54c61SMustapha Ghaddar uint8_t group_id; /**< Group ID */ 16268af54c61SMustapha Ghaddar uint8_t granularity; /**< BW Allocation Granularity */ 16278af54c61SMustapha Ghaddar uint8_t estimated_bw; /**< Estimated_BW */ 16288af54c61SMustapha Ghaddar uint8_t allocated_bw; /**< Allocated_BW */ 16298af54c61SMustapha Ghaddar uint8_t reserved; 16308af54c61SMustapha Ghaddar }; 16318af54c61SMustapha Ghaddar 16328af54c61SMustapha Ghaddar /** 16338af54c61SMustapha Ghaddar * union dpia_notify_data_type - DPIA Notification in Outbox command 16348af54c61SMustapha Ghaddar */ 16358af54c61SMustapha Ghaddar union dpia_notification_data { 16368af54c61SMustapha Ghaddar /** 16378af54c61SMustapha Ghaddar * DPIA Notification for common data struct 16388af54c61SMustapha Ghaddar */ 16398af54c61SMustapha Ghaddar struct dpia_notification_common common_data; 16408af54c61SMustapha Ghaddar 16418af54c61SMustapha Ghaddar /** 16428af54c61SMustapha Ghaddar * DPIA Notification for DP BW Allocation support 16438af54c61SMustapha Ghaddar */ 16448af54c61SMustapha Ghaddar struct dpia_bw_allocation_notify_data dpia_bw_alloc; 16458af54c61SMustapha Ghaddar }; 16468af54c61SMustapha Ghaddar 16478af54c61SMustapha Ghaddar /** 16488af54c61SMustapha Ghaddar * Definition of a DPIA notification payload 16498af54c61SMustapha Ghaddar */ 16508af54c61SMustapha Ghaddar struct dpia_notification_payload { 16518af54c61SMustapha Ghaddar struct dpia_notification_header header; 16528af54c61SMustapha Ghaddar union dpia_notification_data data; /**< DPIA notification payload data */ 16538af54c61SMustapha Ghaddar }; 16548af54c61SMustapha Ghaddar 16558af54c61SMustapha Ghaddar /** 16568af54c61SMustapha Ghaddar * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 16578af54c61SMustapha Ghaddar */ 16588af54c61SMustapha Ghaddar struct dmub_rb_cmd_dpia_notification { 16598af54c61SMustapha Ghaddar struct dmub_cmd_header header; /**< DPIA notification header */ 16608af54c61SMustapha Ghaddar struct dpia_notification_payload payload; /**< DPIA notification payload */ 16618af54c61SMustapha Ghaddar }; 16628af54c61SMustapha Ghaddar 16638af54c61SMustapha Ghaddar /** 1664ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1665ea5a4db9SAnthony Koo */ 1666ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data { 1667ea5a4db9SAnthony Koo uint8_t instance; /**< HPD instance or DPIA instance */ 1668ea5a4db9SAnthony Koo uint8_t result; /**< For returning HPD state */ 1669874714feSAnthony Koo uint16_t pad; /** < Alignment */ 1670ea5a4db9SAnthony Koo enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1671ea5a4db9SAnthony Koo enum aux_return_code_type status; /**< for returning the status of command */ 1672ea5a4db9SAnthony Koo }; 1673ea5a4db9SAnthony Koo 1674ea5a4db9SAnthony Koo /** 1675ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1676ea5a4db9SAnthony Koo */ 1677ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state { 1678ea5a4db9SAnthony Koo /** 1679ea5a4db9SAnthony Koo * Command header. 1680ea5a4db9SAnthony Koo */ 1681ea5a4db9SAnthony Koo struct dmub_cmd_header header; 1682ea5a4db9SAnthony Koo /** 1683ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1684ea5a4db9SAnthony Koo */ 1685ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data data; 1686ea5a4db9SAnthony Koo }; 1687ea5a4db9SAnthony Koo 168884034ad4SAnthony Koo /* 168984034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 169084034ad4SAnthony Koo * Do not reuse or modify IDs. 169184034ad4SAnthony Koo */ 169284034ad4SAnthony Koo 16931a595f28SAnthony Koo /** 16941a595f28SAnthony Koo * PSR command sub-types. 16951a595f28SAnthony Koo */ 169684034ad4SAnthony Koo enum dmub_cmd_psr_type { 16971a595f28SAnthony Koo /** 16981a595f28SAnthony Koo * Set PSR version support. 16991a595f28SAnthony Koo */ 170084034ad4SAnthony Koo DMUB_CMD__PSR_SET_VERSION = 0, 17011a595f28SAnthony Koo /** 17021a595f28SAnthony Koo * Copy driver-calculated parameters to PSR state. 17031a595f28SAnthony Koo */ 170484034ad4SAnthony Koo DMUB_CMD__PSR_COPY_SETTINGS = 1, 17051a595f28SAnthony Koo /** 17061a595f28SAnthony Koo * Enable PSR. 17071a595f28SAnthony Koo */ 170884034ad4SAnthony Koo DMUB_CMD__PSR_ENABLE = 2, 17091a595f28SAnthony Koo 17101a595f28SAnthony Koo /** 17111a595f28SAnthony Koo * Disable PSR. 17121a595f28SAnthony Koo */ 171384034ad4SAnthony Koo DMUB_CMD__PSR_DISABLE = 3, 17141a595f28SAnthony Koo 17151a595f28SAnthony Koo /** 17161a595f28SAnthony Koo * Set PSR level. 17171a595f28SAnthony Koo * PSR level is a 16-bit value dicated by driver that 17181a595f28SAnthony Koo * will enable/disable different functionality. 17191a595f28SAnthony Koo */ 172084034ad4SAnthony Koo DMUB_CMD__PSR_SET_LEVEL = 4, 17211a595f28SAnthony Koo 17221a595f28SAnthony Koo /** 17231a595f28SAnthony Koo * Forces PSR enabled until an explicit PSR disable call. 17241a595f28SAnthony Koo */ 1725672251b2SAnthony Koo DMUB_CMD__PSR_FORCE_STATIC = 5, 1726e5dfcd27SRobin Chen /** 172783eb5385SDavid Zhang * Set vtotal in psr active for FreeSync PSR. 172883eb5385SDavid Zhang */ 172983eb5385SDavid Zhang DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 173083eb5385SDavid Zhang /** 1731e5dfcd27SRobin Chen * Set PSR power option 1732e5dfcd27SRobin Chen */ 1733e5dfcd27SRobin Chen DMUB_CMD__SET_PSR_POWER_OPT = 7, 173484034ad4SAnthony Koo }; 173584034ad4SAnthony Koo 173685f4bc0cSAlvin Lee enum dmub_cmd_fams_type { 173785f4bc0cSAlvin Lee DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 173885f4bc0cSAlvin Lee DMUB_CMD__FAMS_DRR_UPDATE = 1, 173985f4bc0cSAlvin Lee DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 174081f776b6SAnthony Koo /** 174181f776b6SAnthony Koo * For SubVP set manual trigger in FW because it 174281f776b6SAnthony Koo * triggers DRR_UPDATE_PENDING which SubVP relies 174381f776b6SAnthony Koo * on (for any SubVP cases that use a DRR display) 174481f776b6SAnthony Koo */ 174581f776b6SAnthony Koo DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 174685f4bc0cSAlvin Lee }; 174785f4bc0cSAlvin Lee 17481a595f28SAnthony Koo /** 17491a595f28SAnthony Koo * PSR versions. 17501a595f28SAnthony Koo */ 175184034ad4SAnthony Koo enum psr_version { 17521a595f28SAnthony Koo /** 17531a595f28SAnthony Koo * PSR version 1. 17541a595f28SAnthony Koo */ 175584034ad4SAnthony Koo PSR_VERSION_1 = 0, 17561a595f28SAnthony Koo /** 175783eb5385SDavid Zhang * Freesync PSR SU. 175883eb5385SDavid Zhang */ 175983eb5385SDavid Zhang PSR_VERSION_SU_1 = 1, 176083eb5385SDavid Zhang /** 17611a595f28SAnthony Koo * PSR not supported. 17621a595f28SAnthony Koo */ 176384034ad4SAnthony Koo PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 176484034ad4SAnthony Koo }; 176584034ad4SAnthony Koo 1766592a6318SAnthony Koo /** 1767592a6318SAnthony Koo * enum dmub_cmd_mall_type - MALL commands 1768592a6318SAnthony Koo */ 176952f2e83eSBhawanpreet Lakha enum dmub_cmd_mall_type { 1770592a6318SAnthony Koo /** 1771592a6318SAnthony Koo * Allows display refresh from MALL. 1772592a6318SAnthony Koo */ 177352f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_ALLOW = 0, 1774592a6318SAnthony Koo /** 1775592a6318SAnthony Koo * Disallows display refresh from MALL. 1776592a6318SAnthony Koo */ 177752f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1778592a6318SAnthony Koo /** 1779592a6318SAnthony Koo * Cursor copy for MALL. 1780592a6318SAnthony Koo */ 178152f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1782592a6318SAnthony Koo /** 1783592a6318SAnthony Koo * Controls DF requests. 1784592a6318SAnthony Koo */ 1785ea7154d8SBhawanpreet Lakha DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 178652f2e83eSBhawanpreet Lakha }; 178752f2e83eSBhawanpreet Lakha 1788a91b402dSCharlene Liu /** 178978174f47SAnthony Koo * PHY Link rate for DP. 179078174f47SAnthony Koo */ 179178174f47SAnthony Koo enum phy_link_rate { 179278174f47SAnthony Koo /** 179378174f47SAnthony Koo * not supported. 179478174f47SAnthony Koo */ 179578174f47SAnthony Koo PHY_RATE_UNKNOWN = 0, 179678174f47SAnthony Koo /** 179778174f47SAnthony Koo * Rate_1 (RBR) - 1.62 Gbps/Lane 179878174f47SAnthony Koo */ 179978174f47SAnthony Koo PHY_RATE_162 = 1, 180078174f47SAnthony Koo /** 180178174f47SAnthony Koo * Rate_2 - 2.16 Gbps/Lane 180278174f47SAnthony Koo */ 180378174f47SAnthony Koo PHY_RATE_216 = 2, 180478174f47SAnthony Koo /** 180578174f47SAnthony Koo * Rate_3 - 2.43 Gbps/Lane 180678174f47SAnthony Koo */ 180778174f47SAnthony Koo PHY_RATE_243 = 3, 180878174f47SAnthony Koo /** 180978174f47SAnthony Koo * Rate_4 (HBR) - 2.70 Gbps/Lane 181078174f47SAnthony Koo */ 181178174f47SAnthony Koo PHY_RATE_270 = 4, 181278174f47SAnthony Koo /** 181378174f47SAnthony Koo * Rate_5 (RBR2)- 3.24 Gbps/Lane 181478174f47SAnthony Koo */ 181578174f47SAnthony Koo PHY_RATE_324 = 5, 181678174f47SAnthony Koo /** 181778174f47SAnthony Koo * Rate_6 - 4.32 Gbps/Lane 181878174f47SAnthony Koo */ 181978174f47SAnthony Koo PHY_RATE_432 = 6, 182078174f47SAnthony Koo /** 182178174f47SAnthony Koo * Rate_7 (HBR2)- 5.40 Gbps/Lane 182278174f47SAnthony Koo */ 182378174f47SAnthony Koo PHY_RATE_540 = 7, 182478174f47SAnthony Koo /** 182578174f47SAnthony Koo * Rate_8 (HBR3)- 8.10 Gbps/Lane 182678174f47SAnthony Koo */ 182778174f47SAnthony Koo PHY_RATE_810 = 8, 182878174f47SAnthony Koo /** 182978174f47SAnthony Koo * UHBR10 - 10.0 Gbps/Lane 183078174f47SAnthony Koo */ 183178174f47SAnthony Koo PHY_RATE_1000 = 9, 183278174f47SAnthony Koo /** 183378174f47SAnthony Koo * UHBR13.5 - 13.5 Gbps/Lane 183478174f47SAnthony Koo */ 183578174f47SAnthony Koo PHY_RATE_1350 = 10, 183678174f47SAnthony Koo /** 183778174f47SAnthony Koo * UHBR10 - 20.0 Gbps/Lane 183878174f47SAnthony Koo */ 183978174f47SAnthony Koo PHY_RATE_2000 = 11, 184078174f47SAnthony Koo }; 184178174f47SAnthony Koo 184278174f47SAnthony Koo /** 184378174f47SAnthony Koo * enum dmub_phy_fsm_state - PHY FSM states. 184478174f47SAnthony Koo * PHY FSM state to transit to during PSR enable/disable. 184578174f47SAnthony Koo */ 184678174f47SAnthony Koo enum dmub_phy_fsm_state { 184778174f47SAnthony Koo DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 184878174f47SAnthony Koo DMUB_PHY_FSM_RESET, 184978174f47SAnthony Koo DMUB_PHY_FSM_RESET_RELEASED, 185078174f47SAnthony Koo DMUB_PHY_FSM_SRAM_LOAD_DONE, 185178174f47SAnthony Koo DMUB_PHY_FSM_INITIALIZED, 185278174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED, 185378174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_LP, 185478174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_PG, 185578174f47SAnthony Koo DMUB_PHY_FSM_POWER_DOWN, 185678174f47SAnthony Koo DMUB_PHY_FSM_PLL_EN, 185778174f47SAnthony Koo DMUB_PHY_FSM_TX_EN, 185878174f47SAnthony Koo DMUB_PHY_FSM_FAST_LP, 185978174f47SAnthony Koo }; 186078174f47SAnthony Koo 186178174f47SAnthony Koo /** 18621a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 18631a595f28SAnthony Koo */ 18647c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data { 18651a595f28SAnthony Koo /** 18661a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 18671a595f28SAnthony Koo */ 18687b8a6362SAnthony Koo union dmub_psr_debug_flags debug; 18691a595f28SAnthony Koo /** 18701a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 18711a595f28SAnthony Koo */ 18724c1a1335SWyatt Wood uint16_t psr_level; 18731a595f28SAnthony Koo /** 18741a595f28SAnthony Koo * DPP HW instance. 18751a595f28SAnthony Koo */ 18764c1a1335SWyatt Wood uint8_t dpp_inst; 18771a595f28SAnthony Koo /** 18781a595f28SAnthony Koo * MPCC HW instance. 18791a595f28SAnthony Koo * Not used in dmub fw, 188034ba432cSAnthony Koo * dmub fw will get active opp by reading odm registers. 188134ba432cSAnthony Koo */ 18824c1a1335SWyatt Wood uint8_t mpcc_inst; 18831a595f28SAnthony Koo /** 18841a595f28SAnthony Koo * OPP HW instance. 18851a595f28SAnthony Koo * Not used in dmub fw, 18861a595f28SAnthony Koo * dmub fw will get active opp by reading odm registers. 18871a595f28SAnthony Koo */ 18884c1a1335SWyatt Wood uint8_t opp_inst; 18891a595f28SAnthony Koo /** 18901a595f28SAnthony Koo * OTG HW instance. 18911a595f28SAnthony Koo */ 18924c1a1335SWyatt Wood uint8_t otg_inst; 18931a595f28SAnthony Koo /** 18941a595f28SAnthony Koo * DIG FE HW instance. 18951a595f28SAnthony Koo */ 18964c1a1335SWyatt Wood uint8_t digfe_inst; 18971a595f28SAnthony Koo /** 18981a595f28SAnthony Koo * DIG BE HW instance. 18991a595f28SAnthony Koo */ 19004c1a1335SWyatt Wood uint8_t digbe_inst; 19011a595f28SAnthony Koo /** 19021a595f28SAnthony Koo * DP PHY HW instance. 19031a595f28SAnthony Koo */ 19044c1a1335SWyatt Wood uint8_t dpphy_inst; 19051a595f28SAnthony Koo /** 19061a595f28SAnthony Koo * AUX HW instance. 19071a595f28SAnthony Koo */ 19084c1a1335SWyatt Wood uint8_t aux_inst; 19091a595f28SAnthony Koo /** 19101a595f28SAnthony Koo * Determines if SMU optimzations are enabled/disabled. 19111a595f28SAnthony Koo */ 19124c1a1335SWyatt Wood uint8_t smu_optimizations_en; 19131a595f28SAnthony Koo /** 19141a595f28SAnthony Koo * Unused. 19151a595f28SAnthony Koo * TODO: Remove. 19161a595f28SAnthony Koo */ 19174c1a1335SWyatt Wood uint8_t frame_delay; 19181a595f28SAnthony Koo /** 19191a595f28SAnthony Koo * If RFB setup time is greater than the total VBLANK time, 19201a595f28SAnthony Koo * it is not possible for the sink to capture the video frame 19211a595f28SAnthony Koo * in the same frame the SDP is sent. In this case, 19221a595f28SAnthony Koo * the frame capture indication bit should be set and an extra 19231a595f28SAnthony Koo * static frame should be transmitted to the sink. 19241a595f28SAnthony Koo */ 19254c1a1335SWyatt Wood uint8_t frame_cap_ind; 19261a595f28SAnthony Koo /** 192783eb5385SDavid Zhang * Granularity of Y offset supported by sink. 19281a595f28SAnthony Koo */ 192983eb5385SDavid Zhang uint8_t su_y_granularity; 193083eb5385SDavid Zhang /** 193183eb5385SDavid Zhang * Indicates whether sink should start capturing 193283eb5385SDavid Zhang * immediately following active scan line, 193383eb5385SDavid Zhang * or starting with the 2nd active scan line. 193483eb5385SDavid Zhang */ 193583eb5385SDavid Zhang uint8_t line_capture_indication; 19361a595f28SAnthony Koo /** 19371a595f28SAnthony Koo * Multi-display optimizations are implemented on certain ASICs. 19381a595f28SAnthony Koo */ 1939175f0971SYongqiang Sun uint8_t multi_disp_optimizations_en; 19401a595f28SAnthony Koo /** 19411a595f28SAnthony Koo * The last possible line SDP may be transmitted without violating 19421a595f28SAnthony Koo * the RFB setup time or entering the active video frame. 19431a595f28SAnthony Koo */ 194478ead771SAnthony Koo uint16_t init_sdp_deadline; 19451a595f28SAnthony Koo /** 194683eb5385SDavid Zhang * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 19471a595f28SAnthony Koo */ 194883eb5385SDavid Zhang uint8_t rate_control_caps ; 194983eb5385SDavid Zhang /* 195083eb5385SDavid Zhang * Force PSRSU always doing full frame update 195183eb5385SDavid Zhang */ 195283eb5385SDavid Zhang uint8_t force_ffu_mode; 19531a595f28SAnthony Koo /** 19541a595f28SAnthony Koo * Length of each horizontal line in us. 19551a595f28SAnthony Koo */ 19569b56f6bcSAnthony Koo uint32_t line_time_in_us; 1957ecc11601SAnthony Koo /** 1958ecc11601SAnthony Koo * FEC enable status in driver 1959ecc11601SAnthony Koo */ 1960ecc11601SAnthony Koo uint8_t fec_enable_status; 1961ecc11601SAnthony Koo /** 1962ecc11601SAnthony Koo * FEC re-enable delay when PSR exit. 1963ecc11601SAnthony Koo * unit is 100us, range form 0~255(0xFF). 1964ecc11601SAnthony Koo */ 1965ecc11601SAnthony Koo uint8_t fec_enable_delay_in100us; 1966ecc11601SAnthony Koo /** 1967f56c837aSMikita Lipski * PSR control version. 1968ecc11601SAnthony Koo */ 1969f56c837aSMikita Lipski uint8_t cmd_version; 1970f56c837aSMikita Lipski /** 1971f56c837aSMikita Lipski * Panel Instance. 1972f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1973f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1974f56c837aSMikita Lipski */ 1975f56c837aSMikita Lipski uint8_t panel_inst; 19762665f63aSMikita Lipski /* 19772665f63aSMikita Lipski * DSC enable status in driver 1978360d1b65SIan Chen */ 19792665f63aSMikita Lipski uint8_t dsc_enable_status; 1980b5175966SShah Dharati /* 1981b5175966SShah Dharati * Use FSM state for PSR power up/down 19822665f63aSMikita Lipski */ 1983b5175966SShah Dharati uint8_t use_phy_fsm; 1984b5175966SShah Dharati /** 19851a2b886bSRyan Lin * frame delay for frame re-lock 19861a2b886bSRyan Lin */ 19871a2b886bSRyan Lin uint8_t relock_delay_frame_cnt; 19881a2b886bSRyan Lin /** 1989b5175966SShah Dharati * Explicit padding to 2 byte boundary. 1990b5175966SShah Dharati */ 19911a2b886bSRyan Lin uint8_t pad3; 1992c84ff24aSRobin Chen /** 1993c84ff24aSRobin Chen * DSC Slice height. 1994c84ff24aSRobin Chen */ 1995c84ff24aSRobin Chen uint16_t dsc_slice_height; 1996c84ff24aSRobin Chen /** 1997c84ff24aSRobin Chen * Explicit padding to 4 byte boundary. 1998c84ff24aSRobin Chen */ 1999c84ff24aSRobin Chen uint16_t pad; 20007c008829SNicholas Kazlauskas }; 20017c008829SNicholas Kazlauskas 20021a595f28SAnthony Koo /** 20031a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 20041a595f28SAnthony Koo */ 20057c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings { 20061a595f28SAnthony Koo /** 20071a595f28SAnthony Koo * Command header. 20081a595f28SAnthony Koo */ 20097c008829SNicholas Kazlauskas struct dmub_cmd_header header; 20101a595f28SAnthony Koo /** 20111a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 20121a595f28SAnthony Koo */ 20137c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 20147c008829SNicholas Kazlauskas }; 20157c008829SNicholas Kazlauskas 20161a595f28SAnthony Koo /** 20171a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 20181a595f28SAnthony Koo */ 20197c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data { 20201a595f28SAnthony Koo /** 20211a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 20221a595f28SAnthony Koo */ 20237c008829SNicholas Kazlauskas uint16_t psr_level; 20241a595f28SAnthony Koo /** 2025f56c837aSMikita Lipski * PSR control version. 20261a595f28SAnthony Koo */ 2027f56c837aSMikita Lipski uint8_t cmd_version; 2028f56c837aSMikita Lipski /** 2029f56c837aSMikita Lipski * Panel Instance. 2030f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 2031f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2032f56c837aSMikita Lipski */ 2033f56c837aSMikita Lipski uint8_t panel_inst; 20347c008829SNicholas Kazlauskas }; 20357c008829SNicholas Kazlauskas 20361a595f28SAnthony Koo /** 20371a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 20381a595f28SAnthony Koo */ 20397c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level { 20401a595f28SAnthony Koo /** 20411a595f28SAnthony Koo * Command header. 20421a595f28SAnthony Koo */ 20437c008829SNicholas Kazlauskas struct dmub_cmd_header header; 20441a595f28SAnthony Koo /** 20451a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 20461a595f28SAnthony Koo */ 20477c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data psr_set_level_data; 20487c008829SNicholas Kazlauskas }; 20497c008829SNicholas Kazlauskas 2050f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data { 2051f56c837aSMikita Lipski /** 2052f56c837aSMikita Lipski * PSR control version. 2053f56c837aSMikita Lipski */ 2054f56c837aSMikita Lipski uint8_t cmd_version; 2055f56c837aSMikita Lipski /** 2056f56c837aSMikita Lipski * Panel Instance. 2057f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 2058f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2059f56c837aSMikita Lipski */ 2060f56c837aSMikita Lipski uint8_t panel_inst; 2061f56c837aSMikita Lipski /** 206278174f47SAnthony Koo * Phy state to enter. 206378174f47SAnthony Koo * Values to use are defined in dmub_phy_fsm_state 2064f56c837aSMikita Lipski */ 206578174f47SAnthony Koo uint8_t phy_fsm_state; 206678174f47SAnthony Koo /** 206778174f47SAnthony Koo * Phy rate for DP - RBR/HBR/HBR2/HBR3. 206878174f47SAnthony Koo * Set this using enum phy_link_rate. 206978174f47SAnthony Koo * This does not support HDMI/DP2 for now. 207078174f47SAnthony Koo */ 207178174f47SAnthony Koo uint8_t phy_rate; 2072f56c837aSMikita Lipski }; 2073f56c837aSMikita Lipski 20741a595f28SAnthony Koo /** 20751a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 20761a595f28SAnthony Koo * PSR enable/disable is controlled using the sub_type. 20771a595f28SAnthony Koo */ 20787c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_enable { 20791a595f28SAnthony Koo /** 20801a595f28SAnthony Koo * Command header. 20811a595f28SAnthony Koo */ 20827c008829SNicholas Kazlauskas struct dmub_cmd_header header; 2083f56c837aSMikita Lipski 2084f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data data; 20857c008829SNicholas Kazlauskas }; 20867c008829SNicholas Kazlauskas 20871a595f28SAnthony Koo /** 20881a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 20891a595f28SAnthony Koo */ 2090d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data { 20911a595f28SAnthony Koo /** 20921a595f28SAnthony Koo * PSR version that FW should implement. 20931a595f28SAnthony Koo */ 20941a595f28SAnthony Koo enum psr_version version; 2095f56c837aSMikita Lipski /** 2096f56c837aSMikita Lipski * PSR control version. 2097f56c837aSMikita Lipski */ 2098f56c837aSMikita Lipski uint8_t cmd_version; 2099f56c837aSMikita Lipski /** 2100f56c837aSMikita Lipski * Panel Instance. 2101f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 2102f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2103f56c837aSMikita Lipski */ 2104f56c837aSMikita Lipski uint8_t panel_inst; 2105f56c837aSMikita Lipski /** 2106f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 2107f56c837aSMikita Lipski */ 2108f56c837aSMikita Lipski uint8_t pad[2]; 21097c008829SNicholas Kazlauskas }; 21107c008829SNicholas Kazlauskas 21111a595f28SAnthony Koo /** 21121a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 21131a595f28SAnthony Koo */ 2114d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version { 21151a595f28SAnthony Koo /** 21161a595f28SAnthony Koo * Command header. 21171a595f28SAnthony Koo */ 21187c008829SNicholas Kazlauskas struct dmub_cmd_header header; 21191a595f28SAnthony Koo /** 21201a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 21211a595f28SAnthony Koo */ 2122d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data psr_set_version_data; 21237c008829SNicholas Kazlauskas }; 21247c008829SNicholas Kazlauskas 2125f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data { 2126f56c837aSMikita Lipski /** 2127f56c837aSMikita Lipski * PSR control version. 2128f56c837aSMikita Lipski */ 2129f56c837aSMikita Lipski uint8_t cmd_version; 2130f56c837aSMikita Lipski /** 2131f56c837aSMikita Lipski * Panel Instance. 2132f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 2133f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2134f56c837aSMikita Lipski */ 2135f56c837aSMikita Lipski uint8_t panel_inst; 2136f56c837aSMikita Lipski /** 2137ad371c8aSAnthony Koo * Explicit padding to 4 byte boundary. 2138f56c837aSMikita Lipski */ 2139ad371c8aSAnthony Koo uint8_t pad[2]; 2140f56c837aSMikita Lipski }; 2141f56c837aSMikita Lipski 21421a595f28SAnthony Koo /** 21431a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 21441a595f28SAnthony Koo */ 2145672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static { 21461a595f28SAnthony Koo /** 21471a595f28SAnthony Koo * Command header. 21481a595f28SAnthony Koo */ 2149672251b2SAnthony Koo struct dmub_cmd_header header; 2150f56c837aSMikita Lipski /** 2151f56c837aSMikita Lipski * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2152f56c837aSMikita Lipski */ 2153f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data psr_force_static_data; 2154672251b2SAnthony Koo }; 2155672251b2SAnthony Koo 21561a595f28SAnthony Koo /** 215783eb5385SDavid Zhang * PSR SU debug flags. 215883eb5385SDavid Zhang */ 215983eb5385SDavid Zhang union dmub_psr_su_debug_flags { 216083eb5385SDavid Zhang /** 216183eb5385SDavid Zhang * PSR SU debug flags. 216283eb5385SDavid Zhang */ 216383eb5385SDavid Zhang struct { 216483eb5385SDavid Zhang /** 216583eb5385SDavid Zhang * Update dirty rect in SW only. 216683eb5385SDavid Zhang */ 216783eb5385SDavid Zhang uint8_t update_dirty_rect_only : 1; 216883eb5385SDavid Zhang /** 216983eb5385SDavid Zhang * Reset the cursor/plane state before processing the call. 217083eb5385SDavid Zhang */ 217183eb5385SDavid Zhang uint8_t reset_state : 1; 217283eb5385SDavid Zhang } bitfields; 217383eb5385SDavid Zhang 217483eb5385SDavid Zhang /** 217583eb5385SDavid Zhang * Union for debug flags. 217683eb5385SDavid Zhang */ 217783eb5385SDavid Zhang uint32_t u32All; 217883eb5385SDavid Zhang }; 217983eb5385SDavid Zhang 218083eb5385SDavid Zhang /** 218183eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 218283eb5385SDavid Zhang * This triggers a selective update for PSR SU. 218383eb5385SDavid Zhang */ 218483eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data { 218583eb5385SDavid Zhang /** 218683eb5385SDavid Zhang * Dirty rects from OS. 218783eb5385SDavid Zhang */ 218883eb5385SDavid Zhang struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 218983eb5385SDavid Zhang /** 219083eb5385SDavid Zhang * PSR SU debug flags. 219183eb5385SDavid Zhang */ 219283eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags; 219383eb5385SDavid Zhang /** 219483eb5385SDavid Zhang * OTG HW instance. 219583eb5385SDavid Zhang */ 219683eb5385SDavid Zhang uint8_t pipe_idx; 219783eb5385SDavid Zhang /** 219883eb5385SDavid Zhang * Number of dirty rects. 219983eb5385SDavid Zhang */ 220083eb5385SDavid Zhang uint8_t dirty_rect_count; 220183eb5385SDavid Zhang /** 220283eb5385SDavid Zhang * PSR control version. 220383eb5385SDavid Zhang */ 220483eb5385SDavid Zhang uint8_t cmd_version; 220583eb5385SDavid Zhang /** 220683eb5385SDavid Zhang * Panel Instance. 220783eb5385SDavid Zhang * Panel isntance to identify which psr_state to use 220883eb5385SDavid Zhang * Currently the support is only for 0 or 1 220983eb5385SDavid Zhang */ 221083eb5385SDavid Zhang uint8_t panel_inst; 221183eb5385SDavid Zhang }; 221283eb5385SDavid Zhang 221383eb5385SDavid Zhang /** 221483eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 221583eb5385SDavid Zhang */ 221683eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect { 221783eb5385SDavid Zhang /** 221883eb5385SDavid Zhang * Command header. 221983eb5385SDavid Zhang */ 222083eb5385SDavid Zhang struct dmub_cmd_header header; 222183eb5385SDavid Zhang /** 222283eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 222383eb5385SDavid Zhang */ 222483eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 222583eb5385SDavid Zhang }; 222683eb5385SDavid Zhang 222783eb5385SDavid Zhang /** 222883eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 222983eb5385SDavid Zhang */ 2230b73353f7SMax Tseng union dmub_reg_cursor_control_cfg { 2231b73353f7SMax Tseng struct { 2232b73353f7SMax Tseng uint32_t cur_enable: 1; 2233b73353f7SMax Tseng uint32_t reser0: 3; 2234b73353f7SMax Tseng uint32_t cur_2x_magnify: 1; 2235b73353f7SMax Tseng uint32_t reser1: 3; 2236b73353f7SMax Tseng uint32_t mode: 3; 2237b73353f7SMax Tseng uint32_t reser2: 5; 2238b73353f7SMax Tseng uint32_t pitch: 2; 2239b73353f7SMax Tseng uint32_t reser3: 6; 2240b73353f7SMax Tseng uint32_t line_per_chunk: 5; 2241b73353f7SMax Tseng uint32_t reser4: 3; 2242b73353f7SMax Tseng } bits; 2243b73353f7SMax Tseng uint32_t raw; 2244b73353f7SMax Tseng }; 2245b73353f7SMax Tseng struct dmub_cursor_position_cache_hubp { 2246b73353f7SMax Tseng union dmub_reg_cursor_control_cfg cur_ctl; 2247b73353f7SMax Tseng union dmub_reg_position_cfg { 2248b73353f7SMax Tseng struct { 2249b73353f7SMax Tseng uint32_t cur_x_pos: 16; 2250b73353f7SMax Tseng uint32_t cur_y_pos: 16; 2251b73353f7SMax Tseng } bits; 2252b73353f7SMax Tseng uint32_t raw; 2253b73353f7SMax Tseng } position; 2254b73353f7SMax Tseng union dmub_reg_hot_spot_cfg { 2255b73353f7SMax Tseng struct { 2256b73353f7SMax Tseng uint32_t hot_x: 16; 2257b73353f7SMax Tseng uint32_t hot_y: 16; 2258b73353f7SMax Tseng } bits; 2259b73353f7SMax Tseng uint32_t raw; 2260b73353f7SMax Tseng } hot_spot; 2261b73353f7SMax Tseng union dmub_reg_dst_offset_cfg { 2262b73353f7SMax Tseng struct { 2263b73353f7SMax Tseng uint32_t dst_x_offset: 13; 2264b73353f7SMax Tseng uint32_t reserved: 19; 2265b73353f7SMax Tseng } bits; 2266b73353f7SMax Tseng uint32_t raw; 2267b73353f7SMax Tseng } dst_offset; 2268b73353f7SMax Tseng }; 2269b73353f7SMax Tseng 2270b73353f7SMax Tseng union dmub_reg_cur0_control_cfg { 2271b73353f7SMax Tseng struct { 2272b73353f7SMax Tseng uint32_t cur0_enable: 1; 2273b73353f7SMax Tseng uint32_t expansion_mode: 1; 2274b73353f7SMax Tseng uint32_t reser0: 1; 2275b73353f7SMax Tseng uint32_t cur0_rom_en: 1; 2276b73353f7SMax Tseng uint32_t mode: 3; 2277b73353f7SMax Tseng uint32_t reserved: 25; 2278b73353f7SMax Tseng } bits; 2279b73353f7SMax Tseng uint32_t raw; 2280b73353f7SMax Tseng }; 2281b73353f7SMax Tseng struct dmub_cursor_position_cache_dpp { 2282b73353f7SMax Tseng union dmub_reg_cur0_control_cfg cur0_ctl; 2283b73353f7SMax Tseng }; 2284b73353f7SMax Tseng struct dmub_cursor_position_cfg { 2285b73353f7SMax Tseng struct dmub_cursor_position_cache_hubp pHubp; 2286b73353f7SMax Tseng struct dmub_cursor_position_cache_dpp pDpp; 2287b73353f7SMax Tseng uint8_t pipe_idx; 2288b73353f7SMax Tseng /* 2289b73353f7SMax Tseng * Padding is required. To be 4 Bytes Aligned. 2290b73353f7SMax Tseng */ 2291b73353f7SMax Tseng uint8_t padding[3]; 2292b73353f7SMax Tseng }; 2293b73353f7SMax Tseng 2294b73353f7SMax Tseng struct dmub_cursor_attribute_cache_hubp { 2295b73353f7SMax Tseng uint32_t SURFACE_ADDR_HIGH; 2296b73353f7SMax Tseng uint32_t SURFACE_ADDR; 2297b73353f7SMax Tseng union dmub_reg_cursor_control_cfg cur_ctl; 2298b73353f7SMax Tseng union dmub_reg_cursor_size_cfg { 2299b73353f7SMax Tseng struct { 2300b73353f7SMax Tseng uint32_t width: 16; 2301b73353f7SMax Tseng uint32_t height: 16; 2302b73353f7SMax Tseng } bits; 2303b73353f7SMax Tseng uint32_t raw; 2304b73353f7SMax Tseng } size; 2305b73353f7SMax Tseng union dmub_reg_cursor_settings_cfg { 2306b73353f7SMax Tseng struct { 2307b73353f7SMax Tseng uint32_t dst_y_offset: 8; 2308b73353f7SMax Tseng uint32_t chunk_hdl_adjust: 2; 2309b73353f7SMax Tseng uint32_t reserved: 22; 2310b73353f7SMax Tseng } bits; 2311b73353f7SMax Tseng uint32_t raw; 2312b73353f7SMax Tseng } settings; 2313b73353f7SMax Tseng }; 2314b73353f7SMax Tseng struct dmub_cursor_attribute_cache_dpp { 2315b73353f7SMax Tseng union dmub_reg_cur0_control_cfg cur0_ctl; 2316b73353f7SMax Tseng }; 2317b73353f7SMax Tseng struct dmub_cursor_attributes_cfg { 2318b73353f7SMax Tseng struct dmub_cursor_attribute_cache_hubp aHubp; 2319b73353f7SMax Tseng struct dmub_cursor_attribute_cache_dpp aDpp; 2320b73353f7SMax Tseng }; 2321b73353f7SMax Tseng 2322b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 { 232383eb5385SDavid Zhang /** 232483eb5385SDavid Zhang * Cursor dirty rects. 232583eb5385SDavid Zhang */ 232683eb5385SDavid Zhang struct dmub_rect cursor_rect; 232783eb5385SDavid Zhang /** 232883eb5385SDavid Zhang * PSR SU debug flags. 232983eb5385SDavid Zhang */ 233083eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags; 233183eb5385SDavid Zhang /** 233283eb5385SDavid Zhang * Cursor enable/disable. 233383eb5385SDavid Zhang */ 233483eb5385SDavid Zhang uint8_t enable; 233583eb5385SDavid Zhang /** 233683eb5385SDavid Zhang * OTG HW instance. 233783eb5385SDavid Zhang */ 233883eb5385SDavid Zhang uint8_t pipe_idx; 233983eb5385SDavid Zhang /** 234083eb5385SDavid Zhang * PSR control version. 234183eb5385SDavid Zhang */ 234283eb5385SDavid Zhang uint8_t cmd_version; 234383eb5385SDavid Zhang /** 234483eb5385SDavid Zhang * Panel Instance. 234583eb5385SDavid Zhang * Panel isntance to identify which psr_state to use 234683eb5385SDavid Zhang * Currently the support is only for 0 or 1 234783eb5385SDavid Zhang */ 234883eb5385SDavid Zhang uint8_t panel_inst; 2349b73353f7SMax Tseng /** 2350b73353f7SMax Tseng * Cursor Position Register. 2351b73353f7SMax Tseng * Registers contains Hubp & Dpp modules 2352b73353f7SMax Tseng */ 2353b73353f7SMax Tseng struct dmub_cursor_position_cfg position_cfg; 2354b73353f7SMax Tseng }; 2355b73353f7SMax Tseng 2356b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload1 { 2357b73353f7SMax Tseng struct dmub_cursor_attributes_cfg attribute_cfg; 2358b73353f7SMax Tseng }; 2359b73353f7SMax Tseng 2360b73353f7SMax Tseng union dmub_cmd_update_cursor_info_data { 2361b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 payload0; 2362b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload1 payload1; 236383eb5385SDavid Zhang }; 236483eb5385SDavid Zhang /** 236583eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 236683eb5385SDavid Zhang */ 236783eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info { 236883eb5385SDavid Zhang /** 236983eb5385SDavid Zhang * Command header. 237083eb5385SDavid Zhang */ 237183eb5385SDavid Zhang struct dmub_cmd_header header; 237283eb5385SDavid Zhang /** 237383eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 237483eb5385SDavid Zhang */ 2375b73353f7SMax Tseng union dmub_cmd_update_cursor_info_data update_cursor_info_data; 237683eb5385SDavid Zhang }; 237783eb5385SDavid Zhang 237883eb5385SDavid Zhang /** 237983eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 238083eb5385SDavid Zhang */ 238183eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data { 238283eb5385SDavid Zhang /** 238383eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 238483eb5385SDavid Zhang */ 238583eb5385SDavid Zhang uint16_t psr_vtotal_idle; 238683eb5385SDavid Zhang /** 238783eb5385SDavid Zhang * PSR control version. 238883eb5385SDavid Zhang */ 238983eb5385SDavid Zhang uint8_t cmd_version; 239083eb5385SDavid Zhang /** 239183eb5385SDavid Zhang * Panel Instance. 239283eb5385SDavid Zhang * Panel isntance to identify which psr_state to use 239383eb5385SDavid Zhang * Currently the support is only for 0 or 1 239483eb5385SDavid Zhang */ 239583eb5385SDavid Zhang uint8_t panel_inst; 239683eb5385SDavid Zhang /* 239783eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 239883eb5385SDavid Zhang */ 239983eb5385SDavid Zhang uint16_t psr_vtotal_su; 240083eb5385SDavid Zhang /** 240183eb5385SDavid Zhang * Explicit padding to 4 byte boundary. 240283eb5385SDavid Zhang */ 240383eb5385SDavid Zhang uint8_t pad2[2]; 240483eb5385SDavid Zhang }; 240583eb5385SDavid Zhang 240683eb5385SDavid Zhang /** 240783eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 240883eb5385SDavid Zhang */ 240983eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal { 241083eb5385SDavid Zhang /** 241183eb5385SDavid Zhang * Command header. 241283eb5385SDavid Zhang */ 241383eb5385SDavid Zhang struct dmub_cmd_header header; 241483eb5385SDavid Zhang /** 241583eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 241683eb5385SDavid Zhang */ 241783eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 241883eb5385SDavid Zhang }; 241983eb5385SDavid Zhang 242083eb5385SDavid Zhang /** 2421e5dfcd27SRobin Chen * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2422e5dfcd27SRobin Chen */ 2423e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data { 2424e5dfcd27SRobin Chen /** 2425e5dfcd27SRobin Chen * PSR control version. 2426e5dfcd27SRobin Chen */ 2427e5dfcd27SRobin Chen uint8_t cmd_version; 2428e5dfcd27SRobin Chen /** 2429e5dfcd27SRobin Chen * Panel Instance. 2430e5dfcd27SRobin Chen * Panel isntance to identify which psr_state to use 2431e5dfcd27SRobin Chen * Currently the support is only for 0 or 1 2432e5dfcd27SRobin Chen */ 2433e5dfcd27SRobin Chen uint8_t panel_inst; 2434e5dfcd27SRobin Chen /** 2435e5dfcd27SRobin Chen * Explicit padding to 4 byte boundary. 2436e5dfcd27SRobin Chen */ 2437e5dfcd27SRobin Chen uint8_t pad[2]; 2438e5dfcd27SRobin Chen /** 2439e5dfcd27SRobin Chen * PSR power option 2440e5dfcd27SRobin Chen */ 2441e5dfcd27SRobin Chen uint32_t power_opt; 2442e5dfcd27SRobin Chen }; 2443e5dfcd27SRobin Chen 2444e5dfcd27SRobin Chen /** 2445e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2446e5dfcd27SRobin Chen */ 2447e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt { 2448e5dfcd27SRobin Chen /** 2449e5dfcd27SRobin Chen * Command header. 2450e5dfcd27SRobin Chen */ 2451e5dfcd27SRobin Chen struct dmub_cmd_header header; 2452e5dfcd27SRobin Chen /** 2453e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2454e5dfcd27SRobin Chen */ 2455e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2456e5dfcd27SRobin Chen }; 2457e5dfcd27SRobin Chen 2458e5dfcd27SRobin Chen /** 24591a595f28SAnthony Koo * Set of HW components that can be locked. 24600b51e7e8SAnthony Koo * 24610b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 24620b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 24631a595f28SAnthony Koo */ 2464788408b7SAnthony Koo union dmub_hw_lock_flags { 24651a595f28SAnthony Koo /** 24661a595f28SAnthony Koo * Set of HW components that can be locked. 24671a595f28SAnthony Koo */ 2468788408b7SAnthony Koo struct { 24691a595f28SAnthony Koo /** 24701a595f28SAnthony Koo * Lock/unlock OTG master update lock. 24711a595f28SAnthony Koo */ 2472788408b7SAnthony Koo uint8_t lock_pipe : 1; 24731a595f28SAnthony Koo /** 24741a595f28SAnthony Koo * Lock/unlock cursor. 24751a595f28SAnthony Koo */ 2476788408b7SAnthony Koo uint8_t lock_cursor : 1; 24771a595f28SAnthony Koo /** 24781a595f28SAnthony Koo * Lock/unlock global update lock. 24791a595f28SAnthony Koo */ 2480788408b7SAnthony Koo uint8_t lock_dig : 1; 24811a595f28SAnthony Koo /** 24821a595f28SAnthony Koo * Triple buffer lock requires additional hw programming to usual OTG master lock. 24831a595f28SAnthony Koo */ 2484788408b7SAnthony Koo uint8_t triple_buffer_lock : 1; 2485788408b7SAnthony Koo } bits; 2486788408b7SAnthony Koo 24871a595f28SAnthony Koo /** 24881a595f28SAnthony Koo * Union for HW Lock flags. 24891a595f28SAnthony Koo */ 2490788408b7SAnthony Koo uint8_t u8All; 2491788408b7SAnthony Koo }; 2492788408b7SAnthony Koo 24931a595f28SAnthony Koo /** 24941a595f28SAnthony Koo * Instances of HW to be locked. 24950b51e7e8SAnthony Koo * 24960b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 24970b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 24981a595f28SAnthony Koo */ 2499788408b7SAnthony Koo struct dmub_hw_lock_inst_flags { 25001a595f28SAnthony Koo /** 25011a595f28SAnthony Koo * OTG HW instance for OTG master update lock. 25021a595f28SAnthony Koo */ 2503788408b7SAnthony Koo uint8_t otg_inst; 25041a595f28SAnthony Koo /** 25051a595f28SAnthony Koo * OPP instance for cursor lock. 25061a595f28SAnthony Koo */ 2507788408b7SAnthony Koo uint8_t opp_inst; 25081a595f28SAnthony Koo /** 25091a595f28SAnthony Koo * OTG HW instance for global update lock. 25101a595f28SAnthony Koo * TODO: Remove, and re-use otg_inst. 25111a595f28SAnthony Koo */ 2512788408b7SAnthony Koo uint8_t dig_inst; 25131a595f28SAnthony Koo /** 25141a595f28SAnthony Koo * Explicit pad to 4 byte boundary. 25151a595f28SAnthony Koo */ 2516788408b7SAnthony Koo uint8_t pad; 2517788408b7SAnthony Koo }; 2518788408b7SAnthony Koo 25191a595f28SAnthony Koo /** 25201a595f28SAnthony Koo * Clients that can acquire the HW Lock Manager. 25210b51e7e8SAnthony Koo * 25220b51e7e8SAnthony Koo * Note: If updating with more clients, fields in 25230b51e7e8SAnthony Koo * dmub_inbox0_cmd_lock_hw must be updated to match. 25241a595f28SAnthony Koo */ 2525788408b7SAnthony Koo enum hw_lock_client { 25261a595f28SAnthony Koo /** 25271a595f28SAnthony Koo * Driver is the client of HW Lock Manager. 25281a595f28SAnthony Koo */ 2529788408b7SAnthony Koo HW_LOCK_CLIENT_DRIVER = 0, 25301a595f28SAnthony Koo /** 253183eb5385SDavid Zhang * PSR SU is the client of HW Lock Manager. 253283eb5385SDavid Zhang */ 253383eb5385SDavid Zhang HW_LOCK_CLIENT_PSR_SU = 1, 253483eb5385SDavid Zhang /** 25351a595f28SAnthony Koo * Invalid client. 25361a595f28SAnthony Koo */ 2537788408b7SAnthony Koo HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2538788408b7SAnthony Koo }; 2539788408b7SAnthony Koo 25401a595f28SAnthony Koo /** 25411a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 25421a595f28SAnthony Koo */ 2543788408b7SAnthony Koo struct dmub_cmd_lock_hw_data { 25441a595f28SAnthony Koo /** 25451a595f28SAnthony Koo * Specifies the client accessing HW Lock Manager. 25461a595f28SAnthony Koo */ 2547788408b7SAnthony Koo enum hw_lock_client client; 25481a595f28SAnthony Koo /** 25491a595f28SAnthony Koo * HW instances to be locked. 25501a595f28SAnthony Koo */ 2551788408b7SAnthony Koo struct dmub_hw_lock_inst_flags inst_flags; 25521a595f28SAnthony Koo /** 25531a595f28SAnthony Koo * Which components to be locked. 25541a595f28SAnthony Koo */ 2555788408b7SAnthony Koo union dmub_hw_lock_flags hw_locks; 25561a595f28SAnthony Koo /** 25571a595f28SAnthony Koo * Specifies lock/unlock. 25581a595f28SAnthony Koo */ 2559788408b7SAnthony Koo uint8_t lock; 25601a595f28SAnthony Koo /** 25611a595f28SAnthony Koo * HW can be unlocked separately from releasing the HW Lock Mgr. 25621a595f28SAnthony Koo * This flag is set if the client wishes to release the object. 25631a595f28SAnthony Koo */ 2564788408b7SAnthony Koo uint8_t should_release; 25651a595f28SAnthony Koo /** 25661a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 25671a595f28SAnthony Koo */ 2568788408b7SAnthony Koo uint8_t pad; 2569788408b7SAnthony Koo }; 2570788408b7SAnthony Koo 25711a595f28SAnthony Koo /** 25721a595f28SAnthony Koo * Definition of a DMUB_CMD__HW_LOCK command. 25731a595f28SAnthony Koo * Command is used by driver and FW. 25741a595f28SAnthony Koo */ 2575788408b7SAnthony Koo struct dmub_rb_cmd_lock_hw { 25761a595f28SAnthony Koo /** 25771a595f28SAnthony Koo * Command header. 25781a595f28SAnthony Koo */ 2579788408b7SAnthony Koo struct dmub_cmd_header header; 25801a595f28SAnthony Koo /** 25811a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 25821a595f28SAnthony Koo */ 2583788408b7SAnthony Koo struct dmub_cmd_lock_hw_data lock_hw_data; 2584788408b7SAnthony Koo }; 2585788408b7SAnthony Koo 25861a595f28SAnthony Koo /** 25871a595f28SAnthony Koo * ABM command sub-types. 25881a595f28SAnthony Koo */ 258984034ad4SAnthony Koo enum dmub_cmd_abm_type { 25901a595f28SAnthony Koo /** 25911a595f28SAnthony Koo * Initialize parameters for ABM algorithm. 25921a595f28SAnthony Koo * Data is passed through an indirect buffer. 25931a595f28SAnthony Koo */ 259484034ad4SAnthony Koo DMUB_CMD__ABM_INIT_CONFIG = 0, 25951a595f28SAnthony Koo /** 25961a595f28SAnthony Koo * Set OTG and panel HW instance. 25971a595f28SAnthony Koo */ 259884034ad4SAnthony Koo DMUB_CMD__ABM_SET_PIPE = 1, 25991a595f28SAnthony Koo /** 26001a595f28SAnthony Koo * Set user requested backklight level. 26011a595f28SAnthony Koo */ 260284034ad4SAnthony Koo DMUB_CMD__ABM_SET_BACKLIGHT = 2, 26031a595f28SAnthony Koo /** 26041a595f28SAnthony Koo * Set ABM operating/aggression level. 26051a595f28SAnthony Koo */ 260684034ad4SAnthony Koo DMUB_CMD__ABM_SET_LEVEL = 3, 26071a595f28SAnthony Koo /** 26081a595f28SAnthony Koo * Set ambient light level. 26091a595f28SAnthony Koo */ 261084034ad4SAnthony Koo DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 26111a595f28SAnthony Koo /** 26121a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 26131a595f28SAnthony Koo */ 261484034ad4SAnthony Koo DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2615b629a824SEric Yang 2616b629a824SEric Yang /** 2617b629a824SEric Yang * unregister vertical interrupt after steady state is reached 2618b629a824SEric Yang */ 2619b629a824SEric Yang DMUB_CMD__ABM_PAUSE = 6, 262084034ad4SAnthony Koo }; 262184034ad4SAnthony Koo 26221a595f28SAnthony Koo /** 26231a595f28SAnthony Koo * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 26241a595f28SAnthony Koo * Requirements: 26251a595f28SAnthony Koo * - Padded explicitly to 32-bit boundary. 26261a595f28SAnthony Koo * - Must ensure this structure matches the one on driver-side, 26271a595f28SAnthony Koo * otherwise it won't be aligned. 262884034ad4SAnthony Koo */ 262984034ad4SAnthony Koo struct abm_config_table { 26301a595f28SAnthony Koo /** 26311a595f28SAnthony Koo * Gamma curve thresholds, used for crgb conversion. 26321a595f28SAnthony Koo */ 263384034ad4SAnthony Koo uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 26341a595f28SAnthony Koo /** 26351a595f28SAnthony Koo * Gamma curve offsets, used for crgb conversion. 26361a595f28SAnthony Koo */ 2637b6402afeSAnthony Koo uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 26381a595f28SAnthony Koo /** 26391a595f28SAnthony Koo * Gamma curve slopes, used for crgb conversion. 26401a595f28SAnthony Koo */ 2641b6402afeSAnthony Koo uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 26421a595f28SAnthony Koo /** 26431a595f28SAnthony Koo * Custom backlight curve thresholds. 26441a595f28SAnthony Koo */ 2645b6402afeSAnthony Koo uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 26461a595f28SAnthony Koo /** 26471a595f28SAnthony Koo * Custom backlight curve offsets. 26481a595f28SAnthony Koo */ 2649b6402afeSAnthony Koo uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 26501a595f28SAnthony Koo /** 26511a595f28SAnthony Koo * Ambient light thresholds. 26521a595f28SAnthony Koo */ 2653b6402afeSAnthony Koo uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 26541a595f28SAnthony Koo /** 26551a595f28SAnthony Koo * Minimum programmable backlight. 26561a595f28SAnthony Koo */ 2657b6402afeSAnthony Koo uint16_t min_abm_backlight; // 122B 26581a595f28SAnthony Koo /** 26591a595f28SAnthony Koo * Minimum reduction values. 26601a595f28SAnthony Koo */ 2661b6402afeSAnthony Koo uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 26621a595f28SAnthony Koo /** 26631a595f28SAnthony Koo * Maximum reduction values. 26641a595f28SAnthony Koo */ 2665b6402afeSAnthony Koo uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 26661a595f28SAnthony Koo /** 26671a595f28SAnthony Koo * Bright positive gain. 26681a595f28SAnthony Koo */ 2669b6402afeSAnthony Koo uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 26701a595f28SAnthony Koo /** 26711a595f28SAnthony Koo * Dark negative gain. 26721a595f28SAnthony Koo */ 2673b6402afeSAnthony Koo uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 26741a595f28SAnthony Koo /** 26751a595f28SAnthony Koo * Hybrid factor. 26761a595f28SAnthony Koo */ 2677b6402afeSAnthony Koo uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 26781a595f28SAnthony Koo /** 26791a595f28SAnthony Koo * Contrast factor. 26801a595f28SAnthony Koo */ 2681b6402afeSAnthony Koo uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 26821a595f28SAnthony Koo /** 26831a595f28SAnthony Koo * Deviation gain. 26841a595f28SAnthony Koo */ 2685b6402afeSAnthony Koo uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 26861a595f28SAnthony Koo /** 26871a595f28SAnthony Koo * Minimum knee. 26881a595f28SAnthony Koo */ 2689b6402afeSAnthony Koo uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 26901a595f28SAnthony Koo /** 26911a595f28SAnthony Koo * Maximum knee. 26921a595f28SAnthony Koo */ 2693b6402afeSAnthony Koo uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 26941a595f28SAnthony Koo /** 26951a595f28SAnthony Koo * Unused. 26961a595f28SAnthony Koo */ 2697b6402afeSAnthony Koo uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 26981a595f28SAnthony Koo /** 26991a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 27001a595f28SAnthony Koo */ 2701b6402afeSAnthony Koo uint8_t pad3[3]; // 229B 27021a595f28SAnthony Koo /** 27031a595f28SAnthony Koo * Backlight ramp reduction. 27041a595f28SAnthony Koo */ 2705b6402afeSAnthony Koo uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 27061a595f28SAnthony Koo /** 27071a595f28SAnthony Koo * Backlight ramp start. 27081a595f28SAnthony Koo */ 2709b6402afeSAnthony Koo uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 271084034ad4SAnthony Koo }; 271184034ad4SAnthony Koo 27121a595f28SAnthony Koo /** 27131a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 27141a595f28SAnthony Koo */ 2715e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data { 27161a595f28SAnthony Koo /** 27171a595f28SAnthony Koo * OTG HW instance. 27181a595f28SAnthony Koo */ 27197b8a6362SAnthony Koo uint8_t otg_inst; 27201a595f28SAnthony Koo 27211a595f28SAnthony Koo /** 27221a595f28SAnthony Koo * Panel Control HW instance. 27231a595f28SAnthony Koo */ 27247b8a6362SAnthony Koo uint8_t panel_inst; 27251a595f28SAnthony Koo 27261a595f28SAnthony Koo /** 27271a595f28SAnthony Koo * Controls how ABM will interpret a set pipe or set level command. 27281a595f28SAnthony Koo */ 27297b8a6362SAnthony Koo uint8_t set_pipe_option; 27301a595f28SAnthony Koo 27311a595f28SAnthony Koo /** 27321a595f28SAnthony Koo * Unused. 27331a595f28SAnthony Koo * TODO: Remove. 27341a595f28SAnthony Koo */ 27351a595f28SAnthony Koo uint8_t ramping_boundary; 2736e6ea8c34SWyatt Wood }; 2737e6ea8c34SWyatt Wood 27381a595f28SAnthony Koo /** 27391a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 27401a595f28SAnthony Koo */ 2741e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe { 27421a595f28SAnthony Koo /** 27431a595f28SAnthony Koo * Command header. 27441a595f28SAnthony Koo */ 2745e6ea8c34SWyatt Wood struct dmub_cmd_header header; 27461a595f28SAnthony Koo 27471a595f28SAnthony Koo /** 27481a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 27491a595f28SAnthony Koo */ 2750e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2751e6ea8c34SWyatt Wood }; 2752e6ea8c34SWyatt Wood 27531a595f28SAnthony Koo /** 27541a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 27551a595f28SAnthony Koo */ 2756e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data { 27571a595f28SAnthony Koo /** 27581a595f28SAnthony Koo * Number of frames to ramp to backlight user level. 27591a595f28SAnthony Koo */ 2760e6ea8c34SWyatt Wood uint32_t frame_ramp; 27611a595f28SAnthony Koo 27621a595f28SAnthony Koo /** 27631a595f28SAnthony Koo * Requested backlight level from user. 27641a595f28SAnthony Koo */ 2765474ac4a8SYongqiang Sun uint32_t backlight_user_level; 2766e922057bSJake Wang 2767e922057bSJake Wang /** 276863de4f04SJake Wang * ABM control version. 2769e922057bSJake Wang */ 2770e922057bSJake Wang uint8_t version; 2771e922057bSJake Wang 2772e922057bSJake Wang /** 2773e922057bSJake Wang * Panel Control HW instance mask. 2774e922057bSJake Wang * Bit 0 is Panel Control HW instance 0. 2775e922057bSJake Wang * Bit 1 is Panel Control HW instance 1. 2776e922057bSJake Wang */ 2777e922057bSJake Wang uint8_t panel_mask; 2778e922057bSJake Wang 2779e922057bSJake Wang /** 2780e922057bSJake Wang * Explicit padding to 4 byte boundary. 2781e922057bSJake Wang */ 2782e922057bSJake Wang uint8_t pad[2]; 2783e6ea8c34SWyatt Wood }; 2784e6ea8c34SWyatt Wood 27851a595f28SAnthony Koo /** 27861a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 27871a595f28SAnthony Koo */ 2788e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight { 27891a595f28SAnthony Koo /** 27901a595f28SAnthony Koo * Command header. 27911a595f28SAnthony Koo */ 2792e6ea8c34SWyatt Wood struct dmub_cmd_header header; 27931a595f28SAnthony Koo 27941a595f28SAnthony Koo /** 27951a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 27961a595f28SAnthony Koo */ 2797e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2798e6ea8c34SWyatt Wood }; 2799e6ea8c34SWyatt Wood 28001a595f28SAnthony Koo /** 28011a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 28021a595f28SAnthony Koo */ 2803e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data { 28041a595f28SAnthony Koo /** 28051a595f28SAnthony Koo * Set current ABM operating/aggression level. 28061a595f28SAnthony Koo */ 2807e6ea8c34SWyatt Wood uint32_t level; 280863de4f04SJake Wang 280963de4f04SJake Wang /** 281063de4f04SJake Wang * ABM control version. 281163de4f04SJake Wang */ 281263de4f04SJake Wang uint8_t version; 281363de4f04SJake Wang 281463de4f04SJake Wang /** 281563de4f04SJake Wang * Panel Control HW instance mask. 281663de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 281763de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 281863de4f04SJake Wang */ 281963de4f04SJake Wang uint8_t panel_mask; 282063de4f04SJake Wang 282163de4f04SJake Wang /** 282263de4f04SJake Wang * Explicit padding to 4 byte boundary. 282363de4f04SJake Wang */ 282463de4f04SJake Wang uint8_t pad[2]; 2825e6ea8c34SWyatt Wood }; 2826e6ea8c34SWyatt Wood 28271a595f28SAnthony Koo /** 28281a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 28291a595f28SAnthony Koo */ 2830e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level { 28311a595f28SAnthony Koo /** 28321a595f28SAnthony Koo * Command header. 28331a595f28SAnthony Koo */ 2834e6ea8c34SWyatt Wood struct dmub_cmd_header header; 28351a595f28SAnthony Koo 28361a595f28SAnthony Koo /** 28371a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 28381a595f28SAnthony Koo */ 2839e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data abm_set_level_data; 2840e6ea8c34SWyatt Wood }; 2841e6ea8c34SWyatt Wood 28421a595f28SAnthony Koo /** 28431a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 28441a595f28SAnthony Koo */ 2845e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data { 28461a595f28SAnthony Koo /** 28471a595f28SAnthony Koo * Ambient light sensor reading from OS. 28481a595f28SAnthony Koo */ 2849e6ea8c34SWyatt Wood uint32_t ambient_lux; 285063de4f04SJake Wang 285163de4f04SJake Wang /** 285263de4f04SJake Wang * ABM control version. 285363de4f04SJake Wang */ 285463de4f04SJake Wang uint8_t version; 285563de4f04SJake Wang 285663de4f04SJake Wang /** 285763de4f04SJake Wang * Panel Control HW instance mask. 285863de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 285963de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 286063de4f04SJake Wang */ 286163de4f04SJake Wang uint8_t panel_mask; 286263de4f04SJake Wang 286363de4f04SJake Wang /** 286463de4f04SJake Wang * Explicit padding to 4 byte boundary. 286563de4f04SJake Wang */ 286663de4f04SJake Wang uint8_t pad[2]; 2867e6ea8c34SWyatt Wood }; 2868e6ea8c34SWyatt Wood 28691a595f28SAnthony Koo /** 28701a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 28711a595f28SAnthony Koo */ 2872e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level { 28731a595f28SAnthony Koo /** 28741a595f28SAnthony Koo * Command header. 28751a595f28SAnthony Koo */ 2876e6ea8c34SWyatt Wood struct dmub_cmd_header header; 28771a595f28SAnthony Koo 28781a595f28SAnthony Koo /** 28791a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 28801a595f28SAnthony Koo */ 2881e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2882e6ea8c34SWyatt Wood }; 2883e6ea8c34SWyatt Wood 28841a595f28SAnthony Koo /** 28851a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 28861a595f28SAnthony Koo */ 2887e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data { 28881a595f28SAnthony Koo /** 28891a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 28901a595f28SAnthony Koo * TODO: Convert to uint8_t. 28911a595f28SAnthony Koo */ 2892e6ea8c34SWyatt Wood uint32_t fractional_pwm; 289363de4f04SJake Wang 289463de4f04SJake Wang /** 289563de4f04SJake Wang * ABM control version. 289663de4f04SJake Wang */ 289763de4f04SJake Wang uint8_t version; 289863de4f04SJake Wang 289963de4f04SJake Wang /** 290063de4f04SJake Wang * Panel Control HW instance mask. 290163de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 290263de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 290363de4f04SJake Wang */ 290463de4f04SJake Wang uint8_t panel_mask; 290563de4f04SJake Wang 290663de4f04SJake Wang /** 290763de4f04SJake Wang * Explicit padding to 4 byte boundary. 290863de4f04SJake Wang */ 290963de4f04SJake Wang uint8_t pad[2]; 2910e6ea8c34SWyatt Wood }; 2911e6ea8c34SWyatt Wood 29121a595f28SAnthony Koo /** 29131a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 29141a595f28SAnthony Koo */ 2915e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac { 29161a595f28SAnthony Koo /** 29171a595f28SAnthony Koo * Command header. 29181a595f28SAnthony Koo */ 2919e6ea8c34SWyatt Wood struct dmub_cmd_header header; 29201a595f28SAnthony Koo 29211a595f28SAnthony Koo /** 29221a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 29231a595f28SAnthony Koo */ 2924e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2925e6ea8c34SWyatt Wood }; 2926e6ea8c34SWyatt Wood 29271a595f28SAnthony Koo /** 29281a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 29291a595f28SAnthony Koo */ 293016012806SWyatt Wood struct dmub_cmd_abm_init_config_data { 29311a595f28SAnthony Koo /** 29321a595f28SAnthony Koo * Location of indirect buffer used to pass init data to ABM. 29331a595f28SAnthony Koo */ 293416012806SWyatt Wood union dmub_addr src; 29351a595f28SAnthony Koo 29361a595f28SAnthony Koo /** 29371a595f28SAnthony Koo * Indirect buffer length. 29381a595f28SAnthony Koo */ 293916012806SWyatt Wood uint16_t bytes; 294063de4f04SJake Wang 294163de4f04SJake Wang 294263de4f04SJake Wang /** 294363de4f04SJake Wang * ABM control version. 294463de4f04SJake Wang */ 294563de4f04SJake Wang uint8_t version; 294663de4f04SJake Wang 294763de4f04SJake Wang /** 294863de4f04SJake Wang * Panel Control HW instance mask. 294963de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 295063de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 295163de4f04SJake Wang */ 295263de4f04SJake Wang uint8_t panel_mask; 295363de4f04SJake Wang 295463de4f04SJake Wang /** 295563de4f04SJake Wang * Explicit padding to 4 byte boundary. 295663de4f04SJake Wang */ 295763de4f04SJake Wang uint8_t pad[2]; 295816012806SWyatt Wood }; 295916012806SWyatt Wood 29601a595f28SAnthony Koo /** 29611a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 29621a595f28SAnthony Koo */ 296316012806SWyatt Wood struct dmub_rb_cmd_abm_init_config { 29641a595f28SAnthony Koo /** 29651a595f28SAnthony Koo * Command header. 29661a595f28SAnthony Koo */ 296716012806SWyatt Wood struct dmub_cmd_header header; 29681a595f28SAnthony Koo 29691a595f28SAnthony Koo /** 29701a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 29711a595f28SAnthony Koo */ 297216012806SWyatt Wood struct dmub_cmd_abm_init_config_data abm_init_config_data; 297316012806SWyatt Wood }; 297416012806SWyatt Wood 29751a595f28SAnthony Koo /** 2976b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2977b629a824SEric Yang */ 2978b629a824SEric Yang 2979b629a824SEric Yang struct dmub_cmd_abm_pause_data { 2980b629a824SEric Yang 2981b629a824SEric Yang /** 2982b629a824SEric Yang * Panel Control HW instance mask. 2983b629a824SEric Yang * Bit 0 is Panel Control HW instance 0. 2984b629a824SEric Yang * Bit 1 is Panel Control HW instance 1. 2985b629a824SEric Yang */ 2986b629a824SEric Yang uint8_t panel_mask; 2987b629a824SEric Yang 2988b629a824SEric Yang /** 2989b629a824SEric Yang * OTG hw instance 2990b629a824SEric Yang */ 2991b629a824SEric Yang uint8_t otg_inst; 2992b629a824SEric Yang 2993b629a824SEric Yang /** 2994b629a824SEric Yang * Enable or disable ABM pause 2995b629a824SEric Yang */ 2996b629a824SEric Yang uint8_t enable; 2997b629a824SEric Yang 2998b629a824SEric Yang /** 2999b629a824SEric Yang * Explicit padding to 4 byte boundary. 3000b629a824SEric Yang */ 3001b629a824SEric Yang uint8_t pad[1]; 3002b629a824SEric Yang }; 3003b629a824SEric Yang 3004b629a824SEric Yang /** 3005b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 3006b629a824SEric Yang */ 3007b629a824SEric Yang struct dmub_rb_cmd_abm_pause { 3008b629a824SEric Yang /** 3009b629a824SEric Yang * Command header. 3010b629a824SEric Yang */ 3011b629a824SEric Yang struct dmub_cmd_header header; 3012b629a824SEric Yang 3013b629a824SEric Yang /** 3014b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3015b629a824SEric Yang */ 3016b629a824SEric Yang struct dmub_cmd_abm_pause_data abm_pause_data; 3017b629a824SEric Yang }; 3018b629a824SEric Yang 3019b629a824SEric Yang /** 30201a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 30211a595f28SAnthony Koo */ 302234ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data { 30231a595f28SAnthony Koo /** 30241a595f28SAnthony Koo * DMUB feature capabilities. 30251a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features. 30261a595f28SAnthony Koo */ 302734ba432cSAnthony Koo struct dmub_feature_caps feature_caps; 302834ba432cSAnthony Koo }; 302934ba432cSAnthony Koo 30301a595f28SAnthony Koo /** 30311a595f28SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 30321a595f28SAnthony Koo */ 303334ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps { 30341a595f28SAnthony Koo /** 30351a595f28SAnthony Koo * Command header. 30361a595f28SAnthony Koo */ 303734ba432cSAnthony Koo struct dmub_cmd_header header; 30381a595f28SAnthony Koo /** 30391a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 30401a595f28SAnthony Koo */ 304134ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 304234ba432cSAnthony Koo }; 304334ba432cSAnthony Koo 3044b09c1fffSLeo (Hanghong) Ma /** 3045b09c1fffSLeo (Hanghong) Ma * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3046b09c1fffSLeo (Hanghong) Ma */ 3047b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_visual_confirm_color_data { 3048b09c1fffSLeo (Hanghong) Ma /** 3049b09c1fffSLeo (Hanghong) Ma * DMUB feature capabilities. 3050b09c1fffSLeo (Hanghong) Ma * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3051b09c1fffSLeo (Hanghong) Ma */ 3052b09c1fffSLeo (Hanghong) Ma struct dmub_visual_confirm_color visual_confirm_color; 3053b09c1fffSLeo (Hanghong) Ma }; 3054b09c1fffSLeo (Hanghong) Ma 3055b09c1fffSLeo (Hanghong) Ma /** 3056b09c1fffSLeo (Hanghong) Ma * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3057b09c1fffSLeo (Hanghong) Ma */ 3058b09c1fffSLeo (Hanghong) Ma struct dmub_rb_cmd_get_visual_confirm_color { 3059b09c1fffSLeo (Hanghong) Ma /** 3060b09c1fffSLeo (Hanghong) Ma * Command header. 3061b09c1fffSLeo (Hanghong) Ma */ 3062b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_header header; 3063b09c1fffSLeo (Hanghong) Ma /** 3064b09c1fffSLeo (Hanghong) Ma * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3065b09c1fffSLeo (Hanghong) Ma */ 3066b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3067b09c1fffSLeo (Hanghong) Ma }; 3068b09c1fffSLeo (Hanghong) Ma 3069592a6318SAnthony Koo struct dmub_optc_state { 3070592a6318SAnthony Koo uint32_t v_total_max; 3071592a6318SAnthony Koo uint32_t v_total_min; 3072592a6318SAnthony Koo uint32_t tg_inst; 3073592a6318SAnthony Koo }; 3074592a6318SAnthony Koo 3075592a6318SAnthony Koo struct dmub_rb_cmd_drr_update { 3076592a6318SAnthony Koo struct dmub_cmd_header header; 3077592a6318SAnthony Koo struct dmub_optc_state dmub_optc_state_req; 3078592a6318SAnthony Koo }; 3079592a6318SAnthony Koo 308000fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 308100fa7f03SRodrigo Siqueira uint32_t pix_clk_100hz; 308200fa7f03SRodrigo Siqueira uint8_t max_ramp_step; 308300fa7f03SRodrigo Siqueira uint8_t pipes; 308400fa7f03SRodrigo Siqueira uint8_t min_refresh_in_hz; 308500fa7f03SRodrigo Siqueira uint8_t padding[1]; 308600fa7f03SRodrigo Siqueira }; 308700fa7f03SRodrigo Siqueira 308800fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config { 308900fa7f03SRodrigo Siqueira uint8_t fams_enabled; 309000fa7f03SRodrigo Siqueira uint8_t visual_confirm_enabled; 309100fa7f03SRodrigo Siqueira uint8_t padding[2]; 309200fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 309300fa7f03SRodrigo Siqueira }; 309400fa7f03SRodrigo Siqueira 309500fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch { 309600fa7f03SRodrigo Siqueira struct dmub_cmd_header header; 309700fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 309800fa7f03SRodrigo Siqueira }; 309900fa7f03SRodrigo Siqueira 3100b04cb192SNicholas Kazlauskas /** 3101b04cb192SNicholas Kazlauskas * enum dmub_cmd_panel_cntl_type - Panel control command. 3102b04cb192SNicholas Kazlauskas */ 3103b04cb192SNicholas Kazlauskas enum dmub_cmd_panel_cntl_type { 3104b04cb192SNicholas Kazlauskas /** 3105b04cb192SNicholas Kazlauskas * Initializes embedded panel hardware blocks. 3106b04cb192SNicholas Kazlauskas */ 3107b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3108b04cb192SNicholas Kazlauskas /** 3109b04cb192SNicholas Kazlauskas * Queries backlight info for the embedded panel. 3110b04cb192SNicholas Kazlauskas */ 3111b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3112b04cb192SNicholas Kazlauskas }; 3113b04cb192SNicholas Kazlauskas 3114b04cb192SNicholas Kazlauskas /** 3115b04cb192SNicholas Kazlauskas * struct dmub_cmd_panel_cntl_data - Panel control data. 3116b04cb192SNicholas Kazlauskas */ 3117b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data { 3118b04cb192SNicholas Kazlauskas uint32_t inst; /**< panel instance */ 3119b04cb192SNicholas Kazlauskas uint32_t current_backlight; /* in/out */ 3120b04cb192SNicholas Kazlauskas uint32_t bl_pwm_cntl; /* in/out */ 3121b04cb192SNicholas Kazlauskas uint32_t bl_pwm_period_cntl; /* in/out */ 3122b04cb192SNicholas Kazlauskas uint32_t bl_pwm_ref_div1; /* in/out */ 3123b04cb192SNicholas Kazlauskas uint8_t is_backlight_on : 1; /* in/out */ 3124b04cb192SNicholas Kazlauskas uint8_t is_powered_on : 1; /* in/out */ 3125a91b402dSCharlene Liu uint8_t padding[3]; 3126a91b402dSCharlene Liu uint32_t bl_pwm_ref_div2; /* in/out */ 3127a91b402dSCharlene Liu uint8_t reserved[4]; 3128b04cb192SNicholas Kazlauskas }; 3129b04cb192SNicholas Kazlauskas 3130b04cb192SNicholas Kazlauskas /** 3131b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_panel_cntl - Panel control command. 3132b04cb192SNicholas Kazlauskas */ 3133b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl { 3134b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 3135b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data data; /**< payload */ 3136b04cb192SNicholas Kazlauskas }; 3137b04cb192SNicholas Kazlauskas 31381a595f28SAnthony Koo /** 31391a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 31401a595f28SAnthony Koo */ 31411a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data { 31421a595f28SAnthony Koo uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3143e0886e1fSTony Tascioglu uint8_t bypass_panel_control_wait; 31440888aa30SAnthony Koo uint8_t reserved_0[2]; /**< For future use */ 31451a595f28SAnthony Koo uint8_t panel_inst; /**< LVTMA control instance */ 31461a595f28SAnthony Koo uint8_t reserved_1[3]; /**< For future use */ 31471a595f28SAnthony Koo }; 31481a595f28SAnthony Koo 31491a595f28SAnthony Koo /** 31501a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 31511a595f28SAnthony Koo */ 31521a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control { 31531a595f28SAnthony Koo /** 31541a595f28SAnthony Koo * Command header. 31551a595f28SAnthony Koo */ 31561a595f28SAnthony Koo struct dmub_cmd_header header; 31571a595f28SAnthony Koo /** 31581a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 31591a595f28SAnthony Koo */ 31601a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data data; 31611a595f28SAnthony Koo }; 31621a595f28SAnthony Koo 3163592a6318SAnthony Koo /** 316441f91315SNicholas Kazlauskas * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 316541f91315SNicholas Kazlauskas */ 316641f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data { 316741f91315SNicholas Kazlauskas uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 316841f91315SNicholas Kazlauskas uint8_t is_usb; /**< is phy is usb */ 316941f91315SNicholas Kazlauskas uint8_t is_dp_alt_disable; /**< is dp alt disable */ 317041f91315SNicholas Kazlauskas uint8_t is_dp4; /**< is dp in 4 lane */ 317141f91315SNicholas Kazlauskas }; 317241f91315SNicholas Kazlauskas 317341f91315SNicholas Kazlauskas /** 317441f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 317541f91315SNicholas Kazlauskas */ 317641f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt { 317741f91315SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 317841f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 317941f91315SNicholas Kazlauskas }; 318041f91315SNicholas Kazlauskas 318141f91315SNicholas Kazlauskas /** 3182021eaef8SAnthony Koo * Maximum number of bytes a chunk sent to DMUB for parsing 3183021eaef8SAnthony Koo */ 3184021eaef8SAnthony Koo #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3185021eaef8SAnthony Koo 3186021eaef8SAnthony Koo /** 3187021eaef8SAnthony Koo * Represent a chunk of CEA blocks sent to DMUB for parsing 3188021eaef8SAnthony Koo */ 3189021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea { 3190021eaef8SAnthony Koo uint16_t offset; /**< offset into the CEA block */ 3191021eaef8SAnthony Koo uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3192eb9e59ebSOliver Logush uint16_t cea_total_length; /**< total length of the CEA block */ 3193021eaef8SAnthony Koo uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3194021eaef8SAnthony Koo uint8_t pad[3]; /**< padding and for future expansion */ 3195021eaef8SAnthony Koo }; 3196021eaef8SAnthony Koo 3197021eaef8SAnthony Koo /** 3198021eaef8SAnthony Koo * Result of VSDB parsing from CEA block 3199021eaef8SAnthony Koo */ 3200021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb { 3201021eaef8SAnthony Koo uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3202021eaef8SAnthony Koo uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3203021eaef8SAnthony Koo uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3204021eaef8SAnthony Koo uint16_t min_frame_rate; /**< Maximum frame rate */ 3205021eaef8SAnthony Koo uint16_t max_frame_rate; /**< Minimum frame rate */ 3206021eaef8SAnthony Koo }; 3207021eaef8SAnthony Koo 3208021eaef8SAnthony Koo /** 3209021eaef8SAnthony Koo * Result of sending a CEA chunk 3210021eaef8SAnthony Koo */ 3211021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack { 3212021eaef8SAnthony Koo uint16_t offset; /**< offset of the chunk into the CEA block */ 3213021eaef8SAnthony Koo uint8_t success; /**< 1 if this sending of chunk succeeded */ 3214021eaef8SAnthony Koo uint8_t pad; /**< padding and for future expansion */ 3215021eaef8SAnthony Koo }; 3216021eaef8SAnthony Koo 3217021eaef8SAnthony Koo /** 3218021eaef8SAnthony Koo * Specify whether the result is an ACK/NACK or the parsing has finished 3219021eaef8SAnthony Koo */ 3220021eaef8SAnthony Koo enum dmub_cmd_edid_cea_reply_type { 3221021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3222021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3223021eaef8SAnthony Koo }; 3224021eaef8SAnthony Koo 3225021eaef8SAnthony Koo /** 3226021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 3227021eaef8SAnthony Koo */ 3228021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea { 3229021eaef8SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 3230021eaef8SAnthony Koo union dmub_cmd_edid_cea_data { 3231021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3232021eaef8SAnthony Koo struct dmub_cmd_edid_cea_output { /**< output with results */ 3233021eaef8SAnthony Koo uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3234021eaef8SAnthony Koo union { 3235021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3236021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack ack; 3237021eaef8SAnthony Koo }; 3238021eaef8SAnthony Koo } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3239021eaef8SAnthony Koo } data; /**< Command data */ 3240021eaef8SAnthony Koo 3241021eaef8SAnthony Koo }; 3242021eaef8SAnthony Koo 3243021eaef8SAnthony Koo /** 3244c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3245c595fb05SWenjing Liu */ 3246c595fb05SWenjing Liu struct dmub_cmd_cable_id_input { 3247c595fb05SWenjing Liu uint8_t phy_inst; /**< phy inst for cable id data */ 3248c595fb05SWenjing Liu }; 3249c595fb05SWenjing Liu 3250c595fb05SWenjing Liu /** 3251c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3252c595fb05SWenjing Liu */ 3253c595fb05SWenjing Liu struct dmub_cmd_cable_id_output { 3254c595fb05SWenjing Liu uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3255c595fb05SWenjing Liu uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3256c595fb05SWenjing Liu uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3257c595fb05SWenjing Liu uint8_t RESERVED :2; /**< reserved means not defined */ 3258c595fb05SWenjing Liu }; 3259c595fb05SWenjing Liu 3260c595fb05SWenjing Liu /** 3261c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3262c595fb05SWenjing Liu */ 3263c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id { 3264c595fb05SWenjing Liu struct dmub_cmd_header header; /**< Command header */ 3265c595fb05SWenjing Liu /** 3266c595fb05SWenjing Liu * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3267c595fb05SWenjing Liu */ 3268c595fb05SWenjing Liu union dmub_cmd_cable_id_data { 3269c595fb05SWenjing Liu struct dmub_cmd_cable_id_input input; /**< Input */ 3270c595fb05SWenjing Liu struct dmub_cmd_cable_id_output output; /**< Output */ 3271c595fb05SWenjing Liu uint8_t output_raw; /**< Raw data output */ 3272c595fb05SWenjing Liu } data; 3273c595fb05SWenjing Liu }; 3274c595fb05SWenjing Liu 32751fb695d9SAnthony Koo /** 32761fb695d9SAnthony Koo * Command type of a DMUB_CMD__SECURE_DISPLAY command 32771fb695d9SAnthony Koo */ 3278c0459bddSAlan Liu enum dmub_cmd_secure_display_type { 32791fb695d9SAnthony Koo DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3280c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3281c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3282c0459bddSAlan Liu }; 3283c0459bddSAlan Liu 32841fb695d9SAnthony Koo /** 32851fb695d9SAnthony Koo * Definition of a DMUB_CMD__SECURE_DISPLAY command 32861fb695d9SAnthony Koo */ 3287c0459bddSAlan Liu struct dmub_rb_cmd_secure_display { 3288c0459bddSAlan Liu struct dmub_cmd_header header; 32891fb695d9SAnthony Koo /** 32901fb695d9SAnthony Koo * Data passed from driver to dmub firmware. 32911fb695d9SAnthony Koo */ 3292c0459bddSAlan Liu struct dmub_cmd_roi_info { 3293c0459bddSAlan Liu uint16_t x_start; 3294c0459bddSAlan Liu uint16_t x_end; 3295c0459bddSAlan Liu uint16_t y_start; 3296c0459bddSAlan Liu uint16_t y_end; 3297c0459bddSAlan Liu uint8_t otg_id; 3298c0459bddSAlan Liu uint8_t phy_id; 3299c0459bddSAlan Liu } roi_info; 3300c0459bddSAlan Liu }; 3301c0459bddSAlan Liu 3302c595fb05SWenjing Liu /** 3303592a6318SAnthony Koo * union dmub_rb_cmd - DMUB inbox command. 3304592a6318SAnthony Koo */ 33057c008829SNicholas Kazlauskas union dmub_rb_cmd { 3306592a6318SAnthony Koo /** 3307592a6318SAnthony Koo * Elements shared with all commands. 3308592a6318SAnthony Koo */ 33097c008829SNicholas Kazlauskas struct dmub_rb_cmd_common cmd_common; 3310592a6318SAnthony Koo /** 3311592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3312592a6318SAnthony Koo */ 3313592a6318SAnthony Koo struct dmub_rb_cmd_read_modify_write read_modify_write; 3314592a6318SAnthony Koo /** 3315592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3316592a6318SAnthony Koo */ 3317592a6318SAnthony Koo struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3318592a6318SAnthony Koo /** 3319592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3320592a6318SAnthony Koo */ 3321592a6318SAnthony Koo struct dmub_rb_cmd_burst_write burst_write; 3322592a6318SAnthony Koo /** 3323592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_REG_WAIT command. 3324592a6318SAnthony Koo */ 3325592a6318SAnthony Koo struct dmub_rb_cmd_reg_wait reg_wait; 3326592a6318SAnthony Koo /** 3327592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3328592a6318SAnthony Koo */ 33297c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3330592a6318SAnthony Koo /** 3331592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3332592a6318SAnthony Koo */ 33337c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3334592a6318SAnthony Koo /** 3335592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3336592a6318SAnthony Koo */ 33377c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3338592a6318SAnthony Koo /** 3339592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3340592a6318SAnthony Koo */ 33417c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init dpphy_init; 3342592a6318SAnthony Koo /** 3343592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3344592a6318SAnthony Koo */ 33457c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 33461a595f28SAnthony Koo /** 3347*e383b127SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3348*e383b127SNicholas Kazlauskas */ 3349*e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control domain_control; 3350*e383b127SNicholas Kazlauskas /** 33511a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 33521a595f28SAnthony Koo */ 3353d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version psr_set_version; 33541a595f28SAnthony Koo /** 33551a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 33561a595f28SAnthony Koo */ 33577c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 33581a595f28SAnthony Koo /** 33591a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 33601a595f28SAnthony Koo */ 3361d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_enable psr_enable; 33621a595f28SAnthony Koo /** 33631a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 33641a595f28SAnthony Koo */ 33657c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level psr_set_level; 33661a595f28SAnthony Koo /** 33671a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 33681a595f28SAnthony Koo */ 3369672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static psr_force_static; 3370592a6318SAnthony Koo /** 337183eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 337283eb5385SDavid Zhang */ 337383eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 337483eb5385SDavid Zhang /** 337583eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 337683eb5385SDavid Zhang */ 337783eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info update_cursor_info; 337883eb5385SDavid Zhang /** 337983eb5385SDavid Zhang * Definition of a DMUB_CMD__HW_LOCK command. 338083eb5385SDavid Zhang * Command is used by driver and FW. 338183eb5385SDavid Zhang */ 338283eb5385SDavid Zhang struct dmub_rb_cmd_lock_hw lock_hw; 338383eb5385SDavid Zhang /** 338483eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 338583eb5385SDavid Zhang */ 338683eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 338783eb5385SDavid Zhang /** 3388e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3389e5dfcd27SRobin Chen */ 3390e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3391e5dfcd27SRobin Chen /** 3392592a6318SAnthony Koo * Definition of a DMUB_CMD__PLAT_54186_WA command. 3393592a6318SAnthony Koo */ 3394bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3395592a6318SAnthony Koo /** 3396592a6318SAnthony Koo * Definition of a DMUB_CMD__MALL command. 3397592a6318SAnthony Koo */ 339852f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall mall; 3399b04cb192SNicholas Kazlauskas /** 3400ac2e555eSAurabindo Pillai * Definition of a DMUB_CMD__CAB command. 3401ac2e555eSAurabindo Pillai */ 3402ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss cab; 340385f4bc0cSAlvin Lee 340485f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 340585f4bc0cSAlvin Lee 3406ac2e555eSAurabindo Pillai /** 3407b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3408b04cb192SNicholas Kazlauskas */ 3409b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3410b04cb192SNicholas Kazlauskas 3411b04cb192SNicholas Kazlauskas /** 3412b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3413b04cb192SNicholas Kazlauskas */ 3414b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3415b04cb192SNicholas Kazlauskas 3416b04cb192SNicholas Kazlauskas /** 3417b04cb192SNicholas Kazlauskas * Definition of DMUB_CMD__PANEL_CNTL commands. 3418b04cb192SNicholas Kazlauskas */ 3419b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl panel_cntl; 34201a595f28SAnthony Koo /** 34211a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 34221a595f28SAnthony Koo */ 3423e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 34241a595f28SAnthony Koo 34251a595f28SAnthony Koo /** 34261a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 34271a595f28SAnthony Koo */ 3428e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 34291a595f28SAnthony Koo 34301a595f28SAnthony Koo /** 34311a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 34321a595f28SAnthony Koo */ 3433e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level abm_set_level; 34341a595f28SAnthony Koo 34351a595f28SAnthony Koo /** 34361a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 34371a595f28SAnthony Koo */ 3438e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 34391a595f28SAnthony Koo 34401a595f28SAnthony Koo /** 34411a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 34421a595f28SAnthony Koo */ 3443e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 34441a595f28SAnthony Koo 34451a595f28SAnthony Koo /** 34461a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 34471a595f28SAnthony Koo */ 344816012806SWyatt Wood struct dmub_rb_cmd_abm_init_config abm_init_config; 34491a595f28SAnthony Koo 34501a595f28SAnthony Koo /** 3451b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 3452b629a824SEric Yang */ 3453b629a824SEric Yang struct dmub_rb_cmd_abm_pause abm_pause; 3454b629a824SEric Yang 3455b629a824SEric Yang /** 34561a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 34571a595f28SAnthony Koo */ 3458d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access dp_aux_access; 34591a595f28SAnthony Koo 34601a595f28SAnthony Koo /** 3461592a6318SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3462592a6318SAnthony Koo */ 3463592a6318SAnthony Koo struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3464592a6318SAnthony Koo 3465592a6318SAnthony Koo /** 3466592a6318SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 34671a595f28SAnthony Koo */ 346834ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3469b09c1fffSLeo (Hanghong) Ma 3470b09c1fffSLeo (Hanghong) Ma /** 3471b09c1fffSLeo (Hanghong) Ma * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3472b09c1fffSLeo (Hanghong) Ma */ 3473b09c1fffSLeo (Hanghong) Ma struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3474592a6318SAnthony Koo struct dmub_rb_cmd_drr_update drr_update; 347500fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 347600fa7f03SRodrigo Siqueira 34771a595f28SAnthony Koo /** 34781a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 34791a595f28SAnthony Koo */ 34801a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control lvtma_control; 3481021eaef8SAnthony Koo /** 348241f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 348341f91315SNicholas Kazlauskas */ 348441f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 348541f91315SNicholas Kazlauskas /** 348676724b76SJimmy Kizito * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 348776724b76SJimmy Kizito */ 348876724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 348976724b76SJimmy Kizito /** 349071af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 349171af9d46SMeenakshikumar Somasundaram */ 349271af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access set_config_access; 349371af9d46SMeenakshikumar Somasundaram /** 3494139a3311SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3495139a3311SMeenakshikumar Somasundaram */ 3496139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3497139a3311SMeenakshikumar Somasundaram /** 3498021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 3499021eaef8SAnthony Koo */ 3500021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea edid_cea; 3501c595fb05SWenjing Liu /** 3502c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3503c595fb05SWenjing Liu */ 3504c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3505ea5a4db9SAnthony Koo 3506ea5a4db9SAnthony Koo /** 3507ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3508ea5a4db9SAnthony Koo */ 3509ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state query_hpd; 35106f4f8ff5SMeenakshikumar Somasundaram /** 3511c0459bddSAlan Liu * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3512c0459bddSAlan Liu */ 3513c0459bddSAlan Liu struct dmub_rb_cmd_secure_display secure_display; 35141fb695d9SAnthony Koo 3515c0459bddSAlan Liu /** 35166f4f8ff5SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 35176f4f8ff5SMeenakshikumar Somasundaram */ 35186f4f8ff5SMeenakshikumar Somasundaram struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 35197c008829SNicholas Kazlauskas }; 35207c008829SNicholas Kazlauskas 3521592a6318SAnthony Koo /** 3522592a6318SAnthony Koo * union dmub_rb_out_cmd - Outbox command 3523592a6318SAnthony Koo */ 3524d9beecfcSAnthony Koo union dmub_rb_out_cmd { 3525592a6318SAnthony Koo /** 3526592a6318SAnthony Koo * Parameters common to every command. 3527592a6318SAnthony Koo */ 3528d9beecfcSAnthony Koo struct dmub_rb_cmd_common cmd_common; 3529592a6318SAnthony Koo /** 3530592a6318SAnthony Koo * AUX reply command. 3531592a6318SAnthony Koo */ 3532d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3533592a6318SAnthony Koo /** 3534592a6318SAnthony Koo * HPD notify command. 3535592a6318SAnthony Koo */ 3536d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 353771af9d46SMeenakshikumar Somasundaram /** 353871af9d46SMeenakshikumar Somasundaram * SET_CONFIG reply command. 353971af9d46SMeenakshikumar Somasundaram */ 354071af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3541669018a9SMustapha Ghaddar /** 35428af54c61SMustapha Ghaddar * DPIA notification command. 3543669018a9SMustapha Ghaddar */ 35448af54c61SMustapha Ghaddar struct dmub_rb_cmd_dpia_notification dpia_notification; 3545d9beecfcSAnthony Koo }; 35467c008829SNicholas Kazlauskas #pragma pack(pop) 35477c008829SNicholas Kazlauskas 354884034ad4SAnthony Koo 354984034ad4SAnthony Koo //============================================================================== 355084034ad4SAnthony Koo //</DMUB_CMD>=================================================================== 355184034ad4SAnthony Koo //============================================================================== 355284034ad4SAnthony Koo //< DMUB_RB>==================================================================== 355384034ad4SAnthony Koo //============================================================================== 355484034ad4SAnthony Koo 355584034ad4SAnthony Koo #if defined(__cplusplus) 355684034ad4SAnthony Koo extern "C" { 355784034ad4SAnthony Koo #endif 355884034ad4SAnthony Koo 3559592a6318SAnthony Koo /** 3560592a6318SAnthony Koo * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3561592a6318SAnthony Koo */ 356284034ad4SAnthony Koo struct dmub_rb_init_params { 3563592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 3564592a6318SAnthony Koo void *base_address; /**< CPU base address for ring's data */ 3565592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3566592a6318SAnthony Koo uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3567592a6318SAnthony Koo uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 356884034ad4SAnthony Koo }; 356984034ad4SAnthony Koo 3570592a6318SAnthony Koo /** 3571592a6318SAnthony Koo * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3572592a6318SAnthony Koo */ 357384034ad4SAnthony Koo struct dmub_rb { 3574592a6318SAnthony Koo void *base_address; /**< CPU address for the ring's data */ 3575592a6318SAnthony Koo uint32_t rptr; /**< Read pointer for consumer in bytes */ 3576592a6318SAnthony Koo uint32_t wrpt; /**< Write pointer for producer in bytes */ 3577592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 357884034ad4SAnthony Koo 3579592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 3580592a6318SAnthony Koo void *dmub; /**< Pointer to the DMUB interface */ 358184034ad4SAnthony Koo }; 358284034ad4SAnthony Koo 3583592a6318SAnthony Koo /** 3584592a6318SAnthony Koo * @brief Checks if the ringbuffer is empty. 3585592a6318SAnthony Koo * 3586592a6318SAnthony Koo * @param rb DMUB Ringbuffer 3587592a6318SAnthony Koo * @return true if empty 3588592a6318SAnthony Koo * @return false otherwise 3589592a6318SAnthony Koo */ 359084034ad4SAnthony Koo static inline bool dmub_rb_empty(struct dmub_rb *rb) 359184034ad4SAnthony Koo { 359284034ad4SAnthony Koo return (rb->wrpt == rb->rptr); 359384034ad4SAnthony Koo } 359484034ad4SAnthony Koo 3595592a6318SAnthony Koo /** 3596592a6318SAnthony Koo * @brief Checks if the ringbuffer is full 3597592a6318SAnthony Koo * 3598592a6318SAnthony Koo * @param rb DMUB Ringbuffer 3599592a6318SAnthony Koo * @return true if full 3600592a6318SAnthony Koo * @return false otherwise 3601592a6318SAnthony Koo */ 360284034ad4SAnthony Koo static inline bool dmub_rb_full(struct dmub_rb *rb) 360384034ad4SAnthony Koo { 360484034ad4SAnthony Koo uint32_t data_count; 360584034ad4SAnthony Koo 360684034ad4SAnthony Koo if (rb->wrpt >= rb->rptr) 360784034ad4SAnthony Koo data_count = rb->wrpt - rb->rptr; 360884034ad4SAnthony Koo else 360984034ad4SAnthony Koo data_count = rb->capacity - (rb->rptr - rb->wrpt); 361084034ad4SAnthony Koo 361184034ad4SAnthony Koo return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 361284034ad4SAnthony Koo } 361384034ad4SAnthony Koo 3614592a6318SAnthony Koo /** 3615592a6318SAnthony Koo * @brief Pushes a command into the ringbuffer 3616592a6318SAnthony Koo * 3617592a6318SAnthony Koo * @param rb DMUB ringbuffer 3618592a6318SAnthony Koo * @param cmd The command to push 3619592a6318SAnthony Koo * @return true if the ringbuffer was not full 3620592a6318SAnthony Koo * @return false otherwise 3621592a6318SAnthony Koo */ 362284034ad4SAnthony Koo static inline bool dmub_rb_push_front(struct dmub_rb *rb, 362384034ad4SAnthony Koo const union dmub_rb_cmd *cmd) 362484034ad4SAnthony Koo { 36253f232a0fSAnthony Koo uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 36263a9d5b0bSAnthony Koo const uint64_t *src = (const uint64_t *)cmd; 36273a9d5b0bSAnthony Koo uint8_t i; 362884034ad4SAnthony Koo 362984034ad4SAnthony Koo if (dmub_rb_full(rb)) 363084034ad4SAnthony Koo return false; 363184034ad4SAnthony Koo 363284034ad4SAnthony Koo // copying data 36333a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 36343a9d5b0bSAnthony Koo *dst++ = *src++; 363584034ad4SAnthony Koo 363684034ad4SAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 363784034ad4SAnthony Koo 363884034ad4SAnthony Koo if (rb->wrpt >= rb->capacity) 363984034ad4SAnthony Koo rb->wrpt %= rb->capacity; 364084034ad4SAnthony Koo 364184034ad4SAnthony Koo return true; 364284034ad4SAnthony Koo } 364384034ad4SAnthony Koo 3644592a6318SAnthony Koo /** 3645592a6318SAnthony Koo * @brief Pushes a command into the DMUB outbox ringbuffer 3646592a6318SAnthony Koo * 3647592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 3648592a6318SAnthony Koo * @param cmd Outbox command 3649592a6318SAnthony Koo * @return true if not full 3650592a6318SAnthony Koo * @return false otherwise 3651592a6318SAnthony Koo */ 3652d9beecfcSAnthony Koo static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3653d9beecfcSAnthony Koo const union dmub_rb_out_cmd *cmd) 3654d9beecfcSAnthony Koo { 3655d9beecfcSAnthony Koo uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3656d459b79bSAnthony Koo const uint8_t *src = (const uint8_t *)cmd; 3657d9beecfcSAnthony Koo 3658d9beecfcSAnthony Koo if (dmub_rb_full(rb)) 3659d9beecfcSAnthony Koo return false; 3660d9beecfcSAnthony Koo 3661d9beecfcSAnthony Koo dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3662d9beecfcSAnthony Koo 3663d9beecfcSAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 3664d9beecfcSAnthony Koo 3665d9beecfcSAnthony Koo if (rb->wrpt >= rb->capacity) 3666d9beecfcSAnthony Koo rb->wrpt %= rb->capacity; 3667d9beecfcSAnthony Koo 3668d9beecfcSAnthony Koo return true; 3669d9beecfcSAnthony Koo } 3670d9beecfcSAnthony Koo 3671592a6318SAnthony Koo /** 3672592a6318SAnthony Koo * @brief Returns the next unprocessed command in the ringbuffer. 3673592a6318SAnthony Koo * 3674592a6318SAnthony Koo * @param rb DMUB ringbuffer 3675592a6318SAnthony Koo * @param cmd The command to return 3676592a6318SAnthony Koo * @return true if not empty 3677592a6318SAnthony Koo * @return false otherwise 3678592a6318SAnthony Koo */ 367984034ad4SAnthony Koo static inline bool dmub_rb_front(struct dmub_rb *rb, 368034ba432cSAnthony Koo union dmub_rb_cmd **cmd) 368184034ad4SAnthony Koo { 368234ba432cSAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 368384034ad4SAnthony Koo 368484034ad4SAnthony Koo if (dmub_rb_empty(rb)) 368584034ad4SAnthony Koo return false; 368684034ad4SAnthony Koo 368734ba432cSAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 368884034ad4SAnthony Koo 368984034ad4SAnthony Koo return true; 369084034ad4SAnthony Koo } 369184034ad4SAnthony Koo 3692592a6318SAnthony Koo /** 36930b51e7e8SAnthony Koo * @brief Determines the next ringbuffer offset. 36940b51e7e8SAnthony Koo * 36950b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 36960b51e7e8SAnthony Koo * @param num_cmds Number of commands 36970b51e7e8SAnthony Koo * @param next_rptr The next offset in the ringbuffer 36980b51e7e8SAnthony Koo */ 36990b51e7e8SAnthony Koo static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 37000b51e7e8SAnthony Koo uint32_t num_cmds, 37010b51e7e8SAnthony Koo uint32_t *next_rptr) 37020b51e7e8SAnthony Koo { 37030b51e7e8SAnthony Koo *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 37040b51e7e8SAnthony Koo 37050b51e7e8SAnthony Koo if (*next_rptr >= rb->capacity) 37060b51e7e8SAnthony Koo *next_rptr %= rb->capacity; 37070b51e7e8SAnthony Koo } 37080b51e7e8SAnthony Koo 37090b51e7e8SAnthony Koo /** 37100b51e7e8SAnthony Koo * @brief Returns a pointer to a command in the inbox. 37110b51e7e8SAnthony Koo * 37120b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 37130b51e7e8SAnthony Koo * @param cmd The inbox command to return 37140b51e7e8SAnthony Koo * @param rptr The ringbuffer offset 37150b51e7e8SAnthony Koo * @return true if not empty 37160b51e7e8SAnthony Koo * @return false otherwise 37170b51e7e8SAnthony Koo */ 37180b51e7e8SAnthony Koo static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 37190b51e7e8SAnthony Koo union dmub_rb_cmd **cmd, 37200b51e7e8SAnthony Koo uint32_t rptr) 37210b51e7e8SAnthony Koo { 37220b51e7e8SAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 37230b51e7e8SAnthony Koo 37240b51e7e8SAnthony Koo if (dmub_rb_empty(rb)) 37250b51e7e8SAnthony Koo return false; 37260b51e7e8SAnthony Koo 37270b51e7e8SAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 37280b51e7e8SAnthony Koo 37290b51e7e8SAnthony Koo return true; 37300b51e7e8SAnthony Koo } 37310b51e7e8SAnthony Koo 37320b51e7e8SAnthony Koo /** 3733592a6318SAnthony Koo * @brief Returns the next unprocessed command in the outbox. 3734592a6318SAnthony Koo * 3735592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 3736592a6318SAnthony Koo * @param cmd The outbox command to return 3737592a6318SAnthony Koo * @return true if not empty 3738592a6318SAnthony Koo * @return false otherwise 3739592a6318SAnthony Koo */ 3740d9beecfcSAnthony Koo static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3741d9beecfcSAnthony Koo union dmub_rb_out_cmd *cmd) 3742d9beecfcSAnthony Koo { 37433f232a0fSAnthony Koo const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 37443a9d5b0bSAnthony Koo uint64_t *dst = (uint64_t *)cmd; 37453a9d5b0bSAnthony Koo uint8_t i; 3746d9beecfcSAnthony Koo 3747d9beecfcSAnthony Koo if (dmub_rb_empty(rb)) 3748d9beecfcSAnthony Koo return false; 3749d9beecfcSAnthony Koo 3750d9beecfcSAnthony Koo // copying data 37513a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 37523a9d5b0bSAnthony Koo *dst++ = *src++; 3753d9beecfcSAnthony Koo 3754d9beecfcSAnthony Koo return true; 3755d9beecfcSAnthony Koo } 3756d9beecfcSAnthony Koo 3757592a6318SAnthony Koo /** 3758592a6318SAnthony Koo * @brief Removes the front entry in the ringbuffer. 3759592a6318SAnthony Koo * 3760592a6318SAnthony Koo * @param rb DMUB ringbuffer 3761592a6318SAnthony Koo * @return true if the command was removed 3762592a6318SAnthony Koo * @return false if there were no commands 3763592a6318SAnthony Koo */ 376484034ad4SAnthony Koo static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 376584034ad4SAnthony Koo { 376684034ad4SAnthony Koo if (dmub_rb_empty(rb)) 376784034ad4SAnthony Koo return false; 376884034ad4SAnthony Koo 376984034ad4SAnthony Koo rb->rptr += DMUB_RB_CMD_SIZE; 377084034ad4SAnthony Koo 377184034ad4SAnthony Koo if (rb->rptr >= rb->capacity) 377284034ad4SAnthony Koo rb->rptr %= rb->capacity; 377384034ad4SAnthony Koo 377484034ad4SAnthony Koo return true; 377584034ad4SAnthony Koo } 377684034ad4SAnthony Koo 3777592a6318SAnthony Koo /** 3778592a6318SAnthony Koo * @brief Flushes commands in the ringbuffer to framebuffer memory. 3779592a6318SAnthony Koo * 3780592a6318SAnthony Koo * Avoids a race condition where DMCUB accesses memory while 3781592a6318SAnthony Koo * there are still writes in flight to framebuffer. 3782592a6318SAnthony Koo * 3783592a6318SAnthony Koo * @param rb DMUB ringbuffer 3784592a6318SAnthony Koo */ 378584034ad4SAnthony Koo static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 378684034ad4SAnthony Koo { 378784034ad4SAnthony Koo uint32_t rptr = rb->rptr; 378884034ad4SAnthony Koo uint32_t wptr = rb->wrpt; 378984034ad4SAnthony Koo 379084034ad4SAnthony Koo while (rptr != wptr) { 37917da7b02eSAashish Sharma uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 37923a9d5b0bSAnthony Koo uint8_t i; 379384034ad4SAnthony Koo 379423da6e0fSMaíra Canal /* Don't remove this. 379523da6e0fSMaíra Canal * The contents need to actually be read from the ring buffer 379623da6e0fSMaíra Canal * for this function to be effective. 379723da6e0fSMaíra Canal */ 37983a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 37997da7b02eSAashish Sharma (void)READ_ONCE(*data++); 380084034ad4SAnthony Koo 380184034ad4SAnthony Koo rptr += DMUB_RB_CMD_SIZE; 380284034ad4SAnthony Koo if (rptr >= rb->capacity) 380384034ad4SAnthony Koo rptr %= rb->capacity; 380484034ad4SAnthony Koo } 380584034ad4SAnthony Koo } 380684034ad4SAnthony Koo 3807592a6318SAnthony Koo /** 3808592a6318SAnthony Koo * @brief Initializes a DMCUB ringbuffer 3809592a6318SAnthony Koo * 3810592a6318SAnthony Koo * @param rb DMUB ringbuffer 3811592a6318SAnthony Koo * @param init_params initial configuration for the ringbuffer 3812592a6318SAnthony Koo */ 381384034ad4SAnthony Koo static inline void dmub_rb_init(struct dmub_rb *rb, 381484034ad4SAnthony Koo struct dmub_rb_init_params *init_params) 381584034ad4SAnthony Koo { 381684034ad4SAnthony Koo rb->base_address = init_params->base_address; 381784034ad4SAnthony Koo rb->capacity = init_params->capacity; 381884034ad4SAnthony Koo rb->rptr = init_params->read_ptr; 381984034ad4SAnthony Koo rb->wrpt = init_params->write_ptr; 382084034ad4SAnthony Koo } 382184034ad4SAnthony Koo 3822592a6318SAnthony Koo /** 3823592a6318SAnthony Koo * @brief Copies output data from in/out commands into the given command. 3824592a6318SAnthony Koo * 3825592a6318SAnthony Koo * @param rb DMUB ringbuffer 3826592a6318SAnthony Koo * @param cmd Command to copy data into 3827592a6318SAnthony Koo */ 382834ba432cSAnthony Koo static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 382934ba432cSAnthony Koo union dmub_rb_cmd *cmd) 383034ba432cSAnthony Koo { 383134ba432cSAnthony Koo // Copy rb entry back into command 383234ba432cSAnthony Koo uint8_t *rd_ptr = (rb->rptr == 0) ? 383334ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 383434ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 383534ba432cSAnthony Koo 383634ba432cSAnthony Koo dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 383734ba432cSAnthony Koo } 383834ba432cSAnthony Koo 383984034ad4SAnthony Koo #if defined(__cplusplus) 384084034ad4SAnthony Koo } 384184034ad4SAnthony Koo #endif 384284034ad4SAnthony Koo 384384034ad4SAnthony Koo //============================================================================== 384484034ad4SAnthony Koo //</DMUB_RB>==================================================================== 384584034ad4SAnthony Koo //============================================================================== 384684034ad4SAnthony Koo 38477c008829SNicholas Kazlauskas #endif /* _DMUB_CMD_H_ */ 3848