17c008829SNicholas Kazlauskas /* 27c008829SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 37c008829SNicholas Kazlauskas * 47c008829SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 57c008829SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 67c008829SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 77c008829SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87c008829SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 97c008829SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 107c008829SNicholas Kazlauskas * 117c008829SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 127c008829SNicholas Kazlauskas * all copies or substantial portions of the Software. 137c008829SNicholas Kazlauskas * 147c008829SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157c008829SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167c008829SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177c008829SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187c008829SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197c008829SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207c008829SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 217c008829SNicholas Kazlauskas * 227c008829SNicholas Kazlauskas * Authors: AMD 237c008829SNicholas Kazlauskas * 247c008829SNicholas Kazlauskas */ 257c008829SNicholas Kazlauskas 267c008829SNicholas Kazlauskas #ifndef _DMUB_CMD_H_ 277c008829SNicholas Kazlauskas #define _DMUB_CMD_H_ 287c008829SNicholas Kazlauskas 298b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 308b19a4e3SAnthony Koo #include "dmub_fw_types.h" 318b19a4e3SAnthony Koo #include "include_legacy/atomfirmware.h" 328b19a4e3SAnthony Koo 338b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) 348b19a4e3SAnthony Koo #include <string.h> 358b19a4e3SAnthony Koo #endif 368b19a4e3SAnthony Koo #else 378b19a4e3SAnthony Koo 3884034ad4SAnthony Koo #include <asm/byteorder.h> 3984034ad4SAnthony Koo #include <linux/types.h> 4084034ad4SAnthony Koo #include <linux/string.h> 4184034ad4SAnthony Koo #include <linux/delay.h> 4284034ad4SAnthony Koo #include <stdarg.h> 4384034ad4SAnthony Koo 447c008829SNicholas Kazlauskas #include "atomfirmware.h" 4522aa5614SYongqiang Sun 468b19a4e3SAnthony Koo #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 478b19a4e3SAnthony Koo 488598a722SAnthony Koo /* Firmware versioning. */ 498598a722SAnthony Koo #ifdef DMUB_EXPOSE_VERSION 50*d459b79bSAnthony Koo #define DMUB_FW_VERSION_GIT_HASH 0xc761b9efd 51b2265774SAnthony Koo #define DMUB_FW_VERSION_MAJOR 0 528598a722SAnthony Koo #define DMUB_FW_VERSION_MINOR 0 53*d459b79bSAnthony Koo #define DMUB_FW_VERSION_REVISION 73 54ded750e6SAnthony Koo #define DMUB_FW_VERSION_TEST 0 55ded750e6SAnthony Koo #define DMUB_FW_VERSION_VBIOS 0 56ded750e6SAnthony Koo #define DMUB_FW_VERSION_HOTFIX 0 57ded750e6SAnthony Koo #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 58ded750e6SAnthony Koo ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 59ded750e6SAnthony Koo ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 60ded750e6SAnthony Koo ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 61ded750e6SAnthony Koo ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 62ded750e6SAnthony Koo (DMUB_FW_VERSION_HOTFIX & 0x3F)) 63ded750e6SAnthony Koo 648598a722SAnthony Koo #endif 6584034ad4SAnthony Koo 6684034ad4SAnthony Koo //<DMUB_TYPES>================================================================== 6784034ad4SAnthony Koo /* Basic type definitions. */ 6884034ad4SAnthony Koo 698b19a4e3SAnthony Koo #define __forceinline inline 708b19a4e3SAnthony Koo 711a595f28SAnthony Koo /** 721a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled gradually 731a595f28SAnthony Koo * by slowly reversing all backlight programming and pixel compensation. 741a595f28SAnthony Koo */ 7584034ad4SAnthony Koo #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 761a595f28SAnthony Koo 771a595f28SAnthony Koo /** 781a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 791a595f28SAnthony Koo * and undo all backlight programming and pixel compensation. 801a595f28SAnthony Koo */ 8184034ad4SAnthony Koo #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 821a595f28SAnthony Koo 831a595f28SAnthony Koo /** 841a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 851a595f28SAnthony Koo * and keep the current backlight programming and pixel compensation. 861a595f28SAnthony Koo */ 87d9beecfcSAnthony Koo #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 881a595f28SAnthony Koo 891a595f28SAnthony Koo /** 901a595f28SAnthony Koo * Flag from driver to set the current ABM pipe index or ABM operating level. 911a595f28SAnthony Koo */ 9284034ad4SAnthony Koo #define SET_ABM_PIPE_NORMAL 1 9384034ad4SAnthony Koo 941a595f28SAnthony Koo /** 951a595f28SAnthony Koo * Number of ambient light levels in ABM algorithm. 961a595f28SAnthony Koo */ 971a595f28SAnthony Koo #define NUM_AMBI_LEVEL 5 981a595f28SAnthony Koo 991a595f28SAnthony Koo /** 1001a595f28SAnthony Koo * Number of operating/aggression levels in ABM algorithm. 1011a595f28SAnthony Koo */ 1021a595f28SAnthony Koo #define NUM_AGGR_LEVEL 4 1031a595f28SAnthony Koo 1041a595f28SAnthony Koo /** 1051a595f28SAnthony Koo * Number of segments in the gamma curve. 1061a595f28SAnthony Koo */ 1071a595f28SAnthony Koo #define NUM_POWER_FN_SEGS 8 1081a595f28SAnthony Koo 1091a595f28SAnthony Koo /** 1101a595f28SAnthony Koo * Number of segments in the backlight curve. 1111a595f28SAnthony Koo */ 1121a595f28SAnthony Koo #define NUM_BL_CURVE_SEGS 16 1131a595f28SAnthony Koo 11484034ad4SAnthony Koo /* Maximum number of streams on any ASIC. */ 11584034ad4SAnthony Koo #define DMUB_MAX_STREAMS 6 11684034ad4SAnthony Koo 11784034ad4SAnthony Koo /* Maximum number of planes on any ASIC. */ 11884034ad4SAnthony Koo #define DMUB_MAX_PLANES 6 11984034ad4SAnthony Koo 12070732504SYongqiang Sun /* Trace buffer offset for entry */ 12170732504SYongqiang Sun #define TRACE_BUFFER_ENTRY_OFFSET 16 12270732504SYongqiang Sun 123592a6318SAnthony Koo /** 124f56c837aSMikita Lipski * 125f56c837aSMikita Lipski * PSR control version legacy 126f56c837aSMikita Lipski */ 127f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 128f56c837aSMikita Lipski /** 129f56c837aSMikita Lipski * PSR control version with multi edp support 130f56c837aSMikita Lipski */ 131f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 132f56c837aSMikita Lipski 133f56c837aSMikita Lipski 134f56c837aSMikita Lipski /** 13563de4f04SJake Wang * ABM control version legacy 136e922057bSJake Wang */ 13763de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 138e922057bSJake Wang 139e922057bSJake Wang /** 14063de4f04SJake Wang * ABM control version with multi edp support 141e922057bSJake Wang */ 14263de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 143e922057bSJake Wang 144e922057bSJake Wang /** 145592a6318SAnthony Koo * Physical framebuffer address location, 64-bit. 146592a6318SAnthony Koo */ 14784034ad4SAnthony Koo #ifndef PHYSICAL_ADDRESS_LOC 14884034ad4SAnthony Koo #define PHYSICAL_ADDRESS_LOC union large_integer 14984034ad4SAnthony Koo #endif 15084034ad4SAnthony Koo 151592a6318SAnthony Koo /** 152592a6318SAnthony Koo * OS/FW agnostic memcpy 153592a6318SAnthony Koo */ 15484034ad4SAnthony Koo #ifndef dmub_memcpy 15584034ad4SAnthony Koo #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 15684034ad4SAnthony Koo #endif 15784034ad4SAnthony Koo 158592a6318SAnthony Koo /** 159592a6318SAnthony Koo * OS/FW agnostic memset 160592a6318SAnthony Koo */ 16184034ad4SAnthony Koo #ifndef dmub_memset 16284034ad4SAnthony Koo #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 16384034ad4SAnthony Koo #endif 16484034ad4SAnthony Koo 165d9beecfcSAnthony Koo #if defined(__cplusplus) 166d9beecfcSAnthony Koo extern "C" { 167d9beecfcSAnthony Koo #endif 168d9beecfcSAnthony Koo 169592a6318SAnthony Koo /** 170592a6318SAnthony Koo * OS/FW agnostic udelay 171592a6318SAnthony Koo */ 17284034ad4SAnthony Koo #ifndef dmub_udelay 17384034ad4SAnthony Koo #define dmub_udelay(microseconds) udelay(microseconds) 17484034ad4SAnthony Koo #endif 17584034ad4SAnthony Koo 176592a6318SAnthony Koo /** 1770b51e7e8SAnthony Koo * Number of nanoseconds per DMUB tick. 1780b51e7e8SAnthony Koo * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default. 1790b51e7e8SAnthony Koo * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true. 1800b51e7e8SAnthony Koo */ 1810b51e7e8SAnthony Koo #define NS_PER_DMUB_TICK 10 1820b51e7e8SAnthony Koo 1830b51e7e8SAnthony Koo /** 184592a6318SAnthony Koo * union dmub_addr - DMUB physical/virtual 64-bit address. 185592a6318SAnthony Koo */ 18684034ad4SAnthony Koo union dmub_addr { 18784034ad4SAnthony Koo struct { 188592a6318SAnthony Koo uint32_t low_part; /**< Lower 32 bits */ 189592a6318SAnthony Koo uint32_t high_part; /**< Upper 32 bits */ 190592a6318SAnthony Koo } u; /*<< Low/high bit access */ 191592a6318SAnthony Koo uint64_t quad_part; /*<< 64 bit address */ 19284034ad4SAnthony Koo }; 19384034ad4SAnthony Koo 1941a595f28SAnthony Koo /** 1951a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 1961a595f28SAnthony Koo */ 19784034ad4SAnthony Koo union dmub_psr_debug_flags { 1981a595f28SAnthony Koo /** 1991a595f28SAnthony Koo * Debug flags. 2001a595f28SAnthony Koo */ 20184034ad4SAnthony Koo struct { 2021a595f28SAnthony Koo /** 2031a595f28SAnthony Koo * Enable visual confirm in FW. 2041a595f28SAnthony Koo */ 205447f3d0fSAnthony Koo uint32_t visual_confirm : 1; 2061a595f28SAnthony Koo /** 2071a595f28SAnthony Koo * Use HW Lock Mgr object to do HW locking in FW. 2081a595f28SAnthony Koo */ 209447f3d0fSAnthony Koo uint32_t use_hw_lock_mgr : 1; 2101a595f28SAnthony Koo 2111a595f28SAnthony Koo /** 2121a595f28SAnthony Koo * Unused. 2131a595f28SAnthony Koo * TODO: Remove. 2141a595f28SAnthony Koo */ 2158b3f6b98SAnthony Koo uint32_t log_line_nums : 1; 21684034ad4SAnthony Koo } bitfields; 21784034ad4SAnthony Koo 2181a595f28SAnthony Koo /** 2191a595f28SAnthony Koo * Union for debug flags. 2201a595f28SAnthony Koo */ 221447f3d0fSAnthony Koo uint32_t u32All; 22284034ad4SAnthony Koo }; 22384034ad4SAnthony Koo 2241a595f28SAnthony Koo /** 2251a595f28SAnthony Koo * DMUB feature capabilities. 2261a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2271a595f28SAnthony Koo */ 22834ba432cSAnthony Koo struct dmub_feature_caps { 2291a595f28SAnthony Koo /** 2301a595f28SAnthony Koo * Max PSR version supported by FW. 2311a595f28SAnthony Koo */ 23234ba432cSAnthony Koo uint8_t psr; 23334ba432cSAnthony Koo uint8_t reserved[7]; 23434ba432cSAnthony Koo }; 23534ba432cSAnthony Koo 23684034ad4SAnthony Koo #if defined(__cplusplus) 23784034ad4SAnthony Koo } 23884034ad4SAnthony Koo #endif 23984034ad4SAnthony Koo 24084034ad4SAnthony Koo //============================================================================== 24184034ad4SAnthony Koo //</DMUB_TYPES>================================================================= 24284034ad4SAnthony Koo //============================================================================== 24384034ad4SAnthony Koo //< DMUB_META>================================================================== 24484034ad4SAnthony Koo //============================================================================== 24584034ad4SAnthony Koo #pragma pack(push, 1) 24684034ad4SAnthony Koo 24784034ad4SAnthony Koo /* Magic value for identifying dmub_fw_meta_info */ 24884034ad4SAnthony Koo #define DMUB_FW_META_MAGIC 0x444D5542 24984034ad4SAnthony Koo 25084034ad4SAnthony Koo /* Offset from the end of the file to the dmub_fw_meta_info */ 25184034ad4SAnthony Koo #define DMUB_FW_META_OFFSET 0x24 25284034ad4SAnthony Koo 25384034ad4SAnthony Koo /** 25484034ad4SAnthony Koo * struct dmub_fw_meta_info - metadata associated with fw binary 25584034ad4SAnthony Koo * 25684034ad4SAnthony Koo * NOTE: This should be considered a stable API. Fields should 25784034ad4SAnthony Koo * not be repurposed or reordered. New fields should be 25884034ad4SAnthony Koo * added instead to extend the structure. 25984034ad4SAnthony Koo * 26084034ad4SAnthony Koo * @magic_value: magic value identifying DMUB firmware meta info 26184034ad4SAnthony Koo * @fw_region_size: size of the firmware state region 26284034ad4SAnthony Koo * @trace_buffer_size: size of the tracebuffer region 26384034ad4SAnthony Koo * @fw_version: the firmware version information 264b2265774SAnthony Koo * @dal_fw: 1 if the firmware is DAL 26584034ad4SAnthony Koo */ 26684034ad4SAnthony Koo struct dmub_fw_meta_info { 267592a6318SAnthony Koo uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 268592a6318SAnthony Koo uint32_t fw_region_size; /**< size of the firmware state region */ 269592a6318SAnthony Koo uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 270592a6318SAnthony Koo uint32_t fw_version; /**< the firmware version information */ 271592a6318SAnthony Koo uint8_t dal_fw; /**< 1 if the firmware is DAL */ 272592a6318SAnthony Koo uint8_t reserved[3]; /**< padding bits */ 27384034ad4SAnthony Koo }; 27484034ad4SAnthony Koo 275592a6318SAnthony Koo /** 276592a6318SAnthony Koo * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 277592a6318SAnthony Koo */ 27884034ad4SAnthony Koo union dmub_fw_meta { 279592a6318SAnthony Koo struct dmub_fw_meta_info info; /**< metadata info */ 280592a6318SAnthony Koo uint8_t reserved[64]; /**< padding bits */ 28184034ad4SAnthony Koo }; 28284034ad4SAnthony Koo 28384034ad4SAnthony Koo #pragma pack(pop) 284788408b7SAnthony Koo 28584034ad4SAnthony Koo //============================================================================== 2866b66208fSYongqiang Sun //< DMUB Trace Buffer>================================================================ 2876b66208fSYongqiang Sun //============================================================================== 288592a6318SAnthony Koo /** 289592a6318SAnthony Koo * dmub_trace_code_t - firmware trace code, 32-bits 290592a6318SAnthony Koo */ 2916b66208fSYongqiang Sun typedef uint32_t dmub_trace_code_t; 2926b66208fSYongqiang Sun 293592a6318SAnthony Koo /** 294592a6318SAnthony Koo * struct dmcub_trace_buf_entry - Firmware trace entry 295592a6318SAnthony Koo */ 2966b66208fSYongqiang Sun struct dmcub_trace_buf_entry { 297592a6318SAnthony Koo dmub_trace_code_t trace_code; /**< trace code for the event */ 298592a6318SAnthony Koo uint32_t tick_count; /**< the tick count at time of trace */ 299592a6318SAnthony Koo uint32_t param0; /**< trace defined parameter 0 */ 300592a6318SAnthony Koo uint32_t param1; /**< trace defined parameter 1 */ 3016b66208fSYongqiang Sun }; 3026b66208fSYongqiang Sun 3036b66208fSYongqiang Sun //============================================================================== 304788408b7SAnthony Koo //< DMUB_STATUS>================================================================ 305788408b7SAnthony Koo //============================================================================== 306788408b7SAnthony Koo 307788408b7SAnthony Koo /** 308788408b7SAnthony Koo * DMCUB scratch registers can be used to determine firmware status. 309788408b7SAnthony Koo * Current scratch register usage is as follows: 310788408b7SAnthony Koo * 311492dd8a8SAnthony Koo * SCRATCH0: FW Boot Status register 312021eaef8SAnthony Koo * SCRATCH5: LVTMA Status Register 313492dd8a8SAnthony Koo * SCRATCH15: FW Boot Options register 314788408b7SAnthony Koo */ 315788408b7SAnthony Koo 316592a6318SAnthony Koo /** 317592a6318SAnthony Koo * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 318592a6318SAnthony Koo */ 319492dd8a8SAnthony Koo union dmub_fw_boot_status { 320492dd8a8SAnthony Koo struct { 321592a6318SAnthony Koo uint32_t dal_fw : 1; /**< 1 if DAL FW */ 322592a6318SAnthony Koo uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 323592a6318SAnthony Koo uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 324592a6318SAnthony Koo uint32_t restore_required : 1; /**< 1 if driver should call restore */ 325592a6318SAnthony Koo } bits; /**< status bits */ 326592a6318SAnthony Koo uint32_t all; /**< 32-bit access to status bits */ 327492dd8a8SAnthony Koo }; 328492dd8a8SAnthony Koo 329592a6318SAnthony Koo /** 330592a6318SAnthony Koo * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 331592a6318SAnthony Koo */ 332492dd8a8SAnthony Koo enum dmub_fw_boot_status_bit { 333592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 334592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 335592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 336592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 3371e0958bbSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 338492dd8a8SAnthony Koo }; 339492dd8a8SAnthony Koo 340021eaef8SAnthony Koo /* Register bit definition for SCRATCH5 */ 341021eaef8SAnthony Koo union dmub_lvtma_status { 342021eaef8SAnthony Koo struct { 343021eaef8SAnthony Koo uint32_t psp_ok : 1; 344021eaef8SAnthony Koo uint32_t edp_on : 1; 345021eaef8SAnthony Koo uint32_t reserved : 30; 346021eaef8SAnthony Koo } bits; 347021eaef8SAnthony Koo uint32_t all; 348021eaef8SAnthony Koo }; 349021eaef8SAnthony Koo 350021eaef8SAnthony Koo enum dmub_lvtma_status_bit { 351021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 352021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 353021eaef8SAnthony Koo }; 354021eaef8SAnthony Koo 355592a6318SAnthony Koo /** 3561e0958bbSAnthony Koo * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 357592a6318SAnthony Koo */ 358492dd8a8SAnthony Koo union dmub_fw_boot_options { 359492dd8a8SAnthony Koo struct { 360592a6318SAnthony Koo uint32_t pemu_env : 1; /**< 1 if PEMU */ 361592a6318SAnthony Koo uint32_t fpga_env : 1; /**< 1 if FPGA */ 362592a6318SAnthony Koo uint32_t optimized_init : 1; /**< 1 if optimized init */ 363592a6318SAnthony Koo uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 364592a6318SAnthony Koo uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 365592a6318SAnthony Koo uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 366b04cb192SNicholas Kazlauskas uint32_t z10_disable: 1; /**< 1 to disable z10 */ 3671e0958bbSAnthony Koo uint32_t reserved2: 1; /**< reserved for an unreleased feature */ 368*d459b79bSAnthony Koo uint32_t reserved_unreleased1: 1; /**< reserved for an unreleased feature */ 3691e0958bbSAnthony Koo uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 3701e0958bbSAnthony Koo uint32_t reserved : 23; /**< reserved */ 371592a6318SAnthony Koo } bits; /**< boot bits */ 372592a6318SAnthony Koo uint32_t all; /**< 32-bit access to bits */ 373492dd8a8SAnthony Koo }; 374492dd8a8SAnthony Koo 375492dd8a8SAnthony Koo enum dmub_fw_boot_options_bit { 376592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 377592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 378592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 379492dd8a8SAnthony Koo }; 380492dd8a8SAnthony Koo 381788408b7SAnthony Koo //============================================================================== 382788408b7SAnthony Koo //</DMUB_STATUS>================================================================ 38384034ad4SAnthony Koo //============================================================================== 38484034ad4SAnthony Koo //< DMUB_VBIOS>================================================================= 38584034ad4SAnthony Koo //============================================================================== 38684034ad4SAnthony Koo 38784034ad4SAnthony Koo /* 388592a6318SAnthony Koo * enum dmub_cmd_vbios_type - VBIOS commands. 389592a6318SAnthony Koo * 39084034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 39184034ad4SAnthony Koo * Do not reuse or modify IDs. 39284034ad4SAnthony Koo */ 39384034ad4SAnthony Koo enum dmub_cmd_vbios_type { 394592a6318SAnthony Koo /** 395592a6318SAnthony Koo * Configures the DIG encoder. 396592a6318SAnthony Koo */ 39784034ad4SAnthony Koo DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 398592a6318SAnthony Koo /** 399592a6318SAnthony Koo * Controls the PHY. 400592a6318SAnthony Koo */ 40184034ad4SAnthony Koo DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 402592a6318SAnthony Koo /** 403592a6318SAnthony Koo * Sets the pixel clock/symbol clock. 404592a6318SAnthony Koo */ 40584034ad4SAnthony Koo DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 406592a6318SAnthony Koo /** 407592a6318SAnthony Koo * Enables or disables power gating. 408592a6318SAnthony Koo */ 40984034ad4SAnthony Koo DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 4102ac685bfSAnthony Koo DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 41184034ad4SAnthony Koo }; 41284034ad4SAnthony Koo 41384034ad4SAnthony Koo //============================================================================== 41484034ad4SAnthony Koo //</DMUB_VBIOS>================================================================= 41584034ad4SAnthony Koo //============================================================================== 41684034ad4SAnthony Koo //< DMUB_GPINT>================================================================= 41784034ad4SAnthony Koo //============================================================================== 41884034ad4SAnthony Koo 41984034ad4SAnthony Koo /** 42084034ad4SAnthony Koo * The shifts and masks below may alternatively be used to format and read 42184034ad4SAnthony Koo * the command register bits. 42284034ad4SAnthony Koo */ 42384034ad4SAnthony Koo 42484034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 42584034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_SHIFT 0 42684034ad4SAnthony Koo 42784034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 42884034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 42984034ad4SAnthony Koo 43084034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_MASK 0xF 43184034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_SHIFT 28 43284034ad4SAnthony Koo 43384034ad4SAnthony Koo /** 43484034ad4SAnthony Koo * Command responses. 43584034ad4SAnthony Koo */ 43684034ad4SAnthony Koo 437592a6318SAnthony Koo /** 438592a6318SAnthony Koo * Return response for DMUB_GPINT__STOP_FW command. 439592a6318SAnthony Koo */ 44084034ad4SAnthony Koo #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 44184034ad4SAnthony Koo 44284034ad4SAnthony Koo /** 443592a6318SAnthony Koo * union dmub_gpint_data_register - Format for sending a command via the GPINT. 44484034ad4SAnthony Koo */ 44584034ad4SAnthony Koo union dmub_gpint_data_register { 44684034ad4SAnthony Koo struct { 447592a6318SAnthony Koo uint32_t param : 16; /**< 16-bit parameter */ 448592a6318SAnthony Koo uint32_t command_code : 12; /**< GPINT command */ 449592a6318SAnthony Koo uint32_t status : 4; /**< Command status bit */ 450592a6318SAnthony Koo } bits; /**< GPINT bit access */ 451592a6318SAnthony Koo uint32_t all; /**< GPINT 32-bit access */ 45284034ad4SAnthony Koo }; 45384034ad4SAnthony Koo 45484034ad4SAnthony Koo /* 455592a6318SAnthony Koo * enum dmub_gpint_command - GPINT command to DMCUB FW 456592a6318SAnthony Koo * 45784034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 45884034ad4SAnthony Koo * Do not reuse or modify IDs. 45984034ad4SAnthony Koo */ 46084034ad4SAnthony Koo enum dmub_gpint_command { 461592a6318SAnthony Koo /** 462592a6318SAnthony Koo * Invalid command, ignored. 463592a6318SAnthony Koo */ 46484034ad4SAnthony Koo DMUB_GPINT__INVALID_COMMAND = 0, 465592a6318SAnthony Koo /** 466592a6318SAnthony Koo * DESC: Queries the firmware version. 467592a6318SAnthony Koo * RETURN: Firmware version. 468592a6318SAnthony Koo */ 46984034ad4SAnthony Koo DMUB_GPINT__GET_FW_VERSION = 1, 470592a6318SAnthony Koo /** 471592a6318SAnthony Koo * DESC: Halts the firmware. 472592a6318SAnthony Koo * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 473592a6318SAnthony Koo */ 47484034ad4SAnthony Koo DMUB_GPINT__STOP_FW = 2, 4751a595f28SAnthony Koo /** 4761a595f28SAnthony Koo * DESC: Get PSR state from FW. 4771a595f28SAnthony Koo * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 4781a595f28SAnthony Koo */ 47984034ad4SAnthony Koo DMUB_GPINT__GET_PSR_STATE = 7, 48080eba958SAnthony Koo /** 48180eba958SAnthony Koo * DESC: Notifies DMCUB of the currently active streams. 48280eba958SAnthony Koo * ARGS: Stream mask, 1 bit per active stream index. 48380eba958SAnthony Koo */ 48480eba958SAnthony Koo DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 4851a595f28SAnthony Koo /** 4861a595f28SAnthony Koo * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 4871a595f28SAnthony Koo * ARGS: We can measure residency from various points. The argument will specify the residency mode. 4881a595f28SAnthony Koo * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 4891a595f28SAnthony Koo * RETURN: PSR residency in milli-percent. 4901a595f28SAnthony Koo */ 491672251b2SAnthony Koo DMUB_GPINT__PSR_RESIDENCY = 9, 49284034ad4SAnthony Koo }; 49384034ad4SAnthony Koo 4940b51e7e8SAnthony Koo /** 4950b51e7e8SAnthony Koo * INBOX0 generic command definition 4960b51e7e8SAnthony Koo */ 4970b51e7e8SAnthony Koo union dmub_inbox0_cmd_common { 4980b51e7e8SAnthony Koo struct { 4990b51e7e8SAnthony Koo uint32_t command_code: 8; /**< INBOX0 command code */ 5000b51e7e8SAnthony Koo uint32_t param: 24; /**< 24-bit parameter */ 5010b51e7e8SAnthony Koo } bits; 5020b51e7e8SAnthony Koo uint32_t all; 5030b51e7e8SAnthony Koo }; 5040b51e7e8SAnthony Koo 5050b51e7e8SAnthony Koo /** 5060b51e7e8SAnthony Koo * INBOX0 hw_lock command definition 5070b51e7e8SAnthony Koo */ 5080b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw { 5090b51e7e8SAnthony Koo struct { 5100b51e7e8SAnthony Koo uint32_t command_code: 8; 5110b51e7e8SAnthony Koo 5120b51e7e8SAnthony Koo /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 5130b51e7e8SAnthony Koo uint32_t hw_lock_client: 1; 5140b51e7e8SAnthony Koo 5150b51e7e8SAnthony Koo /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 5160b51e7e8SAnthony Koo uint32_t otg_inst: 3; 5170b51e7e8SAnthony Koo uint32_t opp_inst: 3; 5180b51e7e8SAnthony Koo uint32_t dig_inst: 3; 5190b51e7e8SAnthony Koo 5200b51e7e8SAnthony Koo /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 5210b51e7e8SAnthony Koo uint32_t lock_pipe: 1; 5220b51e7e8SAnthony Koo uint32_t lock_cursor: 1; 5230b51e7e8SAnthony Koo uint32_t lock_dig: 1; 5240b51e7e8SAnthony Koo uint32_t triple_buffer_lock: 1; 5250b51e7e8SAnthony Koo 5260b51e7e8SAnthony Koo uint32_t lock: 1; /**< Lock */ 5270b51e7e8SAnthony Koo uint32_t should_release: 1; /**< Release */ 5280b51e7e8SAnthony Koo uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ 5290b51e7e8SAnthony Koo } bits; 5300b51e7e8SAnthony Koo uint32_t all; 5310b51e7e8SAnthony Koo }; 5320b51e7e8SAnthony Koo 5330b51e7e8SAnthony Koo union dmub_inbox0_data_register { 5340b51e7e8SAnthony Koo union dmub_inbox0_cmd_common inbox0_cmd_common; 5350b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 5360b51e7e8SAnthony Koo }; 5370b51e7e8SAnthony Koo 5380b51e7e8SAnthony Koo enum dmub_inbox0_command { 5390b51e7e8SAnthony Koo /** 5400b51e7e8SAnthony Koo * DESC: Invalid command, ignored. 5410b51e7e8SAnthony Koo */ 5420b51e7e8SAnthony Koo DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 5430b51e7e8SAnthony Koo /** 5440b51e7e8SAnthony Koo * DESC: Notification to acquire/release HW lock 5450b51e7e8SAnthony Koo * ARGS: 5460b51e7e8SAnthony Koo */ 5470b51e7e8SAnthony Koo DMUB_INBOX0_CMD__HW_LOCK = 1, 5480b51e7e8SAnthony Koo }; 54984034ad4SAnthony Koo //============================================================================== 55084034ad4SAnthony Koo //</DMUB_GPINT>================================================================= 55184034ad4SAnthony Koo //============================================================================== 55284034ad4SAnthony Koo //< DMUB_CMD>=================================================================== 55384034ad4SAnthony Koo //============================================================================== 55484034ad4SAnthony Koo 555592a6318SAnthony Koo /** 556592a6318SAnthony Koo * Size in bytes of each DMUB command. 557592a6318SAnthony Koo */ 5587c008829SNicholas Kazlauskas #define DMUB_RB_CMD_SIZE 64 559592a6318SAnthony Koo 560592a6318SAnthony Koo /** 561592a6318SAnthony Koo * Maximum number of items in the DMUB ringbuffer. 562592a6318SAnthony Koo */ 5637c008829SNicholas Kazlauskas #define DMUB_RB_MAX_ENTRY 128 564592a6318SAnthony Koo 565592a6318SAnthony Koo /** 566592a6318SAnthony Koo * Ringbuffer size in bytes. 567592a6318SAnthony Koo */ 5687c008829SNicholas Kazlauskas #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 569592a6318SAnthony Koo 570592a6318SAnthony Koo /** 571592a6318SAnthony Koo * REG_SET mask for reg offload. 572592a6318SAnthony Koo */ 5737c008829SNicholas Kazlauskas #define REG_SET_MASK 0xFFFF 5747c008829SNicholas Kazlauskas 575d4bbcecbSNicholas Kazlauskas /* 576592a6318SAnthony Koo * enum dmub_cmd_type - DMUB inbox command. 577592a6318SAnthony Koo * 578d4bbcecbSNicholas Kazlauskas * Command IDs should be treated as stable ABI. 579d4bbcecbSNicholas Kazlauskas * Do not reuse or modify IDs. 580d4bbcecbSNicholas Kazlauskas */ 581d4bbcecbSNicholas Kazlauskas enum dmub_cmd_type { 582592a6318SAnthony Koo /** 583592a6318SAnthony Koo * Invalid command. 584592a6318SAnthony Koo */ 585d4bbcecbSNicholas Kazlauskas DMUB_CMD__NULL = 0, 586592a6318SAnthony Koo /** 587592a6318SAnthony Koo * Read modify write register sequence offload. 588592a6318SAnthony Koo */ 589d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 590592a6318SAnthony Koo /** 591592a6318SAnthony Koo * Field update register sequence offload. 592592a6318SAnthony Koo */ 593d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 594592a6318SAnthony Koo /** 595592a6318SAnthony Koo * Burst write sequence offload. 596592a6318SAnthony Koo */ 597d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 598592a6318SAnthony Koo /** 599592a6318SAnthony Koo * Reg wait sequence offload. 600592a6318SAnthony Koo */ 601d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_REG_WAIT = 4, 602592a6318SAnthony Koo /** 603592a6318SAnthony Koo * Workaround to avoid HUBP underflow during NV12 playback. 604592a6318SAnthony Koo */ 605bae9c49bSYongqiang Sun DMUB_CMD__PLAT_54186_WA = 5, 6061a595f28SAnthony Koo /** 6071a595f28SAnthony Koo * Command type used to query FW feature caps. 6081a595f28SAnthony Koo */ 60934ba432cSAnthony Koo DMUB_CMD__QUERY_FEATURE_CAPS = 6, 6101a595f28SAnthony Koo /** 6111a595f28SAnthony Koo * Command type used for all PSR commands. 6121a595f28SAnthony Koo */ 613d4bbcecbSNicholas Kazlauskas DMUB_CMD__PSR = 64, 614592a6318SAnthony Koo /** 615592a6318SAnthony Koo * Command type used for all MALL commands. 616592a6318SAnthony Koo */ 61752f2e83eSBhawanpreet Lakha DMUB_CMD__MALL = 65, 6181a595f28SAnthony Koo /** 6191a595f28SAnthony Koo * Command type used for all ABM commands. 6201a595f28SAnthony Koo */ 621e6ea8c34SWyatt Wood DMUB_CMD__ABM = 66, 6221a595f28SAnthony Koo /** 6231a595f28SAnthony Koo * Command type used for HW locking in FW. 6241a595f28SAnthony Koo */ 625788408b7SAnthony Koo DMUB_CMD__HW_LOCK = 69, 6261a595f28SAnthony Koo /** 6271a595f28SAnthony Koo * Command type used to access DP AUX. 6281a595f28SAnthony Koo */ 629d9beecfcSAnthony Koo DMUB_CMD__DP_AUX_ACCESS = 70, 6301a595f28SAnthony Koo /** 6311a595f28SAnthony Koo * Command type used for OUTBOX1 notification enable 6321a595f28SAnthony Koo */ 633d9beecfcSAnthony Koo DMUB_CMD__OUTBOX1_ENABLE = 71, 634b04cb192SNicholas Kazlauskas /** 635b04cb192SNicholas Kazlauskas * Command type used for all idle optimization commands. 636b04cb192SNicholas Kazlauskas */ 637b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT = 72, 638b04cb192SNicholas Kazlauskas /** 639b04cb192SNicholas Kazlauskas * Command type used for all clock manager commands. 640b04cb192SNicholas Kazlauskas */ 641b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR = 73, 642b04cb192SNicholas Kazlauskas /** 643b04cb192SNicholas Kazlauskas * Command type used for all panel control commands. 644b04cb192SNicholas Kazlauskas */ 645b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL = 74, 646592a6318SAnthony Koo /** 647021eaef8SAnthony Koo * Command type used for EDID CEA parsing 648021eaef8SAnthony Koo */ 649021eaef8SAnthony Koo DMUB_CMD__EDID_CEA = 79, 650021eaef8SAnthony Koo /** 651592a6318SAnthony Koo * Command type used for all VBIOS interface commands. 652592a6318SAnthony Koo */ 653d4bbcecbSNicholas Kazlauskas DMUB_CMD__VBIOS = 128, 6547c008829SNicholas Kazlauskas }; 6557c008829SNicholas Kazlauskas 656592a6318SAnthony Koo /** 657592a6318SAnthony Koo * enum dmub_out_cmd_type - DMUB outbox commands. 658592a6318SAnthony Koo */ 6593b37260bSAnthony Koo enum dmub_out_cmd_type { 660592a6318SAnthony Koo /** 661592a6318SAnthony Koo * Invalid outbox command, ignored. 662592a6318SAnthony Koo */ 6633b37260bSAnthony Koo DMUB_OUT_CMD__NULL = 0, 6641a595f28SAnthony Koo /** 6651a595f28SAnthony Koo * Command type used for DP AUX Reply data notification 6661a595f28SAnthony Koo */ 667d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_AUX_REPLY = 1, 6683b37260bSAnthony Koo }; 6693b37260bSAnthony Koo 6707c008829SNicholas Kazlauskas #pragma pack(push, 1) 6717c008829SNicholas Kazlauskas 672592a6318SAnthony Koo /** 673592a6318SAnthony Koo * struct dmub_cmd_header - Common command header fields. 674592a6318SAnthony Koo */ 6757c008829SNicholas Kazlauskas struct dmub_cmd_header { 676592a6318SAnthony Koo unsigned int type : 8; /**< command type */ 677592a6318SAnthony Koo unsigned int sub_type : 8; /**< command sub type */ 678592a6318SAnthony Koo unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 6790b51e7e8SAnthony Koo unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 6800b51e7e8SAnthony Koo unsigned int reserved0 : 6; /**< reserved bits */ 681592a6318SAnthony Koo unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 682592a6318SAnthony Koo unsigned int reserved1 : 2; /**< reserved bits */ 6837c008829SNicholas Kazlauskas }; 6847c008829SNicholas Kazlauskas 6857c008829SNicholas Kazlauskas /* 686592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write 6877c008829SNicholas Kazlauskas * 6887c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 5 sets of read modify writes, 6897c008829SNicholas Kazlauskas * each take 3 dwords. 6907c008829SNicholas Kazlauskas * 6917c008829SNicholas Kazlauskas * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 6927c008829SNicholas Kazlauskas * 6937c008829SNicholas Kazlauskas * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 6947c008829SNicholas Kazlauskas * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 6957c008829SNicholas Kazlauskas */ 6967c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence { 697592a6318SAnthony Koo uint32_t addr; /**< register address */ 698592a6318SAnthony Koo uint32_t modify_mask; /**< modify mask */ 699592a6318SAnthony Koo uint32_t modify_value; /**< modify value */ 7007c008829SNicholas Kazlauskas }; 7017c008829SNicholas Kazlauskas 702592a6318SAnthony Koo /** 703592a6318SAnthony Koo * Maximum number of ops in read modify write sequence. 704592a6318SAnthony Koo */ 7057c008829SNicholas Kazlauskas #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 706592a6318SAnthony Koo 707592a6318SAnthony Koo /** 708592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 709592a6318SAnthony Koo */ 7107c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write { 711592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 712592a6318SAnthony Koo /** 713592a6318SAnthony Koo * Read modify write sequence. 714592a6318SAnthony Koo */ 7157c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 7167c008829SNicholas Kazlauskas }; 7177c008829SNicholas Kazlauskas 7187c008829SNicholas Kazlauskas /* 7197c008829SNicholas Kazlauskas * Update a register with specified masks and values sequeunce 7207c008829SNicholas Kazlauskas * 7217c008829SNicholas Kazlauskas * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 7227c008829SNicholas Kazlauskas * 7237c008829SNicholas Kazlauskas * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 7247c008829SNicholas Kazlauskas * 7257c008829SNicholas Kazlauskas * 7267c008829SNicholas Kazlauskas * USE CASE: 7277c008829SNicholas Kazlauskas * 1. auto-increment register where additional read would update pointer and produce wrong result 7287c008829SNicholas Kazlauskas * 2. toggle a bit without read in the middle 7297c008829SNicholas Kazlauskas */ 7307c008829SNicholas Kazlauskas 7317c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence { 732592a6318SAnthony Koo uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 733592a6318SAnthony Koo uint32_t modify_value; /**< value to update with */ 7347c008829SNicholas Kazlauskas }; 7357c008829SNicholas Kazlauskas 736592a6318SAnthony Koo /** 737592a6318SAnthony Koo * Maximum number of ops in field update sequence. 738592a6318SAnthony Koo */ 7397c008829SNicholas Kazlauskas #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 740592a6318SAnthony Koo 741592a6318SAnthony Koo /** 742592a6318SAnthony Koo * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 743592a6318SAnthony Koo */ 7447c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence { 745592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 746592a6318SAnthony Koo uint32_t addr; /**< register address */ 747592a6318SAnthony Koo /** 748592a6318SAnthony Koo * Field update sequence. 749592a6318SAnthony Koo */ 7507c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 7517c008829SNicholas Kazlauskas }; 7527c008829SNicholas Kazlauskas 753592a6318SAnthony Koo 754592a6318SAnthony Koo /** 755592a6318SAnthony Koo * Maximum number of burst write values. 756592a6318SAnthony Koo */ 757592a6318SAnthony Koo #define DMUB_BURST_WRITE_VALUES__MAX 14 758592a6318SAnthony Koo 7597c008829SNicholas Kazlauskas /* 760592a6318SAnthony Koo * struct dmub_rb_cmd_burst_write - Burst write 7617c008829SNicholas Kazlauskas * 7627c008829SNicholas Kazlauskas * support use case such as writing out LUTs. 7637c008829SNicholas Kazlauskas * 7647c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 14 values to write to given address 7657c008829SNicholas Kazlauskas * 7667c008829SNicholas Kazlauskas * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 7677c008829SNicholas Kazlauskas */ 7687c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write { 769592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 770592a6318SAnthony Koo uint32_t addr; /**< register start address */ 771592a6318SAnthony Koo /** 772592a6318SAnthony Koo * Burst write register values. 773592a6318SAnthony Koo */ 7747c008829SNicholas Kazlauskas uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 7757c008829SNicholas Kazlauskas }; 7767c008829SNicholas Kazlauskas 777592a6318SAnthony Koo /** 778592a6318SAnthony Koo * struct dmub_rb_cmd_common - Common command header 779592a6318SAnthony Koo */ 7807c008829SNicholas Kazlauskas struct dmub_rb_cmd_common { 781592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 782592a6318SAnthony Koo /** 783592a6318SAnthony Koo * Padding to RB_CMD_SIZE 784592a6318SAnthony Koo */ 7857c008829SNicholas Kazlauskas uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 7867c008829SNicholas Kazlauskas }; 7877c008829SNicholas Kazlauskas 788592a6318SAnthony Koo /** 789592a6318SAnthony Koo * struct dmub_cmd_reg_wait_data - Register wait data 790592a6318SAnthony Koo */ 7917c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data { 792592a6318SAnthony Koo uint32_t addr; /**< Register address */ 793592a6318SAnthony Koo uint32_t mask; /**< Mask for register bits */ 794592a6318SAnthony Koo uint32_t condition_field_value; /**< Value to wait for */ 795592a6318SAnthony Koo uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 7967c008829SNicholas Kazlauskas }; 7977c008829SNicholas Kazlauskas 798592a6318SAnthony Koo /** 799592a6318SAnthony Koo * struct dmub_rb_cmd_reg_wait - Register wait command 800592a6318SAnthony Koo */ 8017c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait { 802592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 803592a6318SAnthony Koo struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 8047c008829SNicholas Kazlauskas }; 8057c008829SNicholas Kazlauskas 806592a6318SAnthony Koo /** 807592a6318SAnthony Koo * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 808592a6318SAnthony Koo * 809592a6318SAnthony Koo * Reprograms surface parameters to avoid underflow. 810592a6318SAnthony Koo */ 811bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa { 812592a6318SAnthony Koo uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 813592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 814592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 815592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 816592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 81722aa5614SYongqiang Sun struct { 818592a6318SAnthony Koo uint8_t hubp_inst : 4; /**< HUBP instance */ 819592a6318SAnthony Koo uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 820592a6318SAnthony Koo uint8_t immediate :1; /**< Immediate flip */ 821592a6318SAnthony Koo uint8_t vmid : 4; /**< VMID */ 822592a6318SAnthony Koo uint8_t grph_stereo : 1; /**< 1 if stereo */ 823592a6318SAnthony Koo uint32_t reserved : 21; /**< Reserved */ 824592a6318SAnthony Koo } flip_params; /**< Pageflip parameters */ 825592a6318SAnthony Koo uint32_t reserved[9]; /**< Reserved bits */ 8268c019253SYongqiang Sun }; 8278c019253SYongqiang Sun 828592a6318SAnthony Koo /** 829592a6318SAnthony Koo * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 830592a6318SAnthony Koo */ 831bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa { 832592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 833592a6318SAnthony Koo struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 8348c019253SYongqiang Sun }; 8358c019253SYongqiang Sun 836592a6318SAnthony Koo /** 837592a6318SAnthony Koo * struct dmub_rb_cmd_mall - MALL command data. 838592a6318SAnthony Koo */ 83952f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall { 840592a6318SAnthony Koo struct dmub_cmd_header header; /**< Common command header */ 841592a6318SAnthony Koo union dmub_addr cursor_copy_src; /**< Cursor copy address */ 842592a6318SAnthony Koo union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 843592a6318SAnthony Koo uint32_t tmr_delay; /**< Timer delay */ 844592a6318SAnthony Koo uint32_t tmr_scale; /**< Timer scale */ 845592a6318SAnthony Koo uint16_t cursor_width; /**< Cursor width in pixels */ 846592a6318SAnthony Koo uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 847592a6318SAnthony Koo uint16_t cursor_height; /**< Cursor height in pixels */ 848592a6318SAnthony Koo uint8_t cursor_bpp; /**< Cursor bits per pixel */ 849592a6318SAnthony Koo uint8_t debug_bits; /**< Debug bits */ 850ea7154d8SBhawanpreet Lakha 851592a6318SAnthony Koo uint8_t reserved1; /**< Reserved bits */ 852592a6318SAnthony Koo uint8_t reserved2; /**< Reserved bits */ 85352f2e83eSBhawanpreet Lakha }; 85452f2e83eSBhawanpreet Lakha 855b04cb192SNicholas Kazlauskas /** 856b04cb192SNicholas Kazlauskas * enum dmub_cmd_idle_opt_type - Idle optimization command type. 857b04cb192SNicholas Kazlauskas */ 858b04cb192SNicholas Kazlauskas enum dmub_cmd_idle_opt_type { 859b04cb192SNicholas Kazlauskas /** 860b04cb192SNicholas Kazlauskas * DCN hardware restore. 861b04cb192SNicholas Kazlauskas */ 862b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 863b04cb192SNicholas Kazlauskas }; 864b04cb192SNicholas Kazlauskas 865b04cb192SNicholas Kazlauskas /** 866b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 867b04cb192SNicholas Kazlauskas */ 868b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore { 869b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 870b04cb192SNicholas Kazlauskas }; 871b04cb192SNicholas Kazlauskas 872b04cb192SNicholas Kazlauskas /** 873b04cb192SNicholas Kazlauskas * struct dmub_clocks - Clock update notification. 874b04cb192SNicholas Kazlauskas */ 875b04cb192SNicholas Kazlauskas struct dmub_clocks { 876b04cb192SNicholas Kazlauskas uint32_t dispclk_khz; /**< dispclk kHz */ 877b04cb192SNicholas Kazlauskas uint32_t dppclk_khz; /**< dppclk kHz */ 878b04cb192SNicholas Kazlauskas uint32_t dcfclk_khz; /**< dcfclk kHz */ 879b04cb192SNicholas Kazlauskas uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 880b04cb192SNicholas Kazlauskas }; 881b04cb192SNicholas Kazlauskas 882b04cb192SNicholas Kazlauskas /** 883b04cb192SNicholas Kazlauskas * enum dmub_cmd_clk_mgr_type - Clock manager commands. 884b04cb192SNicholas Kazlauskas */ 885b04cb192SNicholas Kazlauskas enum dmub_cmd_clk_mgr_type { 886b04cb192SNicholas Kazlauskas /** 887b04cb192SNicholas Kazlauskas * Notify DMCUB of clock update. 888b04cb192SNicholas Kazlauskas */ 889b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 890b04cb192SNicholas Kazlauskas }; 891b04cb192SNicholas Kazlauskas 892b04cb192SNicholas Kazlauskas /** 893b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 894b04cb192SNicholas Kazlauskas */ 895b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks { 896b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 897b04cb192SNicholas Kazlauskas struct dmub_clocks clocks; /**< clock data */ 898b04cb192SNicholas Kazlauskas }; 8998fe44c08SAlex Deucher 900592a6318SAnthony Koo /** 901592a6318SAnthony Koo * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 902592a6318SAnthony Koo */ 9037c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data { 904592a6318SAnthony Koo union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 9057c008829SNicholas Kazlauskas }; 9067c008829SNicholas Kazlauskas 907592a6318SAnthony Koo /** 908592a6318SAnthony Koo * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 909592a6318SAnthony Koo */ 9107c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control { 911592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 912592a6318SAnthony Koo struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 9137c008829SNicholas Kazlauskas }; 9147c008829SNicholas Kazlauskas 915592a6318SAnthony Koo /** 916592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 917592a6318SAnthony Koo */ 9187c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data { 919592a6318SAnthony Koo struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 9207c008829SNicholas Kazlauskas }; 9217c008829SNicholas Kazlauskas 922592a6318SAnthony Koo /** 923592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 924592a6318SAnthony Koo */ 9257c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock { 926592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 927592a6318SAnthony Koo struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 9287c008829SNicholas Kazlauskas }; 9297c008829SNicholas Kazlauskas 930592a6318SAnthony Koo /** 931592a6318SAnthony Koo * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 932592a6318SAnthony Koo */ 9337c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data { 934592a6318SAnthony Koo struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 9357c008829SNicholas Kazlauskas }; 9367c008829SNicholas Kazlauskas 937592a6318SAnthony Koo /** 938592a6318SAnthony Koo * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 939592a6318SAnthony Koo */ 9407c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating { 941592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 942592a6318SAnthony Koo struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 9437c008829SNicholas Kazlauskas }; 9447c008829SNicholas Kazlauskas 945592a6318SAnthony Koo /** 946592a6318SAnthony Koo * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 947592a6318SAnthony Koo */ 948d448521eSAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 { 949d448521eSAnthony Koo uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 950d448521eSAnthony Koo uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 951d448521eSAnthony Koo union { 952d448521eSAnthony Koo uint8_t digmode; /**< enum atom_encode_mode_def */ 953d448521eSAnthony Koo uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 954d448521eSAnthony Koo } mode_laneset; 955d448521eSAnthony Koo uint8_t lanenum; /**< Number of lanes */ 956d448521eSAnthony Koo union { 957d448521eSAnthony Koo uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 958d448521eSAnthony Koo } symclk_units; 959d448521eSAnthony Koo uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 960d448521eSAnthony Koo uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 961d448521eSAnthony Koo uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 962d448521eSAnthony Koo uint8_t reserved0; /**< For future use */ 963d448521eSAnthony Koo uint8_t reserved1; /**< For future use */ 964d448521eSAnthony Koo uint8_t reserved2[3]; /**< For future use */ 965d448521eSAnthony Koo uint32_t reserved3[11]; /**< For future use */ 966d448521eSAnthony Koo }; 967d448521eSAnthony Koo 968592a6318SAnthony Koo /** 969592a6318SAnthony Koo * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 970592a6318SAnthony Koo */ 971d448521eSAnthony Koo union dmub_cmd_dig1_transmitter_control_data { 972592a6318SAnthony Koo struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 973592a6318SAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 9747c008829SNicholas Kazlauskas }; 9757c008829SNicholas Kazlauskas 976592a6318SAnthony Koo /** 977592a6318SAnthony Koo * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 978592a6318SAnthony Koo */ 9797c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control { 980592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 981592a6318SAnthony Koo union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 9827c008829SNicholas Kazlauskas }; 9837c008829SNicholas Kazlauskas 984592a6318SAnthony Koo /** 985592a6318SAnthony Koo * struct dmub_rb_cmd_dpphy_init - DPPHY init. 986592a6318SAnthony Koo */ 9877c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init { 988592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 989592a6318SAnthony Koo uint8_t reserved[60]; /**< reserved bits */ 9907c008829SNicholas Kazlauskas }; 9917c008829SNicholas Kazlauskas 9921a595f28SAnthony Koo /** 9931a595f28SAnthony Koo * enum dp_aux_request_action - DP AUX request command listing. 9941a595f28SAnthony Koo * 9951a595f28SAnthony Koo * 4 AUX request command bits are shifted to high nibble. 9961a595f28SAnthony Koo */ 997d9beecfcSAnthony Koo enum dp_aux_request_action { 9981a595f28SAnthony Koo /** I2C-over-AUX write request */ 999d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 10001a595f28SAnthony Koo /** I2C-over-AUX read request */ 1001d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ = 0x10, 10021a595f28SAnthony Koo /** I2C-over-AUX write status request */ 1003d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 10041a595f28SAnthony Koo /** I2C-over-AUX write request with MOT=1 */ 1005d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 10061a595f28SAnthony Koo /** I2C-over-AUX read request with MOT=1 */ 1007d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 10081a595f28SAnthony Koo /** I2C-over-AUX write status request with MOT=1 */ 1009d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 10101a595f28SAnthony Koo /** Native AUX write request */ 1011d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 10121a595f28SAnthony Koo /** Native AUX read request */ 1013d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1014d9beecfcSAnthony Koo }; 1015d9beecfcSAnthony Koo 10161a595f28SAnthony Koo /** 10171a595f28SAnthony Koo * enum aux_return_code_type - DP AUX process return code listing. 10181a595f28SAnthony Koo */ 1019fd0f1d21SAnthony Koo enum aux_return_code_type { 10201a595f28SAnthony Koo /** AUX process succeeded */ 1021fd0f1d21SAnthony Koo AUX_RET_SUCCESS = 0, 10221a595f28SAnthony Koo /** AUX process failed with unknown reason */ 1023b6402afeSAnthony Koo AUX_RET_ERROR_UNKNOWN, 10241a595f28SAnthony Koo /** AUX process completed with invalid reply */ 1025b6402afeSAnthony Koo AUX_RET_ERROR_INVALID_REPLY, 10261a595f28SAnthony Koo /** AUX process timed out */ 1027fd0f1d21SAnthony Koo AUX_RET_ERROR_TIMEOUT, 10281a595f28SAnthony Koo /** HPD was low during AUX process */ 1029b6402afeSAnthony Koo AUX_RET_ERROR_HPD_DISCON, 10301a595f28SAnthony Koo /** Failed to acquire AUX engine */ 1031b6402afeSAnthony Koo AUX_RET_ERROR_ENGINE_ACQUIRE, 10321a595f28SAnthony Koo /** AUX request not supported */ 1033fd0f1d21SAnthony Koo AUX_RET_ERROR_INVALID_OPERATION, 10341a595f28SAnthony Koo /** AUX process not available */ 1035fd0f1d21SAnthony Koo AUX_RET_ERROR_PROTOCOL_ERROR, 1036fd0f1d21SAnthony Koo }; 1037fd0f1d21SAnthony Koo 10381a595f28SAnthony Koo /** 10391a595f28SAnthony Koo * enum aux_channel_type - DP AUX channel type listing. 10401a595f28SAnthony Koo */ 1041b6402afeSAnthony Koo enum aux_channel_type { 10421a595f28SAnthony Koo /** AUX thru Legacy DP AUX */ 1043b6402afeSAnthony Koo AUX_CHANNEL_LEGACY_DDC, 10441a595f28SAnthony Koo /** AUX thru DPIA DP tunneling */ 1045b6402afeSAnthony Koo AUX_CHANNEL_DPIA 1046b6402afeSAnthony Koo }; 1047b6402afeSAnthony Koo 10481a595f28SAnthony Koo /** 10491a595f28SAnthony Koo * struct aux_transaction_parameters - DP AUX request transaction data 10501a595f28SAnthony Koo */ 1051d9beecfcSAnthony Koo struct aux_transaction_parameters { 10521a595f28SAnthony Koo uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 10531a595f28SAnthony Koo uint8_t action; /**< enum dp_aux_request_action */ 10541a595f28SAnthony Koo uint8_t length; /**< DP AUX request data length */ 10551a595f28SAnthony Koo uint8_t reserved; /**< For future use */ 10561a595f28SAnthony Koo uint32_t address; /**< DP AUX address */ 10571a595f28SAnthony Koo uint8_t data[16]; /**< DP AUX write data */ 1058d9beecfcSAnthony Koo }; 1059d9beecfcSAnthony Koo 10601a595f28SAnthony Koo /** 10611a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 10621a595f28SAnthony Koo */ 1063d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data { 10641a595f28SAnthony Koo uint8_t instance; /**< AUX instance or DPIA instance */ 10651a595f28SAnthony Koo uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 10661a595f28SAnthony Koo uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 10671a595f28SAnthony Koo uint8_t reserved0; /**< For future use */ 10681a595f28SAnthony Koo uint16_t timeout; /**< timeout time in us */ 10691a595f28SAnthony Koo uint16_t reserved1; /**< For future use */ 10701a595f28SAnthony Koo enum aux_channel_type type; /**< enum aux_channel_type */ 10711a595f28SAnthony Koo struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1072d9beecfcSAnthony Koo }; 1073d9beecfcSAnthony Koo 10741a595f28SAnthony Koo /** 10751a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 10761a595f28SAnthony Koo */ 1077d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access { 10781a595f28SAnthony Koo /** 10791a595f28SAnthony Koo * Command header. 10801a595f28SAnthony Koo */ 1081d9beecfcSAnthony Koo struct dmub_cmd_header header; 10821a595f28SAnthony Koo /** 10831a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 10841a595f28SAnthony Koo */ 1085d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data aux_control; 1086d9beecfcSAnthony Koo }; 1087d9beecfcSAnthony Koo 10881a595f28SAnthony Koo /** 10891a595f28SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 10901a595f28SAnthony Koo */ 1091d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable { 10921a595f28SAnthony Koo /** 10931a595f28SAnthony Koo * Command header. 10941a595f28SAnthony Koo */ 1095d9beecfcSAnthony Koo struct dmub_cmd_header header; 10961a595f28SAnthony Koo /** 10971a595f28SAnthony Koo * enable: 0x0 -> disable outbox1 notification (default value) 10981a595f28SAnthony Koo * 0x1 -> enable outbox1 notification 10991a595f28SAnthony Koo */ 1100d9beecfcSAnthony Koo uint32_t enable; 1101d9beecfcSAnthony Koo }; 1102d9beecfcSAnthony Koo 1103d9beecfcSAnthony Koo /* DP AUX Reply command - OutBox Cmd */ 11041a595f28SAnthony Koo /** 11051a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 11061a595f28SAnthony Koo */ 1107d9beecfcSAnthony Koo struct aux_reply_data { 11081a595f28SAnthony Koo /** 11091a595f28SAnthony Koo * Aux cmd 11101a595f28SAnthony Koo */ 1111d9beecfcSAnthony Koo uint8_t command; 11121a595f28SAnthony Koo /** 11131a595f28SAnthony Koo * Aux reply data length (max: 16 bytes) 11141a595f28SAnthony Koo */ 1115d9beecfcSAnthony Koo uint8_t length; 11161a595f28SAnthony Koo /** 11171a595f28SAnthony Koo * Alignment only 11181a595f28SAnthony Koo */ 1119d9beecfcSAnthony Koo uint8_t pad[2]; 11201a595f28SAnthony Koo /** 11211a595f28SAnthony Koo * Aux reply data 11221a595f28SAnthony Koo */ 1123d9beecfcSAnthony Koo uint8_t data[16]; 1124d9beecfcSAnthony Koo }; 1125d9beecfcSAnthony Koo 11261a595f28SAnthony Koo /** 11271a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 11281a595f28SAnthony Koo */ 1129d9beecfcSAnthony Koo struct aux_reply_control_data { 11301a595f28SAnthony Koo /** 11311a595f28SAnthony Koo * Reserved for future use 11321a595f28SAnthony Koo */ 1133d9beecfcSAnthony Koo uint32_t handle; 11341a595f28SAnthony Koo /** 11351a595f28SAnthony Koo * Aux Instance 11361a595f28SAnthony Koo */ 1137b6402afeSAnthony Koo uint8_t instance; 11381a595f28SAnthony Koo /** 11391a595f28SAnthony Koo * Aux transaction result: definition in enum aux_return_code_type 11401a595f28SAnthony Koo */ 1141d9beecfcSAnthony Koo uint8_t result; 11421a595f28SAnthony Koo /** 11431a595f28SAnthony Koo * Alignment only 11441a595f28SAnthony Koo */ 1145d9beecfcSAnthony Koo uint16_t pad; 1146d9beecfcSAnthony Koo }; 1147d9beecfcSAnthony Koo 11481a595f28SAnthony Koo /** 11491a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 11501a595f28SAnthony Koo */ 1151d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply { 11521a595f28SAnthony Koo /** 11531a595f28SAnthony Koo * Command header. 11541a595f28SAnthony Koo */ 1155d9beecfcSAnthony Koo struct dmub_cmd_header header; 11561a595f28SAnthony Koo /** 11571a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 11581a595f28SAnthony Koo */ 1159d9beecfcSAnthony Koo struct aux_reply_control_data control; 11601a595f28SAnthony Koo /** 11611a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 11621a595f28SAnthony Koo */ 1163d9beecfcSAnthony Koo struct aux_reply_data reply_data; 1164d9beecfcSAnthony Koo }; 1165d9beecfcSAnthony Koo 1166fd0f1d21SAnthony Koo /* DP HPD Notify command - OutBox Cmd */ 11671a595f28SAnthony Koo /** 11681a595f28SAnthony Koo * DP HPD Type 11691a595f28SAnthony Koo */ 1170fd0f1d21SAnthony Koo enum dp_hpd_type { 11711a595f28SAnthony Koo /** 11721a595f28SAnthony Koo * Normal DP HPD 11731a595f28SAnthony Koo */ 1174fd0f1d21SAnthony Koo DP_HPD = 0, 11751a595f28SAnthony Koo /** 11761a595f28SAnthony Koo * DP HPD short pulse 11771a595f28SAnthony Koo */ 1178fd0f1d21SAnthony Koo DP_IRQ 1179fd0f1d21SAnthony Koo }; 1180fd0f1d21SAnthony Koo 11811a595f28SAnthony Koo /** 11821a595f28SAnthony Koo * DP HPD Status 11831a595f28SAnthony Koo */ 1184fd0f1d21SAnthony Koo enum dp_hpd_status { 11851a595f28SAnthony Koo /** 11861a595f28SAnthony Koo * DP_HPD status low 11871a595f28SAnthony Koo */ 1188fd0f1d21SAnthony Koo DP_HPD_UNPLUG = 0, 11891a595f28SAnthony Koo /** 11901a595f28SAnthony Koo * DP_HPD status high 11911a595f28SAnthony Koo */ 1192fd0f1d21SAnthony Koo DP_HPD_PLUG 1193fd0f1d21SAnthony Koo }; 1194fd0f1d21SAnthony Koo 11951a595f28SAnthony Koo /** 11961a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 11971a595f28SAnthony Koo */ 1198d9beecfcSAnthony Koo struct dp_hpd_data { 11991a595f28SAnthony Koo /** 12001a595f28SAnthony Koo * DP HPD instance 12011a595f28SAnthony Koo */ 1202b6402afeSAnthony Koo uint8_t instance; 12031a595f28SAnthony Koo /** 12041a595f28SAnthony Koo * HPD type 12051a595f28SAnthony Koo */ 1206d9beecfcSAnthony Koo uint8_t hpd_type; 12071a595f28SAnthony Koo /** 12081a595f28SAnthony Koo * HPD status: only for type: DP_HPD to indicate status 12091a595f28SAnthony Koo */ 1210d9beecfcSAnthony Koo uint8_t hpd_status; 12111a595f28SAnthony Koo /** 12121a595f28SAnthony Koo * Alignment only 12131a595f28SAnthony Koo */ 1214d9beecfcSAnthony Koo uint8_t pad; 1215d9beecfcSAnthony Koo }; 1216d9beecfcSAnthony Koo 12171a595f28SAnthony Koo /** 12181a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 12191a595f28SAnthony Koo */ 1220d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify { 12211a595f28SAnthony Koo /** 12221a595f28SAnthony Koo * Command header. 12231a595f28SAnthony Koo */ 1224d9beecfcSAnthony Koo struct dmub_cmd_header header; 12251a595f28SAnthony Koo /** 12261a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 12271a595f28SAnthony Koo */ 1228d9beecfcSAnthony Koo struct dp_hpd_data hpd_data; 1229d9beecfcSAnthony Koo }; 1230d9beecfcSAnthony Koo 123184034ad4SAnthony Koo /* 123284034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 123384034ad4SAnthony Koo * Do not reuse or modify IDs. 123484034ad4SAnthony Koo */ 123584034ad4SAnthony Koo 12361a595f28SAnthony Koo /** 12371a595f28SAnthony Koo * PSR command sub-types. 12381a595f28SAnthony Koo */ 123984034ad4SAnthony Koo enum dmub_cmd_psr_type { 12401a595f28SAnthony Koo /** 12411a595f28SAnthony Koo * Set PSR version support. 12421a595f28SAnthony Koo */ 124384034ad4SAnthony Koo DMUB_CMD__PSR_SET_VERSION = 0, 12441a595f28SAnthony Koo /** 12451a595f28SAnthony Koo * Copy driver-calculated parameters to PSR state. 12461a595f28SAnthony Koo */ 124784034ad4SAnthony Koo DMUB_CMD__PSR_COPY_SETTINGS = 1, 12481a595f28SAnthony Koo /** 12491a595f28SAnthony Koo * Enable PSR. 12501a595f28SAnthony Koo */ 125184034ad4SAnthony Koo DMUB_CMD__PSR_ENABLE = 2, 12521a595f28SAnthony Koo 12531a595f28SAnthony Koo /** 12541a595f28SAnthony Koo * Disable PSR. 12551a595f28SAnthony Koo */ 125684034ad4SAnthony Koo DMUB_CMD__PSR_DISABLE = 3, 12571a595f28SAnthony Koo 12581a595f28SAnthony Koo /** 12591a595f28SAnthony Koo * Set PSR level. 12601a595f28SAnthony Koo * PSR level is a 16-bit value dicated by driver that 12611a595f28SAnthony Koo * will enable/disable different functionality. 12621a595f28SAnthony Koo */ 126384034ad4SAnthony Koo DMUB_CMD__PSR_SET_LEVEL = 4, 12641a595f28SAnthony Koo 12651a595f28SAnthony Koo /** 12661a595f28SAnthony Koo * Forces PSR enabled until an explicit PSR disable call. 12671a595f28SAnthony Koo */ 1268672251b2SAnthony Koo DMUB_CMD__PSR_FORCE_STATIC = 5, 126984034ad4SAnthony Koo }; 127084034ad4SAnthony Koo 12711a595f28SAnthony Koo /** 12721a595f28SAnthony Koo * PSR versions. 12731a595f28SAnthony Koo */ 127484034ad4SAnthony Koo enum psr_version { 12751a595f28SAnthony Koo /** 12761a595f28SAnthony Koo * PSR version 1. 12771a595f28SAnthony Koo */ 127884034ad4SAnthony Koo PSR_VERSION_1 = 0, 12791a595f28SAnthony Koo /** 12801a595f28SAnthony Koo * PSR not supported. 12811a595f28SAnthony Koo */ 128284034ad4SAnthony Koo PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 128384034ad4SAnthony Koo }; 128484034ad4SAnthony Koo 1285592a6318SAnthony Koo /** 1286592a6318SAnthony Koo * enum dmub_cmd_mall_type - MALL commands 1287592a6318SAnthony Koo */ 128852f2e83eSBhawanpreet Lakha enum dmub_cmd_mall_type { 1289592a6318SAnthony Koo /** 1290592a6318SAnthony Koo * Allows display refresh from MALL. 1291592a6318SAnthony Koo */ 129252f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_ALLOW = 0, 1293592a6318SAnthony Koo /** 1294592a6318SAnthony Koo * Disallows display refresh from MALL. 1295592a6318SAnthony Koo */ 129652f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1297592a6318SAnthony Koo /** 1298592a6318SAnthony Koo * Cursor copy for MALL. 1299592a6318SAnthony Koo */ 130052f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1301592a6318SAnthony Koo /** 1302592a6318SAnthony Koo * Controls DF requests. 1303592a6318SAnthony Koo */ 1304ea7154d8SBhawanpreet Lakha DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 130552f2e83eSBhawanpreet Lakha }; 130652f2e83eSBhawanpreet Lakha 1307592a6318SAnthony Koo 13081a595f28SAnthony Koo /** 13091a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 13101a595f28SAnthony Koo */ 13117c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data { 13121a595f28SAnthony Koo /** 13131a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 13141a595f28SAnthony Koo */ 13157b8a6362SAnthony Koo union dmub_psr_debug_flags debug; 13161a595f28SAnthony Koo /** 13171a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 13181a595f28SAnthony Koo */ 13194c1a1335SWyatt Wood uint16_t psr_level; 13201a595f28SAnthony Koo /** 13211a595f28SAnthony Koo * DPP HW instance. 13221a595f28SAnthony Koo */ 13234c1a1335SWyatt Wood uint8_t dpp_inst; 13241a595f28SAnthony Koo /** 13251a595f28SAnthony Koo * MPCC HW instance. 13261a595f28SAnthony Koo * Not used in dmub fw, 132734ba432cSAnthony Koo * dmub fw will get active opp by reading odm registers. 132834ba432cSAnthony Koo */ 13294c1a1335SWyatt Wood uint8_t mpcc_inst; 13301a595f28SAnthony Koo /** 13311a595f28SAnthony Koo * OPP HW instance. 13321a595f28SAnthony Koo * Not used in dmub fw, 13331a595f28SAnthony Koo * dmub fw will get active opp by reading odm registers. 13341a595f28SAnthony Koo */ 13354c1a1335SWyatt Wood uint8_t opp_inst; 13361a595f28SAnthony Koo /** 13371a595f28SAnthony Koo * OTG HW instance. 13381a595f28SAnthony Koo */ 13394c1a1335SWyatt Wood uint8_t otg_inst; 13401a595f28SAnthony Koo /** 13411a595f28SAnthony Koo * DIG FE HW instance. 13421a595f28SAnthony Koo */ 13434c1a1335SWyatt Wood uint8_t digfe_inst; 13441a595f28SAnthony Koo /** 13451a595f28SAnthony Koo * DIG BE HW instance. 13461a595f28SAnthony Koo */ 13474c1a1335SWyatt Wood uint8_t digbe_inst; 13481a595f28SAnthony Koo /** 13491a595f28SAnthony Koo * DP PHY HW instance. 13501a595f28SAnthony Koo */ 13514c1a1335SWyatt Wood uint8_t dpphy_inst; 13521a595f28SAnthony Koo /** 13531a595f28SAnthony Koo * AUX HW instance. 13541a595f28SAnthony Koo */ 13554c1a1335SWyatt Wood uint8_t aux_inst; 13561a595f28SAnthony Koo /** 13571a595f28SAnthony Koo * Determines if SMU optimzations are enabled/disabled. 13581a595f28SAnthony Koo */ 13594c1a1335SWyatt Wood uint8_t smu_optimizations_en; 13601a595f28SAnthony Koo /** 13611a595f28SAnthony Koo * Unused. 13621a595f28SAnthony Koo * TODO: Remove. 13631a595f28SAnthony Koo */ 13644c1a1335SWyatt Wood uint8_t frame_delay; 13651a595f28SAnthony Koo /** 13661a595f28SAnthony Koo * If RFB setup time is greater than the total VBLANK time, 13671a595f28SAnthony Koo * it is not possible for the sink to capture the video frame 13681a595f28SAnthony Koo * in the same frame the SDP is sent. In this case, 13691a595f28SAnthony Koo * the frame capture indication bit should be set and an extra 13701a595f28SAnthony Koo * static frame should be transmitted to the sink. 13711a595f28SAnthony Koo */ 13724c1a1335SWyatt Wood uint8_t frame_cap_ind; 13731a595f28SAnthony Koo /** 13741a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 13751a595f28SAnthony Koo */ 1376175f0971SYongqiang Sun uint8_t pad[2]; 13771a595f28SAnthony Koo /** 13781a595f28SAnthony Koo * Multi-display optimizations are implemented on certain ASICs. 13791a595f28SAnthony Koo */ 1380175f0971SYongqiang Sun uint8_t multi_disp_optimizations_en; 13811a595f28SAnthony Koo /** 13821a595f28SAnthony Koo * The last possible line SDP may be transmitted without violating 13831a595f28SAnthony Koo * the RFB setup time or entering the active video frame. 13841a595f28SAnthony Koo */ 138578ead771SAnthony Koo uint16_t init_sdp_deadline; 13861a595f28SAnthony Koo /** 13871a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 13881a595f28SAnthony Koo */ 138978ead771SAnthony Koo uint16_t pad2; 13901a595f28SAnthony Koo /** 13911a595f28SAnthony Koo * Length of each horizontal line in us. 13921a595f28SAnthony Koo */ 13939b56f6bcSAnthony Koo uint32_t line_time_in_us; 1394ecc11601SAnthony Koo /** 1395ecc11601SAnthony Koo * FEC enable status in driver 1396ecc11601SAnthony Koo */ 1397ecc11601SAnthony Koo uint8_t fec_enable_status; 1398ecc11601SAnthony Koo /** 1399ecc11601SAnthony Koo * FEC re-enable delay when PSR exit. 1400ecc11601SAnthony Koo * unit is 100us, range form 0~255(0xFF). 1401ecc11601SAnthony Koo */ 1402ecc11601SAnthony Koo uint8_t fec_enable_delay_in100us; 1403ecc11601SAnthony Koo /** 1404f56c837aSMikita Lipski * PSR control version. 1405ecc11601SAnthony Koo */ 1406f56c837aSMikita Lipski uint8_t cmd_version; 1407f56c837aSMikita Lipski /** 1408f56c837aSMikita Lipski * Panel Instance. 1409f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1410f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1411f56c837aSMikita Lipski */ 1412f56c837aSMikita Lipski uint8_t panel_inst; 1413360d1b65SIan Chen /** 1414360d1b65SIan Chen * Explicit padding to 4 byte boundary. 1415360d1b65SIan Chen */ 1416360d1b65SIan Chen uint8_t pad3[4]; 14177c008829SNicholas Kazlauskas }; 14187c008829SNicholas Kazlauskas 14191a595f28SAnthony Koo /** 14201a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 14211a595f28SAnthony Koo */ 14227c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings { 14231a595f28SAnthony Koo /** 14241a595f28SAnthony Koo * Command header. 14251a595f28SAnthony Koo */ 14267c008829SNicholas Kazlauskas struct dmub_cmd_header header; 14271a595f28SAnthony Koo /** 14281a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 14291a595f28SAnthony Koo */ 14307c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 14317c008829SNicholas Kazlauskas }; 14327c008829SNicholas Kazlauskas 14331a595f28SAnthony Koo /** 14341a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 14351a595f28SAnthony Koo */ 14367c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data { 14371a595f28SAnthony Koo /** 14381a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 14391a595f28SAnthony Koo */ 14407c008829SNicholas Kazlauskas uint16_t psr_level; 14411a595f28SAnthony Koo /** 1442f56c837aSMikita Lipski * PSR control version. 14431a595f28SAnthony Koo */ 1444f56c837aSMikita Lipski uint8_t cmd_version; 1445f56c837aSMikita Lipski /** 1446f56c837aSMikita Lipski * Panel Instance. 1447f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1448f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1449f56c837aSMikita Lipski */ 1450f56c837aSMikita Lipski uint8_t panel_inst; 1451*d459b79bSAnthony Koo /** 1452*d459b79bSAnthony Koo * Explicit padding to 4 byte boundary. 1453*d459b79bSAnthony Koo */ 1454*d459b79bSAnthony Koo uint8_t pad3[4]; 14557c008829SNicholas Kazlauskas }; 14567c008829SNicholas Kazlauskas 14571a595f28SAnthony Koo /** 14581a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 14591a595f28SAnthony Koo */ 14607c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level { 14611a595f28SAnthony Koo /** 14621a595f28SAnthony Koo * Command header. 14631a595f28SAnthony Koo */ 14647c008829SNicholas Kazlauskas struct dmub_cmd_header header; 14651a595f28SAnthony Koo /** 14661a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 14671a595f28SAnthony Koo */ 14687c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data psr_set_level_data; 14697c008829SNicholas Kazlauskas }; 14707c008829SNicholas Kazlauskas 1471f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data { 1472f56c837aSMikita Lipski /** 1473f56c837aSMikita Lipski * PSR control version. 1474f56c837aSMikita Lipski */ 1475f56c837aSMikita Lipski uint8_t cmd_version; 1476f56c837aSMikita Lipski /** 1477f56c837aSMikita Lipski * Panel Instance. 1478f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1479f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1480f56c837aSMikita Lipski */ 1481f56c837aSMikita Lipski uint8_t panel_inst; 1482f56c837aSMikita Lipski /** 1483f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 1484f56c837aSMikita Lipski */ 1485f56c837aSMikita Lipski uint8_t pad[2]; 1486f56c837aSMikita Lipski }; 1487f56c837aSMikita Lipski 14881a595f28SAnthony Koo /** 14891a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 14901a595f28SAnthony Koo * PSR enable/disable is controlled using the sub_type. 14911a595f28SAnthony Koo */ 14927c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_enable { 14931a595f28SAnthony Koo /** 14941a595f28SAnthony Koo * Command header. 14951a595f28SAnthony Koo */ 14967c008829SNicholas Kazlauskas struct dmub_cmd_header header; 1497f56c837aSMikita Lipski 1498f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data data; 14997c008829SNicholas Kazlauskas }; 15007c008829SNicholas Kazlauskas 15011a595f28SAnthony Koo /** 15021a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 15031a595f28SAnthony Koo */ 1504d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data { 15051a595f28SAnthony Koo /** 15061a595f28SAnthony Koo * PSR version that FW should implement. 15071a595f28SAnthony Koo */ 15081a595f28SAnthony Koo enum psr_version version; 1509f56c837aSMikita Lipski /** 1510f56c837aSMikita Lipski * PSR control version. 1511f56c837aSMikita Lipski */ 1512f56c837aSMikita Lipski uint8_t cmd_version; 1513f56c837aSMikita Lipski /** 1514f56c837aSMikita Lipski * Panel Instance. 1515f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1516f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1517f56c837aSMikita Lipski */ 1518f56c837aSMikita Lipski uint8_t panel_inst; 1519f56c837aSMikita Lipski /** 1520f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 1521f56c837aSMikita Lipski */ 1522f56c837aSMikita Lipski uint8_t pad[2]; 15237c008829SNicholas Kazlauskas }; 15247c008829SNicholas Kazlauskas 15251a595f28SAnthony Koo /** 15261a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 15271a595f28SAnthony Koo */ 1528d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version { 15291a595f28SAnthony Koo /** 15301a595f28SAnthony Koo * Command header. 15311a595f28SAnthony Koo */ 15327c008829SNicholas Kazlauskas struct dmub_cmd_header header; 15331a595f28SAnthony Koo /** 15341a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 15351a595f28SAnthony Koo */ 1536d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data psr_set_version_data; 15377c008829SNicholas Kazlauskas }; 15387c008829SNicholas Kazlauskas 1539f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data { 1540f56c837aSMikita Lipski /** 1541f56c837aSMikita Lipski * PSR control version. 1542f56c837aSMikita Lipski */ 1543f56c837aSMikita Lipski uint8_t cmd_version; 1544f56c837aSMikita Lipski /** 1545f56c837aSMikita Lipski * Panel Instance. 1546f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1547f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1548f56c837aSMikita Lipski */ 1549f56c837aSMikita Lipski uint8_t panel_inst; 1550f56c837aSMikita Lipski /** 1551f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 1552f56c837aSMikita Lipski */ 1553f56c837aSMikita Lipski uint8_t pad[2]; 1554f56c837aSMikita Lipski }; 1555f56c837aSMikita Lipski 15561a595f28SAnthony Koo /** 15571a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 15581a595f28SAnthony Koo */ 1559672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static { 15601a595f28SAnthony Koo /** 15611a595f28SAnthony Koo * Command header. 15621a595f28SAnthony Koo */ 1563672251b2SAnthony Koo struct dmub_cmd_header header; 1564f56c837aSMikita Lipski /** 1565f56c837aSMikita Lipski * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1566f56c837aSMikita Lipski */ 1567f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data psr_force_static_data; 1568672251b2SAnthony Koo }; 1569672251b2SAnthony Koo 15701a595f28SAnthony Koo /** 15711a595f28SAnthony Koo * Set of HW components that can be locked. 15720b51e7e8SAnthony Koo * 15730b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 15740b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 15751a595f28SAnthony Koo */ 1576788408b7SAnthony Koo union dmub_hw_lock_flags { 15771a595f28SAnthony Koo /** 15781a595f28SAnthony Koo * Set of HW components that can be locked. 15791a595f28SAnthony Koo */ 1580788408b7SAnthony Koo struct { 15811a595f28SAnthony Koo /** 15821a595f28SAnthony Koo * Lock/unlock OTG master update lock. 15831a595f28SAnthony Koo */ 1584788408b7SAnthony Koo uint8_t lock_pipe : 1; 15851a595f28SAnthony Koo /** 15861a595f28SAnthony Koo * Lock/unlock cursor. 15871a595f28SAnthony Koo */ 1588788408b7SAnthony Koo uint8_t lock_cursor : 1; 15891a595f28SAnthony Koo /** 15901a595f28SAnthony Koo * Lock/unlock global update lock. 15911a595f28SAnthony Koo */ 1592788408b7SAnthony Koo uint8_t lock_dig : 1; 15931a595f28SAnthony Koo /** 15941a595f28SAnthony Koo * Triple buffer lock requires additional hw programming to usual OTG master lock. 15951a595f28SAnthony Koo */ 1596788408b7SAnthony Koo uint8_t triple_buffer_lock : 1; 1597788408b7SAnthony Koo } bits; 1598788408b7SAnthony Koo 15991a595f28SAnthony Koo /** 16001a595f28SAnthony Koo * Union for HW Lock flags. 16011a595f28SAnthony Koo */ 1602788408b7SAnthony Koo uint8_t u8All; 1603788408b7SAnthony Koo }; 1604788408b7SAnthony Koo 16051a595f28SAnthony Koo /** 16061a595f28SAnthony Koo * Instances of HW to be locked. 16070b51e7e8SAnthony Koo * 16080b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 16090b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 16101a595f28SAnthony Koo */ 1611788408b7SAnthony Koo struct dmub_hw_lock_inst_flags { 16121a595f28SAnthony Koo /** 16131a595f28SAnthony Koo * OTG HW instance for OTG master update lock. 16141a595f28SAnthony Koo */ 1615788408b7SAnthony Koo uint8_t otg_inst; 16161a595f28SAnthony Koo /** 16171a595f28SAnthony Koo * OPP instance for cursor lock. 16181a595f28SAnthony Koo */ 1619788408b7SAnthony Koo uint8_t opp_inst; 16201a595f28SAnthony Koo /** 16211a595f28SAnthony Koo * OTG HW instance for global update lock. 16221a595f28SAnthony Koo * TODO: Remove, and re-use otg_inst. 16231a595f28SAnthony Koo */ 1624788408b7SAnthony Koo uint8_t dig_inst; 16251a595f28SAnthony Koo /** 16261a595f28SAnthony Koo * Explicit pad to 4 byte boundary. 16271a595f28SAnthony Koo */ 1628788408b7SAnthony Koo uint8_t pad; 1629788408b7SAnthony Koo }; 1630788408b7SAnthony Koo 16311a595f28SAnthony Koo /** 16321a595f28SAnthony Koo * Clients that can acquire the HW Lock Manager. 16330b51e7e8SAnthony Koo * 16340b51e7e8SAnthony Koo * Note: If updating with more clients, fields in 16350b51e7e8SAnthony Koo * dmub_inbox0_cmd_lock_hw must be updated to match. 16361a595f28SAnthony Koo */ 1637788408b7SAnthony Koo enum hw_lock_client { 16381a595f28SAnthony Koo /** 16391a595f28SAnthony Koo * Driver is the client of HW Lock Manager. 16401a595f28SAnthony Koo */ 1641788408b7SAnthony Koo HW_LOCK_CLIENT_DRIVER = 0, 16421a595f28SAnthony Koo /** 16431a595f28SAnthony Koo * Invalid client. 16441a595f28SAnthony Koo */ 1645788408b7SAnthony Koo HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1646788408b7SAnthony Koo }; 1647788408b7SAnthony Koo 16481a595f28SAnthony Koo /** 16491a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 16501a595f28SAnthony Koo */ 1651788408b7SAnthony Koo struct dmub_cmd_lock_hw_data { 16521a595f28SAnthony Koo /** 16531a595f28SAnthony Koo * Specifies the client accessing HW Lock Manager. 16541a595f28SAnthony Koo */ 1655788408b7SAnthony Koo enum hw_lock_client client; 16561a595f28SAnthony Koo /** 16571a595f28SAnthony Koo * HW instances to be locked. 16581a595f28SAnthony Koo */ 1659788408b7SAnthony Koo struct dmub_hw_lock_inst_flags inst_flags; 16601a595f28SAnthony Koo /** 16611a595f28SAnthony Koo * Which components to be locked. 16621a595f28SAnthony Koo */ 1663788408b7SAnthony Koo union dmub_hw_lock_flags hw_locks; 16641a595f28SAnthony Koo /** 16651a595f28SAnthony Koo * Specifies lock/unlock. 16661a595f28SAnthony Koo */ 1667788408b7SAnthony Koo uint8_t lock; 16681a595f28SAnthony Koo /** 16691a595f28SAnthony Koo * HW can be unlocked separately from releasing the HW Lock Mgr. 16701a595f28SAnthony Koo * This flag is set if the client wishes to release the object. 16711a595f28SAnthony Koo */ 1672788408b7SAnthony Koo uint8_t should_release; 16731a595f28SAnthony Koo /** 16741a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 16751a595f28SAnthony Koo */ 1676788408b7SAnthony Koo uint8_t pad; 1677788408b7SAnthony Koo }; 1678788408b7SAnthony Koo 16791a595f28SAnthony Koo /** 16801a595f28SAnthony Koo * Definition of a DMUB_CMD__HW_LOCK command. 16811a595f28SAnthony Koo * Command is used by driver and FW. 16821a595f28SAnthony Koo */ 1683788408b7SAnthony Koo struct dmub_rb_cmd_lock_hw { 16841a595f28SAnthony Koo /** 16851a595f28SAnthony Koo * Command header. 16861a595f28SAnthony Koo */ 1687788408b7SAnthony Koo struct dmub_cmd_header header; 16881a595f28SAnthony Koo /** 16891a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 16901a595f28SAnthony Koo */ 1691788408b7SAnthony Koo struct dmub_cmd_lock_hw_data lock_hw_data; 1692788408b7SAnthony Koo }; 1693788408b7SAnthony Koo 16941a595f28SAnthony Koo /** 16951a595f28SAnthony Koo * ABM command sub-types. 16961a595f28SAnthony Koo */ 169784034ad4SAnthony Koo enum dmub_cmd_abm_type { 16981a595f28SAnthony Koo /** 16991a595f28SAnthony Koo * Initialize parameters for ABM algorithm. 17001a595f28SAnthony Koo * Data is passed through an indirect buffer. 17011a595f28SAnthony Koo */ 170284034ad4SAnthony Koo DMUB_CMD__ABM_INIT_CONFIG = 0, 17031a595f28SAnthony Koo /** 17041a595f28SAnthony Koo * Set OTG and panel HW instance. 17051a595f28SAnthony Koo */ 170684034ad4SAnthony Koo DMUB_CMD__ABM_SET_PIPE = 1, 17071a595f28SAnthony Koo /** 17081a595f28SAnthony Koo * Set user requested backklight level. 17091a595f28SAnthony Koo */ 171084034ad4SAnthony Koo DMUB_CMD__ABM_SET_BACKLIGHT = 2, 17111a595f28SAnthony Koo /** 17121a595f28SAnthony Koo * Set ABM operating/aggression level. 17131a595f28SAnthony Koo */ 171484034ad4SAnthony Koo DMUB_CMD__ABM_SET_LEVEL = 3, 17151a595f28SAnthony Koo /** 17161a595f28SAnthony Koo * Set ambient light level. 17171a595f28SAnthony Koo */ 171884034ad4SAnthony Koo DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 17191a595f28SAnthony Koo /** 17201a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 17211a595f28SAnthony Koo */ 172284034ad4SAnthony Koo DMUB_CMD__ABM_SET_PWM_FRAC = 5, 172384034ad4SAnthony Koo }; 172484034ad4SAnthony Koo 17251a595f28SAnthony Koo /** 17261a595f28SAnthony Koo * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 17271a595f28SAnthony Koo * Requirements: 17281a595f28SAnthony Koo * - Padded explicitly to 32-bit boundary. 17291a595f28SAnthony Koo * - Must ensure this structure matches the one on driver-side, 17301a595f28SAnthony Koo * otherwise it won't be aligned. 173184034ad4SAnthony Koo */ 173284034ad4SAnthony Koo struct abm_config_table { 17331a595f28SAnthony Koo /** 17341a595f28SAnthony Koo * Gamma curve thresholds, used for crgb conversion. 17351a595f28SAnthony Koo */ 173684034ad4SAnthony Koo uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 17371a595f28SAnthony Koo /** 17381a595f28SAnthony Koo * Gamma curve offsets, used for crgb conversion. 17391a595f28SAnthony Koo */ 1740b6402afeSAnthony Koo uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 17411a595f28SAnthony Koo /** 17421a595f28SAnthony Koo * Gamma curve slopes, used for crgb conversion. 17431a595f28SAnthony Koo */ 1744b6402afeSAnthony Koo uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 17451a595f28SAnthony Koo /** 17461a595f28SAnthony Koo * Custom backlight curve thresholds. 17471a595f28SAnthony Koo */ 1748b6402afeSAnthony Koo uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 17491a595f28SAnthony Koo /** 17501a595f28SAnthony Koo * Custom backlight curve offsets. 17511a595f28SAnthony Koo */ 1752b6402afeSAnthony Koo uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 17531a595f28SAnthony Koo /** 17541a595f28SAnthony Koo * Ambient light thresholds. 17551a595f28SAnthony Koo */ 1756b6402afeSAnthony Koo uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 17571a595f28SAnthony Koo /** 17581a595f28SAnthony Koo * Minimum programmable backlight. 17591a595f28SAnthony Koo */ 1760b6402afeSAnthony Koo uint16_t min_abm_backlight; // 122B 17611a595f28SAnthony Koo /** 17621a595f28SAnthony Koo * Minimum reduction values. 17631a595f28SAnthony Koo */ 1764b6402afeSAnthony Koo uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 17651a595f28SAnthony Koo /** 17661a595f28SAnthony Koo * Maximum reduction values. 17671a595f28SAnthony Koo */ 1768b6402afeSAnthony Koo uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 17691a595f28SAnthony Koo /** 17701a595f28SAnthony Koo * Bright positive gain. 17711a595f28SAnthony Koo */ 1772b6402afeSAnthony Koo uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 17731a595f28SAnthony Koo /** 17741a595f28SAnthony Koo * Dark negative gain. 17751a595f28SAnthony Koo */ 1776b6402afeSAnthony Koo uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 17771a595f28SAnthony Koo /** 17781a595f28SAnthony Koo * Hybrid factor. 17791a595f28SAnthony Koo */ 1780b6402afeSAnthony Koo uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 17811a595f28SAnthony Koo /** 17821a595f28SAnthony Koo * Contrast factor. 17831a595f28SAnthony Koo */ 1784b6402afeSAnthony Koo uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 17851a595f28SAnthony Koo /** 17861a595f28SAnthony Koo * Deviation gain. 17871a595f28SAnthony Koo */ 1788b6402afeSAnthony Koo uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 17891a595f28SAnthony Koo /** 17901a595f28SAnthony Koo * Minimum knee. 17911a595f28SAnthony Koo */ 1792b6402afeSAnthony Koo uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 17931a595f28SAnthony Koo /** 17941a595f28SAnthony Koo * Maximum knee. 17951a595f28SAnthony Koo */ 1796b6402afeSAnthony Koo uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 17971a595f28SAnthony Koo /** 17981a595f28SAnthony Koo * Unused. 17991a595f28SAnthony Koo */ 1800b6402afeSAnthony Koo uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 18011a595f28SAnthony Koo /** 18021a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 18031a595f28SAnthony Koo */ 1804b6402afeSAnthony Koo uint8_t pad3[3]; // 229B 18051a595f28SAnthony Koo /** 18061a595f28SAnthony Koo * Backlight ramp reduction. 18071a595f28SAnthony Koo */ 1808b6402afeSAnthony Koo uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 18091a595f28SAnthony Koo /** 18101a595f28SAnthony Koo * Backlight ramp start. 18111a595f28SAnthony Koo */ 1812b6402afeSAnthony Koo uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 181384034ad4SAnthony Koo }; 181484034ad4SAnthony Koo 18151a595f28SAnthony Koo /** 18161a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 18171a595f28SAnthony Koo */ 1818e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data { 18191a595f28SAnthony Koo /** 18201a595f28SAnthony Koo * OTG HW instance. 18211a595f28SAnthony Koo */ 18227b8a6362SAnthony Koo uint8_t otg_inst; 18231a595f28SAnthony Koo 18241a595f28SAnthony Koo /** 18251a595f28SAnthony Koo * Panel Control HW instance. 18261a595f28SAnthony Koo */ 18277b8a6362SAnthony Koo uint8_t panel_inst; 18281a595f28SAnthony Koo 18291a595f28SAnthony Koo /** 18301a595f28SAnthony Koo * Controls how ABM will interpret a set pipe or set level command. 18311a595f28SAnthony Koo */ 18327b8a6362SAnthony Koo uint8_t set_pipe_option; 18331a595f28SAnthony Koo 18341a595f28SAnthony Koo /** 18351a595f28SAnthony Koo * Unused. 18361a595f28SAnthony Koo * TODO: Remove. 18371a595f28SAnthony Koo */ 18381a595f28SAnthony Koo uint8_t ramping_boundary; 1839e6ea8c34SWyatt Wood }; 1840e6ea8c34SWyatt Wood 18411a595f28SAnthony Koo /** 18421a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 18431a595f28SAnthony Koo */ 1844e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe { 18451a595f28SAnthony Koo /** 18461a595f28SAnthony Koo * Command header. 18471a595f28SAnthony Koo */ 1848e6ea8c34SWyatt Wood struct dmub_cmd_header header; 18491a595f28SAnthony Koo 18501a595f28SAnthony Koo /** 18511a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 18521a595f28SAnthony Koo */ 1853e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 1854e6ea8c34SWyatt Wood }; 1855e6ea8c34SWyatt Wood 18561a595f28SAnthony Koo /** 18571a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 18581a595f28SAnthony Koo */ 1859e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data { 18601a595f28SAnthony Koo /** 18611a595f28SAnthony Koo * Number of frames to ramp to backlight user level. 18621a595f28SAnthony Koo */ 1863e6ea8c34SWyatt Wood uint32_t frame_ramp; 18641a595f28SAnthony Koo 18651a595f28SAnthony Koo /** 18661a595f28SAnthony Koo * Requested backlight level from user. 18671a595f28SAnthony Koo */ 1868474ac4a8SYongqiang Sun uint32_t backlight_user_level; 1869e922057bSJake Wang 1870e922057bSJake Wang /** 187163de4f04SJake Wang * ABM control version. 1872e922057bSJake Wang */ 1873e922057bSJake Wang uint8_t version; 1874e922057bSJake Wang 1875e922057bSJake Wang /** 1876e922057bSJake Wang * Panel Control HW instance mask. 1877e922057bSJake Wang * Bit 0 is Panel Control HW instance 0. 1878e922057bSJake Wang * Bit 1 is Panel Control HW instance 1. 1879e922057bSJake Wang */ 1880e922057bSJake Wang uint8_t panel_mask; 1881e922057bSJake Wang 1882e922057bSJake Wang /** 1883e922057bSJake Wang * Explicit padding to 4 byte boundary. 1884e922057bSJake Wang */ 1885e922057bSJake Wang uint8_t pad[2]; 1886e6ea8c34SWyatt Wood }; 1887e6ea8c34SWyatt Wood 18881a595f28SAnthony Koo /** 18891a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 18901a595f28SAnthony Koo */ 1891e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight { 18921a595f28SAnthony Koo /** 18931a595f28SAnthony Koo * Command header. 18941a595f28SAnthony Koo */ 1895e6ea8c34SWyatt Wood struct dmub_cmd_header header; 18961a595f28SAnthony Koo 18971a595f28SAnthony Koo /** 18981a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 18991a595f28SAnthony Koo */ 1900e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 1901e6ea8c34SWyatt Wood }; 1902e6ea8c34SWyatt Wood 19031a595f28SAnthony Koo /** 19041a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 19051a595f28SAnthony Koo */ 1906e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data { 19071a595f28SAnthony Koo /** 19081a595f28SAnthony Koo * Set current ABM operating/aggression level. 19091a595f28SAnthony Koo */ 1910e6ea8c34SWyatt Wood uint32_t level; 191163de4f04SJake Wang 191263de4f04SJake Wang /** 191363de4f04SJake Wang * ABM control version. 191463de4f04SJake Wang */ 191563de4f04SJake Wang uint8_t version; 191663de4f04SJake Wang 191763de4f04SJake Wang /** 191863de4f04SJake Wang * Panel Control HW instance mask. 191963de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 192063de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 192163de4f04SJake Wang */ 192263de4f04SJake Wang uint8_t panel_mask; 192363de4f04SJake Wang 192463de4f04SJake Wang /** 192563de4f04SJake Wang * Explicit padding to 4 byte boundary. 192663de4f04SJake Wang */ 192763de4f04SJake Wang uint8_t pad[2]; 1928e6ea8c34SWyatt Wood }; 1929e6ea8c34SWyatt Wood 19301a595f28SAnthony Koo /** 19311a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 19321a595f28SAnthony Koo */ 1933e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level { 19341a595f28SAnthony Koo /** 19351a595f28SAnthony Koo * Command header. 19361a595f28SAnthony Koo */ 1937e6ea8c34SWyatt Wood struct dmub_cmd_header header; 19381a595f28SAnthony Koo 19391a595f28SAnthony Koo /** 19401a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 19411a595f28SAnthony Koo */ 1942e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data abm_set_level_data; 1943e6ea8c34SWyatt Wood }; 1944e6ea8c34SWyatt Wood 19451a595f28SAnthony Koo /** 19461a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 19471a595f28SAnthony Koo */ 1948e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data { 19491a595f28SAnthony Koo /** 19501a595f28SAnthony Koo * Ambient light sensor reading from OS. 19511a595f28SAnthony Koo */ 1952e6ea8c34SWyatt Wood uint32_t ambient_lux; 195363de4f04SJake Wang 195463de4f04SJake Wang /** 195563de4f04SJake Wang * ABM control version. 195663de4f04SJake Wang */ 195763de4f04SJake Wang uint8_t version; 195863de4f04SJake Wang 195963de4f04SJake Wang /** 196063de4f04SJake Wang * Panel Control HW instance mask. 196163de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 196263de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 196363de4f04SJake Wang */ 196463de4f04SJake Wang uint8_t panel_mask; 196563de4f04SJake Wang 196663de4f04SJake Wang /** 196763de4f04SJake Wang * Explicit padding to 4 byte boundary. 196863de4f04SJake Wang */ 196963de4f04SJake Wang uint8_t pad[2]; 1970e6ea8c34SWyatt Wood }; 1971e6ea8c34SWyatt Wood 19721a595f28SAnthony Koo /** 19731a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 19741a595f28SAnthony Koo */ 1975e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level { 19761a595f28SAnthony Koo /** 19771a595f28SAnthony Koo * Command header. 19781a595f28SAnthony Koo */ 1979e6ea8c34SWyatt Wood struct dmub_cmd_header header; 19801a595f28SAnthony Koo 19811a595f28SAnthony Koo /** 19821a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 19831a595f28SAnthony Koo */ 1984e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 1985e6ea8c34SWyatt Wood }; 1986e6ea8c34SWyatt Wood 19871a595f28SAnthony Koo /** 19881a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 19891a595f28SAnthony Koo */ 1990e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data { 19911a595f28SAnthony Koo /** 19921a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 19931a595f28SAnthony Koo * TODO: Convert to uint8_t. 19941a595f28SAnthony Koo */ 1995e6ea8c34SWyatt Wood uint32_t fractional_pwm; 199663de4f04SJake Wang 199763de4f04SJake Wang /** 199863de4f04SJake Wang * ABM control version. 199963de4f04SJake Wang */ 200063de4f04SJake Wang uint8_t version; 200163de4f04SJake Wang 200263de4f04SJake Wang /** 200363de4f04SJake Wang * Panel Control HW instance mask. 200463de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 200563de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 200663de4f04SJake Wang */ 200763de4f04SJake Wang uint8_t panel_mask; 200863de4f04SJake Wang 200963de4f04SJake Wang /** 201063de4f04SJake Wang * Explicit padding to 4 byte boundary. 201163de4f04SJake Wang */ 201263de4f04SJake Wang uint8_t pad[2]; 2013e6ea8c34SWyatt Wood }; 2014e6ea8c34SWyatt Wood 20151a595f28SAnthony Koo /** 20161a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 20171a595f28SAnthony Koo */ 2018e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac { 20191a595f28SAnthony Koo /** 20201a595f28SAnthony Koo * Command header. 20211a595f28SAnthony Koo */ 2022e6ea8c34SWyatt Wood struct dmub_cmd_header header; 20231a595f28SAnthony Koo 20241a595f28SAnthony Koo /** 20251a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 20261a595f28SAnthony Koo */ 2027e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2028e6ea8c34SWyatt Wood }; 2029e6ea8c34SWyatt Wood 20301a595f28SAnthony Koo /** 20311a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 20321a595f28SAnthony Koo */ 203316012806SWyatt Wood struct dmub_cmd_abm_init_config_data { 20341a595f28SAnthony Koo /** 20351a595f28SAnthony Koo * Location of indirect buffer used to pass init data to ABM. 20361a595f28SAnthony Koo */ 203716012806SWyatt Wood union dmub_addr src; 20381a595f28SAnthony Koo 20391a595f28SAnthony Koo /** 20401a595f28SAnthony Koo * Indirect buffer length. 20411a595f28SAnthony Koo */ 204216012806SWyatt Wood uint16_t bytes; 204363de4f04SJake Wang 204463de4f04SJake Wang 204563de4f04SJake Wang /** 204663de4f04SJake Wang * ABM control version. 204763de4f04SJake Wang */ 204863de4f04SJake Wang uint8_t version; 204963de4f04SJake Wang 205063de4f04SJake Wang /** 205163de4f04SJake Wang * Panel Control HW instance mask. 205263de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 205363de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 205463de4f04SJake Wang */ 205563de4f04SJake Wang uint8_t panel_mask; 205663de4f04SJake Wang 205763de4f04SJake Wang /** 205863de4f04SJake Wang * Explicit padding to 4 byte boundary. 205963de4f04SJake Wang */ 206063de4f04SJake Wang uint8_t pad[2]; 206116012806SWyatt Wood }; 206216012806SWyatt Wood 20631a595f28SAnthony Koo /** 20641a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 20651a595f28SAnthony Koo */ 206616012806SWyatt Wood struct dmub_rb_cmd_abm_init_config { 20671a595f28SAnthony Koo /** 20681a595f28SAnthony Koo * Command header. 20691a595f28SAnthony Koo */ 207016012806SWyatt Wood struct dmub_cmd_header header; 20711a595f28SAnthony Koo 20721a595f28SAnthony Koo /** 20731a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 20741a595f28SAnthony Koo */ 207516012806SWyatt Wood struct dmub_cmd_abm_init_config_data abm_init_config_data; 207616012806SWyatt Wood }; 207716012806SWyatt Wood 20781a595f28SAnthony Koo /** 20791a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 20801a595f28SAnthony Koo */ 208134ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data { 20821a595f28SAnthony Koo /** 20831a595f28SAnthony Koo * DMUB feature capabilities. 20841a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features. 20851a595f28SAnthony Koo */ 208634ba432cSAnthony Koo struct dmub_feature_caps feature_caps; 208734ba432cSAnthony Koo }; 208834ba432cSAnthony Koo 20891a595f28SAnthony Koo /** 20901a595f28SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 20911a595f28SAnthony Koo */ 209234ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps { 20931a595f28SAnthony Koo /** 20941a595f28SAnthony Koo * Command header. 20951a595f28SAnthony Koo */ 209634ba432cSAnthony Koo struct dmub_cmd_header header; 20971a595f28SAnthony Koo /** 20981a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 20991a595f28SAnthony Koo */ 210034ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 210134ba432cSAnthony Koo }; 210234ba432cSAnthony Koo 2103592a6318SAnthony Koo struct dmub_optc_state { 2104592a6318SAnthony Koo uint32_t v_total_max; 2105592a6318SAnthony Koo uint32_t v_total_min; 2106592a6318SAnthony Koo uint32_t v_total_mid; 2107592a6318SAnthony Koo uint32_t v_total_mid_frame_num; 2108592a6318SAnthony Koo uint32_t tg_inst; 2109592a6318SAnthony Koo uint32_t enable_manual_trigger; 2110592a6318SAnthony Koo uint32_t clear_force_vsync; 2111592a6318SAnthony Koo }; 2112592a6318SAnthony Koo 2113592a6318SAnthony Koo struct dmub_rb_cmd_drr_update { 2114592a6318SAnthony Koo struct dmub_cmd_header header; 2115592a6318SAnthony Koo struct dmub_optc_state dmub_optc_state_req; 2116592a6318SAnthony Koo }; 2117592a6318SAnthony Koo 2118b04cb192SNicholas Kazlauskas /** 2119b04cb192SNicholas Kazlauskas * enum dmub_cmd_panel_cntl_type - Panel control command. 2120b04cb192SNicholas Kazlauskas */ 2121b04cb192SNicholas Kazlauskas enum dmub_cmd_panel_cntl_type { 2122b04cb192SNicholas Kazlauskas /** 2123b04cb192SNicholas Kazlauskas * Initializes embedded panel hardware blocks. 2124b04cb192SNicholas Kazlauskas */ 2125b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2126b04cb192SNicholas Kazlauskas /** 2127b04cb192SNicholas Kazlauskas * Queries backlight info for the embedded panel. 2128b04cb192SNicholas Kazlauskas */ 2129b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2130b04cb192SNicholas Kazlauskas }; 2131b04cb192SNicholas Kazlauskas 2132b04cb192SNicholas Kazlauskas /** 2133b04cb192SNicholas Kazlauskas * struct dmub_cmd_panel_cntl_data - Panel control data. 2134b04cb192SNicholas Kazlauskas */ 2135b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data { 2136b04cb192SNicholas Kazlauskas uint32_t inst; /**< panel instance */ 2137b04cb192SNicholas Kazlauskas uint32_t current_backlight; /* in/out */ 2138b04cb192SNicholas Kazlauskas uint32_t bl_pwm_cntl; /* in/out */ 2139b04cb192SNicholas Kazlauskas uint32_t bl_pwm_period_cntl; /* in/out */ 2140b04cb192SNicholas Kazlauskas uint32_t bl_pwm_ref_div1; /* in/out */ 2141b04cb192SNicholas Kazlauskas uint8_t is_backlight_on : 1; /* in/out */ 2142b04cb192SNicholas Kazlauskas uint8_t is_powered_on : 1; /* in/out */ 2143b04cb192SNicholas Kazlauskas }; 2144b04cb192SNicholas Kazlauskas 2145b04cb192SNicholas Kazlauskas /** 2146b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_panel_cntl - Panel control command. 2147b04cb192SNicholas Kazlauskas */ 2148b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl { 2149b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 2150b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data data; /**< payload */ 2151b04cb192SNicholas Kazlauskas }; 2152b04cb192SNicholas Kazlauskas 21531a595f28SAnthony Koo /** 21541a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 21551a595f28SAnthony Koo */ 21561a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data { 21571a595f28SAnthony Koo uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 21581a595f28SAnthony Koo uint8_t reserved_0[3]; /**< For future use */ 21591a595f28SAnthony Koo uint8_t panel_inst; /**< LVTMA control instance */ 21601a595f28SAnthony Koo uint8_t reserved_1[3]; /**< For future use */ 21611a595f28SAnthony Koo }; 21621a595f28SAnthony Koo 21631a595f28SAnthony Koo /** 21641a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 21651a595f28SAnthony Koo */ 21661a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control { 21671a595f28SAnthony Koo /** 21681a595f28SAnthony Koo * Command header. 21691a595f28SAnthony Koo */ 21701a595f28SAnthony Koo struct dmub_cmd_header header; 21711a595f28SAnthony Koo /** 21721a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 21731a595f28SAnthony Koo */ 21741a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data data; 21751a595f28SAnthony Koo }; 21761a595f28SAnthony Koo 2177592a6318SAnthony Koo /** 2178021eaef8SAnthony Koo * Maximum number of bytes a chunk sent to DMUB for parsing 2179021eaef8SAnthony Koo */ 2180021eaef8SAnthony Koo #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2181021eaef8SAnthony Koo 2182021eaef8SAnthony Koo /** 2183021eaef8SAnthony Koo * Represent a chunk of CEA blocks sent to DMUB for parsing 2184021eaef8SAnthony Koo */ 2185021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea { 2186021eaef8SAnthony Koo uint16_t offset; /**< offset into the CEA block */ 2187021eaef8SAnthony Koo uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2188021eaef8SAnthony Koo uint16_t total_length; /**< total length of the CEA block */ 2189021eaef8SAnthony Koo uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2190021eaef8SAnthony Koo uint8_t pad[3]; /**< padding and for future expansion */ 2191021eaef8SAnthony Koo }; 2192021eaef8SAnthony Koo 2193021eaef8SAnthony Koo /** 2194021eaef8SAnthony Koo * Result of VSDB parsing from CEA block 2195021eaef8SAnthony Koo */ 2196021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb { 2197021eaef8SAnthony Koo uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2198021eaef8SAnthony Koo uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2199021eaef8SAnthony Koo uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2200021eaef8SAnthony Koo uint16_t min_frame_rate; /**< Maximum frame rate */ 2201021eaef8SAnthony Koo uint16_t max_frame_rate; /**< Minimum frame rate */ 2202021eaef8SAnthony Koo }; 2203021eaef8SAnthony Koo 2204021eaef8SAnthony Koo /** 2205021eaef8SAnthony Koo * Result of sending a CEA chunk 2206021eaef8SAnthony Koo */ 2207021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack { 2208021eaef8SAnthony Koo uint16_t offset; /**< offset of the chunk into the CEA block */ 2209021eaef8SAnthony Koo uint8_t success; /**< 1 if this sending of chunk succeeded */ 2210021eaef8SAnthony Koo uint8_t pad; /**< padding and for future expansion */ 2211021eaef8SAnthony Koo }; 2212021eaef8SAnthony Koo 2213021eaef8SAnthony Koo /** 2214021eaef8SAnthony Koo * Specify whether the result is an ACK/NACK or the parsing has finished 2215021eaef8SAnthony Koo */ 2216021eaef8SAnthony Koo enum dmub_cmd_edid_cea_reply_type { 2217021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2218021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2219021eaef8SAnthony Koo }; 2220021eaef8SAnthony Koo 2221021eaef8SAnthony Koo /** 2222021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 2223021eaef8SAnthony Koo */ 2224021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea { 2225021eaef8SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 2226021eaef8SAnthony Koo union dmub_cmd_edid_cea_data { 2227021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2228021eaef8SAnthony Koo struct dmub_cmd_edid_cea_output { /**< output with results */ 2229021eaef8SAnthony Koo uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2230021eaef8SAnthony Koo union { 2231021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2232021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack ack; 2233021eaef8SAnthony Koo }; 2234021eaef8SAnthony Koo } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2235021eaef8SAnthony Koo } data; /**< Command data */ 2236021eaef8SAnthony Koo 2237021eaef8SAnthony Koo }; 2238021eaef8SAnthony Koo 2239021eaef8SAnthony Koo /** 2240592a6318SAnthony Koo * union dmub_rb_cmd - DMUB inbox command. 2241592a6318SAnthony Koo */ 22427c008829SNicholas Kazlauskas union dmub_rb_cmd { 2243dc6e2448SWyatt Wood struct dmub_rb_cmd_lock_hw lock_hw; 2244592a6318SAnthony Koo /** 2245592a6318SAnthony Koo * Elements shared with all commands. 2246592a6318SAnthony Koo */ 22477c008829SNicholas Kazlauskas struct dmub_rb_cmd_common cmd_common; 2248592a6318SAnthony Koo /** 2249592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2250592a6318SAnthony Koo */ 2251592a6318SAnthony Koo struct dmub_rb_cmd_read_modify_write read_modify_write; 2252592a6318SAnthony Koo /** 2253592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2254592a6318SAnthony Koo */ 2255592a6318SAnthony Koo struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2256592a6318SAnthony Koo /** 2257592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2258592a6318SAnthony Koo */ 2259592a6318SAnthony Koo struct dmub_rb_cmd_burst_write burst_write; 2260592a6318SAnthony Koo /** 2261592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_REG_WAIT command. 2262592a6318SAnthony Koo */ 2263592a6318SAnthony Koo struct dmub_rb_cmd_reg_wait reg_wait; 2264592a6318SAnthony Koo /** 2265592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2266592a6318SAnthony Koo */ 22677c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2268592a6318SAnthony Koo /** 2269592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2270592a6318SAnthony Koo */ 22717c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2272592a6318SAnthony Koo /** 2273592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2274592a6318SAnthony Koo */ 22757c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2276592a6318SAnthony Koo /** 2277592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2278592a6318SAnthony Koo */ 22797c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init dpphy_init; 2280592a6318SAnthony Koo /** 2281592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2282592a6318SAnthony Koo */ 22837c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 22841a595f28SAnthony Koo /** 22851a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 22861a595f28SAnthony Koo */ 2287d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version psr_set_version; 22881a595f28SAnthony Koo /** 22891a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 22901a595f28SAnthony Koo */ 22917c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 22921a595f28SAnthony Koo /** 22931a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 22941a595f28SAnthony Koo */ 2295d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_enable psr_enable; 22961a595f28SAnthony Koo /** 22971a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 22981a595f28SAnthony Koo */ 22997c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level psr_set_level; 23001a595f28SAnthony Koo /** 23011a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 23021a595f28SAnthony Koo */ 2303672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static psr_force_static; 2304592a6318SAnthony Koo /** 2305592a6318SAnthony Koo * Definition of a DMUB_CMD__PLAT_54186_WA command. 2306592a6318SAnthony Koo */ 2307bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2308592a6318SAnthony Koo /** 2309592a6318SAnthony Koo * Definition of a DMUB_CMD__MALL command. 2310592a6318SAnthony Koo */ 231152f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall mall; 2312b04cb192SNicholas Kazlauskas /** 2313b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2314b04cb192SNicholas Kazlauskas */ 2315b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2316b04cb192SNicholas Kazlauskas 2317b04cb192SNicholas Kazlauskas /** 2318b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2319b04cb192SNicholas Kazlauskas */ 2320b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2321b04cb192SNicholas Kazlauskas 2322b04cb192SNicholas Kazlauskas /** 2323b04cb192SNicholas Kazlauskas * Definition of DMUB_CMD__PANEL_CNTL commands. 2324b04cb192SNicholas Kazlauskas */ 2325b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl panel_cntl; 23261a595f28SAnthony Koo /** 23271a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 23281a595f28SAnthony Koo */ 2329e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 23301a595f28SAnthony Koo 23311a595f28SAnthony Koo /** 23321a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 23331a595f28SAnthony Koo */ 2334e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 23351a595f28SAnthony Koo 23361a595f28SAnthony Koo /** 23371a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 23381a595f28SAnthony Koo */ 2339e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level abm_set_level; 23401a595f28SAnthony Koo 23411a595f28SAnthony Koo /** 23421a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 23431a595f28SAnthony Koo */ 2344e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 23451a595f28SAnthony Koo 23461a595f28SAnthony Koo /** 23471a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 23481a595f28SAnthony Koo */ 2349e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 23501a595f28SAnthony Koo 23511a595f28SAnthony Koo /** 23521a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 23531a595f28SAnthony Koo */ 235416012806SWyatt Wood struct dmub_rb_cmd_abm_init_config abm_init_config; 23551a595f28SAnthony Koo 23561a595f28SAnthony Koo /** 23571a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 23581a595f28SAnthony Koo */ 2359d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access dp_aux_access; 23601a595f28SAnthony Koo 23611a595f28SAnthony Koo /** 2362592a6318SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2363592a6318SAnthony Koo */ 2364592a6318SAnthony Koo struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2365592a6318SAnthony Koo 2366592a6318SAnthony Koo /** 2367592a6318SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 23681a595f28SAnthony Koo */ 236934ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2370592a6318SAnthony Koo struct dmub_rb_cmd_drr_update drr_update; 23711a595f28SAnthony Koo /** 23721a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 23731a595f28SAnthony Koo */ 23741a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control lvtma_control; 2375021eaef8SAnthony Koo /** 2376021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 2377021eaef8SAnthony Koo */ 2378021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea edid_cea; 23797c008829SNicholas Kazlauskas }; 23807c008829SNicholas Kazlauskas 2381592a6318SAnthony Koo /** 2382592a6318SAnthony Koo * union dmub_rb_out_cmd - Outbox command 2383592a6318SAnthony Koo */ 2384d9beecfcSAnthony Koo union dmub_rb_out_cmd { 2385592a6318SAnthony Koo /** 2386592a6318SAnthony Koo * Parameters common to every command. 2387592a6318SAnthony Koo */ 2388d9beecfcSAnthony Koo struct dmub_rb_cmd_common cmd_common; 2389592a6318SAnthony Koo /** 2390592a6318SAnthony Koo * AUX reply command. 2391592a6318SAnthony Koo */ 2392d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2393592a6318SAnthony Koo /** 2394592a6318SAnthony Koo * HPD notify command. 2395592a6318SAnthony Koo */ 2396d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2397d9beecfcSAnthony Koo }; 23987c008829SNicholas Kazlauskas #pragma pack(pop) 23997c008829SNicholas Kazlauskas 240084034ad4SAnthony Koo 240184034ad4SAnthony Koo //============================================================================== 240284034ad4SAnthony Koo //</DMUB_CMD>=================================================================== 240384034ad4SAnthony Koo //============================================================================== 240484034ad4SAnthony Koo //< DMUB_RB>==================================================================== 240584034ad4SAnthony Koo //============================================================================== 240684034ad4SAnthony Koo 240784034ad4SAnthony Koo #if defined(__cplusplus) 240884034ad4SAnthony Koo extern "C" { 240984034ad4SAnthony Koo #endif 241084034ad4SAnthony Koo 2411592a6318SAnthony Koo /** 2412592a6318SAnthony Koo * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2413592a6318SAnthony Koo */ 241484034ad4SAnthony Koo struct dmub_rb_init_params { 2415592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 2416592a6318SAnthony Koo void *base_address; /**< CPU base address for ring's data */ 2417592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2418592a6318SAnthony Koo uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2419592a6318SAnthony Koo uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 242084034ad4SAnthony Koo }; 242184034ad4SAnthony Koo 2422592a6318SAnthony Koo /** 2423592a6318SAnthony Koo * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2424592a6318SAnthony Koo */ 242584034ad4SAnthony Koo struct dmub_rb { 2426592a6318SAnthony Koo void *base_address; /**< CPU address for the ring's data */ 2427592a6318SAnthony Koo uint32_t rptr; /**< Read pointer for consumer in bytes */ 2428592a6318SAnthony Koo uint32_t wrpt; /**< Write pointer for producer in bytes */ 2429592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 243084034ad4SAnthony Koo 2431592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 2432592a6318SAnthony Koo void *dmub; /**< Pointer to the DMUB interface */ 243384034ad4SAnthony Koo }; 243484034ad4SAnthony Koo 2435592a6318SAnthony Koo /** 2436592a6318SAnthony Koo * @brief Checks if the ringbuffer is empty. 2437592a6318SAnthony Koo * 2438592a6318SAnthony Koo * @param rb DMUB Ringbuffer 2439592a6318SAnthony Koo * @return true if empty 2440592a6318SAnthony Koo * @return false otherwise 2441592a6318SAnthony Koo */ 244284034ad4SAnthony Koo static inline bool dmub_rb_empty(struct dmub_rb *rb) 244384034ad4SAnthony Koo { 244484034ad4SAnthony Koo return (rb->wrpt == rb->rptr); 244584034ad4SAnthony Koo } 244684034ad4SAnthony Koo 2447592a6318SAnthony Koo /** 2448592a6318SAnthony Koo * @brief Checks if the ringbuffer is full 2449592a6318SAnthony Koo * 2450592a6318SAnthony Koo * @param rb DMUB Ringbuffer 2451592a6318SAnthony Koo * @return true if full 2452592a6318SAnthony Koo * @return false otherwise 2453592a6318SAnthony Koo */ 245484034ad4SAnthony Koo static inline bool dmub_rb_full(struct dmub_rb *rb) 245584034ad4SAnthony Koo { 245684034ad4SAnthony Koo uint32_t data_count; 245784034ad4SAnthony Koo 245884034ad4SAnthony Koo if (rb->wrpt >= rb->rptr) 245984034ad4SAnthony Koo data_count = rb->wrpt - rb->rptr; 246084034ad4SAnthony Koo else 246184034ad4SAnthony Koo data_count = rb->capacity - (rb->rptr - rb->wrpt); 246284034ad4SAnthony Koo 246384034ad4SAnthony Koo return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 246484034ad4SAnthony Koo } 246584034ad4SAnthony Koo 2466592a6318SAnthony Koo /** 2467592a6318SAnthony Koo * @brief Pushes a command into the ringbuffer 2468592a6318SAnthony Koo * 2469592a6318SAnthony Koo * @param rb DMUB ringbuffer 2470592a6318SAnthony Koo * @param cmd The command to push 2471592a6318SAnthony Koo * @return true if the ringbuffer was not full 2472592a6318SAnthony Koo * @return false otherwise 2473592a6318SAnthony Koo */ 247484034ad4SAnthony Koo static inline bool dmub_rb_push_front(struct dmub_rb *rb, 247584034ad4SAnthony Koo const union dmub_rb_cmd *cmd) 247684034ad4SAnthony Koo { 247784034ad4SAnthony Koo uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 247884034ad4SAnthony Koo const uint64_t *src = (const uint64_t *)cmd; 247934ba432cSAnthony Koo uint8_t i; 248084034ad4SAnthony Koo 248184034ad4SAnthony Koo if (dmub_rb_full(rb)) 248284034ad4SAnthony Koo return false; 248384034ad4SAnthony Koo 248484034ad4SAnthony Koo // copying data 248584034ad4SAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 248684034ad4SAnthony Koo *dst++ = *src++; 248784034ad4SAnthony Koo 248884034ad4SAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 248984034ad4SAnthony Koo 249084034ad4SAnthony Koo if (rb->wrpt >= rb->capacity) 249184034ad4SAnthony Koo rb->wrpt %= rb->capacity; 249284034ad4SAnthony Koo 249384034ad4SAnthony Koo return true; 249484034ad4SAnthony Koo } 249584034ad4SAnthony Koo 2496592a6318SAnthony Koo /** 2497592a6318SAnthony Koo * @brief Pushes a command into the DMUB outbox ringbuffer 2498592a6318SAnthony Koo * 2499592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 2500592a6318SAnthony Koo * @param cmd Outbox command 2501592a6318SAnthony Koo * @return true if not full 2502592a6318SAnthony Koo * @return false otherwise 2503592a6318SAnthony Koo */ 2504d9beecfcSAnthony Koo static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2505d9beecfcSAnthony Koo const union dmub_rb_out_cmd *cmd) 2506d9beecfcSAnthony Koo { 2507d9beecfcSAnthony Koo uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2508*d459b79bSAnthony Koo const uint8_t *src = (const uint8_t *)cmd; 2509d9beecfcSAnthony Koo 2510d9beecfcSAnthony Koo if (dmub_rb_full(rb)) 2511d9beecfcSAnthony Koo return false; 2512d9beecfcSAnthony Koo 2513d9beecfcSAnthony Koo dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2514d9beecfcSAnthony Koo 2515d9beecfcSAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 2516d9beecfcSAnthony Koo 2517d9beecfcSAnthony Koo if (rb->wrpt >= rb->capacity) 2518d9beecfcSAnthony Koo rb->wrpt %= rb->capacity; 2519d9beecfcSAnthony Koo 2520d9beecfcSAnthony Koo return true; 2521d9beecfcSAnthony Koo } 2522d9beecfcSAnthony Koo 2523592a6318SAnthony Koo /** 2524592a6318SAnthony Koo * @brief Returns the next unprocessed command in the ringbuffer. 2525592a6318SAnthony Koo * 2526592a6318SAnthony Koo * @param rb DMUB ringbuffer 2527592a6318SAnthony Koo * @param cmd The command to return 2528592a6318SAnthony Koo * @return true if not empty 2529592a6318SAnthony Koo * @return false otherwise 2530592a6318SAnthony Koo */ 253184034ad4SAnthony Koo static inline bool dmub_rb_front(struct dmub_rb *rb, 253234ba432cSAnthony Koo union dmub_rb_cmd **cmd) 253384034ad4SAnthony Koo { 253434ba432cSAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 253584034ad4SAnthony Koo 253684034ad4SAnthony Koo if (dmub_rb_empty(rb)) 253784034ad4SAnthony Koo return false; 253884034ad4SAnthony Koo 253934ba432cSAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 254084034ad4SAnthony Koo 254184034ad4SAnthony Koo return true; 254284034ad4SAnthony Koo } 254384034ad4SAnthony Koo 2544592a6318SAnthony Koo /** 25450b51e7e8SAnthony Koo * @brief Determines the next ringbuffer offset. 25460b51e7e8SAnthony Koo * 25470b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 25480b51e7e8SAnthony Koo * @param num_cmds Number of commands 25490b51e7e8SAnthony Koo * @param next_rptr The next offset in the ringbuffer 25500b51e7e8SAnthony Koo */ 25510b51e7e8SAnthony Koo static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 25520b51e7e8SAnthony Koo uint32_t num_cmds, 25530b51e7e8SAnthony Koo uint32_t *next_rptr) 25540b51e7e8SAnthony Koo { 25550b51e7e8SAnthony Koo *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 25560b51e7e8SAnthony Koo 25570b51e7e8SAnthony Koo if (*next_rptr >= rb->capacity) 25580b51e7e8SAnthony Koo *next_rptr %= rb->capacity; 25590b51e7e8SAnthony Koo } 25600b51e7e8SAnthony Koo 25610b51e7e8SAnthony Koo /** 25620b51e7e8SAnthony Koo * @brief Returns a pointer to a command in the inbox. 25630b51e7e8SAnthony Koo * 25640b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 25650b51e7e8SAnthony Koo * @param cmd The inbox command to return 25660b51e7e8SAnthony Koo * @param rptr The ringbuffer offset 25670b51e7e8SAnthony Koo * @return true if not empty 25680b51e7e8SAnthony Koo * @return false otherwise 25690b51e7e8SAnthony Koo */ 25700b51e7e8SAnthony Koo static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 25710b51e7e8SAnthony Koo union dmub_rb_cmd **cmd, 25720b51e7e8SAnthony Koo uint32_t rptr) 25730b51e7e8SAnthony Koo { 25740b51e7e8SAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 25750b51e7e8SAnthony Koo 25760b51e7e8SAnthony Koo if (dmub_rb_empty(rb)) 25770b51e7e8SAnthony Koo return false; 25780b51e7e8SAnthony Koo 25790b51e7e8SAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 25800b51e7e8SAnthony Koo 25810b51e7e8SAnthony Koo return true; 25820b51e7e8SAnthony Koo } 25830b51e7e8SAnthony Koo 25840b51e7e8SAnthony Koo /** 2585592a6318SAnthony Koo * @brief Returns the next unprocessed command in the outbox. 2586592a6318SAnthony Koo * 2587592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 2588592a6318SAnthony Koo * @param cmd The outbox command to return 2589592a6318SAnthony Koo * @return true if not empty 2590592a6318SAnthony Koo * @return false otherwise 2591592a6318SAnthony Koo */ 2592d9beecfcSAnthony Koo static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2593d9beecfcSAnthony Koo union dmub_rb_out_cmd *cmd) 2594d9beecfcSAnthony Koo { 2595d9beecfcSAnthony Koo const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 2596d9beecfcSAnthony Koo uint64_t *dst = (uint64_t *)cmd; 259734ba432cSAnthony Koo uint8_t i; 2598d9beecfcSAnthony Koo 2599d9beecfcSAnthony Koo if (dmub_rb_empty(rb)) 2600d9beecfcSAnthony Koo return false; 2601d9beecfcSAnthony Koo 2602d9beecfcSAnthony Koo // copying data 2603d9beecfcSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 2604d9beecfcSAnthony Koo *dst++ = *src++; 2605d9beecfcSAnthony Koo 2606d9beecfcSAnthony Koo return true; 2607d9beecfcSAnthony Koo } 2608d9beecfcSAnthony Koo 2609592a6318SAnthony Koo /** 2610592a6318SAnthony Koo * @brief Removes the front entry in the ringbuffer. 2611592a6318SAnthony Koo * 2612592a6318SAnthony Koo * @param rb DMUB ringbuffer 2613592a6318SAnthony Koo * @return true if the command was removed 2614592a6318SAnthony Koo * @return false if there were no commands 2615592a6318SAnthony Koo */ 261684034ad4SAnthony Koo static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 261784034ad4SAnthony Koo { 261884034ad4SAnthony Koo if (dmub_rb_empty(rb)) 261984034ad4SAnthony Koo return false; 262084034ad4SAnthony Koo 262184034ad4SAnthony Koo rb->rptr += DMUB_RB_CMD_SIZE; 262284034ad4SAnthony Koo 262384034ad4SAnthony Koo if (rb->rptr >= rb->capacity) 262484034ad4SAnthony Koo rb->rptr %= rb->capacity; 262584034ad4SAnthony Koo 262684034ad4SAnthony Koo return true; 262784034ad4SAnthony Koo } 262884034ad4SAnthony Koo 2629592a6318SAnthony Koo /** 2630592a6318SAnthony Koo * @brief Flushes commands in the ringbuffer to framebuffer memory. 2631592a6318SAnthony Koo * 2632592a6318SAnthony Koo * Avoids a race condition where DMCUB accesses memory while 2633592a6318SAnthony Koo * there are still writes in flight to framebuffer. 2634592a6318SAnthony Koo * 2635592a6318SAnthony Koo * @param rb DMUB ringbuffer 2636592a6318SAnthony Koo */ 263784034ad4SAnthony Koo static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 263884034ad4SAnthony Koo { 263984034ad4SAnthony Koo uint32_t rptr = rb->rptr; 264084034ad4SAnthony Koo uint32_t wptr = rb->wrpt; 264184034ad4SAnthony Koo 264284034ad4SAnthony Koo while (rptr != wptr) { 264384034ad4SAnthony Koo uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 264434ba432cSAnthony Koo uint8_t i; 264584034ad4SAnthony Koo 264684034ad4SAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 26478906e5bcSYe Bin *data++; 264884034ad4SAnthony Koo 264984034ad4SAnthony Koo rptr += DMUB_RB_CMD_SIZE; 265084034ad4SAnthony Koo if (rptr >= rb->capacity) 265184034ad4SAnthony Koo rptr %= rb->capacity; 265284034ad4SAnthony Koo } 265384034ad4SAnthony Koo } 265484034ad4SAnthony Koo 2655592a6318SAnthony Koo /** 2656592a6318SAnthony Koo * @brief Initializes a DMCUB ringbuffer 2657592a6318SAnthony Koo * 2658592a6318SAnthony Koo * @param rb DMUB ringbuffer 2659592a6318SAnthony Koo * @param init_params initial configuration for the ringbuffer 2660592a6318SAnthony Koo */ 266184034ad4SAnthony Koo static inline void dmub_rb_init(struct dmub_rb *rb, 266284034ad4SAnthony Koo struct dmub_rb_init_params *init_params) 266384034ad4SAnthony Koo { 266484034ad4SAnthony Koo rb->base_address = init_params->base_address; 266584034ad4SAnthony Koo rb->capacity = init_params->capacity; 266684034ad4SAnthony Koo rb->rptr = init_params->read_ptr; 266784034ad4SAnthony Koo rb->wrpt = init_params->write_ptr; 266884034ad4SAnthony Koo } 266984034ad4SAnthony Koo 2670592a6318SAnthony Koo /** 2671592a6318SAnthony Koo * @brief Copies output data from in/out commands into the given command. 2672592a6318SAnthony Koo * 2673592a6318SAnthony Koo * @param rb DMUB ringbuffer 2674592a6318SAnthony Koo * @param cmd Command to copy data into 2675592a6318SAnthony Koo */ 267634ba432cSAnthony Koo static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 267734ba432cSAnthony Koo union dmub_rb_cmd *cmd) 267834ba432cSAnthony Koo { 267934ba432cSAnthony Koo // Copy rb entry back into command 268034ba432cSAnthony Koo uint8_t *rd_ptr = (rb->rptr == 0) ? 268134ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 268234ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 268334ba432cSAnthony Koo 268434ba432cSAnthony Koo dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 268534ba432cSAnthony Koo } 268634ba432cSAnthony Koo 268784034ad4SAnthony Koo #if defined(__cplusplus) 268884034ad4SAnthony Koo } 268984034ad4SAnthony Koo #endif 269084034ad4SAnthony Koo 269184034ad4SAnthony Koo //============================================================================== 269284034ad4SAnthony Koo //</DMUB_RB>==================================================================== 269384034ad4SAnthony Koo //============================================================================== 269484034ad4SAnthony Koo 26957c008829SNicholas Kazlauskas #endif /* _DMUB_CMD_H_ */ 2696