17c008829SNicholas Kazlauskas /* 27c008829SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 37c008829SNicholas Kazlauskas * 47c008829SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 57c008829SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 67c008829SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 77c008829SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87c008829SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 97c008829SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 107c008829SNicholas Kazlauskas * 117c008829SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 127c008829SNicholas Kazlauskas * all copies or substantial portions of the Software. 137c008829SNicholas Kazlauskas * 147c008829SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157c008829SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167c008829SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177c008829SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187c008829SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197c008829SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207c008829SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 217c008829SNicholas Kazlauskas * 227c008829SNicholas Kazlauskas * Authors: AMD 237c008829SNicholas Kazlauskas * 247c008829SNicholas Kazlauskas */ 257c008829SNicholas Kazlauskas 265624c345SAnthony Koo #ifndef DMUB_CMD_H 275624c345SAnthony Koo #define DMUB_CMD_H 287c008829SNicholas Kazlauskas 298b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 308b19a4e3SAnthony Koo #include "dmub_fw_types.h" 318b19a4e3SAnthony Koo #include "include_legacy/atomfirmware.h" 328b19a4e3SAnthony Koo 338b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) 348b19a4e3SAnthony Koo #include <string.h> 358b19a4e3SAnthony Koo #endif 368b19a4e3SAnthony Koo #else 378b19a4e3SAnthony Koo 3884034ad4SAnthony Koo #include <asm/byteorder.h> 3984034ad4SAnthony Koo #include <linux/types.h> 4084034ad4SAnthony Koo #include <linux/string.h> 4184034ad4SAnthony Koo #include <linux/delay.h> 4284034ad4SAnthony Koo 437c008829SNicholas Kazlauskas #include "atomfirmware.h" 4422aa5614SYongqiang Sun 458b19a4e3SAnthony Koo #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 468b19a4e3SAnthony Koo 4784034ad4SAnthony Koo //<DMUB_TYPES>================================================================== 4884034ad4SAnthony Koo /* Basic type definitions. */ 4984034ad4SAnthony Koo 508b19a4e3SAnthony Koo #define __forceinline inline 518b19a4e3SAnthony Koo 521a595f28SAnthony Koo /** 531a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled gradually 541a595f28SAnthony Koo * by slowly reversing all backlight programming and pixel compensation. 551a595f28SAnthony Koo */ 5684034ad4SAnthony Koo #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 571a595f28SAnthony Koo 581a595f28SAnthony Koo /** 591a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 601a595f28SAnthony Koo * and undo all backlight programming and pixel compensation. 611a595f28SAnthony Koo */ 6284034ad4SAnthony Koo #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 631a595f28SAnthony Koo 641a595f28SAnthony Koo /** 651a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 661a595f28SAnthony Koo * and keep the current backlight programming and pixel compensation. 671a595f28SAnthony Koo */ 68d9beecfcSAnthony Koo #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 691a595f28SAnthony Koo 701a595f28SAnthony Koo /** 711a595f28SAnthony Koo * Flag from driver to set the current ABM pipe index or ABM operating level. 721a595f28SAnthony Koo */ 7384034ad4SAnthony Koo #define SET_ABM_PIPE_NORMAL 1 7484034ad4SAnthony Koo 751a595f28SAnthony Koo /** 761a595f28SAnthony Koo * Number of ambient light levels in ABM algorithm. 771a595f28SAnthony Koo */ 781a595f28SAnthony Koo #define NUM_AMBI_LEVEL 5 791a595f28SAnthony Koo 801a595f28SAnthony Koo /** 811a595f28SAnthony Koo * Number of operating/aggression levels in ABM algorithm. 821a595f28SAnthony Koo */ 831a595f28SAnthony Koo #define NUM_AGGR_LEVEL 4 841a595f28SAnthony Koo 851a595f28SAnthony Koo /** 861a595f28SAnthony Koo * Number of segments in the gamma curve. 871a595f28SAnthony Koo */ 881a595f28SAnthony Koo #define NUM_POWER_FN_SEGS 8 891a595f28SAnthony Koo 901a595f28SAnthony Koo /** 911a595f28SAnthony Koo * Number of segments in the backlight curve. 921a595f28SAnthony Koo */ 931a595f28SAnthony Koo #define NUM_BL_CURVE_SEGS 16 941a595f28SAnthony Koo 9585f4bc0cSAlvin Lee /* Maximum number of SubVP streams */ 9685f4bc0cSAlvin Lee #define DMUB_MAX_SUBVP_STREAMS 2 9785f4bc0cSAlvin Lee 9884034ad4SAnthony Koo /* Maximum number of streams on any ASIC. */ 9984034ad4SAnthony Koo #define DMUB_MAX_STREAMS 6 10084034ad4SAnthony Koo 10184034ad4SAnthony Koo /* Maximum number of planes on any ASIC. */ 10284034ad4SAnthony Koo #define DMUB_MAX_PLANES 6 10384034ad4SAnthony Koo 10470732504SYongqiang Sun /* Trace buffer offset for entry */ 10570732504SYongqiang Sun #define TRACE_BUFFER_ENTRY_OFFSET 16 10670732504SYongqiang Sun 107592a6318SAnthony Koo /** 10883eb5385SDavid Zhang * Maximum number of dirty rects supported by FW. 10983eb5385SDavid Zhang */ 11083eb5385SDavid Zhang #define DMUB_MAX_DIRTY_RECTS 3 11183eb5385SDavid Zhang 11283eb5385SDavid Zhang /** 113f56c837aSMikita Lipski * 114f56c837aSMikita Lipski * PSR control version legacy 115f56c837aSMikita Lipski */ 116f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117f56c837aSMikita Lipski /** 118f56c837aSMikita Lipski * PSR control version with multi edp support 119f56c837aSMikita Lipski */ 120f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121f56c837aSMikita Lipski 122f56c837aSMikita Lipski 123f56c837aSMikita Lipski /** 12463de4f04SJake Wang * ABM control version legacy 125e922057bSJake Wang */ 12663de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127e922057bSJake Wang 128e922057bSJake Wang /** 12963de4f04SJake Wang * ABM control version with multi edp support 130e922057bSJake Wang */ 13163de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132e922057bSJake Wang 133e922057bSJake Wang /** 134592a6318SAnthony Koo * Physical framebuffer address location, 64-bit. 135592a6318SAnthony Koo */ 13684034ad4SAnthony Koo #ifndef PHYSICAL_ADDRESS_LOC 13784034ad4SAnthony Koo #define PHYSICAL_ADDRESS_LOC union large_integer 13884034ad4SAnthony Koo #endif 13984034ad4SAnthony Koo 140592a6318SAnthony Koo /** 141592a6318SAnthony Koo * OS/FW agnostic memcpy 142592a6318SAnthony Koo */ 14384034ad4SAnthony Koo #ifndef dmub_memcpy 14484034ad4SAnthony Koo #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 14584034ad4SAnthony Koo #endif 14684034ad4SAnthony Koo 147592a6318SAnthony Koo /** 148592a6318SAnthony Koo * OS/FW agnostic memset 149592a6318SAnthony Koo */ 15084034ad4SAnthony Koo #ifndef dmub_memset 15184034ad4SAnthony Koo #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 15284034ad4SAnthony Koo #endif 15384034ad4SAnthony Koo 154d9beecfcSAnthony Koo #if defined(__cplusplus) 155d9beecfcSAnthony Koo extern "C" { 156d9beecfcSAnthony Koo #endif 157d9beecfcSAnthony Koo 158592a6318SAnthony Koo /** 159592a6318SAnthony Koo * OS/FW agnostic udelay 160592a6318SAnthony Koo */ 16184034ad4SAnthony Koo #ifndef dmub_udelay 16284034ad4SAnthony Koo #define dmub_udelay(microseconds) udelay(microseconds) 16384034ad4SAnthony Koo #endif 16484034ad4SAnthony Koo 165592a6318SAnthony Koo /** 166592a6318SAnthony Koo * union dmub_addr - DMUB physical/virtual 64-bit address. 167592a6318SAnthony Koo */ 16884034ad4SAnthony Koo union dmub_addr { 16984034ad4SAnthony Koo struct { 170592a6318SAnthony Koo uint32_t low_part; /**< Lower 32 bits */ 171592a6318SAnthony Koo uint32_t high_part; /**< Upper 32 bits */ 172592a6318SAnthony Koo } u; /*<< Low/high bit access */ 173592a6318SAnthony Koo uint64_t quad_part; /*<< 64 bit address */ 17484034ad4SAnthony Koo }; 17584034ad4SAnthony Koo 1761a595f28SAnthony Koo /** 17783eb5385SDavid Zhang * Dirty rect definition. 17883eb5385SDavid Zhang */ 17983eb5385SDavid Zhang struct dmub_rect { 18083eb5385SDavid Zhang /** 18183eb5385SDavid Zhang * Dirty rect x offset. 18283eb5385SDavid Zhang */ 18383eb5385SDavid Zhang uint32_t x; 18483eb5385SDavid Zhang 18583eb5385SDavid Zhang /** 18683eb5385SDavid Zhang * Dirty rect y offset. 18783eb5385SDavid Zhang */ 18883eb5385SDavid Zhang uint32_t y; 18983eb5385SDavid Zhang 19083eb5385SDavid Zhang /** 19183eb5385SDavid Zhang * Dirty rect width. 19283eb5385SDavid Zhang */ 19383eb5385SDavid Zhang uint32_t width; 19483eb5385SDavid Zhang 19583eb5385SDavid Zhang /** 19683eb5385SDavid Zhang * Dirty rect height. 19783eb5385SDavid Zhang */ 19883eb5385SDavid Zhang uint32_t height; 19983eb5385SDavid Zhang }; 20083eb5385SDavid Zhang 20183eb5385SDavid Zhang /** 2021a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 2031a595f28SAnthony Koo */ 20484034ad4SAnthony Koo union dmub_psr_debug_flags { 2051a595f28SAnthony Koo /** 2061a595f28SAnthony Koo * Debug flags. 2071a595f28SAnthony Koo */ 20884034ad4SAnthony Koo struct { 2091a595f28SAnthony Koo /** 2101a595f28SAnthony Koo * Enable visual confirm in FW. 2111a595f28SAnthony Koo */ 212447f3d0fSAnthony Koo uint32_t visual_confirm : 1; 21383eb5385SDavid Zhang 21483eb5385SDavid Zhang /** 21583eb5385SDavid Zhang * Force all selective updates to bw full frame updates. 21683eb5385SDavid Zhang */ 21783eb5385SDavid Zhang uint32_t force_full_frame_update : 1; 21883eb5385SDavid Zhang 2191a595f28SAnthony Koo /** 2201a595f28SAnthony Koo * Use HW Lock Mgr object to do HW locking in FW. 2211a595f28SAnthony Koo */ 222447f3d0fSAnthony Koo uint32_t use_hw_lock_mgr : 1; 2231a595f28SAnthony Koo 2241a595f28SAnthony Koo /** 225548f2125SRobin Chen * Use TPS3 signal when restore main link. 2261a595f28SAnthony Koo */ 227548f2125SRobin Chen uint32_t force_wakeup_by_tps3 : 1; 228*cf472dbdSAnthony Koo 229*cf472dbdSAnthony Koo /** 230*cf472dbdSAnthony Koo * Back to back flip, therefore cannot power down PHY 231*cf472dbdSAnthony Koo */ 232*cf472dbdSAnthony Koo uint32_t back_to_back_flip : 1; 233*cf472dbdSAnthony Koo 23484034ad4SAnthony Koo } bitfields; 23584034ad4SAnthony Koo 2361a595f28SAnthony Koo /** 2371a595f28SAnthony Koo * Union for debug flags. 2381a595f28SAnthony Koo */ 239447f3d0fSAnthony Koo uint32_t u32All; 24084034ad4SAnthony Koo }; 24184034ad4SAnthony Koo 2421a595f28SAnthony Koo /** 2430991f44cSAnthony Koo * DMUB visual confirm color 2441a595f28SAnthony Koo */ 24534ba432cSAnthony Koo struct dmub_feature_caps { 2461a595f28SAnthony Koo /** 2471a595f28SAnthony Koo * Max PSR version supported by FW. 2481a595f28SAnthony Koo */ 24934ba432cSAnthony Koo uint8_t psr; 25000fa7f03SRodrigo Siqueira uint8_t fw_assisted_mclk_switch; 25100fa7f03SRodrigo Siqueira uint8_t reserved[6]; 25234ba432cSAnthony Koo }; 25334ba432cSAnthony Koo 254b09c1fffSLeo (Hanghong) Ma struct dmub_visual_confirm_color { 255b09c1fffSLeo (Hanghong) Ma /** 256b09c1fffSLeo (Hanghong) Ma * Maximum 10 bits color value 257b09c1fffSLeo (Hanghong) Ma */ 258b09c1fffSLeo (Hanghong) Ma uint16_t color_r_cr; 259b09c1fffSLeo (Hanghong) Ma uint16_t color_g_y; 260b09c1fffSLeo (Hanghong) Ma uint16_t color_b_cb; 261b09c1fffSLeo (Hanghong) Ma uint16_t panel_inst; 262b09c1fffSLeo (Hanghong) Ma }; 263b09c1fffSLeo (Hanghong) Ma 26484034ad4SAnthony Koo #if defined(__cplusplus) 26584034ad4SAnthony Koo } 26684034ad4SAnthony Koo #endif 26784034ad4SAnthony Koo 26884034ad4SAnthony Koo //============================================================================== 26984034ad4SAnthony Koo //</DMUB_TYPES>================================================================= 27084034ad4SAnthony Koo //============================================================================== 27184034ad4SAnthony Koo //< DMUB_META>================================================================== 27284034ad4SAnthony Koo //============================================================================== 27384034ad4SAnthony Koo #pragma pack(push, 1) 27484034ad4SAnthony Koo 27584034ad4SAnthony Koo /* Magic value for identifying dmub_fw_meta_info */ 27684034ad4SAnthony Koo #define DMUB_FW_META_MAGIC 0x444D5542 27784034ad4SAnthony Koo 27884034ad4SAnthony Koo /* Offset from the end of the file to the dmub_fw_meta_info */ 27984034ad4SAnthony Koo #define DMUB_FW_META_OFFSET 0x24 28084034ad4SAnthony Koo 28184034ad4SAnthony Koo /** 28284034ad4SAnthony Koo * struct dmub_fw_meta_info - metadata associated with fw binary 28384034ad4SAnthony Koo * 28484034ad4SAnthony Koo * NOTE: This should be considered a stable API. Fields should 28584034ad4SAnthony Koo * not be repurposed or reordered. New fields should be 28684034ad4SAnthony Koo * added instead to extend the structure. 28784034ad4SAnthony Koo * 28884034ad4SAnthony Koo * @magic_value: magic value identifying DMUB firmware meta info 28984034ad4SAnthony Koo * @fw_region_size: size of the firmware state region 29084034ad4SAnthony Koo * @trace_buffer_size: size of the tracebuffer region 29184034ad4SAnthony Koo * @fw_version: the firmware version information 292b2265774SAnthony Koo * @dal_fw: 1 if the firmware is DAL 29384034ad4SAnthony Koo */ 29484034ad4SAnthony Koo struct dmub_fw_meta_info { 295592a6318SAnthony Koo uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 296592a6318SAnthony Koo uint32_t fw_region_size; /**< size of the firmware state region */ 297592a6318SAnthony Koo uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 298592a6318SAnthony Koo uint32_t fw_version; /**< the firmware version information */ 299592a6318SAnthony Koo uint8_t dal_fw; /**< 1 if the firmware is DAL */ 300592a6318SAnthony Koo uint8_t reserved[3]; /**< padding bits */ 30184034ad4SAnthony Koo }; 30284034ad4SAnthony Koo 303592a6318SAnthony Koo /** 304592a6318SAnthony Koo * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 305592a6318SAnthony Koo */ 30684034ad4SAnthony Koo union dmub_fw_meta { 307592a6318SAnthony Koo struct dmub_fw_meta_info info; /**< metadata info */ 308592a6318SAnthony Koo uint8_t reserved[64]; /**< padding bits */ 30984034ad4SAnthony Koo }; 31084034ad4SAnthony Koo 31184034ad4SAnthony Koo #pragma pack(pop) 312788408b7SAnthony Koo 31384034ad4SAnthony Koo //============================================================================== 3146b66208fSYongqiang Sun //< DMUB Trace Buffer>================================================================ 3156b66208fSYongqiang Sun //============================================================================== 316592a6318SAnthony Koo /** 317592a6318SAnthony Koo * dmub_trace_code_t - firmware trace code, 32-bits 318592a6318SAnthony Koo */ 3196b66208fSYongqiang Sun typedef uint32_t dmub_trace_code_t; 3206b66208fSYongqiang Sun 321592a6318SAnthony Koo /** 322592a6318SAnthony Koo * struct dmcub_trace_buf_entry - Firmware trace entry 323592a6318SAnthony Koo */ 3246b66208fSYongqiang Sun struct dmcub_trace_buf_entry { 325592a6318SAnthony Koo dmub_trace_code_t trace_code; /**< trace code for the event */ 326592a6318SAnthony Koo uint32_t tick_count; /**< the tick count at time of trace */ 327592a6318SAnthony Koo uint32_t param0; /**< trace defined parameter 0 */ 328592a6318SAnthony Koo uint32_t param1; /**< trace defined parameter 1 */ 3296b66208fSYongqiang Sun }; 3306b66208fSYongqiang Sun 3316b66208fSYongqiang Sun //============================================================================== 332788408b7SAnthony Koo //< DMUB_STATUS>================================================================ 333788408b7SAnthony Koo //============================================================================== 334788408b7SAnthony Koo 335788408b7SAnthony Koo /** 336788408b7SAnthony Koo * DMCUB scratch registers can be used to determine firmware status. 337788408b7SAnthony Koo * Current scratch register usage is as follows: 338788408b7SAnthony Koo * 339492dd8a8SAnthony Koo * SCRATCH0: FW Boot Status register 340021eaef8SAnthony Koo * SCRATCH5: LVTMA Status Register 341492dd8a8SAnthony Koo * SCRATCH15: FW Boot Options register 342788408b7SAnthony Koo */ 343788408b7SAnthony Koo 344592a6318SAnthony Koo /** 345592a6318SAnthony Koo * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 346592a6318SAnthony Koo */ 347492dd8a8SAnthony Koo union dmub_fw_boot_status { 348492dd8a8SAnthony Koo struct { 349592a6318SAnthony Koo uint32_t dal_fw : 1; /**< 1 if DAL FW */ 350592a6318SAnthony Koo uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 351592a6318SAnthony Koo uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 352592a6318SAnthony Koo uint32_t restore_required : 1; /**< 1 if driver should call restore */ 35301934c30SAnthony Koo uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 35401934c30SAnthony Koo uint32_t reserved : 1; 35501934c30SAnthony Koo uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 35601934c30SAnthony Koo 357592a6318SAnthony Koo } bits; /**< status bits */ 358592a6318SAnthony Koo uint32_t all; /**< 32-bit access to status bits */ 359492dd8a8SAnthony Koo }; 360492dd8a8SAnthony Koo 361592a6318SAnthony Koo /** 362592a6318SAnthony Koo * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 363592a6318SAnthony Koo */ 364492dd8a8SAnthony Koo enum dmub_fw_boot_status_bit { 365592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 366592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 367592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 368592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 3691e0958bbSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 37001934c30SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 371492dd8a8SAnthony Koo }; 372492dd8a8SAnthony Koo 373021eaef8SAnthony Koo /* Register bit definition for SCRATCH5 */ 374021eaef8SAnthony Koo union dmub_lvtma_status { 375021eaef8SAnthony Koo struct { 376021eaef8SAnthony Koo uint32_t psp_ok : 1; 377021eaef8SAnthony Koo uint32_t edp_on : 1; 378021eaef8SAnthony Koo uint32_t reserved : 30; 379021eaef8SAnthony Koo } bits; 380021eaef8SAnthony Koo uint32_t all; 381021eaef8SAnthony Koo }; 382021eaef8SAnthony Koo 383021eaef8SAnthony Koo enum dmub_lvtma_status_bit { 384021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 385021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 386021eaef8SAnthony Koo }; 387021eaef8SAnthony Koo 388592a6318SAnthony Koo /** 3891e0958bbSAnthony Koo * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 390592a6318SAnthony Koo */ 391492dd8a8SAnthony Koo union dmub_fw_boot_options { 392492dd8a8SAnthony Koo struct { 393592a6318SAnthony Koo uint32_t pemu_env : 1; /**< 1 if PEMU */ 394592a6318SAnthony Koo uint32_t fpga_env : 1; /**< 1 if FPGA */ 395592a6318SAnthony Koo uint32_t optimized_init : 1; /**< 1 if optimized init */ 396592a6318SAnthony Koo uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 397592a6318SAnthony Koo uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 398592a6318SAnthony Koo uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 399b04cb192SNicholas Kazlauskas uint32_t z10_disable: 1; /**< 1 to disable z10 */ 400b0ce6272SMeenakshikumar Somasundaram uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 4011e0958bbSAnthony Koo uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 4023137f792SHansen uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 4033137f792SHansen uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 4043137f792SHansen /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 4053137f792SHansen uint32_t power_optimization: 1; 406b129c94eSAnthony Koo uint32_t diag_env: 1; /* 1 if diagnostic environment */ 4075cef7e8eSAnthony Koo uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 408ea5a4db9SAnthony Koo uint32_t usb4_cm_version: 1; /**< 1 CM support */ 4096f4f8ff5SMeenakshikumar Somasundaram uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 410b129c94eSAnthony Koo 4116f4f8ff5SMeenakshikumar Somasundaram uint32_t reserved : 16; /**< reserved */ 412592a6318SAnthony Koo } bits; /**< boot bits */ 413592a6318SAnthony Koo uint32_t all; /**< 32-bit access to bits */ 414492dd8a8SAnthony Koo }; 415492dd8a8SAnthony Koo 416492dd8a8SAnthony Koo enum dmub_fw_boot_options_bit { 417592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 418592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 419592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 420492dd8a8SAnthony Koo }; 421492dd8a8SAnthony Koo 422788408b7SAnthony Koo //============================================================================== 423788408b7SAnthony Koo //</DMUB_STATUS>================================================================ 42484034ad4SAnthony Koo //============================================================================== 42584034ad4SAnthony Koo //< DMUB_VBIOS>================================================================= 42684034ad4SAnthony Koo //============================================================================== 42784034ad4SAnthony Koo 42884034ad4SAnthony Koo /* 429592a6318SAnthony Koo * enum dmub_cmd_vbios_type - VBIOS commands. 430592a6318SAnthony Koo * 43184034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 43284034ad4SAnthony Koo * Do not reuse or modify IDs. 43384034ad4SAnthony Koo */ 43484034ad4SAnthony Koo enum dmub_cmd_vbios_type { 435592a6318SAnthony Koo /** 436592a6318SAnthony Koo * Configures the DIG encoder. 437592a6318SAnthony Koo */ 43884034ad4SAnthony Koo DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 439592a6318SAnthony Koo /** 440592a6318SAnthony Koo * Controls the PHY. 441592a6318SAnthony Koo */ 44284034ad4SAnthony Koo DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 443592a6318SAnthony Koo /** 444592a6318SAnthony Koo * Sets the pixel clock/symbol clock. 445592a6318SAnthony Koo */ 44684034ad4SAnthony Koo DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 447592a6318SAnthony Koo /** 448592a6318SAnthony Koo * Enables or disables power gating. 449592a6318SAnthony Koo */ 45084034ad4SAnthony Koo DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 45141f91315SNicholas Kazlauskas /** 45241f91315SNicholas Kazlauskas * Controls embedded panels. 45341f91315SNicholas Kazlauskas */ 4542ac685bfSAnthony Koo DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 45541f91315SNicholas Kazlauskas /** 45641f91315SNicholas Kazlauskas * Query DP alt status on a transmitter. 45741f91315SNicholas Kazlauskas */ 45841f91315SNicholas Kazlauskas DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 45984034ad4SAnthony Koo }; 46084034ad4SAnthony Koo 46184034ad4SAnthony Koo //============================================================================== 46284034ad4SAnthony Koo //</DMUB_VBIOS>================================================================= 46384034ad4SAnthony Koo //============================================================================== 46484034ad4SAnthony Koo //< DMUB_GPINT>================================================================= 46584034ad4SAnthony Koo //============================================================================== 46684034ad4SAnthony Koo 46784034ad4SAnthony Koo /** 46884034ad4SAnthony Koo * The shifts and masks below may alternatively be used to format and read 46984034ad4SAnthony Koo * the command register bits. 47084034ad4SAnthony Koo */ 47184034ad4SAnthony Koo 47284034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 47384034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_SHIFT 0 47484034ad4SAnthony Koo 47584034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 47684034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 47784034ad4SAnthony Koo 47884034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_MASK 0xF 47984034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_SHIFT 28 48084034ad4SAnthony Koo 48184034ad4SAnthony Koo /** 48284034ad4SAnthony Koo * Command responses. 48384034ad4SAnthony Koo */ 48484034ad4SAnthony Koo 485592a6318SAnthony Koo /** 486592a6318SAnthony Koo * Return response for DMUB_GPINT__STOP_FW command. 487592a6318SAnthony Koo */ 48884034ad4SAnthony Koo #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 48984034ad4SAnthony Koo 49084034ad4SAnthony Koo /** 491592a6318SAnthony Koo * union dmub_gpint_data_register - Format for sending a command via the GPINT. 49284034ad4SAnthony Koo */ 49384034ad4SAnthony Koo union dmub_gpint_data_register { 49484034ad4SAnthony Koo struct { 495592a6318SAnthony Koo uint32_t param : 16; /**< 16-bit parameter */ 496592a6318SAnthony Koo uint32_t command_code : 12; /**< GPINT command */ 497592a6318SAnthony Koo uint32_t status : 4; /**< Command status bit */ 498592a6318SAnthony Koo } bits; /**< GPINT bit access */ 499592a6318SAnthony Koo uint32_t all; /**< GPINT 32-bit access */ 50084034ad4SAnthony Koo }; 50184034ad4SAnthony Koo 50284034ad4SAnthony Koo /* 503592a6318SAnthony Koo * enum dmub_gpint_command - GPINT command to DMCUB FW 504592a6318SAnthony Koo * 50584034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 50684034ad4SAnthony Koo * Do not reuse or modify IDs. 50784034ad4SAnthony Koo */ 50884034ad4SAnthony Koo enum dmub_gpint_command { 509592a6318SAnthony Koo /** 510592a6318SAnthony Koo * Invalid command, ignored. 511592a6318SAnthony Koo */ 51284034ad4SAnthony Koo DMUB_GPINT__INVALID_COMMAND = 0, 513592a6318SAnthony Koo /** 514592a6318SAnthony Koo * DESC: Queries the firmware version. 515592a6318SAnthony Koo * RETURN: Firmware version. 516592a6318SAnthony Koo */ 51784034ad4SAnthony Koo DMUB_GPINT__GET_FW_VERSION = 1, 518592a6318SAnthony Koo /** 519592a6318SAnthony Koo * DESC: Halts the firmware. 520592a6318SAnthony Koo * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 521592a6318SAnthony Koo */ 52284034ad4SAnthony Koo DMUB_GPINT__STOP_FW = 2, 5231a595f28SAnthony Koo /** 5241a595f28SAnthony Koo * DESC: Get PSR state from FW. 5251a595f28SAnthony Koo * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 5261a595f28SAnthony Koo */ 52784034ad4SAnthony Koo DMUB_GPINT__GET_PSR_STATE = 7, 52880eba958SAnthony Koo /** 52980eba958SAnthony Koo * DESC: Notifies DMCUB of the currently active streams. 53080eba958SAnthony Koo * ARGS: Stream mask, 1 bit per active stream index. 53180eba958SAnthony Koo */ 53280eba958SAnthony Koo DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 5331a595f28SAnthony Koo /** 5341a595f28SAnthony Koo * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 5351a595f28SAnthony Koo * ARGS: We can measure residency from various points. The argument will specify the residency mode. 5361a595f28SAnthony Koo * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 5371a595f28SAnthony Koo * RETURN: PSR residency in milli-percent. 5381a595f28SAnthony Koo */ 539672251b2SAnthony Koo DMUB_GPINT__PSR_RESIDENCY = 9, 54001934c30SAnthony Koo 54101934c30SAnthony Koo /** 54201934c30SAnthony Koo * DESC: Notifies DMCUB detection is done so detection required can be cleared. 54301934c30SAnthony Koo */ 54401934c30SAnthony Koo DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 54584034ad4SAnthony Koo }; 54684034ad4SAnthony Koo 5470b51e7e8SAnthony Koo /** 5480b51e7e8SAnthony Koo * INBOX0 generic command definition 5490b51e7e8SAnthony Koo */ 5500b51e7e8SAnthony Koo union dmub_inbox0_cmd_common { 5510b51e7e8SAnthony Koo struct { 5520b51e7e8SAnthony Koo uint32_t command_code: 8; /**< INBOX0 command code */ 5530b51e7e8SAnthony Koo uint32_t param: 24; /**< 24-bit parameter */ 5540b51e7e8SAnthony Koo } bits; 5550b51e7e8SAnthony Koo uint32_t all; 5560b51e7e8SAnthony Koo }; 5570b51e7e8SAnthony Koo 5580b51e7e8SAnthony Koo /** 5590b51e7e8SAnthony Koo * INBOX0 hw_lock command definition 5600b51e7e8SAnthony Koo */ 5610b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw { 5620b51e7e8SAnthony Koo struct { 5630b51e7e8SAnthony Koo uint32_t command_code: 8; 5640b51e7e8SAnthony Koo 5650b51e7e8SAnthony Koo /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 5662412d339SAnthony Koo uint32_t hw_lock_client: 2; 5670b51e7e8SAnthony Koo 5680b51e7e8SAnthony Koo /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 5690b51e7e8SAnthony Koo uint32_t otg_inst: 3; 5700b51e7e8SAnthony Koo uint32_t opp_inst: 3; 5710b51e7e8SAnthony Koo uint32_t dig_inst: 3; 5720b51e7e8SAnthony Koo 5730b51e7e8SAnthony Koo /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 5740b51e7e8SAnthony Koo uint32_t lock_pipe: 1; 5750b51e7e8SAnthony Koo uint32_t lock_cursor: 1; 5760b51e7e8SAnthony Koo uint32_t lock_dig: 1; 5770b51e7e8SAnthony Koo uint32_t triple_buffer_lock: 1; 5780b51e7e8SAnthony Koo 5790b51e7e8SAnthony Koo uint32_t lock: 1; /**< Lock */ 5800b51e7e8SAnthony Koo uint32_t should_release: 1; /**< Release */ 5812412d339SAnthony Koo uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 5820b51e7e8SAnthony Koo } bits; 5830b51e7e8SAnthony Koo uint32_t all; 5840b51e7e8SAnthony Koo }; 5850b51e7e8SAnthony Koo 5860b51e7e8SAnthony Koo union dmub_inbox0_data_register { 5870b51e7e8SAnthony Koo union dmub_inbox0_cmd_common inbox0_cmd_common; 5880b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 5890b51e7e8SAnthony Koo }; 5900b51e7e8SAnthony Koo 5910b51e7e8SAnthony Koo enum dmub_inbox0_command { 5920b51e7e8SAnthony Koo /** 5930b51e7e8SAnthony Koo * DESC: Invalid command, ignored. 5940b51e7e8SAnthony Koo */ 5950b51e7e8SAnthony Koo DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 5960b51e7e8SAnthony Koo /** 5970b51e7e8SAnthony Koo * DESC: Notification to acquire/release HW lock 5980b51e7e8SAnthony Koo * ARGS: 5990b51e7e8SAnthony Koo */ 6000b51e7e8SAnthony Koo DMUB_INBOX0_CMD__HW_LOCK = 1, 6010b51e7e8SAnthony Koo }; 60284034ad4SAnthony Koo //============================================================================== 60384034ad4SAnthony Koo //</DMUB_GPINT>================================================================= 60484034ad4SAnthony Koo //============================================================================== 60584034ad4SAnthony Koo //< DMUB_CMD>=================================================================== 60684034ad4SAnthony Koo //============================================================================== 60784034ad4SAnthony Koo 608592a6318SAnthony Koo /** 609592a6318SAnthony Koo * Size in bytes of each DMUB command. 610592a6318SAnthony Koo */ 6117c008829SNicholas Kazlauskas #define DMUB_RB_CMD_SIZE 64 612592a6318SAnthony Koo 613592a6318SAnthony Koo /** 614592a6318SAnthony Koo * Maximum number of items in the DMUB ringbuffer. 615592a6318SAnthony Koo */ 6167c008829SNicholas Kazlauskas #define DMUB_RB_MAX_ENTRY 128 617592a6318SAnthony Koo 618592a6318SAnthony Koo /** 619592a6318SAnthony Koo * Ringbuffer size in bytes. 620592a6318SAnthony Koo */ 6217c008829SNicholas Kazlauskas #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 622592a6318SAnthony Koo 623592a6318SAnthony Koo /** 624592a6318SAnthony Koo * REG_SET mask for reg offload. 625592a6318SAnthony Koo */ 6267c008829SNicholas Kazlauskas #define REG_SET_MASK 0xFFFF 6277c008829SNicholas Kazlauskas 628d4bbcecbSNicholas Kazlauskas /* 629592a6318SAnthony Koo * enum dmub_cmd_type - DMUB inbox command. 630592a6318SAnthony Koo * 631d4bbcecbSNicholas Kazlauskas * Command IDs should be treated as stable ABI. 632d4bbcecbSNicholas Kazlauskas * Do not reuse or modify IDs. 633d4bbcecbSNicholas Kazlauskas */ 634d4bbcecbSNicholas Kazlauskas enum dmub_cmd_type { 635592a6318SAnthony Koo /** 636592a6318SAnthony Koo * Invalid command. 637592a6318SAnthony Koo */ 638d4bbcecbSNicholas Kazlauskas DMUB_CMD__NULL = 0, 639592a6318SAnthony Koo /** 640592a6318SAnthony Koo * Read modify write register sequence offload. 641592a6318SAnthony Koo */ 642d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 643592a6318SAnthony Koo /** 644592a6318SAnthony Koo * Field update register sequence offload. 645592a6318SAnthony Koo */ 646d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 647592a6318SAnthony Koo /** 648592a6318SAnthony Koo * Burst write sequence offload. 649592a6318SAnthony Koo */ 650d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 651592a6318SAnthony Koo /** 652592a6318SAnthony Koo * Reg wait sequence offload. 653592a6318SAnthony Koo */ 654d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_REG_WAIT = 4, 655592a6318SAnthony Koo /** 656592a6318SAnthony Koo * Workaround to avoid HUBP underflow during NV12 playback. 657592a6318SAnthony Koo */ 658bae9c49bSYongqiang Sun DMUB_CMD__PLAT_54186_WA = 5, 6591a595f28SAnthony Koo /** 6601a595f28SAnthony Koo * Command type used to query FW feature caps. 6611a595f28SAnthony Koo */ 66234ba432cSAnthony Koo DMUB_CMD__QUERY_FEATURE_CAPS = 6, 6631a595f28SAnthony Koo /** 664b09c1fffSLeo (Hanghong) Ma * Command type used to get visual confirm color. 665b09c1fffSLeo (Hanghong) Ma */ 666b09c1fffSLeo (Hanghong) Ma DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 667b09c1fffSLeo (Hanghong) Ma /** 6681a595f28SAnthony Koo * Command type used for all PSR commands. 6691a595f28SAnthony Koo */ 670d4bbcecbSNicholas Kazlauskas DMUB_CMD__PSR = 64, 671592a6318SAnthony Koo /** 672592a6318SAnthony Koo * Command type used for all MALL commands. 673592a6318SAnthony Koo */ 67452f2e83eSBhawanpreet Lakha DMUB_CMD__MALL = 65, 6751a595f28SAnthony Koo /** 6761a595f28SAnthony Koo * Command type used for all ABM commands. 6771a595f28SAnthony Koo */ 678e6ea8c34SWyatt Wood DMUB_CMD__ABM = 66, 6791a595f28SAnthony Koo /** 68083eb5385SDavid Zhang * Command type used to update dirty rects in FW. 68183eb5385SDavid Zhang */ 68283eb5385SDavid Zhang DMUB_CMD__UPDATE_DIRTY_RECT = 67, 68383eb5385SDavid Zhang /** 68483eb5385SDavid Zhang * Command type used to update cursor info in FW. 68583eb5385SDavid Zhang */ 68683eb5385SDavid Zhang DMUB_CMD__UPDATE_CURSOR_INFO = 68, 68783eb5385SDavid Zhang /** 6881a595f28SAnthony Koo * Command type used for HW locking in FW. 6891a595f28SAnthony Koo */ 690788408b7SAnthony Koo DMUB_CMD__HW_LOCK = 69, 6911a595f28SAnthony Koo /** 6921a595f28SAnthony Koo * Command type used to access DP AUX. 6931a595f28SAnthony Koo */ 694d9beecfcSAnthony Koo DMUB_CMD__DP_AUX_ACCESS = 70, 6951a595f28SAnthony Koo /** 6961a595f28SAnthony Koo * Command type used for OUTBOX1 notification enable 6971a595f28SAnthony Koo */ 698d9beecfcSAnthony Koo DMUB_CMD__OUTBOX1_ENABLE = 71, 6995cef7e8eSAnthony Koo 700b04cb192SNicholas Kazlauskas /** 701b04cb192SNicholas Kazlauskas * Command type used for all idle optimization commands. 702b04cb192SNicholas Kazlauskas */ 703b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT = 72, 704b04cb192SNicholas Kazlauskas /** 705b04cb192SNicholas Kazlauskas * Command type used for all clock manager commands. 706b04cb192SNicholas Kazlauskas */ 707b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR = 73, 708b04cb192SNicholas Kazlauskas /** 709b04cb192SNicholas Kazlauskas * Command type used for all panel control commands. 710b04cb192SNicholas Kazlauskas */ 711b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL = 74, 712ac2e555eSAurabindo Pillai /** 713ac2e555eSAurabindo Pillai * Command type used for <TODO:description> 714ac2e555eSAurabindo Pillai */ 715ac2e555eSAurabindo Pillai DMUB_CMD__CAB_FOR_SS = 75, 71685f4bc0cSAlvin Lee 71785f4bc0cSAlvin Lee DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 71885f4bc0cSAlvin Lee 719592a6318SAnthony Koo /** 72076724b76SJimmy Kizito * Command type used for interfacing with DPIA. 72176724b76SJimmy Kizito */ 72276724b76SJimmy Kizito DMUB_CMD__DPIA = 77, 72376724b76SJimmy Kizito /** 724021eaef8SAnthony Koo * Command type used for EDID CEA parsing 725021eaef8SAnthony Koo */ 726021eaef8SAnthony Koo DMUB_CMD__EDID_CEA = 79, 727021eaef8SAnthony Koo /** 728c595fb05SWenjing Liu * Command type used for getting usbc cable ID 729c595fb05SWenjing Liu */ 730c595fb05SWenjing Liu DMUB_CMD_GET_USBC_CABLE_ID = 81, 731c595fb05SWenjing Liu /** 732ea5a4db9SAnthony Koo * Command type used to query HPD state. 733ea5a4db9SAnthony Koo */ 734ea5a4db9SAnthony Koo DMUB_CMD__QUERY_HPD_STATE = 82, 735ea5a4db9SAnthony Koo /** 736592a6318SAnthony Koo * Command type used for all VBIOS interface commands. 737592a6318SAnthony Koo */ 7381fb695d9SAnthony Koo 739c0459bddSAlan Liu /** 740c0459bddSAlan Liu * Command type used for all SECURE_DISPLAY commands. 741c0459bddSAlan Liu */ 742c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY = 85, 7436f4f8ff5SMeenakshikumar Somasundaram 7446f4f8ff5SMeenakshikumar Somasundaram /** 7456f4f8ff5SMeenakshikumar Somasundaram * Command type used to set DPIA HPD interrupt state 7466f4f8ff5SMeenakshikumar Somasundaram */ 7476f4f8ff5SMeenakshikumar Somasundaram DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 7486f4f8ff5SMeenakshikumar Somasundaram 749d4bbcecbSNicholas Kazlauskas DMUB_CMD__VBIOS = 128, 7507c008829SNicholas Kazlauskas }; 7517c008829SNicholas Kazlauskas 752592a6318SAnthony Koo /** 753592a6318SAnthony Koo * enum dmub_out_cmd_type - DMUB outbox commands. 754592a6318SAnthony Koo */ 7553b37260bSAnthony Koo enum dmub_out_cmd_type { 756592a6318SAnthony Koo /** 757592a6318SAnthony Koo * Invalid outbox command, ignored. 758592a6318SAnthony Koo */ 7593b37260bSAnthony Koo DMUB_OUT_CMD__NULL = 0, 7601a595f28SAnthony Koo /** 7611a595f28SAnthony Koo * Command type used for DP AUX Reply data notification 7621a595f28SAnthony Koo */ 763d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_AUX_REPLY = 1, 764892b74a6SMeenakshikumar Somasundaram /** 765892b74a6SMeenakshikumar Somasundaram * Command type used for DP HPD event notification 766892b74a6SMeenakshikumar Somasundaram */ 767892b74a6SMeenakshikumar Somasundaram DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 76871af9d46SMeenakshikumar Somasundaram /** 76971af9d46SMeenakshikumar Somasundaram * Command type used for SET_CONFIG Reply notification 77071af9d46SMeenakshikumar Somasundaram */ 77171af9d46SMeenakshikumar Somasundaram DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 7723b37260bSAnthony Koo }; 7733b37260bSAnthony Koo 77476724b76SJimmy Kizito /* DMUB_CMD__DPIA command sub-types. */ 77576724b76SJimmy Kizito enum dmub_cmd_dpia_type { 77676724b76SJimmy Kizito DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 77771af9d46SMeenakshikumar Somasundaram DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 778139a3311SMeenakshikumar Somasundaram DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 77976724b76SJimmy Kizito }; 78076724b76SJimmy Kizito 7817c008829SNicholas Kazlauskas #pragma pack(push, 1) 7827c008829SNicholas Kazlauskas 783592a6318SAnthony Koo /** 784592a6318SAnthony Koo * struct dmub_cmd_header - Common command header fields. 785592a6318SAnthony Koo */ 7867c008829SNicholas Kazlauskas struct dmub_cmd_header { 787592a6318SAnthony Koo unsigned int type : 8; /**< command type */ 788592a6318SAnthony Koo unsigned int sub_type : 8; /**< command sub type */ 789592a6318SAnthony Koo unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 7900b51e7e8SAnthony Koo unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 7910b51e7e8SAnthony Koo unsigned int reserved0 : 6; /**< reserved bits */ 792592a6318SAnthony Koo unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 793592a6318SAnthony Koo unsigned int reserved1 : 2; /**< reserved bits */ 7947c008829SNicholas Kazlauskas }; 7957c008829SNicholas Kazlauskas 7967c008829SNicholas Kazlauskas /* 797592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write 7987c008829SNicholas Kazlauskas * 7997c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 5 sets of read modify writes, 8007c008829SNicholas Kazlauskas * each take 3 dwords. 8017c008829SNicholas Kazlauskas * 8027c008829SNicholas Kazlauskas * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 8037c008829SNicholas Kazlauskas * 8047c008829SNicholas Kazlauskas * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 8057c008829SNicholas Kazlauskas * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 8067c008829SNicholas Kazlauskas */ 8077c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence { 808592a6318SAnthony Koo uint32_t addr; /**< register address */ 809592a6318SAnthony Koo uint32_t modify_mask; /**< modify mask */ 810592a6318SAnthony Koo uint32_t modify_value; /**< modify value */ 8117c008829SNicholas Kazlauskas }; 8127c008829SNicholas Kazlauskas 813592a6318SAnthony Koo /** 814592a6318SAnthony Koo * Maximum number of ops in read modify write sequence. 815592a6318SAnthony Koo */ 8167c008829SNicholas Kazlauskas #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 817592a6318SAnthony Koo 818592a6318SAnthony Koo /** 819592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 820592a6318SAnthony Koo */ 8217c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write { 822592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 823592a6318SAnthony Koo /** 824592a6318SAnthony Koo * Read modify write sequence. 825592a6318SAnthony Koo */ 8267c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 8277c008829SNicholas Kazlauskas }; 8287c008829SNicholas Kazlauskas 8297c008829SNicholas Kazlauskas /* 8307c008829SNicholas Kazlauskas * Update a register with specified masks and values sequeunce 8317c008829SNicholas Kazlauskas * 8327c008829SNicholas Kazlauskas * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 8337c008829SNicholas Kazlauskas * 8347c008829SNicholas Kazlauskas * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 8357c008829SNicholas Kazlauskas * 8367c008829SNicholas Kazlauskas * 8377c008829SNicholas Kazlauskas * USE CASE: 8387c008829SNicholas Kazlauskas * 1. auto-increment register where additional read would update pointer and produce wrong result 8397c008829SNicholas Kazlauskas * 2. toggle a bit without read in the middle 8407c008829SNicholas Kazlauskas */ 8417c008829SNicholas Kazlauskas 8427c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence { 843592a6318SAnthony Koo uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 844592a6318SAnthony Koo uint32_t modify_value; /**< value to update with */ 8457c008829SNicholas Kazlauskas }; 8467c008829SNicholas Kazlauskas 847592a6318SAnthony Koo /** 848592a6318SAnthony Koo * Maximum number of ops in field update sequence. 849592a6318SAnthony Koo */ 8507c008829SNicholas Kazlauskas #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 851592a6318SAnthony Koo 852592a6318SAnthony Koo /** 853592a6318SAnthony Koo * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 854592a6318SAnthony Koo */ 8557c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence { 856592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 857592a6318SAnthony Koo uint32_t addr; /**< register address */ 858592a6318SAnthony Koo /** 859592a6318SAnthony Koo * Field update sequence. 860592a6318SAnthony Koo */ 8617c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 8627c008829SNicholas Kazlauskas }; 8637c008829SNicholas Kazlauskas 864592a6318SAnthony Koo 865592a6318SAnthony Koo /** 866592a6318SAnthony Koo * Maximum number of burst write values. 867592a6318SAnthony Koo */ 868592a6318SAnthony Koo #define DMUB_BURST_WRITE_VALUES__MAX 14 869592a6318SAnthony Koo 8707c008829SNicholas Kazlauskas /* 871592a6318SAnthony Koo * struct dmub_rb_cmd_burst_write - Burst write 8727c008829SNicholas Kazlauskas * 8737c008829SNicholas Kazlauskas * support use case such as writing out LUTs. 8747c008829SNicholas Kazlauskas * 8757c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 14 values to write to given address 8767c008829SNicholas Kazlauskas * 8777c008829SNicholas Kazlauskas * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 8787c008829SNicholas Kazlauskas */ 8797c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write { 880592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 881592a6318SAnthony Koo uint32_t addr; /**< register start address */ 882592a6318SAnthony Koo /** 883592a6318SAnthony Koo * Burst write register values. 884592a6318SAnthony Koo */ 8857c008829SNicholas Kazlauskas uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 8867c008829SNicholas Kazlauskas }; 8877c008829SNicholas Kazlauskas 888592a6318SAnthony Koo /** 889592a6318SAnthony Koo * struct dmub_rb_cmd_common - Common command header 890592a6318SAnthony Koo */ 8917c008829SNicholas Kazlauskas struct dmub_rb_cmd_common { 892592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 893592a6318SAnthony Koo /** 894592a6318SAnthony Koo * Padding to RB_CMD_SIZE 895592a6318SAnthony Koo */ 8967c008829SNicholas Kazlauskas uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 8977c008829SNicholas Kazlauskas }; 8987c008829SNicholas Kazlauskas 899592a6318SAnthony Koo /** 900592a6318SAnthony Koo * struct dmub_cmd_reg_wait_data - Register wait data 901592a6318SAnthony Koo */ 9027c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data { 903592a6318SAnthony Koo uint32_t addr; /**< Register address */ 904592a6318SAnthony Koo uint32_t mask; /**< Mask for register bits */ 905592a6318SAnthony Koo uint32_t condition_field_value; /**< Value to wait for */ 906592a6318SAnthony Koo uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 9077c008829SNicholas Kazlauskas }; 9087c008829SNicholas Kazlauskas 909592a6318SAnthony Koo /** 910592a6318SAnthony Koo * struct dmub_rb_cmd_reg_wait - Register wait command 911592a6318SAnthony Koo */ 9127c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait { 913592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 914592a6318SAnthony Koo struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 9157c008829SNicholas Kazlauskas }; 9167c008829SNicholas Kazlauskas 917592a6318SAnthony Koo /** 918592a6318SAnthony Koo * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 919592a6318SAnthony Koo * 920592a6318SAnthony Koo * Reprograms surface parameters to avoid underflow. 921592a6318SAnthony Koo */ 922bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa { 923592a6318SAnthony Koo uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 924592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 925592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 926592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 927592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 92822aa5614SYongqiang Sun struct { 929592a6318SAnthony Koo uint8_t hubp_inst : 4; /**< HUBP instance */ 930592a6318SAnthony Koo uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 931592a6318SAnthony Koo uint8_t immediate :1; /**< Immediate flip */ 932592a6318SAnthony Koo uint8_t vmid : 4; /**< VMID */ 933592a6318SAnthony Koo uint8_t grph_stereo : 1; /**< 1 if stereo */ 934592a6318SAnthony Koo uint32_t reserved : 21; /**< Reserved */ 935592a6318SAnthony Koo } flip_params; /**< Pageflip parameters */ 936592a6318SAnthony Koo uint32_t reserved[9]; /**< Reserved bits */ 9378c019253SYongqiang Sun }; 9388c019253SYongqiang Sun 939592a6318SAnthony Koo /** 940592a6318SAnthony Koo * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 941592a6318SAnthony Koo */ 942bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa { 943592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 944592a6318SAnthony Koo struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 9458c019253SYongqiang Sun }; 9468c019253SYongqiang Sun 947592a6318SAnthony Koo /** 948592a6318SAnthony Koo * struct dmub_rb_cmd_mall - MALL command data. 949592a6318SAnthony Koo */ 95052f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall { 951592a6318SAnthony Koo struct dmub_cmd_header header; /**< Common command header */ 952592a6318SAnthony Koo union dmub_addr cursor_copy_src; /**< Cursor copy address */ 953592a6318SAnthony Koo union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 954592a6318SAnthony Koo uint32_t tmr_delay; /**< Timer delay */ 955592a6318SAnthony Koo uint32_t tmr_scale; /**< Timer scale */ 956592a6318SAnthony Koo uint16_t cursor_width; /**< Cursor width in pixels */ 957592a6318SAnthony Koo uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 958592a6318SAnthony Koo uint16_t cursor_height; /**< Cursor height in pixels */ 959592a6318SAnthony Koo uint8_t cursor_bpp; /**< Cursor bits per pixel */ 960592a6318SAnthony Koo uint8_t debug_bits; /**< Debug bits */ 961ea7154d8SBhawanpreet Lakha 962592a6318SAnthony Koo uint8_t reserved1; /**< Reserved bits */ 963592a6318SAnthony Koo uint8_t reserved2; /**< Reserved bits */ 96452f2e83eSBhawanpreet Lakha }; 96552f2e83eSBhawanpreet Lakha 966b04cb192SNicholas Kazlauskas /** 967ac2e555eSAurabindo Pillai * enum dmub_cmd_cab_type - TODO: 968ac2e555eSAurabindo Pillai */ 969ac2e555eSAurabindo Pillai enum dmub_cmd_cab_type { 970ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 971ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_DCN_REQ = 1, 972ac2e555eSAurabindo Pillai DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 973ac2e555eSAurabindo Pillai }; 974ac2e555eSAurabindo Pillai 975ac2e555eSAurabindo Pillai /** 976ac2e555eSAurabindo Pillai * struct dmub_rb_cmd_cab_for_ss - TODO: 977ac2e555eSAurabindo Pillai */ 978ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss { 979ac2e555eSAurabindo Pillai struct dmub_cmd_header header; 980ac2e555eSAurabindo Pillai uint8_t cab_alloc_ways; /* total number of ways */ 981ac2e555eSAurabindo Pillai uint8_t debug_bits; /* debug bits */ 982ac2e555eSAurabindo Pillai }; 98385f4bc0cSAlvin Lee 98485f4bc0cSAlvin Lee enum mclk_switch_mode { 98585f4bc0cSAlvin Lee NONE = 0, 98685f4bc0cSAlvin Lee FPO = 1, 98785f4bc0cSAlvin Lee SUBVP = 2, 98885f4bc0cSAlvin Lee VBLANK = 3, 98985f4bc0cSAlvin Lee }; 99085f4bc0cSAlvin Lee 99185f4bc0cSAlvin Lee /* Per pipe struct which stores the MCLK switch mode 99285f4bc0cSAlvin Lee * data to be sent to DMUB. 99385f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 99485f4bc0cSAlvin Lee * the type name can be updated 99585f4bc0cSAlvin Lee */ 99685f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 99785f4bc0cSAlvin Lee union { 99885f4bc0cSAlvin Lee struct { 99985f4bc0cSAlvin Lee uint32_t pix_clk_100hz; 100085f4bc0cSAlvin Lee uint16_t main_vblank_start; 100185f4bc0cSAlvin Lee uint16_t main_vblank_end; 100285f4bc0cSAlvin Lee uint16_t mall_region_lines; 100385f4bc0cSAlvin Lee uint16_t prefetch_lines; 100485f4bc0cSAlvin Lee uint16_t prefetch_to_mall_start_lines; 100585f4bc0cSAlvin Lee uint16_t processing_delay_lines; 100685f4bc0cSAlvin Lee uint16_t htotal; // required to calculate line time for multi-display cases 100785f4bc0cSAlvin Lee uint16_t vtotal; 100885f4bc0cSAlvin Lee uint8_t main_pipe_index; 100985f4bc0cSAlvin Lee uint8_t phantom_pipe_index; 10100acc5b06SAnthony Koo /* Since the microschedule is calculated in terms of OTG lines, 10110acc5b06SAnthony Koo * include any scaling factors to make sure when we get accurate 10120acc5b06SAnthony Koo * conversion when programming MALL_START_LINE (which is in terms 10130acc5b06SAnthony Koo * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 10140acc5b06SAnthony Koo * is 1/2 (numerator = 1, denominator = 2). 10150acc5b06SAnthony Koo */ 10160acc5b06SAnthony Koo uint8_t scale_factor_numerator; 10170acc5b06SAnthony Koo uint8_t scale_factor_denominator; 101881f776b6SAnthony Koo uint8_t is_drr; 10191591a647SAnthony Koo uint8_t main_split_pipe_index; 10201591a647SAnthony Koo uint8_t phantom_split_pipe_index; 102185f4bc0cSAlvin Lee } subvp_data; 102285f4bc0cSAlvin Lee 102385f4bc0cSAlvin Lee struct { 102485f4bc0cSAlvin Lee uint32_t pix_clk_100hz; 102585f4bc0cSAlvin Lee uint16_t vblank_start; 102685f4bc0cSAlvin Lee uint16_t vblank_end; 102785f4bc0cSAlvin Lee uint16_t vstartup_start; 102885f4bc0cSAlvin Lee uint16_t vtotal; 102985f4bc0cSAlvin Lee uint16_t htotal; 103085f4bc0cSAlvin Lee uint8_t vblank_pipe_index; 103185f4bc0cSAlvin Lee uint8_t padding[2]; 103285f4bc0cSAlvin Lee struct { 103385f4bc0cSAlvin Lee uint8_t drr_in_use; 103485f4bc0cSAlvin Lee uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 103585f4bc0cSAlvin Lee uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 103685f4bc0cSAlvin Lee uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 103785f4bc0cSAlvin Lee uint8_t use_ramping; // Use ramping or not 103885f4bc0cSAlvin Lee } drr_info; // DRR considered as part of SubVP + VBLANK case 103985f4bc0cSAlvin Lee } vblank_data; 104085f4bc0cSAlvin Lee } pipe_config; 104185f4bc0cSAlvin Lee 10420acc5b06SAnthony Koo /* - subvp_data in the union (pipe_config) takes up 27 bytes. 10430acc5b06SAnthony Koo * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 10440acc5b06SAnthony Koo * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 10450acc5b06SAnthony Koo */ 10460acc5b06SAnthony Koo uint8_t mode; // enum mclk_switch_mode 104785f4bc0cSAlvin Lee }; 104885f4bc0cSAlvin Lee 104985f4bc0cSAlvin Lee /** 105085f4bc0cSAlvin Lee * Config data for Sub-VP and FPO 105185f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 105285f4bc0cSAlvin Lee * the type name can be updated 105385f4bc0cSAlvin Lee */ 105485f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 105585f4bc0cSAlvin Lee uint16_t watermark_a_cache; 105685f4bc0cSAlvin Lee uint8_t vertical_int_margin_us; 105785f4bc0cSAlvin Lee uint8_t pstate_allow_width_us; 105885f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 105985f4bc0cSAlvin Lee }; 106085f4bc0cSAlvin Lee 106185f4bc0cSAlvin Lee /** 106285f4bc0cSAlvin Lee * DMUB rb command definition for Sub-VP and FPO 106385f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 106485f4bc0cSAlvin Lee * the type name can be updated 106585f4bc0cSAlvin Lee */ 106685f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 106785f4bc0cSAlvin Lee struct dmub_cmd_header header; 106885f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 106985f4bc0cSAlvin Lee }; 107085f4bc0cSAlvin Lee 1071ac2e555eSAurabindo Pillai /** 1072b04cb192SNicholas Kazlauskas * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1073b04cb192SNicholas Kazlauskas */ 1074b04cb192SNicholas Kazlauskas enum dmub_cmd_idle_opt_type { 1075b04cb192SNicholas Kazlauskas /** 1076b04cb192SNicholas Kazlauskas * DCN hardware restore. 1077b04cb192SNicholas Kazlauskas */ 1078b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1079f586fea8SJake Wang 1080f586fea8SJake Wang /** 1081f586fea8SJake Wang * DCN hardware save. 1082f586fea8SJake Wang */ 1083f586fea8SJake Wang DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1084b04cb192SNicholas Kazlauskas }; 1085b04cb192SNicholas Kazlauskas 1086b04cb192SNicholas Kazlauskas /** 1087b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1088b04cb192SNicholas Kazlauskas */ 1089b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore { 1090b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1091b04cb192SNicholas Kazlauskas }; 1092b04cb192SNicholas Kazlauskas 1093b04cb192SNicholas Kazlauskas /** 1094b04cb192SNicholas Kazlauskas * struct dmub_clocks - Clock update notification. 1095b04cb192SNicholas Kazlauskas */ 1096b04cb192SNicholas Kazlauskas struct dmub_clocks { 1097b04cb192SNicholas Kazlauskas uint32_t dispclk_khz; /**< dispclk kHz */ 1098b04cb192SNicholas Kazlauskas uint32_t dppclk_khz; /**< dppclk kHz */ 1099b04cb192SNicholas Kazlauskas uint32_t dcfclk_khz; /**< dcfclk kHz */ 1100b04cb192SNicholas Kazlauskas uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1101b04cb192SNicholas Kazlauskas }; 1102b04cb192SNicholas Kazlauskas 1103b04cb192SNicholas Kazlauskas /** 1104b04cb192SNicholas Kazlauskas * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1105b04cb192SNicholas Kazlauskas */ 1106b04cb192SNicholas Kazlauskas enum dmub_cmd_clk_mgr_type { 1107b04cb192SNicholas Kazlauskas /** 1108b04cb192SNicholas Kazlauskas * Notify DMCUB of clock update. 1109b04cb192SNicholas Kazlauskas */ 1110b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1111b04cb192SNicholas Kazlauskas }; 1112b04cb192SNicholas Kazlauskas 1113b04cb192SNicholas Kazlauskas /** 1114b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1115b04cb192SNicholas Kazlauskas */ 1116b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks { 1117b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1118b04cb192SNicholas Kazlauskas struct dmub_clocks clocks; /**< clock data */ 1119b04cb192SNicholas Kazlauskas }; 11208fe44c08SAlex Deucher 1121592a6318SAnthony Koo /** 1122592a6318SAnthony Koo * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1123592a6318SAnthony Koo */ 11247c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data { 1125592a6318SAnthony Koo union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 11267c008829SNicholas Kazlauskas }; 11277c008829SNicholas Kazlauskas 1128592a6318SAnthony Koo /** 1129592a6318SAnthony Koo * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1130592a6318SAnthony Koo */ 11317c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control { 1132592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1133592a6318SAnthony Koo struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 11347c008829SNicholas Kazlauskas }; 11357c008829SNicholas Kazlauskas 1136592a6318SAnthony Koo /** 1137592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1138592a6318SAnthony Koo */ 11397c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data { 1140592a6318SAnthony Koo struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 11417c008829SNicholas Kazlauskas }; 11427c008829SNicholas Kazlauskas 1143592a6318SAnthony Koo /** 1144592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1145592a6318SAnthony Koo */ 11467c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock { 1147592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1148592a6318SAnthony Koo struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 11497c008829SNicholas Kazlauskas }; 11507c008829SNicholas Kazlauskas 1151592a6318SAnthony Koo /** 1152592a6318SAnthony Koo * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1153592a6318SAnthony Koo */ 11547c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data { 1155592a6318SAnthony Koo struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 11567c008829SNicholas Kazlauskas }; 11577c008829SNicholas Kazlauskas 1158592a6318SAnthony Koo /** 1159592a6318SAnthony Koo * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1160592a6318SAnthony Koo */ 11617c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating { 1162592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1163592a6318SAnthony Koo struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 11647c008829SNicholas Kazlauskas }; 11657c008829SNicholas Kazlauskas 1166592a6318SAnthony Koo /** 1167592a6318SAnthony Koo * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1168592a6318SAnthony Koo */ 1169d448521eSAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 { 1170d448521eSAnthony Koo uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1171d448521eSAnthony Koo uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1172d448521eSAnthony Koo union { 1173d448521eSAnthony Koo uint8_t digmode; /**< enum atom_encode_mode_def */ 1174d448521eSAnthony Koo uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1175d448521eSAnthony Koo } mode_laneset; 1176d448521eSAnthony Koo uint8_t lanenum; /**< Number of lanes */ 1177d448521eSAnthony Koo union { 1178d448521eSAnthony Koo uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1179d448521eSAnthony Koo } symclk_units; 1180d448521eSAnthony Koo uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1181d448521eSAnthony Koo uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1182d448521eSAnthony Koo uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 11835a2730fcSFangzhi Zuo uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1184d448521eSAnthony Koo uint8_t reserved1; /**< For future use */ 1185d448521eSAnthony Koo uint8_t reserved2[3]; /**< For future use */ 1186d448521eSAnthony Koo uint32_t reserved3[11]; /**< For future use */ 1187d448521eSAnthony Koo }; 1188d448521eSAnthony Koo 1189592a6318SAnthony Koo /** 1190592a6318SAnthony Koo * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1191592a6318SAnthony Koo */ 1192d448521eSAnthony Koo union dmub_cmd_dig1_transmitter_control_data { 1193592a6318SAnthony Koo struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1194592a6318SAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 11957c008829SNicholas Kazlauskas }; 11967c008829SNicholas Kazlauskas 1197592a6318SAnthony Koo /** 1198592a6318SAnthony Koo * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1199592a6318SAnthony Koo */ 12007c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control { 1201592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1202592a6318SAnthony Koo union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 12037c008829SNicholas Kazlauskas }; 12047c008829SNicholas Kazlauskas 1205592a6318SAnthony Koo /** 120676724b76SJimmy Kizito * DPIA tunnel command parameters. 120776724b76SJimmy Kizito */ 120876724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data { 120976724b76SJimmy Kizito uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 121076724b76SJimmy Kizito uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 121176724b76SJimmy Kizito union { 121276724b76SJimmy Kizito uint8_t digmode; /** enum atom_encode_mode_def */ 121376724b76SJimmy Kizito uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 121476724b76SJimmy Kizito } mode_laneset; 121576724b76SJimmy Kizito uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 121676724b76SJimmy Kizito uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 121776724b76SJimmy Kizito uint8_t hpdsel; /** =0: HPD is not assigned */ 121876724b76SJimmy Kizito uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 121976724b76SJimmy Kizito uint8_t dpia_id; /** Index of DPIA */ 122076724b76SJimmy Kizito uint8_t fec_rdy : 1; 122176724b76SJimmy Kizito uint8_t reserved : 7; 122276724b76SJimmy Kizito uint32_t reserved1; 122376724b76SJimmy Kizito }; 122476724b76SJimmy Kizito 122576724b76SJimmy Kizito /** 122676724b76SJimmy Kizito * DMUB command for DPIA tunnel control. 122776724b76SJimmy Kizito */ 122876724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control { 122976724b76SJimmy Kizito struct dmub_cmd_header header; 123076724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data dpia_control; 123176724b76SJimmy Kizito }; 123276724b76SJimmy Kizito 123376724b76SJimmy Kizito /** 123471af9d46SMeenakshikumar Somasundaram * SET_CONFIG Command Payload 123571af9d46SMeenakshikumar Somasundaram */ 123671af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload { 123771af9d46SMeenakshikumar Somasundaram uint8_t msg_type; /* set config message type */ 123871af9d46SMeenakshikumar Somasundaram uint8_t msg_data; /* set config message data */ 123971af9d46SMeenakshikumar Somasundaram }; 124071af9d46SMeenakshikumar Somasundaram 124171af9d46SMeenakshikumar Somasundaram /** 124271af9d46SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 124371af9d46SMeenakshikumar Somasundaram */ 124471af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data { 124571af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload cmd_pkt; 124671af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */ 124771af9d46SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned in case of error */ 124871af9d46SMeenakshikumar Somasundaram }; 124971af9d46SMeenakshikumar Somasundaram 125071af9d46SMeenakshikumar Somasundaram /** 125171af9d46SMeenakshikumar Somasundaram * DMUB command structure for SET_CONFIG command. 125271af9d46SMeenakshikumar Somasundaram */ 125371af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access { 125471af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 125571af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 125671af9d46SMeenakshikumar Somasundaram }; 125771af9d46SMeenakshikumar Somasundaram 125871af9d46SMeenakshikumar Somasundaram /** 1259139a3311SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1260139a3311SMeenakshikumar Somasundaram */ 1261139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data { 1262139a3311SMeenakshikumar Somasundaram uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1263139a3311SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */ 1264139a3311SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1265139a3311SMeenakshikumar Somasundaram uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1266139a3311SMeenakshikumar Somasundaram }; 1267139a3311SMeenakshikumar Somasundaram 1268139a3311SMeenakshikumar Somasundaram /** 1269139a3311SMeenakshikumar Somasundaram * DMUB command structure for SET_ command. 1270139a3311SMeenakshikumar Somasundaram */ 1271139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots { 1272139a3311SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 1273139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1274139a3311SMeenakshikumar Somasundaram }; 1275139a3311SMeenakshikumar Somasundaram 1276139a3311SMeenakshikumar Somasundaram /** 12776f4f8ff5SMeenakshikumar Somasundaram * DMUB command structure for DPIA HPD int enable control. 12786f4f8ff5SMeenakshikumar Somasundaram */ 12796f4f8ff5SMeenakshikumar Somasundaram struct dmub_rb_cmd_dpia_hpd_int_enable { 12806f4f8ff5SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 12816f4f8ff5SMeenakshikumar Somasundaram uint32_t enable; /* dpia hpd interrupt enable */ 12826f4f8ff5SMeenakshikumar Somasundaram }; 12836f4f8ff5SMeenakshikumar Somasundaram 12846f4f8ff5SMeenakshikumar Somasundaram /** 1285592a6318SAnthony Koo * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1286592a6318SAnthony Koo */ 12877c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init { 1288592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1289592a6318SAnthony Koo uint8_t reserved[60]; /**< reserved bits */ 12907c008829SNicholas Kazlauskas }; 12917c008829SNicholas Kazlauskas 12921a595f28SAnthony Koo /** 12931a595f28SAnthony Koo * enum dp_aux_request_action - DP AUX request command listing. 12941a595f28SAnthony Koo * 12951a595f28SAnthony Koo * 4 AUX request command bits are shifted to high nibble. 12961a595f28SAnthony Koo */ 1297d9beecfcSAnthony Koo enum dp_aux_request_action { 12981a595f28SAnthony Koo /** I2C-over-AUX write request */ 1299d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 13001a595f28SAnthony Koo /** I2C-over-AUX read request */ 1301d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ = 0x10, 13021a595f28SAnthony Koo /** I2C-over-AUX write status request */ 1303d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 13041a595f28SAnthony Koo /** I2C-over-AUX write request with MOT=1 */ 1305d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 13061a595f28SAnthony Koo /** I2C-over-AUX read request with MOT=1 */ 1307d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 13081a595f28SAnthony Koo /** I2C-over-AUX write status request with MOT=1 */ 1309d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 13101a595f28SAnthony Koo /** Native AUX write request */ 1311d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 13121a595f28SAnthony Koo /** Native AUX read request */ 1313d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1314d9beecfcSAnthony Koo }; 1315d9beecfcSAnthony Koo 13161a595f28SAnthony Koo /** 13171a595f28SAnthony Koo * enum aux_return_code_type - DP AUX process return code listing. 13181a595f28SAnthony Koo */ 1319fd0f1d21SAnthony Koo enum aux_return_code_type { 13201a595f28SAnthony Koo /** AUX process succeeded */ 1321fd0f1d21SAnthony Koo AUX_RET_SUCCESS = 0, 13221a595f28SAnthony Koo /** AUX process failed with unknown reason */ 1323b6402afeSAnthony Koo AUX_RET_ERROR_UNKNOWN, 13241a595f28SAnthony Koo /** AUX process completed with invalid reply */ 1325b6402afeSAnthony Koo AUX_RET_ERROR_INVALID_REPLY, 13261a595f28SAnthony Koo /** AUX process timed out */ 1327fd0f1d21SAnthony Koo AUX_RET_ERROR_TIMEOUT, 13281a595f28SAnthony Koo /** HPD was low during AUX process */ 1329b6402afeSAnthony Koo AUX_RET_ERROR_HPD_DISCON, 13301a595f28SAnthony Koo /** Failed to acquire AUX engine */ 1331b6402afeSAnthony Koo AUX_RET_ERROR_ENGINE_ACQUIRE, 13321a595f28SAnthony Koo /** AUX request not supported */ 1333fd0f1d21SAnthony Koo AUX_RET_ERROR_INVALID_OPERATION, 13341a595f28SAnthony Koo /** AUX process not available */ 1335fd0f1d21SAnthony Koo AUX_RET_ERROR_PROTOCOL_ERROR, 1336fd0f1d21SAnthony Koo }; 1337fd0f1d21SAnthony Koo 13381a595f28SAnthony Koo /** 13391a595f28SAnthony Koo * enum aux_channel_type - DP AUX channel type listing. 13401a595f28SAnthony Koo */ 1341b6402afeSAnthony Koo enum aux_channel_type { 13421a595f28SAnthony Koo /** AUX thru Legacy DP AUX */ 1343b6402afeSAnthony Koo AUX_CHANNEL_LEGACY_DDC, 13441a595f28SAnthony Koo /** AUX thru DPIA DP tunneling */ 1345b6402afeSAnthony Koo AUX_CHANNEL_DPIA 1346b6402afeSAnthony Koo }; 1347b6402afeSAnthony Koo 13481a595f28SAnthony Koo /** 13491a595f28SAnthony Koo * struct aux_transaction_parameters - DP AUX request transaction data 13501a595f28SAnthony Koo */ 1351d9beecfcSAnthony Koo struct aux_transaction_parameters { 13521a595f28SAnthony Koo uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 13531a595f28SAnthony Koo uint8_t action; /**< enum dp_aux_request_action */ 13541a595f28SAnthony Koo uint8_t length; /**< DP AUX request data length */ 13551a595f28SAnthony Koo uint8_t reserved; /**< For future use */ 13561a595f28SAnthony Koo uint32_t address; /**< DP AUX address */ 13571a595f28SAnthony Koo uint8_t data[16]; /**< DP AUX write data */ 1358d9beecfcSAnthony Koo }; 1359d9beecfcSAnthony Koo 13601a595f28SAnthony Koo /** 13611a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 13621a595f28SAnthony Koo */ 1363d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data { 13641a595f28SAnthony Koo uint8_t instance; /**< AUX instance or DPIA instance */ 13651a595f28SAnthony Koo uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 13661a595f28SAnthony Koo uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 13671a595f28SAnthony Koo uint8_t reserved0; /**< For future use */ 13681a595f28SAnthony Koo uint16_t timeout; /**< timeout time in us */ 13691a595f28SAnthony Koo uint16_t reserved1; /**< For future use */ 13701a595f28SAnthony Koo enum aux_channel_type type; /**< enum aux_channel_type */ 13711a595f28SAnthony Koo struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1372d9beecfcSAnthony Koo }; 1373d9beecfcSAnthony Koo 13741a595f28SAnthony Koo /** 13751a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 13761a595f28SAnthony Koo */ 1377d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access { 13781a595f28SAnthony Koo /** 13791a595f28SAnthony Koo * Command header. 13801a595f28SAnthony Koo */ 1381d9beecfcSAnthony Koo struct dmub_cmd_header header; 13821a595f28SAnthony Koo /** 13831a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 13841a595f28SAnthony Koo */ 1385d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data aux_control; 1386d9beecfcSAnthony Koo }; 1387d9beecfcSAnthony Koo 13881a595f28SAnthony Koo /** 13891a595f28SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 13901a595f28SAnthony Koo */ 1391d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable { 13921a595f28SAnthony Koo /** 13931a595f28SAnthony Koo * Command header. 13941a595f28SAnthony Koo */ 1395d9beecfcSAnthony Koo struct dmub_cmd_header header; 13961a595f28SAnthony Koo /** 13971a595f28SAnthony Koo * enable: 0x0 -> disable outbox1 notification (default value) 13981a595f28SAnthony Koo * 0x1 -> enable outbox1 notification 13991a595f28SAnthony Koo */ 1400d9beecfcSAnthony Koo uint32_t enable; 1401d9beecfcSAnthony Koo }; 1402d9beecfcSAnthony Koo 1403d9beecfcSAnthony Koo /* DP AUX Reply command - OutBox Cmd */ 14041a595f28SAnthony Koo /** 14051a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14061a595f28SAnthony Koo */ 1407d9beecfcSAnthony Koo struct aux_reply_data { 14081a595f28SAnthony Koo /** 14091a595f28SAnthony Koo * Aux cmd 14101a595f28SAnthony Koo */ 1411d9beecfcSAnthony Koo uint8_t command; 14121a595f28SAnthony Koo /** 14131a595f28SAnthony Koo * Aux reply data length (max: 16 bytes) 14141a595f28SAnthony Koo */ 1415d9beecfcSAnthony Koo uint8_t length; 14161a595f28SAnthony Koo /** 14171a595f28SAnthony Koo * Alignment only 14181a595f28SAnthony Koo */ 1419d9beecfcSAnthony Koo uint8_t pad[2]; 14201a595f28SAnthony Koo /** 14211a595f28SAnthony Koo * Aux reply data 14221a595f28SAnthony Koo */ 1423d9beecfcSAnthony Koo uint8_t data[16]; 1424d9beecfcSAnthony Koo }; 1425d9beecfcSAnthony Koo 14261a595f28SAnthony Koo /** 14271a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14281a595f28SAnthony Koo */ 1429d9beecfcSAnthony Koo struct aux_reply_control_data { 14301a595f28SAnthony Koo /** 14311a595f28SAnthony Koo * Reserved for future use 14321a595f28SAnthony Koo */ 1433d9beecfcSAnthony Koo uint32_t handle; 14341a595f28SAnthony Koo /** 14351a595f28SAnthony Koo * Aux Instance 14361a595f28SAnthony Koo */ 1437b6402afeSAnthony Koo uint8_t instance; 14381a595f28SAnthony Koo /** 14391a595f28SAnthony Koo * Aux transaction result: definition in enum aux_return_code_type 14401a595f28SAnthony Koo */ 1441d9beecfcSAnthony Koo uint8_t result; 14421a595f28SAnthony Koo /** 14431a595f28SAnthony Koo * Alignment only 14441a595f28SAnthony Koo */ 1445d9beecfcSAnthony Koo uint16_t pad; 1446d9beecfcSAnthony Koo }; 1447d9beecfcSAnthony Koo 14481a595f28SAnthony Koo /** 14491a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 14501a595f28SAnthony Koo */ 1451d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply { 14521a595f28SAnthony Koo /** 14531a595f28SAnthony Koo * Command header. 14541a595f28SAnthony Koo */ 1455d9beecfcSAnthony Koo struct dmub_cmd_header header; 14561a595f28SAnthony Koo /** 14571a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14581a595f28SAnthony Koo */ 1459d9beecfcSAnthony Koo struct aux_reply_control_data control; 14601a595f28SAnthony Koo /** 14611a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14621a595f28SAnthony Koo */ 1463d9beecfcSAnthony Koo struct aux_reply_data reply_data; 1464d9beecfcSAnthony Koo }; 1465d9beecfcSAnthony Koo 1466fd0f1d21SAnthony Koo /* DP HPD Notify command - OutBox Cmd */ 14671a595f28SAnthony Koo /** 14681a595f28SAnthony Koo * DP HPD Type 14691a595f28SAnthony Koo */ 1470fd0f1d21SAnthony Koo enum dp_hpd_type { 14711a595f28SAnthony Koo /** 14721a595f28SAnthony Koo * Normal DP HPD 14731a595f28SAnthony Koo */ 1474fd0f1d21SAnthony Koo DP_HPD = 0, 14751a595f28SAnthony Koo /** 14761a595f28SAnthony Koo * DP HPD short pulse 14771a595f28SAnthony Koo */ 1478fd0f1d21SAnthony Koo DP_IRQ 1479fd0f1d21SAnthony Koo }; 1480fd0f1d21SAnthony Koo 14811a595f28SAnthony Koo /** 14821a595f28SAnthony Koo * DP HPD Status 14831a595f28SAnthony Koo */ 1484fd0f1d21SAnthony Koo enum dp_hpd_status { 14851a595f28SAnthony Koo /** 14861a595f28SAnthony Koo * DP_HPD status low 14871a595f28SAnthony Koo */ 1488fd0f1d21SAnthony Koo DP_HPD_UNPLUG = 0, 14891a595f28SAnthony Koo /** 14901a595f28SAnthony Koo * DP_HPD status high 14911a595f28SAnthony Koo */ 1492fd0f1d21SAnthony Koo DP_HPD_PLUG 1493fd0f1d21SAnthony Koo }; 1494fd0f1d21SAnthony Koo 14951a595f28SAnthony Koo /** 14961a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 14971a595f28SAnthony Koo */ 1498d9beecfcSAnthony Koo struct dp_hpd_data { 14991a595f28SAnthony Koo /** 15001a595f28SAnthony Koo * DP HPD instance 15011a595f28SAnthony Koo */ 1502b6402afeSAnthony Koo uint8_t instance; 15031a595f28SAnthony Koo /** 15041a595f28SAnthony Koo * HPD type 15051a595f28SAnthony Koo */ 1506d9beecfcSAnthony Koo uint8_t hpd_type; 15071a595f28SAnthony Koo /** 15081a595f28SAnthony Koo * HPD status: only for type: DP_HPD to indicate status 15091a595f28SAnthony Koo */ 1510d9beecfcSAnthony Koo uint8_t hpd_status; 15111a595f28SAnthony Koo /** 15121a595f28SAnthony Koo * Alignment only 15131a595f28SAnthony Koo */ 1514d9beecfcSAnthony Koo uint8_t pad; 1515d9beecfcSAnthony Koo }; 1516d9beecfcSAnthony Koo 15171a595f28SAnthony Koo /** 15181a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 15191a595f28SAnthony Koo */ 1520d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify { 15211a595f28SAnthony Koo /** 15221a595f28SAnthony Koo * Command header. 15231a595f28SAnthony Koo */ 1524d9beecfcSAnthony Koo struct dmub_cmd_header header; 15251a595f28SAnthony Koo /** 15261a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 15271a595f28SAnthony Koo */ 1528d9beecfcSAnthony Koo struct dp_hpd_data hpd_data; 1529d9beecfcSAnthony Koo }; 1530d9beecfcSAnthony Koo 153171af9d46SMeenakshikumar Somasundaram /** 153271af9d46SMeenakshikumar Somasundaram * Definition of a SET_CONFIG reply from DPOA. 153371af9d46SMeenakshikumar Somasundaram */ 153471af9d46SMeenakshikumar Somasundaram enum set_config_status { 153571af9d46SMeenakshikumar Somasundaram SET_CONFIG_PENDING = 0, 153671af9d46SMeenakshikumar Somasundaram SET_CONFIG_ACK_RECEIVED, 153771af9d46SMeenakshikumar Somasundaram SET_CONFIG_RX_TIMEOUT, 153871af9d46SMeenakshikumar Somasundaram SET_CONFIG_UNKNOWN_ERROR, 153971af9d46SMeenakshikumar Somasundaram }; 154071af9d46SMeenakshikumar Somasundaram 154171af9d46SMeenakshikumar Somasundaram /** 154271af9d46SMeenakshikumar Somasundaram * Definition of a set_config reply 154371af9d46SMeenakshikumar Somasundaram */ 154471af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data { 154571af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA Instance */ 154671af9d46SMeenakshikumar Somasundaram uint8_t status; /* Set Config reply */ 154771af9d46SMeenakshikumar Somasundaram uint16_t pad; /* Alignment */ 154871af9d46SMeenakshikumar Somasundaram }; 154971af9d46SMeenakshikumar Somasundaram 155071af9d46SMeenakshikumar Somasundaram /** 155171af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 155271af9d46SMeenakshikumar Somasundaram */ 155371af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply { 155471af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; 155571af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data set_config_reply_control; 155671af9d46SMeenakshikumar Somasundaram }; 155771af9d46SMeenakshikumar Somasundaram 1558ea5a4db9SAnthony Koo /** 1559ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1560ea5a4db9SAnthony Koo */ 1561ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data { 1562ea5a4db9SAnthony Koo uint8_t instance; /**< HPD instance or DPIA instance */ 1563ea5a4db9SAnthony Koo uint8_t result; /**< For returning HPD state */ 1564874714feSAnthony Koo uint16_t pad; /** < Alignment */ 1565ea5a4db9SAnthony Koo enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1566ea5a4db9SAnthony Koo enum aux_return_code_type status; /**< for returning the status of command */ 1567ea5a4db9SAnthony Koo }; 1568ea5a4db9SAnthony Koo 1569ea5a4db9SAnthony Koo /** 1570ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1571ea5a4db9SAnthony Koo */ 1572ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state { 1573ea5a4db9SAnthony Koo /** 1574ea5a4db9SAnthony Koo * Command header. 1575ea5a4db9SAnthony Koo */ 1576ea5a4db9SAnthony Koo struct dmub_cmd_header header; 1577ea5a4db9SAnthony Koo /** 1578ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1579ea5a4db9SAnthony Koo */ 1580ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data data; 1581ea5a4db9SAnthony Koo }; 1582ea5a4db9SAnthony Koo 158384034ad4SAnthony Koo /* 158484034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 158584034ad4SAnthony Koo * Do not reuse or modify IDs. 158684034ad4SAnthony Koo */ 158784034ad4SAnthony Koo 15881a595f28SAnthony Koo /** 15891a595f28SAnthony Koo * PSR command sub-types. 15901a595f28SAnthony Koo */ 159184034ad4SAnthony Koo enum dmub_cmd_psr_type { 15921a595f28SAnthony Koo /** 15931a595f28SAnthony Koo * Set PSR version support. 15941a595f28SAnthony Koo */ 159584034ad4SAnthony Koo DMUB_CMD__PSR_SET_VERSION = 0, 15961a595f28SAnthony Koo /** 15971a595f28SAnthony Koo * Copy driver-calculated parameters to PSR state. 15981a595f28SAnthony Koo */ 159984034ad4SAnthony Koo DMUB_CMD__PSR_COPY_SETTINGS = 1, 16001a595f28SAnthony Koo /** 16011a595f28SAnthony Koo * Enable PSR. 16021a595f28SAnthony Koo */ 160384034ad4SAnthony Koo DMUB_CMD__PSR_ENABLE = 2, 16041a595f28SAnthony Koo 16051a595f28SAnthony Koo /** 16061a595f28SAnthony Koo * Disable PSR. 16071a595f28SAnthony Koo */ 160884034ad4SAnthony Koo DMUB_CMD__PSR_DISABLE = 3, 16091a595f28SAnthony Koo 16101a595f28SAnthony Koo /** 16111a595f28SAnthony Koo * Set PSR level. 16121a595f28SAnthony Koo * PSR level is a 16-bit value dicated by driver that 16131a595f28SAnthony Koo * will enable/disable different functionality. 16141a595f28SAnthony Koo */ 161584034ad4SAnthony Koo DMUB_CMD__PSR_SET_LEVEL = 4, 16161a595f28SAnthony Koo 16171a595f28SAnthony Koo /** 16181a595f28SAnthony Koo * Forces PSR enabled until an explicit PSR disable call. 16191a595f28SAnthony Koo */ 1620672251b2SAnthony Koo DMUB_CMD__PSR_FORCE_STATIC = 5, 1621e5dfcd27SRobin Chen /** 162283eb5385SDavid Zhang * Set vtotal in psr active for FreeSync PSR. 162383eb5385SDavid Zhang */ 162483eb5385SDavid Zhang DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 162583eb5385SDavid Zhang /** 1626e5dfcd27SRobin Chen * Set PSR power option 1627e5dfcd27SRobin Chen */ 1628e5dfcd27SRobin Chen DMUB_CMD__SET_PSR_POWER_OPT = 7, 162984034ad4SAnthony Koo }; 163084034ad4SAnthony Koo 163185f4bc0cSAlvin Lee enum dmub_cmd_fams_type { 163285f4bc0cSAlvin Lee DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 163385f4bc0cSAlvin Lee DMUB_CMD__FAMS_DRR_UPDATE = 1, 163485f4bc0cSAlvin Lee DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 163581f776b6SAnthony Koo /** 163681f776b6SAnthony Koo * For SubVP set manual trigger in FW because it 163781f776b6SAnthony Koo * triggers DRR_UPDATE_PENDING which SubVP relies 163881f776b6SAnthony Koo * on (for any SubVP cases that use a DRR display) 163981f776b6SAnthony Koo */ 164081f776b6SAnthony Koo DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 164185f4bc0cSAlvin Lee }; 164285f4bc0cSAlvin Lee 16431a595f28SAnthony Koo /** 16441a595f28SAnthony Koo * PSR versions. 16451a595f28SAnthony Koo */ 164684034ad4SAnthony Koo enum psr_version { 16471a595f28SAnthony Koo /** 16481a595f28SAnthony Koo * PSR version 1. 16491a595f28SAnthony Koo */ 165084034ad4SAnthony Koo PSR_VERSION_1 = 0, 16511a595f28SAnthony Koo /** 165283eb5385SDavid Zhang * Freesync PSR SU. 165383eb5385SDavid Zhang */ 165483eb5385SDavid Zhang PSR_VERSION_SU_1 = 1, 165583eb5385SDavid Zhang /** 16561a595f28SAnthony Koo * PSR not supported. 16571a595f28SAnthony Koo */ 165884034ad4SAnthony Koo PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 165984034ad4SAnthony Koo }; 166084034ad4SAnthony Koo 1661592a6318SAnthony Koo /** 1662592a6318SAnthony Koo * enum dmub_cmd_mall_type - MALL commands 1663592a6318SAnthony Koo */ 166452f2e83eSBhawanpreet Lakha enum dmub_cmd_mall_type { 1665592a6318SAnthony Koo /** 1666592a6318SAnthony Koo * Allows display refresh from MALL. 1667592a6318SAnthony Koo */ 166852f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_ALLOW = 0, 1669592a6318SAnthony Koo /** 1670592a6318SAnthony Koo * Disallows display refresh from MALL. 1671592a6318SAnthony Koo */ 167252f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1673592a6318SAnthony Koo /** 1674592a6318SAnthony Koo * Cursor copy for MALL. 1675592a6318SAnthony Koo */ 167652f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1677592a6318SAnthony Koo /** 1678592a6318SAnthony Koo * Controls DF requests. 1679592a6318SAnthony Koo */ 1680ea7154d8SBhawanpreet Lakha DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 168152f2e83eSBhawanpreet Lakha }; 168252f2e83eSBhawanpreet Lakha 1683a91b402dSCharlene Liu /** 168478174f47SAnthony Koo * PHY Link rate for DP. 168578174f47SAnthony Koo */ 168678174f47SAnthony Koo enum phy_link_rate { 168778174f47SAnthony Koo /** 168878174f47SAnthony Koo * not supported. 168978174f47SAnthony Koo */ 169078174f47SAnthony Koo PHY_RATE_UNKNOWN = 0, 169178174f47SAnthony Koo /** 169278174f47SAnthony Koo * Rate_1 (RBR) - 1.62 Gbps/Lane 169378174f47SAnthony Koo */ 169478174f47SAnthony Koo PHY_RATE_162 = 1, 169578174f47SAnthony Koo /** 169678174f47SAnthony Koo * Rate_2 - 2.16 Gbps/Lane 169778174f47SAnthony Koo */ 169878174f47SAnthony Koo PHY_RATE_216 = 2, 169978174f47SAnthony Koo /** 170078174f47SAnthony Koo * Rate_3 - 2.43 Gbps/Lane 170178174f47SAnthony Koo */ 170278174f47SAnthony Koo PHY_RATE_243 = 3, 170378174f47SAnthony Koo /** 170478174f47SAnthony Koo * Rate_4 (HBR) - 2.70 Gbps/Lane 170578174f47SAnthony Koo */ 170678174f47SAnthony Koo PHY_RATE_270 = 4, 170778174f47SAnthony Koo /** 170878174f47SAnthony Koo * Rate_5 (RBR2)- 3.24 Gbps/Lane 170978174f47SAnthony Koo */ 171078174f47SAnthony Koo PHY_RATE_324 = 5, 171178174f47SAnthony Koo /** 171278174f47SAnthony Koo * Rate_6 - 4.32 Gbps/Lane 171378174f47SAnthony Koo */ 171478174f47SAnthony Koo PHY_RATE_432 = 6, 171578174f47SAnthony Koo /** 171678174f47SAnthony Koo * Rate_7 (HBR2)- 5.40 Gbps/Lane 171778174f47SAnthony Koo */ 171878174f47SAnthony Koo PHY_RATE_540 = 7, 171978174f47SAnthony Koo /** 172078174f47SAnthony Koo * Rate_8 (HBR3)- 8.10 Gbps/Lane 172178174f47SAnthony Koo */ 172278174f47SAnthony Koo PHY_RATE_810 = 8, 172378174f47SAnthony Koo /** 172478174f47SAnthony Koo * UHBR10 - 10.0 Gbps/Lane 172578174f47SAnthony Koo */ 172678174f47SAnthony Koo PHY_RATE_1000 = 9, 172778174f47SAnthony Koo /** 172878174f47SAnthony Koo * UHBR13.5 - 13.5 Gbps/Lane 172978174f47SAnthony Koo */ 173078174f47SAnthony Koo PHY_RATE_1350 = 10, 173178174f47SAnthony Koo /** 173278174f47SAnthony Koo * UHBR10 - 20.0 Gbps/Lane 173378174f47SAnthony Koo */ 173478174f47SAnthony Koo PHY_RATE_2000 = 11, 173578174f47SAnthony Koo }; 173678174f47SAnthony Koo 173778174f47SAnthony Koo /** 173878174f47SAnthony Koo * enum dmub_phy_fsm_state - PHY FSM states. 173978174f47SAnthony Koo * PHY FSM state to transit to during PSR enable/disable. 174078174f47SAnthony Koo */ 174178174f47SAnthony Koo enum dmub_phy_fsm_state { 174278174f47SAnthony Koo DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 174378174f47SAnthony Koo DMUB_PHY_FSM_RESET, 174478174f47SAnthony Koo DMUB_PHY_FSM_RESET_RELEASED, 174578174f47SAnthony Koo DMUB_PHY_FSM_SRAM_LOAD_DONE, 174678174f47SAnthony Koo DMUB_PHY_FSM_INITIALIZED, 174778174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED, 174878174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_LP, 174978174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_PG, 175078174f47SAnthony Koo DMUB_PHY_FSM_POWER_DOWN, 175178174f47SAnthony Koo DMUB_PHY_FSM_PLL_EN, 175278174f47SAnthony Koo DMUB_PHY_FSM_TX_EN, 175378174f47SAnthony Koo DMUB_PHY_FSM_FAST_LP, 175478174f47SAnthony Koo }; 175578174f47SAnthony Koo 175678174f47SAnthony Koo /** 17571a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 17581a595f28SAnthony Koo */ 17597c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data { 17601a595f28SAnthony Koo /** 17611a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 17621a595f28SAnthony Koo */ 17637b8a6362SAnthony Koo union dmub_psr_debug_flags debug; 17641a595f28SAnthony Koo /** 17651a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 17661a595f28SAnthony Koo */ 17674c1a1335SWyatt Wood uint16_t psr_level; 17681a595f28SAnthony Koo /** 17691a595f28SAnthony Koo * DPP HW instance. 17701a595f28SAnthony Koo */ 17714c1a1335SWyatt Wood uint8_t dpp_inst; 17721a595f28SAnthony Koo /** 17731a595f28SAnthony Koo * MPCC HW instance. 17741a595f28SAnthony Koo * Not used in dmub fw, 177534ba432cSAnthony Koo * dmub fw will get active opp by reading odm registers. 177634ba432cSAnthony Koo */ 17774c1a1335SWyatt Wood uint8_t mpcc_inst; 17781a595f28SAnthony Koo /** 17791a595f28SAnthony Koo * OPP HW instance. 17801a595f28SAnthony Koo * Not used in dmub fw, 17811a595f28SAnthony Koo * dmub fw will get active opp by reading odm registers. 17821a595f28SAnthony Koo */ 17834c1a1335SWyatt Wood uint8_t opp_inst; 17841a595f28SAnthony Koo /** 17851a595f28SAnthony Koo * OTG HW instance. 17861a595f28SAnthony Koo */ 17874c1a1335SWyatt Wood uint8_t otg_inst; 17881a595f28SAnthony Koo /** 17891a595f28SAnthony Koo * DIG FE HW instance. 17901a595f28SAnthony Koo */ 17914c1a1335SWyatt Wood uint8_t digfe_inst; 17921a595f28SAnthony Koo /** 17931a595f28SAnthony Koo * DIG BE HW instance. 17941a595f28SAnthony Koo */ 17954c1a1335SWyatt Wood uint8_t digbe_inst; 17961a595f28SAnthony Koo /** 17971a595f28SAnthony Koo * DP PHY HW instance. 17981a595f28SAnthony Koo */ 17994c1a1335SWyatt Wood uint8_t dpphy_inst; 18001a595f28SAnthony Koo /** 18011a595f28SAnthony Koo * AUX HW instance. 18021a595f28SAnthony Koo */ 18034c1a1335SWyatt Wood uint8_t aux_inst; 18041a595f28SAnthony Koo /** 18051a595f28SAnthony Koo * Determines if SMU optimzations are enabled/disabled. 18061a595f28SAnthony Koo */ 18074c1a1335SWyatt Wood uint8_t smu_optimizations_en; 18081a595f28SAnthony Koo /** 18091a595f28SAnthony Koo * Unused. 18101a595f28SAnthony Koo * TODO: Remove. 18111a595f28SAnthony Koo */ 18124c1a1335SWyatt Wood uint8_t frame_delay; 18131a595f28SAnthony Koo /** 18141a595f28SAnthony Koo * If RFB setup time is greater than the total VBLANK time, 18151a595f28SAnthony Koo * it is not possible for the sink to capture the video frame 18161a595f28SAnthony Koo * in the same frame the SDP is sent. In this case, 18171a595f28SAnthony Koo * the frame capture indication bit should be set and an extra 18181a595f28SAnthony Koo * static frame should be transmitted to the sink. 18191a595f28SAnthony Koo */ 18204c1a1335SWyatt Wood uint8_t frame_cap_ind; 18211a595f28SAnthony Koo /** 182283eb5385SDavid Zhang * Granularity of Y offset supported by sink. 18231a595f28SAnthony Koo */ 182483eb5385SDavid Zhang uint8_t su_y_granularity; 182583eb5385SDavid Zhang /** 182683eb5385SDavid Zhang * Indicates whether sink should start capturing 182783eb5385SDavid Zhang * immediately following active scan line, 182883eb5385SDavid Zhang * or starting with the 2nd active scan line. 182983eb5385SDavid Zhang */ 183083eb5385SDavid Zhang uint8_t line_capture_indication; 18311a595f28SAnthony Koo /** 18321a595f28SAnthony Koo * Multi-display optimizations are implemented on certain ASICs. 18331a595f28SAnthony Koo */ 1834175f0971SYongqiang Sun uint8_t multi_disp_optimizations_en; 18351a595f28SAnthony Koo /** 18361a595f28SAnthony Koo * The last possible line SDP may be transmitted without violating 18371a595f28SAnthony Koo * the RFB setup time or entering the active video frame. 18381a595f28SAnthony Koo */ 183978ead771SAnthony Koo uint16_t init_sdp_deadline; 18401a595f28SAnthony Koo /** 184183eb5385SDavid Zhang * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 18421a595f28SAnthony Koo */ 184383eb5385SDavid Zhang uint8_t rate_control_caps ; 184483eb5385SDavid Zhang /* 184583eb5385SDavid Zhang * Force PSRSU always doing full frame update 184683eb5385SDavid Zhang */ 184783eb5385SDavid Zhang uint8_t force_ffu_mode; 18481a595f28SAnthony Koo /** 18491a595f28SAnthony Koo * Length of each horizontal line in us. 18501a595f28SAnthony Koo */ 18519b56f6bcSAnthony Koo uint32_t line_time_in_us; 1852ecc11601SAnthony Koo /** 1853ecc11601SAnthony Koo * FEC enable status in driver 1854ecc11601SAnthony Koo */ 1855ecc11601SAnthony Koo uint8_t fec_enable_status; 1856ecc11601SAnthony Koo /** 1857ecc11601SAnthony Koo * FEC re-enable delay when PSR exit. 1858ecc11601SAnthony Koo * unit is 100us, range form 0~255(0xFF). 1859ecc11601SAnthony Koo */ 1860ecc11601SAnthony Koo uint8_t fec_enable_delay_in100us; 1861ecc11601SAnthony Koo /** 1862f56c837aSMikita Lipski * PSR control version. 1863ecc11601SAnthony Koo */ 1864f56c837aSMikita Lipski uint8_t cmd_version; 1865f56c837aSMikita Lipski /** 1866f56c837aSMikita Lipski * Panel Instance. 1867f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1868f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1869f56c837aSMikita Lipski */ 1870f56c837aSMikita Lipski uint8_t panel_inst; 18712665f63aSMikita Lipski /* 18722665f63aSMikita Lipski * DSC enable status in driver 1873360d1b65SIan Chen */ 18742665f63aSMikita Lipski uint8_t dsc_enable_status; 1875b5175966SShah Dharati /* 1876b5175966SShah Dharati * Use FSM state for PSR power up/down 18772665f63aSMikita Lipski */ 1878b5175966SShah Dharati uint8_t use_phy_fsm; 1879b5175966SShah Dharati /** 1880b5175966SShah Dharati * Explicit padding to 2 byte boundary. 1881b5175966SShah Dharati */ 1882b5175966SShah Dharati uint8_t pad3[2]; 18837c008829SNicholas Kazlauskas }; 18847c008829SNicholas Kazlauskas 18851a595f28SAnthony Koo /** 18861a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 18871a595f28SAnthony Koo */ 18887c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings { 18891a595f28SAnthony Koo /** 18901a595f28SAnthony Koo * Command header. 18911a595f28SAnthony Koo */ 18927c008829SNicholas Kazlauskas struct dmub_cmd_header header; 18931a595f28SAnthony Koo /** 18941a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 18951a595f28SAnthony Koo */ 18967c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 18977c008829SNicholas Kazlauskas }; 18987c008829SNicholas Kazlauskas 18991a595f28SAnthony Koo /** 19001a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 19011a595f28SAnthony Koo */ 19027c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data { 19031a595f28SAnthony Koo /** 19041a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 19051a595f28SAnthony Koo */ 19067c008829SNicholas Kazlauskas uint16_t psr_level; 19071a595f28SAnthony Koo /** 1908f56c837aSMikita Lipski * PSR control version. 19091a595f28SAnthony Koo */ 1910f56c837aSMikita Lipski uint8_t cmd_version; 1911f56c837aSMikita Lipski /** 1912f56c837aSMikita Lipski * Panel Instance. 1913f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1914f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1915f56c837aSMikita Lipski */ 1916f56c837aSMikita Lipski uint8_t panel_inst; 19177c008829SNicholas Kazlauskas }; 19187c008829SNicholas Kazlauskas 19191a595f28SAnthony Koo /** 19201a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 19211a595f28SAnthony Koo */ 19227c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level { 19231a595f28SAnthony Koo /** 19241a595f28SAnthony Koo * Command header. 19251a595f28SAnthony Koo */ 19267c008829SNicholas Kazlauskas struct dmub_cmd_header header; 19271a595f28SAnthony Koo /** 19281a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 19291a595f28SAnthony Koo */ 19307c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data psr_set_level_data; 19317c008829SNicholas Kazlauskas }; 19327c008829SNicholas Kazlauskas 1933f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data { 1934f56c837aSMikita Lipski /** 1935f56c837aSMikita Lipski * PSR control version. 1936f56c837aSMikita Lipski */ 1937f56c837aSMikita Lipski uint8_t cmd_version; 1938f56c837aSMikita Lipski /** 1939f56c837aSMikita Lipski * Panel Instance. 1940f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1941f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1942f56c837aSMikita Lipski */ 1943f56c837aSMikita Lipski uint8_t panel_inst; 1944f56c837aSMikita Lipski /** 194578174f47SAnthony Koo * Phy state to enter. 194678174f47SAnthony Koo * Values to use are defined in dmub_phy_fsm_state 1947f56c837aSMikita Lipski */ 194878174f47SAnthony Koo uint8_t phy_fsm_state; 194978174f47SAnthony Koo /** 195078174f47SAnthony Koo * Phy rate for DP - RBR/HBR/HBR2/HBR3. 195178174f47SAnthony Koo * Set this using enum phy_link_rate. 195278174f47SAnthony Koo * This does not support HDMI/DP2 for now. 195378174f47SAnthony Koo */ 195478174f47SAnthony Koo uint8_t phy_rate; 1955f56c837aSMikita Lipski }; 1956f56c837aSMikita Lipski 19571a595f28SAnthony Koo /** 19581a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 19591a595f28SAnthony Koo * PSR enable/disable is controlled using the sub_type. 19601a595f28SAnthony Koo */ 19617c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_enable { 19621a595f28SAnthony Koo /** 19631a595f28SAnthony Koo * Command header. 19641a595f28SAnthony Koo */ 19657c008829SNicholas Kazlauskas struct dmub_cmd_header header; 1966f56c837aSMikita Lipski 1967f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data data; 19687c008829SNicholas Kazlauskas }; 19697c008829SNicholas Kazlauskas 19701a595f28SAnthony Koo /** 19711a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 19721a595f28SAnthony Koo */ 1973d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data { 19741a595f28SAnthony Koo /** 19751a595f28SAnthony Koo * PSR version that FW should implement. 19761a595f28SAnthony Koo */ 19771a595f28SAnthony Koo enum psr_version version; 1978f56c837aSMikita Lipski /** 1979f56c837aSMikita Lipski * PSR control version. 1980f56c837aSMikita Lipski */ 1981f56c837aSMikita Lipski uint8_t cmd_version; 1982f56c837aSMikita Lipski /** 1983f56c837aSMikita Lipski * Panel Instance. 1984f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1985f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1986f56c837aSMikita Lipski */ 1987f56c837aSMikita Lipski uint8_t panel_inst; 1988f56c837aSMikita Lipski /** 1989f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 1990f56c837aSMikita Lipski */ 1991f56c837aSMikita Lipski uint8_t pad[2]; 19927c008829SNicholas Kazlauskas }; 19937c008829SNicholas Kazlauskas 19941a595f28SAnthony Koo /** 19951a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 19961a595f28SAnthony Koo */ 1997d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version { 19981a595f28SAnthony Koo /** 19991a595f28SAnthony Koo * Command header. 20001a595f28SAnthony Koo */ 20017c008829SNicholas Kazlauskas struct dmub_cmd_header header; 20021a595f28SAnthony Koo /** 20031a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 20041a595f28SAnthony Koo */ 2005d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data psr_set_version_data; 20067c008829SNicholas Kazlauskas }; 20077c008829SNicholas Kazlauskas 2008f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data { 2009f56c837aSMikita Lipski /** 2010f56c837aSMikita Lipski * PSR control version. 2011f56c837aSMikita Lipski */ 2012f56c837aSMikita Lipski uint8_t cmd_version; 2013f56c837aSMikita Lipski /** 2014f56c837aSMikita Lipski * Panel Instance. 2015f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 2016f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2017f56c837aSMikita Lipski */ 2018f56c837aSMikita Lipski uint8_t panel_inst; 2019f56c837aSMikita Lipski /** 2020ad371c8aSAnthony Koo * Explicit padding to 4 byte boundary. 2021f56c837aSMikita Lipski */ 2022ad371c8aSAnthony Koo uint8_t pad[2]; 2023f56c837aSMikita Lipski }; 2024f56c837aSMikita Lipski 20251a595f28SAnthony Koo /** 20261a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 20271a595f28SAnthony Koo */ 2028672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static { 20291a595f28SAnthony Koo /** 20301a595f28SAnthony Koo * Command header. 20311a595f28SAnthony Koo */ 2032672251b2SAnthony Koo struct dmub_cmd_header header; 2033f56c837aSMikita Lipski /** 2034f56c837aSMikita Lipski * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2035f56c837aSMikita Lipski */ 2036f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data psr_force_static_data; 2037672251b2SAnthony Koo }; 2038672251b2SAnthony Koo 20391a595f28SAnthony Koo /** 204083eb5385SDavid Zhang * PSR SU debug flags. 204183eb5385SDavid Zhang */ 204283eb5385SDavid Zhang union dmub_psr_su_debug_flags { 204383eb5385SDavid Zhang /** 204483eb5385SDavid Zhang * PSR SU debug flags. 204583eb5385SDavid Zhang */ 204683eb5385SDavid Zhang struct { 204783eb5385SDavid Zhang /** 204883eb5385SDavid Zhang * Update dirty rect in SW only. 204983eb5385SDavid Zhang */ 205083eb5385SDavid Zhang uint8_t update_dirty_rect_only : 1; 205183eb5385SDavid Zhang /** 205283eb5385SDavid Zhang * Reset the cursor/plane state before processing the call. 205383eb5385SDavid Zhang */ 205483eb5385SDavid Zhang uint8_t reset_state : 1; 205583eb5385SDavid Zhang } bitfields; 205683eb5385SDavid Zhang 205783eb5385SDavid Zhang /** 205883eb5385SDavid Zhang * Union for debug flags. 205983eb5385SDavid Zhang */ 206083eb5385SDavid Zhang uint32_t u32All; 206183eb5385SDavid Zhang }; 206283eb5385SDavid Zhang 206383eb5385SDavid Zhang /** 206483eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 206583eb5385SDavid Zhang * This triggers a selective update for PSR SU. 206683eb5385SDavid Zhang */ 206783eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data { 206883eb5385SDavid Zhang /** 206983eb5385SDavid Zhang * Dirty rects from OS. 207083eb5385SDavid Zhang */ 207183eb5385SDavid Zhang struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 207283eb5385SDavid Zhang /** 207383eb5385SDavid Zhang * PSR SU debug flags. 207483eb5385SDavid Zhang */ 207583eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags; 207683eb5385SDavid Zhang /** 207783eb5385SDavid Zhang * OTG HW instance. 207883eb5385SDavid Zhang */ 207983eb5385SDavid Zhang uint8_t pipe_idx; 208083eb5385SDavid Zhang /** 208183eb5385SDavid Zhang * Number of dirty rects. 208283eb5385SDavid Zhang */ 208383eb5385SDavid Zhang uint8_t dirty_rect_count; 208483eb5385SDavid Zhang /** 208583eb5385SDavid Zhang * PSR control version. 208683eb5385SDavid Zhang */ 208783eb5385SDavid Zhang uint8_t cmd_version; 208883eb5385SDavid Zhang /** 208983eb5385SDavid Zhang * Panel Instance. 209083eb5385SDavid Zhang * Panel isntance to identify which psr_state to use 209183eb5385SDavid Zhang * Currently the support is only for 0 or 1 209283eb5385SDavid Zhang */ 209383eb5385SDavid Zhang uint8_t panel_inst; 209483eb5385SDavid Zhang }; 209583eb5385SDavid Zhang 209683eb5385SDavid Zhang /** 209783eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 209883eb5385SDavid Zhang */ 209983eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect { 210083eb5385SDavid Zhang /** 210183eb5385SDavid Zhang * Command header. 210283eb5385SDavid Zhang */ 210383eb5385SDavid Zhang struct dmub_cmd_header header; 210483eb5385SDavid Zhang /** 210583eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 210683eb5385SDavid Zhang */ 210783eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 210883eb5385SDavid Zhang }; 210983eb5385SDavid Zhang 211083eb5385SDavid Zhang /** 211183eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 211283eb5385SDavid Zhang */ 2113b73353f7SMax Tseng union dmub_reg_cursor_control_cfg { 2114b73353f7SMax Tseng struct { 2115b73353f7SMax Tseng uint32_t cur_enable: 1; 2116b73353f7SMax Tseng uint32_t reser0: 3; 2117b73353f7SMax Tseng uint32_t cur_2x_magnify: 1; 2118b73353f7SMax Tseng uint32_t reser1: 3; 2119b73353f7SMax Tseng uint32_t mode: 3; 2120b73353f7SMax Tseng uint32_t reser2: 5; 2121b73353f7SMax Tseng uint32_t pitch: 2; 2122b73353f7SMax Tseng uint32_t reser3: 6; 2123b73353f7SMax Tseng uint32_t line_per_chunk: 5; 2124b73353f7SMax Tseng uint32_t reser4: 3; 2125b73353f7SMax Tseng } bits; 2126b73353f7SMax Tseng uint32_t raw; 2127b73353f7SMax Tseng }; 2128b73353f7SMax Tseng struct dmub_cursor_position_cache_hubp { 2129b73353f7SMax Tseng union dmub_reg_cursor_control_cfg cur_ctl; 2130b73353f7SMax Tseng union dmub_reg_position_cfg { 2131b73353f7SMax Tseng struct { 2132b73353f7SMax Tseng uint32_t cur_x_pos: 16; 2133b73353f7SMax Tseng uint32_t cur_y_pos: 16; 2134b73353f7SMax Tseng } bits; 2135b73353f7SMax Tseng uint32_t raw; 2136b73353f7SMax Tseng } position; 2137b73353f7SMax Tseng union dmub_reg_hot_spot_cfg { 2138b73353f7SMax Tseng struct { 2139b73353f7SMax Tseng uint32_t hot_x: 16; 2140b73353f7SMax Tseng uint32_t hot_y: 16; 2141b73353f7SMax Tseng } bits; 2142b73353f7SMax Tseng uint32_t raw; 2143b73353f7SMax Tseng } hot_spot; 2144b73353f7SMax Tseng union dmub_reg_dst_offset_cfg { 2145b73353f7SMax Tseng struct { 2146b73353f7SMax Tseng uint32_t dst_x_offset: 13; 2147b73353f7SMax Tseng uint32_t reserved: 19; 2148b73353f7SMax Tseng } bits; 2149b73353f7SMax Tseng uint32_t raw; 2150b73353f7SMax Tseng } dst_offset; 2151b73353f7SMax Tseng }; 2152b73353f7SMax Tseng 2153b73353f7SMax Tseng union dmub_reg_cur0_control_cfg { 2154b73353f7SMax Tseng struct { 2155b73353f7SMax Tseng uint32_t cur0_enable: 1; 2156b73353f7SMax Tseng uint32_t expansion_mode: 1; 2157b73353f7SMax Tseng uint32_t reser0: 1; 2158b73353f7SMax Tseng uint32_t cur0_rom_en: 1; 2159b73353f7SMax Tseng uint32_t mode: 3; 2160b73353f7SMax Tseng uint32_t reserved: 25; 2161b73353f7SMax Tseng } bits; 2162b73353f7SMax Tseng uint32_t raw; 2163b73353f7SMax Tseng }; 2164b73353f7SMax Tseng struct dmub_cursor_position_cache_dpp { 2165b73353f7SMax Tseng union dmub_reg_cur0_control_cfg cur0_ctl; 2166b73353f7SMax Tseng }; 2167b73353f7SMax Tseng struct dmub_cursor_position_cfg { 2168b73353f7SMax Tseng struct dmub_cursor_position_cache_hubp pHubp; 2169b73353f7SMax Tseng struct dmub_cursor_position_cache_dpp pDpp; 2170b73353f7SMax Tseng uint8_t pipe_idx; 2171b73353f7SMax Tseng /* 2172b73353f7SMax Tseng * Padding is required. To be 4 Bytes Aligned. 2173b73353f7SMax Tseng */ 2174b73353f7SMax Tseng uint8_t padding[3]; 2175b73353f7SMax Tseng }; 2176b73353f7SMax Tseng 2177b73353f7SMax Tseng struct dmub_cursor_attribute_cache_hubp { 2178b73353f7SMax Tseng uint32_t SURFACE_ADDR_HIGH; 2179b73353f7SMax Tseng uint32_t SURFACE_ADDR; 2180b73353f7SMax Tseng union dmub_reg_cursor_control_cfg cur_ctl; 2181b73353f7SMax Tseng union dmub_reg_cursor_size_cfg { 2182b73353f7SMax Tseng struct { 2183b73353f7SMax Tseng uint32_t width: 16; 2184b73353f7SMax Tseng uint32_t height: 16; 2185b73353f7SMax Tseng } bits; 2186b73353f7SMax Tseng uint32_t raw; 2187b73353f7SMax Tseng } size; 2188b73353f7SMax Tseng union dmub_reg_cursor_settings_cfg { 2189b73353f7SMax Tseng struct { 2190b73353f7SMax Tseng uint32_t dst_y_offset: 8; 2191b73353f7SMax Tseng uint32_t chunk_hdl_adjust: 2; 2192b73353f7SMax Tseng uint32_t reserved: 22; 2193b73353f7SMax Tseng } bits; 2194b73353f7SMax Tseng uint32_t raw; 2195b73353f7SMax Tseng } settings; 2196b73353f7SMax Tseng }; 2197b73353f7SMax Tseng struct dmub_cursor_attribute_cache_dpp { 2198b73353f7SMax Tseng union dmub_reg_cur0_control_cfg cur0_ctl; 2199b73353f7SMax Tseng }; 2200b73353f7SMax Tseng struct dmub_cursor_attributes_cfg { 2201b73353f7SMax Tseng struct dmub_cursor_attribute_cache_hubp aHubp; 2202b73353f7SMax Tseng struct dmub_cursor_attribute_cache_dpp aDpp; 2203b73353f7SMax Tseng }; 2204b73353f7SMax Tseng 2205b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 { 220683eb5385SDavid Zhang /** 220783eb5385SDavid Zhang * Cursor dirty rects. 220883eb5385SDavid Zhang */ 220983eb5385SDavid Zhang struct dmub_rect cursor_rect; 221083eb5385SDavid Zhang /** 221183eb5385SDavid Zhang * PSR SU debug flags. 221283eb5385SDavid Zhang */ 221383eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags; 221483eb5385SDavid Zhang /** 221583eb5385SDavid Zhang * Cursor enable/disable. 221683eb5385SDavid Zhang */ 221783eb5385SDavid Zhang uint8_t enable; 221883eb5385SDavid Zhang /** 221983eb5385SDavid Zhang * OTG HW instance. 222083eb5385SDavid Zhang */ 222183eb5385SDavid Zhang uint8_t pipe_idx; 222283eb5385SDavid Zhang /** 222383eb5385SDavid Zhang * PSR control version. 222483eb5385SDavid Zhang */ 222583eb5385SDavid Zhang uint8_t cmd_version; 222683eb5385SDavid Zhang /** 222783eb5385SDavid Zhang * Panel Instance. 222883eb5385SDavid Zhang * Panel isntance to identify which psr_state to use 222983eb5385SDavid Zhang * Currently the support is only for 0 or 1 223083eb5385SDavid Zhang */ 223183eb5385SDavid Zhang uint8_t panel_inst; 2232b73353f7SMax Tseng /** 2233b73353f7SMax Tseng * Cursor Position Register. 2234b73353f7SMax Tseng * Registers contains Hubp & Dpp modules 2235b73353f7SMax Tseng */ 2236b73353f7SMax Tseng struct dmub_cursor_position_cfg position_cfg; 2237b73353f7SMax Tseng }; 2238b73353f7SMax Tseng 2239b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload1 { 2240b73353f7SMax Tseng struct dmub_cursor_attributes_cfg attribute_cfg; 2241b73353f7SMax Tseng }; 2242b73353f7SMax Tseng 2243b73353f7SMax Tseng union dmub_cmd_update_cursor_info_data { 2244b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 payload0; 2245b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload1 payload1; 224683eb5385SDavid Zhang }; 224783eb5385SDavid Zhang /** 224883eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 224983eb5385SDavid Zhang */ 225083eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info { 225183eb5385SDavid Zhang /** 225283eb5385SDavid Zhang * Command header. 225383eb5385SDavid Zhang */ 225483eb5385SDavid Zhang struct dmub_cmd_header header; 225583eb5385SDavid Zhang /** 225683eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 225783eb5385SDavid Zhang */ 2258b73353f7SMax Tseng union dmub_cmd_update_cursor_info_data update_cursor_info_data; 225983eb5385SDavid Zhang }; 226083eb5385SDavid Zhang 226183eb5385SDavid Zhang /** 226283eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 226383eb5385SDavid Zhang */ 226483eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data { 226583eb5385SDavid Zhang /** 226683eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 226783eb5385SDavid Zhang */ 226883eb5385SDavid Zhang uint16_t psr_vtotal_idle; 226983eb5385SDavid Zhang /** 227083eb5385SDavid Zhang * PSR control version. 227183eb5385SDavid Zhang */ 227283eb5385SDavid Zhang uint8_t cmd_version; 227383eb5385SDavid Zhang /** 227483eb5385SDavid Zhang * Panel Instance. 227583eb5385SDavid Zhang * Panel isntance to identify which psr_state to use 227683eb5385SDavid Zhang * Currently the support is only for 0 or 1 227783eb5385SDavid Zhang */ 227883eb5385SDavid Zhang uint8_t panel_inst; 227983eb5385SDavid Zhang /* 228083eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 228183eb5385SDavid Zhang */ 228283eb5385SDavid Zhang uint16_t psr_vtotal_su; 228383eb5385SDavid Zhang /** 228483eb5385SDavid Zhang * Explicit padding to 4 byte boundary. 228583eb5385SDavid Zhang */ 228683eb5385SDavid Zhang uint8_t pad2[2]; 228783eb5385SDavid Zhang }; 228883eb5385SDavid Zhang 228983eb5385SDavid Zhang /** 229083eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 229183eb5385SDavid Zhang */ 229283eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal { 229383eb5385SDavid Zhang /** 229483eb5385SDavid Zhang * Command header. 229583eb5385SDavid Zhang */ 229683eb5385SDavid Zhang struct dmub_cmd_header header; 229783eb5385SDavid Zhang /** 229883eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 229983eb5385SDavid Zhang */ 230083eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 230183eb5385SDavid Zhang }; 230283eb5385SDavid Zhang 230383eb5385SDavid Zhang /** 2304e5dfcd27SRobin Chen * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2305e5dfcd27SRobin Chen */ 2306e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data { 2307e5dfcd27SRobin Chen /** 2308e5dfcd27SRobin Chen * PSR control version. 2309e5dfcd27SRobin Chen */ 2310e5dfcd27SRobin Chen uint8_t cmd_version; 2311e5dfcd27SRobin Chen /** 2312e5dfcd27SRobin Chen * Panel Instance. 2313e5dfcd27SRobin Chen * Panel isntance to identify which psr_state to use 2314e5dfcd27SRobin Chen * Currently the support is only for 0 or 1 2315e5dfcd27SRobin Chen */ 2316e5dfcd27SRobin Chen uint8_t panel_inst; 2317e5dfcd27SRobin Chen /** 2318e5dfcd27SRobin Chen * Explicit padding to 4 byte boundary. 2319e5dfcd27SRobin Chen */ 2320e5dfcd27SRobin Chen uint8_t pad[2]; 2321e5dfcd27SRobin Chen /** 2322e5dfcd27SRobin Chen * PSR power option 2323e5dfcd27SRobin Chen */ 2324e5dfcd27SRobin Chen uint32_t power_opt; 2325e5dfcd27SRobin Chen }; 2326e5dfcd27SRobin Chen 2327e5dfcd27SRobin Chen /** 2328e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2329e5dfcd27SRobin Chen */ 2330e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt { 2331e5dfcd27SRobin Chen /** 2332e5dfcd27SRobin Chen * Command header. 2333e5dfcd27SRobin Chen */ 2334e5dfcd27SRobin Chen struct dmub_cmd_header header; 2335e5dfcd27SRobin Chen /** 2336e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2337e5dfcd27SRobin Chen */ 2338e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2339e5dfcd27SRobin Chen }; 2340e5dfcd27SRobin Chen 2341e5dfcd27SRobin Chen /** 23421a595f28SAnthony Koo * Set of HW components that can be locked. 23430b51e7e8SAnthony Koo * 23440b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 23450b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 23461a595f28SAnthony Koo */ 2347788408b7SAnthony Koo union dmub_hw_lock_flags { 23481a595f28SAnthony Koo /** 23491a595f28SAnthony Koo * Set of HW components that can be locked. 23501a595f28SAnthony Koo */ 2351788408b7SAnthony Koo struct { 23521a595f28SAnthony Koo /** 23531a595f28SAnthony Koo * Lock/unlock OTG master update lock. 23541a595f28SAnthony Koo */ 2355788408b7SAnthony Koo uint8_t lock_pipe : 1; 23561a595f28SAnthony Koo /** 23571a595f28SAnthony Koo * Lock/unlock cursor. 23581a595f28SAnthony Koo */ 2359788408b7SAnthony Koo uint8_t lock_cursor : 1; 23601a595f28SAnthony Koo /** 23611a595f28SAnthony Koo * Lock/unlock global update lock. 23621a595f28SAnthony Koo */ 2363788408b7SAnthony Koo uint8_t lock_dig : 1; 23641a595f28SAnthony Koo /** 23651a595f28SAnthony Koo * Triple buffer lock requires additional hw programming to usual OTG master lock. 23661a595f28SAnthony Koo */ 2367788408b7SAnthony Koo uint8_t triple_buffer_lock : 1; 2368788408b7SAnthony Koo } bits; 2369788408b7SAnthony Koo 23701a595f28SAnthony Koo /** 23711a595f28SAnthony Koo * Union for HW Lock flags. 23721a595f28SAnthony Koo */ 2373788408b7SAnthony Koo uint8_t u8All; 2374788408b7SAnthony Koo }; 2375788408b7SAnthony Koo 23761a595f28SAnthony Koo /** 23771a595f28SAnthony Koo * Instances of HW to be locked. 23780b51e7e8SAnthony Koo * 23790b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 23800b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 23811a595f28SAnthony Koo */ 2382788408b7SAnthony Koo struct dmub_hw_lock_inst_flags { 23831a595f28SAnthony Koo /** 23841a595f28SAnthony Koo * OTG HW instance for OTG master update lock. 23851a595f28SAnthony Koo */ 2386788408b7SAnthony Koo uint8_t otg_inst; 23871a595f28SAnthony Koo /** 23881a595f28SAnthony Koo * OPP instance for cursor lock. 23891a595f28SAnthony Koo */ 2390788408b7SAnthony Koo uint8_t opp_inst; 23911a595f28SAnthony Koo /** 23921a595f28SAnthony Koo * OTG HW instance for global update lock. 23931a595f28SAnthony Koo * TODO: Remove, and re-use otg_inst. 23941a595f28SAnthony Koo */ 2395788408b7SAnthony Koo uint8_t dig_inst; 23961a595f28SAnthony Koo /** 23971a595f28SAnthony Koo * Explicit pad to 4 byte boundary. 23981a595f28SAnthony Koo */ 2399788408b7SAnthony Koo uint8_t pad; 2400788408b7SAnthony Koo }; 2401788408b7SAnthony Koo 24021a595f28SAnthony Koo /** 24031a595f28SAnthony Koo * Clients that can acquire the HW Lock Manager. 24040b51e7e8SAnthony Koo * 24050b51e7e8SAnthony Koo * Note: If updating with more clients, fields in 24060b51e7e8SAnthony Koo * dmub_inbox0_cmd_lock_hw must be updated to match. 24071a595f28SAnthony Koo */ 2408788408b7SAnthony Koo enum hw_lock_client { 24091a595f28SAnthony Koo /** 24101a595f28SAnthony Koo * Driver is the client of HW Lock Manager. 24111a595f28SAnthony Koo */ 2412788408b7SAnthony Koo HW_LOCK_CLIENT_DRIVER = 0, 24131a595f28SAnthony Koo /** 241483eb5385SDavid Zhang * PSR SU is the client of HW Lock Manager. 241583eb5385SDavid Zhang */ 241683eb5385SDavid Zhang HW_LOCK_CLIENT_PSR_SU = 1, 241783eb5385SDavid Zhang /** 24181a595f28SAnthony Koo * Invalid client. 24191a595f28SAnthony Koo */ 2420788408b7SAnthony Koo HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2421788408b7SAnthony Koo }; 2422788408b7SAnthony Koo 24231a595f28SAnthony Koo /** 24241a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 24251a595f28SAnthony Koo */ 2426788408b7SAnthony Koo struct dmub_cmd_lock_hw_data { 24271a595f28SAnthony Koo /** 24281a595f28SAnthony Koo * Specifies the client accessing HW Lock Manager. 24291a595f28SAnthony Koo */ 2430788408b7SAnthony Koo enum hw_lock_client client; 24311a595f28SAnthony Koo /** 24321a595f28SAnthony Koo * HW instances to be locked. 24331a595f28SAnthony Koo */ 2434788408b7SAnthony Koo struct dmub_hw_lock_inst_flags inst_flags; 24351a595f28SAnthony Koo /** 24361a595f28SAnthony Koo * Which components to be locked. 24371a595f28SAnthony Koo */ 2438788408b7SAnthony Koo union dmub_hw_lock_flags hw_locks; 24391a595f28SAnthony Koo /** 24401a595f28SAnthony Koo * Specifies lock/unlock. 24411a595f28SAnthony Koo */ 2442788408b7SAnthony Koo uint8_t lock; 24431a595f28SAnthony Koo /** 24441a595f28SAnthony Koo * HW can be unlocked separately from releasing the HW Lock Mgr. 24451a595f28SAnthony Koo * This flag is set if the client wishes to release the object. 24461a595f28SAnthony Koo */ 2447788408b7SAnthony Koo uint8_t should_release; 24481a595f28SAnthony Koo /** 24491a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 24501a595f28SAnthony Koo */ 2451788408b7SAnthony Koo uint8_t pad; 2452788408b7SAnthony Koo }; 2453788408b7SAnthony Koo 24541a595f28SAnthony Koo /** 24551a595f28SAnthony Koo * Definition of a DMUB_CMD__HW_LOCK command. 24561a595f28SAnthony Koo * Command is used by driver and FW. 24571a595f28SAnthony Koo */ 2458788408b7SAnthony Koo struct dmub_rb_cmd_lock_hw { 24591a595f28SAnthony Koo /** 24601a595f28SAnthony Koo * Command header. 24611a595f28SAnthony Koo */ 2462788408b7SAnthony Koo struct dmub_cmd_header header; 24631a595f28SAnthony Koo /** 24641a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 24651a595f28SAnthony Koo */ 2466788408b7SAnthony Koo struct dmub_cmd_lock_hw_data lock_hw_data; 2467788408b7SAnthony Koo }; 2468788408b7SAnthony Koo 24691a595f28SAnthony Koo /** 24701a595f28SAnthony Koo * ABM command sub-types. 24711a595f28SAnthony Koo */ 247284034ad4SAnthony Koo enum dmub_cmd_abm_type { 24731a595f28SAnthony Koo /** 24741a595f28SAnthony Koo * Initialize parameters for ABM algorithm. 24751a595f28SAnthony Koo * Data is passed through an indirect buffer. 24761a595f28SAnthony Koo */ 247784034ad4SAnthony Koo DMUB_CMD__ABM_INIT_CONFIG = 0, 24781a595f28SAnthony Koo /** 24791a595f28SAnthony Koo * Set OTG and panel HW instance. 24801a595f28SAnthony Koo */ 248184034ad4SAnthony Koo DMUB_CMD__ABM_SET_PIPE = 1, 24821a595f28SAnthony Koo /** 24831a595f28SAnthony Koo * Set user requested backklight level. 24841a595f28SAnthony Koo */ 248584034ad4SAnthony Koo DMUB_CMD__ABM_SET_BACKLIGHT = 2, 24861a595f28SAnthony Koo /** 24871a595f28SAnthony Koo * Set ABM operating/aggression level. 24881a595f28SAnthony Koo */ 248984034ad4SAnthony Koo DMUB_CMD__ABM_SET_LEVEL = 3, 24901a595f28SAnthony Koo /** 24911a595f28SAnthony Koo * Set ambient light level. 24921a595f28SAnthony Koo */ 249384034ad4SAnthony Koo DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 24941a595f28SAnthony Koo /** 24951a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 24961a595f28SAnthony Koo */ 249784034ad4SAnthony Koo DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2498b629a824SEric Yang 2499b629a824SEric Yang /** 2500b629a824SEric Yang * unregister vertical interrupt after steady state is reached 2501b629a824SEric Yang */ 2502b629a824SEric Yang DMUB_CMD__ABM_PAUSE = 6, 250384034ad4SAnthony Koo }; 250484034ad4SAnthony Koo 25051a595f28SAnthony Koo /** 25061a595f28SAnthony Koo * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 25071a595f28SAnthony Koo * Requirements: 25081a595f28SAnthony Koo * - Padded explicitly to 32-bit boundary. 25091a595f28SAnthony Koo * - Must ensure this structure matches the one on driver-side, 25101a595f28SAnthony Koo * otherwise it won't be aligned. 251184034ad4SAnthony Koo */ 251284034ad4SAnthony Koo struct abm_config_table { 25131a595f28SAnthony Koo /** 25141a595f28SAnthony Koo * Gamma curve thresholds, used for crgb conversion. 25151a595f28SAnthony Koo */ 251684034ad4SAnthony Koo uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 25171a595f28SAnthony Koo /** 25181a595f28SAnthony Koo * Gamma curve offsets, used for crgb conversion. 25191a595f28SAnthony Koo */ 2520b6402afeSAnthony Koo uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 25211a595f28SAnthony Koo /** 25221a595f28SAnthony Koo * Gamma curve slopes, used for crgb conversion. 25231a595f28SAnthony Koo */ 2524b6402afeSAnthony Koo uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 25251a595f28SAnthony Koo /** 25261a595f28SAnthony Koo * Custom backlight curve thresholds. 25271a595f28SAnthony Koo */ 2528b6402afeSAnthony Koo uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 25291a595f28SAnthony Koo /** 25301a595f28SAnthony Koo * Custom backlight curve offsets. 25311a595f28SAnthony Koo */ 2532b6402afeSAnthony Koo uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 25331a595f28SAnthony Koo /** 25341a595f28SAnthony Koo * Ambient light thresholds. 25351a595f28SAnthony Koo */ 2536b6402afeSAnthony Koo uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 25371a595f28SAnthony Koo /** 25381a595f28SAnthony Koo * Minimum programmable backlight. 25391a595f28SAnthony Koo */ 2540b6402afeSAnthony Koo uint16_t min_abm_backlight; // 122B 25411a595f28SAnthony Koo /** 25421a595f28SAnthony Koo * Minimum reduction values. 25431a595f28SAnthony Koo */ 2544b6402afeSAnthony Koo uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 25451a595f28SAnthony Koo /** 25461a595f28SAnthony Koo * Maximum reduction values. 25471a595f28SAnthony Koo */ 2548b6402afeSAnthony Koo uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 25491a595f28SAnthony Koo /** 25501a595f28SAnthony Koo * Bright positive gain. 25511a595f28SAnthony Koo */ 2552b6402afeSAnthony Koo uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 25531a595f28SAnthony Koo /** 25541a595f28SAnthony Koo * Dark negative gain. 25551a595f28SAnthony Koo */ 2556b6402afeSAnthony Koo uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 25571a595f28SAnthony Koo /** 25581a595f28SAnthony Koo * Hybrid factor. 25591a595f28SAnthony Koo */ 2560b6402afeSAnthony Koo uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 25611a595f28SAnthony Koo /** 25621a595f28SAnthony Koo * Contrast factor. 25631a595f28SAnthony Koo */ 2564b6402afeSAnthony Koo uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 25651a595f28SAnthony Koo /** 25661a595f28SAnthony Koo * Deviation gain. 25671a595f28SAnthony Koo */ 2568b6402afeSAnthony Koo uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 25691a595f28SAnthony Koo /** 25701a595f28SAnthony Koo * Minimum knee. 25711a595f28SAnthony Koo */ 2572b6402afeSAnthony Koo uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 25731a595f28SAnthony Koo /** 25741a595f28SAnthony Koo * Maximum knee. 25751a595f28SAnthony Koo */ 2576b6402afeSAnthony Koo uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 25771a595f28SAnthony Koo /** 25781a595f28SAnthony Koo * Unused. 25791a595f28SAnthony Koo */ 2580b6402afeSAnthony Koo uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 25811a595f28SAnthony Koo /** 25821a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 25831a595f28SAnthony Koo */ 2584b6402afeSAnthony Koo uint8_t pad3[3]; // 229B 25851a595f28SAnthony Koo /** 25861a595f28SAnthony Koo * Backlight ramp reduction. 25871a595f28SAnthony Koo */ 2588b6402afeSAnthony Koo uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 25891a595f28SAnthony Koo /** 25901a595f28SAnthony Koo * Backlight ramp start. 25911a595f28SAnthony Koo */ 2592b6402afeSAnthony Koo uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 259384034ad4SAnthony Koo }; 259484034ad4SAnthony Koo 25951a595f28SAnthony Koo /** 25961a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 25971a595f28SAnthony Koo */ 2598e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data { 25991a595f28SAnthony Koo /** 26001a595f28SAnthony Koo * OTG HW instance. 26011a595f28SAnthony Koo */ 26027b8a6362SAnthony Koo uint8_t otg_inst; 26031a595f28SAnthony Koo 26041a595f28SAnthony Koo /** 26051a595f28SAnthony Koo * Panel Control HW instance. 26061a595f28SAnthony Koo */ 26077b8a6362SAnthony Koo uint8_t panel_inst; 26081a595f28SAnthony Koo 26091a595f28SAnthony Koo /** 26101a595f28SAnthony Koo * Controls how ABM will interpret a set pipe or set level command. 26111a595f28SAnthony Koo */ 26127b8a6362SAnthony Koo uint8_t set_pipe_option; 26131a595f28SAnthony Koo 26141a595f28SAnthony Koo /** 26151a595f28SAnthony Koo * Unused. 26161a595f28SAnthony Koo * TODO: Remove. 26171a595f28SAnthony Koo */ 26181a595f28SAnthony Koo uint8_t ramping_boundary; 2619e6ea8c34SWyatt Wood }; 2620e6ea8c34SWyatt Wood 26211a595f28SAnthony Koo /** 26221a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 26231a595f28SAnthony Koo */ 2624e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe { 26251a595f28SAnthony Koo /** 26261a595f28SAnthony Koo * Command header. 26271a595f28SAnthony Koo */ 2628e6ea8c34SWyatt Wood struct dmub_cmd_header header; 26291a595f28SAnthony Koo 26301a595f28SAnthony Koo /** 26311a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 26321a595f28SAnthony Koo */ 2633e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2634e6ea8c34SWyatt Wood }; 2635e6ea8c34SWyatt Wood 26361a595f28SAnthony Koo /** 26371a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 26381a595f28SAnthony Koo */ 2639e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data { 26401a595f28SAnthony Koo /** 26411a595f28SAnthony Koo * Number of frames to ramp to backlight user level. 26421a595f28SAnthony Koo */ 2643e6ea8c34SWyatt Wood uint32_t frame_ramp; 26441a595f28SAnthony Koo 26451a595f28SAnthony Koo /** 26461a595f28SAnthony Koo * Requested backlight level from user. 26471a595f28SAnthony Koo */ 2648474ac4a8SYongqiang Sun uint32_t backlight_user_level; 2649e922057bSJake Wang 2650e922057bSJake Wang /** 265163de4f04SJake Wang * ABM control version. 2652e922057bSJake Wang */ 2653e922057bSJake Wang uint8_t version; 2654e922057bSJake Wang 2655e922057bSJake Wang /** 2656e922057bSJake Wang * Panel Control HW instance mask. 2657e922057bSJake Wang * Bit 0 is Panel Control HW instance 0. 2658e922057bSJake Wang * Bit 1 is Panel Control HW instance 1. 2659e922057bSJake Wang */ 2660e922057bSJake Wang uint8_t panel_mask; 2661e922057bSJake Wang 2662e922057bSJake Wang /** 2663e922057bSJake Wang * Explicit padding to 4 byte boundary. 2664e922057bSJake Wang */ 2665e922057bSJake Wang uint8_t pad[2]; 2666e6ea8c34SWyatt Wood }; 2667e6ea8c34SWyatt Wood 26681a595f28SAnthony Koo /** 26691a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 26701a595f28SAnthony Koo */ 2671e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight { 26721a595f28SAnthony Koo /** 26731a595f28SAnthony Koo * Command header. 26741a595f28SAnthony Koo */ 2675e6ea8c34SWyatt Wood struct dmub_cmd_header header; 26761a595f28SAnthony Koo 26771a595f28SAnthony Koo /** 26781a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 26791a595f28SAnthony Koo */ 2680e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2681e6ea8c34SWyatt Wood }; 2682e6ea8c34SWyatt Wood 26831a595f28SAnthony Koo /** 26841a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 26851a595f28SAnthony Koo */ 2686e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data { 26871a595f28SAnthony Koo /** 26881a595f28SAnthony Koo * Set current ABM operating/aggression level. 26891a595f28SAnthony Koo */ 2690e6ea8c34SWyatt Wood uint32_t level; 269163de4f04SJake Wang 269263de4f04SJake Wang /** 269363de4f04SJake Wang * ABM control version. 269463de4f04SJake Wang */ 269563de4f04SJake Wang uint8_t version; 269663de4f04SJake Wang 269763de4f04SJake Wang /** 269863de4f04SJake Wang * Panel Control HW instance mask. 269963de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 270063de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 270163de4f04SJake Wang */ 270263de4f04SJake Wang uint8_t panel_mask; 270363de4f04SJake Wang 270463de4f04SJake Wang /** 270563de4f04SJake Wang * Explicit padding to 4 byte boundary. 270663de4f04SJake Wang */ 270763de4f04SJake Wang uint8_t pad[2]; 2708e6ea8c34SWyatt Wood }; 2709e6ea8c34SWyatt Wood 27101a595f28SAnthony Koo /** 27111a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 27121a595f28SAnthony Koo */ 2713e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level { 27141a595f28SAnthony Koo /** 27151a595f28SAnthony Koo * Command header. 27161a595f28SAnthony Koo */ 2717e6ea8c34SWyatt Wood struct dmub_cmd_header header; 27181a595f28SAnthony Koo 27191a595f28SAnthony Koo /** 27201a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 27211a595f28SAnthony Koo */ 2722e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data abm_set_level_data; 2723e6ea8c34SWyatt Wood }; 2724e6ea8c34SWyatt Wood 27251a595f28SAnthony Koo /** 27261a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 27271a595f28SAnthony Koo */ 2728e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data { 27291a595f28SAnthony Koo /** 27301a595f28SAnthony Koo * Ambient light sensor reading from OS. 27311a595f28SAnthony Koo */ 2732e6ea8c34SWyatt Wood uint32_t ambient_lux; 273363de4f04SJake Wang 273463de4f04SJake Wang /** 273563de4f04SJake Wang * ABM control version. 273663de4f04SJake Wang */ 273763de4f04SJake Wang uint8_t version; 273863de4f04SJake Wang 273963de4f04SJake Wang /** 274063de4f04SJake Wang * Panel Control HW instance mask. 274163de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 274263de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 274363de4f04SJake Wang */ 274463de4f04SJake Wang uint8_t panel_mask; 274563de4f04SJake Wang 274663de4f04SJake Wang /** 274763de4f04SJake Wang * Explicit padding to 4 byte boundary. 274863de4f04SJake Wang */ 274963de4f04SJake Wang uint8_t pad[2]; 2750e6ea8c34SWyatt Wood }; 2751e6ea8c34SWyatt Wood 27521a595f28SAnthony Koo /** 27531a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 27541a595f28SAnthony Koo */ 2755e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level { 27561a595f28SAnthony Koo /** 27571a595f28SAnthony Koo * Command header. 27581a595f28SAnthony Koo */ 2759e6ea8c34SWyatt Wood struct dmub_cmd_header header; 27601a595f28SAnthony Koo 27611a595f28SAnthony Koo /** 27621a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 27631a595f28SAnthony Koo */ 2764e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2765e6ea8c34SWyatt Wood }; 2766e6ea8c34SWyatt Wood 27671a595f28SAnthony Koo /** 27681a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 27691a595f28SAnthony Koo */ 2770e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data { 27711a595f28SAnthony Koo /** 27721a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 27731a595f28SAnthony Koo * TODO: Convert to uint8_t. 27741a595f28SAnthony Koo */ 2775e6ea8c34SWyatt Wood uint32_t fractional_pwm; 277663de4f04SJake Wang 277763de4f04SJake Wang /** 277863de4f04SJake Wang * ABM control version. 277963de4f04SJake Wang */ 278063de4f04SJake Wang uint8_t version; 278163de4f04SJake Wang 278263de4f04SJake Wang /** 278363de4f04SJake Wang * Panel Control HW instance mask. 278463de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 278563de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 278663de4f04SJake Wang */ 278763de4f04SJake Wang uint8_t panel_mask; 278863de4f04SJake Wang 278963de4f04SJake Wang /** 279063de4f04SJake Wang * Explicit padding to 4 byte boundary. 279163de4f04SJake Wang */ 279263de4f04SJake Wang uint8_t pad[2]; 2793e6ea8c34SWyatt Wood }; 2794e6ea8c34SWyatt Wood 27951a595f28SAnthony Koo /** 27961a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 27971a595f28SAnthony Koo */ 2798e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac { 27991a595f28SAnthony Koo /** 28001a595f28SAnthony Koo * Command header. 28011a595f28SAnthony Koo */ 2802e6ea8c34SWyatt Wood struct dmub_cmd_header header; 28031a595f28SAnthony Koo 28041a595f28SAnthony Koo /** 28051a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 28061a595f28SAnthony Koo */ 2807e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2808e6ea8c34SWyatt Wood }; 2809e6ea8c34SWyatt Wood 28101a595f28SAnthony Koo /** 28111a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 28121a595f28SAnthony Koo */ 281316012806SWyatt Wood struct dmub_cmd_abm_init_config_data { 28141a595f28SAnthony Koo /** 28151a595f28SAnthony Koo * Location of indirect buffer used to pass init data to ABM. 28161a595f28SAnthony Koo */ 281716012806SWyatt Wood union dmub_addr src; 28181a595f28SAnthony Koo 28191a595f28SAnthony Koo /** 28201a595f28SAnthony Koo * Indirect buffer length. 28211a595f28SAnthony Koo */ 282216012806SWyatt Wood uint16_t bytes; 282363de4f04SJake Wang 282463de4f04SJake Wang 282563de4f04SJake Wang /** 282663de4f04SJake Wang * ABM control version. 282763de4f04SJake Wang */ 282863de4f04SJake Wang uint8_t version; 282963de4f04SJake Wang 283063de4f04SJake Wang /** 283163de4f04SJake Wang * Panel Control HW instance mask. 283263de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 283363de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 283463de4f04SJake Wang */ 283563de4f04SJake Wang uint8_t panel_mask; 283663de4f04SJake Wang 283763de4f04SJake Wang /** 283863de4f04SJake Wang * Explicit padding to 4 byte boundary. 283963de4f04SJake Wang */ 284063de4f04SJake Wang uint8_t pad[2]; 284116012806SWyatt Wood }; 284216012806SWyatt Wood 28431a595f28SAnthony Koo /** 28441a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 28451a595f28SAnthony Koo */ 284616012806SWyatt Wood struct dmub_rb_cmd_abm_init_config { 28471a595f28SAnthony Koo /** 28481a595f28SAnthony Koo * Command header. 28491a595f28SAnthony Koo */ 285016012806SWyatt Wood struct dmub_cmd_header header; 28511a595f28SAnthony Koo 28521a595f28SAnthony Koo /** 28531a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 28541a595f28SAnthony Koo */ 285516012806SWyatt Wood struct dmub_cmd_abm_init_config_data abm_init_config_data; 285616012806SWyatt Wood }; 285716012806SWyatt Wood 28581a595f28SAnthony Koo /** 2859b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2860b629a824SEric Yang */ 2861b629a824SEric Yang 2862b629a824SEric Yang struct dmub_cmd_abm_pause_data { 2863b629a824SEric Yang 2864b629a824SEric Yang /** 2865b629a824SEric Yang * Panel Control HW instance mask. 2866b629a824SEric Yang * Bit 0 is Panel Control HW instance 0. 2867b629a824SEric Yang * Bit 1 is Panel Control HW instance 1. 2868b629a824SEric Yang */ 2869b629a824SEric Yang uint8_t panel_mask; 2870b629a824SEric Yang 2871b629a824SEric Yang /** 2872b629a824SEric Yang * OTG hw instance 2873b629a824SEric Yang */ 2874b629a824SEric Yang uint8_t otg_inst; 2875b629a824SEric Yang 2876b629a824SEric Yang /** 2877b629a824SEric Yang * Enable or disable ABM pause 2878b629a824SEric Yang */ 2879b629a824SEric Yang uint8_t enable; 2880b629a824SEric Yang 2881b629a824SEric Yang /** 2882b629a824SEric Yang * Explicit padding to 4 byte boundary. 2883b629a824SEric Yang */ 2884b629a824SEric Yang uint8_t pad[1]; 2885b629a824SEric Yang }; 2886b629a824SEric Yang 2887b629a824SEric Yang /** 2888b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 2889b629a824SEric Yang */ 2890b629a824SEric Yang struct dmub_rb_cmd_abm_pause { 2891b629a824SEric Yang /** 2892b629a824SEric Yang * Command header. 2893b629a824SEric Yang */ 2894b629a824SEric Yang struct dmub_cmd_header header; 2895b629a824SEric Yang 2896b629a824SEric Yang /** 2897b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2898b629a824SEric Yang */ 2899b629a824SEric Yang struct dmub_cmd_abm_pause_data abm_pause_data; 2900b629a824SEric Yang }; 2901b629a824SEric Yang 2902b629a824SEric Yang /** 29031a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 29041a595f28SAnthony Koo */ 290534ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data { 29061a595f28SAnthony Koo /** 29071a595f28SAnthony Koo * DMUB feature capabilities. 29081a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features. 29091a595f28SAnthony Koo */ 291034ba432cSAnthony Koo struct dmub_feature_caps feature_caps; 291134ba432cSAnthony Koo }; 291234ba432cSAnthony Koo 29131a595f28SAnthony Koo /** 29141a595f28SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 29151a595f28SAnthony Koo */ 291634ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps { 29171a595f28SAnthony Koo /** 29181a595f28SAnthony Koo * Command header. 29191a595f28SAnthony Koo */ 292034ba432cSAnthony Koo struct dmub_cmd_header header; 29211a595f28SAnthony Koo /** 29221a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 29231a595f28SAnthony Koo */ 292434ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 292534ba432cSAnthony Koo }; 292634ba432cSAnthony Koo 2927b09c1fffSLeo (Hanghong) Ma /** 2928b09c1fffSLeo (Hanghong) Ma * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2929b09c1fffSLeo (Hanghong) Ma */ 2930b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_visual_confirm_color_data { 2931b09c1fffSLeo (Hanghong) Ma /** 2932b09c1fffSLeo (Hanghong) Ma * DMUB feature capabilities. 2933b09c1fffSLeo (Hanghong) Ma * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2934b09c1fffSLeo (Hanghong) Ma */ 2935b09c1fffSLeo (Hanghong) Ma struct dmub_visual_confirm_color visual_confirm_color; 2936b09c1fffSLeo (Hanghong) Ma }; 2937b09c1fffSLeo (Hanghong) Ma 2938b09c1fffSLeo (Hanghong) Ma /** 2939b09c1fffSLeo (Hanghong) Ma * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2940b09c1fffSLeo (Hanghong) Ma */ 2941b09c1fffSLeo (Hanghong) Ma struct dmub_rb_cmd_get_visual_confirm_color { 2942b09c1fffSLeo (Hanghong) Ma /** 2943b09c1fffSLeo (Hanghong) Ma * Command header. 2944b09c1fffSLeo (Hanghong) Ma */ 2945b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_header header; 2946b09c1fffSLeo (Hanghong) Ma /** 2947b09c1fffSLeo (Hanghong) Ma * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2948b09c1fffSLeo (Hanghong) Ma */ 2949b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 2950b09c1fffSLeo (Hanghong) Ma }; 2951b09c1fffSLeo (Hanghong) Ma 2952592a6318SAnthony Koo struct dmub_optc_state { 2953592a6318SAnthony Koo uint32_t v_total_max; 2954592a6318SAnthony Koo uint32_t v_total_min; 2955592a6318SAnthony Koo uint32_t tg_inst; 2956592a6318SAnthony Koo }; 2957592a6318SAnthony Koo 2958592a6318SAnthony Koo struct dmub_rb_cmd_drr_update { 2959592a6318SAnthony Koo struct dmub_cmd_header header; 2960592a6318SAnthony Koo struct dmub_optc_state dmub_optc_state_req; 2961592a6318SAnthony Koo }; 2962592a6318SAnthony Koo 296300fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 296400fa7f03SRodrigo Siqueira uint32_t pix_clk_100hz; 296500fa7f03SRodrigo Siqueira uint8_t max_ramp_step; 296600fa7f03SRodrigo Siqueira uint8_t pipes; 296700fa7f03SRodrigo Siqueira uint8_t min_refresh_in_hz; 296800fa7f03SRodrigo Siqueira uint8_t padding[1]; 296900fa7f03SRodrigo Siqueira }; 297000fa7f03SRodrigo Siqueira 297100fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config { 297200fa7f03SRodrigo Siqueira uint8_t fams_enabled; 297300fa7f03SRodrigo Siqueira uint8_t visual_confirm_enabled; 297400fa7f03SRodrigo Siqueira uint8_t padding[2]; 297500fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 297600fa7f03SRodrigo Siqueira }; 297700fa7f03SRodrigo Siqueira 297800fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch { 297900fa7f03SRodrigo Siqueira struct dmub_cmd_header header; 298000fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 298100fa7f03SRodrigo Siqueira }; 298200fa7f03SRodrigo Siqueira 2983b04cb192SNicholas Kazlauskas /** 2984b04cb192SNicholas Kazlauskas * enum dmub_cmd_panel_cntl_type - Panel control command. 2985b04cb192SNicholas Kazlauskas */ 2986b04cb192SNicholas Kazlauskas enum dmub_cmd_panel_cntl_type { 2987b04cb192SNicholas Kazlauskas /** 2988b04cb192SNicholas Kazlauskas * Initializes embedded panel hardware blocks. 2989b04cb192SNicholas Kazlauskas */ 2990b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2991b04cb192SNicholas Kazlauskas /** 2992b04cb192SNicholas Kazlauskas * Queries backlight info for the embedded panel. 2993b04cb192SNicholas Kazlauskas */ 2994b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2995b04cb192SNicholas Kazlauskas }; 2996b04cb192SNicholas Kazlauskas 2997b04cb192SNicholas Kazlauskas /** 2998b04cb192SNicholas Kazlauskas * struct dmub_cmd_panel_cntl_data - Panel control data. 2999b04cb192SNicholas Kazlauskas */ 3000b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data { 3001b04cb192SNicholas Kazlauskas uint32_t inst; /**< panel instance */ 3002b04cb192SNicholas Kazlauskas uint32_t current_backlight; /* in/out */ 3003b04cb192SNicholas Kazlauskas uint32_t bl_pwm_cntl; /* in/out */ 3004b04cb192SNicholas Kazlauskas uint32_t bl_pwm_period_cntl; /* in/out */ 3005b04cb192SNicholas Kazlauskas uint32_t bl_pwm_ref_div1; /* in/out */ 3006b04cb192SNicholas Kazlauskas uint8_t is_backlight_on : 1; /* in/out */ 3007b04cb192SNicholas Kazlauskas uint8_t is_powered_on : 1; /* in/out */ 3008a91b402dSCharlene Liu uint8_t padding[3]; 3009a91b402dSCharlene Liu uint32_t bl_pwm_ref_div2; /* in/out */ 3010a91b402dSCharlene Liu uint8_t reserved[4]; 3011b04cb192SNicholas Kazlauskas }; 3012b04cb192SNicholas Kazlauskas 3013b04cb192SNicholas Kazlauskas /** 3014b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_panel_cntl - Panel control command. 3015b04cb192SNicholas Kazlauskas */ 3016b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl { 3017b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 3018b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data data; /**< payload */ 3019b04cb192SNicholas Kazlauskas }; 3020b04cb192SNicholas Kazlauskas 30211a595f28SAnthony Koo /** 30221a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 30231a595f28SAnthony Koo */ 30241a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data { 30251a595f28SAnthony Koo uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 30261a595f28SAnthony Koo uint8_t reserved_0[3]; /**< For future use */ 30271a595f28SAnthony Koo uint8_t panel_inst; /**< LVTMA control instance */ 30281a595f28SAnthony Koo uint8_t reserved_1[3]; /**< For future use */ 30291a595f28SAnthony Koo }; 30301a595f28SAnthony Koo 30311a595f28SAnthony Koo /** 30321a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 30331a595f28SAnthony Koo */ 30341a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control { 30351a595f28SAnthony Koo /** 30361a595f28SAnthony Koo * Command header. 30371a595f28SAnthony Koo */ 30381a595f28SAnthony Koo struct dmub_cmd_header header; 30391a595f28SAnthony Koo /** 30401a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 30411a595f28SAnthony Koo */ 30421a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data data; 30431a595f28SAnthony Koo }; 30441a595f28SAnthony Koo 3045592a6318SAnthony Koo /** 304641f91315SNicholas Kazlauskas * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 304741f91315SNicholas Kazlauskas */ 304841f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data { 304941f91315SNicholas Kazlauskas uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 305041f91315SNicholas Kazlauskas uint8_t is_usb; /**< is phy is usb */ 305141f91315SNicholas Kazlauskas uint8_t is_dp_alt_disable; /**< is dp alt disable */ 305241f91315SNicholas Kazlauskas uint8_t is_dp4; /**< is dp in 4 lane */ 305341f91315SNicholas Kazlauskas }; 305441f91315SNicholas Kazlauskas 305541f91315SNicholas Kazlauskas /** 305641f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 305741f91315SNicholas Kazlauskas */ 305841f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt { 305941f91315SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 306041f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 306141f91315SNicholas Kazlauskas }; 306241f91315SNicholas Kazlauskas 306341f91315SNicholas Kazlauskas /** 3064021eaef8SAnthony Koo * Maximum number of bytes a chunk sent to DMUB for parsing 3065021eaef8SAnthony Koo */ 3066021eaef8SAnthony Koo #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3067021eaef8SAnthony Koo 3068021eaef8SAnthony Koo /** 3069021eaef8SAnthony Koo * Represent a chunk of CEA blocks sent to DMUB for parsing 3070021eaef8SAnthony Koo */ 3071021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea { 3072021eaef8SAnthony Koo uint16_t offset; /**< offset into the CEA block */ 3073021eaef8SAnthony Koo uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3074eb9e59ebSOliver Logush uint16_t cea_total_length; /**< total length of the CEA block */ 3075021eaef8SAnthony Koo uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3076021eaef8SAnthony Koo uint8_t pad[3]; /**< padding and for future expansion */ 3077021eaef8SAnthony Koo }; 3078021eaef8SAnthony Koo 3079021eaef8SAnthony Koo /** 3080021eaef8SAnthony Koo * Result of VSDB parsing from CEA block 3081021eaef8SAnthony Koo */ 3082021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb { 3083021eaef8SAnthony Koo uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3084021eaef8SAnthony Koo uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3085021eaef8SAnthony Koo uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3086021eaef8SAnthony Koo uint16_t min_frame_rate; /**< Maximum frame rate */ 3087021eaef8SAnthony Koo uint16_t max_frame_rate; /**< Minimum frame rate */ 3088021eaef8SAnthony Koo }; 3089021eaef8SAnthony Koo 3090021eaef8SAnthony Koo /** 3091021eaef8SAnthony Koo * Result of sending a CEA chunk 3092021eaef8SAnthony Koo */ 3093021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack { 3094021eaef8SAnthony Koo uint16_t offset; /**< offset of the chunk into the CEA block */ 3095021eaef8SAnthony Koo uint8_t success; /**< 1 if this sending of chunk succeeded */ 3096021eaef8SAnthony Koo uint8_t pad; /**< padding and for future expansion */ 3097021eaef8SAnthony Koo }; 3098021eaef8SAnthony Koo 3099021eaef8SAnthony Koo /** 3100021eaef8SAnthony Koo * Specify whether the result is an ACK/NACK or the parsing has finished 3101021eaef8SAnthony Koo */ 3102021eaef8SAnthony Koo enum dmub_cmd_edid_cea_reply_type { 3103021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3104021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3105021eaef8SAnthony Koo }; 3106021eaef8SAnthony Koo 3107021eaef8SAnthony Koo /** 3108021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 3109021eaef8SAnthony Koo */ 3110021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea { 3111021eaef8SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 3112021eaef8SAnthony Koo union dmub_cmd_edid_cea_data { 3113021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3114021eaef8SAnthony Koo struct dmub_cmd_edid_cea_output { /**< output with results */ 3115021eaef8SAnthony Koo uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3116021eaef8SAnthony Koo union { 3117021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3118021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack ack; 3119021eaef8SAnthony Koo }; 3120021eaef8SAnthony Koo } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3121021eaef8SAnthony Koo } data; /**< Command data */ 3122021eaef8SAnthony Koo 3123021eaef8SAnthony Koo }; 3124021eaef8SAnthony Koo 3125021eaef8SAnthony Koo /** 3126c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3127c595fb05SWenjing Liu */ 3128c595fb05SWenjing Liu struct dmub_cmd_cable_id_input { 3129c595fb05SWenjing Liu uint8_t phy_inst; /**< phy inst for cable id data */ 3130c595fb05SWenjing Liu }; 3131c595fb05SWenjing Liu 3132c595fb05SWenjing Liu /** 3133c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3134c595fb05SWenjing Liu */ 3135c595fb05SWenjing Liu struct dmub_cmd_cable_id_output { 3136c595fb05SWenjing Liu uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3137c595fb05SWenjing Liu uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3138c595fb05SWenjing Liu uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3139c595fb05SWenjing Liu uint8_t RESERVED :2; /**< reserved means not defined */ 3140c595fb05SWenjing Liu }; 3141c595fb05SWenjing Liu 3142c595fb05SWenjing Liu /** 3143c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3144c595fb05SWenjing Liu */ 3145c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id { 3146c595fb05SWenjing Liu struct dmub_cmd_header header; /**< Command header */ 3147c595fb05SWenjing Liu /** 3148c595fb05SWenjing Liu * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3149c595fb05SWenjing Liu */ 3150c595fb05SWenjing Liu union dmub_cmd_cable_id_data { 3151c595fb05SWenjing Liu struct dmub_cmd_cable_id_input input; /**< Input */ 3152c595fb05SWenjing Liu struct dmub_cmd_cable_id_output output; /**< Output */ 3153c595fb05SWenjing Liu uint8_t output_raw; /**< Raw data output */ 3154c595fb05SWenjing Liu } data; 3155c595fb05SWenjing Liu }; 3156c595fb05SWenjing Liu 31571fb695d9SAnthony Koo /** 31581fb695d9SAnthony Koo * Command type of a DMUB_CMD__SECURE_DISPLAY command 31591fb695d9SAnthony Koo */ 3160c0459bddSAlan Liu enum dmub_cmd_secure_display_type { 31611fb695d9SAnthony Koo DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3162c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3163c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3164c0459bddSAlan Liu }; 3165c0459bddSAlan Liu 31661fb695d9SAnthony Koo /** 31671fb695d9SAnthony Koo * Definition of a DMUB_CMD__SECURE_DISPLAY command 31681fb695d9SAnthony Koo */ 3169c0459bddSAlan Liu struct dmub_rb_cmd_secure_display { 3170c0459bddSAlan Liu struct dmub_cmd_header header; 31711fb695d9SAnthony Koo /** 31721fb695d9SAnthony Koo * Data passed from driver to dmub firmware. 31731fb695d9SAnthony Koo */ 3174c0459bddSAlan Liu struct dmub_cmd_roi_info { 3175c0459bddSAlan Liu uint16_t x_start; 3176c0459bddSAlan Liu uint16_t x_end; 3177c0459bddSAlan Liu uint16_t y_start; 3178c0459bddSAlan Liu uint16_t y_end; 3179c0459bddSAlan Liu uint8_t otg_id; 3180c0459bddSAlan Liu uint8_t phy_id; 3181c0459bddSAlan Liu } roi_info; 3182c0459bddSAlan Liu }; 3183c0459bddSAlan Liu 3184c595fb05SWenjing Liu /** 3185592a6318SAnthony Koo * union dmub_rb_cmd - DMUB inbox command. 3186592a6318SAnthony Koo */ 31877c008829SNicholas Kazlauskas union dmub_rb_cmd { 3188592a6318SAnthony Koo /** 3189592a6318SAnthony Koo * Elements shared with all commands. 3190592a6318SAnthony Koo */ 31917c008829SNicholas Kazlauskas struct dmub_rb_cmd_common cmd_common; 3192592a6318SAnthony Koo /** 3193592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3194592a6318SAnthony Koo */ 3195592a6318SAnthony Koo struct dmub_rb_cmd_read_modify_write read_modify_write; 3196592a6318SAnthony Koo /** 3197592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3198592a6318SAnthony Koo */ 3199592a6318SAnthony Koo struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3200592a6318SAnthony Koo /** 3201592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3202592a6318SAnthony Koo */ 3203592a6318SAnthony Koo struct dmub_rb_cmd_burst_write burst_write; 3204592a6318SAnthony Koo /** 3205592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_REG_WAIT command. 3206592a6318SAnthony Koo */ 3207592a6318SAnthony Koo struct dmub_rb_cmd_reg_wait reg_wait; 3208592a6318SAnthony Koo /** 3209592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3210592a6318SAnthony Koo */ 32117c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3212592a6318SAnthony Koo /** 3213592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3214592a6318SAnthony Koo */ 32157c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3216592a6318SAnthony Koo /** 3217592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3218592a6318SAnthony Koo */ 32197c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3220592a6318SAnthony Koo /** 3221592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3222592a6318SAnthony Koo */ 32237c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init dpphy_init; 3224592a6318SAnthony Koo /** 3225592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3226592a6318SAnthony Koo */ 32277c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 32281a595f28SAnthony Koo /** 32291a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 32301a595f28SAnthony Koo */ 3231d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version psr_set_version; 32321a595f28SAnthony Koo /** 32331a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 32341a595f28SAnthony Koo */ 32357c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 32361a595f28SAnthony Koo /** 32371a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 32381a595f28SAnthony Koo */ 3239d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_enable psr_enable; 32401a595f28SAnthony Koo /** 32411a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 32421a595f28SAnthony Koo */ 32437c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level psr_set_level; 32441a595f28SAnthony Koo /** 32451a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 32461a595f28SAnthony Koo */ 3247672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static psr_force_static; 3248592a6318SAnthony Koo /** 324983eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 325083eb5385SDavid Zhang */ 325183eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 325283eb5385SDavid Zhang /** 325383eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 325483eb5385SDavid Zhang */ 325583eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info update_cursor_info; 325683eb5385SDavid Zhang /** 325783eb5385SDavid Zhang * Definition of a DMUB_CMD__HW_LOCK command. 325883eb5385SDavid Zhang * Command is used by driver and FW. 325983eb5385SDavid Zhang */ 326083eb5385SDavid Zhang struct dmub_rb_cmd_lock_hw lock_hw; 326183eb5385SDavid Zhang /** 326283eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 326383eb5385SDavid Zhang */ 326483eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 326583eb5385SDavid Zhang /** 3266e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3267e5dfcd27SRobin Chen */ 3268e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3269e5dfcd27SRobin Chen /** 3270592a6318SAnthony Koo * Definition of a DMUB_CMD__PLAT_54186_WA command. 3271592a6318SAnthony Koo */ 3272bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3273592a6318SAnthony Koo /** 3274592a6318SAnthony Koo * Definition of a DMUB_CMD__MALL command. 3275592a6318SAnthony Koo */ 327652f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall mall; 3277b04cb192SNicholas Kazlauskas /** 3278ac2e555eSAurabindo Pillai * Definition of a DMUB_CMD__CAB command. 3279ac2e555eSAurabindo Pillai */ 3280ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss cab; 328185f4bc0cSAlvin Lee 328285f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 328385f4bc0cSAlvin Lee 3284ac2e555eSAurabindo Pillai /** 3285b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3286b04cb192SNicholas Kazlauskas */ 3287b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3288b04cb192SNicholas Kazlauskas 3289b04cb192SNicholas Kazlauskas /** 3290b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3291b04cb192SNicholas Kazlauskas */ 3292b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3293b04cb192SNicholas Kazlauskas 3294b04cb192SNicholas Kazlauskas /** 3295b04cb192SNicholas Kazlauskas * Definition of DMUB_CMD__PANEL_CNTL commands. 3296b04cb192SNicholas Kazlauskas */ 3297b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl panel_cntl; 32981a595f28SAnthony Koo /** 32991a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 33001a595f28SAnthony Koo */ 3301e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 33021a595f28SAnthony Koo 33031a595f28SAnthony Koo /** 33041a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 33051a595f28SAnthony Koo */ 3306e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 33071a595f28SAnthony Koo 33081a595f28SAnthony Koo /** 33091a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 33101a595f28SAnthony Koo */ 3311e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level abm_set_level; 33121a595f28SAnthony Koo 33131a595f28SAnthony Koo /** 33141a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 33151a595f28SAnthony Koo */ 3316e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 33171a595f28SAnthony Koo 33181a595f28SAnthony Koo /** 33191a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 33201a595f28SAnthony Koo */ 3321e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 33221a595f28SAnthony Koo 33231a595f28SAnthony Koo /** 33241a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 33251a595f28SAnthony Koo */ 332616012806SWyatt Wood struct dmub_rb_cmd_abm_init_config abm_init_config; 33271a595f28SAnthony Koo 33281a595f28SAnthony Koo /** 3329b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 3330b629a824SEric Yang */ 3331b629a824SEric Yang struct dmub_rb_cmd_abm_pause abm_pause; 3332b629a824SEric Yang 3333b629a824SEric Yang /** 33341a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 33351a595f28SAnthony Koo */ 3336d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access dp_aux_access; 33371a595f28SAnthony Koo 33381a595f28SAnthony Koo /** 3339592a6318SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3340592a6318SAnthony Koo */ 3341592a6318SAnthony Koo struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3342592a6318SAnthony Koo 3343592a6318SAnthony Koo /** 3344592a6318SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 33451a595f28SAnthony Koo */ 334634ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3347b09c1fffSLeo (Hanghong) Ma 3348b09c1fffSLeo (Hanghong) Ma /** 3349b09c1fffSLeo (Hanghong) Ma * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3350b09c1fffSLeo (Hanghong) Ma */ 3351b09c1fffSLeo (Hanghong) Ma struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3352592a6318SAnthony Koo struct dmub_rb_cmd_drr_update drr_update; 335300fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 335400fa7f03SRodrigo Siqueira 33551a595f28SAnthony Koo /** 33561a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 33571a595f28SAnthony Koo */ 33581a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control lvtma_control; 3359021eaef8SAnthony Koo /** 336041f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 336141f91315SNicholas Kazlauskas */ 336241f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 336341f91315SNicholas Kazlauskas /** 336476724b76SJimmy Kizito * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 336576724b76SJimmy Kizito */ 336676724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 336776724b76SJimmy Kizito /** 336871af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 336971af9d46SMeenakshikumar Somasundaram */ 337071af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access set_config_access; 337171af9d46SMeenakshikumar Somasundaram /** 3372139a3311SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3373139a3311SMeenakshikumar Somasundaram */ 3374139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3375139a3311SMeenakshikumar Somasundaram /** 3376021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 3377021eaef8SAnthony Koo */ 3378021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea edid_cea; 3379c595fb05SWenjing Liu /** 3380c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3381c595fb05SWenjing Liu */ 3382c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3383ea5a4db9SAnthony Koo 3384ea5a4db9SAnthony Koo /** 3385ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3386ea5a4db9SAnthony Koo */ 3387ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state query_hpd; 33886f4f8ff5SMeenakshikumar Somasundaram /** 3389c0459bddSAlan Liu * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3390c0459bddSAlan Liu */ 3391c0459bddSAlan Liu struct dmub_rb_cmd_secure_display secure_display; 33921fb695d9SAnthony Koo 3393c0459bddSAlan Liu /** 33946f4f8ff5SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 33956f4f8ff5SMeenakshikumar Somasundaram */ 33966f4f8ff5SMeenakshikumar Somasundaram struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 33977c008829SNicholas Kazlauskas }; 33987c008829SNicholas Kazlauskas 3399592a6318SAnthony Koo /** 3400592a6318SAnthony Koo * union dmub_rb_out_cmd - Outbox command 3401592a6318SAnthony Koo */ 3402d9beecfcSAnthony Koo union dmub_rb_out_cmd { 3403592a6318SAnthony Koo /** 3404592a6318SAnthony Koo * Parameters common to every command. 3405592a6318SAnthony Koo */ 3406d9beecfcSAnthony Koo struct dmub_rb_cmd_common cmd_common; 3407592a6318SAnthony Koo /** 3408592a6318SAnthony Koo * AUX reply command. 3409592a6318SAnthony Koo */ 3410d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3411592a6318SAnthony Koo /** 3412592a6318SAnthony Koo * HPD notify command. 3413592a6318SAnthony Koo */ 3414d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 341571af9d46SMeenakshikumar Somasundaram /** 341671af9d46SMeenakshikumar Somasundaram * SET_CONFIG reply command. 341771af9d46SMeenakshikumar Somasundaram */ 341871af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3419d9beecfcSAnthony Koo }; 34207c008829SNicholas Kazlauskas #pragma pack(pop) 34217c008829SNicholas Kazlauskas 342284034ad4SAnthony Koo 342384034ad4SAnthony Koo //============================================================================== 342484034ad4SAnthony Koo //</DMUB_CMD>=================================================================== 342584034ad4SAnthony Koo //============================================================================== 342684034ad4SAnthony Koo //< DMUB_RB>==================================================================== 342784034ad4SAnthony Koo //============================================================================== 342884034ad4SAnthony Koo 342984034ad4SAnthony Koo #if defined(__cplusplus) 343084034ad4SAnthony Koo extern "C" { 343184034ad4SAnthony Koo #endif 343284034ad4SAnthony Koo 3433592a6318SAnthony Koo /** 3434592a6318SAnthony Koo * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3435592a6318SAnthony Koo */ 343684034ad4SAnthony Koo struct dmub_rb_init_params { 3437592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 3438592a6318SAnthony Koo void *base_address; /**< CPU base address for ring's data */ 3439592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3440592a6318SAnthony Koo uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3441592a6318SAnthony Koo uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 344284034ad4SAnthony Koo }; 344384034ad4SAnthony Koo 3444592a6318SAnthony Koo /** 3445592a6318SAnthony Koo * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3446592a6318SAnthony Koo */ 344784034ad4SAnthony Koo struct dmub_rb { 3448592a6318SAnthony Koo void *base_address; /**< CPU address for the ring's data */ 3449592a6318SAnthony Koo uint32_t rptr; /**< Read pointer for consumer in bytes */ 3450592a6318SAnthony Koo uint32_t wrpt; /**< Write pointer for producer in bytes */ 3451592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 345284034ad4SAnthony Koo 3453592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 3454592a6318SAnthony Koo void *dmub; /**< Pointer to the DMUB interface */ 345584034ad4SAnthony Koo }; 345684034ad4SAnthony Koo 3457592a6318SAnthony Koo /** 3458592a6318SAnthony Koo * @brief Checks if the ringbuffer is empty. 3459592a6318SAnthony Koo * 3460592a6318SAnthony Koo * @param rb DMUB Ringbuffer 3461592a6318SAnthony Koo * @return true if empty 3462592a6318SAnthony Koo * @return false otherwise 3463592a6318SAnthony Koo */ 346484034ad4SAnthony Koo static inline bool dmub_rb_empty(struct dmub_rb *rb) 346584034ad4SAnthony Koo { 346684034ad4SAnthony Koo return (rb->wrpt == rb->rptr); 346784034ad4SAnthony Koo } 346884034ad4SAnthony Koo 3469592a6318SAnthony Koo /** 3470592a6318SAnthony Koo * @brief Checks if the ringbuffer is full 3471592a6318SAnthony Koo * 3472592a6318SAnthony Koo * @param rb DMUB Ringbuffer 3473592a6318SAnthony Koo * @return true if full 3474592a6318SAnthony Koo * @return false otherwise 3475592a6318SAnthony Koo */ 347684034ad4SAnthony Koo static inline bool dmub_rb_full(struct dmub_rb *rb) 347784034ad4SAnthony Koo { 347884034ad4SAnthony Koo uint32_t data_count; 347984034ad4SAnthony Koo 348084034ad4SAnthony Koo if (rb->wrpt >= rb->rptr) 348184034ad4SAnthony Koo data_count = rb->wrpt - rb->rptr; 348284034ad4SAnthony Koo else 348384034ad4SAnthony Koo data_count = rb->capacity - (rb->rptr - rb->wrpt); 348484034ad4SAnthony Koo 348584034ad4SAnthony Koo return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 348684034ad4SAnthony Koo } 348784034ad4SAnthony Koo 3488592a6318SAnthony Koo /** 3489592a6318SAnthony Koo * @brief Pushes a command into the ringbuffer 3490592a6318SAnthony Koo * 3491592a6318SAnthony Koo * @param rb DMUB ringbuffer 3492592a6318SAnthony Koo * @param cmd The command to push 3493592a6318SAnthony Koo * @return true if the ringbuffer was not full 3494592a6318SAnthony Koo * @return false otherwise 3495592a6318SAnthony Koo */ 349684034ad4SAnthony Koo static inline bool dmub_rb_push_front(struct dmub_rb *rb, 349784034ad4SAnthony Koo const union dmub_rb_cmd *cmd) 349884034ad4SAnthony Koo { 34993f232a0fSAnthony Koo uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 35003a9d5b0bSAnthony Koo const uint64_t *src = (const uint64_t *)cmd; 35013a9d5b0bSAnthony Koo uint8_t i; 350284034ad4SAnthony Koo 350384034ad4SAnthony Koo if (dmub_rb_full(rb)) 350484034ad4SAnthony Koo return false; 350584034ad4SAnthony Koo 350684034ad4SAnthony Koo // copying data 35073a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 35083a9d5b0bSAnthony Koo *dst++ = *src++; 350984034ad4SAnthony Koo 351084034ad4SAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 351184034ad4SAnthony Koo 351284034ad4SAnthony Koo if (rb->wrpt >= rb->capacity) 351384034ad4SAnthony Koo rb->wrpt %= rb->capacity; 351484034ad4SAnthony Koo 351584034ad4SAnthony Koo return true; 351684034ad4SAnthony Koo } 351784034ad4SAnthony Koo 3518592a6318SAnthony Koo /** 3519592a6318SAnthony Koo * @brief Pushes a command into the DMUB outbox ringbuffer 3520592a6318SAnthony Koo * 3521592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 3522592a6318SAnthony Koo * @param cmd Outbox command 3523592a6318SAnthony Koo * @return true if not full 3524592a6318SAnthony Koo * @return false otherwise 3525592a6318SAnthony Koo */ 3526d9beecfcSAnthony Koo static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3527d9beecfcSAnthony Koo const union dmub_rb_out_cmd *cmd) 3528d9beecfcSAnthony Koo { 3529d9beecfcSAnthony Koo uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3530d459b79bSAnthony Koo const uint8_t *src = (const uint8_t *)cmd; 3531d9beecfcSAnthony Koo 3532d9beecfcSAnthony Koo if (dmub_rb_full(rb)) 3533d9beecfcSAnthony Koo return false; 3534d9beecfcSAnthony Koo 3535d9beecfcSAnthony Koo dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3536d9beecfcSAnthony Koo 3537d9beecfcSAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 3538d9beecfcSAnthony Koo 3539d9beecfcSAnthony Koo if (rb->wrpt >= rb->capacity) 3540d9beecfcSAnthony Koo rb->wrpt %= rb->capacity; 3541d9beecfcSAnthony Koo 3542d9beecfcSAnthony Koo return true; 3543d9beecfcSAnthony Koo } 3544d9beecfcSAnthony Koo 3545592a6318SAnthony Koo /** 3546592a6318SAnthony Koo * @brief Returns the next unprocessed command in the ringbuffer. 3547592a6318SAnthony Koo * 3548592a6318SAnthony Koo * @param rb DMUB ringbuffer 3549592a6318SAnthony Koo * @param cmd The command to return 3550592a6318SAnthony Koo * @return true if not empty 3551592a6318SAnthony Koo * @return false otherwise 3552592a6318SAnthony Koo */ 355384034ad4SAnthony Koo static inline bool dmub_rb_front(struct dmub_rb *rb, 355434ba432cSAnthony Koo union dmub_rb_cmd **cmd) 355584034ad4SAnthony Koo { 355634ba432cSAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 355784034ad4SAnthony Koo 355884034ad4SAnthony Koo if (dmub_rb_empty(rb)) 355984034ad4SAnthony Koo return false; 356084034ad4SAnthony Koo 356134ba432cSAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 356284034ad4SAnthony Koo 356384034ad4SAnthony Koo return true; 356484034ad4SAnthony Koo } 356584034ad4SAnthony Koo 3566592a6318SAnthony Koo /** 35670b51e7e8SAnthony Koo * @brief Determines the next ringbuffer offset. 35680b51e7e8SAnthony Koo * 35690b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 35700b51e7e8SAnthony Koo * @param num_cmds Number of commands 35710b51e7e8SAnthony Koo * @param next_rptr The next offset in the ringbuffer 35720b51e7e8SAnthony Koo */ 35730b51e7e8SAnthony Koo static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 35740b51e7e8SAnthony Koo uint32_t num_cmds, 35750b51e7e8SAnthony Koo uint32_t *next_rptr) 35760b51e7e8SAnthony Koo { 35770b51e7e8SAnthony Koo *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 35780b51e7e8SAnthony Koo 35790b51e7e8SAnthony Koo if (*next_rptr >= rb->capacity) 35800b51e7e8SAnthony Koo *next_rptr %= rb->capacity; 35810b51e7e8SAnthony Koo } 35820b51e7e8SAnthony Koo 35830b51e7e8SAnthony Koo /** 35840b51e7e8SAnthony Koo * @brief Returns a pointer to a command in the inbox. 35850b51e7e8SAnthony Koo * 35860b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 35870b51e7e8SAnthony Koo * @param cmd The inbox command to return 35880b51e7e8SAnthony Koo * @param rptr The ringbuffer offset 35890b51e7e8SAnthony Koo * @return true if not empty 35900b51e7e8SAnthony Koo * @return false otherwise 35910b51e7e8SAnthony Koo */ 35920b51e7e8SAnthony Koo static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 35930b51e7e8SAnthony Koo union dmub_rb_cmd **cmd, 35940b51e7e8SAnthony Koo uint32_t rptr) 35950b51e7e8SAnthony Koo { 35960b51e7e8SAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 35970b51e7e8SAnthony Koo 35980b51e7e8SAnthony Koo if (dmub_rb_empty(rb)) 35990b51e7e8SAnthony Koo return false; 36000b51e7e8SAnthony Koo 36010b51e7e8SAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 36020b51e7e8SAnthony Koo 36030b51e7e8SAnthony Koo return true; 36040b51e7e8SAnthony Koo } 36050b51e7e8SAnthony Koo 36060b51e7e8SAnthony Koo /** 3607592a6318SAnthony Koo * @brief Returns the next unprocessed command in the outbox. 3608592a6318SAnthony Koo * 3609592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 3610592a6318SAnthony Koo * @param cmd The outbox command to return 3611592a6318SAnthony Koo * @return true if not empty 3612592a6318SAnthony Koo * @return false otherwise 3613592a6318SAnthony Koo */ 3614d9beecfcSAnthony Koo static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3615d9beecfcSAnthony Koo union dmub_rb_out_cmd *cmd) 3616d9beecfcSAnthony Koo { 36173f232a0fSAnthony Koo const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 36183a9d5b0bSAnthony Koo uint64_t *dst = (uint64_t *)cmd; 36193a9d5b0bSAnthony Koo uint8_t i; 3620d9beecfcSAnthony Koo 3621d9beecfcSAnthony Koo if (dmub_rb_empty(rb)) 3622d9beecfcSAnthony Koo return false; 3623d9beecfcSAnthony Koo 3624d9beecfcSAnthony Koo // copying data 36253a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 36263a9d5b0bSAnthony Koo *dst++ = *src++; 3627d9beecfcSAnthony Koo 3628d9beecfcSAnthony Koo return true; 3629d9beecfcSAnthony Koo } 3630d9beecfcSAnthony Koo 3631592a6318SAnthony Koo /** 3632592a6318SAnthony Koo * @brief Removes the front entry in the ringbuffer. 3633592a6318SAnthony Koo * 3634592a6318SAnthony Koo * @param rb DMUB ringbuffer 3635592a6318SAnthony Koo * @return true if the command was removed 3636592a6318SAnthony Koo * @return false if there were no commands 3637592a6318SAnthony Koo */ 363884034ad4SAnthony Koo static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 363984034ad4SAnthony Koo { 364084034ad4SAnthony Koo if (dmub_rb_empty(rb)) 364184034ad4SAnthony Koo return false; 364284034ad4SAnthony Koo 364384034ad4SAnthony Koo rb->rptr += DMUB_RB_CMD_SIZE; 364484034ad4SAnthony Koo 364584034ad4SAnthony Koo if (rb->rptr >= rb->capacity) 364684034ad4SAnthony Koo rb->rptr %= rb->capacity; 364784034ad4SAnthony Koo 364884034ad4SAnthony Koo return true; 364984034ad4SAnthony Koo } 365084034ad4SAnthony Koo 3651592a6318SAnthony Koo /** 3652592a6318SAnthony Koo * @brief Flushes commands in the ringbuffer to framebuffer memory. 3653592a6318SAnthony Koo * 3654592a6318SAnthony Koo * Avoids a race condition where DMCUB accesses memory while 3655592a6318SAnthony Koo * there are still writes in flight to framebuffer. 3656592a6318SAnthony Koo * 3657592a6318SAnthony Koo * @param rb DMUB ringbuffer 3658592a6318SAnthony Koo */ 365984034ad4SAnthony Koo static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 366084034ad4SAnthony Koo { 366184034ad4SAnthony Koo uint32_t rptr = rb->rptr; 366284034ad4SAnthony Koo uint32_t wptr = rb->wrpt; 366384034ad4SAnthony Koo 366484034ad4SAnthony Koo while (rptr != wptr) { 36657da7b02eSAashish Sharma uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 36663a9d5b0bSAnthony Koo uint8_t i; 366784034ad4SAnthony Koo 366823da6e0fSMaíra Canal /* Don't remove this. 366923da6e0fSMaíra Canal * The contents need to actually be read from the ring buffer 367023da6e0fSMaíra Canal * for this function to be effective. 367123da6e0fSMaíra Canal */ 36723a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 36737da7b02eSAashish Sharma (void)READ_ONCE(*data++); 367484034ad4SAnthony Koo 367584034ad4SAnthony Koo rptr += DMUB_RB_CMD_SIZE; 367684034ad4SAnthony Koo if (rptr >= rb->capacity) 367784034ad4SAnthony Koo rptr %= rb->capacity; 367884034ad4SAnthony Koo } 367984034ad4SAnthony Koo } 368084034ad4SAnthony Koo 3681592a6318SAnthony Koo /** 3682592a6318SAnthony Koo * @brief Initializes a DMCUB ringbuffer 3683592a6318SAnthony Koo * 3684592a6318SAnthony Koo * @param rb DMUB ringbuffer 3685592a6318SAnthony Koo * @param init_params initial configuration for the ringbuffer 3686592a6318SAnthony Koo */ 368784034ad4SAnthony Koo static inline void dmub_rb_init(struct dmub_rb *rb, 368884034ad4SAnthony Koo struct dmub_rb_init_params *init_params) 368984034ad4SAnthony Koo { 369084034ad4SAnthony Koo rb->base_address = init_params->base_address; 369184034ad4SAnthony Koo rb->capacity = init_params->capacity; 369284034ad4SAnthony Koo rb->rptr = init_params->read_ptr; 369384034ad4SAnthony Koo rb->wrpt = init_params->write_ptr; 369484034ad4SAnthony Koo } 369584034ad4SAnthony Koo 3696592a6318SAnthony Koo /** 3697592a6318SAnthony Koo * @brief Copies output data from in/out commands into the given command. 3698592a6318SAnthony Koo * 3699592a6318SAnthony Koo * @param rb DMUB ringbuffer 3700592a6318SAnthony Koo * @param cmd Command to copy data into 3701592a6318SAnthony Koo */ 370234ba432cSAnthony Koo static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 370334ba432cSAnthony Koo union dmub_rb_cmd *cmd) 370434ba432cSAnthony Koo { 370534ba432cSAnthony Koo // Copy rb entry back into command 370634ba432cSAnthony Koo uint8_t *rd_ptr = (rb->rptr == 0) ? 370734ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 370834ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 370934ba432cSAnthony Koo 371034ba432cSAnthony Koo dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 371134ba432cSAnthony Koo } 371234ba432cSAnthony Koo 371384034ad4SAnthony Koo #if defined(__cplusplus) 371484034ad4SAnthony Koo } 371584034ad4SAnthony Koo #endif 371684034ad4SAnthony Koo 371784034ad4SAnthony Koo //============================================================================== 371884034ad4SAnthony Koo //</DMUB_RB>==================================================================== 371984034ad4SAnthony Koo //============================================================================== 372084034ad4SAnthony Koo 37217c008829SNicholas Kazlauskas #endif /* _DMUB_CMD_H_ */ 3722