17c008829SNicholas Kazlauskas /* 27c008829SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 37c008829SNicholas Kazlauskas * 47c008829SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 57c008829SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 67c008829SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 77c008829SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87c008829SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 97c008829SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 107c008829SNicholas Kazlauskas * 117c008829SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 127c008829SNicholas Kazlauskas * all copies or substantial portions of the Software. 137c008829SNicholas Kazlauskas * 147c008829SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157c008829SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167c008829SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177c008829SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187c008829SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197c008829SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207c008829SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 217c008829SNicholas Kazlauskas * 227c008829SNicholas Kazlauskas * Authors: AMD 237c008829SNicholas Kazlauskas * 247c008829SNicholas Kazlauskas */ 257c008829SNicholas Kazlauskas 265624c345SAnthony Koo #ifndef DMUB_CMD_H 275624c345SAnthony Koo #define DMUB_CMD_H 287c008829SNicholas Kazlauskas 298b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 308b19a4e3SAnthony Koo #include "dmub_fw_types.h" 318b19a4e3SAnthony Koo #include "include_legacy/atomfirmware.h" 328b19a4e3SAnthony Koo 338b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) 348b19a4e3SAnthony Koo #include <string.h> 358b19a4e3SAnthony Koo #endif 368b19a4e3SAnthony Koo #else 378b19a4e3SAnthony Koo 3884034ad4SAnthony Koo #include <asm/byteorder.h> 3984034ad4SAnthony Koo #include <linux/types.h> 4084034ad4SAnthony Koo #include <linux/string.h> 4184034ad4SAnthony Koo #include <linux/delay.h> 4284034ad4SAnthony Koo 437c008829SNicholas Kazlauskas #include "atomfirmware.h" 4422aa5614SYongqiang Sun 458b19a4e3SAnthony Koo #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 468b19a4e3SAnthony Koo 478598a722SAnthony Koo /* Firmware versioning. */ 488598a722SAnthony Koo #ifdef DMUB_EXPOSE_VERSION 49bf72ca73SAnthony Koo #define DMUB_FW_VERSION_GIT_HASH 0xeb0940cc 50b2265774SAnthony Koo #define DMUB_FW_VERSION_MAJOR 0 518598a722SAnthony Koo #define DMUB_FW_VERSION_MINOR 0 52bf72ca73SAnthony Koo #define DMUB_FW_VERSION_REVISION 85 53ded750e6SAnthony Koo #define DMUB_FW_VERSION_TEST 0 54ded750e6SAnthony Koo #define DMUB_FW_VERSION_VBIOS 0 55ded750e6SAnthony Koo #define DMUB_FW_VERSION_HOTFIX 0 56ded750e6SAnthony Koo #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 57ded750e6SAnthony Koo ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 58ded750e6SAnthony Koo ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 59ded750e6SAnthony Koo ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 60ded750e6SAnthony Koo ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 61ded750e6SAnthony Koo (DMUB_FW_VERSION_HOTFIX & 0x3F)) 62ded750e6SAnthony Koo 638598a722SAnthony Koo #endif 6484034ad4SAnthony Koo 6584034ad4SAnthony Koo //<DMUB_TYPES>================================================================== 6684034ad4SAnthony Koo /* Basic type definitions. */ 6784034ad4SAnthony Koo 688b19a4e3SAnthony Koo #define __forceinline inline 698b19a4e3SAnthony Koo 701a595f28SAnthony Koo /** 711a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled gradually 721a595f28SAnthony Koo * by slowly reversing all backlight programming and pixel compensation. 731a595f28SAnthony Koo */ 7484034ad4SAnthony Koo #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 751a595f28SAnthony Koo 761a595f28SAnthony Koo /** 771a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 781a595f28SAnthony Koo * and undo all backlight programming and pixel compensation. 791a595f28SAnthony Koo */ 8084034ad4SAnthony Koo #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 811a595f28SAnthony Koo 821a595f28SAnthony Koo /** 831a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 841a595f28SAnthony Koo * and keep the current backlight programming and pixel compensation. 851a595f28SAnthony Koo */ 86d9beecfcSAnthony Koo #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 871a595f28SAnthony Koo 881a595f28SAnthony Koo /** 891a595f28SAnthony Koo * Flag from driver to set the current ABM pipe index or ABM operating level. 901a595f28SAnthony Koo */ 9184034ad4SAnthony Koo #define SET_ABM_PIPE_NORMAL 1 9284034ad4SAnthony Koo 931a595f28SAnthony Koo /** 941a595f28SAnthony Koo * Number of ambient light levels in ABM algorithm. 951a595f28SAnthony Koo */ 961a595f28SAnthony Koo #define NUM_AMBI_LEVEL 5 971a595f28SAnthony Koo 981a595f28SAnthony Koo /** 991a595f28SAnthony Koo * Number of operating/aggression levels in ABM algorithm. 1001a595f28SAnthony Koo */ 1011a595f28SAnthony Koo #define NUM_AGGR_LEVEL 4 1021a595f28SAnthony Koo 1031a595f28SAnthony Koo /** 1041a595f28SAnthony Koo * Number of segments in the gamma curve. 1051a595f28SAnthony Koo */ 1061a595f28SAnthony Koo #define NUM_POWER_FN_SEGS 8 1071a595f28SAnthony Koo 1081a595f28SAnthony Koo /** 1091a595f28SAnthony Koo * Number of segments in the backlight curve. 1101a595f28SAnthony Koo */ 1111a595f28SAnthony Koo #define NUM_BL_CURVE_SEGS 16 1121a595f28SAnthony Koo 11384034ad4SAnthony Koo /* Maximum number of streams on any ASIC. */ 11484034ad4SAnthony Koo #define DMUB_MAX_STREAMS 6 11584034ad4SAnthony Koo 11684034ad4SAnthony Koo /* Maximum number of planes on any ASIC. */ 11784034ad4SAnthony Koo #define DMUB_MAX_PLANES 6 11884034ad4SAnthony Koo 11970732504SYongqiang Sun /* Trace buffer offset for entry */ 12070732504SYongqiang Sun #define TRACE_BUFFER_ENTRY_OFFSET 16 12170732504SYongqiang Sun 122592a6318SAnthony Koo /** 123f56c837aSMikita Lipski * 124f56c837aSMikita Lipski * PSR control version legacy 125f56c837aSMikita Lipski */ 126f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 127f56c837aSMikita Lipski /** 128f56c837aSMikita Lipski * PSR control version with multi edp support 129f56c837aSMikita Lipski */ 130f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 131f56c837aSMikita Lipski 132f56c837aSMikita Lipski 133f56c837aSMikita Lipski /** 13463de4f04SJake Wang * ABM control version legacy 135e922057bSJake Wang */ 13663de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 137e922057bSJake Wang 138e922057bSJake Wang /** 13963de4f04SJake Wang * ABM control version with multi edp support 140e922057bSJake Wang */ 14163de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 142e922057bSJake Wang 143e922057bSJake Wang /** 144592a6318SAnthony Koo * Physical framebuffer address location, 64-bit. 145592a6318SAnthony Koo */ 14684034ad4SAnthony Koo #ifndef PHYSICAL_ADDRESS_LOC 14784034ad4SAnthony Koo #define PHYSICAL_ADDRESS_LOC union large_integer 14884034ad4SAnthony Koo #endif 14984034ad4SAnthony Koo 150592a6318SAnthony Koo /** 151592a6318SAnthony Koo * OS/FW agnostic memcpy 152592a6318SAnthony Koo */ 15384034ad4SAnthony Koo #ifndef dmub_memcpy 15484034ad4SAnthony Koo #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 15584034ad4SAnthony Koo #endif 15684034ad4SAnthony Koo 157592a6318SAnthony Koo /** 158592a6318SAnthony Koo * OS/FW agnostic memset 159592a6318SAnthony Koo */ 16084034ad4SAnthony Koo #ifndef dmub_memset 16184034ad4SAnthony Koo #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 16284034ad4SAnthony Koo #endif 16384034ad4SAnthony Koo 164d9beecfcSAnthony Koo #if defined(__cplusplus) 165d9beecfcSAnthony Koo extern "C" { 166d9beecfcSAnthony Koo #endif 167d9beecfcSAnthony Koo 168592a6318SAnthony Koo /** 169592a6318SAnthony Koo * OS/FW agnostic udelay 170592a6318SAnthony Koo */ 17184034ad4SAnthony Koo #ifndef dmub_udelay 17284034ad4SAnthony Koo #define dmub_udelay(microseconds) udelay(microseconds) 17384034ad4SAnthony Koo #endif 17484034ad4SAnthony Koo 175592a6318SAnthony Koo /** 1760b51e7e8SAnthony Koo * Number of nanoseconds per DMUB tick. 1770b51e7e8SAnthony Koo * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default. 1780b51e7e8SAnthony Koo * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true. 1790b51e7e8SAnthony Koo */ 1800b51e7e8SAnthony Koo #define NS_PER_DMUB_TICK 10 1810b51e7e8SAnthony Koo 1820b51e7e8SAnthony Koo /** 183592a6318SAnthony Koo * union dmub_addr - DMUB physical/virtual 64-bit address. 184592a6318SAnthony Koo */ 18584034ad4SAnthony Koo union dmub_addr { 18684034ad4SAnthony Koo struct { 187592a6318SAnthony Koo uint32_t low_part; /**< Lower 32 bits */ 188592a6318SAnthony Koo uint32_t high_part; /**< Upper 32 bits */ 189592a6318SAnthony Koo } u; /*<< Low/high bit access */ 190592a6318SAnthony Koo uint64_t quad_part; /*<< 64 bit address */ 19184034ad4SAnthony Koo }; 19284034ad4SAnthony Koo 1931a595f28SAnthony Koo /** 1941a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 1951a595f28SAnthony Koo */ 19684034ad4SAnthony Koo union dmub_psr_debug_flags { 1971a595f28SAnthony Koo /** 1981a595f28SAnthony Koo * Debug flags. 1991a595f28SAnthony Koo */ 20084034ad4SAnthony Koo struct { 2011a595f28SAnthony Koo /** 2021a595f28SAnthony Koo * Enable visual confirm in FW. 2031a595f28SAnthony Koo */ 204447f3d0fSAnthony Koo uint32_t visual_confirm : 1; 2051a595f28SAnthony Koo /** 2061a595f28SAnthony Koo * Use HW Lock Mgr object to do HW locking in FW. 2071a595f28SAnthony Koo */ 208447f3d0fSAnthony Koo uint32_t use_hw_lock_mgr : 1; 2091a595f28SAnthony Koo 2101a595f28SAnthony Koo /** 2111a595f28SAnthony Koo * Unused. 2121a595f28SAnthony Koo * TODO: Remove. 2131a595f28SAnthony Koo */ 2148b3f6b98SAnthony Koo uint32_t log_line_nums : 1; 21584034ad4SAnthony Koo } bitfields; 21684034ad4SAnthony Koo 2171a595f28SAnthony Koo /** 2181a595f28SAnthony Koo * Union for debug flags. 2191a595f28SAnthony Koo */ 220447f3d0fSAnthony Koo uint32_t u32All; 22184034ad4SAnthony Koo }; 22284034ad4SAnthony Koo 2231a595f28SAnthony Koo /** 2241a595f28SAnthony Koo * DMUB feature capabilities. 2251a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2261a595f28SAnthony Koo */ 22734ba432cSAnthony Koo struct dmub_feature_caps { 2281a595f28SAnthony Koo /** 2291a595f28SAnthony Koo * Max PSR version supported by FW. 2301a595f28SAnthony Koo */ 23134ba432cSAnthony Koo uint8_t psr; 23234ba432cSAnthony Koo uint8_t reserved[7]; 23334ba432cSAnthony Koo }; 23434ba432cSAnthony Koo 23584034ad4SAnthony Koo #if defined(__cplusplus) 23684034ad4SAnthony Koo } 23784034ad4SAnthony Koo #endif 23884034ad4SAnthony Koo 23984034ad4SAnthony Koo //============================================================================== 24084034ad4SAnthony Koo //</DMUB_TYPES>================================================================= 24184034ad4SAnthony Koo //============================================================================== 24284034ad4SAnthony Koo //< DMUB_META>================================================================== 24384034ad4SAnthony Koo //============================================================================== 24484034ad4SAnthony Koo #pragma pack(push, 1) 24584034ad4SAnthony Koo 24684034ad4SAnthony Koo /* Magic value for identifying dmub_fw_meta_info */ 24784034ad4SAnthony Koo #define DMUB_FW_META_MAGIC 0x444D5542 24884034ad4SAnthony Koo 24984034ad4SAnthony Koo /* Offset from the end of the file to the dmub_fw_meta_info */ 25084034ad4SAnthony Koo #define DMUB_FW_META_OFFSET 0x24 25184034ad4SAnthony Koo 25284034ad4SAnthony Koo /** 25384034ad4SAnthony Koo * struct dmub_fw_meta_info - metadata associated with fw binary 25484034ad4SAnthony Koo * 25584034ad4SAnthony Koo * NOTE: This should be considered a stable API. Fields should 25684034ad4SAnthony Koo * not be repurposed or reordered. New fields should be 25784034ad4SAnthony Koo * added instead to extend the structure. 25884034ad4SAnthony Koo * 25984034ad4SAnthony Koo * @magic_value: magic value identifying DMUB firmware meta info 26084034ad4SAnthony Koo * @fw_region_size: size of the firmware state region 26184034ad4SAnthony Koo * @trace_buffer_size: size of the tracebuffer region 26284034ad4SAnthony Koo * @fw_version: the firmware version information 263b2265774SAnthony Koo * @dal_fw: 1 if the firmware is DAL 26484034ad4SAnthony Koo */ 26584034ad4SAnthony Koo struct dmub_fw_meta_info { 266592a6318SAnthony Koo uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 267592a6318SAnthony Koo uint32_t fw_region_size; /**< size of the firmware state region */ 268592a6318SAnthony Koo uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 269592a6318SAnthony Koo uint32_t fw_version; /**< the firmware version information */ 270592a6318SAnthony Koo uint8_t dal_fw; /**< 1 if the firmware is DAL */ 271592a6318SAnthony Koo uint8_t reserved[3]; /**< padding bits */ 27284034ad4SAnthony Koo }; 27384034ad4SAnthony Koo 274592a6318SAnthony Koo /** 275592a6318SAnthony Koo * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 276592a6318SAnthony Koo */ 27784034ad4SAnthony Koo union dmub_fw_meta { 278592a6318SAnthony Koo struct dmub_fw_meta_info info; /**< metadata info */ 279592a6318SAnthony Koo uint8_t reserved[64]; /**< padding bits */ 28084034ad4SAnthony Koo }; 28184034ad4SAnthony Koo 28284034ad4SAnthony Koo #pragma pack(pop) 283788408b7SAnthony Koo 28484034ad4SAnthony Koo //============================================================================== 2856b66208fSYongqiang Sun //< DMUB Trace Buffer>================================================================ 2866b66208fSYongqiang Sun //============================================================================== 287592a6318SAnthony Koo /** 288592a6318SAnthony Koo * dmub_trace_code_t - firmware trace code, 32-bits 289592a6318SAnthony Koo */ 2906b66208fSYongqiang Sun typedef uint32_t dmub_trace_code_t; 2916b66208fSYongqiang Sun 292592a6318SAnthony Koo /** 293592a6318SAnthony Koo * struct dmcub_trace_buf_entry - Firmware trace entry 294592a6318SAnthony Koo */ 2956b66208fSYongqiang Sun struct dmcub_trace_buf_entry { 296592a6318SAnthony Koo dmub_trace_code_t trace_code; /**< trace code for the event */ 297592a6318SAnthony Koo uint32_t tick_count; /**< the tick count at time of trace */ 298592a6318SAnthony Koo uint32_t param0; /**< trace defined parameter 0 */ 299592a6318SAnthony Koo uint32_t param1; /**< trace defined parameter 1 */ 3006b66208fSYongqiang Sun }; 3016b66208fSYongqiang Sun 3026b66208fSYongqiang Sun //============================================================================== 303788408b7SAnthony Koo //< DMUB_STATUS>================================================================ 304788408b7SAnthony Koo //============================================================================== 305788408b7SAnthony Koo 306788408b7SAnthony Koo /** 307788408b7SAnthony Koo * DMCUB scratch registers can be used to determine firmware status. 308788408b7SAnthony Koo * Current scratch register usage is as follows: 309788408b7SAnthony Koo * 310492dd8a8SAnthony Koo * SCRATCH0: FW Boot Status register 311021eaef8SAnthony Koo * SCRATCH5: LVTMA Status Register 312492dd8a8SAnthony Koo * SCRATCH15: FW Boot Options register 313788408b7SAnthony Koo */ 314788408b7SAnthony Koo 315592a6318SAnthony Koo /** 316592a6318SAnthony Koo * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 317592a6318SAnthony Koo */ 318492dd8a8SAnthony Koo union dmub_fw_boot_status { 319492dd8a8SAnthony Koo struct { 320592a6318SAnthony Koo uint32_t dal_fw : 1; /**< 1 if DAL FW */ 321592a6318SAnthony Koo uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 322592a6318SAnthony Koo uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 323592a6318SAnthony Koo uint32_t restore_required : 1; /**< 1 if driver should call restore */ 32401934c30SAnthony Koo uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 32501934c30SAnthony Koo uint32_t reserved : 1; 32601934c30SAnthony Koo uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 32701934c30SAnthony Koo 328592a6318SAnthony Koo } bits; /**< status bits */ 329592a6318SAnthony Koo uint32_t all; /**< 32-bit access to status bits */ 330492dd8a8SAnthony Koo }; 331492dd8a8SAnthony Koo 332592a6318SAnthony Koo /** 333592a6318SAnthony Koo * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 334592a6318SAnthony Koo */ 335492dd8a8SAnthony Koo enum dmub_fw_boot_status_bit { 336592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 337592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 338592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 339592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 3401e0958bbSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 34101934c30SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 342492dd8a8SAnthony Koo }; 343492dd8a8SAnthony Koo 344021eaef8SAnthony Koo /* Register bit definition for SCRATCH5 */ 345021eaef8SAnthony Koo union dmub_lvtma_status { 346021eaef8SAnthony Koo struct { 347021eaef8SAnthony Koo uint32_t psp_ok : 1; 348021eaef8SAnthony Koo uint32_t edp_on : 1; 349021eaef8SAnthony Koo uint32_t reserved : 30; 350021eaef8SAnthony Koo } bits; 351021eaef8SAnthony Koo uint32_t all; 352021eaef8SAnthony Koo }; 353021eaef8SAnthony Koo 354021eaef8SAnthony Koo enum dmub_lvtma_status_bit { 355021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 356021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 357021eaef8SAnthony Koo }; 358021eaef8SAnthony Koo 359592a6318SAnthony Koo /** 3601e0958bbSAnthony Koo * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 361592a6318SAnthony Koo */ 362492dd8a8SAnthony Koo union dmub_fw_boot_options { 363492dd8a8SAnthony Koo struct { 364592a6318SAnthony Koo uint32_t pemu_env : 1; /**< 1 if PEMU */ 365592a6318SAnthony Koo uint32_t fpga_env : 1; /**< 1 if FPGA */ 366592a6318SAnthony Koo uint32_t optimized_init : 1; /**< 1 if optimized init */ 367592a6318SAnthony Koo uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 368592a6318SAnthony Koo uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 369592a6318SAnthony Koo uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 370b04cb192SNicholas Kazlauskas uint32_t z10_disable: 1; /**< 1 to disable z10 */ 3711e0958bbSAnthony Koo uint32_t reserved2: 1; /**< reserved for an unreleased feature */ 372d459b79bSAnthony Koo uint32_t reserved_unreleased1: 1; /**< reserved for an unreleased feature */ 3731e0958bbSAnthony Koo uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 37439371f7dSMeenakshikumar Somasundaram uint32_t reserved_unreleased2: 1; /**< reserved for an unreleased feature */ 37539371f7dSMeenakshikumar Somasundaram uint32_t reserved : 22; /**< reserved */ 376592a6318SAnthony Koo } bits; /**< boot bits */ 377592a6318SAnthony Koo uint32_t all; /**< 32-bit access to bits */ 378492dd8a8SAnthony Koo }; 379492dd8a8SAnthony Koo 380492dd8a8SAnthony Koo enum dmub_fw_boot_options_bit { 381592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 382592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 383592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 384492dd8a8SAnthony Koo }; 385492dd8a8SAnthony Koo 386788408b7SAnthony Koo //============================================================================== 387788408b7SAnthony Koo //</DMUB_STATUS>================================================================ 38884034ad4SAnthony Koo //============================================================================== 38984034ad4SAnthony Koo //< DMUB_VBIOS>================================================================= 39084034ad4SAnthony Koo //============================================================================== 39184034ad4SAnthony Koo 39284034ad4SAnthony Koo /* 393592a6318SAnthony Koo * enum dmub_cmd_vbios_type - VBIOS commands. 394592a6318SAnthony Koo * 39584034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 39684034ad4SAnthony Koo * Do not reuse or modify IDs. 39784034ad4SAnthony Koo */ 39884034ad4SAnthony Koo enum dmub_cmd_vbios_type { 399592a6318SAnthony Koo /** 400592a6318SAnthony Koo * Configures the DIG encoder. 401592a6318SAnthony Koo */ 40284034ad4SAnthony Koo DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 403592a6318SAnthony Koo /** 404592a6318SAnthony Koo * Controls the PHY. 405592a6318SAnthony Koo */ 40684034ad4SAnthony Koo DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 407592a6318SAnthony Koo /** 408592a6318SAnthony Koo * Sets the pixel clock/symbol clock. 409592a6318SAnthony Koo */ 41084034ad4SAnthony Koo DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 411592a6318SAnthony Koo /** 412592a6318SAnthony Koo * Enables or disables power gating. 413592a6318SAnthony Koo */ 41484034ad4SAnthony Koo DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 4152ac685bfSAnthony Koo DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 41684034ad4SAnthony Koo }; 41784034ad4SAnthony Koo 41884034ad4SAnthony Koo //============================================================================== 41984034ad4SAnthony Koo //</DMUB_VBIOS>================================================================= 42084034ad4SAnthony Koo //============================================================================== 42184034ad4SAnthony Koo //< DMUB_GPINT>================================================================= 42284034ad4SAnthony Koo //============================================================================== 42384034ad4SAnthony Koo 42484034ad4SAnthony Koo /** 42584034ad4SAnthony Koo * The shifts and masks below may alternatively be used to format and read 42684034ad4SAnthony Koo * the command register bits. 42784034ad4SAnthony Koo */ 42884034ad4SAnthony Koo 42984034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 43084034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_SHIFT 0 43184034ad4SAnthony Koo 43284034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 43384034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 43484034ad4SAnthony Koo 43584034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_MASK 0xF 43684034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_SHIFT 28 43784034ad4SAnthony Koo 43884034ad4SAnthony Koo /** 43984034ad4SAnthony Koo * Command responses. 44084034ad4SAnthony Koo */ 44184034ad4SAnthony Koo 442592a6318SAnthony Koo /** 443592a6318SAnthony Koo * Return response for DMUB_GPINT__STOP_FW command. 444592a6318SAnthony Koo */ 44584034ad4SAnthony Koo #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 44684034ad4SAnthony Koo 44784034ad4SAnthony Koo /** 448592a6318SAnthony Koo * union dmub_gpint_data_register - Format for sending a command via the GPINT. 44984034ad4SAnthony Koo */ 45084034ad4SAnthony Koo union dmub_gpint_data_register { 45184034ad4SAnthony Koo struct { 452592a6318SAnthony Koo uint32_t param : 16; /**< 16-bit parameter */ 453592a6318SAnthony Koo uint32_t command_code : 12; /**< GPINT command */ 454592a6318SAnthony Koo uint32_t status : 4; /**< Command status bit */ 455592a6318SAnthony Koo } bits; /**< GPINT bit access */ 456592a6318SAnthony Koo uint32_t all; /**< GPINT 32-bit access */ 45784034ad4SAnthony Koo }; 45884034ad4SAnthony Koo 45984034ad4SAnthony Koo /* 460592a6318SAnthony Koo * enum dmub_gpint_command - GPINT command to DMCUB FW 461592a6318SAnthony Koo * 46284034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 46384034ad4SAnthony Koo * Do not reuse or modify IDs. 46484034ad4SAnthony Koo */ 46584034ad4SAnthony Koo enum dmub_gpint_command { 466592a6318SAnthony Koo /** 467592a6318SAnthony Koo * Invalid command, ignored. 468592a6318SAnthony Koo */ 46984034ad4SAnthony Koo DMUB_GPINT__INVALID_COMMAND = 0, 470592a6318SAnthony Koo /** 471592a6318SAnthony Koo * DESC: Queries the firmware version. 472592a6318SAnthony Koo * RETURN: Firmware version. 473592a6318SAnthony Koo */ 47484034ad4SAnthony Koo DMUB_GPINT__GET_FW_VERSION = 1, 475592a6318SAnthony Koo /** 476592a6318SAnthony Koo * DESC: Halts the firmware. 477592a6318SAnthony Koo * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 478592a6318SAnthony Koo */ 47984034ad4SAnthony Koo DMUB_GPINT__STOP_FW = 2, 4801a595f28SAnthony Koo /** 4811a595f28SAnthony Koo * DESC: Get PSR state from FW. 4821a595f28SAnthony Koo * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 4831a595f28SAnthony Koo */ 48484034ad4SAnthony Koo DMUB_GPINT__GET_PSR_STATE = 7, 48580eba958SAnthony Koo /** 48680eba958SAnthony Koo * DESC: Notifies DMCUB of the currently active streams. 48780eba958SAnthony Koo * ARGS: Stream mask, 1 bit per active stream index. 48880eba958SAnthony Koo */ 48980eba958SAnthony Koo DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 4901a595f28SAnthony Koo /** 4911a595f28SAnthony Koo * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 4921a595f28SAnthony Koo * ARGS: We can measure residency from various points. The argument will specify the residency mode. 4931a595f28SAnthony Koo * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 4941a595f28SAnthony Koo * RETURN: PSR residency in milli-percent. 4951a595f28SAnthony Koo */ 496672251b2SAnthony Koo DMUB_GPINT__PSR_RESIDENCY = 9, 49701934c30SAnthony Koo 49801934c30SAnthony Koo /** 49901934c30SAnthony Koo * DESC: Notifies DMCUB detection is done so detection required can be cleared. 50001934c30SAnthony Koo */ 50101934c30SAnthony Koo DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 50284034ad4SAnthony Koo }; 50384034ad4SAnthony Koo 5040b51e7e8SAnthony Koo /** 5050b51e7e8SAnthony Koo * INBOX0 generic command definition 5060b51e7e8SAnthony Koo */ 5070b51e7e8SAnthony Koo union dmub_inbox0_cmd_common { 5080b51e7e8SAnthony Koo struct { 5090b51e7e8SAnthony Koo uint32_t command_code: 8; /**< INBOX0 command code */ 5100b51e7e8SAnthony Koo uint32_t param: 24; /**< 24-bit parameter */ 5110b51e7e8SAnthony Koo } bits; 5120b51e7e8SAnthony Koo uint32_t all; 5130b51e7e8SAnthony Koo }; 5140b51e7e8SAnthony Koo 5150b51e7e8SAnthony Koo /** 5160b51e7e8SAnthony Koo * INBOX0 hw_lock command definition 5170b51e7e8SAnthony Koo */ 5180b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw { 5190b51e7e8SAnthony Koo struct { 5200b51e7e8SAnthony Koo uint32_t command_code: 8; 5210b51e7e8SAnthony Koo 5220b51e7e8SAnthony Koo /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 5230b51e7e8SAnthony Koo uint32_t hw_lock_client: 1; 5240b51e7e8SAnthony Koo 5250b51e7e8SAnthony Koo /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 5260b51e7e8SAnthony Koo uint32_t otg_inst: 3; 5270b51e7e8SAnthony Koo uint32_t opp_inst: 3; 5280b51e7e8SAnthony Koo uint32_t dig_inst: 3; 5290b51e7e8SAnthony Koo 5300b51e7e8SAnthony Koo /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 5310b51e7e8SAnthony Koo uint32_t lock_pipe: 1; 5320b51e7e8SAnthony Koo uint32_t lock_cursor: 1; 5330b51e7e8SAnthony Koo uint32_t lock_dig: 1; 5340b51e7e8SAnthony Koo uint32_t triple_buffer_lock: 1; 5350b51e7e8SAnthony Koo 5360b51e7e8SAnthony Koo uint32_t lock: 1; /**< Lock */ 5370b51e7e8SAnthony Koo uint32_t should_release: 1; /**< Release */ 5380b51e7e8SAnthony Koo uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ 5390b51e7e8SAnthony Koo } bits; 5400b51e7e8SAnthony Koo uint32_t all; 5410b51e7e8SAnthony Koo }; 5420b51e7e8SAnthony Koo 5430b51e7e8SAnthony Koo union dmub_inbox0_data_register { 5440b51e7e8SAnthony Koo union dmub_inbox0_cmd_common inbox0_cmd_common; 5450b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 5460b51e7e8SAnthony Koo }; 5470b51e7e8SAnthony Koo 5480b51e7e8SAnthony Koo enum dmub_inbox0_command { 5490b51e7e8SAnthony Koo /** 5500b51e7e8SAnthony Koo * DESC: Invalid command, ignored. 5510b51e7e8SAnthony Koo */ 5520b51e7e8SAnthony Koo DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 5530b51e7e8SAnthony Koo /** 5540b51e7e8SAnthony Koo * DESC: Notification to acquire/release HW lock 5550b51e7e8SAnthony Koo * ARGS: 5560b51e7e8SAnthony Koo */ 5570b51e7e8SAnthony Koo DMUB_INBOX0_CMD__HW_LOCK = 1, 5580b51e7e8SAnthony Koo }; 55984034ad4SAnthony Koo //============================================================================== 56084034ad4SAnthony Koo //</DMUB_GPINT>================================================================= 56184034ad4SAnthony Koo //============================================================================== 56284034ad4SAnthony Koo //< DMUB_CMD>=================================================================== 56384034ad4SAnthony Koo //============================================================================== 56484034ad4SAnthony Koo 565592a6318SAnthony Koo /** 566592a6318SAnthony Koo * Size in bytes of each DMUB command. 567592a6318SAnthony Koo */ 5687c008829SNicholas Kazlauskas #define DMUB_RB_CMD_SIZE 64 569592a6318SAnthony Koo 570592a6318SAnthony Koo /** 571592a6318SAnthony Koo * Maximum number of items in the DMUB ringbuffer. 572592a6318SAnthony Koo */ 5737c008829SNicholas Kazlauskas #define DMUB_RB_MAX_ENTRY 128 574592a6318SAnthony Koo 575592a6318SAnthony Koo /** 576592a6318SAnthony Koo * Ringbuffer size in bytes. 577592a6318SAnthony Koo */ 5787c008829SNicholas Kazlauskas #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 579592a6318SAnthony Koo 580592a6318SAnthony Koo /** 581592a6318SAnthony Koo * REG_SET mask for reg offload. 582592a6318SAnthony Koo */ 5837c008829SNicholas Kazlauskas #define REG_SET_MASK 0xFFFF 5847c008829SNicholas Kazlauskas 585d4bbcecbSNicholas Kazlauskas /* 586592a6318SAnthony Koo * enum dmub_cmd_type - DMUB inbox command. 587592a6318SAnthony Koo * 588d4bbcecbSNicholas Kazlauskas * Command IDs should be treated as stable ABI. 589d4bbcecbSNicholas Kazlauskas * Do not reuse or modify IDs. 590d4bbcecbSNicholas Kazlauskas */ 591d4bbcecbSNicholas Kazlauskas enum dmub_cmd_type { 592592a6318SAnthony Koo /** 593592a6318SAnthony Koo * Invalid command. 594592a6318SAnthony Koo */ 595d4bbcecbSNicholas Kazlauskas DMUB_CMD__NULL = 0, 596592a6318SAnthony Koo /** 597592a6318SAnthony Koo * Read modify write register sequence offload. 598592a6318SAnthony Koo */ 599d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 600592a6318SAnthony Koo /** 601592a6318SAnthony Koo * Field update register sequence offload. 602592a6318SAnthony Koo */ 603d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 604592a6318SAnthony Koo /** 605592a6318SAnthony Koo * Burst write sequence offload. 606592a6318SAnthony Koo */ 607d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 608592a6318SAnthony Koo /** 609592a6318SAnthony Koo * Reg wait sequence offload. 610592a6318SAnthony Koo */ 611d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_REG_WAIT = 4, 612592a6318SAnthony Koo /** 613592a6318SAnthony Koo * Workaround to avoid HUBP underflow during NV12 playback. 614592a6318SAnthony Koo */ 615bae9c49bSYongqiang Sun DMUB_CMD__PLAT_54186_WA = 5, 6161a595f28SAnthony Koo /** 6171a595f28SAnthony Koo * Command type used to query FW feature caps. 6181a595f28SAnthony Koo */ 61934ba432cSAnthony Koo DMUB_CMD__QUERY_FEATURE_CAPS = 6, 6201a595f28SAnthony Koo /** 6211a595f28SAnthony Koo * Command type used for all PSR commands. 6221a595f28SAnthony Koo */ 623d4bbcecbSNicholas Kazlauskas DMUB_CMD__PSR = 64, 624592a6318SAnthony Koo /** 625592a6318SAnthony Koo * Command type used for all MALL commands. 626592a6318SAnthony Koo */ 62752f2e83eSBhawanpreet Lakha DMUB_CMD__MALL = 65, 6281a595f28SAnthony Koo /** 6291a595f28SAnthony Koo * Command type used for all ABM commands. 6301a595f28SAnthony Koo */ 631e6ea8c34SWyatt Wood DMUB_CMD__ABM = 66, 6321a595f28SAnthony Koo /** 6331a595f28SAnthony Koo * Command type used for HW locking in FW. 6341a595f28SAnthony Koo */ 635788408b7SAnthony Koo DMUB_CMD__HW_LOCK = 69, 6361a595f28SAnthony Koo /** 6371a595f28SAnthony Koo * Command type used to access DP AUX. 6381a595f28SAnthony Koo */ 639d9beecfcSAnthony Koo DMUB_CMD__DP_AUX_ACCESS = 70, 6401a595f28SAnthony Koo /** 6411a595f28SAnthony Koo * Command type used for OUTBOX1 notification enable 6421a595f28SAnthony Koo */ 643d9beecfcSAnthony Koo DMUB_CMD__OUTBOX1_ENABLE = 71, 644b04cb192SNicholas Kazlauskas /** 645b04cb192SNicholas Kazlauskas * Command type used for all idle optimization commands. 646b04cb192SNicholas Kazlauskas */ 647b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT = 72, 648b04cb192SNicholas Kazlauskas /** 649b04cb192SNicholas Kazlauskas * Command type used for all clock manager commands. 650b04cb192SNicholas Kazlauskas */ 651b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR = 73, 652b04cb192SNicholas Kazlauskas /** 653b04cb192SNicholas Kazlauskas * Command type used for all panel control commands. 654b04cb192SNicholas Kazlauskas */ 655b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL = 74, 656592a6318SAnthony Koo /** 657021eaef8SAnthony Koo * Command type used for EDID CEA parsing 658021eaef8SAnthony Koo */ 659021eaef8SAnthony Koo DMUB_CMD__EDID_CEA = 79, 660021eaef8SAnthony Koo /** 661592a6318SAnthony Koo * Command type used for all VBIOS interface commands. 662592a6318SAnthony Koo */ 663d4bbcecbSNicholas Kazlauskas DMUB_CMD__VBIOS = 128, 6647c008829SNicholas Kazlauskas }; 6657c008829SNicholas Kazlauskas 666592a6318SAnthony Koo /** 667592a6318SAnthony Koo * enum dmub_out_cmd_type - DMUB outbox commands. 668592a6318SAnthony Koo */ 6693b37260bSAnthony Koo enum dmub_out_cmd_type { 670592a6318SAnthony Koo /** 671592a6318SAnthony Koo * Invalid outbox command, ignored. 672592a6318SAnthony Koo */ 6733b37260bSAnthony Koo DMUB_OUT_CMD__NULL = 0, 6741a595f28SAnthony Koo /** 6751a595f28SAnthony Koo * Command type used for DP AUX Reply data notification 6761a595f28SAnthony Koo */ 677d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_AUX_REPLY = 1, 6783b37260bSAnthony Koo }; 6793b37260bSAnthony Koo 6807c008829SNicholas Kazlauskas #pragma pack(push, 1) 6817c008829SNicholas Kazlauskas 682592a6318SAnthony Koo /** 683592a6318SAnthony Koo * struct dmub_cmd_header - Common command header fields. 684592a6318SAnthony Koo */ 6857c008829SNicholas Kazlauskas struct dmub_cmd_header { 686592a6318SAnthony Koo unsigned int type : 8; /**< command type */ 687592a6318SAnthony Koo unsigned int sub_type : 8; /**< command sub type */ 688592a6318SAnthony Koo unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 6890b51e7e8SAnthony Koo unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 6900b51e7e8SAnthony Koo unsigned int reserved0 : 6; /**< reserved bits */ 691592a6318SAnthony Koo unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 692592a6318SAnthony Koo unsigned int reserved1 : 2; /**< reserved bits */ 6937c008829SNicholas Kazlauskas }; 6947c008829SNicholas Kazlauskas 6957c008829SNicholas Kazlauskas /* 696592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write 6977c008829SNicholas Kazlauskas * 6987c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 5 sets of read modify writes, 6997c008829SNicholas Kazlauskas * each take 3 dwords. 7007c008829SNicholas Kazlauskas * 7017c008829SNicholas Kazlauskas * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 7027c008829SNicholas Kazlauskas * 7037c008829SNicholas Kazlauskas * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 7047c008829SNicholas Kazlauskas * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 7057c008829SNicholas Kazlauskas */ 7067c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence { 707592a6318SAnthony Koo uint32_t addr; /**< register address */ 708592a6318SAnthony Koo uint32_t modify_mask; /**< modify mask */ 709592a6318SAnthony Koo uint32_t modify_value; /**< modify value */ 7107c008829SNicholas Kazlauskas }; 7117c008829SNicholas Kazlauskas 712592a6318SAnthony Koo /** 713592a6318SAnthony Koo * Maximum number of ops in read modify write sequence. 714592a6318SAnthony Koo */ 7157c008829SNicholas Kazlauskas #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 716592a6318SAnthony Koo 717592a6318SAnthony Koo /** 718592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 719592a6318SAnthony Koo */ 7207c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write { 721592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 722592a6318SAnthony Koo /** 723592a6318SAnthony Koo * Read modify write sequence. 724592a6318SAnthony Koo */ 7257c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 7267c008829SNicholas Kazlauskas }; 7277c008829SNicholas Kazlauskas 7287c008829SNicholas Kazlauskas /* 7297c008829SNicholas Kazlauskas * Update a register with specified masks and values sequeunce 7307c008829SNicholas Kazlauskas * 7317c008829SNicholas Kazlauskas * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 7327c008829SNicholas Kazlauskas * 7337c008829SNicholas Kazlauskas * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 7347c008829SNicholas Kazlauskas * 7357c008829SNicholas Kazlauskas * 7367c008829SNicholas Kazlauskas * USE CASE: 7377c008829SNicholas Kazlauskas * 1. auto-increment register where additional read would update pointer and produce wrong result 7387c008829SNicholas Kazlauskas * 2. toggle a bit without read in the middle 7397c008829SNicholas Kazlauskas */ 7407c008829SNicholas Kazlauskas 7417c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence { 742592a6318SAnthony Koo uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 743592a6318SAnthony Koo uint32_t modify_value; /**< value to update with */ 7447c008829SNicholas Kazlauskas }; 7457c008829SNicholas Kazlauskas 746592a6318SAnthony Koo /** 747592a6318SAnthony Koo * Maximum number of ops in field update sequence. 748592a6318SAnthony Koo */ 7497c008829SNicholas Kazlauskas #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 750592a6318SAnthony Koo 751592a6318SAnthony Koo /** 752592a6318SAnthony Koo * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 753592a6318SAnthony Koo */ 7547c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence { 755592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 756592a6318SAnthony Koo uint32_t addr; /**< register address */ 757592a6318SAnthony Koo /** 758592a6318SAnthony Koo * Field update sequence. 759592a6318SAnthony Koo */ 7607c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 7617c008829SNicholas Kazlauskas }; 7627c008829SNicholas Kazlauskas 763592a6318SAnthony Koo 764592a6318SAnthony Koo /** 765592a6318SAnthony Koo * Maximum number of burst write values. 766592a6318SAnthony Koo */ 767592a6318SAnthony Koo #define DMUB_BURST_WRITE_VALUES__MAX 14 768592a6318SAnthony Koo 7697c008829SNicholas Kazlauskas /* 770592a6318SAnthony Koo * struct dmub_rb_cmd_burst_write - Burst write 7717c008829SNicholas Kazlauskas * 7727c008829SNicholas Kazlauskas * support use case such as writing out LUTs. 7737c008829SNicholas Kazlauskas * 7747c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 14 values to write to given address 7757c008829SNicholas Kazlauskas * 7767c008829SNicholas Kazlauskas * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 7777c008829SNicholas Kazlauskas */ 7787c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write { 779592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 780592a6318SAnthony Koo uint32_t addr; /**< register start address */ 781592a6318SAnthony Koo /** 782592a6318SAnthony Koo * Burst write register values. 783592a6318SAnthony Koo */ 7847c008829SNicholas Kazlauskas uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 7857c008829SNicholas Kazlauskas }; 7867c008829SNicholas Kazlauskas 787592a6318SAnthony Koo /** 788592a6318SAnthony Koo * struct dmub_rb_cmd_common - Common command header 789592a6318SAnthony Koo */ 7907c008829SNicholas Kazlauskas struct dmub_rb_cmd_common { 791592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 792592a6318SAnthony Koo /** 793592a6318SAnthony Koo * Padding to RB_CMD_SIZE 794592a6318SAnthony Koo */ 7957c008829SNicholas Kazlauskas uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 7967c008829SNicholas Kazlauskas }; 7977c008829SNicholas Kazlauskas 798592a6318SAnthony Koo /** 799592a6318SAnthony Koo * struct dmub_cmd_reg_wait_data - Register wait data 800592a6318SAnthony Koo */ 8017c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data { 802592a6318SAnthony Koo uint32_t addr; /**< Register address */ 803592a6318SAnthony Koo uint32_t mask; /**< Mask for register bits */ 804592a6318SAnthony Koo uint32_t condition_field_value; /**< Value to wait for */ 805592a6318SAnthony Koo uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 8067c008829SNicholas Kazlauskas }; 8077c008829SNicholas Kazlauskas 808592a6318SAnthony Koo /** 809592a6318SAnthony Koo * struct dmub_rb_cmd_reg_wait - Register wait command 810592a6318SAnthony Koo */ 8117c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait { 812592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 813592a6318SAnthony Koo struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 8147c008829SNicholas Kazlauskas }; 8157c008829SNicholas Kazlauskas 816592a6318SAnthony Koo /** 817592a6318SAnthony Koo * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 818592a6318SAnthony Koo * 819592a6318SAnthony Koo * Reprograms surface parameters to avoid underflow. 820592a6318SAnthony Koo */ 821bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa { 822592a6318SAnthony Koo uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 823592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 824592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 825592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 826592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 82722aa5614SYongqiang Sun struct { 828592a6318SAnthony Koo uint8_t hubp_inst : 4; /**< HUBP instance */ 829592a6318SAnthony Koo uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 830592a6318SAnthony Koo uint8_t immediate :1; /**< Immediate flip */ 831592a6318SAnthony Koo uint8_t vmid : 4; /**< VMID */ 832592a6318SAnthony Koo uint8_t grph_stereo : 1; /**< 1 if stereo */ 833592a6318SAnthony Koo uint32_t reserved : 21; /**< Reserved */ 834592a6318SAnthony Koo } flip_params; /**< Pageflip parameters */ 835592a6318SAnthony Koo uint32_t reserved[9]; /**< Reserved bits */ 8368c019253SYongqiang Sun }; 8378c019253SYongqiang Sun 838592a6318SAnthony Koo /** 839592a6318SAnthony Koo * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 840592a6318SAnthony Koo */ 841bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa { 842592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 843592a6318SAnthony Koo struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 8448c019253SYongqiang Sun }; 8458c019253SYongqiang Sun 846592a6318SAnthony Koo /** 847592a6318SAnthony Koo * struct dmub_rb_cmd_mall - MALL command data. 848592a6318SAnthony Koo */ 84952f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall { 850592a6318SAnthony Koo struct dmub_cmd_header header; /**< Common command header */ 851592a6318SAnthony Koo union dmub_addr cursor_copy_src; /**< Cursor copy address */ 852592a6318SAnthony Koo union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 853592a6318SAnthony Koo uint32_t tmr_delay; /**< Timer delay */ 854592a6318SAnthony Koo uint32_t tmr_scale; /**< Timer scale */ 855592a6318SAnthony Koo uint16_t cursor_width; /**< Cursor width in pixels */ 856592a6318SAnthony Koo uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 857592a6318SAnthony Koo uint16_t cursor_height; /**< Cursor height in pixels */ 858592a6318SAnthony Koo uint8_t cursor_bpp; /**< Cursor bits per pixel */ 859592a6318SAnthony Koo uint8_t debug_bits; /**< Debug bits */ 860ea7154d8SBhawanpreet Lakha 861592a6318SAnthony Koo uint8_t reserved1; /**< Reserved bits */ 862592a6318SAnthony Koo uint8_t reserved2; /**< Reserved bits */ 86352f2e83eSBhawanpreet Lakha }; 86452f2e83eSBhawanpreet Lakha 865b04cb192SNicholas Kazlauskas /** 866b04cb192SNicholas Kazlauskas * enum dmub_cmd_idle_opt_type - Idle optimization command type. 867b04cb192SNicholas Kazlauskas */ 868b04cb192SNicholas Kazlauskas enum dmub_cmd_idle_opt_type { 869b04cb192SNicholas Kazlauskas /** 870b04cb192SNicholas Kazlauskas * DCN hardware restore. 871b04cb192SNicholas Kazlauskas */ 872b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 873f586fea8SJake Wang 874f586fea8SJake Wang /** 875f586fea8SJake Wang * DCN hardware save. 876f586fea8SJake Wang */ 877f586fea8SJake Wang DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 878b04cb192SNicholas Kazlauskas }; 879b04cb192SNicholas Kazlauskas 880b04cb192SNicholas Kazlauskas /** 881b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 882b04cb192SNicholas Kazlauskas */ 883b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore { 884b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 885b04cb192SNicholas Kazlauskas }; 886b04cb192SNicholas Kazlauskas 887b04cb192SNicholas Kazlauskas /** 888b04cb192SNicholas Kazlauskas * struct dmub_clocks - Clock update notification. 889b04cb192SNicholas Kazlauskas */ 890b04cb192SNicholas Kazlauskas struct dmub_clocks { 891b04cb192SNicholas Kazlauskas uint32_t dispclk_khz; /**< dispclk kHz */ 892b04cb192SNicholas Kazlauskas uint32_t dppclk_khz; /**< dppclk kHz */ 893b04cb192SNicholas Kazlauskas uint32_t dcfclk_khz; /**< dcfclk kHz */ 894b04cb192SNicholas Kazlauskas uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 895b04cb192SNicholas Kazlauskas }; 896b04cb192SNicholas Kazlauskas 897b04cb192SNicholas Kazlauskas /** 898b04cb192SNicholas Kazlauskas * enum dmub_cmd_clk_mgr_type - Clock manager commands. 899b04cb192SNicholas Kazlauskas */ 900b04cb192SNicholas Kazlauskas enum dmub_cmd_clk_mgr_type { 901b04cb192SNicholas Kazlauskas /** 902b04cb192SNicholas Kazlauskas * Notify DMCUB of clock update. 903b04cb192SNicholas Kazlauskas */ 904b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 905b04cb192SNicholas Kazlauskas }; 906b04cb192SNicholas Kazlauskas 907b04cb192SNicholas Kazlauskas /** 908b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 909b04cb192SNicholas Kazlauskas */ 910b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks { 911b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 912b04cb192SNicholas Kazlauskas struct dmub_clocks clocks; /**< clock data */ 913b04cb192SNicholas Kazlauskas }; 9148fe44c08SAlex Deucher 915592a6318SAnthony Koo /** 916592a6318SAnthony Koo * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 917592a6318SAnthony Koo */ 9187c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data { 919592a6318SAnthony Koo union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 9207c008829SNicholas Kazlauskas }; 9217c008829SNicholas Kazlauskas 922592a6318SAnthony Koo /** 923592a6318SAnthony Koo * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 924592a6318SAnthony Koo */ 9257c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control { 926592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 927592a6318SAnthony Koo struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 9287c008829SNicholas Kazlauskas }; 9297c008829SNicholas Kazlauskas 930592a6318SAnthony Koo /** 931592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 932592a6318SAnthony Koo */ 9337c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data { 934592a6318SAnthony Koo struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 9357c008829SNicholas Kazlauskas }; 9367c008829SNicholas Kazlauskas 937592a6318SAnthony Koo /** 938592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 939592a6318SAnthony Koo */ 9407c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock { 941592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 942592a6318SAnthony Koo struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 9437c008829SNicholas Kazlauskas }; 9447c008829SNicholas Kazlauskas 945592a6318SAnthony Koo /** 946592a6318SAnthony Koo * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 947592a6318SAnthony Koo */ 9487c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data { 949592a6318SAnthony Koo struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 9507c008829SNicholas Kazlauskas }; 9517c008829SNicholas Kazlauskas 952592a6318SAnthony Koo /** 953592a6318SAnthony Koo * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 954592a6318SAnthony Koo */ 9557c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating { 956592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 957592a6318SAnthony Koo struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 9587c008829SNicholas Kazlauskas }; 9597c008829SNicholas Kazlauskas 960592a6318SAnthony Koo /** 961592a6318SAnthony Koo * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 962592a6318SAnthony Koo */ 963d448521eSAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 { 964d448521eSAnthony Koo uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 965d448521eSAnthony Koo uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 966d448521eSAnthony Koo union { 967d448521eSAnthony Koo uint8_t digmode; /**< enum atom_encode_mode_def */ 968d448521eSAnthony Koo uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 969d448521eSAnthony Koo } mode_laneset; 970d448521eSAnthony Koo uint8_t lanenum; /**< Number of lanes */ 971d448521eSAnthony Koo union { 972d448521eSAnthony Koo uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 973d448521eSAnthony Koo } symclk_units; 974d448521eSAnthony Koo uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 975d448521eSAnthony Koo uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 976d448521eSAnthony Koo uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 9775a2730fcSFangzhi Zuo uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 978d448521eSAnthony Koo uint8_t reserved1; /**< For future use */ 979d448521eSAnthony Koo uint8_t reserved2[3]; /**< For future use */ 980d448521eSAnthony Koo uint32_t reserved3[11]; /**< For future use */ 981d448521eSAnthony Koo }; 982d448521eSAnthony Koo 983592a6318SAnthony Koo /** 984592a6318SAnthony Koo * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 985592a6318SAnthony Koo */ 986d448521eSAnthony Koo union dmub_cmd_dig1_transmitter_control_data { 987592a6318SAnthony Koo struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 988592a6318SAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 9897c008829SNicholas Kazlauskas }; 9907c008829SNicholas Kazlauskas 991592a6318SAnthony Koo /** 992592a6318SAnthony Koo * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 993592a6318SAnthony Koo */ 9947c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control { 995592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 996592a6318SAnthony Koo union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 9977c008829SNicholas Kazlauskas }; 9987c008829SNicholas Kazlauskas 999592a6318SAnthony Koo /** 1000592a6318SAnthony Koo * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1001592a6318SAnthony Koo */ 10027c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init { 1003592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1004592a6318SAnthony Koo uint8_t reserved[60]; /**< reserved bits */ 10057c008829SNicholas Kazlauskas }; 10067c008829SNicholas Kazlauskas 10071a595f28SAnthony Koo /** 10081a595f28SAnthony Koo * enum dp_aux_request_action - DP AUX request command listing. 10091a595f28SAnthony Koo * 10101a595f28SAnthony Koo * 4 AUX request command bits are shifted to high nibble. 10111a595f28SAnthony Koo */ 1012d9beecfcSAnthony Koo enum dp_aux_request_action { 10131a595f28SAnthony Koo /** I2C-over-AUX write request */ 1014d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 10151a595f28SAnthony Koo /** I2C-over-AUX read request */ 1016d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ = 0x10, 10171a595f28SAnthony Koo /** I2C-over-AUX write status request */ 1018d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 10191a595f28SAnthony Koo /** I2C-over-AUX write request with MOT=1 */ 1020d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 10211a595f28SAnthony Koo /** I2C-over-AUX read request with MOT=1 */ 1022d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 10231a595f28SAnthony Koo /** I2C-over-AUX write status request with MOT=1 */ 1024d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 10251a595f28SAnthony Koo /** Native AUX write request */ 1026d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 10271a595f28SAnthony Koo /** Native AUX read request */ 1028d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1029d9beecfcSAnthony Koo }; 1030d9beecfcSAnthony Koo 10311a595f28SAnthony Koo /** 10321a595f28SAnthony Koo * enum aux_return_code_type - DP AUX process return code listing. 10331a595f28SAnthony Koo */ 1034fd0f1d21SAnthony Koo enum aux_return_code_type { 10351a595f28SAnthony Koo /** AUX process succeeded */ 1036fd0f1d21SAnthony Koo AUX_RET_SUCCESS = 0, 10371a595f28SAnthony Koo /** AUX process failed with unknown reason */ 1038b6402afeSAnthony Koo AUX_RET_ERROR_UNKNOWN, 10391a595f28SAnthony Koo /** AUX process completed with invalid reply */ 1040b6402afeSAnthony Koo AUX_RET_ERROR_INVALID_REPLY, 10411a595f28SAnthony Koo /** AUX process timed out */ 1042fd0f1d21SAnthony Koo AUX_RET_ERROR_TIMEOUT, 10431a595f28SAnthony Koo /** HPD was low during AUX process */ 1044b6402afeSAnthony Koo AUX_RET_ERROR_HPD_DISCON, 10451a595f28SAnthony Koo /** Failed to acquire AUX engine */ 1046b6402afeSAnthony Koo AUX_RET_ERROR_ENGINE_ACQUIRE, 10471a595f28SAnthony Koo /** AUX request not supported */ 1048fd0f1d21SAnthony Koo AUX_RET_ERROR_INVALID_OPERATION, 10491a595f28SAnthony Koo /** AUX process not available */ 1050fd0f1d21SAnthony Koo AUX_RET_ERROR_PROTOCOL_ERROR, 1051fd0f1d21SAnthony Koo }; 1052fd0f1d21SAnthony Koo 10531a595f28SAnthony Koo /** 10541a595f28SAnthony Koo * enum aux_channel_type - DP AUX channel type listing. 10551a595f28SAnthony Koo */ 1056b6402afeSAnthony Koo enum aux_channel_type { 10571a595f28SAnthony Koo /** AUX thru Legacy DP AUX */ 1058b6402afeSAnthony Koo AUX_CHANNEL_LEGACY_DDC, 10591a595f28SAnthony Koo /** AUX thru DPIA DP tunneling */ 1060b6402afeSAnthony Koo AUX_CHANNEL_DPIA 1061b6402afeSAnthony Koo }; 1062b6402afeSAnthony Koo 10631a595f28SAnthony Koo /** 10641a595f28SAnthony Koo * struct aux_transaction_parameters - DP AUX request transaction data 10651a595f28SAnthony Koo */ 1066d9beecfcSAnthony Koo struct aux_transaction_parameters { 10671a595f28SAnthony Koo uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 10681a595f28SAnthony Koo uint8_t action; /**< enum dp_aux_request_action */ 10691a595f28SAnthony Koo uint8_t length; /**< DP AUX request data length */ 10701a595f28SAnthony Koo uint8_t reserved; /**< For future use */ 10711a595f28SAnthony Koo uint32_t address; /**< DP AUX address */ 10721a595f28SAnthony Koo uint8_t data[16]; /**< DP AUX write data */ 1073d9beecfcSAnthony Koo }; 1074d9beecfcSAnthony Koo 10751a595f28SAnthony Koo /** 10761a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 10771a595f28SAnthony Koo */ 1078d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data { 10791a595f28SAnthony Koo uint8_t instance; /**< AUX instance or DPIA instance */ 10801a595f28SAnthony Koo uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 10811a595f28SAnthony Koo uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 10821a595f28SAnthony Koo uint8_t reserved0; /**< For future use */ 10831a595f28SAnthony Koo uint16_t timeout; /**< timeout time in us */ 10841a595f28SAnthony Koo uint16_t reserved1; /**< For future use */ 10851a595f28SAnthony Koo enum aux_channel_type type; /**< enum aux_channel_type */ 10861a595f28SAnthony Koo struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1087d9beecfcSAnthony Koo }; 1088d9beecfcSAnthony Koo 10891a595f28SAnthony Koo /** 10901a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 10911a595f28SAnthony Koo */ 1092d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access { 10931a595f28SAnthony Koo /** 10941a595f28SAnthony Koo * Command header. 10951a595f28SAnthony Koo */ 1096d9beecfcSAnthony Koo struct dmub_cmd_header header; 10971a595f28SAnthony Koo /** 10981a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 10991a595f28SAnthony Koo */ 1100d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data aux_control; 1101d9beecfcSAnthony Koo }; 1102d9beecfcSAnthony Koo 11031a595f28SAnthony Koo /** 11041a595f28SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 11051a595f28SAnthony Koo */ 1106d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable { 11071a595f28SAnthony Koo /** 11081a595f28SAnthony Koo * Command header. 11091a595f28SAnthony Koo */ 1110d9beecfcSAnthony Koo struct dmub_cmd_header header; 11111a595f28SAnthony Koo /** 11121a595f28SAnthony Koo * enable: 0x0 -> disable outbox1 notification (default value) 11131a595f28SAnthony Koo * 0x1 -> enable outbox1 notification 11141a595f28SAnthony Koo */ 1115d9beecfcSAnthony Koo uint32_t enable; 1116d9beecfcSAnthony Koo }; 1117d9beecfcSAnthony Koo 1118d9beecfcSAnthony Koo /* DP AUX Reply command - OutBox Cmd */ 11191a595f28SAnthony Koo /** 11201a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 11211a595f28SAnthony Koo */ 1122d9beecfcSAnthony Koo struct aux_reply_data { 11231a595f28SAnthony Koo /** 11241a595f28SAnthony Koo * Aux cmd 11251a595f28SAnthony Koo */ 1126d9beecfcSAnthony Koo uint8_t command; 11271a595f28SAnthony Koo /** 11281a595f28SAnthony Koo * Aux reply data length (max: 16 bytes) 11291a595f28SAnthony Koo */ 1130d9beecfcSAnthony Koo uint8_t length; 11311a595f28SAnthony Koo /** 11321a595f28SAnthony Koo * Alignment only 11331a595f28SAnthony Koo */ 1134d9beecfcSAnthony Koo uint8_t pad[2]; 11351a595f28SAnthony Koo /** 11361a595f28SAnthony Koo * Aux reply data 11371a595f28SAnthony Koo */ 1138d9beecfcSAnthony Koo uint8_t data[16]; 1139d9beecfcSAnthony Koo }; 1140d9beecfcSAnthony Koo 11411a595f28SAnthony Koo /** 11421a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 11431a595f28SAnthony Koo */ 1144d9beecfcSAnthony Koo struct aux_reply_control_data { 11451a595f28SAnthony Koo /** 11461a595f28SAnthony Koo * Reserved for future use 11471a595f28SAnthony Koo */ 1148d9beecfcSAnthony Koo uint32_t handle; 11491a595f28SAnthony Koo /** 11501a595f28SAnthony Koo * Aux Instance 11511a595f28SAnthony Koo */ 1152b6402afeSAnthony Koo uint8_t instance; 11531a595f28SAnthony Koo /** 11541a595f28SAnthony Koo * Aux transaction result: definition in enum aux_return_code_type 11551a595f28SAnthony Koo */ 1156d9beecfcSAnthony Koo uint8_t result; 11571a595f28SAnthony Koo /** 11581a595f28SAnthony Koo * Alignment only 11591a595f28SAnthony Koo */ 1160d9beecfcSAnthony Koo uint16_t pad; 1161d9beecfcSAnthony Koo }; 1162d9beecfcSAnthony Koo 11631a595f28SAnthony Koo /** 11641a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 11651a595f28SAnthony Koo */ 1166d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply { 11671a595f28SAnthony Koo /** 11681a595f28SAnthony Koo * Command header. 11691a595f28SAnthony Koo */ 1170d9beecfcSAnthony Koo struct dmub_cmd_header header; 11711a595f28SAnthony Koo /** 11721a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 11731a595f28SAnthony Koo */ 1174d9beecfcSAnthony Koo struct aux_reply_control_data control; 11751a595f28SAnthony Koo /** 11761a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 11771a595f28SAnthony Koo */ 1178d9beecfcSAnthony Koo struct aux_reply_data reply_data; 1179d9beecfcSAnthony Koo }; 1180d9beecfcSAnthony Koo 1181fd0f1d21SAnthony Koo /* DP HPD Notify command - OutBox Cmd */ 11821a595f28SAnthony Koo /** 11831a595f28SAnthony Koo * DP HPD Type 11841a595f28SAnthony Koo */ 1185fd0f1d21SAnthony Koo enum dp_hpd_type { 11861a595f28SAnthony Koo /** 11871a595f28SAnthony Koo * Normal DP HPD 11881a595f28SAnthony Koo */ 1189fd0f1d21SAnthony Koo DP_HPD = 0, 11901a595f28SAnthony Koo /** 11911a595f28SAnthony Koo * DP HPD short pulse 11921a595f28SAnthony Koo */ 1193fd0f1d21SAnthony Koo DP_IRQ 1194fd0f1d21SAnthony Koo }; 1195fd0f1d21SAnthony Koo 11961a595f28SAnthony Koo /** 11971a595f28SAnthony Koo * DP HPD Status 11981a595f28SAnthony Koo */ 1199fd0f1d21SAnthony Koo enum dp_hpd_status { 12001a595f28SAnthony Koo /** 12011a595f28SAnthony Koo * DP_HPD status low 12021a595f28SAnthony Koo */ 1203fd0f1d21SAnthony Koo DP_HPD_UNPLUG = 0, 12041a595f28SAnthony Koo /** 12051a595f28SAnthony Koo * DP_HPD status high 12061a595f28SAnthony Koo */ 1207fd0f1d21SAnthony Koo DP_HPD_PLUG 1208fd0f1d21SAnthony Koo }; 1209fd0f1d21SAnthony Koo 12101a595f28SAnthony Koo /** 12111a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 12121a595f28SAnthony Koo */ 1213d9beecfcSAnthony Koo struct dp_hpd_data { 12141a595f28SAnthony Koo /** 12151a595f28SAnthony Koo * DP HPD instance 12161a595f28SAnthony Koo */ 1217b6402afeSAnthony Koo uint8_t instance; 12181a595f28SAnthony Koo /** 12191a595f28SAnthony Koo * HPD type 12201a595f28SAnthony Koo */ 1221d9beecfcSAnthony Koo uint8_t hpd_type; 12221a595f28SAnthony Koo /** 12231a595f28SAnthony Koo * HPD status: only for type: DP_HPD to indicate status 12241a595f28SAnthony Koo */ 1225d9beecfcSAnthony Koo uint8_t hpd_status; 12261a595f28SAnthony Koo /** 12271a595f28SAnthony Koo * Alignment only 12281a595f28SAnthony Koo */ 1229d9beecfcSAnthony Koo uint8_t pad; 1230d9beecfcSAnthony Koo }; 1231d9beecfcSAnthony Koo 12321a595f28SAnthony Koo /** 12331a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 12341a595f28SAnthony Koo */ 1235d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify { 12361a595f28SAnthony Koo /** 12371a595f28SAnthony Koo * Command header. 12381a595f28SAnthony Koo */ 1239d9beecfcSAnthony Koo struct dmub_cmd_header header; 12401a595f28SAnthony Koo /** 12411a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 12421a595f28SAnthony Koo */ 1243d9beecfcSAnthony Koo struct dp_hpd_data hpd_data; 1244d9beecfcSAnthony Koo }; 1245d9beecfcSAnthony Koo 124684034ad4SAnthony Koo /* 124784034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 124884034ad4SAnthony Koo * Do not reuse or modify IDs. 124984034ad4SAnthony Koo */ 125084034ad4SAnthony Koo 12511a595f28SAnthony Koo /** 12521a595f28SAnthony Koo * PSR command sub-types. 12531a595f28SAnthony Koo */ 125484034ad4SAnthony Koo enum dmub_cmd_psr_type { 12551a595f28SAnthony Koo /** 12561a595f28SAnthony Koo * Set PSR version support. 12571a595f28SAnthony Koo */ 125884034ad4SAnthony Koo DMUB_CMD__PSR_SET_VERSION = 0, 12591a595f28SAnthony Koo /** 12601a595f28SAnthony Koo * Copy driver-calculated parameters to PSR state. 12611a595f28SAnthony Koo */ 126284034ad4SAnthony Koo DMUB_CMD__PSR_COPY_SETTINGS = 1, 12631a595f28SAnthony Koo /** 12641a595f28SAnthony Koo * Enable PSR. 12651a595f28SAnthony Koo */ 126684034ad4SAnthony Koo DMUB_CMD__PSR_ENABLE = 2, 12671a595f28SAnthony Koo 12681a595f28SAnthony Koo /** 12691a595f28SAnthony Koo * Disable PSR. 12701a595f28SAnthony Koo */ 127184034ad4SAnthony Koo DMUB_CMD__PSR_DISABLE = 3, 12721a595f28SAnthony Koo 12731a595f28SAnthony Koo /** 12741a595f28SAnthony Koo * Set PSR level. 12751a595f28SAnthony Koo * PSR level is a 16-bit value dicated by driver that 12761a595f28SAnthony Koo * will enable/disable different functionality. 12771a595f28SAnthony Koo */ 127884034ad4SAnthony Koo DMUB_CMD__PSR_SET_LEVEL = 4, 12791a595f28SAnthony Koo 12801a595f28SAnthony Koo /** 12811a595f28SAnthony Koo * Forces PSR enabled until an explicit PSR disable call. 12821a595f28SAnthony Koo */ 1283672251b2SAnthony Koo DMUB_CMD__PSR_FORCE_STATIC = 5, 128484034ad4SAnthony Koo }; 128584034ad4SAnthony Koo 12861a595f28SAnthony Koo /** 12871a595f28SAnthony Koo * PSR versions. 12881a595f28SAnthony Koo */ 128984034ad4SAnthony Koo enum psr_version { 12901a595f28SAnthony Koo /** 12911a595f28SAnthony Koo * PSR version 1. 12921a595f28SAnthony Koo */ 129384034ad4SAnthony Koo PSR_VERSION_1 = 0, 12941a595f28SAnthony Koo /** 12951a595f28SAnthony Koo * PSR not supported. 12961a595f28SAnthony Koo */ 129784034ad4SAnthony Koo PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 129884034ad4SAnthony Koo }; 129984034ad4SAnthony Koo 1300592a6318SAnthony Koo /** 1301592a6318SAnthony Koo * enum dmub_cmd_mall_type - MALL commands 1302592a6318SAnthony Koo */ 130352f2e83eSBhawanpreet Lakha enum dmub_cmd_mall_type { 1304592a6318SAnthony Koo /** 1305592a6318SAnthony Koo * Allows display refresh from MALL. 1306592a6318SAnthony Koo */ 130752f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_ALLOW = 0, 1308592a6318SAnthony Koo /** 1309592a6318SAnthony Koo * Disallows display refresh from MALL. 1310592a6318SAnthony Koo */ 131152f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1312592a6318SAnthony Koo /** 1313592a6318SAnthony Koo * Cursor copy for MALL. 1314592a6318SAnthony Koo */ 131552f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1316592a6318SAnthony Koo /** 1317592a6318SAnthony Koo * Controls DF requests. 1318592a6318SAnthony Koo */ 1319ea7154d8SBhawanpreet Lakha DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 132052f2e83eSBhawanpreet Lakha }; 132152f2e83eSBhawanpreet Lakha 1322592a6318SAnthony Koo 13231a595f28SAnthony Koo /** 13241a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 13251a595f28SAnthony Koo */ 13267c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data { 13271a595f28SAnthony Koo /** 13281a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 13291a595f28SAnthony Koo */ 13307b8a6362SAnthony Koo union dmub_psr_debug_flags debug; 13311a595f28SAnthony Koo /** 13321a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 13331a595f28SAnthony Koo */ 13344c1a1335SWyatt Wood uint16_t psr_level; 13351a595f28SAnthony Koo /** 13361a595f28SAnthony Koo * DPP HW instance. 13371a595f28SAnthony Koo */ 13384c1a1335SWyatt Wood uint8_t dpp_inst; 13391a595f28SAnthony Koo /** 13401a595f28SAnthony Koo * MPCC HW instance. 13411a595f28SAnthony Koo * Not used in dmub fw, 134234ba432cSAnthony Koo * dmub fw will get active opp by reading odm registers. 134334ba432cSAnthony Koo */ 13444c1a1335SWyatt Wood uint8_t mpcc_inst; 13451a595f28SAnthony Koo /** 13461a595f28SAnthony Koo * OPP HW instance. 13471a595f28SAnthony Koo * Not used in dmub fw, 13481a595f28SAnthony Koo * dmub fw will get active opp by reading odm registers. 13491a595f28SAnthony Koo */ 13504c1a1335SWyatt Wood uint8_t opp_inst; 13511a595f28SAnthony Koo /** 13521a595f28SAnthony Koo * OTG HW instance. 13531a595f28SAnthony Koo */ 13544c1a1335SWyatt Wood uint8_t otg_inst; 13551a595f28SAnthony Koo /** 13561a595f28SAnthony Koo * DIG FE HW instance. 13571a595f28SAnthony Koo */ 13584c1a1335SWyatt Wood uint8_t digfe_inst; 13591a595f28SAnthony Koo /** 13601a595f28SAnthony Koo * DIG BE HW instance. 13611a595f28SAnthony Koo */ 13624c1a1335SWyatt Wood uint8_t digbe_inst; 13631a595f28SAnthony Koo /** 13641a595f28SAnthony Koo * DP PHY HW instance. 13651a595f28SAnthony Koo */ 13664c1a1335SWyatt Wood uint8_t dpphy_inst; 13671a595f28SAnthony Koo /** 13681a595f28SAnthony Koo * AUX HW instance. 13691a595f28SAnthony Koo */ 13704c1a1335SWyatt Wood uint8_t aux_inst; 13711a595f28SAnthony Koo /** 13721a595f28SAnthony Koo * Determines if SMU optimzations are enabled/disabled. 13731a595f28SAnthony Koo */ 13744c1a1335SWyatt Wood uint8_t smu_optimizations_en; 13751a595f28SAnthony Koo /** 13761a595f28SAnthony Koo * Unused. 13771a595f28SAnthony Koo * TODO: Remove. 13781a595f28SAnthony Koo */ 13794c1a1335SWyatt Wood uint8_t frame_delay; 13801a595f28SAnthony Koo /** 13811a595f28SAnthony Koo * If RFB setup time is greater than the total VBLANK time, 13821a595f28SAnthony Koo * it is not possible for the sink to capture the video frame 13831a595f28SAnthony Koo * in the same frame the SDP is sent. In this case, 13841a595f28SAnthony Koo * the frame capture indication bit should be set and an extra 13851a595f28SAnthony Koo * static frame should be transmitted to the sink. 13861a595f28SAnthony Koo */ 13874c1a1335SWyatt Wood uint8_t frame_cap_ind; 13881a595f28SAnthony Koo /** 13891a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 13901a595f28SAnthony Koo */ 1391175f0971SYongqiang Sun uint8_t pad[2]; 13921a595f28SAnthony Koo /** 13931a595f28SAnthony Koo * Multi-display optimizations are implemented on certain ASICs. 13941a595f28SAnthony Koo */ 1395175f0971SYongqiang Sun uint8_t multi_disp_optimizations_en; 13961a595f28SAnthony Koo /** 13971a595f28SAnthony Koo * The last possible line SDP may be transmitted without violating 13981a595f28SAnthony Koo * the RFB setup time or entering the active video frame. 13991a595f28SAnthony Koo */ 140078ead771SAnthony Koo uint16_t init_sdp_deadline; 14011a595f28SAnthony Koo /** 14021a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 14031a595f28SAnthony Koo */ 140478ead771SAnthony Koo uint16_t pad2; 14051a595f28SAnthony Koo /** 14061a595f28SAnthony Koo * Length of each horizontal line in us. 14071a595f28SAnthony Koo */ 14089b56f6bcSAnthony Koo uint32_t line_time_in_us; 1409ecc11601SAnthony Koo /** 1410ecc11601SAnthony Koo * FEC enable status in driver 1411ecc11601SAnthony Koo */ 1412ecc11601SAnthony Koo uint8_t fec_enable_status; 1413ecc11601SAnthony Koo /** 1414ecc11601SAnthony Koo * FEC re-enable delay when PSR exit. 1415ecc11601SAnthony Koo * unit is 100us, range form 0~255(0xFF). 1416ecc11601SAnthony Koo */ 1417ecc11601SAnthony Koo uint8_t fec_enable_delay_in100us; 1418ecc11601SAnthony Koo /** 1419f56c837aSMikita Lipski * PSR control version. 1420ecc11601SAnthony Koo */ 1421f56c837aSMikita Lipski uint8_t cmd_version; 1422f56c837aSMikita Lipski /** 1423f56c837aSMikita Lipski * Panel Instance. 1424f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1425f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1426f56c837aSMikita Lipski */ 1427f56c837aSMikita Lipski uint8_t panel_inst; 1428360d1b65SIan Chen /** 1429360d1b65SIan Chen * Explicit padding to 4 byte boundary. 1430360d1b65SIan Chen */ 1431360d1b65SIan Chen uint8_t pad3[4]; 14327c008829SNicholas Kazlauskas }; 14337c008829SNicholas Kazlauskas 14341a595f28SAnthony Koo /** 14351a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 14361a595f28SAnthony Koo */ 14377c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings { 14381a595f28SAnthony Koo /** 14391a595f28SAnthony Koo * Command header. 14401a595f28SAnthony Koo */ 14417c008829SNicholas Kazlauskas struct dmub_cmd_header header; 14421a595f28SAnthony Koo /** 14431a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 14441a595f28SAnthony Koo */ 14457c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 14467c008829SNicholas Kazlauskas }; 14477c008829SNicholas Kazlauskas 14481a595f28SAnthony Koo /** 14491a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 14501a595f28SAnthony Koo */ 14517c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data { 14521a595f28SAnthony Koo /** 14531a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 14541a595f28SAnthony Koo */ 14557c008829SNicholas Kazlauskas uint16_t psr_level; 14561a595f28SAnthony Koo /** 1457f56c837aSMikita Lipski * PSR control version. 14581a595f28SAnthony Koo */ 1459f56c837aSMikita Lipski uint8_t cmd_version; 1460f56c837aSMikita Lipski /** 1461f56c837aSMikita Lipski * Panel Instance. 1462f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1463f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1464f56c837aSMikita Lipski */ 1465f56c837aSMikita Lipski uint8_t panel_inst; 14667c008829SNicholas Kazlauskas }; 14677c008829SNicholas Kazlauskas 14681a595f28SAnthony Koo /** 14691a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 14701a595f28SAnthony Koo */ 14717c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level { 14721a595f28SAnthony Koo /** 14731a595f28SAnthony Koo * Command header. 14741a595f28SAnthony Koo */ 14757c008829SNicholas Kazlauskas struct dmub_cmd_header header; 14761a595f28SAnthony Koo /** 14771a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 14781a595f28SAnthony Koo */ 14797c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data psr_set_level_data; 14807c008829SNicholas Kazlauskas }; 14817c008829SNicholas Kazlauskas 1482f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data { 1483f56c837aSMikita Lipski /** 1484f56c837aSMikita Lipski * PSR control version. 1485f56c837aSMikita Lipski */ 1486f56c837aSMikita Lipski uint8_t cmd_version; 1487f56c837aSMikita Lipski /** 1488f56c837aSMikita Lipski * Panel Instance. 1489f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1490f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1491f56c837aSMikita Lipski */ 1492f56c837aSMikita Lipski uint8_t panel_inst; 1493f56c837aSMikita Lipski /** 1494f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 1495f56c837aSMikita Lipski */ 1496f56c837aSMikita Lipski uint8_t pad[2]; 1497f56c837aSMikita Lipski }; 1498f56c837aSMikita Lipski 14991a595f28SAnthony Koo /** 15001a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 15011a595f28SAnthony Koo * PSR enable/disable is controlled using the sub_type. 15021a595f28SAnthony Koo */ 15037c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_enable { 15041a595f28SAnthony Koo /** 15051a595f28SAnthony Koo * Command header. 15061a595f28SAnthony Koo */ 15077c008829SNicholas Kazlauskas struct dmub_cmd_header header; 1508f56c837aSMikita Lipski 1509f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data data; 15107c008829SNicholas Kazlauskas }; 15117c008829SNicholas Kazlauskas 15121a595f28SAnthony Koo /** 15131a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 15141a595f28SAnthony Koo */ 1515d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data { 15161a595f28SAnthony Koo /** 15171a595f28SAnthony Koo * PSR version that FW should implement. 15181a595f28SAnthony Koo */ 15191a595f28SAnthony Koo enum psr_version version; 1520f56c837aSMikita Lipski /** 1521f56c837aSMikita Lipski * PSR control version. 1522f56c837aSMikita Lipski */ 1523f56c837aSMikita Lipski uint8_t cmd_version; 1524f56c837aSMikita Lipski /** 1525f56c837aSMikita Lipski * Panel Instance. 1526f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1527f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1528f56c837aSMikita Lipski */ 1529f56c837aSMikita Lipski uint8_t panel_inst; 1530f56c837aSMikita Lipski /** 1531f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 1532f56c837aSMikita Lipski */ 1533f56c837aSMikita Lipski uint8_t pad[2]; 15347c008829SNicholas Kazlauskas }; 15357c008829SNicholas Kazlauskas 15361a595f28SAnthony Koo /** 15371a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 15381a595f28SAnthony Koo */ 1539d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version { 15401a595f28SAnthony Koo /** 15411a595f28SAnthony Koo * Command header. 15421a595f28SAnthony Koo */ 15437c008829SNicholas Kazlauskas struct dmub_cmd_header header; 15441a595f28SAnthony Koo /** 15451a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 15461a595f28SAnthony Koo */ 1547d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data psr_set_version_data; 15487c008829SNicholas Kazlauskas }; 15497c008829SNicholas Kazlauskas 1550f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data { 1551f56c837aSMikita Lipski /** 1552f56c837aSMikita Lipski * PSR control version. 1553f56c837aSMikita Lipski */ 1554f56c837aSMikita Lipski uint8_t cmd_version; 1555f56c837aSMikita Lipski /** 1556f56c837aSMikita Lipski * Panel Instance. 1557f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1558f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1559f56c837aSMikita Lipski */ 1560f56c837aSMikita Lipski uint8_t panel_inst; 1561f56c837aSMikita Lipski /** 1562f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 1563f56c837aSMikita Lipski */ 1564f56c837aSMikita Lipski uint8_t pad[2]; 1565f56c837aSMikita Lipski }; 1566f56c837aSMikita Lipski 15671a595f28SAnthony Koo /** 15681a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 15691a595f28SAnthony Koo */ 1570672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static { 15711a595f28SAnthony Koo /** 15721a595f28SAnthony Koo * Command header. 15731a595f28SAnthony Koo */ 1574672251b2SAnthony Koo struct dmub_cmd_header header; 1575f56c837aSMikita Lipski /** 1576f56c837aSMikita Lipski * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1577f56c837aSMikita Lipski */ 1578f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data psr_force_static_data; 1579672251b2SAnthony Koo }; 1580672251b2SAnthony Koo 15811a595f28SAnthony Koo /** 15821a595f28SAnthony Koo * Set of HW components that can be locked. 15830b51e7e8SAnthony Koo * 15840b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 15850b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 15861a595f28SAnthony Koo */ 1587788408b7SAnthony Koo union dmub_hw_lock_flags { 15881a595f28SAnthony Koo /** 15891a595f28SAnthony Koo * Set of HW components that can be locked. 15901a595f28SAnthony Koo */ 1591788408b7SAnthony Koo struct { 15921a595f28SAnthony Koo /** 15931a595f28SAnthony Koo * Lock/unlock OTG master update lock. 15941a595f28SAnthony Koo */ 1595788408b7SAnthony Koo uint8_t lock_pipe : 1; 15961a595f28SAnthony Koo /** 15971a595f28SAnthony Koo * Lock/unlock cursor. 15981a595f28SAnthony Koo */ 1599788408b7SAnthony Koo uint8_t lock_cursor : 1; 16001a595f28SAnthony Koo /** 16011a595f28SAnthony Koo * Lock/unlock global update lock. 16021a595f28SAnthony Koo */ 1603788408b7SAnthony Koo uint8_t lock_dig : 1; 16041a595f28SAnthony Koo /** 16051a595f28SAnthony Koo * Triple buffer lock requires additional hw programming to usual OTG master lock. 16061a595f28SAnthony Koo */ 1607788408b7SAnthony Koo uint8_t triple_buffer_lock : 1; 1608788408b7SAnthony Koo } bits; 1609788408b7SAnthony Koo 16101a595f28SAnthony Koo /** 16111a595f28SAnthony Koo * Union for HW Lock flags. 16121a595f28SAnthony Koo */ 1613788408b7SAnthony Koo uint8_t u8All; 1614788408b7SAnthony Koo }; 1615788408b7SAnthony Koo 16161a595f28SAnthony Koo /** 16171a595f28SAnthony Koo * Instances of HW to be locked. 16180b51e7e8SAnthony Koo * 16190b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 16200b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 16211a595f28SAnthony Koo */ 1622788408b7SAnthony Koo struct dmub_hw_lock_inst_flags { 16231a595f28SAnthony Koo /** 16241a595f28SAnthony Koo * OTG HW instance for OTG master update lock. 16251a595f28SAnthony Koo */ 1626788408b7SAnthony Koo uint8_t otg_inst; 16271a595f28SAnthony Koo /** 16281a595f28SAnthony Koo * OPP instance for cursor lock. 16291a595f28SAnthony Koo */ 1630788408b7SAnthony Koo uint8_t opp_inst; 16311a595f28SAnthony Koo /** 16321a595f28SAnthony Koo * OTG HW instance for global update lock. 16331a595f28SAnthony Koo * TODO: Remove, and re-use otg_inst. 16341a595f28SAnthony Koo */ 1635788408b7SAnthony Koo uint8_t dig_inst; 16361a595f28SAnthony Koo /** 16371a595f28SAnthony Koo * Explicit pad to 4 byte boundary. 16381a595f28SAnthony Koo */ 1639788408b7SAnthony Koo uint8_t pad; 1640788408b7SAnthony Koo }; 1641788408b7SAnthony Koo 16421a595f28SAnthony Koo /** 16431a595f28SAnthony Koo * Clients that can acquire the HW Lock Manager. 16440b51e7e8SAnthony Koo * 16450b51e7e8SAnthony Koo * Note: If updating with more clients, fields in 16460b51e7e8SAnthony Koo * dmub_inbox0_cmd_lock_hw must be updated to match. 16471a595f28SAnthony Koo */ 1648788408b7SAnthony Koo enum hw_lock_client { 16491a595f28SAnthony Koo /** 16501a595f28SAnthony Koo * Driver is the client of HW Lock Manager. 16511a595f28SAnthony Koo */ 1652788408b7SAnthony Koo HW_LOCK_CLIENT_DRIVER = 0, 16531a595f28SAnthony Koo /** 16541a595f28SAnthony Koo * Invalid client. 16551a595f28SAnthony Koo */ 1656788408b7SAnthony Koo HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1657788408b7SAnthony Koo }; 1658788408b7SAnthony Koo 16591a595f28SAnthony Koo /** 16601a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 16611a595f28SAnthony Koo */ 1662788408b7SAnthony Koo struct dmub_cmd_lock_hw_data { 16631a595f28SAnthony Koo /** 16641a595f28SAnthony Koo * Specifies the client accessing HW Lock Manager. 16651a595f28SAnthony Koo */ 1666788408b7SAnthony Koo enum hw_lock_client client; 16671a595f28SAnthony Koo /** 16681a595f28SAnthony Koo * HW instances to be locked. 16691a595f28SAnthony Koo */ 1670788408b7SAnthony Koo struct dmub_hw_lock_inst_flags inst_flags; 16711a595f28SAnthony Koo /** 16721a595f28SAnthony Koo * Which components to be locked. 16731a595f28SAnthony Koo */ 1674788408b7SAnthony Koo union dmub_hw_lock_flags hw_locks; 16751a595f28SAnthony Koo /** 16761a595f28SAnthony Koo * Specifies lock/unlock. 16771a595f28SAnthony Koo */ 1678788408b7SAnthony Koo uint8_t lock; 16791a595f28SAnthony Koo /** 16801a595f28SAnthony Koo * HW can be unlocked separately from releasing the HW Lock Mgr. 16811a595f28SAnthony Koo * This flag is set if the client wishes to release the object. 16821a595f28SAnthony Koo */ 1683788408b7SAnthony Koo uint8_t should_release; 16841a595f28SAnthony Koo /** 16851a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 16861a595f28SAnthony Koo */ 1687788408b7SAnthony Koo uint8_t pad; 1688788408b7SAnthony Koo }; 1689788408b7SAnthony Koo 16901a595f28SAnthony Koo /** 16911a595f28SAnthony Koo * Definition of a DMUB_CMD__HW_LOCK command. 16921a595f28SAnthony Koo * Command is used by driver and FW. 16931a595f28SAnthony Koo */ 1694788408b7SAnthony Koo struct dmub_rb_cmd_lock_hw { 16951a595f28SAnthony Koo /** 16961a595f28SAnthony Koo * Command header. 16971a595f28SAnthony Koo */ 1698788408b7SAnthony Koo struct dmub_cmd_header header; 16991a595f28SAnthony Koo /** 17001a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 17011a595f28SAnthony Koo */ 1702788408b7SAnthony Koo struct dmub_cmd_lock_hw_data lock_hw_data; 1703788408b7SAnthony Koo }; 1704788408b7SAnthony Koo 17051a595f28SAnthony Koo /** 17061a595f28SAnthony Koo * ABM command sub-types. 17071a595f28SAnthony Koo */ 170884034ad4SAnthony Koo enum dmub_cmd_abm_type { 17091a595f28SAnthony Koo /** 17101a595f28SAnthony Koo * Initialize parameters for ABM algorithm. 17111a595f28SAnthony Koo * Data is passed through an indirect buffer. 17121a595f28SAnthony Koo */ 171384034ad4SAnthony Koo DMUB_CMD__ABM_INIT_CONFIG = 0, 17141a595f28SAnthony Koo /** 17151a595f28SAnthony Koo * Set OTG and panel HW instance. 17161a595f28SAnthony Koo */ 171784034ad4SAnthony Koo DMUB_CMD__ABM_SET_PIPE = 1, 17181a595f28SAnthony Koo /** 17191a595f28SAnthony Koo * Set user requested backklight level. 17201a595f28SAnthony Koo */ 172184034ad4SAnthony Koo DMUB_CMD__ABM_SET_BACKLIGHT = 2, 17221a595f28SAnthony Koo /** 17231a595f28SAnthony Koo * Set ABM operating/aggression level. 17241a595f28SAnthony Koo */ 172584034ad4SAnthony Koo DMUB_CMD__ABM_SET_LEVEL = 3, 17261a595f28SAnthony Koo /** 17271a595f28SAnthony Koo * Set ambient light level. 17281a595f28SAnthony Koo */ 172984034ad4SAnthony Koo DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 17301a595f28SAnthony Koo /** 17311a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 17321a595f28SAnthony Koo */ 173384034ad4SAnthony Koo DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1734*b629a824SEric Yang 1735*b629a824SEric Yang /** 1736*b629a824SEric Yang * unregister vertical interrupt after steady state is reached 1737*b629a824SEric Yang */ 1738*b629a824SEric Yang DMUB_CMD__ABM_PAUSE = 6, 173984034ad4SAnthony Koo }; 174084034ad4SAnthony Koo 17411a595f28SAnthony Koo /** 17421a595f28SAnthony Koo * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 17431a595f28SAnthony Koo * Requirements: 17441a595f28SAnthony Koo * - Padded explicitly to 32-bit boundary. 17451a595f28SAnthony Koo * - Must ensure this structure matches the one on driver-side, 17461a595f28SAnthony Koo * otherwise it won't be aligned. 174784034ad4SAnthony Koo */ 174884034ad4SAnthony Koo struct abm_config_table { 17491a595f28SAnthony Koo /** 17501a595f28SAnthony Koo * Gamma curve thresholds, used for crgb conversion. 17511a595f28SAnthony Koo */ 175284034ad4SAnthony Koo uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 17531a595f28SAnthony Koo /** 17541a595f28SAnthony Koo * Gamma curve offsets, used for crgb conversion. 17551a595f28SAnthony Koo */ 1756b6402afeSAnthony Koo uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 17571a595f28SAnthony Koo /** 17581a595f28SAnthony Koo * Gamma curve slopes, used for crgb conversion. 17591a595f28SAnthony Koo */ 1760b6402afeSAnthony Koo uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 17611a595f28SAnthony Koo /** 17621a595f28SAnthony Koo * Custom backlight curve thresholds. 17631a595f28SAnthony Koo */ 1764b6402afeSAnthony Koo uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 17651a595f28SAnthony Koo /** 17661a595f28SAnthony Koo * Custom backlight curve offsets. 17671a595f28SAnthony Koo */ 1768b6402afeSAnthony Koo uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 17691a595f28SAnthony Koo /** 17701a595f28SAnthony Koo * Ambient light thresholds. 17711a595f28SAnthony Koo */ 1772b6402afeSAnthony Koo uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 17731a595f28SAnthony Koo /** 17741a595f28SAnthony Koo * Minimum programmable backlight. 17751a595f28SAnthony Koo */ 1776b6402afeSAnthony Koo uint16_t min_abm_backlight; // 122B 17771a595f28SAnthony Koo /** 17781a595f28SAnthony Koo * Minimum reduction values. 17791a595f28SAnthony Koo */ 1780b6402afeSAnthony Koo uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 17811a595f28SAnthony Koo /** 17821a595f28SAnthony Koo * Maximum reduction values. 17831a595f28SAnthony Koo */ 1784b6402afeSAnthony Koo uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 17851a595f28SAnthony Koo /** 17861a595f28SAnthony Koo * Bright positive gain. 17871a595f28SAnthony Koo */ 1788b6402afeSAnthony Koo uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 17891a595f28SAnthony Koo /** 17901a595f28SAnthony Koo * Dark negative gain. 17911a595f28SAnthony Koo */ 1792b6402afeSAnthony Koo uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 17931a595f28SAnthony Koo /** 17941a595f28SAnthony Koo * Hybrid factor. 17951a595f28SAnthony Koo */ 1796b6402afeSAnthony Koo uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 17971a595f28SAnthony Koo /** 17981a595f28SAnthony Koo * Contrast factor. 17991a595f28SAnthony Koo */ 1800b6402afeSAnthony Koo uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 18011a595f28SAnthony Koo /** 18021a595f28SAnthony Koo * Deviation gain. 18031a595f28SAnthony Koo */ 1804b6402afeSAnthony Koo uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 18051a595f28SAnthony Koo /** 18061a595f28SAnthony Koo * Minimum knee. 18071a595f28SAnthony Koo */ 1808b6402afeSAnthony Koo uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 18091a595f28SAnthony Koo /** 18101a595f28SAnthony Koo * Maximum knee. 18111a595f28SAnthony Koo */ 1812b6402afeSAnthony Koo uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 18131a595f28SAnthony Koo /** 18141a595f28SAnthony Koo * Unused. 18151a595f28SAnthony Koo */ 1816b6402afeSAnthony Koo uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 18171a595f28SAnthony Koo /** 18181a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 18191a595f28SAnthony Koo */ 1820b6402afeSAnthony Koo uint8_t pad3[3]; // 229B 18211a595f28SAnthony Koo /** 18221a595f28SAnthony Koo * Backlight ramp reduction. 18231a595f28SAnthony Koo */ 1824b6402afeSAnthony Koo uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 18251a595f28SAnthony Koo /** 18261a595f28SAnthony Koo * Backlight ramp start. 18271a595f28SAnthony Koo */ 1828b6402afeSAnthony Koo uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 182984034ad4SAnthony Koo }; 183084034ad4SAnthony Koo 18311a595f28SAnthony Koo /** 18321a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 18331a595f28SAnthony Koo */ 1834e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data { 18351a595f28SAnthony Koo /** 18361a595f28SAnthony Koo * OTG HW instance. 18371a595f28SAnthony Koo */ 18387b8a6362SAnthony Koo uint8_t otg_inst; 18391a595f28SAnthony Koo 18401a595f28SAnthony Koo /** 18411a595f28SAnthony Koo * Panel Control HW instance. 18421a595f28SAnthony Koo */ 18437b8a6362SAnthony Koo uint8_t panel_inst; 18441a595f28SAnthony Koo 18451a595f28SAnthony Koo /** 18461a595f28SAnthony Koo * Controls how ABM will interpret a set pipe or set level command. 18471a595f28SAnthony Koo */ 18487b8a6362SAnthony Koo uint8_t set_pipe_option; 18491a595f28SAnthony Koo 18501a595f28SAnthony Koo /** 18511a595f28SAnthony Koo * Unused. 18521a595f28SAnthony Koo * TODO: Remove. 18531a595f28SAnthony Koo */ 18541a595f28SAnthony Koo uint8_t ramping_boundary; 1855e6ea8c34SWyatt Wood }; 1856e6ea8c34SWyatt Wood 18571a595f28SAnthony Koo /** 18581a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 18591a595f28SAnthony Koo */ 1860e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe { 18611a595f28SAnthony Koo /** 18621a595f28SAnthony Koo * Command header. 18631a595f28SAnthony Koo */ 1864e6ea8c34SWyatt Wood struct dmub_cmd_header header; 18651a595f28SAnthony Koo 18661a595f28SAnthony Koo /** 18671a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 18681a595f28SAnthony Koo */ 1869e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 1870e6ea8c34SWyatt Wood }; 1871e6ea8c34SWyatt Wood 18721a595f28SAnthony Koo /** 18731a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 18741a595f28SAnthony Koo */ 1875e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data { 18761a595f28SAnthony Koo /** 18771a595f28SAnthony Koo * Number of frames to ramp to backlight user level. 18781a595f28SAnthony Koo */ 1879e6ea8c34SWyatt Wood uint32_t frame_ramp; 18801a595f28SAnthony Koo 18811a595f28SAnthony Koo /** 18821a595f28SAnthony Koo * Requested backlight level from user. 18831a595f28SAnthony Koo */ 1884474ac4a8SYongqiang Sun uint32_t backlight_user_level; 1885e922057bSJake Wang 1886e922057bSJake Wang /** 188763de4f04SJake Wang * ABM control version. 1888e922057bSJake Wang */ 1889e922057bSJake Wang uint8_t version; 1890e922057bSJake Wang 1891e922057bSJake Wang /** 1892e922057bSJake Wang * Panel Control HW instance mask. 1893e922057bSJake Wang * Bit 0 is Panel Control HW instance 0. 1894e922057bSJake Wang * Bit 1 is Panel Control HW instance 1. 1895e922057bSJake Wang */ 1896e922057bSJake Wang uint8_t panel_mask; 1897e922057bSJake Wang 1898e922057bSJake Wang /** 1899e922057bSJake Wang * Explicit padding to 4 byte boundary. 1900e922057bSJake Wang */ 1901e922057bSJake Wang uint8_t pad[2]; 1902e6ea8c34SWyatt Wood }; 1903e6ea8c34SWyatt Wood 19041a595f28SAnthony Koo /** 19051a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 19061a595f28SAnthony Koo */ 1907e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight { 19081a595f28SAnthony Koo /** 19091a595f28SAnthony Koo * Command header. 19101a595f28SAnthony Koo */ 1911e6ea8c34SWyatt Wood struct dmub_cmd_header header; 19121a595f28SAnthony Koo 19131a595f28SAnthony Koo /** 19141a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 19151a595f28SAnthony Koo */ 1916e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 1917e6ea8c34SWyatt Wood }; 1918e6ea8c34SWyatt Wood 19191a595f28SAnthony Koo /** 19201a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 19211a595f28SAnthony Koo */ 1922e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data { 19231a595f28SAnthony Koo /** 19241a595f28SAnthony Koo * Set current ABM operating/aggression level. 19251a595f28SAnthony Koo */ 1926e6ea8c34SWyatt Wood uint32_t level; 192763de4f04SJake Wang 192863de4f04SJake Wang /** 192963de4f04SJake Wang * ABM control version. 193063de4f04SJake Wang */ 193163de4f04SJake Wang uint8_t version; 193263de4f04SJake Wang 193363de4f04SJake Wang /** 193463de4f04SJake Wang * Panel Control HW instance mask. 193563de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 193663de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 193763de4f04SJake Wang */ 193863de4f04SJake Wang uint8_t panel_mask; 193963de4f04SJake Wang 194063de4f04SJake Wang /** 194163de4f04SJake Wang * Explicit padding to 4 byte boundary. 194263de4f04SJake Wang */ 194363de4f04SJake Wang uint8_t pad[2]; 1944e6ea8c34SWyatt Wood }; 1945e6ea8c34SWyatt Wood 19461a595f28SAnthony Koo /** 19471a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 19481a595f28SAnthony Koo */ 1949e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level { 19501a595f28SAnthony Koo /** 19511a595f28SAnthony Koo * Command header. 19521a595f28SAnthony Koo */ 1953e6ea8c34SWyatt Wood struct dmub_cmd_header header; 19541a595f28SAnthony Koo 19551a595f28SAnthony Koo /** 19561a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 19571a595f28SAnthony Koo */ 1958e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data abm_set_level_data; 1959e6ea8c34SWyatt Wood }; 1960e6ea8c34SWyatt Wood 19611a595f28SAnthony Koo /** 19621a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 19631a595f28SAnthony Koo */ 1964e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data { 19651a595f28SAnthony Koo /** 19661a595f28SAnthony Koo * Ambient light sensor reading from OS. 19671a595f28SAnthony Koo */ 1968e6ea8c34SWyatt Wood uint32_t ambient_lux; 196963de4f04SJake Wang 197063de4f04SJake Wang /** 197163de4f04SJake Wang * ABM control version. 197263de4f04SJake Wang */ 197363de4f04SJake Wang uint8_t version; 197463de4f04SJake Wang 197563de4f04SJake Wang /** 197663de4f04SJake Wang * Panel Control HW instance mask. 197763de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 197863de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 197963de4f04SJake Wang */ 198063de4f04SJake Wang uint8_t panel_mask; 198163de4f04SJake Wang 198263de4f04SJake Wang /** 198363de4f04SJake Wang * Explicit padding to 4 byte boundary. 198463de4f04SJake Wang */ 198563de4f04SJake Wang uint8_t pad[2]; 1986e6ea8c34SWyatt Wood }; 1987e6ea8c34SWyatt Wood 19881a595f28SAnthony Koo /** 19891a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 19901a595f28SAnthony Koo */ 1991e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level { 19921a595f28SAnthony Koo /** 19931a595f28SAnthony Koo * Command header. 19941a595f28SAnthony Koo */ 1995e6ea8c34SWyatt Wood struct dmub_cmd_header header; 19961a595f28SAnthony Koo 19971a595f28SAnthony Koo /** 19981a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 19991a595f28SAnthony Koo */ 2000e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2001e6ea8c34SWyatt Wood }; 2002e6ea8c34SWyatt Wood 20031a595f28SAnthony Koo /** 20041a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 20051a595f28SAnthony Koo */ 2006e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data { 20071a595f28SAnthony Koo /** 20081a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 20091a595f28SAnthony Koo * TODO: Convert to uint8_t. 20101a595f28SAnthony Koo */ 2011e6ea8c34SWyatt Wood uint32_t fractional_pwm; 201263de4f04SJake Wang 201363de4f04SJake Wang /** 201463de4f04SJake Wang * ABM control version. 201563de4f04SJake Wang */ 201663de4f04SJake Wang uint8_t version; 201763de4f04SJake Wang 201863de4f04SJake Wang /** 201963de4f04SJake Wang * Panel Control HW instance mask. 202063de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 202163de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 202263de4f04SJake Wang */ 202363de4f04SJake Wang uint8_t panel_mask; 202463de4f04SJake Wang 202563de4f04SJake Wang /** 202663de4f04SJake Wang * Explicit padding to 4 byte boundary. 202763de4f04SJake Wang */ 202863de4f04SJake Wang uint8_t pad[2]; 2029e6ea8c34SWyatt Wood }; 2030e6ea8c34SWyatt Wood 20311a595f28SAnthony Koo /** 20321a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 20331a595f28SAnthony Koo */ 2034e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac { 20351a595f28SAnthony Koo /** 20361a595f28SAnthony Koo * Command header. 20371a595f28SAnthony Koo */ 2038e6ea8c34SWyatt Wood struct dmub_cmd_header header; 20391a595f28SAnthony Koo 20401a595f28SAnthony Koo /** 20411a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 20421a595f28SAnthony Koo */ 2043e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2044e6ea8c34SWyatt Wood }; 2045e6ea8c34SWyatt Wood 20461a595f28SAnthony Koo /** 20471a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 20481a595f28SAnthony Koo */ 204916012806SWyatt Wood struct dmub_cmd_abm_init_config_data { 20501a595f28SAnthony Koo /** 20511a595f28SAnthony Koo * Location of indirect buffer used to pass init data to ABM. 20521a595f28SAnthony Koo */ 205316012806SWyatt Wood union dmub_addr src; 20541a595f28SAnthony Koo 20551a595f28SAnthony Koo /** 20561a595f28SAnthony Koo * Indirect buffer length. 20571a595f28SAnthony Koo */ 205816012806SWyatt Wood uint16_t bytes; 205963de4f04SJake Wang 206063de4f04SJake Wang 206163de4f04SJake Wang /** 206263de4f04SJake Wang * ABM control version. 206363de4f04SJake Wang */ 206463de4f04SJake Wang uint8_t version; 206563de4f04SJake Wang 206663de4f04SJake Wang /** 206763de4f04SJake Wang * Panel Control HW instance mask. 206863de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 206963de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 207063de4f04SJake Wang */ 207163de4f04SJake Wang uint8_t panel_mask; 207263de4f04SJake Wang 207363de4f04SJake Wang /** 207463de4f04SJake Wang * Explicit padding to 4 byte boundary. 207563de4f04SJake Wang */ 207663de4f04SJake Wang uint8_t pad[2]; 207716012806SWyatt Wood }; 207816012806SWyatt Wood 20791a595f28SAnthony Koo /** 20801a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 20811a595f28SAnthony Koo */ 208216012806SWyatt Wood struct dmub_rb_cmd_abm_init_config { 20831a595f28SAnthony Koo /** 20841a595f28SAnthony Koo * Command header. 20851a595f28SAnthony Koo */ 208616012806SWyatt Wood struct dmub_cmd_header header; 20871a595f28SAnthony Koo 20881a595f28SAnthony Koo /** 20891a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 20901a595f28SAnthony Koo */ 209116012806SWyatt Wood struct dmub_cmd_abm_init_config_data abm_init_config_data; 209216012806SWyatt Wood }; 209316012806SWyatt Wood 20941a595f28SAnthony Koo /** 2095*b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2096*b629a824SEric Yang */ 2097*b629a824SEric Yang 2098*b629a824SEric Yang struct dmub_cmd_abm_pause_data { 2099*b629a824SEric Yang 2100*b629a824SEric Yang /** 2101*b629a824SEric Yang * Panel Control HW instance mask. 2102*b629a824SEric Yang * Bit 0 is Panel Control HW instance 0. 2103*b629a824SEric Yang * Bit 1 is Panel Control HW instance 1. 2104*b629a824SEric Yang */ 2105*b629a824SEric Yang uint8_t panel_mask; 2106*b629a824SEric Yang 2107*b629a824SEric Yang /** 2108*b629a824SEric Yang * OTG hw instance 2109*b629a824SEric Yang */ 2110*b629a824SEric Yang uint8_t otg_inst; 2111*b629a824SEric Yang 2112*b629a824SEric Yang /** 2113*b629a824SEric Yang * Enable or disable ABM pause 2114*b629a824SEric Yang */ 2115*b629a824SEric Yang uint8_t enable; 2116*b629a824SEric Yang 2117*b629a824SEric Yang /** 2118*b629a824SEric Yang * Explicit padding to 4 byte boundary. 2119*b629a824SEric Yang */ 2120*b629a824SEric Yang uint8_t pad[1]; 2121*b629a824SEric Yang }; 2122*b629a824SEric Yang 2123*b629a824SEric Yang /** 2124*b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 2125*b629a824SEric Yang */ 2126*b629a824SEric Yang struct dmub_rb_cmd_abm_pause { 2127*b629a824SEric Yang /** 2128*b629a824SEric Yang * Command header. 2129*b629a824SEric Yang */ 2130*b629a824SEric Yang struct dmub_cmd_header header; 2131*b629a824SEric Yang 2132*b629a824SEric Yang /** 2133*b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2134*b629a824SEric Yang */ 2135*b629a824SEric Yang struct dmub_cmd_abm_pause_data abm_pause_data; 2136*b629a824SEric Yang }; 2137*b629a824SEric Yang 2138*b629a824SEric Yang /** 21391a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 21401a595f28SAnthony Koo */ 214134ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data { 21421a595f28SAnthony Koo /** 21431a595f28SAnthony Koo * DMUB feature capabilities. 21441a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features. 21451a595f28SAnthony Koo */ 214634ba432cSAnthony Koo struct dmub_feature_caps feature_caps; 214734ba432cSAnthony Koo }; 214834ba432cSAnthony Koo 21491a595f28SAnthony Koo /** 21501a595f28SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 21511a595f28SAnthony Koo */ 215234ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps { 21531a595f28SAnthony Koo /** 21541a595f28SAnthony Koo * Command header. 21551a595f28SAnthony Koo */ 215634ba432cSAnthony Koo struct dmub_cmd_header header; 21571a595f28SAnthony Koo /** 21581a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 21591a595f28SAnthony Koo */ 216034ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 216134ba432cSAnthony Koo }; 216234ba432cSAnthony Koo 2163592a6318SAnthony Koo struct dmub_optc_state { 2164592a6318SAnthony Koo uint32_t v_total_max; 2165592a6318SAnthony Koo uint32_t v_total_min; 2166592a6318SAnthony Koo uint32_t v_total_mid; 2167592a6318SAnthony Koo uint32_t v_total_mid_frame_num; 2168592a6318SAnthony Koo uint32_t tg_inst; 2169592a6318SAnthony Koo uint32_t enable_manual_trigger; 2170592a6318SAnthony Koo uint32_t clear_force_vsync; 2171592a6318SAnthony Koo }; 2172592a6318SAnthony Koo 2173592a6318SAnthony Koo struct dmub_rb_cmd_drr_update { 2174592a6318SAnthony Koo struct dmub_cmd_header header; 2175592a6318SAnthony Koo struct dmub_optc_state dmub_optc_state_req; 2176592a6318SAnthony Koo }; 2177592a6318SAnthony Koo 2178b04cb192SNicholas Kazlauskas /** 2179b04cb192SNicholas Kazlauskas * enum dmub_cmd_panel_cntl_type - Panel control command. 2180b04cb192SNicholas Kazlauskas */ 2181b04cb192SNicholas Kazlauskas enum dmub_cmd_panel_cntl_type { 2182b04cb192SNicholas Kazlauskas /** 2183b04cb192SNicholas Kazlauskas * Initializes embedded panel hardware blocks. 2184b04cb192SNicholas Kazlauskas */ 2185b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2186b04cb192SNicholas Kazlauskas /** 2187b04cb192SNicholas Kazlauskas * Queries backlight info for the embedded panel. 2188b04cb192SNicholas Kazlauskas */ 2189b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2190b04cb192SNicholas Kazlauskas }; 2191b04cb192SNicholas Kazlauskas 2192b04cb192SNicholas Kazlauskas /** 2193b04cb192SNicholas Kazlauskas * struct dmub_cmd_panel_cntl_data - Panel control data. 2194b04cb192SNicholas Kazlauskas */ 2195b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data { 2196b04cb192SNicholas Kazlauskas uint32_t inst; /**< panel instance */ 2197b04cb192SNicholas Kazlauskas uint32_t current_backlight; /* in/out */ 2198b04cb192SNicholas Kazlauskas uint32_t bl_pwm_cntl; /* in/out */ 2199b04cb192SNicholas Kazlauskas uint32_t bl_pwm_period_cntl; /* in/out */ 2200b04cb192SNicholas Kazlauskas uint32_t bl_pwm_ref_div1; /* in/out */ 2201b04cb192SNicholas Kazlauskas uint8_t is_backlight_on : 1; /* in/out */ 2202b04cb192SNicholas Kazlauskas uint8_t is_powered_on : 1; /* in/out */ 2203b04cb192SNicholas Kazlauskas }; 2204b04cb192SNicholas Kazlauskas 2205b04cb192SNicholas Kazlauskas /** 2206b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_panel_cntl - Panel control command. 2207b04cb192SNicholas Kazlauskas */ 2208b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl { 2209b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 2210b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data data; /**< payload */ 2211b04cb192SNicholas Kazlauskas }; 2212b04cb192SNicholas Kazlauskas 22131a595f28SAnthony Koo /** 22141a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 22151a595f28SAnthony Koo */ 22161a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data { 22171a595f28SAnthony Koo uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 22181a595f28SAnthony Koo uint8_t reserved_0[3]; /**< For future use */ 22191a595f28SAnthony Koo uint8_t panel_inst; /**< LVTMA control instance */ 22201a595f28SAnthony Koo uint8_t reserved_1[3]; /**< For future use */ 22211a595f28SAnthony Koo }; 22221a595f28SAnthony Koo 22231a595f28SAnthony Koo /** 22241a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 22251a595f28SAnthony Koo */ 22261a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control { 22271a595f28SAnthony Koo /** 22281a595f28SAnthony Koo * Command header. 22291a595f28SAnthony Koo */ 22301a595f28SAnthony Koo struct dmub_cmd_header header; 22311a595f28SAnthony Koo /** 22321a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 22331a595f28SAnthony Koo */ 22341a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data data; 22351a595f28SAnthony Koo }; 22361a595f28SAnthony Koo 2237592a6318SAnthony Koo /** 2238021eaef8SAnthony Koo * Maximum number of bytes a chunk sent to DMUB for parsing 2239021eaef8SAnthony Koo */ 2240021eaef8SAnthony Koo #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2241021eaef8SAnthony Koo 2242021eaef8SAnthony Koo /** 2243021eaef8SAnthony Koo * Represent a chunk of CEA blocks sent to DMUB for parsing 2244021eaef8SAnthony Koo */ 2245021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea { 2246021eaef8SAnthony Koo uint16_t offset; /**< offset into the CEA block */ 2247021eaef8SAnthony Koo uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2248021eaef8SAnthony Koo uint16_t total_length; /**< total length of the CEA block */ 2249021eaef8SAnthony Koo uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2250021eaef8SAnthony Koo uint8_t pad[3]; /**< padding and for future expansion */ 2251021eaef8SAnthony Koo }; 2252021eaef8SAnthony Koo 2253021eaef8SAnthony Koo /** 2254021eaef8SAnthony Koo * Result of VSDB parsing from CEA block 2255021eaef8SAnthony Koo */ 2256021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb { 2257021eaef8SAnthony Koo uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2258021eaef8SAnthony Koo uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2259021eaef8SAnthony Koo uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2260021eaef8SAnthony Koo uint16_t min_frame_rate; /**< Maximum frame rate */ 2261021eaef8SAnthony Koo uint16_t max_frame_rate; /**< Minimum frame rate */ 2262021eaef8SAnthony Koo }; 2263021eaef8SAnthony Koo 2264021eaef8SAnthony Koo /** 2265021eaef8SAnthony Koo * Result of sending a CEA chunk 2266021eaef8SAnthony Koo */ 2267021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack { 2268021eaef8SAnthony Koo uint16_t offset; /**< offset of the chunk into the CEA block */ 2269021eaef8SAnthony Koo uint8_t success; /**< 1 if this sending of chunk succeeded */ 2270021eaef8SAnthony Koo uint8_t pad; /**< padding and for future expansion */ 2271021eaef8SAnthony Koo }; 2272021eaef8SAnthony Koo 2273021eaef8SAnthony Koo /** 2274021eaef8SAnthony Koo * Specify whether the result is an ACK/NACK or the parsing has finished 2275021eaef8SAnthony Koo */ 2276021eaef8SAnthony Koo enum dmub_cmd_edid_cea_reply_type { 2277021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2278021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2279021eaef8SAnthony Koo }; 2280021eaef8SAnthony Koo 2281021eaef8SAnthony Koo /** 2282021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 2283021eaef8SAnthony Koo */ 2284021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea { 2285021eaef8SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 2286021eaef8SAnthony Koo union dmub_cmd_edid_cea_data { 2287021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2288021eaef8SAnthony Koo struct dmub_cmd_edid_cea_output { /**< output with results */ 2289021eaef8SAnthony Koo uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2290021eaef8SAnthony Koo union { 2291021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2292021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack ack; 2293021eaef8SAnthony Koo }; 2294021eaef8SAnthony Koo } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2295021eaef8SAnthony Koo } data; /**< Command data */ 2296021eaef8SAnthony Koo 2297021eaef8SAnthony Koo }; 2298021eaef8SAnthony Koo 2299021eaef8SAnthony Koo /** 2300592a6318SAnthony Koo * union dmub_rb_cmd - DMUB inbox command. 2301592a6318SAnthony Koo */ 23027c008829SNicholas Kazlauskas union dmub_rb_cmd { 2303dc6e2448SWyatt Wood struct dmub_rb_cmd_lock_hw lock_hw; 2304592a6318SAnthony Koo /** 2305592a6318SAnthony Koo * Elements shared with all commands. 2306592a6318SAnthony Koo */ 23077c008829SNicholas Kazlauskas struct dmub_rb_cmd_common cmd_common; 2308592a6318SAnthony Koo /** 2309592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2310592a6318SAnthony Koo */ 2311592a6318SAnthony Koo struct dmub_rb_cmd_read_modify_write read_modify_write; 2312592a6318SAnthony Koo /** 2313592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2314592a6318SAnthony Koo */ 2315592a6318SAnthony Koo struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2316592a6318SAnthony Koo /** 2317592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2318592a6318SAnthony Koo */ 2319592a6318SAnthony Koo struct dmub_rb_cmd_burst_write burst_write; 2320592a6318SAnthony Koo /** 2321592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_REG_WAIT command. 2322592a6318SAnthony Koo */ 2323592a6318SAnthony Koo struct dmub_rb_cmd_reg_wait reg_wait; 2324592a6318SAnthony Koo /** 2325592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2326592a6318SAnthony Koo */ 23277c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2328592a6318SAnthony Koo /** 2329592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2330592a6318SAnthony Koo */ 23317c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2332592a6318SAnthony Koo /** 2333592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2334592a6318SAnthony Koo */ 23357c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2336592a6318SAnthony Koo /** 2337592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2338592a6318SAnthony Koo */ 23397c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init dpphy_init; 2340592a6318SAnthony Koo /** 2341592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2342592a6318SAnthony Koo */ 23437c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 23441a595f28SAnthony Koo /** 23451a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 23461a595f28SAnthony Koo */ 2347d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version psr_set_version; 23481a595f28SAnthony Koo /** 23491a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 23501a595f28SAnthony Koo */ 23517c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 23521a595f28SAnthony Koo /** 23531a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 23541a595f28SAnthony Koo */ 2355d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_enable psr_enable; 23561a595f28SAnthony Koo /** 23571a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 23581a595f28SAnthony Koo */ 23597c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level psr_set_level; 23601a595f28SAnthony Koo /** 23611a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 23621a595f28SAnthony Koo */ 2363672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static psr_force_static; 2364592a6318SAnthony Koo /** 2365592a6318SAnthony Koo * Definition of a DMUB_CMD__PLAT_54186_WA command. 2366592a6318SAnthony Koo */ 2367bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2368592a6318SAnthony Koo /** 2369592a6318SAnthony Koo * Definition of a DMUB_CMD__MALL command. 2370592a6318SAnthony Koo */ 237152f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall mall; 2372b04cb192SNicholas Kazlauskas /** 2373b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2374b04cb192SNicholas Kazlauskas */ 2375b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2376b04cb192SNicholas Kazlauskas 2377b04cb192SNicholas Kazlauskas /** 2378b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2379b04cb192SNicholas Kazlauskas */ 2380b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2381b04cb192SNicholas Kazlauskas 2382b04cb192SNicholas Kazlauskas /** 2383b04cb192SNicholas Kazlauskas * Definition of DMUB_CMD__PANEL_CNTL commands. 2384b04cb192SNicholas Kazlauskas */ 2385b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl panel_cntl; 23861a595f28SAnthony Koo /** 23871a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 23881a595f28SAnthony Koo */ 2389e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 23901a595f28SAnthony Koo 23911a595f28SAnthony Koo /** 23921a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 23931a595f28SAnthony Koo */ 2394e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 23951a595f28SAnthony Koo 23961a595f28SAnthony Koo /** 23971a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 23981a595f28SAnthony Koo */ 2399e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level abm_set_level; 24001a595f28SAnthony Koo 24011a595f28SAnthony Koo /** 24021a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 24031a595f28SAnthony Koo */ 2404e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 24051a595f28SAnthony Koo 24061a595f28SAnthony Koo /** 24071a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 24081a595f28SAnthony Koo */ 2409e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 24101a595f28SAnthony Koo 24111a595f28SAnthony Koo /** 24121a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 24131a595f28SAnthony Koo */ 241416012806SWyatt Wood struct dmub_rb_cmd_abm_init_config abm_init_config; 24151a595f28SAnthony Koo 24161a595f28SAnthony Koo /** 2417*b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 2418*b629a824SEric Yang */ 2419*b629a824SEric Yang struct dmub_rb_cmd_abm_pause abm_pause; 2420*b629a824SEric Yang 2421*b629a824SEric Yang /** 24221a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 24231a595f28SAnthony Koo */ 2424d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access dp_aux_access; 24251a595f28SAnthony Koo 24261a595f28SAnthony Koo /** 2427592a6318SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2428592a6318SAnthony Koo */ 2429592a6318SAnthony Koo struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2430592a6318SAnthony Koo 2431592a6318SAnthony Koo /** 2432592a6318SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 24331a595f28SAnthony Koo */ 243434ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2435592a6318SAnthony Koo struct dmub_rb_cmd_drr_update drr_update; 24361a595f28SAnthony Koo /** 24371a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 24381a595f28SAnthony Koo */ 24391a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control lvtma_control; 2440021eaef8SAnthony Koo /** 2441021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 2442021eaef8SAnthony Koo */ 2443021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea edid_cea; 24447c008829SNicholas Kazlauskas }; 24457c008829SNicholas Kazlauskas 2446592a6318SAnthony Koo /** 2447592a6318SAnthony Koo * union dmub_rb_out_cmd - Outbox command 2448592a6318SAnthony Koo */ 2449d9beecfcSAnthony Koo union dmub_rb_out_cmd { 2450592a6318SAnthony Koo /** 2451592a6318SAnthony Koo * Parameters common to every command. 2452592a6318SAnthony Koo */ 2453d9beecfcSAnthony Koo struct dmub_rb_cmd_common cmd_common; 2454592a6318SAnthony Koo /** 2455592a6318SAnthony Koo * AUX reply command. 2456592a6318SAnthony Koo */ 2457d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2458592a6318SAnthony Koo /** 2459592a6318SAnthony Koo * HPD notify command. 2460592a6318SAnthony Koo */ 2461d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 2462d9beecfcSAnthony Koo }; 24637c008829SNicholas Kazlauskas #pragma pack(pop) 24647c008829SNicholas Kazlauskas 246584034ad4SAnthony Koo 246684034ad4SAnthony Koo //============================================================================== 246784034ad4SAnthony Koo //</DMUB_CMD>=================================================================== 246884034ad4SAnthony Koo //============================================================================== 246984034ad4SAnthony Koo //< DMUB_RB>==================================================================== 247084034ad4SAnthony Koo //============================================================================== 247184034ad4SAnthony Koo 247284034ad4SAnthony Koo #if defined(__cplusplus) 247384034ad4SAnthony Koo extern "C" { 247484034ad4SAnthony Koo #endif 247584034ad4SAnthony Koo 2476592a6318SAnthony Koo /** 2477592a6318SAnthony Koo * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2478592a6318SAnthony Koo */ 247984034ad4SAnthony Koo struct dmub_rb_init_params { 2480592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 2481592a6318SAnthony Koo void *base_address; /**< CPU base address for ring's data */ 2482592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2483592a6318SAnthony Koo uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2484592a6318SAnthony Koo uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 248584034ad4SAnthony Koo }; 248684034ad4SAnthony Koo 2487592a6318SAnthony Koo /** 2488592a6318SAnthony Koo * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2489592a6318SAnthony Koo */ 249084034ad4SAnthony Koo struct dmub_rb { 2491592a6318SAnthony Koo void *base_address; /**< CPU address for the ring's data */ 2492592a6318SAnthony Koo uint32_t rptr; /**< Read pointer for consumer in bytes */ 2493592a6318SAnthony Koo uint32_t wrpt; /**< Write pointer for producer in bytes */ 2494592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 249584034ad4SAnthony Koo 2496592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 2497592a6318SAnthony Koo void *dmub; /**< Pointer to the DMUB interface */ 249884034ad4SAnthony Koo }; 249984034ad4SAnthony Koo 2500592a6318SAnthony Koo /** 2501592a6318SAnthony Koo * @brief Checks if the ringbuffer is empty. 2502592a6318SAnthony Koo * 2503592a6318SAnthony Koo * @param rb DMUB Ringbuffer 2504592a6318SAnthony Koo * @return true if empty 2505592a6318SAnthony Koo * @return false otherwise 2506592a6318SAnthony Koo */ 250784034ad4SAnthony Koo static inline bool dmub_rb_empty(struct dmub_rb *rb) 250884034ad4SAnthony Koo { 250984034ad4SAnthony Koo return (rb->wrpt == rb->rptr); 251084034ad4SAnthony Koo } 251184034ad4SAnthony Koo 2512592a6318SAnthony Koo /** 2513592a6318SAnthony Koo * @brief Checks if the ringbuffer is full 2514592a6318SAnthony Koo * 2515592a6318SAnthony Koo * @param rb DMUB Ringbuffer 2516592a6318SAnthony Koo * @return true if full 2517592a6318SAnthony Koo * @return false otherwise 2518592a6318SAnthony Koo */ 251984034ad4SAnthony Koo static inline bool dmub_rb_full(struct dmub_rb *rb) 252084034ad4SAnthony Koo { 252184034ad4SAnthony Koo uint32_t data_count; 252284034ad4SAnthony Koo 252384034ad4SAnthony Koo if (rb->wrpt >= rb->rptr) 252484034ad4SAnthony Koo data_count = rb->wrpt - rb->rptr; 252584034ad4SAnthony Koo else 252684034ad4SAnthony Koo data_count = rb->capacity - (rb->rptr - rb->wrpt); 252784034ad4SAnthony Koo 252884034ad4SAnthony Koo return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 252984034ad4SAnthony Koo } 253084034ad4SAnthony Koo 2531592a6318SAnthony Koo /** 2532592a6318SAnthony Koo * @brief Pushes a command into the ringbuffer 2533592a6318SAnthony Koo * 2534592a6318SAnthony Koo * @param rb DMUB ringbuffer 2535592a6318SAnthony Koo * @param cmd The command to push 2536592a6318SAnthony Koo * @return true if the ringbuffer was not full 2537592a6318SAnthony Koo * @return false otherwise 2538592a6318SAnthony Koo */ 253984034ad4SAnthony Koo static inline bool dmub_rb_push_front(struct dmub_rb *rb, 254084034ad4SAnthony Koo const union dmub_rb_cmd *cmd) 254184034ad4SAnthony Koo { 25423a9d5b0bSAnthony Koo uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 25433a9d5b0bSAnthony Koo const uint64_t *src = (const uint64_t *)cmd; 25443a9d5b0bSAnthony Koo uint8_t i; 254584034ad4SAnthony Koo 254684034ad4SAnthony Koo if (dmub_rb_full(rb)) 254784034ad4SAnthony Koo return false; 254884034ad4SAnthony Koo 254984034ad4SAnthony Koo // copying data 25503a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 25513a9d5b0bSAnthony Koo *dst++ = *src++; 255284034ad4SAnthony Koo 255384034ad4SAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 255484034ad4SAnthony Koo 255584034ad4SAnthony Koo if (rb->wrpt >= rb->capacity) 255684034ad4SAnthony Koo rb->wrpt %= rb->capacity; 255784034ad4SAnthony Koo 255884034ad4SAnthony Koo return true; 255984034ad4SAnthony Koo } 256084034ad4SAnthony Koo 2561592a6318SAnthony Koo /** 2562592a6318SAnthony Koo * @brief Pushes a command into the DMUB outbox ringbuffer 2563592a6318SAnthony Koo * 2564592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 2565592a6318SAnthony Koo * @param cmd Outbox command 2566592a6318SAnthony Koo * @return true if not full 2567592a6318SAnthony Koo * @return false otherwise 2568592a6318SAnthony Koo */ 2569d9beecfcSAnthony Koo static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2570d9beecfcSAnthony Koo const union dmub_rb_out_cmd *cmd) 2571d9beecfcSAnthony Koo { 2572d9beecfcSAnthony Koo uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2573d459b79bSAnthony Koo const uint8_t *src = (const uint8_t *)cmd; 2574d9beecfcSAnthony Koo 2575d9beecfcSAnthony Koo if (dmub_rb_full(rb)) 2576d9beecfcSAnthony Koo return false; 2577d9beecfcSAnthony Koo 2578d9beecfcSAnthony Koo dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2579d9beecfcSAnthony Koo 2580d9beecfcSAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 2581d9beecfcSAnthony Koo 2582d9beecfcSAnthony Koo if (rb->wrpt >= rb->capacity) 2583d9beecfcSAnthony Koo rb->wrpt %= rb->capacity; 2584d9beecfcSAnthony Koo 2585d9beecfcSAnthony Koo return true; 2586d9beecfcSAnthony Koo } 2587d9beecfcSAnthony Koo 2588592a6318SAnthony Koo /** 2589592a6318SAnthony Koo * @brief Returns the next unprocessed command in the ringbuffer. 2590592a6318SAnthony Koo * 2591592a6318SAnthony Koo * @param rb DMUB ringbuffer 2592592a6318SAnthony Koo * @param cmd The command to return 2593592a6318SAnthony Koo * @return true if not empty 2594592a6318SAnthony Koo * @return false otherwise 2595592a6318SAnthony Koo */ 259684034ad4SAnthony Koo static inline bool dmub_rb_front(struct dmub_rb *rb, 259734ba432cSAnthony Koo union dmub_rb_cmd **cmd) 259884034ad4SAnthony Koo { 259934ba432cSAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 260084034ad4SAnthony Koo 260184034ad4SAnthony Koo if (dmub_rb_empty(rb)) 260284034ad4SAnthony Koo return false; 260384034ad4SAnthony Koo 260434ba432cSAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 260584034ad4SAnthony Koo 260684034ad4SAnthony Koo return true; 260784034ad4SAnthony Koo } 260884034ad4SAnthony Koo 2609592a6318SAnthony Koo /** 26100b51e7e8SAnthony Koo * @brief Determines the next ringbuffer offset. 26110b51e7e8SAnthony Koo * 26120b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 26130b51e7e8SAnthony Koo * @param num_cmds Number of commands 26140b51e7e8SAnthony Koo * @param next_rptr The next offset in the ringbuffer 26150b51e7e8SAnthony Koo */ 26160b51e7e8SAnthony Koo static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 26170b51e7e8SAnthony Koo uint32_t num_cmds, 26180b51e7e8SAnthony Koo uint32_t *next_rptr) 26190b51e7e8SAnthony Koo { 26200b51e7e8SAnthony Koo *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 26210b51e7e8SAnthony Koo 26220b51e7e8SAnthony Koo if (*next_rptr >= rb->capacity) 26230b51e7e8SAnthony Koo *next_rptr %= rb->capacity; 26240b51e7e8SAnthony Koo } 26250b51e7e8SAnthony Koo 26260b51e7e8SAnthony Koo /** 26270b51e7e8SAnthony Koo * @brief Returns a pointer to a command in the inbox. 26280b51e7e8SAnthony Koo * 26290b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 26300b51e7e8SAnthony Koo * @param cmd The inbox command to return 26310b51e7e8SAnthony Koo * @param rptr The ringbuffer offset 26320b51e7e8SAnthony Koo * @return true if not empty 26330b51e7e8SAnthony Koo * @return false otherwise 26340b51e7e8SAnthony Koo */ 26350b51e7e8SAnthony Koo static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 26360b51e7e8SAnthony Koo union dmub_rb_cmd **cmd, 26370b51e7e8SAnthony Koo uint32_t rptr) 26380b51e7e8SAnthony Koo { 26390b51e7e8SAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 26400b51e7e8SAnthony Koo 26410b51e7e8SAnthony Koo if (dmub_rb_empty(rb)) 26420b51e7e8SAnthony Koo return false; 26430b51e7e8SAnthony Koo 26440b51e7e8SAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 26450b51e7e8SAnthony Koo 26460b51e7e8SAnthony Koo return true; 26470b51e7e8SAnthony Koo } 26480b51e7e8SAnthony Koo 26490b51e7e8SAnthony Koo /** 2650592a6318SAnthony Koo * @brief Returns the next unprocessed command in the outbox. 2651592a6318SAnthony Koo * 2652592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 2653592a6318SAnthony Koo * @param cmd The outbox command to return 2654592a6318SAnthony Koo * @return true if not empty 2655592a6318SAnthony Koo * @return false otherwise 2656592a6318SAnthony Koo */ 2657d9beecfcSAnthony Koo static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2658d9beecfcSAnthony Koo union dmub_rb_out_cmd *cmd) 2659d9beecfcSAnthony Koo { 26603a9d5b0bSAnthony Koo const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 26613a9d5b0bSAnthony Koo uint64_t *dst = (uint64_t *)cmd; 26623a9d5b0bSAnthony Koo uint8_t i; 2663d9beecfcSAnthony Koo 2664d9beecfcSAnthony Koo if (dmub_rb_empty(rb)) 2665d9beecfcSAnthony Koo return false; 2666d9beecfcSAnthony Koo 2667d9beecfcSAnthony Koo // copying data 26683a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 26693a9d5b0bSAnthony Koo *dst++ = *src++; 2670d9beecfcSAnthony Koo 2671d9beecfcSAnthony Koo return true; 2672d9beecfcSAnthony Koo } 2673d9beecfcSAnthony Koo 2674592a6318SAnthony Koo /** 2675592a6318SAnthony Koo * @brief Removes the front entry in the ringbuffer. 2676592a6318SAnthony Koo * 2677592a6318SAnthony Koo * @param rb DMUB ringbuffer 2678592a6318SAnthony Koo * @return true if the command was removed 2679592a6318SAnthony Koo * @return false if there were no commands 2680592a6318SAnthony Koo */ 268184034ad4SAnthony Koo static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 268284034ad4SAnthony Koo { 268384034ad4SAnthony Koo if (dmub_rb_empty(rb)) 268484034ad4SAnthony Koo return false; 268584034ad4SAnthony Koo 268684034ad4SAnthony Koo rb->rptr += DMUB_RB_CMD_SIZE; 268784034ad4SAnthony Koo 268884034ad4SAnthony Koo if (rb->rptr >= rb->capacity) 268984034ad4SAnthony Koo rb->rptr %= rb->capacity; 269084034ad4SAnthony Koo 269184034ad4SAnthony Koo return true; 269284034ad4SAnthony Koo } 269384034ad4SAnthony Koo 2694592a6318SAnthony Koo /** 2695592a6318SAnthony Koo * @brief Flushes commands in the ringbuffer to framebuffer memory. 2696592a6318SAnthony Koo * 2697592a6318SAnthony Koo * Avoids a race condition where DMCUB accesses memory while 2698592a6318SAnthony Koo * there are still writes in flight to framebuffer. 2699592a6318SAnthony Koo * 2700592a6318SAnthony Koo * @param rb DMUB ringbuffer 2701592a6318SAnthony Koo */ 270284034ad4SAnthony Koo static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 270384034ad4SAnthony Koo { 270484034ad4SAnthony Koo uint32_t rptr = rb->rptr; 270584034ad4SAnthony Koo uint32_t wptr = rb->wrpt; 270684034ad4SAnthony Koo 270784034ad4SAnthony Koo while (rptr != wptr) { 27083a9d5b0bSAnthony Koo uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 27093a9d5b0bSAnthony Koo //uint64_t volatile *p = (uint64_t volatile *)data; 27103a9d5b0bSAnthony Koo uint64_t temp; 27113a9d5b0bSAnthony Koo uint8_t i; 271284034ad4SAnthony Koo 27133a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 27143a9d5b0bSAnthony Koo temp = *data++; 271584034ad4SAnthony Koo 271684034ad4SAnthony Koo rptr += DMUB_RB_CMD_SIZE; 271784034ad4SAnthony Koo if (rptr >= rb->capacity) 271884034ad4SAnthony Koo rptr %= rb->capacity; 271984034ad4SAnthony Koo } 272084034ad4SAnthony Koo } 272184034ad4SAnthony Koo 2722592a6318SAnthony Koo /** 2723592a6318SAnthony Koo * @brief Initializes a DMCUB ringbuffer 2724592a6318SAnthony Koo * 2725592a6318SAnthony Koo * @param rb DMUB ringbuffer 2726592a6318SAnthony Koo * @param init_params initial configuration for the ringbuffer 2727592a6318SAnthony Koo */ 272884034ad4SAnthony Koo static inline void dmub_rb_init(struct dmub_rb *rb, 272984034ad4SAnthony Koo struct dmub_rb_init_params *init_params) 273084034ad4SAnthony Koo { 273184034ad4SAnthony Koo rb->base_address = init_params->base_address; 273284034ad4SAnthony Koo rb->capacity = init_params->capacity; 273384034ad4SAnthony Koo rb->rptr = init_params->read_ptr; 273484034ad4SAnthony Koo rb->wrpt = init_params->write_ptr; 273584034ad4SAnthony Koo } 273684034ad4SAnthony Koo 2737592a6318SAnthony Koo /** 2738592a6318SAnthony Koo * @brief Copies output data from in/out commands into the given command. 2739592a6318SAnthony Koo * 2740592a6318SAnthony Koo * @param rb DMUB ringbuffer 2741592a6318SAnthony Koo * @param cmd Command to copy data into 2742592a6318SAnthony Koo */ 274334ba432cSAnthony Koo static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 274434ba432cSAnthony Koo union dmub_rb_cmd *cmd) 274534ba432cSAnthony Koo { 274634ba432cSAnthony Koo // Copy rb entry back into command 274734ba432cSAnthony Koo uint8_t *rd_ptr = (rb->rptr == 0) ? 274834ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 274934ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 275034ba432cSAnthony Koo 275134ba432cSAnthony Koo dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 275234ba432cSAnthony Koo } 275334ba432cSAnthony Koo 275484034ad4SAnthony Koo #if defined(__cplusplus) 275584034ad4SAnthony Koo } 275684034ad4SAnthony Koo #endif 275784034ad4SAnthony Koo 275884034ad4SAnthony Koo //============================================================================== 275984034ad4SAnthony Koo //</DMUB_RB>==================================================================== 276084034ad4SAnthony Koo //============================================================================== 276184034ad4SAnthony Koo 27627c008829SNicholas Kazlauskas #endif /* _DMUB_CMD_H_ */ 2763