17c008829SNicholas Kazlauskas /* 27c008829SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 37c008829SNicholas Kazlauskas * 47c008829SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 57c008829SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 67c008829SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 77c008829SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87c008829SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 97c008829SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 107c008829SNicholas Kazlauskas * 117c008829SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 127c008829SNicholas Kazlauskas * all copies or substantial portions of the Software. 137c008829SNicholas Kazlauskas * 147c008829SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157c008829SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167c008829SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177c008829SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187c008829SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197c008829SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207c008829SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 217c008829SNicholas Kazlauskas * 227c008829SNicholas Kazlauskas * Authors: AMD 237c008829SNicholas Kazlauskas * 247c008829SNicholas Kazlauskas */ 257c008829SNicholas Kazlauskas 267c008829SNicholas Kazlauskas #ifndef _DMUB_CMD_H_ 277c008829SNicholas Kazlauskas #define _DMUB_CMD_H_ 287c008829SNicholas Kazlauskas 297c008829SNicholas Kazlauskas #include "dmub_types.h" 30d4bbcecbSNicholas Kazlauskas #include "dmub_cmd_dal.h" 31d4bbcecbSNicholas Kazlauskas #include "dmub_cmd_vbios.h" 327c008829SNicholas Kazlauskas #include "atomfirmware.h" 3322aa5614SYongqiang Sun 347c008829SNicholas Kazlauskas #define DMUB_RB_CMD_SIZE 64 357c008829SNicholas Kazlauskas #define DMUB_RB_MAX_ENTRY 128 367c008829SNicholas Kazlauskas #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 377c008829SNicholas Kazlauskas #define REG_SET_MASK 0xFFFF 387c008829SNicholas Kazlauskas 39474ac4a8SYongqiang Sun #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 40474ac4a8SYongqiang Sun #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 41474ac4a8SYongqiang Sun #define SET_ABM_PIPE_NORMAL 1 428c019253SYongqiang Sun 43d4bbcecbSNicholas Kazlauskas /* 44d4bbcecbSNicholas Kazlauskas * Command IDs should be treated as stable ABI. 45d4bbcecbSNicholas Kazlauskas * Do not reuse or modify IDs. 46d4bbcecbSNicholas Kazlauskas */ 477c008829SNicholas Kazlauskas 48d4bbcecbSNicholas Kazlauskas enum dmub_cmd_type { 49d4bbcecbSNicholas Kazlauskas DMUB_CMD__NULL = 0, 50d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 51d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 52d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 53d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_REG_WAIT = 4, 54bae9c49bSYongqiang Sun DMUB_CMD__PLAT_54186_WA = 5, 55d4bbcecbSNicholas Kazlauskas DMUB_CMD__PSR = 64, 56e6ea8c34SWyatt Wood DMUB_CMD__ABM = 66, 57d4bbcecbSNicholas Kazlauskas DMUB_CMD__VBIOS = 128, 587c008829SNicholas Kazlauskas }; 597c008829SNicholas Kazlauskas 607c008829SNicholas Kazlauskas #pragma pack(push, 1) 617c008829SNicholas Kazlauskas 627c008829SNicholas Kazlauskas struct dmub_cmd_header { 63d4bbcecbSNicholas Kazlauskas unsigned int type : 8; 64d4bbcecbSNicholas Kazlauskas unsigned int sub_type : 8; 65d4bbcecbSNicholas Kazlauskas unsigned int reserved0 : 8; 667c008829SNicholas Kazlauskas unsigned int payload_bytes : 6; /* up to 60 bytes */ 67d4bbcecbSNicholas Kazlauskas unsigned int reserved1 : 2; 687c008829SNicholas Kazlauskas }; 697c008829SNicholas Kazlauskas 707c008829SNicholas Kazlauskas /* 717c008829SNicholas Kazlauskas * Read modify write 727c008829SNicholas Kazlauskas * 737c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 5 sets of read modify writes, 747c008829SNicholas Kazlauskas * each take 3 dwords. 757c008829SNicholas Kazlauskas * 767c008829SNicholas Kazlauskas * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 777c008829SNicholas Kazlauskas * 787c008829SNicholas Kazlauskas * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 797c008829SNicholas Kazlauskas * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 807c008829SNicholas Kazlauskas */ 817c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence { 827c008829SNicholas Kazlauskas uint32_t addr; 837c008829SNicholas Kazlauskas uint32_t modify_mask; 847c008829SNicholas Kazlauskas uint32_t modify_value; 857c008829SNicholas Kazlauskas }; 867c008829SNicholas Kazlauskas 877c008829SNicholas Kazlauskas #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 887c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write { 897c008829SNicholas Kazlauskas struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 907c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 917c008829SNicholas Kazlauskas }; 927c008829SNicholas Kazlauskas 937c008829SNicholas Kazlauskas /* 947c008829SNicholas Kazlauskas * Update a register with specified masks and values sequeunce 957c008829SNicholas Kazlauskas * 967c008829SNicholas Kazlauskas * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 977c008829SNicholas Kazlauskas * 987c008829SNicholas Kazlauskas * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 997c008829SNicholas Kazlauskas * 1007c008829SNicholas Kazlauskas * 1017c008829SNicholas Kazlauskas * USE CASE: 1027c008829SNicholas Kazlauskas * 1. auto-increment register where additional read would update pointer and produce wrong result 1037c008829SNicholas Kazlauskas * 2. toggle a bit without read in the middle 1047c008829SNicholas Kazlauskas */ 1057c008829SNicholas Kazlauskas 1067c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence { 1077c008829SNicholas Kazlauskas uint32_t modify_mask; // 0xffff'ffff to skip initial read 1087c008829SNicholas Kazlauskas uint32_t modify_value; 1097c008829SNicholas Kazlauskas }; 1107c008829SNicholas Kazlauskas 1117c008829SNicholas Kazlauskas #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1127c008829SNicholas Kazlauskas 1137c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence { 1147c008829SNicholas Kazlauskas struct dmub_cmd_header header; 1157c008829SNicholas Kazlauskas uint32_t addr; 1167c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1177c008829SNicholas Kazlauskas }; 1187c008829SNicholas Kazlauskas 1197c008829SNicholas Kazlauskas 1207c008829SNicholas Kazlauskas /* 1217c008829SNicholas Kazlauskas * Burst write 1227c008829SNicholas Kazlauskas * 1237c008829SNicholas Kazlauskas * support use case such as writing out LUTs. 1247c008829SNicholas Kazlauskas * 1257c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 14 values to write to given address 1267c008829SNicholas Kazlauskas * 1277c008829SNicholas Kazlauskas * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1287c008829SNicholas Kazlauskas */ 1297c008829SNicholas Kazlauskas #define DMUB_BURST_WRITE_VALUES__MAX 14 1307c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write { 1317c008829SNicholas Kazlauskas struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 1327c008829SNicholas Kazlauskas uint32_t addr; 1337c008829SNicholas Kazlauskas uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1347c008829SNicholas Kazlauskas }; 1357c008829SNicholas Kazlauskas 1367c008829SNicholas Kazlauskas 1377c008829SNicholas Kazlauskas struct dmub_rb_cmd_common { 1387c008829SNicholas Kazlauskas struct dmub_cmd_header header; 1397c008829SNicholas Kazlauskas uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1407c008829SNicholas Kazlauskas }; 1417c008829SNicholas Kazlauskas 1427c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data { 1437c008829SNicholas Kazlauskas uint32_t addr; 1447c008829SNicholas Kazlauskas uint32_t mask; 1457c008829SNicholas Kazlauskas uint32_t condition_field_value; 1467c008829SNicholas Kazlauskas uint32_t time_out_us; 1477c008829SNicholas Kazlauskas }; 1487c008829SNicholas Kazlauskas 1497c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait { 1507c008829SNicholas Kazlauskas struct dmub_cmd_header header; 1517c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data reg_wait; 1527c008829SNicholas Kazlauskas }; 1537c008829SNicholas Kazlauskas 1548c019253SYongqiang Sun #ifndef PHYSICAL_ADDRESS_LOC 1558c019253SYongqiang Sun #define PHYSICAL_ADDRESS_LOC union large_integer 1568c019253SYongqiang Sun #endif 1578c019253SYongqiang Sun 158bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa { 1598c019253SYongqiang Sun uint32_t DCSURF_SURFACE_CONTROL; 1608c019253SYongqiang Sun uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 1618c019253SYongqiang Sun uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 1628c019253SYongqiang Sun uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 1638c019253SYongqiang Sun uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 16422aa5614SYongqiang Sun struct { 16522aa5614SYongqiang Sun uint8_t hubp_inst : 4; 16622aa5614SYongqiang Sun uint8_t tmz_surface : 1; 16722aa5614SYongqiang Sun uint8_t immediate :1; 16822aa5614SYongqiang Sun uint8_t vmid : 4; 16922aa5614SYongqiang Sun uint8_t grph_stereo : 1; 17022aa5614SYongqiang Sun uint32_t reserved : 21; 17122aa5614SYongqiang Sun } flip_params; 172bae9c49bSYongqiang Sun uint32_t reserved[9]; 1738c019253SYongqiang Sun }; 1748c019253SYongqiang Sun 175bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa { 1768c019253SYongqiang Sun struct dmub_cmd_header header; 177bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa flip; 1788c019253SYongqiang Sun }; 1798c019253SYongqiang Sun 1807c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data { 1817c008829SNicholas Kazlauskas union dig_encoder_control_parameters_v1_5 dig; 1827c008829SNicholas Kazlauskas }; 1837c008829SNicholas Kazlauskas 1847c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control { 1857c008829SNicholas Kazlauskas struct dmub_cmd_header header; 1867c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data encoder_control; 1877c008829SNicholas Kazlauskas }; 1887c008829SNicholas Kazlauskas 1897c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data { 1907c008829SNicholas Kazlauskas struct set_pixel_clock_parameter_v1_7 clk; 1917c008829SNicholas Kazlauskas }; 1927c008829SNicholas Kazlauskas 1937c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock { 1947c008829SNicholas Kazlauskas struct dmub_cmd_header header; 1957c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data pixel_clock; 1967c008829SNicholas Kazlauskas }; 1977c008829SNicholas Kazlauskas 1987c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data { 1997c008829SNicholas Kazlauskas struct enable_disp_power_gating_parameters_v2_1 pwr; 2007c008829SNicholas Kazlauskas }; 2017c008829SNicholas Kazlauskas 2027c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating { 2037c008829SNicholas Kazlauskas struct dmub_cmd_header header; 2047c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data power_gating; 2057c008829SNicholas Kazlauskas }; 2067c008829SNicholas Kazlauskas 2077c008829SNicholas Kazlauskas struct dmub_cmd_dig1_transmitter_control_data { 2087c008829SNicholas Kazlauskas struct dig_transmitter_control_parameters_v1_6 dig; 2097c008829SNicholas Kazlauskas }; 2107c008829SNicholas Kazlauskas 2117c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control { 2127c008829SNicholas Kazlauskas struct dmub_cmd_header header; 2137c008829SNicholas Kazlauskas struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 2147c008829SNicholas Kazlauskas }; 2157c008829SNicholas Kazlauskas 2167c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init { 2177c008829SNicholas Kazlauskas struct dmub_cmd_header header; 2187c008829SNicholas Kazlauskas uint8_t reserved[60]; 2197c008829SNicholas Kazlauskas }; 2207c008829SNicholas Kazlauskas 2217c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data { 2227b8a6362SAnthony Koo union dmub_psr_debug_flags debug; 2234c1a1335SWyatt Wood uint16_t psr_level; 2244c1a1335SWyatt Wood uint8_t dpp_inst; 2254c1a1335SWyatt Wood uint8_t mpcc_inst; 2264c1a1335SWyatt Wood uint8_t opp_inst; 2274c1a1335SWyatt Wood uint8_t otg_inst; 2284c1a1335SWyatt Wood uint8_t digfe_inst; 2294c1a1335SWyatt Wood uint8_t digbe_inst; 2304c1a1335SWyatt Wood uint8_t dpphy_inst; 2314c1a1335SWyatt Wood uint8_t aux_inst; 2324c1a1335SWyatt Wood uint8_t smu_optimizations_en; 2334c1a1335SWyatt Wood uint8_t frame_delay; 2344c1a1335SWyatt Wood uint8_t frame_cap_ind; 2357b8a6362SAnthony Koo uint8_t pad[3]; 2367c008829SNicholas Kazlauskas }; 2377c008829SNicholas Kazlauskas 2387c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings { 2397c008829SNicholas Kazlauskas struct dmub_cmd_header header; 2407c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2417c008829SNicholas Kazlauskas }; 2427c008829SNicholas Kazlauskas 2437c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data { 2447c008829SNicholas Kazlauskas uint16_t psr_level; 2457b8a6362SAnthony Koo uint8_t pad[2]; 2467c008829SNicholas Kazlauskas }; 2477c008829SNicholas Kazlauskas 2487c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level { 2497c008829SNicholas Kazlauskas struct dmub_cmd_header header; 2507c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data psr_set_level_data; 2517c008829SNicholas Kazlauskas }; 2527c008829SNicholas Kazlauskas 2537c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_enable { 2547c008829SNicholas Kazlauskas struct dmub_cmd_header header; 2557c008829SNicholas Kazlauskas }; 2567c008829SNicholas Kazlauskas 257d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data { 258ec256f44SWyatt Wood enum psr_version version; // PSR version 1 or 2 2597c008829SNicholas Kazlauskas }; 2607c008829SNicholas Kazlauskas 261d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version { 2627c008829SNicholas Kazlauskas struct dmub_cmd_header header; 263d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data psr_set_version_data; 2647c008829SNicholas Kazlauskas }; 2657c008829SNicholas Kazlauskas 266e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data { 2677b8a6362SAnthony Koo uint8_t otg_inst; 2687b8a6362SAnthony Koo uint8_t panel_inst; 2697b8a6362SAnthony Koo uint8_t set_pipe_option; 2707b8a6362SAnthony Koo uint8_t ramping_boundary; // TODO: Remove this 271e6ea8c34SWyatt Wood }; 272e6ea8c34SWyatt Wood 273e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe { 274e6ea8c34SWyatt Wood struct dmub_cmd_header header; 275e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 276e6ea8c34SWyatt Wood }; 277e6ea8c34SWyatt Wood 278e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data { 279e6ea8c34SWyatt Wood uint32_t frame_ramp; 280474ac4a8SYongqiang Sun uint32_t backlight_user_level; 281e6ea8c34SWyatt Wood }; 282e6ea8c34SWyatt Wood 283e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight { 284e6ea8c34SWyatt Wood struct dmub_cmd_header header; 285e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 286e6ea8c34SWyatt Wood }; 287e6ea8c34SWyatt Wood 288e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data { 289e6ea8c34SWyatt Wood uint32_t level; 290e6ea8c34SWyatt Wood }; 291e6ea8c34SWyatt Wood 292e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level { 293e6ea8c34SWyatt Wood struct dmub_cmd_header header; 294e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data abm_set_level_data; 295e6ea8c34SWyatt Wood }; 296e6ea8c34SWyatt Wood 297e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data { 298e6ea8c34SWyatt Wood uint32_t ambient_lux; 299e6ea8c34SWyatt Wood }; 300e6ea8c34SWyatt Wood 301e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level { 302e6ea8c34SWyatt Wood struct dmub_cmd_header header; 303e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 304e6ea8c34SWyatt Wood }; 305e6ea8c34SWyatt Wood 306e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data { 307e6ea8c34SWyatt Wood uint32_t fractional_pwm; 308e6ea8c34SWyatt Wood }; 309e6ea8c34SWyatt Wood 310e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac { 311e6ea8c34SWyatt Wood struct dmub_cmd_header header; 312e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 313e6ea8c34SWyatt Wood }; 314e6ea8c34SWyatt Wood 31516012806SWyatt Wood struct dmub_cmd_abm_init_config_data { 31616012806SWyatt Wood union dmub_addr src; 31716012806SWyatt Wood uint16_t bytes; 31816012806SWyatt Wood }; 31916012806SWyatt Wood 32016012806SWyatt Wood struct dmub_rb_cmd_abm_init_config { 32116012806SWyatt Wood struct dmub_cmd_header header; 32216012806SWyatt Wood struct dmub_cmd_abm_init_config_data abm_init_config_data; 32316012806SWyatt Wood }; 32416012806SWyatt Wood 3257c008829SNicholas Kazlauskas union dmub_rb_cmd { 3267c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write read_modify_write; 3277c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3287c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write burst_write; 3297c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait reg_wait; 3307c008829SNicholas Kazlauskas struct dmub_rb_cmd_common cmd_common; 3317c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3327c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3337c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3347c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init dpphy_init; 3357c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 336d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version psr_set_version; 3377c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 338d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_enable psr_enable; 3397c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level psr_set_level; 340bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 341e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 342e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 343e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level abm_set_level; 344e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 345e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 34616012806SWyatt Wood struct dmub_rb_cmd_abm_init_config abm_init_config; 3477c008829SNicholas Kazlauskas }; 3487c008829SNicholas Kazlauskas 3497c008829SNicholas Kazlauskas #pragma pack(pop) 3507c008829SNicholas Kazlauskas 3517c008829SNicholas Kazlauskas #endif /* _DMUB_CMD_H_ */ 352