17c008829SNicholas Kazlauskas /* 27c008829SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 37c008829SNicholas Kazlauskas * 47c008829SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 57c008829SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 67c008829SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 77c008829SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87c008829SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 97c008829SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 107c008829SNicholas Kazlauskas * 117c008829SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 127c008829SNicholas Kazlauskas * all copies or substantial portions of the Software. 137c008829SNicholas Kazlauskas * 147c008829SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157c008829SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167c008829SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177c008829SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187c008829SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197c008829SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207c008829SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 217c008829SNicholas Kazlauskas * 227c008829SNicholas Kazlauskas * Authors: AMD 237c008829SNicholas Kazlauskas * 247c008829SNicholas Kazlauskas */ 257c008829SNicholas Kazlauskas 265624c345SAnthony Koo #ifndef DMUB_CMD_H 275624c345SAnthony Koo #define DMUB_CMD_H 287c008829SNicholas Kazlauskas 298b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 308b19a4e3SAnthony Koo #include "dmub_fw_types.h" 318b19a4e3SAnthony Koo #include "include_legacy/atomfirmware.h" 328b19a4e3SAnthony Koo 338b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) 348b19a4e3SAnthony Koo #include <string.h> 358b19a4e3SAnthony Koo #endif 368b19a4e3SAnthony Koo #else 378b19a4e3SAnthony Koo 3884034ad4SAnthony Koo #include <asm/byteorder.h> 3984034ad4SAnthony Koo #include <linux/types.h> 4084034ad4SAnthony Koo #include <linux/string.h> 4184034ad4SAnthony Koo #include <linux/delay.h> 4284034ad4SAnthony Koo 437c008829SNicholas Kazlauskas #include "atomfirmware.h" 4422aa5614SYongqiang Sun 458b19a4e3SAnthony Koo #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 468b19a4e3SAnthony Koo 478598a722SAnthony Koo /* Firmware versioning. */ 488598a722SAnthony Koo #ifdef DMUB_EXPOSE_VERSION 49*5b5e0776SAnthony Koo #define DMUB_FW_VERSION_GIT_HASH 0x9525efb5 50b2265774SAnthony Koo #define DMUB_FW_VERSION_MAJOR 0 518598a722SAnthony Koo #define DMUB_FW_VERSION_MINOR 0 52*5b5e0776SAnthony Koo #define DMUB_FW_VERSION_REVISION 90 53ded750e6SAnthony Koo #define DMUB_FW_VERSION_TEST 0 54ded750e6SAnthony Koo #define DMUB_FW_VERSION_VBIOS 0 55ded750e6SAnthony Koo #define DMUB_FW_VERSION_HOTFIX 0 56ded750e6SAnthony Koo #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 57ded750e6SAnthony Koo ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 58ded750e6SAnthony Koo ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 59ded750e6SAnthony Koo ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 60ded750e6SAnthony Koo ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 61ded750e6SAnthony Koo (DMUB_FW_VERSION_HOTFIX & 0x3F)) 62ded750e6SAnthony Koo 638598a722SAnthony Koo #endif 6484034ad4SAnthony Koo 6584034ad4SAnthony Koo //<DMUB_TYPES>================================================================== 6684034ad4SAnthony Koo /* Basic type definitions. */ 6784034ad4SAnthony Koo 688b19a4e3SAnthony Koo #define __forceinline inline 698b19a4e3SAnthony Koo 701a595f28SAnthony Koo /** 711a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled gradually 721a595f28SAnthony Koo * by slowly reversing all backlight programming and pixel compensation. 731a595f28SAnthony Koo */ 7484034ad4SAnthony Koo #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 751a595f28SAnthony Koo 761a595f28SAnthony Koo /** 771a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 781a595f28SAnthony Koo * and undo all backlight programming and pixel compensation. 791a595f28SAnthony Koo */ 8084034ad4SAnthony Koo #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 811a595f28SAnthony Koo 821a595f28SAnthony Koo /** 831a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 841a595f28SAnthony Koo * and keep the current backlight programming and pixel compensation. 851a595f28SAnthony Koo */ 86d9beecfcSAnthony Koo #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 871a595f28SAnthony Koo 881a595f28SAnthony Koo /** 891a595f28SAnthony Koo * Flag from driver to set the current ABM pipe index or ABM operating level. 901a595f28SAnthony Koo */ 9184034ad4SAnthony Koo #define SET_ABM_PIPE_NORMAL 1 9284034ad4SAnthony Koo 931a595f28SAnthony Koo /** 941a595f28SAnthony Koo * Number of ambient light levels in ABM algorithm. 951a595f28SAnthony Koo */ 961a595f28SAnthony Koo #define NUM_AMBI_LEVEL 5 971a595f28SAnthony Koo 981a595f28SAnthony Koo /** 991a595f28SAnthony Koo * Number of operating/aggression levels in ABM algorithm. 1001a595f28SAnthony Koo */ 1011a595f28SAnthony Koo #define NUM_AGGR_LEVEL 4 1021a595f28SAnthony Koo 1031a595f28SAnthony Koo /** 1041a595f28SAnthony Koo * Number of segments in the gamma curve. 1051a595f28SAnthony Koo */ 1061a595f28SAnthony Koo #define NUM_POWER_FN_SEGS 8 1071a595f28SAnthony Koo 1081a595f28SAnthony Koo /** 1091a595f28SAnthony Koo * Number of segments in the backlight curve. 1101a595f28SAnthony Koo */ 1111a595f28SAnthony Koo #define NUM_BL_CURVE_SEGS 16 1121a595f28SAnthony Koo 11384034ad4SAnthony Koo /* Maximum number of streams on any ASIC. */ 11484034ad4SAnthony Koo #define DMUB_MAX_STREAMS 6 11584034ad4SAnthony Koo 11684034ad4SAnthony Koo /* Maximum number of planes on any ASIC. */ 11784034ad4SAnthony Koo #define DMUB_MAX_PLANES 6 11884034ad4SAnthony Koo 11970732504SYongqiang Sun /* Trace buffer offset for entry */ 12070732504SYongqiang Sun #define TRACE_BUFFER_ENTRY_OFFSET 16 12170732504SYongqiang Sun 122592a6318SAnthony Koo /** 123f56c837aSMikita Lipski * 124f56c837aSMikita Lipski * PSR control version legacy 125f56c837aSMikita Lipski */ 126f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 127f56c837aSMikita Lipski /** 128f56c837aSMikita Lipski * PSR control version with multi edp support 129f56c837aSMikita Lipski */ 130f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 131f56c837aSMikita Lipski 132f56c837aSMikita Lipski 133f56c837aSMikita Lipski /** 13463de4f04SJake Wang * ABM control version legacy 135e922057bSJake Wang */ 13663de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 137e922057bSJake Wang 138e922057bSJake Wang /** 13963de4f04SJake Wang * ABM control version with multi edp support 140e922057bSJake Wang */ 14163de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 142e922057bSJake Wang 143e922057bSJake Wang /** 144592a6318SAnthony Koo * Physical framebuffer address location, 64-bit. 145592a6318SAnthony Koo */ 14684034ad4SAnthony Koo #ifndef PHYSICAL_ADDRESS_LOC 14784034ad4SAnthony Koo #define PHYSICAL_ADDRESS_LOC union large_integer 14884034ad4SAnthony Koo #endif 14984034ad4SAnthony Koo 150592a6318SAnthony Koo /** 151592a6318SAnthony Koo * OS/FW agnostic memcpy 152592a6318SAnthony Koo */ 15384034ad4SAnthony Koo #ifndef dmub_memcpy 15484034ad4SAnthony Koo #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 15584034ad4SAnthony Koo #endif 15684034ad4SAnthony Koo 157592a6318SAnthony Koo /** 158592a6318SAnthony Koo * OS/FW agnostic memset 159592a6318SAnthony Koo */ 16084034ad4SAnthony Koo #ifndef dmub_memset 16184034ad4SAnthony Koo #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 16284034ad4SAnthony Koo #endif 16384034ad4SAnthony Koo 164d9beecfcSAnthony Koo #if defined(__cplusplus) 165d9beecfcSAnthony Koo extern "C" { 166d9beecfcSAnthony Koo #endif 167d9beecfcSAnthony Koo 168592a6318SAnthony Koo /** 169592a6318SAnthony Koo * OS/FW agnostic udelay 170592a6318SAnthony Koo */ 17184034ad4SAnthony Koo #ifndef dmub_udelay 17284034ad4SAnthony Koo #define dmub_udelay(microseconds) udelay(microseconds) 17384034ad4SAnthony Koo #endif 17484034ad4SAnthony Koo 175592a6318SAnthony Koo /** 1760b51e7e8SAnthony Koo * Number of nanoseconds per DMUB tick. 1770b51e7e8SAnthony Koo * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default. 1780b51e7e8SAnthony Koo * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true. 1790b51e7e8SAnthony Koo */ 1800b51e7e8SAnthony Koo #define NS_PER_DMUB_TICK 10 1810b51e7e8SAnthony Koo 1820b51e7e8SAnthony Koo /** 183592a6318SAnthony Koo * union dmub_addr - DMUB physical/virtual 64-bit address. 184592a6318SAnthony Koo */ 18584034ad4SAnthony Koo union dmub_addr { 18684034ad4SAnthony Koo struct { 187592a6318SAnthony Koo uint32_t low_part; /**< Lower 32 bits */ 188592a6318SAnthony Koo uint32_t high_part; /**< Upper 32 bits */ 189592a6318SAnthony Koo } u; /*<< Low/high bit access */ 190592a6318SAnthony Koo uint64_t quad_part; /*<< 64 bit address */ 19184034ad4SAnthony Koo }; 19284034ad4SAnthony Koo 1931a595f28SAnthony Koo /** 1941a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 1951a595f28SAnthony Koo */ 19684034ad4SAnthony Koo union dmub_psr_debug_flags { 1971a595f28SAnthony Koo /** 1981a595f28SAnthony Koo * Debug flags. 1991a595f28SAnthony Koo */ 20084034ad4SAnthony Koo struct { 2011a595f28SAnthony Koo /** 2021a595f28SAnthony Koo * Enable visual confirm in FW. 2031a595f28SAnthony Koo */ 204447f3d0fSAnthony Koo uint32_t visual_confirm : 1; 2051a595f28SAnthony Koo /** 2061a595f28SAnthony Koo * Use HW Lock Mgr object to do HW locking in FW. 2071a595f28SAnthony Koo */ 208447f3d0fSAnthony Koo uint32_t use_hw_lock_mgr : 1; 2091a595f28SAnthony Koo 2101a595f28SAnthony Koo /** 2111a595f28SAnthony Koo * Unused. 2121a595f28SAnthony Koo * TODO: Remove. 2131a595f28SAnthony Koo */ 2148b3f6b98SAnthony Koo uint32_t log_line_nums : 1; 21584034ad4SAnthony Koo } bitfields; 21684034ad4SAnthony Koo 2171a595f28SAnthony Koo /** 2181a595f28SAnthony Koo * Union for debug flags. 2191a595f28SAnthony Koo */ 220447f3d0fSAnthony Koo uint32_t u32All; 22184034ad4SAnthony Koo }; 22284034ad4SAnthony Koo 2231a595f28SAnthony Koo /** 2241a595f28SAnthony Koo * DMUB feature capabilities. 2251a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2261a595f28SAnthony Koo */ 22734ba432cSAnthony Koo struct dmub_feature_caps { 2281a595f28SAnthony Koo /** 2291a595f28SAnthony Koo * Max PSR version supported by FW. 2301a595f28SAnthony Koo */ 23134ba432cSAnthony Koo uint8_t psr; 23234ba432cSAnthony Koo uint8_t reserved[7]; 23334ba432cSAnthony Koo }; 23434ba432cSAnthony Koo 23584034ad4SAnthony Koo #if defined(__cplusplus) 23684034ad4SAnthony Koo } 23784034ad4SAnthony Koo #endif 23884034ad4SAnthony Koo 23984034ad4SAnthony Koo //============================================================================== 24084034ad4SAnthony Koo //</DMUB_TYPES>================================================================= 24184034ad4SAnthony Koo //============================================================================== 24284034ad4SAnthony Koo //< DMUB_META>================================================================== 24384034ad4SAnthony Koo //============================================================================== 24484034ad4SAnthony Koo #pragma pack(push, 1) 24584034ad4SAnthony Koo 24684034ad4SAnthony Koo /* Magic value for identifying dmub_fw_meta_info */ 24784034ad4SAnthony Koo #define DMUB_FW_META_MAGIC 0x444D5542 24884034ad4SAnthony Koo 24984034ad4SAnthony Koo /* Offset from the end of the file to the dmub_fw_meta_info */ 25084034ad4SAnthony Koo #define DMUB_FW_META_OFFSET 0x24 25184034ad4SAnthony Koo 25284034ad4SAnthony Koo /** 25384034ad4SAnthony Koo * struct dmub_fw_meta_info - metadata associated with fw binary 25484034ad4SAnthony Koo * 25584034ad4SAnthony Koo * NOTE: This should be considered a stable API. Fields should 25684034ad4SAnthony Koo * not be repurposed or reordered. New fields should be 25784034ad4SAnthony Koo * added instead to extend the structure. 25884034ad4SAnthony Koo * 25984034ad4SAnthony Koo * @magic_value: magic value identifying DMUB firmware meta info 26084034ad4SAnthony Koo * @fw_region_size: size of the firmware state region 26184034ad4SAnthony Koo * @trace_buffer_size: size of the tracebuffer region 26284034ad4SAnthony Koo * @fw_version: the firmware version information 263b2265774SAnthony Koo * @dal_fw: 1 if the firmware is DAL 26484034ad4SAnthony Koo */ 26584034ad4SAnthony Koo struct dmub_fw_meta_info { 266592a6318SAnthony Koo uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 267592a6318SAnthony Koo uint32_t fw_region_size; /**< size of the firmware state region */ 268592a6318SAnthony Koo uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 269592a6318SAnthony Koo uint32_t fw_version; /**< the firmware version information */ 270592a6318SAnthony Koo uint8_t dal_fw; /**< 1 if the firmware is DAL */ 271592a6318SAnthony Koo uint8_t reserved[3]; /**< padding bits */ 27284034ad4SAnthony Koo }; 27384034ad4SAnthony Koo 274592a6318SAnthony Koo /** 275592a6318SAnthony Koo * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 276592a6318SAnthony Koo */ 27784034ad4SAnthony Koo union dmub_fw_meta { 278592a6318SAnthony Koo struct dmub_fw_meta_info info; /**< metadata info */ 279592a6318SAnthony Koo uint8_t reserved[64]; /**< padding bits */ 28084034ad4SAnthony Koo }; 28184034ad4SAnthony Koo 28284034ad4SAnthony Koo #pragma pack(pop) 283788408b7SAnthony Koo 28484034ad4SAnthony Koo //============================================================================== 2856b66208fSYongqiang Sun //< DMUB Trace Buffer>================================================================ 2866b66208fSYongqiang Sun //============================================================================== 287592a6318SAnthony Koo /** 288592a6318SAnthony Koo * dmub_trace_code_t - firmware trace code, 32-bits 289592a6318SAnthony Koo */ 2906b66208fSYongqiang Sun typedef uint32_t dmub_trace_code_t; 2916b66208fSYongqiang Sun 292592a6318SAnthony Koo /** 293592a6318SAnthony Koo * struct dmcub_trace_buf_entry - Firmware trace entry 294592a6318SAnthony Koo */ 2956b66208fSYongqiang Sun struct dmcub_trace_buf_entry { 296592a6318SAnthony Koo dmub_trace_code_t trace_code; /**< trace code for the event */ 297592a6318SAnthony Koo uint32_t tick_count; /**< the tick count at time of trace */ 298592a6318SAnthony Koo uint32_t param0; /**< trace defined parameter 0 */ 299592a6318SAnthony Koo uint32_t param1; /**< trace defined parameter 1 */ 3006b66208fSYongqiang Sun }; 3016b66208fSYongqiang Sun 3026b66208fSYongqiang Sun //============================================================================== 303788408b7SAnthony Koo //< DMUB_STATUS>================================================================ 304788408b7SAnthony Koo //============================================================================== 305788408b7SAnthony Koo 306788408b7SAnthony Koo /** 307788408b7SAnthony Koo * DMCUB scratch registers can be used to determine firmware status. 308788408b7SAnthony Koo * Current scratch register usage is as follows: 309788408b7SAnthony Koo * 310492dd8a8SAnthony Koo * SCRATCH0: FW Boot Status register 311021eaef8SAnthony Koo * SCRATCH5: LVTMA Status Register 312492dd8a8SAnthony Koo * SCRATCH15: FW Boot Options register 313788408b7SAnthony Koo */ 314788408b7SAnthony Koo 315592a6318SAnthony Koo /** 316592a6318SAnthony Koo * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 317592a6318SAnthony Koo */ 318492dd8a8SAnthony Koo union dmub_fw_boot_status { 319492dd8a8SAnthony Koo struct { 320592a6318SAnthony Koo uint32_t dal_fw : 1; /**< 1 if DAL FW */ 321592a6318SAnthony Koo uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 322592a6318SAnthony Koo uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 323592a6318SAnthony Koo uint32_t restore_required : 1; /**< 1 if driver should call restore */ 32401934c30SAnthony Koo uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 32501934c30SAnthony Koo uint32_t reserved : 1; 32601934c30SAnthony Koo uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 32701934c30SAnthony Koo 328592a6318SAnthony Koo } bits; /**< status bits */ 329592a6318SAnthony Koo uint32_t all; /**< 32-bit access to status bits */ 330492dd8a8SAnthony Koo }; 331492dd8a8SAnthony Koo 332592a6318SAnthony Koo /** 333592a6318SAnthony Koo * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 334592a6318SAnthony Koo */ 335492dd8a8SAnthony Koo enum dmub_fw_boot_status_bit { 336592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 337592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 338592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 339592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 3401e0958bbSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 34101934c30SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 342492dd8a8SAnthony Koo }; 343492dd8a8SAnthony Koo 344021eaef8SAnthony Koo /* Register bit definition for SCRATCH5 */ 345021eaef8SAnthony Koo union dmub_lvtma_status { 346021eaef8SAnthony Koo struct { 347021eaef8SAnthony Koo uint32_t psp_ok : 1; 348021eaef8SAnthony Koo uint32_t edp_on : 1; 349021eaef8SAnthony Koo uint32_t reserved : 30; 350021eaef8SAnthony Koo } bits; 351021eaef8SAnthony Koo uint32_t all; 352021eaef8SAnthony Koo }; 353021eaef8SAnthony Koo 354021eaef8SAnthony Koo enum dmub_lvtma_status_bit { 355021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 356021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 357021eaef8SAnthony Koo }; 358021eaef8SAnthony Koo 359592a6318SAnthony Koo /** 3601e0958bbSAnthony Koo * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 361592a6318SAnthony Koo */ 362492dd8a8SAnthony Koo union dmub_fw_boot_options { 363492dd8a8SAnthony Koo struct { 364592a6318SAnthony Koo uint32_t pemu_env : 1; /**< 1 if PEMU */ 365592a6318SAnthony Koo uint32_t fpga_env : 1; /**< 1 if FPGA */ 366592a6318SAnthony Koo uint32_t optimized_init : 1; /**< 1 if optimized init */ 367592a6318SAnthony Koo uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 368592a6318SAnthony Koo uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 369592a6318SAnthony Koo uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 370b04cb192SNicholas Kazlauskas uint32_t z10_disable: 1; /**< 1 to disable z10 */ 371b0ce6272SMeenakshikumar Somasundaram uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 3721e0958bbSAnthony Koo uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 37339371f7dSMeenakshikumar Somasundaram uint32_t reserved_unreleased2: 1; /**< reserved for an unreleased feature */ 374b129c94eSAnthony Koo uint32_t root_clock_gating: 1; /**< 1 if all root clock gating is enabled */ 375b129c94eSAnthony Koo uint32_t diag_env: 1; /* 1 if diagnostic environment */ 376b129c94eSAnthony Koo 377b129c94eSAnthony Koo uint32_t reserved : 19; /**< reserved */ 378592a6318SAnthony Koo } bits; /**< boot bits */ 379592a6318SAnthony Koo uint32_t all; /**< 32-bit access to bits */ 380492dd8a8SAnthony Koo }; 381492dd8a8SAnthony Koo 382492dd8a8SAnthony Koo enum dmub_fw_boot_options_bit { 383592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 384592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 385592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 386492dd8a8SAnthony Koo }; 387492dd8a8SAnthony Koo 388788408b7SAnthony Koo //============================================================================== 389788408b7SAnthony Koo //</DMUB_STATUS>================================================================ 39084034ad4SAnthony Koo //============================================================================== 39184034ad4SAnthony Koo //< DMUB_VBIOS>================================================================= 39284034ad4SAnthony Koo //============================================================================== 39384034ad4SAnthony Koo 39484034ad4SAnthony Koo /* 395592a6318SAnthony Koo * enum dmub_cmd_vbios_type - VBIOS commands. 396592a6318SAnthony Koo * 39784034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 39884034ad4SAnthony Koo * Do not reuse or modify IDs. 39984034ad4SAnthony Koo */ 40084034ad4SAnthony Koo enum dmub_cmd_vbios_type { 401592a6318SAnthony Koo /** 402592a6318SAnthony Koo * Configures the DIG encoder. 403592a6318SAnthony Koo */ 40484034ad4SAnthony Koo DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 405592a6318SAnthony Koo /** 406592a6318SAnthony Koo * Controls the PHY. 407592a6318SAnthony Koo */ 40884034ad4SAnthony Koo DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 409592a6318SAnthony Koo /** 410592a6318SAnthony Koo * Sets the pixel clock/symbol clock. 411592a6318SAnthony Koo */ 41284034ad4SAnthony Koo DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 413592a6318SAnthony Koo /** 414592a6318SAnthony Koo * Enables or disables power gating. 415592a6318SAnthony Koo */ 41684034ad4SAnthony Koo DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 4172ac685bfSAnthony Koo DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 41884034ad4SAnthony Koo }; 41984034ad4SAnthony Koo 42084034ad4SAnthony Koo //============================================================================== 42184034ad4SAnthony Koo //</DMUB_VBIOS>================================================================= 42284034ad4SAnthony Koo //============================================================================== 42384034ad4SAnthony Koo //< DMUB_GPINT>================================================================= 42484034ad4SAnthony Koo //============================================================================== 42584034ad4SAnthony Koo 42684034ad4SAnthony Koo /** 42784034ad4SAnthony Koo * The shifts and masks below may alternatively be used to format and read 42884034ad4SAnthony Koo * the command register bits. 42984034ad4SAnthony Koo */ 43084034ad4SAnthony Koo 43184034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 43284034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_SHIFT 0 43384034ad4SAnthony Koo 43484034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 43584034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 43684034ad4SAnthony Koo 43784034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_MASK 0xF 43884034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_SHIFT 28 43984034ad4SAnthony Koo 44084034ad4SAnthony Koo /** 44184034ad4SAnthony Koo * Command responses. 44284034ad4SAnthony Koo */ 44384034ad4SAnthony Koo 444592a6318SAnthony Koo /** 445592a6318SAnthony Koo * Return response for DMUB_GPINT__STOP_FW command. 446592a6318SAnthony Koo */ 44784034ad4SAnthony Koo #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 44884034ad4SAnthony Koo 44984034ad4SAnthony Koo /** 450592a6318SAnthony Koo * union dmub_gpint_data_register - Format for sending a command via the GPINT. 45184034ad4SAnthony Koo */ 45284034ad4SAnthony Koo union dmub_gpint_data_register { 45384034ad4SAnthony Koo struct { 454592a6318SAnthony Koo uint32_t param : 16; /**< 16-bit parameter */ 455592a6318SAnthony Koo uint32_t command_code : 12; /**< GPINT command */ 456592a6318SAnthony Koo uint32_t status : 4; /**< Command status bit */ 457592a6318SAnthony Koo } bits; /**< GPINT bit access */ 458592a6318SAnthony Koo uint32_t all; /**< GPINT 32-bit access */ 45984034ad4SAnthony Koo }; 46084034ad4SAnthony Koo 46184034ad4SAnthony Koo /* 462592a6318SAnthony Koo * enum dmub_gpint_command - GPINT command to DMCUB FW 463592a6318SAnthony Koo * 46484034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 46584034ad4SAnthony Koo * Do not reuse or modify IDs. 46684034ad4SAnthony Koo */ 46784034ad4SAnthony Koo enum dmub_gpint_command { 468592a6318SAnthony Koo /** 469592a6318SAnthony Koo * Invalid command, ignored. 470592a6318SAnthony Koo */ 47184034ad4SAnthony Koo DMUB_GPINT__INVALID_COMMAND = 0, 472592a6318SAnthony Koo /** 473592a6318SAnthony Koo * DESC: Queries the firmware version. 474592a6318SAnthony Koo * RETURN: Firmware version. 475592a6318SAnthony Koo */ 47684034ad4SAnthony Koo DMUB_GPINT__GET_FW_VERSION = 1, 477592a6318SAnthony Koo /** 478592a6318SAnthony Koo * DESC: Halts the firmware. 479592a6318SAnthony Koo * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 480592a6318SAnthony Koo */ 48184034ad4SAnthony Koo DMUB_GPINT__STOP_FW = 2, 4821a595f28SAnthony Koo /** 4831a595f28SAnthony Koo * DESC: Get PSR state from FW. 4841a595f28SAnthony Koo * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 4851a595f28SAnthony Koo */ 48684034ad4SAnthony Koo DMUB_GPINT__GET_PSR_STATE = 7, 48780eba958SAnthony Koo /** 48880eba958SAnthony Koo * DESC: Notifies DMCUB of the currently active streams. 48980eba958SAnthony Koo * ARGS: Stream mask, 1 bit per active stream index. 49080eba958SAnthony Koo */ 49180eba958SAnthony Koo DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 4921a595f28SAnthony Koo /** 4931a595f28SAnthony Koo * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 4941a595f28SAnthony Koo * ARGS: We can measure residency from various points. The argument will specify the residency mode. 4951a595f28SAnthony Koo * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 4961a595f28SAnthony Koo * RETURN: PSR residency in milli-percent. 4971a595f28SAnthony Koo */ 498672251b2SAnthony Koo DMUB_GPINT__PSR_RESIDENCY = 9, 49901934c30SAnthony Koo 50001934c30SAnthony Koo /** 50101934c30SAnthony Koo * DESC: Notifies DMCUB detection is done so detection required can be cleared. 50201934c30SAnthony Koo */ 50301934c30SAnthony Koo DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 50484034ad4SAnthony Koo }; 50584034ad4SAnthony Koo 5060b51e7e8SAnthony Koo /** 5070b51e7e8SAnthony Koo * INBOX0 generic command definition 5080b51e7e8SAnthony Koo */ 5090b51e7e8SAnthony Koo union dmub_inbox0_cmd_common { 5100b51e7e8SAnthony Koo struct { 5110b51e7e8SAnthony Koo uint32_t command_code: 8; /**< INBOX0 command code */ 5120b51e7e8SAnthony Koo uint32_t param: 24; /**< 24-bit parameter */ 5130b51e7e8SAnthony Koo } bits; 5140b51e7e8SAnthony Koo uint32_t all; 5150b51e7e8SAnthony Koo }; 5160b51e7e8SAnthony Koo 5170b51e7e8SAnthony Koo /** 5180b51e7e8SAnthony Koo * INBOX0 hw_lock command definition 5190b51e7e8SAnthony Koo */ 5200b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw { 5210b51e7e8SAnthony Koo struct { 5220b51e7e8SAnthony Koo uint32_t command_code: 8; 5230b51e7e8SAnthony Koo 5240b51e7e8SAnthony Koo /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 5250b51e7e8SAnthony Koo uint32_t hw_lock_client: 1; 5260b51e7e8SAnthony Koo 5270b51e7e8SAnthony Koo /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 5280b51e7e8SAnthony Koo uint32_t otg_inst: 3; 5290b51e7e8SAnthony Koo uint32_t opp_inst: 3; 5300b51e7e8SAnthony Koo uint32_t dig_inst: 3; 5310b51e7e8SAnthony Koo 5320b51e7e8SAnthony Koo /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 5330b51e7e8SAnthony Koo uint32_t lock_pipe: 1; 5340b51e7e8SAnthony Koo uint32_t lock_cursor: 1; 5350b51e7e8SAnthony Koo uint32_t lock_dig: 1; 5360b51e7e8SAnthony Koo uint32_t triple_buffer_lock: 1; 5370b51e7e8SAnthony Koo 5380b51e7e8SAnthony Koo uint32_t lock: 1; /**< Lock */ 5390b51e7e8SAnthony Koo uint32_t should_release: 1; /**< Release */ 5400b51e7e8SAnthony Koo uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */ 5410b51e7e8SAnthony Koo } bits; 5420b51e7e8SAnthony Koo uint32_t all; 5430b51e7e8SAnthony Koo }; 5440b51e7e8SAnthony Koo 5450b51e7e8SAnthony Koo union dmub_inbox0_data_register { 5460b51e7e8SAnthony Koo union dmub_inbox0_cmd_common inbox0_cmd_common; 5470b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 5480b51e7e8SAnthony Koo }; 5490b51e7e8SAnthony Koo 5500b51e7e8SAnthony Koo enum dmub_inbox0_command { 5510b51e7e8SAnthony Koo /** 5520b51e7e8SAnthony Koo * DESC: Invalid command, ignored. 5530b51e7e8SAnthony Koo */ 5540b51e7e8SAnthony Koo DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 5550b51e7e8SAnthony Koo /** 5560b51e7e8SAnthony Koo * DESC: Notification to acquire/release HW lock 5570b51e7e8SAnthony Koo * ARGS: 5580b51e7e8SAnthony Koo */ 5590b51e7e8SAnthony Koo DMUB_INBOX0_CMD__HW_LOCK = 1, 5600b51e7e8SAnthony Koo }; 56184034ad4SAnthony Koo //============================================================================== 56284034ad4SAnthony Koo //</DMUB_GPINT>================================================================= 56384034ad4SAnthony Koo //============================================================================== 56484034ad4SAnthony Koo //< DMUB_CMD>=================================================================== 56584034ad4SAnthony Koo //============================================================================== 56684034ad4SAnthony Koo 567592a6318SAnthony Koo /** 568592a6318SAnthony Koo * Size in bytes of each DMUB command. 569592a6318SAnthony Koo */ 5707c008829SNicholas Kazlauskas #define DMUB_RB_CMD_SIZE 64 571592a6318SAnthony Koo 572592a6318SAnthony Koo /** 573592a6318SAnthony Koo * Maximum number of items in the DMUB ringbuffer. 574592a6318SAnthony Koo */ 5757c008829SNicholas Kazlauskas #define DMUB_RB_MAX_ENTRY 128 576592a6318SAnthony Koo 577592a6318SAnthony Koo /** 578592a6318SAnthony Koo * Ringbuffer size in bytes. 579592a6318SAnthony Koo */ 5807c008829SNicholas Kazlauskas #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 581592a6318SAnthony Koo 582592a6318SAnthony Koo /** 583592a6318SAnthony Koo * REG_SET mask for reg offload. 584592a6318SAnthony Koo */ 5857c008829SNicholas Kazlauskas #define REG_SET_MASK 0xFFFF 5867c008829SNicholas Kazlauskas 587d4bbcecbSNicholas Kazlauskas /* 588592a6318SAnthony Koo * enum dmub_cmd_type - DMUB inbox command. 589592a6318SAnthony Koo * 590d4bbcecbSNicholas Kazlauskas * Command IDs should be treated as stable ABI. 591d4bbcecbSNicholas Kazlauskas * Do not reuse or modify IDs. 592d4bbcecbSNicholas Kazlauskas */ 593d4bbcecbSNicholas Kazlauskas enum dmub_cmd_type { 594592a6318SAnthony Koo /** 595592a6318SAnthony Koo * Invalid command. 596592a6318SAnthony Koo */ 597d4bbcecbSNicholas Kazlauskas DMUB_CMD__NULL = 0, 598592a6318SAnthony Koo /** 599592a6318SAnthony Koo * Read modify write register sequence offload. 600592a6318SAnthony Koo */ 601d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 602592a6318SAnthony Koo /** 603592a6318SAnthony Koo * Field update register sequence offload. 604592a6318SAnthony Koo */ 605d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 606592a6318SAnthony Koo /** 607592a6318SAnthony Koo * Burst write sequence offload. 608592a6318SAnthony Koo */ 609d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 610592a6318SAnthony Koo /** 611592a6318SAnthony Koo * Reg wait sequence offload. 612592a6318SAnthony Koo */ 613d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_REG_WAIT = 4, 614592a6318SAnthony Koo /** 615592a6318SAnthony Koo * Workaround to avoid HUBP underflow during NV12 playback. 616592a6318SAnthony Koo */ 617bae9c49bSYongqiang Sun DMUB_CMD__PLAT_54186_WA = 5, 6181a595f28SAnthony Koo /** 6191a595f28SAnthony Koo * Command type used to query FW feature caps. 6201a595f28SAnthony Koo */ 62134ba432cSAnthony Koo DMUB_CMD__QUERY_FEATURE_CAPS = 6, 6221a595f28SAnthony Koo /** 6231a595f28SAnthony Koo * Command type used for all PSR commands. 6241a595f28SAnthony Koo */ 625d4bbcecbSNicholas Kazlauskas DMUB_CMD__PSR = 64, 626592a6318SAnthony Koo /** 627592a6318SAnthony Koo * Command type used for all MALL commands. 628592a6318SAnthony Koo */ 62952f2e83eSBhawanpreet Lakha DMUB_CMD__MALL = 65, 6301a595f28SAnthony Koo /** 6311a595f28SAnthony Koo * Command type used for all ABM commands. 6321a595f28SAnthony Koo */ 633e6ea8c34SWyatt Wood DMUB_CMD__ABM = 66, 6341a595f28SAnthony Koo /** 6351a595f28SAnthony Koo * Command type used for HW locking in FW. 6361a595f28SAnthony Koo */ 637788408b7SAnthony Koo DMUB_CMD__HW_LOCK = 69, 6381a595f28SAnthony Koo /** 6391a595f28SAnthony Koo * Command type used to access DP AUX. 6401a595f28SAnthony Koo */ 641d9beecfcSAnthony Koo DMUB_CMD__DP_AUX_ACCESS = 70, 6421a595f28SAnthony Koo /** 6431a595f28SAnthony Koo * Command type used for OUTBOX1 notification enable 6441a595f28SAnthony Koo */ 645d9beecfcSAnthony Koo DMUB_CMD__OUTBOX1_ENABLE = 71, 646b04cb192SNicholas Kazlauskas /** 647b04cb192SNicholas Kazlauskas * Command type used for all idle optimization commands. 648b04cb192SNicholas Kazlauskas */ 649b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT = 72, 650b04cb192SNicholas Kazlauskas /** 651b04cb192SNicholas Kazlauskas * Command type used for all clock manager commands. 652b04cb192SNicholas Kazlauskas */ 653b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR = 73, 654b04cb192SNicholas Kazlauskas /** 655b04cb192SNicholas Kazlauskas * Command type used for all panel control commands. 656b04cb192SNicholas Kazlauskas */ 657b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL = 74, 658592a6318SAnthony Koo /** 65976724b76SJimmy Kizito * Command type used for interfacing with DPIA. 66076724b76SJimmy Kizito */ 66176724b76SJimmy Kizito DMUB_CMD__DPIA = 77, 66276724b76SJimmy Kizito /** 663021eaef8SAnthony Koo * Command type used for EDID CEA parsing 664021eaef8SAnthony Koo */ 665021eaef8SAnthony Koo DMUB_CMD__EDID_CEA = 79, 666021eaef8SAnthony Koo /** 667592a6318SAnthony Koo * Command type used for all VBIOS interface commands. 668592a6318SAnthony Koo */ 669d4bbcecbSNicholas Kazlauskas DMUB_CMD__VBIOS = 128, 6707c008829SNicholas Kazlauskas }; 6717c008829SNicholas Kazlauskas 672592a6318SAnthony Koo /** 673592a6318SAnthony Koo * enum dmub_out_cmd_type - DMUB outbox commands. 674592a6318SAnthony Koo */ 6753b37260bSAnthony Koo enum dmub_out_cmd_type { 676592a6318SAnthony Koo /** 677592a6318SAnthony Koo * Invalid outbox command, ignored. 678592a6318SAnthony Koo */ 6793b37260bSAnthony Koo DMUB_OUT_CMD__NULL = 0, 6801a595f28SAnthony Koo /** 6811a595f28SAnthony Koo * Command type used for DP AUX Reply data notification 6821a595f28SAnthony Koo */ 683d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_AUX_REPLY = 1, 684892b74a6SMeenakshikumar Somasundaram /** 685892b74a6SMeenakshikumar Somasundaram * Command type used for DP HPD event notification 686892b74a6SMeenakshikumar Somasundaram */ 687892b74a6SMeenakshikumar Somasundaram DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 68871af9d46SMeenakshikumar Somasundaram /** 68971af9d46SMeenakshikumar Somasundaram * Command type used for SET_CONFIG Reply notification 69071af9d46SMeenakshikumar Somasundaram */ 69171af9d46SMeenakshikumar Somasundaram DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 6923b37260bSAnthony Koo }; 6933b37260bSAnthony Koo 69476724b76SJimmy Kizito /* DMUB_CMD__DPIA command sub-types. */ 69576724b76SJimmy Kizito enum dmub_cmd_dpia_type { 69676724b76SJimmy Kizito DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 69771af9d46SMeenakshikumar Somasundaram DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 69876724b76SJimmy Kizito }; 69976724b76SJimmy Kizito 7007c008829SNicholas Kazlauskas #pragma pack(push, 1) 7017c008829SNicholas Kazlauskas 702592a6318SAnthony Koo /** 703592a6318SAnthony Koo * struct dmub_cmd_header - Common command header fields. 704592a6318SAnthony Koo */ 7057c008829SNicholas Kazlauskas struct dmub_cmd_header { 706592a6318SAnthony Koo unsigned int type : 8; /**< command type */ 707592a6318SAnthony Koo unsigned int sub_type : 8; /**< command sub type */ 708592a6318SAnthony Koo unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 7090b51e7e8SAnthony Koo unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 7100b51e7e8SAnthony Koo unsigned int reserved0 : 6; /**< reserved bits */ 711592a6318SAnthony Koo unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 712592a6318SAnthony Koo unsigned int reserved1 : 2; /**< reserved bits */ 7137c008829SNicholas Kazlauskas }; 7147c008829SNicholas Kazlauskas 7157c008829SNicholas Kazlauskas /* 716592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write 7177c008829SNicholas Kazlauskas * 7187c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 5 sets of read modify writes, 7197c008829SNicholas Kazlauskas * each take 3 dwords. 7207c008829SNicholas Kazlauskas * 7217c008829SNicholas Kazlauskas * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 7227c008829SNicholas Kazlauskas * 7237c008829SNicholas Kazlauskas * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 7247c008829SNicholas Kazlauskas * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 7257c008829SNicholas Kazlauskas */ 7267c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence { 727592a6318SAnthony Koo uint32_t addr; /**< register address */ 728592a6318SAnthony Koo uint32_t modify_mask; /**< modify mask */ 729592a6318SAnthony Koo uint32_t modify_value; /**< modify value */ 7307c008829SNicholas Kazlauskas }; 7317c008829SNicholas Kazlauskas 732592a6318SAnthony Koo /** 733592a6318SAnthony Koo * Maximum number of ops in read modify write sequence. 734592a6318SAnthony Koo */ 7357c008829SNicholas Kazlauskas #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 736592a6318SAnthony Koo 737592a6318SAnthony Koo /** 738592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 739592a6318SAnthony Koo */ 7407c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write { 741592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 742592a6318SAnthony Koo /** 743592a6318SAnthony Koo * Read modify write sequence. 744592a6318SAnthony Koo */ 7457c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 7467c008829SNicholas Kazlauskas }; 7477c008829SNicholas Kazlauskas 7487c008829SNicholas Kazlauskas /* 7497c008829SNicholas Kazlauskas * Update a register with specified masks and values sequeunce 7507c008829SNicholas Kazlauskas * 7517c008829SNicholas Kazlauskas * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 7527c008829SNicholas Kazlauskas * 7537c008829SNicholas Kazlauskas * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 7547c008829SNicholas Kazlauskas * 7557c008829SNicholas Kazlauskas * 7567c008829SNicholas Kazlauskas * USE CASE: 7577c008829SNicholas Kazlauskas * 1. auto-increment register where additional read would update pointer and produce wrong result 7587c008829SNicholas Kazlauskas * 2. toggle a bit without read in the middle 7597c008829SNicholas Kazlauskas */ 7607c008829SNicholas Kazlauskas 7617c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence { 762592a6318SAnthony Koo uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 763592a6318SAnthony Koo uint32_t modify_value; /**< value to update with */ 7647c008829SNicholas Kazlauskas }; 7657c008829SNicholas Kazlauskas 766592a6318SAnthony Koo /** 767592a6318SAnthony Koo * Maximum number of ops in field update sequence. 768592a6318SAnthony Koo */ 7697c008829SNicholas Kazlauskas #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 770592a6318SAnthony Koo 771592a6318SAnthony Koo /** 772592a6318SAnthony Koo * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 773592a6318SAnthony Koo */ 7747c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence { 775592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 776592a6318SAnthony Koo uint32_t addr; /**< register address */ 777592a6318SAnthony Koo /** 778592a6318SAnthony Koo * Field update sequence. 779592a6318SAnthony Koo */ 7807c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 7817c008829SNicholas Kazlauskas }; 7827c008829SNicholas Kazlauskas 783592a6318SAnthony Koo 784592a6318SAnthony Koo /** 785592a6318SAnthony Koo * Maximum number of burst write values. 786592a6318SAnthony Koo */ 787592a6318SAnthony Koo #define DMUB_BURST_WRITE_VALUES__MAX 14 788592a6318SAnthony Koo 7897c008829SNicholas Kazlauskas /* 790592a6318SAnthony Koo * struct dmub_rb_cmd_burst_write - Burst write 7917c008829SNicholas Kazlauskas * 7927c008829SNicholas Kazlauskas * support use case such as writing out LUTs. 7937c008829SNicholas Kazlauskas * 7947c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 14 values to write to given address 7957c008829SNicholas Kazlauskas * 7967c008829SNicholas Kazlauskas * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 7977c008829SNicholas Kazlauskas */ 7987c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write { 799592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 800592a6318SAnthony Koo uint32_t addr; /**< register start address */ 801592a6318SAnthony Koo /** 802592a6318SAnthony Koo * Burst write register values. 803592a6318SAnthony Koo */ 8047c008829SNicholas Kazlauskas uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 8057c008829SNicholas Kazlauskas }; 8067c008829SNicholas Kazlauskas 807592a6318SAnthony Koo /** 808592a6318SAnthony Koo * struct dmub_rb_cmd_common - Common command header 809592a6318SAnthony Koo */ 8107c008829SNicholas Kazlauskas struct dmub_rb_cmd_common { 811592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 812592a6318SAnthony Koo /** 813592a6318SAnthony Koo * Padding to RB_CMD_SIZE 814592a6318SAnthony Koo */ 8157c008829SNicholas Kazlauskas uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 8167c008829SNicholas Kazlauskas }; 8177c008829SNicholas Kazlauskas 818592a6318SAnthony Koo /** 819592a6318SAnthony Koo * struct dmub_cmd_reg_wait_data - Register wait data 820592a6318SAnthony Koo */ 8217c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data { 822592a6318SAnthony Koo uint32_t addr; /**< Register address */ 823592a6318SAnthony Koo uint32_t mask; /**< Mask for register bits */ 824592a6318SAnthony Koo uint32_t condition_field_value; /**< Value to wait for */ 825592a6318SAnthony Koo uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 8267c008829SNicholas Kazlauskas }; 8277c008829SNicholas Kazlauskas 828592a6318SAnthony Koo /** 829592a6318SAnthony Koo * struct dmub_rb_cmd_reg_wait - Register wait command 830592a6318SAnthony Koo */ 8317c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait { 832592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 833592a6318SAnthony Koo struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 8347c008829SNicholas Kazlauskas }; 8357c008829SNicholas Kazlauskas 836592a6318SAnthony Koo /** 837592a6318SAnthony Koo * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 838592a6318SAnthony Koo * 839592a6318SAnthony Koo * Reprograms surface parameters to avoid underflow. 840592a6318SAnthony Koo */ 841bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa { 842592a6318SAnthony Koo uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 843592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 844592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 845592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 846592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 84722aa5614SYongqiang Sun struct { 848592a6318SAnthony Koo uint8_t hubp_inst : 4; /**< HUBP instance */ 849592a6318SAnthony Koo uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 850592a6318SAnthony Koo uint8_t immediate :1; /**< Immediate flip */ 851592a6318SAnthony Koo uint8_t vmid : 4; /**< VMID */ 852592a6318SAnthony Koo uint8_t grph_stereo : 1; /**< 1 if stereo */ 853592a6318SAnthony Koo uint32_t reserved : 21; /**< Reserved */ 854592a6318SAnthony Koo } flip_params; /**< Pageflip parameters */ 855592a6318SAnthony Koo uint32_t reserved[9]; /**< Reserved bits */ 8568c019253SYongqiang Sun }; 8578c019253SYongqiang Sun 858592a6318SAnthony Koo /** 859592a6318SAnthony Koo * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 860592a6318SAnthony Koo */ 861bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa { 862592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 863592a6318SAnthony Koo struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 8648c019253SYongqiang Sun }; 8658c019253SYongqiang Sun 866592a6318SAnthony Koo /** 867592a6318SAnthony Koo * struct dmub_rb_cmd_mall - MALL command data. 868592a6318SAnthony Koo */ 86952f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall { 870592a6318SAnthony Koo struct dmub_cmd_header header; /**< Common command header */ 871592a6318SAnthony Koo union dmub_addr cursor_copy_src; /**< Cursor copy address */ 872592a6318SAnthony Koo union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 873592a6318SAnthony Koo uint32_t tmr_delay; /**< Timer delay */ 874592a6318SAnthony Koo uint32_t tmr_scale; /**< Timer scale */ 875592a6318SAnthony Koo uint16_t cursor_width; /**< Cursor width in pixels */ 876592a6318SAnthony Koo uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 877592a6318SAnthony Koo uint16_t cursor_height; /**< Cursor height in pixels */ 878592a6318SAnthony Koo uint8_t cursor_bpp; /**< Cursor bits per pixel */ 879592a6318SAnthony Koo uint8_t debug_bits; /**< Debug bits */ 880ea7154d8SBhawanpreet Lakha 881592a6318SAnthony Koo uint8_t reserved1; /**< Reserved bits */ 882592a6318SAnthony Koo uint8_t reserved2; /**< Reserved bits */ 88352f2e83eSBhawanpreet Lakha }; 88452f2e83eSBhawanpreet Lakha 885b04cb192SNicholas Kazlauskas /** 886b04cb192SNicholas Kazlauskas * enum dmub_cmd_idle_opt_type - Idle optimization command type. 887b04cb192SNicholas Kazlauskas */ 888b04cb192SNicholas Kazlauskas enum dmub_cmd_idle_opt_type { 889b04cb192SNicholas Kazlauskas /** 890b04cb192SNicholas Kazlauskas * DCN hardware restore. 891b04cb192SNicholas Kazlauskas */ 892b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 893f586fea8SJake Wang 894f586fea8SJake Wang /** 895f586fea8SJake Wang * DCN hardware save. 896f586fea8SJake Wang */ 897f586fea8SJake Wang DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 898b04cb192SNicholas Kazlauskas }; 899b04cb192SNicholas Kazlauskas 900b04cb192SNicholas Kazlauskas /** 901b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 902b04cb192SNicholas Kazlauskas */ 903b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore { 904b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 905b04cb192SNicholas Kazlauskas }; 906b04cb192SNicholas Kazlauskas 907b04cb192SNicholas Kazlauskas /** 908b04cb192SNicholas Kazlauskas * struct dmub_clocks - Clock update notification. 909b04cb192SNicholas Kazlauskas */ 910b04cb192SNicholas Kazlauskas struct dmub_clocks { 911b04cb192SNicholas Kazlauskas uint32_t dispclk_khz; /**< dispclk kHz */ 912b04cb192SNicholas Kazlauskas uint32_t dppclk_khz; /**< dppclk kHz */ 913b04cb192SNicholas Kazlauskas uint32_t dcfclk_khz; /**< dcfclk kHz */ 914b04cb192SNicholas Kazlauskas uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 915b04cb192SNicholas Kazlauskas }; 916b04cb192SNicholas Kazlauskas 917b04cb192SNicholas Kazlauskas /** 918b04cb192SNicholas Kazlauskas * enum dmub_cmd_clk_mgr_type - Clock manager commands. 919b04cb192SNicholas Kazlauskas */ 920b04cb192SNicholas Kazlauskas enum dmub_cmd_clk_mgr_type { 921b04cb192SNicholas Kazlauskas /** 922b04cb192SNicholas Kazlauskas * Notify DMCUB of clock update. 923b04cb192SNicholas Kazlauskas */ 924b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 925b04cb192SNicholas Kazlauskas }; 926b04cb192SNicholas Kazlauskas 927b04cb192SNicholas Kazlauskas /** 928b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 929b04cb192SNicholas Kazlauskas */ 930b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks { 931b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 932b04cb192SNicholas Kazlauskas struct dmub_clocks clocks; /**< clock data */ 933b04cb192SNicholas Kazlauskas }; 9348fe44c08SAlex Deucher 935592a6318SAnthony Koo /** 936592a6318SAnthony Koo * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 937592a6318SAnthony Koo */ 9387c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data { 939592a6318SAnthony Koo union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 9407c008829SNicholas Kazlauskas }; 9417c008829SNicholas Kazlauskas 942592a6318SAnthony Koo /** 943592a6318SAnthony Koo * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 944592a6318SAnthony Koo */ 9457c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control { 946592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 947592a6318SAnthony Koo struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 9487c008829SNicholas Kazlauskas }; 9497c008829SNicholas Kazlauskas 950592a6318SAnthony Koo /** 951592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 952592a6318SAnthony Koo */ 9537c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data { 954592a6318SAnthony Koo struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 9557c008829SNicholas Kazlauskas }; 9567c008829SNicholas Kazlauskas 957592a6318SAnthony Koo /** 958592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 959592a6318SAnthony Koo */ 9607c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock { 961592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 962592a6318SAnthony Koo struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 9637c008829SNicholas Kazlauskas }; 9647c008829SNicholas Kazlauskas 965592a6318SAnthony Koo /** 966592a6318SAnthony Koo * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 967592a6318SAnthony Koo */ 9687c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data { 969592a6318SAnthony Koo struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 9707c008829SNicholas Kazlauskas }; 9717c008829SNicholas Kazlauskas 972592a6318SAnthony Koo /** 973592a6318SAnthony Koo * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 974592a6318SAnthony Koo */ 9757c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating { 976592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 977592a6318SAnthony Koo struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 9787c008829SNicholas Kazlauskas }; 9797c008829SNicholas Kazlauskas 980592a6318SAnthony Koo /** 981592a6318SAnthony Koo * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 982592a6318SAnthony Koo */ 983d448521eSAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 { 984d448521eSAnthony Koo uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 985d448521eSAnthony Koo uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 986d448521eSAnthony Koo union { 987d448521eSAnthony Koo uint8_t digmode; /**< enum atom_encode_mode_def */ 988d448521eSAnthony Koo uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 989d448521eSAnthony Koo } mode_laneset; 990d448521eSAnthony Koo uint8_t lanenum; /**< Number of lanes */ 991d448521eSAnthony Koo union { 992d448521eSAnthony Koo uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 993d448521eSAnthony Koo } symclk_units; 994d448521eSAnthony Koo uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 995d448521eSAnthony Koo uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 996d448521eSAnthony Koo uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 9975a2730fcSFangzhi Zuo uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 998d448521eSAnthony Koo uint8_t reserved1; /**< For future use */ 999d448521eSAnthony Koo uint8_t reserved2[3]; /**< For future use */ 1000d448521eSAnthony Koo uint32_t reserved3[11]; /**< For future use */ 1001d448521eSAnthony Koo }; 1002d448521eSAnthony Koo 1003592a6318SAnthony Koo /** 1004592a6318SAnthony Koo * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1005592a6318SAnthony Koo */ 1006d448521eSAnthony Koo union dmub_cmd_dig1_transmitter_control_data { 1007592a6318SAnthony Koo struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1008592a6318SAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 10097c008829SNicholas Kazlauskas }; 10107c008829SNicholas Kazlauskas 1011592a6318SAnthony Koo /** 1012592a6318SAnthony Koo * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1013592a6318SAnthony Koo */ 10147c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control { 1015592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1016592a6318SAnthony Koo union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 10177c008829SNicholas Kazlauskas }; 10187c008829SNicholas Kazlauskas 1019592a6318SAnthony Koo /** 102076724b76SJimmy Kizito * DPIA tunnel command parameters. 102176724b76SJimmy Kizito */ 102276724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data { 102376724b76SJimmy Kizito uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 102476724b76SJimmy Kizito uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 102576724b76SJimmy Kizito union { 102676724b76SJimmy Kizito uint8_t digmode; /** enum atom_encode_mode_def */ 102776724b76SJimmy Kizito uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 102876724b76SJimmy Kizito } mode_laneset; 102976724b76SJimmy Kizito uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 103076724b76SJimmy Kizito uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 103176724b76SJimmy Kizito uint8_t hpdsel; /** =0: HPD is not assigned */ 103276724b76SJimmy Kizito uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 103376724b76SJimmy Kizito uint8_t dpia_id; /** Index of DPIA */ 103476724b76SJimmy Kizito uint8_t fec_rdy : 1; 103576724b76SJimmy Kizito uint8_t reserved : 7; 103676724b76SJimmy Kizito uint32_t reserved1; 103776724b76SJimmy Kizito }; 103876724b76SJimmy Kizito 103976724b76SJimmy Kizito /** 104076724b76SJimmy Kizito * DMUB command for DPIA tunnel control. 104176724b76SJimmy Kizito */ 104276724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control { 104376724b76SJimmy Kizito struct dmub_cmd_header header; 104476724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data dpia_control; 104576724b76SJimmy Kizito }; 104676724b76SJimmy Kizito 104776724b76SJimmy Kizito /** 104871af9d46SMeenakshikumar Somasundaram * SET_CONFIG Command Payload 104971af9d46SMeenakshikumar Somasundaram */ 105071af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload { 105171af9d46SMeenakshikumar Somasundaram uint8_t msg_type; /* set config message type */ 105271af9d46SMeenakshikumar Somasundaram uint8_t msg_data; /* set config message data */ 105371af9d46SMeenakshikumar Somasundaram }; 105471af9d46SMeenakshikumar Somasundaram 105571af9d46SMeenakshikumar Somasundaram /** 105671af9d46SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 105771af9d46SMeenakshikumar Somasundaram */ 105871af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data { 105971af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload cmd_pkt; 106071af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */ 106171af9d46SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned in case of error */ 106271af9d46SMeenakshikumar Somasundaram }; 106371af9d46SMeenakshikumar Somasundaram 106471af9d46SMeenakshikumar Somasundaram /** 106571af9d46SMeenakshikumar Somasundaram * DMUB command structure for SET_CONFIG command. 106671af9d46SMeenakshikumar Somasundaram */ 106771af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access { 106871af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 106971af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 107071af9d46SMeenakshikumar Somasundaram }; 107171af9d46SMeenakshikumar Somasundaram 107271af9d46SMeenakshikumar Somasundaram /** 1073592a6318SAnthony Koo * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1074592a6318SAnthony Koo */ 10757c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init { 1076592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1077592a6318SAnthony Koo uint8_t reserved[60]; /**< reserved bits */ 10787c008829SNicholas Kazlauskas }; 10797c008829SNicholas Kazlauskas 10801a595f28SAnthony Koo /** 10811a595f28SAnthony Koo * enum dp_aux_request_action - DP AUX request command listing. 10821a595f28SAnthony Koo * 10831a595f28SAnthony Koo * 4 AUX request command bits are shifted to high nibble. 10841a595f28SAnthony Koo */ 1085d9beecfcSAnthony Koo enum dp_aux_request_action { 10861a595f28SAnthony Koo /** I2C-over-AUX write request */ 1087d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 10881a595f28SAnthony Koo /** I2C-over-AUX read request */ 1089d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ = 0x10, 10901a595f28SAnthony Koo /** I2C-over-AUX write status request */ 1091d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 10921a595f28SAnthony Koo /** I2C-over-AUX write request with MOT=1 */ 1093d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 10941a595f28SAnthony Koo /** I2C-over-AUX read request with MOT=1 */ 1095d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 10961a595f28SAnthony Koo /** I2C-over-AUX write status request with MOT=1 */ 1097d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 10981a595f28SAnthony Koo /** Native AUX write request */ 1099d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 11001a595f28SAnthony Koo /** Native AUX read request */ 1101d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1102d9beecfcSAnthony Koo }; 1103d9beecfcSAnthony Koo 11041a595f28SAnthony Koo /** 11051a595f28SAnthony Koo * enum aux_return_code_type - DP AUX process return code listing. 11061a595f28SAnthony Koo */ 1107fd0f1d21SAnthony Koo enum aux_return_code_type { 11081a595f28SAnthony Koo /** AUX process succeeded */ 1109fd0f1d21SAnthony Koo AUX_RET_SUCCESS = 0, 11101a595f28SAnthony Koo /** AUX process failed with unknown reason */ 1111b6402afeSAnthony Koo AUX_RET_ERROR_UNKNOWN, 11121a595f28SAnthony Koo /** AUX process completed with invalid reply */ 1113b6402afeSAnthony Koo AUX_RET_ERROR_INVALID_REPLY, 11141a595f28SAnthony Koo /** AUX process timed out */ 1115fd0f1d21SAnthony Koo AUX_RET_ERROR_TIMEOUT, 11161a595f28SAnthony Koo /** HPD was low during AUX process */ 1117b6402afeSAnthony Koo AUX_RET_ERROR_HPD_DISCON, 11181a595f28SAnthony Koo /** Failed to acquire AUX engine */ 1119b6402afeSAnthony Koo AUX_RET_ERROR_ENGINE_ACQUIRE, 11201a595f28SAnthony Koo /** AUX request not supported */ 1121fd0f1d21SAnthony Koo AUX_RET_ERROR_INVALID_OPERATION, 11221a595f28SAnthony Koo /** AUX process not available */ 1123fd0f1d21SAnthony Koo AUX_RET_ERROR_PROTOCOL_ERROR, 1124fd0f1d21SAnthony Koo }; 1125fd0f1d21SAnthony Koo 11261a595f28SAnthony Koo /** 11271a595f28SAnthony Koo * enum aux_channel_type - DP AUX channel type listing. 11281a595f28SAnthony Koo */ 1129b6402afeSAnthony Koo enum aux_channel_type { 11301a595f28SAnthony Koo /** AUX thru Legacy DP AUX */ 1131b6402afeSAnthony Koo AUX_CHANNEL_LEGACY_DDC, 11321a595f28SAnthony Koo /** AUX thru DPIA DP tunneling */ 1133b6402afeSAnthony Koo AUX_CHANNEL_DPIA 1134b6402afeSAnthony Koo }; 1135b6402afeSAnthony Koo 11361a595f28SAnthony Koo /** 11371a595f28SAnthony Koo * struct aux_transaction_parameters - DP AUX request transaction data 11381a595f28SAnthony Koo */ 1139d9beecfcSAnthony Koo struct aux_transaction_parameters { 11401a595f28SAnthony Koo uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 11411a595f28SAnthony Koo uint8_t action; /**< enum dp_aux_request_action */ 11421a595f28SAnthony Koo uint8_t length; /**< DP AUX request data length */ 11431a595f28SAnthony Koo uint8_t reserved; /**< For future use */ 11441a595f28SAnthony Koo uint32_t address; /**< DP AUX address */ 11451a595f28SAnthony Koo uint8_t data[16]; /**< DP AUX write data */ 1146d9beecfcSAnthony Koo }; 1147d9beecfcSAnthony Koo 11481a595f28SAnthony Koo /** 11491a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 11501a595f28SAnthony Koo */ 1151d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data { 11521a595f28SAnthony Koo uint8_t instance; /**< AUX instance or DPIA instance */ 11531a595f28SAnthony Koo uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 11541a595f28SAnthony Koo uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 11551a595f28SAnthony Koo uint8_t reserved0; /**< For future use */ 11561a595f28SAnthony Koo uint16_t timeout; /**< timeout time in us */ 11571a595f28SAnthony Koo uint16_t reserved1; /**< For future use */ 11581a595f28SAnthony Koo enum aux_channel_type type; /**< enum aux_channel_type */ 11591a595f28SAnthony Koo struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1160d9beecfcSAnthony Koo }; 1161d9beecfcSAnthony Koo 11621a595f28SAnthony Koo /** 11631a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 11641a595f28SAnthony Koo */ 1165d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access { 11661a595f28SAnthony Koo /** 11671a595f28SAnthony Koo * Command header. 11681a595f28SAnthony Koo */ 1169d9beecfcSAnthony Koo struct dmub_cmd_header header; 11701a595f28SAnthony Koo /** 11711a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 11721a595f28SAnthony Koo */ 1173d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data aux_control; 1174d9beecfcSAnthony Koo }; 1175d9beecfcSAnthony Koo 11761a595f28SAnthony Koo /** 11771a595f28SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 11781a595f28SAnthony Koo */ 1179d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable { 11801a595f28SAnthony Koo /** 11811a595f28SAnthony Koo * Command header. 11821a595f28SAnthony Koo */ 1183d9beecfcSAnthony Koo struct dmub_cmd_header header; 11841a595f28SAnthony Koo /** 11851a595f28SAnthony Koo * enable: 0x0 -> disable outbox1 notification (default value) 11861a595f28SAnthony Koo * 0x1 -> enable outbox1 notification 11871a595f28SAnthony Koo */ 1188d9beecfcSAnthony Koo uint32_t enable; 1189d9beecfcSAnthony Koo }; 1190d9beecfcSAnthony Koo 1191d9beecfcSAnthony Koo /* DP AUX Reply command - OutBox Cmd */ 11921a595f28SAnthony Koo /** 11931a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 11941a595f28SAnthony Koo */ 1195d9beecfcSAnthony Koo struct aux_reply_data { 11961a595f28SAnthony Koo /** 11971a595f28SAnthony Koo * Aux cmd 11981a595f28SAnthony Koo */ 1199d9beecfcSAnthony Koo uint8_t command; 12001a595f28SAnthony Koo /** 12011a595f28SAnthony Koo * Aux reply data length (max: 16 bytes) 12021a595f28SAnthony Koo */ 1203d9beecfcSAnthony Koo uint8_t length; 12041a595f28SAnthony Koo /** 12051a595f28SAnthony Koo * Alignment only 12061a595f28SAnthony Koo */ 1207d9beecfcSAnthony Koo uint8_t pad[2]; 12081a595f28SAnthony Koo /** 12091a595f28SAnthony Koo * Aux reply data 12101a595f28SAnthony Koo */ 1211d9beecfcSAnthony Koo uint8_t data[16]; 1212d9beecfcSAnthony Koo }; 1213d9beecfcSAnthony Koo 12141a595f28SAnthony Koo /** 12151a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 12161a595f28SAnthony Koo */ 1217d9beecfcSAnthony Koo struct aux_reply_control_data { 12181a595f28SAnthony Koo /** 12191a595f28SAnthony Koo * Reserved for future use 12201a595f28SAnthony Koo */ 1221d9beecfcSAnthony Koo uint32_t handle; 12221a595f28SAnthony Koo /** 12231a595f28SAnthony Koo * Aux Instance 12241a595f28SAnthony Koo */ 1225b6402afeSAnthony Koo uint8_t instance; 12261a595f28SAnthony Koo /** 12271a595f28SAnthony Koo * Aux transaction result: definition in enum aux_return_code_type 12281a595f28SAnthony Koo */ 1229d9beecfcSAnthony Koo uint8_t result; 12301a595f28SAnthony Koo /** 12311a595f28SAnthony Koo * Alignment only 12321a595f28SAnthony Koo */ 1233d9beecfcSAnthony Koo uint16_t pad; 1234d9beecfcSAnthony Koo }; 1235d9beecfcSAnthony Koo 12361a595f28SAnthony Koo /** 12371a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 12381a595f28SAnthony Koo */ 1239d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply { 12401a595f28SAnthony Koo /** 12411a595f28SAnthony Koo * Command header. 12421a595f28SAnthony Koo */ 1243d9beecfcSAnthony Koo struct dmub_cmd_header header; 12441a595f28SAnthony Koo /** 12451a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 12461a595f28SAnthony Koo */ 1247d9beecfcSAnthony Koo struct aux_reply_control_data control; 12481a595f28SAnthony Koo /** 12491a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 12501a595f28SAnthony Koo */ 1251d9beecfcSAnthony Koo struct aux_reply_data reply_data; 1252d9beecfcSAnthony Koo }; 1253d9beecfcSAnthony Koo 1254fd0f1d21SAnthony Koo /* DP HPD Notify command - OutBox Cmd */ 12551a595f28SAnthony Koo /** 12561a595f28SAnthony Koo * DP HPD Type 12571a595f28SAnthony Koo */ 1258fd0f1d21SAnthony Koo enum dp_hpd_type { 12591a595f28SAnthony Koo /** 12601a595f28SAnthony Koo * Normal DP HPD 12611a595f28SAnthony Koo */ 1262fd0f1d21SAnthony Koo DP_HPD = 0, 12631a595f28SAnthony Koo /** 12641a595f28SAnthony Koo * DP HPD short pulse 12651a595f28SAnthony Koo */ 1266fd0f1d21SAnthony Koo DP_IRQ 1267fd0f1d21SAnthony Koo }; 1268fd0f1d21SAnthony Koo 12691a595f28SAnthony Koo /** 12701a595f28SAnthony Koo * DP HPD Status 12711a595f28SAnthony Koo */ 1272fd0f1d21SAnthony Koo enum dp_hpd_status { 12731a595f28SAnthony Koo /** 12741a595f28SAnthony Koo * DP_HPD status low 12751a595f28SAnthony Koo */ 1276fd0f1d21SAnthony Koo DP_HPD_UNPLUG = 0, 12771a595f28SAnthony Koo /** 12781a595f28SAnthony Koo * DP_HPD status high 12791a595f28SAnthony Koo */ 1280fd0f1d21SAnthony Koo DP_HPD_PLUG 1281fd0f1d21SAnthony Koo }; 1282fd0f1d21SAnthony Koo 12831a595f28SAnthony Koo /** 12841a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 12851a595f28SAnthony Koo */ 1286d9beecfcSAnthony Koo struct dp_hpd_data { 12871a595f28SAnthony Koo /** 12881a595f28SAnthony Koo * DP HPD instance 12891a595f28SAnthony Koo */ 1290b6402afeSAnthony Koo uint8_t instance; 12911a595f28SAnthony Koo /** 12921a595f28SAnthony Koo * HPD type 12931a595f28SAnthony Koo */ 1294d9beecfcSAnthony Koo uint8_t hpd_type; 12951a595f28SAnthony Koo /** 12961a595f28SAnthony Koo * HPD status: only for type: DP_HPD to indicate status 12971a595f28SAnthony Koo */ 1298d9beecfcSAnthony Koo uint8_t hpd_status; 12991a595f28SAnthony Koo /** 13001a595f28SAnthony Koo * Alignment only 13011a595f28SAnthony Koo */ 1302d9beecfcSAnthony Koo uint8_t pad; 1303d9beecfcSAnthony Koo }; 1304d9beecfcSAnthony Koo 13051a595f28SAnthony Koo /** 13061a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 13071a595f28SAnthony Koo */ 1308d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify { 13091a595f28SAnthony Koo /** 13101a595f28SAnthony Koo * Command header. 13111a595f28SAnthony Koo */ 1312d9beecfcSAnthony Koo struct dmub_cmd_header header; 13131a595f28SAnthony Koo /** 13141a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 13151a595f28SAnthony Koo */ 1316d9beecfcSAnthony Koo struct dp_hpd_data hpd_data; 1317d9beecfcSAnthony Koo }; 1318d9beecfcSAnthony Koo 131971af9d46SMeenakshikumar Somasundaram /** 132071af9d46SMeenakshikumar Somasundaram * Definition of a SET_CONFIG reply from DPOA. 132171af9d46SMeenakshikumar Somasundaram */ 132271af9d46SMeenakshikumar Somasundaram enum set_config_status { 132371af9d46SMeenakshikumar Somasundaram SET_CONFIG_PENDING = 0, 132471af9d46SMeenakshikumar Somasundaram SET_CONFIG_ACK_RECEIVED, 132571af9d46SMeenakshikumar Somasundaram SET_CONFIG_RX_TIMEOUT, 132671af9d46SMeenakshikumar Somasundaram SET_CONFIG_UNKNOWN_ERROR, 132771af9d46SMeenakshikumar Somasundaram }; 132871af9d46SMeenakshikumar Somasundaram 132971af9d46SMeenakshikumar Somasundaram /** 133071af9d46SMeenakshikumar Somasundaram * Definition of a set_config reply 133171af9d46SMeenakshikumar Somasundaram */ 133271af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data { 133371af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA Instance */ 133471af9d46SMeenakshikumar Somasundaram uint8_t status; /* Set Config reply */ 133571af9d46SMeenakshikumar Somasundaram uint16_t pad; /* Alignment */ 133671af9d46SMeenakshikumar Somasundaram }; 133771af9d46SMeenakshikumar Somasundaram 133871af9d46SMeenakshikumar Somasundaram /** 133971af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 134071af9d46SMeenakshikumar Somasundaram */ 134171af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply { 134271af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; 134371af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data set_config_reply_control; 134471af9d46SMeenakshikumar Somasundaram }; 134571af9d46SMeenakshikumar Somasundaram 134684034ad4SAnthony Koo /* 134784034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 134884034ad4SAnthony Koo * Do not reuse or modify IDs. 134984034ad4SAnthony Koo */ 135084034ad4SAnthony Koo 13511a595f28SAnthony Koo /** 13521a595f28SAnthony Koo * PSR command sub-types. 13531a595f28SAnthony Koo */ 135484034ad4SAnthony Koo enum dmub_cmd_psr_type { 13551a595f28SAnthony Koo /** 13561a595f28SAnthony Koo * Set PSR version support. 13571a595f28SAnthony Koo */ 135884034ad4SAnthony Koo DMUB_CMD__PSR_SET_VERSION = 0, 13591a595f28SAnthony Koo /** 13601a595f28SAnthony Koo * Copy driver-calculated parameters to PSR state. 13611a595f28SAnthony Koo */ 136284034ad4SAnthony Koo DMUB_CMD__PSR_COPY_SETTINGS = 1, 13631a595f28SAnthony Koo /** 13641a595f28SAnthony Koo * Enable PSR. 13651a595f28SAnthony Koo */ 136684034ad4SAnthony Koo DMUB_CMD__PSR_ENABLE = 2, 13671a595f28SAnthony Koo 13681a595f28SAnthony Koo /** 13691a595f28SAnthony Koo * Disable PSR. 13701a595f28SAnthony Koo */ 137184034ad4SAnthony Koo DMUB_CMD__PSR_DISABLE = 3, 13721a595f28SAnthony Koo 13731a595f28SAnthony Koo /** 13741a595f28SAnthony Koo * Set PSR level. 13751a595f28SAnthony Koo * PSR level is a 16-bit value dicated by driver that 13761a595f28SAnthony Koo * will enable/disable different functionality. 13771a595f28SAnthony Koo */ 137884034ad4SAnthony Koo DMUB_CMD__PSR_SET_LEVEL = 4, 13791a595f28SAnthony Koo 13801a595f28SAnthony Koo /** 13811a595f28SAnthony Koo * Forces PSR enabled until an explicit PSR disable call. 13821a595f28SAnthony Koo */ 1383672251b2SAnthony Koo DMUB_CMD__PSR_FORCE_STATIC = 5, 1384e5dfcd27SRobin Chen /** 1385e5dfcd27SRobin Chen * Set PSR power option 1386e5dfcd27SRobin Chen */ 1387e5dfcd27SRobin Chen DMUB_CMD__SET_PSR_POWER_OPT = 7, 138884034ad4SAnthony Koo }; 138984034ad4SAnthony Koo 13901a595f28SAnthony Koo /** 13911a595f28SAnthony Koo * PSR versions. 13921a595f28SAnthony Koo */ 139384034ad4SAnthony Koo enum psr_version { 13941a595f28SAnthony Koo /** 13951a595f28SAnthony Koo * PSR version 1. 13961a595f28SAnthony Koo */ 139784034ad4SAnthony Koo PSR_VERSION_1 = 0, 13981a595f28SAnthony Koo /** 13991a595f28SAnthony Koo * PSR not supported. 14001a595f28SAnthony Koo */ 140184034ad4SAnthony Koo PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 140284034ad4SAnthony Koo }; 140384034ad4SAnthony Koo 1404592a6318SAnthony Koo /** 1405592a6318SAnthony Koo * enum dmub_cmd_mall_type - MALL commands 1406592a6318SAnthony Koo */ 140752f2e83eSBhawanpreet Lakha enum dmub_cmd_mall_type { 1408592a6318SAnthony Koo /** 1409592a6318SAnthony Koo * Allows display refresh from MALL. 1410592a6318SAnthony Koo */ 141152f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_ALLOW = 0, 1412592a6318SAnthony Koo /** 1413592a6318SAnthony Koo * Disallows display refresh from MALL. 1414592a6318SAnthony Koo */ 141552f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1416592a6318SAnthony Koo /** 1417592a6318SAnthony Koo * Cursor copy for MALL. 1418592a6318SAnthony Koo */ 141952f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1420592a6318SAnthony Koo /** 1421592a6318SAnthony Koo * Controls DF requests. 1422592a6318SAnthony Koo */ 1423ea7154d8SBhawanpreet Lakha DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 142452f2e83eSBhawanpreet Lakha }; 142552f2e83eSBhawanpreet Lakha 1426592a6318SAnthony Koo 14271a595f28SAnthony Koo /** 14281a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 14291a595f28SAnthony Koo */ 14307c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data { 14311a595f28SAnthony Koo /** 14321a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 14331a595f28SAnthony Koo */ 14347b8a6362SAnthony Koo union dmub_psr_debug_flags debug; 14351a595f28SAnthony Koo /** 14361a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 14371a595f28SAnthony Koo */ 14384c1a1335SWyatt Wood uint16_t psr_level; 14391a595f28SAnthony Koo /** 14401a595f28SAnthony Koo * DPP HW instance. 14411a595f28SAnthony Koo */ 14424c1a1335SWyatt Wood uint8_t dpp_inst; 14431a595f28SAnthony Koo /** 14441a595f28SAnthony Koo * MPCC HW instance. 14451a595f28SAnthony Koo * Not used in dmub fw, 144634ba432cSAnthony Koo * dmub fw will get active opp by reading odm registers. 144734ba432cSAnthony Koo */ 14484c1a1335SWyatt Wood uint8_t mpcc_inst; 14491a595f28SAnthony Koo /** 14501a595f28SAnthony Koo * OPP HW instance. 14511a595f28SAnthony Koo * Not used in dmub fw, 14521a595f28SAnthony Koo * dmub fw will get active opp by reading odm registers. 14531a595f28SAnthony Koo */ 14544c1a1335SWyatt Wood uint8_t opp_inst; 14551a595f28SAnthony Koo /** 14561a595f28SAnthony Koo * OTG HW instance. 14571a595f28SAnthony Koo */ 14584c1a1335SWyatt Wood uint8_t otg_inst; 14591a595f28SAnthony Koo /** 14601a595f28SAnthony Koo * DIG FE HW instance. 14611a595f28SAnthony Koo */ 14624c1a1335SWyatt Wood uint8_t digfe_inst; 14631a595f28SAnthony Koo /** 14641a595f28SAnthony Koo * DIG BE HW instance. 14651a595f28SAnthony Koo */ 14664c1a1335SWyatt Wood uint8_t digbe_inst; 14671a595f28SAnthony Koo /** 14681a595f28SAnthony Koo * DP PHY HW instance. 14691a595f28SAnthony Koo */ 14704c1a1335SWyatt Wood uint8_t dpphy_inst; 14711a595f28SAnthony Koo /** 14721a595f28SAnthony Koo * AUX HW instance. 14731a595f28SAnthony Koo */ 14744c1a1335SWyatt Wood uint8_t aux_inst; 14751a595f28SAnthony Koo /** 14761a595f28SAnthony Koo * Determines if SMU optimzations are enabled/disabled. 14771a595f28SAnthony Koo */ 14784c1a1335SWyatt Wood uint8_t smu_optimizations_en; 14791a595f28SAnthony Koo /** 14801a595f28SAnthony Koo * Unused. 14811a595f28SAnthony Koo * TODO: Remove. 14821a595f28SAnthony Koo */ 14834c1a1335SWyatt Wood uint8_t frame_delay; 14841a595f28SAnthony Koo /** 14851a595f28SAnthony Koo * If RFB setup time is greater than the total VBLANK time, 14861a595f28SAnthony Koo * it is not possible for the sink to capture the video frame 14871a595f28SAnthony Koo * in the same frame the SDP is sent. In this case, 14881a595f28SAnthony Koo * the frame capture indication bit should be set and an extra 14891a595f28SAnthony Koo * static frame should be transmitted to the sink. 14901a595f28SAnthony Koo */ 14914c1a1335SWyatt Wood uint8_t frame_cap_ind; 14921a595f28SAnthony Koo /** 14931a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 14941a595f28SAnthony Koo */ 1495175f0971SYongqiang Sun uint8_t pad[2]; 14961a595f28SAnthony Koo /** 14971a595f28SAnthony Koo * Multi-display optimizations are implemented on certain ASICs. 14981a595f28SAnthony Koo */ 1499175f0971SYongqiang Sun uint8_t multi_disp_optimizations_en; 15001a595f28SAnthony Koo /** 15011a595f28SAnthony Koo * The last possible line SDP may be transmitted without violating 15021a595f28SAnthony Koo * the RFB setup time or entering the active video frame. 15031a595f28SAnthony Koo */ 150478ead771SAnthony Koo uint16_t init_sdp_deadline; 15051a595f28SAnthony Koo /** 15061a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 15071a595f28SAnthony Koo */ 150878ead771SAnthony Koo uint16_t pad2; 15091a595f28SAnthony Koo /** 15101a595f28SAnthony Koo * Length of each horizontal line in us. 15111a595f28SAnthony Koo */ 15129b56f6bcSAnthony Koo uint32_t line_time_in_us; 1513ecc11601SAnthony Koo /** 1514ecc11601SAnthony Koo * FEC enable status in driver 1515ecc11601SAnthony Koo */ 1516ecc11601SAnthony Koo uint8_t fec_enable_status; 1517ecc11601SAnthony Koo /** 1518ecc11601SAnthony Koo * FEC re-enable delay when PSR exit. 1519ecc11601SAnthony Koo * unit is 100us, range form 0~255(0xFF). 1520ecc11601SAnthony Koo */ 1521ecc11601SAnthony Koo uint8_t fec_enable_delay_in100us; 1522ecc11601SAnthony Koo /** 1523f56c837aSMikita Lipski * PSR control version. 1524ecc11601SAnthony Koo */ 1525f56c837aSMikita Lipski uint8_t cmd_version; 1526f56c837aSMikita Lipski /** 1527f56c837aSMikita Lipski * Panel Instance. 1528f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1529f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1530f56c837aSMikita Lipski */ 1531f56c837aSMikita Lipski uint8_t panel_inst; 1532360d1b65SIan Chen /** 1533360d1b65SIan Chen * Explicit padding to 4 byte boundary. 1534360d1b65SIan Chen */ 1535360d1b65SIan Chen uint8_t pad3[4]; 15367c008829SNicholas Kazlauskas }; 15377c008829SNicholas Kazlauskas 15381a595f28SAnthony Koo /** 15391a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 15401a595f28SAnthony Koo */ 15417c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings { 15421a595f28SAnthony Koo /** 15431a595f28SAnthony Koo * Command header. 15441a595f28SAnthony Koo */ 15457c008829SNicholas Kazlauskas struct dmub_cmd_header header; 15461a595f28SAnthony Koo /** 15471a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 15481a595f28SAnthony Koo */ 15497c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 15507c008829SNicholas Kazlauskas }; 15517c008829SNicholas Kazlauskas 15521a595f28SAnthony Koo /** 15531a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 15541a595f28SAnthony Koo */ 15557c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data { 15561a595f28SAnthony Koo /** 15571a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 15581a595f28SAnthony Koo */ 15597c008829SNicholas Kazlauskas uint16_t psr_level; 15601a595f28SAnthony Koo /** 1561f56c837aSMikita Lipski * PSR control version. 15621a595f28SAnthony Koo */ 1563f56c837aSMikita Lipski uint8_t cmd_version; 1564f56c837aSMikita Lipski /** 1565f56c837aSMikita Lipski * Panel Instance. 1566f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1567f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1568f56c837aSMikita Lipski */ 1569f56c837aSMikita Lipski uint8_t panel_inst; 15707c008829SNicholas Kazlauskas }; 15717c008829SNicholas Kazlauskas 15721a595f28SAnthony Koo /** 15731a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 15741a595f28SAnthony Koo */ 15757c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level { 15761a595f28SAnthony Koo /** 15771a595f28SAnthony Koo * Command header. 15781a595f28SAnthony Koo */ 15797c008829SNicholas Kazlauskas struct dmub_cmd_header header; 15801a595f28SAnthony Koo /** 15811a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 15821a595f28SAnthony Koo */ 15837c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data psr_set_level_data; 15847c008829SNicholas Kazlauskas }; 15857c008829SNicholas Kazlauskas 1586f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data { 1587f56c837aSMikita Lipski /** 1588f56c837aSMikita Lipski * PSR control version. 1589f56c837aSMikita Lipski */ 1590f56c837aSMikita Lipski uint8_t cmd_version; 1591f56c837aSMikita Lipski /** 1592f56c837aSMikita Lipski * Panel Instance. 1593f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1594f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1595f56c837aSMikita Lipski */ 1596f56c837aSMikita Lipski uint8_t panel_inst; 1597f56c837aSMikita Lipski /** 1598f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 1599f56c837aSMikita Lipski */ 1600f56c837aSMikita Lipski uint8_t pad[2]; 1601f56c837aSMikita Lipski }; 1602f56c837aSMikita Lipski 16031a595f28SAnthony Koo /** 16041a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 16051a595f28SAnthony Koo * PSR enable/disable is controlled using the sub_type. 16061a595f28SAnthony Koo */ 16077c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_enable { 16081a595f28SAnthony Koo /** 16091a595f28SAnthony Koo * Command header. 16101a595f28SAnthony Koo */ 16117c008829SNicholas Kazlauskas struct dmub_cmd_header header; 1612f56c837aSMikita Lipski 1613f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data data; 16147c008829SNicholas Kazlauskas }; 16157c008829SNicholas Kazlauskas 16161a595f28SAnthony Koo /** 16171a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 16181a595f28SAnthony Koo */ 1619d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data { 16201a595f28SAnthony Koo /** 16211a595f28SAnthony Koo * PSR version that FW should implement. 16221a595f28SAnthony Koo */ 16231a595f28SAnthony Koo enum psr_version version; 1624f56c837aSMikita Lipski /** 1625f56c837aSMikita Lipski * PSR control version. 1626f56c837aSMikita Lipski */ 1627f56c837aSMikita Lipski uint8_t cmd_version; 1628f56c837aSMikita Lipski /** 1629f56c837aSMikita Lipski * Panel Instance. 1630f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1631f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1632f56c837aSMikita Lipski */ 1633f56c837aSMikita Lipski uint8_t panel_inst; 1634f56c837aSMikita Lipski /** 1635f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 1636f56c837aSMikita Lipski */ 1637f56c837aSMikita Lipski uint8_t pad[2]; 16387c008829SNicholas Kazlauskas }; 16397c008829SNicholas Kazlauskas 16401a595f28SAnthony Koo /** 16411a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 16421a595f28SAnthony Koo */ 1643d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version { 16441a595f28SAnthony Koo /** 16451a595f28SAnthony Koo * Command header. 16461a595f28SAnthony Koo */ 16477c008829SNicholas Kazlauskas struct dmub_cmd_header header; 16481a595f28SAnthony Koo /** 16491a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 16501a595f28SAnthony Koo */ 1651d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data psr_set_version_data; 16527c008829SNicholas Kazlauskas }; 16537c008829SNicholas Kazlauskas 1654f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data { 1655f56c837aSMikita Lipski /** 1656f56c837aSMikita Lipski * PSR control version. 1657f56c837aSMikita Lipski */ 1658f56c837aSMikita Lipski uint8_t cmd_version; 1659f56c837aSMikita Lipski /** 1660f56c837aSMikita Lipski * Panel Instance. 1661f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1662f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1663f56c837aSMikita Lipski */ 1664f56c837aSMikita Lipski uint8_t panel_inst; 1665f56c837aSMikita Lipski /** 1666f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 1667f56c837aSMikita Lipski */ 1668f56c837aSMikita Lipski uint8_t pad[2]; 1669f56c837aSMikita Lipski }; 1670f56c837aSMikita Lipski 16711a595f28SAnthony Koo /** 16721a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 16731a595f28SAnthony Koo */ 1674672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static { 16751a595f28SAnthony Koo /** 16761a595f28SAnthony Koo * Command header. 16771a595f28SAnthony Koo */ 1678672251b2SAnthony Koo struct dmub_cmd_header header; 1679f56c837aSMikita Lipski /** 1680f56c837aSMikita Lipski * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1681f56c837aSMikita Lipski */ 1682f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data psr_force_static_data; 1683672251b2SAnthony Koo }; 1684672251b2SAnthony Koo 16851a595f28SAnthony Koo /** 1686e5dfcd27SRobin Chen * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 1687e5dfcd27SRobin Chen */ 1688e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data { 1689e5dfcd27SRobin Chen /** 1690e5dfcd27SRobin Chen * PSR control version. 1691e5dfcd27SRobin Chen */ 1692e5dfcd27SRobin Chen uint8_t cmd_version; 1693e5dfcd27SRobin Chen /** 1694e5dfcd27SRobin Chen * Panel Instance. 1695e5dfcd27SRobin Chen * Panel isntance to identify which psr_state to use 1696e5dfcd27SRobin Chen * Currently the support is only for 0 or 1 1697e5dfcd27SRobin Chen */ 1698e5dfcd27SRobin Chen uint8_t panel_inst; 1699e5dfcd27SRobin Chen /** 1700e5dfcd27SRobin Chen * Explicit padding to 4 byte boundary. 1701e5dfcd27SRobin Chen */ 1702e5dfcd27SRobin Chen uint8_t pad[2]; 1703e5dfcd27SRobin Chen /** 1704e5dfcd27SRobin Chen * PSR power option 1705e5dfcd27SRobin Chen */ 1706e5dfcd27SRobin Chen uint32_t power_opt; 1707e5dfcd27SRobin Chen }; 1708e5dfcd27SRobin Chen 1709e5dfcd27SRobin Chen /** 1710e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1711e5dfcd27SRobin Chen */ 1712e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt { 1713e5dfcd27SRobin Chen /** 1714e5dfcd27SRobin Chen * Command header. 1715e5dfcd27SRobin Chen */ 1716e5dfcd27SRobin Chen struct dmub_cmd_header header; 1717e5dfcd27SRobin Chen /** 1718e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 1719e5dfcd27SRobin Chen */ 1720e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 1721e5dfcd27SRobin Chen }; 1722e5dfcd27SRobin Chen 1723e5dfcd27SRobin Chen /** 17241a595f28SAnthony Koo * Set of HW components that can be locked. 17250b51e7e8SAnthony Koo * 17260b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 17270b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 17281a595f28SAnthony Koo */ 1729788408b7SAnthony Koo union dmub_hw_lock_flags { 17301a595f28SAnthony Koo /** 17311a595f28SAnthony Koo * Set of HW components that can be locked. 17321a595f28SAnthony Koo */ 1733788408b7SAnthony Koo struct { 17341a595f28SAnthony Koo /** 17351a595f28SAnthony Koo * Lock/unlock OTG master update lock. 17361a595f28SAnthony Koo */ 1737788408b7SAnthony Koo uint8_t lock_pipe : 1; 17381a595f28SAnthony Koo /** 17391a595f28SAnthony Koo * Lock/unlock cursor. 17401a595f28SAnthony Koo */ 1741788408b7SAnthony Koo uint8_t lock_cursor : 1; 17421a595f28SAnthony Koo /** 17431a595f28SAnthony Koo * Lock/unlock global update lock. 17441a595f28SAnthony Koo */ 1745788408b7SAnthony Koo uint8_t lock_dig : 1; 17461a595f28SAnthony Koo /** 17471a595f28SAnthony Koo * Triple buffer lock requires additional hw programming to usual OTG master lock. 17481a595f28SAnthony Koo */ 1749788408b7SAnthony Koo uint8_t triple_buffer_lock : 1; 1750788408b7SAnthony Koo } bits; 1751788408b7SAnthony Koo 17521a595f28SAnthony Koo /** 17531a595f28SAnthony Koo * Union for HW Lock flags. 17541a595f28SAnthony Koo */ 1755788408b7SAnthony Koo uint8_t u8All; 1756788408b7SAnthony Koo }; 1757788408b7SAnthony Koo 17581a595f28SAnthony Koo /** 17591a595f28SAnthony Koo * Instances of HW to be locked. 17600b51e7e8SAnthony Koo * 17610b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 17620b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 17631a595f28SAnthony Koo */ 1764788408b7SAnthony Koo struct dmub_hw_lock_inst_flags { 17651a595f28SAnthony Koo /** 17661a595f28SAnthony Koo * OTG HW instance for OTG master update lock. 17671a595f28SAnthony Koo */ 1768788408b7SAnthony Koo uint8_t otg_inst; 17691a595f28SAnthony Koo /** 17701a595f28SAnthony Koo * OPP instance for cursor lock. 17711a595f28SAnthony Koo */ 1772788408b7SAnthony Koo uint8_t opp_inst; 17731a595f28SAnthony Koo /** 17741a595f28SAnthony Koo * OTG HW instance for global update lock. 17751a595f28SAnthony Koo * TODO: Remove, and re-use otg_inst. 17761a595f28SAnthony Koo */ 1777788408b7SAnthony Koo uint8_t dig_inst; 17781a595f28SAnthony Koo /** 17791a595f28SAnthony Koo * Explicit pad to 4 byte boundary. 17801a595f28SAnthony Koo */ 1781788408b7SAnthony Koo uint8_t pad; 1782788408b7SAnthony Koo }; 1783788408b7SAnthony Koo 17841a595f28SAnthony Koo /** 17851a595f28SAnthony Koo * Clients that can acquire the HW Lock Manager. 17860b51e7e8SAnthony Koo * 17870b51e7e8SAnthony Koo * Note: If updating with more clients, fields in 17880b51e7e8SAnthony Koo * dmub_inbox0_cmd_lock_hw must be updated to match. 17891a595f28SAnthony Koo */ 1790788408b7SAnthony Koo enum hw_lock_client { 17911a595f28SAnthony Koo /** 17921a595f28SAnthony Koo * Driver is the client of HW Lock Manager. 17931a595f28SAnthony Koo */ 1794788408b7SAnthony Koo HW_LOCK_CLIENT_DRIVER = 0, 17951a595f28SAnthony Koo /** 17961a595f28SAnthony Koo * Invalid client. 17971a595f28SAnthony Koo */ 1798788408b7SAnthony Koo HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 1799788408b7SAnthony Koo }; 1800788408b7SAnthony Koo 18011a595f28SAnthony Koo /** 18021a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 18031a595f28SAnthony Koo */ 1804788408b7SAnthony Koo struct dmub_cmd_lock_hw_data { 18051a595f28SAnthony Koo /** 18061a595f28SAnthony Koo * Specifies the client accessing HW Lock Manager. 18071a595f28SAnthony Koo */ 1808788408b7SAnthony Koo enum hw_lock_client client; 18091a595f28SAnthony Koo /** 18101a595f28SAnthony Koo * HW instances to be locked. 18111a595f28SAnthony Koo */ 1812788408b7SAnthony Koo struct dmub_hw_lock_inst_flags inst_flags; 18131a595f28SAnthony Koo /** 18141a595f28SAnthony Koo * Which components to be locked. 18151a595f28SAnthony Koo */ 1816788408b7SAnthony Koo union dmub_hw_lock_flags hw_locks; 18171a595f28SAnthony Koo /** 18181a595f28SAnthony Koo * Specifies lock/unlock. 18191a595f28SAnthony Koo */ 1820788408b7SAnthony Koo uint8_t lock; 18211a595f28SAnthony Koo /** 18221a595f28SAnthony Koo * HW can be unlocked separately from releasing the HW Lock Mgr. 18231a595f28SAnthony Koo * This flag is set if the client wishes to release the object. 18241a595f28SAnthony Koo */ 1825788408b7SAnthony Koo uint8_t should_release; 18261a595f28SAnthony Koo /** 18271a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 18281a595f28SAnthony Koo */ 1829788408b7SAnthony Koo uint8_t pad; 1830788408b7SAnthony Koo }; 1831788408b7SAnthony Koo 18321a595f28SAnthony Koo /** 18331a595f28SAnthony Koo * Definition of a DMUB_CMD__HW_LOCK command. 18341a595f28SAnthony Koo * Command is used by driver and FW. 18351a595f28SAnthony Koo */ 1836788408b7SAnthony Koo struct dmub_rb_cmd_lock_hw { 18371a595f28SAnthony Koo /** 18381a595f28SAnthony Koo * Command header. 18391a595f28SAnthony Koo */ 1840788408b7SAnthony Koo struct dmub_cmd_header header; 18411a595f28SAnthony Koo /** 18421a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 18431a595f28SAnthony Koo */ 1844788408b7SAnthony Koo struct dmub_cmd_lock_hw_data lock_hw_data; 1845788408b7SAnthony Koo }; 1846788408b7SAnthony Koo 18471a595f28SAnthony Koo /** 18481a595f28SAnthony Koo * ABM command sub-types. 18491a595f28SAnthony Koo */ 185084034ad4SAnthony Koo enum dmub_cmd_abm_type { 18511a595f28SAnthony Koo /** 18521a595f28SAnthony Koo * Initialize parameters for ABM algorithm. 18531a595f28SAnthony Koo * Data is passed through an indirect buffer. 18541a595f28SAnthony Koo */ 185584034ad4SAnthony Koo DMUB_CMD__ABM_INIT_CONFIG = 0, 18561a595f28SAnthony Koo /** 18571a595f28SAnthony Koo * Set OTG and panel HW instance. 18581a595f28SAnthony Koo */ 185984034ad4SAnthony Koo DMUB_CMD__ABM_SET_PIPE = 1, 18601a595f28SAnthony Koo /** 18611a595f28SAnthony Koo * Set user requested backklight level. 18621a595f28SAnthony Koo */ 186384034ad4SAnthony Koo DMUB_CMD__ABM_SET_BACKLIGHT = 2, 18641a595f28SAnthony Koo /** 18651a595f28SAnthony Koo * Set ABM operating/aggression level. 18661a595f28SAnthony Koo */ 186784034ad4SAnthony Koo DMUB_CMD__ABM_SET_LEVEL = 3, 18681a595f28SAnthony Koo /** 18691a595f28SAnthony Koo * Set ambient light level. 18701a595f28SAnthony Koo */ 187184034ad4SAnthony Koo DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 18721a595f28SAnthony Koo /** 18731a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 18741a595f28SAnthony Koo */ 187584034ad4SAnthony Koo DMUB_CMD__ABM_SET_PWM_FRAC = 5, 1876b629a824SEric Yang 1877b629a824SEric Yang /** 1878b629a824SEric Yang * unregister vertical interrupt after steady state is reached 1879b629a824SEric Yang */ 1880b629a824SEric Yang DMUB_CMD__ABM_PAUSE = 6, 188184034ad4SAnthony Koo }; 188284034ad4SAnthony Koo 18831a595f28SAnthony Koo /** 18841a595f28SAnthony Koo * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 18851a595f28SAnthony Koo * Requirements: 18861a595f28SAnthony Koo * - Padded explicitly to 32-bit boundary. 18871a595f28SAnthony Koo * - Must ensure this structure matches the one on driver-side, 18881a595f28SAnthony Koo * otherwise it won't be aligned. 188984034ad4SAnthony Koo */ 189084034ad4SAnthony Koo struct abm_config_table { 18911a595f28SAnthony Koo /** 18921a595f28SAnthony Koo * Gamma curve thresholds, used for crgb conversion. 18931a595f28SAnthony Koo */ 189484034ad4SAnthony Koo uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 18951a595f28SAnthony Koo /** 18961a595f28SAnthony Koo * Gamma curve offsets, used for crgb conversion. 18971a595f28SAnthony Koo */ 1898b6402afeSAnthony Koo uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 18991a595f28SAnthony Koo /** 19001a595f28SAnthony Koo * Gamma curve slopes, used for crgb conversion. 19011a595f28SAnthony Koo */ 1902b6402afeSAnthony Koo uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 19031a595f28SAnthony Koo /** 19041a595f28SAnthony Koo * Custom backlight curve thresholds. 19051a595f28SAnthony Koo */ 1906b6402afeSAnthony Koo uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 19071a595f28SAnthony Koo /** 19081a595f28SAnthony Koo * Custom backlight curve offsets. 19091a595f28SAnthony Koo */ 1910b6402afeSAnthony Koo uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 19111a595f28SAnthony Koo /** 19121a595f28SAnthony Koo * Ambient light thresholds. 19131a595f28SAnthony Koo */ 1914b6402afeSAnthony Koo uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 19151a595f28SAnthony Koo /** 19161a595f28SAnthony Koo * Minimum programmable backlight. 19171a595f28SAnthony Koo */ 1918b6402afeSAnthony Koo uint16_t min_abm_backlight; // 122B 19191a595f28SAnthony Koo /** 19201a595f28SAnthony Koo * Minimum reduction values. 19211a595f28SAnthony Koo */ 1922b6402afeSAnthony Koo uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 19231a595f28SAnthony Koo /** 19241a595f28SAnthony Koo * Maximum reduction values. 19251a595f28SAnthony Koo */ 1926b6402afeSAnthony Koo uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 19271a595f28SAnthony Koo /** 19281a595f28SAnthony Koo * Bright positive gain. 19291a595f28SAnthony Koo */ 1930b6402afeSAnthony Koo uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 19311a595f28SAnthony Koo /** 19321a595f28SAnthony Koo * Dark negative gain. 19331a595f28SAnthony Koo */ 1934b6402afeSAnthony Koo uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 19351a595f28SAnthony Koo /** 19361a595f28SAnthony Koo * Hybrid factor. 19371a595f28SAnthony Koo */ 1938b6402afeSAnthony Koo uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 19391a595f28SAnthony Koo /** 19401a595f28SAnthony Koo * Contrast factor. 19411a595f28SAnthony Koo */ 1942b6402afeSAnthony Koo uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 19431a595f28SAnthony Koo /** 19441a595f28SAnthony Koo * Deviation gain. 19451a595f28SAnthony Koo */ 1946b6402afeSAnthony Koo uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 19471a595f28SAnthony Koo /** 19481a595f28SAnthony Koo * Minimum knee. 19491a595f28SAnthony Koo */ 1950b6402afeSAnthony Koo uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 19511a595f28SAnthony Koo /** 19521a595f28SAnthony Koo * Maximum knee. 19531a595f28SAnthony Koo */ 1954b6402afeSAnthony Koo uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 19551a595f28SAnthony Koo /** 19561a595f28SAnthony Koo * Unused. 19571a595f28SAnthony Koo */ 1958b6402afeSAnthony Koo uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 19591a595f28SAnthony Koo /** 19601a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 19611a595f28SAnthony Koo */ 1962b6402afeSAnthony Koo uint8_t pad3[3]; // 229B 19631a595f28SAnthony Koo /** 19641a595f28SAnthony Koo * Backlight ramp reduction. 19651a595f28SAnthony Koo */ 1966b6402afeSAnthony Koo uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 19671a595f28SAnthony Koo /** 19681a595f28SAnthony Koo * Backlight ramp start. 19691a595f28SAnthony Koo */ 1970b6402afeSAnthony Koo uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 197184034ad4SAnthony Koo }; 197284034ad4SAnthony Koo 19731a595f28SAnthony Koo /** 19741a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 19751a595f28SAnthony Koo */ 1976e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data { 19771a595f28SAnthony Koo /** 19781a595f28SAnthony Koo * OTG HW instance. 19791a595f28SAnthony Koo */ 19807b8a6362SAnthony Koo uint8_t otg_inst; 19811a595f28SAnthony Koo 19821a595f28SAnthony Koo /** 19831a595f28SAnthony Koo * Panel Control HW instance. 19841a595f28SAnthony Koo */ 19857b8a6362SAnthony Koo uint8_t panel_inst; 19861a595f28SAnthony Koo 19871a595f28SAnthony Koo /** 19881a595f28SAnthony Koo * Controls how ABM will interpret a set pipe or set level command. 19891a595f28SAnthony Koo */ 19907b8a6362SAnthony Koo uint8_t set_pipe_option; 19911a595f28SAnthony Koo 19921a595f28SAnthony Koo /** 19931a595f28SAnthony Koo * Unused. 19941a595f28SAnthony Koo * TODO: Remove. 19951a595f28SAnthony Koo */ 19961a595f28SAnthony Koo uint8_t ramping_boundary; 1997e6ea8c34SWyatt Wood }; 1998e6ea8c34SWyatt Wood 19991a595f28SAnthony Koo /** 20001a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 20011a595f28SAnthony Koo */ 2002e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe { 20031a595f28SAnthony Koo /** 20041a595f28SAnthony Koo * Command header. 20051a595f28SAnthony Koo */ 2006e6ea8c34SWyatt Wood struct dmub_cmd_header header; 20071a595f28SAnthony Koo 20081a595f28SAnthony Koo /** 20091a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 20101a595f28SAnthony Koo */ 2011e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2012e6ea8c34SWyatt Wood }; 2013e6ea8c34SWyatt Wood 20141a595f28SAnthony Koo /** 20151a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 20161a595f28SAnthony Koo */ 2017e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data { 20181a595f28SAnthony Koo /** 20191a595f28SAnthony Koo * Number of frames to ramp to backlight user level. 20201a595f28SAnthony Koo */ 2021e6ea8c34SWyatt Wood uint32_t frame_ramp; 20221a595f28SAnthony Koo 20231a595f28SAnthony Koo /** 20241a595f28SAnthony Koo * Requested backlight level from user. 20251a595f28SAnthony Koo */ 2026474ac4a8SYongqiang Sun uint32_t backlight_user_level; 2027e922057bSJake Wang 2028e922057bSJake Wang /** 202963de4f04SJake Wang * ABM control version. 2030e922057bSJake Wang */ 2031e922057bSJake Wang uint8_t version; 2032e922057bSJake Wang 2033e922057bSJake Wang /** 2034e922057bSJake Wang * Panel Control HW instance mask. 2035e922057bSJake Wang * Bit 0 is Panel Control HW instance 0. 2036e922057bSJake Wang * Bit 1 is Panel Control HW instance 1. 2037e922057bSJake Wang */ 2038e922057bSJake Wang uint8_t panel_mask; 2039e922057bSJake Wang 2040e922057bSJake Wang /** 2041e922057bSJake Wang * Explicit padding to 4 byte boundary. 2042e922057bSJake Wang */ 2043e922057bSJake Wang uint8_t pad[2]; 2044e6ea8c34SWyatt Wood }; 2045e6ea8c34SWyatt Wood 20461a595f28SAnthony Koo /** 20471a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 20481a595f28SAnthony Koo */ 2049e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight { 20501a595f28SAnthony Koo /** 20511a595f28SAnthony Koo * Command header. 20521a595f28SAnthony Koo */ 2053e6ea8c34SWyatt Wood struct dmub_cmd_header header; 20541a595f28SAnthony Koo 20551a595f28SAnthony Koo /** 20561a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 20571a595f28SAnthony Koo */ 2058e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2059e6ea8c34SWyatt Wood }; 2060e6ea8c34SWyatt Wood 20611a595f28SAnthony Koo /** 20621a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 20631a595f28SAnthony Koo */ 2064e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data { 20651a595f28SAnthony Koo /** 20661a595f28SAnthony Koo * Set current ABM operating/aggression level. 20671a595f28SAnthony Koo */ 2068e6ea8c34SWyatt Wood uint32_t level; 206963de4f04SJake Wang 207063de4f04SJake Wang /** 207163de4f04SJake Wang * ABM control version. 207263de4f04SJake Wang */ 207363de4f04SJake Wang uint8_t version; 207463de4f04SJake Wang 207563de4f04SJake Wang /** 207663de4f04SJake Wang * Panel Control HW instance mask. 207763de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 207863de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 207963de4f04SJake Wang */ 208063de4f04SJake Wang uint8_t panel_mask; 208163de4f04SJake Wang 208263de4f04SJake Wang /** 208363de4f04SJake Wang * Explicit padding to 4 byte boundary. 208463de4f04SJake Wang */ 208563de4f04SJake Wang uint8_t pad[2]; 2086e6ea8c34SWyatt Wood }; 2087e6ea8c34SWyatt Wood 20881a595f28SAnthony Koo /** 20891a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 20901a595f28SAnthony Koo */ 2091e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level { 20921a595f28SAnthony Koo /** 20931a595f28SAnthony Koo * Command header. 20941a595f28SAnthony Koo */ 2095e6ea8c34SWyatt Wood struct dmub_cmd_header header; 20961a595f28SAnthony Koo 20971a595f28SAnthony Koo /** 20981a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 20991a595f28SAnthony Koo */ 2100e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data abm_set_level_data; 2101e6ea8c34SWyatt Wood }; 2102e6ea8c34SWyatt Wood 21031a595f28SAnthony Koo /** 21041a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 21051a595f28SAnthony Koo */ 2106e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data { 21071a595f28SAnthony Koo /** 21081a595f28SAnthony Koo * Ambient light sensor reading from OS. 21091a595f28SAnthony Koo */ 2110e6ea8c34SWyatt Wood uint32_t ambient_lux; 211163de4f04SJake Wang 211263de4f04SJake Wang /** 211363de4f04SJake Wang * ABM control version. 211463de4f04SJake Wang */ 211563de4f04SJake Wang uint8_t version; 211663de4f04SJake Wang 211763de4f04SJake Wang /** 211863de4f04SJake Wang * Panel Control HW instance mask. 211963de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 212063de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 212163de4f04SJake Wang */ 212263de4f04SJake Wang uint8_t panel_mask; 212363de4f04SJake Wang 212463de4f04SJake Wang /** 212563de4f04SJake Wang * Explicit padding to 4 byte boundary. 212663de4f04SJake Wang */ 212763de4f04SJake Wang uint8_t pad[2]; 2128e6ea8c34SWyatt Wood }; 2129e6ea8c34SWyatt Wood 21301a595f28SAnthony Koo /** 21311a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 21321a595f28SAnthony Koo */ 2133e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level { 21341a595f28SAnthony Koo /** 21351a595f28SAnthony Koo * Command header. 21361a595f28SAnthony Koo */ 2137e6ea8c34SWyatt Wood struct dmub_cmd_header header; 21381a595f28SAnthony Koo 21391a595f28SAnthony Koo /** 21401a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 21411a595f28SAnthony Koo */ 2142e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2143e6ea8c34SWyatt Wood }; 2144e6ea8c34SWyatt Wood 21451a595f28SAnthony Koo /** 21461a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 21471a595f28SAnthony Koo */ 2148e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data { 21491a595f28SAnthony Koo /** 21501a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 21511a595f28SAnthony Koo * TODO: Convert to uint8_t. 21521a595f28SAnthony Koo */ 2153e6ea8c34SWyatt Wood uint32_t fractional_pwm; 215463de4f04SJake Wang 215563de4f04SJake Wang /** 215663de4f04SJake Wang * ABM control version. 215763de4f04SJake Wang */ 215863de4f04SJake Wang uint8_t version; 215963de4f04SJake Wang 216063de4f04SJake Wang /** 216163de4f04SJake Wang * Panel Control HW instance mask. 216263de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 216363de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 216463de4f04SJake Wang */ 216563de4f04SJake Wang uint8_t panel_mask; 216663de4f04SJake Wang 216763de4f04SJake Wang /** 216863de4f04SJake Wang * Explicit padding to 4 byte boundary. 216963de4f04SJake Wang */ 217063de4f04SJake Wang uint8_t pad[2]; 2171e6ea8c34SWyatt Wood }; 2172e6ea8c34SWyatt Wood 21731a595f28SAnthony Koo /** 21741a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 21751a595f28SAnthony Koo */ 2176e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac { 21771a595f28SAnthony Koo /** 21781a595f28SAnthony Koo * Command header. 21791a595f28SAnthony Koo */ 2180e6ea8c34SWyatt Wood struct dmub_cmd_header header; 21811a595f28SAnthony Koo 21821a595f28SAnthony Koo /** 21831a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 21841a595f28SAnthony Koo */ 2185e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2186e6ea8c34SWyatt Wood }; 2187e6ea8c34SWyatt Wood 21881a595f28SAnthony Koo /** 21891a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 21901a595f28SAnthony Koo */ 219116012806SWyatt Wood struct dmub_cmd_abm_init_config_data { 21921a595f28SAnthony Koo /** 21931a595f28SAnthony Koo * Location of indirect buffer used to pass init data to ABM. 21941a595f28SAnthony Koo */ 219516012806SWyatt Wood union dmub_addr src; 21961a595f28SAnthony Koo 21971a595f28SAnthony Koo /** 21981a595f28SAnthony Koo * Indirect buffer length. 21991a595f28SAnthony Koo */ 220016012806SWyatt Wood uint16_t bytes; 220163de4f04SJake Wang 220263de4f04SJake Wang 220363de4f04SJake Wang /** 220463de4f04SJake Wang * ABM control version. 220563de4f04SJake Wang */ 220663de4f04SJake Wang uint8_t version; 220763de4f04SJake Wang 220863de4f04SJake Wang /** 220963de4f04SJake Wang * Panel Control HW instance mask. 221063de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 221163de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 221263de4f04SJake Wang */ 221363de4f04SJake Wang uint8_t panel_mask; 221463de4f04SJake Wang 221563de4f04SJake Wang /** 221663de4f04SJake Wang * Explicit padding to 4 byte boundary. 221763de4f04SJake Wang */ 221863de4f04SJake Wang uint8_t pad[2]; 221916012806SWyatt Wood }; 222016012806SWyatt Wood 22211a595f28SAnthony Koo /** 22221a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 22231a595f28SAnthony Koo */ 222416012806SWyatt Wood struct dmub_rb_cmd_abm_init_config { 22251a595f28SAnthony Koo /** 22261a595f28SAnthony Koo * Command header. 22271a595f28SAnthony Koo */ 222816012806SWyatt Wood struct dmub_cmd_header header; 22291a595f28SAnthony Koo 22301a595f28SAnthony Koo /** 22311a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 22321a595f28SAnthony Koo */ 223316012806SWyatt Wood struct dmub_cmd_abm_init_config_data abm_init_config_data; 223416012806SWyatt Wood }; 223516012806SWyatt Wood 22361a595f28SAnthony Koo /** 2237b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2238b629a824SEric Yang */ 2239b629a824SEric Yang 2240b629a824SEric Yang struct dmub_cmd_abm_pause_data { 2241b629a824SEric Yang 2242b629a824SEric Yang /** 2243b629a824SEric Yang * Panel Control HW instance mask. 2244b629a824SEric Yang * Bit 0 is Panel Control HW instance 0. 2245b629a824SEric Yang * Bit 1 is Panel Control HW instance 1. 2246b629a824SEric Yang */ 2247b629a824SEric Yang uint8_t panel_mask; 2248b629a824SEric Yang 2249b629a824SEric Yang /** 2250b629a824SEric Yang * OTG hw instance 2251b629a824SEric Yang */ 2252b629a824SEric Yang uint8_t otg_inst; 2253b629a824SEric Yang 2254b629a824SEric Yang /** 2255b629a824SEric Yang * Enable or disable ABM pause 2256b629a824SEric Yang */ 2257b629a824SEric Yang uint8_t enable; 2258b629a824SEric Yang 2259b629a824SEric Yang /** 2260b629a824SEric Yang * Explicit padding to 4 byte boundary. 2261b629a824SEric Yang */ 2262b629a824SEric Yang uint8_t pad[1]; 2263b629a824SEric Yang }; 2264b629a824SEric Yang 2265b629a824SEric Yang /** 2266b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 2267b629a824SEric Yang */ 2268b629a824SEric Yang struct dmub_rb_cmd_abm_pause { 2269b629a824SEric Yang /** 2270b629a824SEric Yang * Command header. 2271b629a824SEric Yang */ 2272b629a824SEric Yang struct dmub_cmd_header header; 2273b629a824SEric Yang 2274b629a824SEric Yang /** 2275b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2276b629a824SEric Yang */ 2277b629a824SEric Yang struct dmub_cmd_abm_pause_data abm_pause_data; 2278b629a824SEric Yang }; 2279b629a824SEric Yang 2280b629a824SEric Yang /** 22811a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 22821a595f28SAnthony Koo */ 228334ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data { 22841a595f28SAnthony Koo /** 22851a595f28SAnthony Koo * DMUB feature capabilities. 22861a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features. 22871a595f28SAnthony Koo */ 228834ba432cSAnthony Koo struct dmub_feature_caps feature_caps; 228934ba432cSAnthony Koo }; 229034ba432cSAnthony Koo 22911a595f28SAnthony Koo /** 22921a595f28SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 22931a595f28SAnthony Koo */ 229434ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps { 22951a595f28SAnthony Koo /** 22961a595f28SAnthony Koo * Command header. 22971a595f28SAnthony Koo */ 229834ba432cSAnthony Koo struct dmub_cmd_header header; 22991a595f28SAnthony Koo /** 23001a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 23011a595f28SAnthony Koo */ 230234ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 230334ba432cSAnthony Koo }; 230434ba432cSAnthony Koo 2305592a6318SAnthony Koo struct dmub_optc_state { 2306592a6318SAnthony Koo uint32_t v_total_max; 2307592a6318SAnthony Koo uint32_t v_total_min; 2308592a6318SAnthony Koo uint32_t v_total_mid; 2309592a6318SAnthony Koo uint32_t v_total_mid_frame_num; 2310592a6318SAnthony Koo uint32_t tg_inst; 2311592a6318SAnthony Koo uint32_t enable_manual_trigger; 2312592a6318SAnthony Koo uint32_t clear_force_vsync; 2313592a6318SAnthony Koo }; 2314592a6318SAnthony Koo 2315592a6318SAnthony Koo struct dmub_rb_cmd_drr_update { 2316592a6318SAnthony Koo struct dmub_cmd_header header; 2317592a6318SAnthony Koo struct dmub_optc_state dmub_optc_state_req; 2318592a6318SAnthony Koo }; 2319592a6318SAnthony Koo 2320b04cb192SNicholas Kazlauskas /** 2321b04cb192SNicholas Kazlauskas * enum dmub_cmd_panel_cntl_type - Panel control command. 2322b04cb192SNicholas Kazlauskas */ 2323b04cb192SNicholas Kazlauskas enum dmub_cmd_panel_cntl_type { 2324b04cb192SNicholas Kazlauskas /** 2325b04cb192SNicholas Kazlauskas * Initializes embedded panel hardware blocks. 2326b04cb192SNicholas Kazlauskas */ 2327b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2328b04cb192SNicholas Kazlauskas /** 2329b04cb192SNicholas Kazlauskas * Queries backlight info for the embedded panel. 2330b04cb192SNicholas Kazlauskas */ 2331b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2332b04cb192SNicholas Kazlauskas }; 2333b04cb192SNicholas Kazlauskas 2334b04cb192SNicholas Kazlauskas /** 2335b04cb192SNicholas Kazlauskas * struct dmub_cmd_panel_cntl_data - Panel control data. 2336b04cb192SNicholas Kazlauskas */ 2337b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data { 2338b04cb192SNicholas Kazlauskas uint32_t inst; /**< panel instance */ 2339b04cb192SNicholas Kazlauskas uint32_t current_backlight; /* in/out */ 2340b04cb192SNicholas Kazlauskas uint32_t bl_pwm_cntl; /* in/out */ 2341b04cb192SNicholas Kazlauskas uint32_t bl_pwm_period_cntl; /* in/out */ 2342b04cb192SNicholas Kazlauskas uint32_t bl_pwm_ref_div1; /* in/out */ 2343b04cb192SNicholas Kazlauskas uint8_t is_backlight_on : 1; /* in/out */ 2344b04cb192SNicholas Kazlauskas uint8_t is_powered_on : 1; /* in/out */ 2345b04cb192SNicholas Kazlauskas }; 2346b04cb192SNicholas Kazlauskas 2347b04cb192SNicholas Kazlauskas /** 2348b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_panel_cntl - Panel control command. 2349b04cb192SNicholas Kazlauskas */ 2350b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl { 2351b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 2352b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data data; /**< payload */ 2353b04cb192SNicholas Kazlauskas }; 2354b04cb192SNicholas Kazlauskas 23551a595f28SAnthony Koo /** 23561a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 23571a595f28SAnthony Koo */ 23581a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data { 23591a595f28SAnthony Koo uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 23601a595f28SAnthony Koo uint8_t reserved_0[3]; /**< For future use */ 23611a595f28SAnthony Koo uint8_t panel_inst; /**< LVTMA control instance */ 23621a595f28SAnthony Koo uint8_t reserved_1[3]; /**< For future use */ 23631a595f28SAnthony Koo }; 23641a595f28SAnthony Koo 23651a595f28SAnthony Koo /** 23661a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 23671a595f28SAnthony Koo */ 23681a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control { 23691a595f28SAnthony Koo /** 23701a595f28SAnthony Koo * Command header. 23711a595f28SAnthony Koo */ 23721a595f28SAnthony Koo struct dmub_cmd_header header; 23731a595f28SAnthony Koo /** 23741a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 23751a595f28SAnthony Koo */ 23761a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data data; 23771a595f28SAnthony Koo }; 23781a595f28SAnthony Koo 2379592a6318SAnthony Koo /** 2380021eaef8SAnthony Koo * Maximum number of bytes a chunk sent to DMUB for parsing 2381021eaef8SAnthony Koo */ 2382021eaef8SAnthony Koo #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2383021eaef8SAnthony Koo 2384021eaef8SAnthony Koo /** 2385021eaef8SAnthony Koo * Represent a chunk of CEA blocks sent to DMUB for parsing 2386021eaef8SAnthony Koo */ 2387021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea { 2388021eaef8SAnthony Koo uint16_t offset; /**< offset into the CEA block */ 2389021eaef8SAnthony Koo uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2390021eaef8SAnthony Koo uint16_t total_length; /**< total length of the CEA block */ 2391021eaef8SAnthony Koo uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2392021eaef8SAnthony Koo uint8_t pad[3]; /**< padding and for future expansion */ 2393021eaef8SAnthony Koo }; 2394021eaef8SAnthony Koo 2395021eaef8SAnthony Koo /** 2396021eaef8SAnthony Koo * Result of VSDB parsing from CEA block 2397021eaef8SAnthony Koo */ 2398021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb { 2399021eaef8SAnthony Koo uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2400021eaef8SAnthony Koo uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2401021eaef8SAnthony Koo uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2402021eaef8SAnthony Koo uint16_t min_frame_rate; /**< Maximum frame rate */ 2403021eaef8SAnthony Koo uint16_t max_frame_rate; /**< Minimum frame rate */ 2404021eaef8SAnthony Koo }; 2405021eaef8SAnthony Koo 2406021eaef8SAnthony Koo /** 2407021eaef8SAnthony Koo * Result of sending a CEA chunk 2408021eaef8SAnthony Koo */ 2409021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack { 2410021eaef8SAnthony Koo uint16_t offset; /**< offset of the chunk into the CEA block */ 2411021eaef8SAnthony Koo uint8_t success; /**< 1 if this sending of chunk succeeded */ 2412021eaef8SAnthony Koo uint8_t pad; /**< padding and for future expansion */ 2413021eaef8SAnthony Koo }; 2414021eaef8SAnthony Koo 2415021eaef8SAnthony Koo /** 2416021eaef8SAnthony Koo * Specify whether the result is an ACK/NACK or the parsing has finished 2417021eaef8SAnthony Koo */ 2418021eaef8SAnthony Koo enum dmub_cmd_edid_cea_reply_type { 2419021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2420021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2421021eaef8SAnthony Koo }; 2422021eaef8SAnthony Koo 2423021eaef8SAnthony Koo /** 2424021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 2425021eaef8SAnthony Koo */ 2426021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea { 2427021eaef8SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 2428021eaef8SAnthony Koo union dmub_cmd_edid_cea_data { 2429021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2430021eaef8SAnthony Koo struct dmub_cmd_edid_cea_output { /**< output with results */ 2431021eaef8SAnthony Koo uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2432021eaef8SAnthony Koo union { 2433021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2434021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack ack; 2435021eaef8SAnthony Koo }; 2436021eaef8SAnthony Koo } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2437021eaef8SAnthony Koo } data; /**< Command data */ 2438021eaef8SAnthony Koo 2439021eaef8SAnthony Koo }; 2440021eaef8SAnthony Koo 2441021eaef8SAnthony Koo /** 2442592a6318SAnthony Koo * union dmub_rb_cmd - DMUB inbox command. 2443592a6318SAnthony Koo */ 24447c008829SNicholas Kazlauskas union dmub_rb_cmd { 2445dc6e2448SWyatt Wood struct dmub_rb_cmd_lock_hw lock_hw; 2446592a6318SAnthony Koo /** 2447592a6318SAnthony Koo * Elements shared with all commands. 2448592a6318SAnthony Koo */ 24497c008829SNicholas Kazlauskas struct dmub_rb_cmd_common cmd_common; 2450592a6318SAnthony Koo /** 2451592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 2452592a6318SAnthony Koo */ 2453592a6318SAnthony Koo struct dmub_rb_cmd_read_modify_write read_modify_write; 2454592a6318SAnthony Koo /** 2455592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 2456592a6318SAnthony Koo */ 2457592a6318SAnthony Koo struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 2458592a6318SAnthony Koo /** 2459592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 2460592a6318SAnthony Koo */ 2461592a6318SAnthony Koo struct dmub_rb_cmd_burst_write burst_write; 2462592a6318SAnthony Koo /** 2463592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_REG_WAIT command. 2464592a6318SAnthony Koo */ 2465592a6318SAnthony Koo struct dmub_rb_cmd_reg_wait reg_wait; 2466592a6318SAnthony Koo /** 2467592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 2468592a6318SAnthony Koo */ 24697c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 2470592a6318SAnthony Koo /** 2471592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 2472592a6318SAnthony Koo */ 24737c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 2474592a6318SAnthony Koo /** 2475592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 2476592a6318SAnthony Koo */ 24777c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 2478592a6318SAnthony Koo /** 2479592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 2480592a6318SAnthony Koo */ 24817c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init dpphy_init; 2482592a6318SAnthony Koo /** 2483592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 2484592a6318SAnthony Koo */ 24857c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 24861a595f28SAnthony Koo /** 24871a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 24881a595f28SAnthony Koo */ 2489d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version psr_set_version; 24901a595f28SAnthony Koo /** 24911a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 24921a595f28SAnthony Koo */ 24937c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 24941a595f28SAnthony Koo /** 24951a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 24961a595f28SAnthony Koo */ 2497d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_enable psr_enable; 24981a595f28SAnthony Koo /** 24991a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 25001a595f28SAnthony Koo */ 25017c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level psr_set_level; 25021a595f28SAnthony Koo /** 25031a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 25041a595f28SAnthony Koo */ 2505672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static psr_force_static; 2506592a6318SAnthony Koo /** 2507e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2508e5dfcd27SRobin Chen */ 2509e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 2510e5dfcd27SRobin Chen /** 2511592a6318SAnthony Koo * Definition of a DMUB_CMD__PLAT_54186_WA command. 2512592a6318SAnthony Koo */ 2513bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 2514592a6318SAnthony Koo /** 2515592a6318SAnthony Koo * Definition of a DMUB_CMD__MALL command. 2516592a6318SAnthony Koo */ 251752f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall mall; 2518b04cb192SNicholas Kazlauskas /** 2519b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 2520b04cb192SNicholas Kazlauskas */ 2521b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 2522b04cb192SNicholas Kazlauskas 2523b04cb192SNicholas Kazlauskas /** 2524b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 2525b04cb192SNicholas Kazlauskas */ 2526b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 2527b04cb192SNicholas Kazlauskas 2528b04cb192SNicholas Kazlauskas /** 2529b04cb192SNicholas Kazlauskas * Definition of DMUB_CMD__PANEL_CNTL commands. 2530b04cb192SNicholas Kazlauskas */ 2531b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl panel_cntl; 25321a595f28SAnthony Koo /** 25331a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 25341a595f28SAnthony Koo */ 2535e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 25361a595f28SAnthony Koo 25371a595f28SAnthony Koo /** 25381a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 25391a595f28SAnthony Koo */ 2540e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 25411a595f28SAnthony Koo 25421a595f28SAnthony Koo /** 25431a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 25441a595f28SAnthony Koo */ 2545e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level abm_set_level; 25461a595f28SAnthony Koo 25471a595f28SAnthony Koo /** 25481a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 25491a595f28SAnthony Koo */ 2550e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 25511a595f28SAnthony Koo 25521a595f28SAnthony Koo /** 25531a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 25541a595f28SAnthony Koo */ 2555e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 25561a595f28SAnthony Koo 25571a595f28SAnthony Koo /** 25581a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 25591a595f28SAnthony Koo */ 256016012806SWyatt Wood struct dmub_rb_cmd_abm_init_config abm_init_config; 25611a595f28SAnthony Koo 25621a595f28SAnthony Koo /** 2563b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 2564b629a824SEric Yang */ 2565b629a824SEric Yang struct dmub_rb_cmd_abm_pause abm_pause; 2566b629a824SEric Yang 2567b629a824SEric Yang /** 25681a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 25691a595f28SAnthony Koo */ 2570d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access dp_aux_access; 25711a595f28SAnthony Koo 25721a595f28SAnthony Koo /** 2573592a6318SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2574592a6318SAnthony Koo */ 2575592a6318SAnthony Koo struct dmub_rb_cmd_outbox1_enable outbox1_enable; 2576592a6318SAnthony Koo 2577592a6318SAnthony Koo /** 2578592a6318SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 25791a595f28SAnthony Koo */ 258034ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps query_feature_caps; 2581592a6318SAnthony Koo struct dmub_rb_cmd_drr_update drr_update; 25821a595f28SAnthony Koo /** 25831a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 25841a595f28SAnthony Koo */ 25851a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control lvtma_control; 2586021eaef8SAnthony Koo /** 258776724b76SJimmy Kizito * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 258876724b76SJimmy Kizito */ 258976724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 259076724b76SJimmy Kizito /** 259171af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 259271af9d46SMeenakshikumar Somasundaram */ 259371af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access set_config_access; 259471af9d46SMeenakshikumar Somasundaram /** 2595021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 2596021eaef8SAnthony Koo */ 2597021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea edid_cea; 25987c008829SNicholas Kazlauskas }; 25997c008829SNicholas Kazlauskas 2600592a6318SAnthony Koo /** 2601592a6318SAnthony Koo * union dmub_rb_out_cmd - Outbox command 2602592a6318SAnthony Koo */ 2603d9beecfcSAnthony Koo union dmub_rb_out_cmd { 2604592a6318SAnthony Koo /** 2605592a6318SAnthony Koo * Parameters common to every command. 2606592a6318SAnthony Koo */ 2607d9beecfcSAnthony Koo struct dmub_rb_cmd_common cmd_common; 2608592a6318SAnthony Koo /** 2609592a6318SAnthony Koo * AUX reply command. 2610592a6318SAnthony Koo */ 2611d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 2612592a6318SAnthony Koo /** 2613592a6318SAnthony Koo * HPD notify command. 2614592a6318SAnthony Koo */ 2615d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 261671af9d46SMeenakshikumar Somasundaram /** 261771af9d46SMeenakshikumar Somasundaram * SET_CONFIG reply command. 261871af9d46SMeenakshikumar Somasundaram */ 261971af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 2620d9beecfcSAnthony Koo }; 26217c008829SNicholas Kazlauskas #pragma pack(pop) 26227c008829SNicholas Kazlauskas 262384034ad4SAnthony Koo 262484034ad4SAnthony Koo //============================================================================== 262584034ad4SAnthony Koo //</DMUB_CMD>=================================================================== 262684034ad4SAnthony Koo //============================================================================== 262784034ad4SAnthony Koo //< DMUB_RB>==================================================================== 262884034ad4SAnthony Koo //============================================================================== 262984034ad4SAnthony Koo 263084034ad4SAnthony Koo #if defined(__cplusplus) 263184034ad4SAnthony Koo extern "C" { 263284034ad4SAnthony Koo #endif 263384034ad4SAnthony Koo 2634592a6318SAnthony Koo /** 2635592a6318SAnthony Koo * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 2636592a6318SAnthony Koo */ 263784034ad4SAnthony Koo struct dmub_rb_init_params { 2638592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 2639592a6318SAnthony Koo void *base_address; /**< CPU base address for ring's data */ 2640592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 2641592a6318SAnthony Koo uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 2642592a6318SAnthony Koo uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 264384034ad4SAnthony Koo }; 264484034ad4SAnthony Koo 2645592a6318SAnthony Koo /** 2646592a6318SAnthony Koo * struct dmub_rb - Inbox or outbox DMUB ringbuffer 2647592a6318SAnthony Koo */ 264884034ad4SAnthony Koo struct dmub_rb { 2649592a6318SAnthony Koo void *base_address; /**< CPU address for the ring's data */ 2650592a6318SAnthony Koo uint32_t rptr; /**< Read pointer for consumer in bytes */ 2651592a6318SAnthony Koo uint32_t wrpt; /**< Write pointer for producer in bytes */ 2652592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 265384034ad4SAnthony Koo 2654592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 2655592a6318SAnthony Koo void *dmub; /**< Pointer to the DMUB interface */ 265684034ad4SAnthony Koo }; 265784034ad4SAnthony Koo 2658592a6318SAnthony Koo /** 2659592a6318SAnthony Koo * @brief Checks if the ringbuffer is empty. 2660592a6318SAnthony Koo * 2661592a6318SAnthony Koo * @param rb DMUB Ringbuffer 2662592a6318SAnthony Koo * @return true if empty 2663592a6318SAnthony Koo * @return false otherwise 2664592a6318SAnthony Koo */ 266584034ad4SAnthony Koo static inline bool dmub_rb_empty(struct dmub_rb *rb) 266684034ad4SAnthony Koo { 266784034ad4SAnthony Koo return (rb->wrpt == rb->rptr); 266884034ad4SAnthony Koo } 266984034ad4SAnthony Koo 2670592a6318SAnthony Koo /** 2671592a6318SAnthony Koo * @brief Checks if the ringbuffer is full 2672592a6318SAnthony Koo * 2673592a6318SAnthony Koo * @param rb DMUB Ringbuffer 2674592a6318SAnthony Koo * @return true if full 2675592a6318SAnthony Koo * @return false otherwise 2676592a6318SAnthony Koo */ 267784034ad4SAnthony Koo static inline bool dmub_rb_full(struct dmub_rb *rb) 267884034ad4SAnthony Koo { 267984034ad4SAnthony Koo uint32_t data_count; 268084034ad4SAnthony Koo 268184034ad4SAnthony Koo if (rb->wrpt >= rb->rptr) 268284034ad4SAnthony Koo data_count = rb->wrpt - rb->rptr; 268384034ad4SAnthony Koo else 268484034ad4SAnthony Koo data_count = rb->capacity - (rb->rptr - rb->wrpt); 268584034ad4SAnthony Koo 268684034ad4SAnthony Koo return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 268784034ad4SAnthony Koo } 268884034ad4SAnthony Koo 2689592a6318SAnthony Koo /** 2690592a6318SAnthony Koo * @brief Pushes a command into the ringbuffer 2691592a6318SAnthony Koo * 2692592a6318SAnthony Koo * @param rb DMUB ringbuffer 2693592a6318SAnthony Koo * @param cmd The command to push 2694592a6318SAnthony Koo * @return true if the ringbuffer was not full 2695592a6318SAnthony Koo * @return false otherwise 2696592a6318SAnthony Koo */ 269784034ad4SAnthony Koo static inline bool dmub_rb_push_front(struct dmub_rb *rb, 269884034ad4SAnthony Koo const union dmub_rb_cmd *cmd) 269984034ad4SAnthony Koo { 27003a9d5b0bSAnthony Koo uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 27013a9d5b0bSAnthony Koo const uint64_t *src = (const uint64_t *)cmd; 27023a9d5b0bSAnthony Koo uint8_t i; 270384034ad4SAnthony Koo 270484034ad4SAnthony Koo if (dmub_rb_full(rb)) 270584034ad4SAnthony Koo return false; 270684034ad4SAnthony Koo 270784034ad4SAnthony Koo // copying data 27083a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 27093a9d5b0bSAnthony Koo *dst++ = *src++; 271084034ad4SAnthony Koo 271184034ad4SAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 271284034ad4SAnthony Koo 271384034ad4SAnthony Koo if (rb->wrpt >= rb->capacity) 271484034ad4SAnthony Koo rb->wrpt %= rb->capacity; 271584034ad4SAnthony Koo 271684034ad4SAnthony Koo return true; 271784034ad4SAnthony Koo } 271884034ad4SAnthony Koo 2719592a6318SAnthony Koo /** 2720592a6318SAnthony Koo * @brief Pushes a command into the DMUB outbox ringbuffer 2721592a6318SAnthony Koo * 2722592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 2723592a6318SAnthony Koo * @param cmd Outbox command 2724592a6318SAnthony Koo * @return true if not full 2725592a6318SAnthony Koo * @return false otherwise 2726592a6318SAnthony Koo */ 2727d9beecfcSAnthony Koo static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 2728d9beecfcSAnthony Koo const union dmub_rb_out_cmd *cmd) 2729d9beecfcSAnthony Koo { 2730d9beecfcSAnthony Koo uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 2731d459b79bSAnthony Koo const uint8_t *src = (const uint8_t *)cmd; 2732d9beecfcSAnthony Koo 2733d9beecfcSAnthony Koo if (dmub_rb_full(rb)) 2734d9beecfcSAnthony Koo return false; 2735d9beecfcSAnthony Koo 2736d9beecfcSAnthony Koo dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 2737d9beecfcSAnthony Koo 2738d9beecfcSAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 2739d9beecfcSAnthony Koo 2740d9beecfcSAnthony Koo if (rb->wrpt >= rb->capacity) 2741d9beecfcSAnthony Koo rb->wrpt %= rb->capacity; 2742d9beecfcSAnthony Koo 2743d9beecfcSAnthony Koo return true; 2744d9beecfcSAnthony Koo } 2745d9beecfcSAnthony Koo 2746592a6318SAnthony Koo /** 2747592a6318SAnthony Koo * @brief Returns the next unprocessed command in the ringbuffer. 2748592a6318SAnthony Koo * 2749592a6318SAnthony Koo * @param rb DMUB ringbuffer 2750592a6318SAnthony Koo * @param cmd The command to return 2751592a6318SAnthony Koo * @return true if not empty 2752592a6318SAnthony Koo * @return false otherwise 2753592a6318SAnthony Koo */ 275484034ad4SAnthony Koo static inline bool dmub_rb_front(struct dmub_rb *rb, 275534ba432cSAnthony Koo union dmub_rb_cmd **cmd) 275684034ad4SAnthony Koo { 275734ba432cSAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 275884034ad4SAnthony Koo 275984034ad4SAnthony Koo if (dmub_rb_empty(rb)) 276084034ad4SAnthony Koo return false; 276184034ad4SAnthony Koo 276234ba432cSAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 276384034ad4SAnthony Koo 276484034ad4SAnthony Koo return true; 276584034ad4SAnthony Koo } 276684034ad4SAnthony Koo 2767592a6318SAnthony Koo /** 27680b51e7e8SAnthony Koo * @brief Determines the next ringbuffer offset. 27690b51e7e8SAnthony Koo * 27700b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 27710b51e7e8SAnthony Koo * @param num_cmds Number of commands 27720b51e7e8SAnthony Koo * @param next_rptr The next offset in the ringbuffer 27730b51e7e8SAnthony Koo */ 27740b51e7e8SAnthony Koo static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 27750b51e7e8SAnthony Koo uint32_t num_cmds, 27760b51e7e8SAnthony Koo uint32_t *next_rptr) 27770b51e7e8SAnthony Koo { 27780b51e7e8SAnthony Koo *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 27790b51e7e8SAnthony Koo 27800b51e7e8SAnthony Koo if (*next_rptr >= rb->capacity) 27810b51e7e8SAnthony Koo *next_rptr %= rb->capacity; 27820b51e7e8SAnthony Koo } 27830b51e7e8SAnthony Koo 27840b51e7e8SAnthony Koo /** 27850b51e7e8SAnthony Koo * @brief Returns a pointer to a command in the inbox. 27860b51e7e8SAnthony Koo * 27870b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 27880b51e7e8SAnthony Koo * @param cmd The inbox command to return 27890b51e7e8SAnthony Koo * @param rptr The ringbuffer offset 27900b51e7e8SAnthony Koo * @return true if not empty 27910b51e7e8SAnthony Koo * @return false otherwise 27920b51e7e8SAnthony Koo */ 27930b51e7e8SAnthony Koo static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 27940b51e7e8SAnthony Koo union dmub_rb_cmd **cmd, 27950b51e7e8SAnthony Koo uint32_t rptr) 27960b51e7e8SAnthony Koo { 27970b51e7e8SAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 27980b51e7e8SAnthony Koo 27990b51e7e8SAnthony Koo if (dmub_rb_empty(rb)) 28000b51e7e8SAnthony Koo return false; 28010b51e7e8SAnthony Koo 28020b51e7e8SAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 28030b51e7e8SAnthony Koo 28040b51e7e8SAnthony Koo return true; 28050b51e7e8SAnthony Koo } 28060b51e7e8SAnthony Koo 28070b51e7e8SAnthony Koo /** 2808592a6318SAnthony Koo * @brief Returns the next unprocessed command in the outbox. 2809592a6318SAnthony Koo * 2810592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 2811592a6318SAnthony Koo * @param cmd The outbox command to return 2812592a6318SAnthony Koo * @return true if not empty 2813592a6318SAnthony Koo * @return false otherwise 2814592a6318SAnthony Koo */ 2815d9beecfcSAnthony Koo static inline bool dmub_rb_out_front(struct dmub_rb *rb, 2816d9beecfcSAnthony Koo union dmub_rb_out_cmd *cmd) 2817d9beecfcSAnthony Koo { 28183a9d5b0bSAnthony Koo const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 28193a9d5b0bSAnthony Koo uint64_t *dst = (uint64_t *)cmd; 28203a9d5b0bSAnthony Koo uint8_t i; 2821d9beecfcSAnthony Koo 2822d9beecfcSAnthony Koo if (dmub_rb_empty(rb)) 2823d9beecfcSAnthony Koo return false; 2824d9beecfcSAnthony Koo 2825d9beecfcSAnthony Koo // copying data 28263a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 28273a9d5b0bSAnthony Koo *dst++ = *src++; 2828d9beecfcSAnthony Koo 2829d9beecfcSAnthony Koo return true; 2830d9beecfcSAnthony Koo } 2831d9beecfcSAnthony Koo 2832592a6318SAnthony Koo /** 2833592a6318SAnthony Koo * @brief Removes the front entry in the ringbuffer. 2834592a6318SAnthony Koo * 2835592a6318SAnthony Koo * @param rb DMUB ringbuffer 2836592a6318SAnthony Koo * @return true if the command was removed 2837592a6318SAnthony Koo * @return false if there were no commands 2838592a6318SAnthony Koo */ 283984034ad4SAnthony Koo static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 284084034ad4SAnthony Koo { 284184034ad4SAnthony Koo if (dmub_rb_empty(rb)) 284284034ad4SAnthony Koo return false; 284384034ad4SAnthony Koo 284484034ad4SAnthony Koo rb->rptr += DMUB_RB_CMD_SIZE; 284584034ad4SAnthony Koo 284684034ad4SAnthony Koo if (rb->rptr >= rb->capacity) 284784034ad4SAnthony Koo rb->rptr %= rb->capacity; 284884034ad4SAnthony Koo 284984034ad4SAnthony Koo return true; 285084034ad4SAnthony Koo } 285184034ad4SAnthony Koo 2852592a6318SAnthony Koo /** 2853592a6318SAnthony Koo * @brief Flushes commands in the ringbuffer to framebuffer memory. 2854592a6318SAnthony Koo * 2855592a6318SAnthony Koo * Avoids a race condition where DMCUB accesses memory while 2856592a6318SAnthony Koo * there are still writes in flight to framebuffer. 2857592a6318SAnthony Koo * 2858592a6318SAnthony Koo * @param rb DMUB ringbuffer 2859592a6318SAnthony Koo */ 286084034ad4SAnthony Koo static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 286184034ad4SAnthony Koo { 286284034ad4SAnthony Koo uint32_t rptr = rb->rptr; 286384034ad4SAnthony Koo uint32_t wptr = rb->wrpt; 286484034ad4SAnthony Koo 286584034ad4SAnthony Koo while (rptr != wptr) { 28663a9d5b0bSAnthony Koo uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 28673a9d5b0bSAnthony Koo //uint64_t volatile *p = (uint64_t volatile *)data; 28683a9d5b0bSAnthony Koo uint64_t temp; 28693a9d5b0bSAnthony Koo uint8_t i; 287084034ad4SAnthony Koo 28713a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 28723a9d5b0bSAnthony Koo temp = *data++; 287384034ad4SAnthony Koo 287484034ad4SAnthony Koo rptr += DMUB_RB_CMD_SIZE; 287584034ad4SAnthony Koo if (rptr >= rb->capacity) 287684034ad4SAnthony Koo rptr %= rb->capacity; 287784034ad4SAnthony Koo } 287884034ad4SAnthony Koo } 287984034ad4SAnthony Koo 2880592a6318SAnthony Koo /** 2881592a6318SAnthony Koo * @brief Initializes a DMCUB ringbuffer 2882592a6318SAnthony Koo * 2883592a6318SAnthony Koo * @param rb DMUB ringbuffer 2884592a6318SAnthony Koo * @param init_params initial configuration for the ringbuffer 2885592a6318SAnthony Koo */ 288684034ad4SAnthony Koo static inline void dmub_rb_init(struct dmub_rb *rb, 288784034ad4SAnthony Koo struct dmub_rb_init_params *init_params) 288884034ad4SAnthony Koo { 288984034ad4SAnthony Koo rb->base_address = init_params->base_address; 289084034ad4SAnthony Koo rb->capacity = init_params->capacity; 289184034ad4SAnthony Koo rb->rptr = init_params->read_ptr; 289284034ad4SAnthony Koo rb->wrpt = init_params->write_ptr; 289384034ad4SAnthony Koo } 289484034ad4SAnthony Koo 2895592a6318SAnthony Koo /** 2896592a6318SAnthony Koo * @brief Copies output data from in/out commands into the given command. 2897592a6318SAnthony Koo * 2898592a6318SAnthony Koo * @param rb DMUB ringbuffer 2899592a6318SAnthony Koo * @param cmd Command to copy data into 2900592a6318SAnthony Koo */ 290134ba432cSAnthony Koo static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 290234ba432cSAnthony Koo union dmub_rb_cmd *cmd) 290334ba432cSAnthony Koo { 290434ba432cSAnthony Koo // Copy rb entry back into command 290534ba432cSAnthony Koo uint8_t *rd_ptr = (rb->rptr == 0) ? 290634ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 290734ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 290834ba432cSAnthony Koo 290934ba432cSAnthony Koo dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 291034ba432cSAnthony Koo } 291134ba432cSAnthony Koo 291284034ad4SAnthony Koo #if defined(__cplusplus) 291384034ad4SAnthony Koo } 291484034ad4SAnthony Koo #endif 291584034ad4SAnthony Koo 291684034ad4SAnthony Koo //============================================================================== 291784034ad4SAnthony Koo //</DMUB_RB>==================================================================== 291884034ad4SAnthony Koo //============================================================================== 291984034ad4SAnthony Koo 29207c008829SNicholas Kazlauskas #endif /* _DMUB_CMD_H_ */ 2921