17c008829SNicholas Kazlauskas /* 27c008829SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 37c008829SNicholas Kazlauskas * 47c008829SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 57c008829SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 67c008829SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 77c008829SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87c008829SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 97c008829SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 107c008829SNicholas Kazlauskas * 117c008829SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 127c008829SNicholas Kazlauskas * all copies or substantial portions of the Software. 137c008829SNicholas Kazlauskas * 147c008829SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157c008829SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167c008829SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177c008829SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187c008829SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197c008829SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207c008829SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 217c008829SNicholas Kazlauskas * 227c008829SNicholas Kazlauskas * Authors: AMD 237c008829SNicholas Kazlauskas * 247c008829SNicholas Kazlauskas */ 257c008829SNicholas Kazlauskas 265624c345SAnthony Koo #ifndef DMUB_CMD_H 275624c345SAnthony Koo #define DMUB_CMD_H 287c008829SNicholas Kazlauskas 298b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 308b19a4e3SAnthony Koo #include "dmub_fw_types.h" 318b19a4e3SAnthony Koo #include "include_legacy/atomfirmware.h" 328b19a4e3SAnthony Koo 338b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) 348b19a4e3SAnthony Koo #include <string.h> 358b19a4e3SAnthony Koo #endif 368b19a4e3SAnthony Koo #else 378b19a4e3SAnthony Koo 3884034ad4SAnthony Koo #include <asm/byteorder.h> 3984034ad4SAnthony Koo #include <linux/types.h> 4084034ad4SAnthony Koo #include <linux/string.h> 4184034ad4SAnthony Koo #include <linux/delay.h> 4284034ad4SAnthony Koo 437c008829SNicholas Kazlauskas #include "atomfirmware.h" 4422aa5614SYongqiang Sun 458b19a4e3SAnthony Koo #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 468b19a4e3SAnthony Koo 4784034ad4SAnthony Koo //<DMUB_TYPES>================================================================== 4884034ad4SAnthony Koo /* Basic type definitions. */ 4984034ad4SAnthony Koo 508b19a4e3SAnthony Koo #define __forceinline inline 518b19a4e3SAnthony Koo 521a595f28SAnthony Koo /** 531a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled gradually 541a595f28SAnthony Koo * by slowly reversing all backlight programming and pixel compensation. 551a595f28SAnthony Koo */ 5684034ad4SAnthony Koo #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 571a595f28SAnthony Koo 581a595f28SAnthony Koo /** 591a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 601a595f28SAnthony Koo * and undo all backlight programming and pixel compensation. 611a595f28SAnthony Koo */ 6284034ad4SAnthony Koo #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 631a595f28SAnthony Koo 641a595f28SAnthony Koo /** 651a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 661a595f28SAnthony Koo * and keep the current backlight programming and pixel compensation. 671a595f28SAnthony Koo */ 68d9beecfcSAnthony Koo #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 691a595f28SAnthony Koo 701a595f28SAnthony Koo /** 711a595f28SAnthony Koo * Flag from driver to set the current ABM pipe index or ABM operating level. 721a595f28SAnthony Koo */ 7384034ad4SAnthony Koo #define SET_ABM_PIPE_NORMAL 1 7484034ad4SAnthony Koo 751a595f28SAnthony Koo /** 761a595f28SAnthony Koo * Number of ambient light levels in ABM algorithm. 771a595f28SAnthony Koo */ 781a595f28SAnthony Koo #define NUM_AMBI_LEVEL 5 791a595f28SAnthony Koo 801a595f28SAnthony Koo /** 811a595f28SAnthony Koo * Number of operating/aggression levels in ABM algorithm. 821a595f28SAnthony Koo */ 831a595f28SAnthony Koo #define NUM_AGGR_LEVEL 4 841a595f28SAnthony Koo 851a595f28SAnthony Koo /** 861a595f28SAnthony Koo * Number of segments in the gamma curve. 871a595f28SAnthony Koo */ 881a595f28SAnthony Koo #define NUM_POWER_FN_SEGS 8 891a595f28SAnthony Koo 901a595f28SAnthony Koo /** 911a595f28SAnthony Koo * Number of segments in the backlight curve. 921a595f28SAnthony Koo */ 931a595f28SAnthony Koo #define NUM_BL_CURVE_SEGS 16 941a595f28SAnthony Koo 9585f4bc0cSAlvin Lee /* Maximum number of SubVP streams */ 9685f4bc0cSAlvin Lee #define DMUB_MAX_SUBVP_STREAMS 2 9785f4bc0cSAlvin Lee 98d3981ee7SAnthony Koo /* Define max FPO streams as 4 for now. Current implementation today 99d3981ee7SAnthony Koo * only supports 1, but could be more in the future. Reduce array 100d3981ee7SAnthony Koo * size to ensure the command size remains less than 64 bytes if 101d3981ee7SAnthony Koo * adding new fields. 102d3981ee7SAnthony Koo */ 103d3981ee7SAnthony Koo #define DMUB_MAX_FPO_STREAMS 4 104d3981ee7SAnthony Koo 10584034ad4SAnthony Koo /* Maximum number of streams on any ASIC. */ 10684034ad4SAnthony Koo #define DMUB_MAX_STREAMS 6 10784034ad4SAnthony Koo 10884034ad4SAnthony Koo /* Maximum number of planes on any ASIC. */ 10984034ad4SAnthony Koo #define DMUB_MAX_PLANES 6 11084034ad4SAnthony Koo 11170732504SYongqiang Sun /* Trace buffer offset for entry */ 11270732504SYongqiang Sun #define TRACE_BUFFER_ENTRY_OFFSET 16 11370732504SYongqiang Sun 114592a6318SAnthony Koo /** 11583eb5385SDavid Zhang * Maximum number of dirty rects supported by FW. 11683eb5385SDavid Zhang */ 11783eb5385SDavid Zhang #define DMUB_MAX_DIRTY_RECTS 3 11883eb5385SDavid Zhang 11983eb5385SDavid Zhang /** 120f56c837aSMikita Lipski * 121f56c837aSMikita Lipski * PSR control version legacy 122f56c837aSMikita Lipski */ 123f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 124f56c837aSMikita Lipski /** 125f56c837aSMikita Lipski * PSR control version with multi edp support 126f56c837aSMikita Lipski */ 127f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 128f56c837aSMikita Lipski 129f56c837aSMikita Lipski 130f56c837aSMikita Lipski /** 13163de4f04SJake Wang * ABM control version legacy 132e922057bSJake Wang */ 13363de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 134e922057bSJake Wang 135e922057bSJake Wang /** 13663de4f04SJake Wang * ABM control version with multi edp support 137e922057bSJake Wang */ 13863de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 139e922057bSJake Wang 140e922057bSJake Wang /** 141592a6318SAnthony Koo * Physical framebuffer address location, 64-bit. 142592a6318SAnthony Koo */ 14384034ad4SAnthony Koo #ifndef PHYSICAL_ADDRESS_LOC 14484034ad4SAnthony Koo #define PHYSICAL_ADDRESS_LOC union large_integer 14584034ad4SAnthony Koo #endif 14684034ad4SAnthony Koo 147da915efaSReza Amini #define ABM_NUM_OF_ACE_SEGMENTS 5 148da915efaSReza Amini 149da915efaSReza Amini union abm_flags { 150da915efaSReza Amini struct { 151da915efaSReza Amini /** 152*519e3637SReza Amini * @abm_enabled: Indicates if ABM is enabled. 153da915efaSReza Amini */ 154da915efaSReza Amini unsigned int abm_enabled : 1; 155da915efaSReza Amini 156da915efaSReza Amini /** 157*519e3637SReza Amini * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 158da915efaSReza Amini */ 159da915efaSReza Amini unsigned int disable_abm_requested : 1; 160da915efaSReza Amini 161da915efaSReza Amini /** 162*519e3637SReza Amini * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled 163*519e3637SReza Amini * immediately. 164da915efaSReza Amini */ 165da915efaSReza Amini unsigned int disable_abm_immediately : 1; 166da915efaSReza Amini 167da915efaSReza Amini /** 168*519e3637SReza Amini * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 169da915efaSReza Amini * to be disabled immediately and keep gain. 170da915efaSReza Amini */ 171da915efaSReza Amini unsigned int disable_abm_immediate_keep_gain : 1; 172da915efaSReza Amini 173da915efaSReza Amini /** 174*519e3637SReza Amini * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 175da915efaSReza Amini */ 176da915efaSReza Amini unsigned int fractional_pwm : 1; 177da915efaSReza Amini 178da915efaSReza Amini /** 179*519e3637SReza Amini * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 180da915efaSReza Amini * of user backlight level. 181da915efaSReza Amini */ 182da915efaSReza Amini unsigned int abm_gradual_bl_change : 1; 183da915efaSReza Amini } bitfields; 184da915efaSReza Amini 185*519e3637SReza Amini unsigned int u32All; 186da915efaSReza Amini }; 187da915efaSReza Amini 188da915efaSReza Amini struct abm_save_restore { 189da915efaSReza Amini /** 190da915efaSReza Amini * @flags: Misc. ABM flags. 191da915efaSReza Amini */ 192da915efaSReza Amini union abm_flags flags; 193da915efaSReza Amini 194da915efaSReza Amini /** 195da915efaSReza Amini * @pause: true: pause ABM and get state 196*519e3637SReza Amini * false: unpause ABM after setting state 197da915efaSReza Amini */ 198da915efaSReza Amini uint32_t pause; 199da915efaSReza Amini 200da915efaSReza Amini /** 201da915efaSReza Amini * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 202da915efaSReza Amini */ 203da915efaSReza Amini uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 204da915efaSReza Amini 205da915efaSReza Amini /** 206da915efaSReza Amini * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 207da915efaSReza Amini */ 208da915efaSReza Amini uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 209da915efaSReza Amini 210da915efaSReza Amini /** 211da915efaSReza Amini * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 212da915efaSReza Amini */ 213da915efaSReza Amini uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 214da915efaSReza Amini 215da915efaSReza Amini 216da915efaSReza Amini /** 217da915efaSReza Amini * @knee_threshold: Current x-position of ACE knee (u0.16). 218da915efaSReza Amini */ 219da915efaSReza Amini uint32_t knee_threshold; 220da915efaSReza Amini /** 221da915efaSReza Amini * @current_gain: Current backlight reduction (u16.16). 222da915efaSReza Amini */ 223da915efaSReza Amini uint32_t current_gain; 224da915efaSReza Amini /** 225da915efaSReza Amini * @curr_bl_level: Current actual backlight level converging to target backlight level. 226da915efaSReza Amini */ 227da915efaSReza Amini uint16_t curr_bl_level; 228da915efaSReza Amini 229da915efaSReza Amini /** 230da915efaSReza Amini * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 231da915efaSReza Amini */ 232da915efaSReza Amini uint16_t curr_user_bl_level; 233da915efaSReza Amini 234da915efaSReza Amini }; 235da915efaSReza Amini 236da915efaSReza Amini 237da915efaSReza Amini 238592a6318SAnthony Koo /** 239592a6318SAnthony Koo * OS/FW agnostic memcpy 240592a6318SAnthony Koo */ 24184034ad4SAnthony Koo #ifndef dmub_memcpy 24284034ad4SAnthony Koo #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 24384034ad4SAnthony Koo #endif 24484034ad4SAnthony Koo 245592a6318SAnthony Koo /** 246592a6318SAnthony Koo * OS/FW agnostic memset 247592a6318SAnthony Koo */ 24884034ad4SAnthony Koo #ifndef dmub_memset 24984034ad4SAnthony Koo #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 25084034ad4SAnthony Koo #endif 25184034ad4SAnthony Koo 252d9beecfcSAnthony Koo #if defined(__cplusplus) 253d9beecfcSAnthony Koo extern "C" { 254d9beecfcSAnthony Koo #endif 255d9beecfcSAnthony Koo 256592a6318SAnthony Koo /** 257592a6318SAnthony Koo * OS/FW agnostic udelay 258592a6318SAnthony Koo */ 25984034ad4SAnthony Koo #ifndef dmub_udelay 26084034ad4SAnthony Koo #define dmub_udelay(microseconds) udelay(microseconds) 26184034ad4SAnthony Koo #endif 26284034ad4SAnthony Koo 2636e60cba6SJonathan Gray #pragma pack(push, 1) 264592a6318SAnthony Koo /** 265592a6318SAnthony Koo * union dmub_addr - DMUB physical/virtual 64-bit address. 266592a6318SAnthony Koo */ 26784034ad4SAnthony Koo union dmub_addr { 26884034ad4SAnthony Koo struct { 269592a6318SAnthony Koo uint32_t low_part; /**< Lower 32 bits */ 270592a6318SAnthony Koo uint32_t high_part; /**< Upper 32 bits */ 271592a6318SAnthony Koo } u; /*<< Low/high bit access */ 272592a6318SAnthony Koo uint64_t quad_part; /*<< 64 bit address */ 27384034ad4SAnthony Koo }; 2746e60cba6SJonathan Gray #pragma pack(pop) 27584034ad4SAnthony Koo 2761a595f28SAnthony Koo /** 27783eb5385SDavid Zhang * Dirty rect definition. 27883eb5385SDavid Zhang */ 27983eb5385SDavid Zhang struct dmub_rect { 28083eb5385SDavid Zhang /** 28183eb5385SDavid Zhang * Dirty rect x offset. 28283eb5385SDavid Zhang */ 28383eb5385SDavid Zhang uint32_t x; 28483eb5385SDavid Zhang 28583eb5385SDavid Zhang /** 28683eb5385SDavid Zhang * Dirty rect y offset. 28783eb5385SDavid Zhang */ 28883eb5385SDavid Zhang uint32_t y; 28983eb5385SDavid Zhang 29083eb5385SDavid Zhang /** 29183eb5385SDavid Zhang * Dirty rect width. 29283eb5385SDavid Zhang */ 29383eb5385SDavid Zhang uint32_t width; 29483eb5385SDavid Zhang 29583eb5385SDavid Zhang /** 29683eb5385SDavid Zhang * Dirty rect height. 29783eb5385SDavid Zhang */ 29883eb5385SDavid Zhang uint32_t height; 29983eb5385SDavid Zhang }; 30083eb5385SDavid Zhang 30183eb5385SDavid Zhang /** 3021a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 3031a595f28SAnthony Koo */ 30484034ad4SAnthony Koo union dmub_psr_debug_flags { 3051a595f28SAnthony Koo /** 3061a595f28SAnthony Koo * Debug flags. 3071a595f28SAnthony Koo */ 30884034ad4SAnthony Koo struct { 3091a595f28SAnthony Koo /** 3101a595f28SAnthony Koo * Enable visual confirm in FW. 3111a595f28SAnthony Koo */ 312447f3d0fSAnthony Koo uint32_t visual_confirm : 1; 31383eb5385SDavid Zhang 31483eb5385SDavid Zhang /** 31583eb5385SDavid Zhang * Force all selective updates to bw full frame updates. 31683eb5385SDavid Zhang */ 31783eb5385SDavid Zhang uint32_t force_full_frame_update : 1; 31883eb5385SDavid Zhang 3191a595f28SAnthony Koo /** 3201a595f28SAnthony Koo * Use HW Lock Mgr object to do HW locking in FW. 3211a595f28SAnthony Koo */ 322447f3d0fSAnthony Koo uint32_t use_hw_lock_mgr : 1; 3231a595f28SAnthony Koo 3241a595f28SAnthony Koo /** 325548f2125SRobin Chen * Use TPS3 signal when restore main link. 3261a595f28SAnthony Koo */ 327548f2125SRobin Chen uint32_t force_wakeup_by_tps3 : 1; 328cf472dbdSAnthony Koo 329cf472dbdSAnthony Koo /** 330cf472dbdSAnthony Koo * Back to back flip, therefore cannot power down PHY 331cf472dbdSAnthony Koo */ 332cf472dbdSAnthony Koo uint32_t back_to_back_flip : 1; 333cf472dbdSAnthony Koo 33484034ad4SAnthony Koo } bitfields; 33584034ad4SAnthony Koo 3361a595f28SAnthony Koo /** 3371a595f28SAnthony Koo * Union for debug flags. 3381a595f28SAnthony Koo */ 339447f3d0fSAnthony Koo uint32_t u32All; 34084034ad4SAnthony Koo }; 34184034ad4SAnthony Koo 3421a595f28SAnthony Koo /** 3430991f44cSAnthony Koo * DMUB visual confirm color 3441a595f28SAnthony Koo */ 34534ba432cSAnthony Koo struct dmub_feature_caps { 3461a595f28SAnthony Koo /** 3471a595f28SAnthony Koo * Max PSR version supported by FW. 3481a595f28SAnthony Koo */ 34934ba432cSAnthony Koo uint8_t psr; 35000fa7f03SRodrigo Siqueira uint8_t fw_assisted_mclk_switch; 351278d3de6SAlvin Lee uint8_t reserved[4]; 35293aac179SAnthony Koo uint8_t subvp_psr_support; 353278d3de6SAlvin Lee uint8_t gecc_enable; 35434ba432cSAnthony Koo }; 35534ba432cSAnthony Koo 356b09c1fffSLeo (Hanghong) Ma struct dmub_visual_confirm_color { 357b09c1fffSLeo (Hanghong) Ma /** 358b09c1fffSLeo (Hanghong) Ma * Maximum 10 bits color value 359b09c1fffSLeo (Hanghong) Ma */ 360b09c1fffSLeo (Hanghong) Ma uint16_t color_r_cr; 361b09c1fffSLeo (Hanghong) Ma uint16_t color_g_y; 362b09c1fffSLeo (Hanghong) Ma uint16_t color_b_cb; 363b09c1fffSLeo (Hanghong) Ma uint16_t panel_inst; 364b09c1fffSLeo (Hanghong) Ma }; 365b09c1fffSLeo (Hanghong) Ma 36684034ad4SAnthony Koo #if defined(__cplusplus) 36784034ad4SAnthony Koo } 36884034ad4SAnthony Koo #endif 36984034ad4SAnthony Koo 37084034ad4SAnthony Koo //============================================================================== 37184034ad4SAnthony Koo //</DMUB_TYPES>================================================================= 37284034ad4SAnthony Koo //============================================================================== 37384034ad4SAnthony Koo //< DMUB_META>================================================================== 37484034ad4SAnthony Koo //============================================================================== 37584034ad4SAnthony Koo #pragma pack(push, 1) 37684034ad4SAnthony Koo 37784034ad4SAnthony Koo /* Magic value for identifying dmub_fw_meta_info */ 37884034ad4SAnthony Koo #define DMUB_FW_META_MAGIC 0x444D5542 37984034ad4SAnthony Koo 38084034ad4SAnthony Koo /* Offset from the end of the file to the dmub_fw_meta_info */ 38184034ad4SAnthony Koo #define DMUB_FW_META_OFFSET 0x24 38284034ad4SAnthony Koo 38384034ad4SAnthony Koo /** 38484034ad4SAnthony Koo * struct dmub_fw_meta_info - metadata associated with fw binary 38584034ad4SAnthony Koo * 38684034ad4SAnthony Koo * NOTE: This should be considered a stable API. Fields should 38784034ad4SAnthony Koo * not be repurposed or reordered. New fields should be 38884034ad4SAnthony Koo * added instead to extend the structure. 38984034ad4SAnthony Koo * 39084034ad4SAnthony Koo * @magic_value: magic value identifying DMUB firmware meta info 39184034ad4SAnthony Koo * @fw_region_size: size of the firmware state region 39284034ad4SAnthony Koo * @trace_buffer_size: size of the tracebuffer region 39384034ad4SAnthony Koo * @fw_version: the firmware version information 394b2265774SAnthony Koo * @dal_fw: 1 if the firmware is DAL 39584034ad4SAnthony Koo */ 39684034ad4SAnthony Koo struct dmub_fw_meta_info { 397592a6318SAnthony Koo uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 398592a6318SAnthony Koo uint32_t fw_region_size; /**< size of the firmware state region */ 399592a6318SAnthony Koo uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 400592a6318SAnthony Koo uint32_t fw_version; /**< the firmware version information */ 401592a6318SAnthony Koo uint8_t dal_fw; /**< 1 if the firmware is DAL */ 402592a6318SAnthony Koo uint8_t reserved[3]; /**< padding bits */ 40384034ad4SAnthony Koo }; 40484034ad4SAnthony Koo 405592a6318SAnthony Koo /** 406592a6318SAnthony Koo * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 407592a6318SAnthony Koo */ 40884034ad4SAnthony Koo union dmub_fw_meta { 409592a6318SAnthony Koo struct dmub_fw_meta_info info; /**< metadata info */ 410592a6318SAnthony Koo uint8_t reserved[64]; /**< padding bits */ 41184034ad4SAnthony Koo }; 41284034ad4SAnthony Koo 41384034ad4SAnthony Koo #pragma pack(pop) 414788408b7SAnthony Koo 41584034ad4SAnthony Koo //============================================================================== 4166b66208fSYongqiang Sun //< DMUB Trace Buffer>================================================================ 4176b66208fSYongqiang Sun //============================================================================== 418592a6318SAnthony Koo /** 419592a6318SAnthony Koo * dmub_trace_code_t - firmware trace code, 32-bits 420592a6318SAnthony Koo */ 4216b66208fSYongqiang Sun typedef uint32_t dmub_trace_code_t; 4226b66208fSYongqiang Sun 423592a6318SAnthony Koo /** 424592a6318SAnthony Koo * struct dmcub_trace_buf_entry - Firmware trace entry 425592a6318SAnthony Koo */ 4266b66208fSYongqiang Sun struct dmcub_trace_buf_entry { 427592a6318SAnthony Koo dmub_trace_code_t trace_code; /**< trace code for the event */ 428592a6318SAnthony Koo uint32_t tick_count; /**< the tick count at time of trace */ 429592a6318SAnthony Koo uint32_t param0; /**< trace defined parameter 0 */ 430592a6318SAnthony Koo uint32_t param1; /**< trace defined parameter 1 */ 4316b66208fSYongqiang Sun }; 4326b66208fSYongqiang Sun 4336b66208fSYongqiang Sun //============================================================================== 434788408b7SAnthony Koo //< DMUB_STATUS>================================================================ 435788408b7SAnthony Koo //============================================================================== 436788408b7SAnthony Koo 437788408b7SAnthony Koo /** 438788408b7SAnthony Koo * DMCUB scratch registers can be used to determine firmware status. 439788408b7SAnthony Koo * Current scratch register usage is as follows: 440788408b7SAnthony Koo * 441492dd8a8SAnthony Koo * SCRATCH0: FW Boot Status register 442021eaef8SAnthony Koo * SCRATCH5: LVTMA Status Register 443492dd8a8SAnthony Koo * SCRATCH15: FW Boot Options register 444788408b7SAnthony Koo */ 445788408b7SAnthony Koo 446592a6318SAnthony Koo /** 447592a6318SAnthony Koo * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 448592a6318SAnthony Koo */ 449492dd8a8SAnthony Koo union dmub_fw_boot_status { 450492dd8a8SAnthony Koo struct { 451592a6318SAnthony Koo uint32_t dal_fw : 1; /**< 1 if DAL FW */ 452592a6318SAnthony Koo uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 453592a6318SAnthony Koo uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 454592a6318SAnthony Koo uint32_t restore_required : 1; /**< 1 if driver should call restore */ 45501934c30SAnthony Koo uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 456e3416e87SRodrigo Siqueira uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 45701934c30SAnthony Koo uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 4589dce8c2aSAnthony Koo uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 459592a6318SAnthony Koo } bits; /**< status bits */ 460592a6318SAnthony Koo uint32_t all; /**< 32-bit access to status bits */ 461492dd8a8SAnthony Koo }; 462492dd8a8SAnthony Koo 463592a6318SAnthony Koo /** 464592a6318SAnthony Koo * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 465592a6318SAnthony Koo */ 466492dd8a8SAnthony Koo enum dmub_fw_boot_status_bit { 467592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 468592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 469592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 470592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 4711e0958bbSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 472053065a4SAurabindo Pillai DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 47301934c30SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 4749dce8c2aSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 475492dd8a8SAnthony Koo }; 476492dd8a8SAnthony Koo 477021eaef8SAnthony Koo /* Register bit definition for SCRATCH5 */ 478021eaef8SAnthony Koo union dmub_lvtma_status { 479021eaef8SAnthony Koo struct { 480021eaef8SAnthony Koo uint32_t psp_ok : 1; 481021eaef8SAnthony Koo uint32_t edp_on : 1; 482021eaef8SAnthony Koo uint32_t reserved : 30; 483021eaef8SAnthony Koo } bits; 484021eaef8SAnthony Koo uint32_t all; 485021eaef8SAnthony Koo }; 486021eaef8SAnthony Koo 487021eaef8SAnthony Koo enum dmub_lvtma_status_bit { 488021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 489021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 490021eaef8SAnthony Koo }; 491021eaef8SAnthony Koo 4926d7d0a4bSAnthony Koo enum dmub_ips_disable_type { 4936d7d0a4bSAnthony Koo DMUB_IPS_DISABLE_IPS1 = 1, 4946d7d0a4bSAnthony Koo DMUB_IPS_DISABLE_IPS2 = 2, 4956d7d0a4bSAnthony Koo DMUB_IPS_DISABLE_IPS2_Z10 = 3, 4966d7d0a4bSAnthony Koo }; 4976d7d0a4bSAnthony Koo 498592a6318SAnthony Koo /** 4991e0958bbSAnthony Koo * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 500592a6318SAnthony Koo */ 501492dd8a8SAnthony Koo union dmub_fw_boot_options { 502492dd8a8SAnthony Koo struct { 503592a6318SAnthony Koo uint32_t pemu_env : 1; /**< 1 if PEMU */ 504592a6318SAnthony Koo uint32_t fpga_env : 1; /**< 1 if FPGA */ 505592a6318SAnthony Koo uint32_t optimized_init : 1; /**< 1 if optimized init */ 506592a6318SAnthony Koo uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 507592a6318SAnthony Koo uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 508592a6318SAnthony Koo uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 509b04cb192SNicholas Kazlauskas uint32_t z10_disable: 1; /**< 1 to disable z10 */ 510b0ce6272SMeenakshikumar Somasundaram uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 5111e0958bbSAnthony Koo uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 5123137f792SHansen uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 5133137f792SHansen uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 5143137f792SHansen /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 5153137f792SHansen uint32_t power_optimization: 1; 516b129c94eSAnthony Koo uint32_t diag_env: 1; /* 1 if diagnostic environment */ 5175cef7e8eSAnthony Koo uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 518ea5a4db9SAnthony Koo uint32_t usb4_cm_version: 1; /**< 1 CM support */ 5196f4f8ff5SMeenakshikumar Somasundaram uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 52073f73741SAnthony Koo uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 521c79503dcSAnthony Koo uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 52227664177SAnthony Koo uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 5236d7d0a4bSAnthony Koo uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 5246d7d0a4bSAnthony Koo uint32_t ips_disable: 2; /* options to disable ips support*/ 5256d7d0a4bSAnthony Koo uint32_t reserved : 10; /**< reserved */ 526592a6318SAnthony Koo } bits; /**< boot bits */ 527592a6318SAnthony Koo uint32_t all; /**< 32-bit access to bits */ 528492dd8a8SAnthony Koo }; 529492dd8a8SAnthony Koo 530492dd8a8SAnthony Koo enum dmub_fw_boot_options_bit { 531592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 532592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 533592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 534492dd8a8SAnthony Koo }; 535492dd8a8SAnthony Koo 536788408b7SAnthony Koo //============================================================================== 537788408b7SAnthony Koo //</DMUB_STATUS>================================================================ 53884034ad4SAnthony Koo //============================================================================== 53984034ad4SAnthony Koo //< DMUB_VBIOS>================================================================= 54084034ad4SAnthony Koo //============================================================================== 54184034ad4SAnthony Koo 54284034ad4SAnthony Koo /* 543592a6318SAnthony Koo * enum dmub_cmd_vbios_type - VBIOS commands. 544592a6318SAnthony Koo * 54584034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 54684034ad4SAnthony Koo * Do not reuse or modify IDs. 54784034ad4SAnthony Koo */ 54884034ad4SAnthony Koo enum dmub_cmd_vbios_type { 549592a6318SAnthony Koo /** 550592a6318SAnthony Koo * Configures the DIG encoder. 551592a6318SAnthony Koo */ 55284034ad4SAnthony Koo DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 553592a6318SAnthony Koo /** 554592a6318SAnthony Koo * Controls the PHY. 555592a6318SAnthony Koo */ 55684034ad4SAnthony Koo DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 557592a6318SAnthony Koo /** 558592a6318SAnthony Koo * Sets the pixel clock/symbol clock. 559592a6318SAnthony Koo */ 56084034ad4SAnthony Koo DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 561592a6318SAnthony Koo /** 562592a6318SAnthony Koo * Enables or disables power gating. 563592a6318SAnthony Koo */ 56484034ad4SAnthony Koo DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 56541f91315SNicholas Kazlauskas /** 56641f91315SNicholas Kazlauskas * Controls embedded panels. 56741f91315SNicholas Kazlauskas */ 5682ac685bfSAnthony Koo DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 56941f91315SNicholas Kazlauskas /** 57041f91315SNicholas Kazlauskas * Query DP alt status on a transmitter. 57141f91315SNicholas Kazlauskas */ 57241f91315SNicholas Kazlauskas DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 573e383b127SNicholas Kazlauskas /** 574e383b127SNicholas Kazlauskas * Controls domain power gating 575e383b127SNicholas Kazlauskas */ 576e383b127SNicholas Kazlauskas DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 57784034ad4SAnthony Koo }; 57884034ad4SAnthony Koo 57984034ad4SAnthony Koo //============================================================================== 58084034ad4SAnthony Koo //</DMUB_VBIOS>================================================================= 58184034ad4SAnthony Koo //============================================================================== 58284034ad4SAnthony Koo //< DMUB_GPINT>================================================================= 58384034ad4SAnthony Koo //============================================================================== 58484034ad4SAnthony Koo 58584034ad4SAnthony Koo /** 58684034ad4SAnthony Koo * The shifts and masks below may alternatively be used to format and read 58784034ad4SAnthony Koo * the command register bits. 58884034ad4SAnthony Koo */ 58984034ad4SAnthony Koo 59084034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 59184034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_SHIFT 0 59284034ad4SAnthony Koo 59384034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 59484034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 59584034ad4SAnthony Koo 59684034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_MASK 0xF 59784034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_SHIFT 28 59884034ad4SAnthony Koo 59984034ad4SAnthony Koo /** 60084034ad4SAnthony Koo * Command responses. 60184034ad4SAnthony Koo */ 60284034ad4SAnthony Koo 603592a6318SAnthony Koo /** 604592a6318SAnthony Koo * Return response for DMUB_GPINT__STOP_FW command. 605592a6318SAnthony Koo */ 60684034ad4SAnthony Koo #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 60784034ad4SAnthony Koo 60884034ad4SAnthony Koo /** 609592a6318SAnthony Koo * union dmub_gpint_data_register - Format for sending a command via the GPINT. 61084034ad4SAnthony Koo */ 61184034ad4SAnthony Koo union dmub_gpint_data_register { 61284034ad4SAnthony Koo struct { 613592a6318SAnthony Koo uint32_t param : 16; /**< 16-bit parameter */ 614592a6318SAnthony Koo uint32_t command_code : 12; /**< GPINT command */ 615592a6318SAnthony Koo uint32_t status : 4; /**< Command status bit */ 616592a6318SAnthony Koo } bits; /**< GPINT bit access */ 617592a6318SAnthony Koo uint32_t all; /**< GPINT 32-bit access */ 61884034ad4SAnthony Koo }; 61984034ad4SAnthony Koo 62084034ad4SAnthony Koo /* 621592a6318SAnthony Koo * enum dmub_gpint_command - GPINT command to DMCUB FW 622592a6318SAnthony Koo * 62384034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 62484034ad4SAnthony Koo * Do not reuse or modify IDs. 62584034ad4SAnthony Koo */ 62684034ad4SAnthony Koo enum dmub_gpint_command { 627592a6318SAnthony Koo /** 628592a6318SAnthony Koo * Invalid command, ignored. 629592a6318SAnthony Koo */ 63084034ad4SAnthony Koo DMUB_GPINT__INVALID_COMMAND = 0, 631592a6318SAnthony Koo /** 632592a6318SAnthony Koo * DESC: Queries the firmware version. 633592a6318SAnthony Koo * RETURN: Firmware version. 634592a6318SAnthony Koo */ 63584034ad4SAnthony Koo DMUB_GPINT__GET_FW_VERSION = 1, 636592a6318SAnthony Koo /** 637592a6318SAnthony Koo * DESC: Halts the firmware. 638592a6318SAnthony Koo * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 639592a6318SAnthony Koo */ 64084034ad4SAnthony Koo DMUB_GPINT__STOP_FW = 2, 6411a595f28SAnthony Koo /** 6421a595f28SAnthony Koo * DESC: Get PSR state from FW. 6431a595f28SAnthony Koo * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 6441a595f28SAnthony Koo */ 64584034ad4SAnthony Koo DMUB_GPINT__GET_PSR_STATE = 7, 64680eba958SAnthony Koo /** 64780eba958SAnthony Koo * DESC: Notifies DMCUB of the currently active streams. 64880eba958SAnthony Koo * ARGS: Stream mask, 1 bit per active stream index. 64980eba958SAnthony Koo */ 65080eba958SAnthony Koo DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 6511a595f28SAnthony Koo /** 6521a595f28SAnthony Koo * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 6531a595f28SAnthony Koo * ARGS: We can measure residency from various points. The argument will specify the residency mode. 6541a595f28SAnthony Koo * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 6551a595f28SAnthony Koo * RETURN: PSR residency in milli-percent. 6561a595f28SAnthony Koo */ 657672251b2SAnthony Koo DMUB_GPINT__PSR_RESIDENCY = 9, 65801934c30SAnthony Koo 65901934c30SAnthony Koo /** 66001934c30SAnthony Koo * DESC: Notifies DMCUB detection is done so detection required can be cleared. 66101934c30SAnthony Koo */ 66201934c30SAnthony Koo DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 66384034ad4SAnthony Koo }; 66484034ad4SAnthony Koo 6650b51e7e8SAnthony Koo /** 6660b51e7e8SAnthony Koo * INBOX0 generic command definition 6670b51e7e8SAnthony Koo */ 6680b51e7e8SAnthony Koo union dmub_inbox0_cmd_common { 6690b51e7e8SAnthony Koo struct { 6700b51e7e8SAnthony Koo uint32_t command_code: 8; /**< INBOX0 command code */ 6710b51e7e8SAnthony Koo uint32_t param: 24; /**< 24-bit parameter */ 6720b51e7e8SAnthony Koo } bits; 6730b51e7e8SAnthony Koo uint32_t all; 6740b51e7e8SAnthony Koo }; 6750b51e7e8SAnthony Koo 6760b51e7e8SAnthony Koo /** 6770b51e7e8SAnthony Koo * INBOX0 hw_lock command definition 6780b51e7e8SAnthony Koo */ 6790b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw { 6800b51e7e8SAnthony Koo struct { 6810b51e7e8SAnthony Koo uint32_t command_code: 8; 6820b51e7e8SAnthony Koo 6830b51e7e8SAnthony Koo /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 6842412d339SAnthony Koo uint32_t hw_lock_client: 2; 6850b51e7e8SAnthony Koo 6860b51e7e8SAnthony Koo /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 6870b51e7e8SAnthony Koo uint32_t otg_inst: 3; 6880b51e7e8SAnthony Koo uint32_t opp_inst: 3; 6890b51e7e8SAnthony Koo uint32_t dig_inst: 3; 6900b51e7e8SAnthony Koo 6910b51e7e8SAnthony Koo /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 6920b51e7e8SAnthony Koo uint32_t lock_pipe: 1; 6930b51e7e8SAnthony Koo uint32_t lock_cursor: 1; 6940b51e7e8SAnthony Koo uint32_t lock_dig: 1; 6950b51e7e8SAnthony Koo uint32_t triple_buffer_lock: 1; 6960b51e7e8SAnthony Koo 6970b51e7e8SAnthony Koo uint32_t lock: 1; /**< Lock */ 6980b51e7e8SAnthony Koo uint32_t should_release: 1; /**< Release */ 6992412d339SAnthony Koo uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 7000b51e7e8SAnthony Koo } bits; 7010b51e7e8SAnthony Koo uint32_t all; 7020b51e7e8SAnthony Koo }; 7030b51e7e8SAnthony Koo 7040b51e7e8SAnthony Koo union dmub_inbox0_data_register { 7050b51e7e8SAnthony Koo union dmub_inbox0_cmd_common inbox0_cmd_common; 7060b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 7070b51e7e8SAnthony Koo }; 7080b51e7e8SAnthony Koo 7090b51e7e8SAnthony Koo enum dmub_inbox0_command { 7100b51e7e8SAnthony Koo /** 7110b51e7e8SAnthony Koo * DESC: Invalid command, ignored. 7120b51e7e8SAnthony Koo */ 7130b51e7e8SAnthony Koo DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 7140b51e7e8SAnthony Koo /** 7150b51e7e8SAnthony Koo * DESC: Notification to acquire/release HW lock 7160b51e7e8SAnthony Koo * ARGS: 7170b51e7e8SAnthony Koo */ 7180b51e7e8SAnthony Koo DMUB_INBOX0_CMD__HW_LOCK = 1, 7190b51e7e8SAnthony Koo }; 72084034ad4SAnthony Koo //============================================================================== 72184034ad4SAnthony Koo //</DMUB_GPINT>================================================================= 72284034ad4SAnthony Koo //============================================================================== 72384034ad4SAnthony Koo //< DMUB_CMD>=================================================================== 72484034ad4SAnthony Koo //============================================================================== 72584034ad4SAnthony Koo 726592a6318SAnthony Koo /** 727592a6318SAnthony Koo * Size in bytes of each DMUB command. 728592a6318SAnthony Koo */ 7297c008829SNicholas Kazlauskas #define DMUB_RB_CMD_SIZE 64 730592a6318SAnthony Koo 731592a6318SAnthony Koo /** 732592a6318SAnthony Koo * Maximum number of items in the DMUB ringbuffer. 733592a6318SAnthony Koo */ 7347c008829SNicholas Kazlauskas #define DMUB_RB_MAX_ENTRY 128 735592a6318SAnthony Koo 736592a6318SAnthony Koo /** 737592a6318SAnthony Koo * Ringbuffer size in bytes. 738592a6318SAnthony Koo */ 7397c008829SNicholas Kazlauskas #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 740592a6318SAnthony Koo 741592a6318SAnthony Koo /** 742592a6318SAnthony Koo * REG_SET mask for reg offload. 743592a6318SAnthony Koo */ 7447c008829SNicholas Kazlauskas #define REG_SET_MASK 0xFFFF 7457c008829SNicholas Kazlauskas 746d4bbcecbSNicholas Kazlauskas /* 747592a6318SAnthony Koo * enum dmub_cmd_type - DMUB inbox command. 748592a6318SAnthony Koo * 749d4bbcecbSNicholas Kazlauskas * Command IDs should be treated as stable ABI. 750d4bbcecbSNicholas Kazlauskas * Do not reuse or modify IDs. 751d4bbcecbSNicholas Kazlauskas */ 752d4bbcecbSNicholas Kazlauskas enum dmub_cmd_type { 753592a6318SAnthony Koo /** 754592a6318SAnthony Koo * Invalid command. 755592a6318SAnthony Koo */ 756d4bbcecbSNicholas Kazlauskas DMUB_CMD__NULL = 0, 757592a6318SAnthony Koo /** 758592a6318SAnthony Koo * Read modify write register sequence offload. 759592a6318SAnthony Koo */ 760d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 761592a6318SAnthony Koo /** 762592a6318SAnthony Koo * Field update register sequence offload. 763592a6318SAnthony Koo */ 764d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 765592a6318SAnthony Koo /** 766592a6318SAnthony Koo * Burst write sequence offload. 767592a6318SAnthony Koo */ 768d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 769592a6318SAnthony Koo /** 770592a6318SAnthony Koo * Reg wait sequence offload. 771592a6318SAnthony Koo */ 772d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_REG_WAIT = 4, 773592a6318SAnthony Koo /** 774592a6318SAnthony Koo * Workaround to avoid HUBP underflow during NV12 playback. 775592a6318SAnthony Koo */ 776bae9c49bSYongqiang Sun DMUB_CMD__PLAT_54186_WA = 5, 7771a595f28SAnthony Koo /** 7781a595f28SAnthony Koo * Command type used to query FW feature caps. 7791a595f28SAnthony Koo */ 78034ba432cSAnthony Koo DMUB_CMD__QUERY_FEATURE_CAPS = 6, 7811a595f28SAnthony Koo /** 782b09c1fffSLeo (Hanghong) Ma * Command type used to get visual confirm color. 783b09c1fffSLeo (Hanghong) Ma */ 784b09c1fffSLeo (Hanghong) Ma DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 785b09c1fffSLeo (Hanghong) Ma /** 7861a595f28SAnthony Koo * Command type used for all PSR commands. 7871a595f28SAnthony Koo */ 788d4bbcecbSNicholas Kazlauskas DMUB_CMD__PSR = 64, 789592a6318SAnthony Koo /** 790592a6318SAnthony Koo * Command type used for all MALL commands. 791592a6318SAnthony Koo */ 79252f2e83eSBhawanpreet Lakha DMUB_CMD__MALL = 65, 7931a595f28SAnthony Koo /** 7941a595f28SAnthony Koo * Command type used for all ABM commands. 7951a595f28SAnthony Koo */ 796e6ea8c34SWyatt Wood DMUB_CMD__ABM = 66, 7971a595f28SAnthony Koo /** 79883eb5385SDavid Zhang * Command type used to update dirty rects in FW. 79983eb5385SDavid Zhang */ 80083eb5385SDavid Zhang DMUB_CMD__UPDATE_DIRTY_RECT = 67, 80183eb5385SDavid Zhang /** 80283eb5385SDavid Zhang * Command type used to update cursor info in FW. 80383eb5385SDavid Zhang */ 80483eb5385SDavid Zhang DMUB_CMD__UPDATE_CURSOR_INFO = 68, 80583eb5385SDavid Zhang /** 8061a595f28SAnthony Koo * Command type used for HW locking in FW. 8071a595f28SAnthony Koo */ 808788408b7SAnthony Koo DMUB_CMD__HW_LOCK = 69, 8091a595f28SAnthony Koo /** 8101a595f28SAnthony Koo * Command type used to access DP AUX. 8111a595f28SAnthony Koo */ 812d9beecfcSAnthony Koo DMUB_CMD__DP_AUX_ACCESS = 70, 8131a595f28SAnthony Koo /** 8141a595f28SAnthony Koo * Command type used for OUTBOX1 notification enable 8151a595f28SAnthony Koo */ 816d9beecfcSAnthony Koo DMUB_CMD__OUTBOX1_ENABLE = 71, 8175cef7e8eSAnthony Koo 818b04cb192SNicholas Kazlauskas /** 819b04cb192SNicholas Kazlauskas * Command type used for all idle optimization commands. 820b04cb192SNicholas Kazlauskas */ 821b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT = 72, 822b04cb192SNicholas Kazlauskas /** 823b04cb192SNicholas Kazlauskas * Command type used for all clock manager commands. 824b04cb192SNicholas Kazlauskas */ 825b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR = 73, 826b04cb192SNicholas Kazlauskas /** 827b04cb192SNicholas Kazlauskas * Command type used for all panel control commands. 828b04cb192SNicholas Kazlauskas */ 829b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL = 74, 830ac2e555eSAurabindo Pillai /** 831ac2e555eSAurabindo Pillai * Command type used for <TODO:description> 832ac2e555eSAurabindo Pillai */ 833ac2e555eSAurabindo Pillai DMUB_CMD__CAB_FOR_SS = 75, 83485f4bc0cSAlvin Lee 83585f4bc0cSAlvin Lee DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 83685f4bc0cSAlvin Lee 837592a6318SAnthony Koo /** 83876724b76SJimmy Kizito * Command type used for interfacing with DPIA. 83976724b76SJimmy Kizito */ 84076724b76SJimmy Kizito DMUB_CMD__DPIA = 77, 84176724b76SJimmy Kizito /** 842021eaef8SAnthony Koo * Command type used for EDID CEA parsing 843021eaef8SAnthony Koo */ 844021eaef8SAnthony Koo DMUB_CMD__EDID_CEA = 79, 845021eaef8SAnthony Koo /** 846c595fb05SWenjing Liu * Command type used for getting usbc cable ID 847c595fb05SWenjing Liu */ 848c595fb05SWenjing Liu DMUB_CMD_GET_USBC_CABLE_ID = 81, 849c595fb05SWenjing Liu /** 850ea5a4db9SAnthony Koo * Command type used to query HPD state. 851ea5a4db9SAnthony Koo */ 852ea5a4db9SAnthony Koo DMUB_CMD__QUERY_HPD_STATE = 82, 853ea5a4db9SAnthony Koo /** 854592a6318SAnthony Koo * Command type used for all VBIOS interface commands. 855592a6318SAnthony Koo */ 8561fb695d9SAnthony Koo 857c0459bddSAlan Liu /** 858c0459bddSAlan Liu * Command type used for all SECURE_DISPLAY commands. 859c0459bddSAlan Liu */ 860c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY = 85, 8616f4f8ff5SMeenakshikumar Somasundaram 8626f4f8ff5SMeenakshikumar Somasundaram /** 8636f4f8ff5SMeenakshikumar Somasundaram * Command type used to set DPIA HPD interrupt state 8646f4f8ff5SMeenakshikumar Somasundaram */ 8656f4f8ff5SMeenakshikumar Somasundaram DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 8666f4f8ff5SMeenakshikumar Somasundaram 867d4bbcecbSNicholas Kazlauskas DMUB_CMD__VBIOS = 128, 8687c008829SNicholas Kazlauskas }; 8697c008829SNicholas Kazlauskas 870592a6318SAnthony Koo /** 871592a6318SAnthony Koo * enum dmub_out_cmd_type - DMUB outbox commands. 872592a6318SAnthony Koo */ 8733b37260bSAnthony Koo enum dmub_out_cmd_type { 874592a6318SAnthony Koo /** 875592a6318SAnthony Koo * Invalid outbox command, ignored. 876592a6318SAnthony Koo */ 8773b37260bSAnthony Koo DMUB_OUT_CMD__NULL = 0, 8781a595f28SAnthony Koo /** 8791a595f28SAnthony Koo * Command type used for DP AUX Reply data notification 8801a595f28SAnthony Koo */ 881d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_AUX_REPLY = 1, 882892b74a6SMeenakshikumar Somasundaram /** 883892b74a6SMeenakshikumar Somasundaram * Command type used for DP HPD event notification 884892b74a6SMeenakshikumar Somasundaram */ 885892b74a6SMeenakshikumar Somasundaram DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 88671af9d46SMeenakshikumar Somasundaram /** 88771af9d46SMeenakshikumar Somasundaram * Command type used for SET_CONFIG Reply notification 88871af9d46SMeenakshikumar Somasundaram */ 88971af9d46SMeenakshikumar Somasundaram DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 8908af54c61SMustapha Ghaddar /** 8918af54c61SMustapha Ghaddar * Command type used for USB4 DPIA notification 8928af54c61SMustapha Ghaddar */ 8938af54c61SMustapha Ghaddar DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 8943b37260bSAnthony Koo }; 8953b37260bSAnthony Koo 89676724b76SJimmy Kizito /* DMUB_CMD__DPIA command sub-types. */ 89776724b76SJimmy Kizito enum dmub_cmd_dpia_type { 89876724b76SJimmy Kizito DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 89971af9d46SMeenakshikumar Somasundaram DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 900139a3311SMeenakshikumar Somasundaram DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 90176724b76SJimmy Kizito }; 90276724b76SJimmy Kizito 9038af54c61SMustapha Ghaddar /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 9048af54c61SMustapha Ghaddar enum dmub_cmd_dpia_notification_type { 9058af54c61SMustapha Ghaddar DPIA_NOTIFY__BW_ALLOCATION = 0, 9068af54c61SMustapha Ghaddar }; 9078af54c61SMustapha Ghaddar 9087c008829SNicholas Kazlauskas #pragma pack(push, 1) 9097c008829SNicholas Kazlauskas 910592a6318SAnthony Koo /** 911592a6318SAnthony Koo * struct dmub_cmd_header - Common command header fields. 912592a6318SAnthony Koo */ 9137c008829SNicholas Kazlauskas struct dmub_cmd_header { 914592a6318SAnthony Koo unsigned int type : 8; /**< command type */ 915592a6318SAnthony Koo unsigned int sub_type : 8; /**< command sub type */ 916592a6318SAnthony Koo unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 9170b51e7e8SAnthony Koo unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 9180b51e7e8SAnthony Koo unsigned int reserved0 : 6; /**< reserved bits */ 919592a6318SAnthony Koo unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 920592a6318SAnthony Koo unsigned int reserved1 : 2; /**< reserved bits */ 9217c008829SNicholas Kazlauskas }; 9227c008829SNicholas Kazlauskas 9237c008829SNicholas Kazlauskas /* 924592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write 9257c008829SNicholas Kazlauskas * 9267c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 5 sets of read modify writes, 9277c008829SNicholas Kazlauskas * each take 3 dwords. 9287c008829SNicholas Kazlauskas * 9297c008829SNicholas Kazlauskas * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 9307c008829SNicholas Kazlauskas * 9317c008829SNicholas Kazlauskas * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 9327c008829SNicholas Kazlauskas * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 9337c008829SNicholas Kazlauskas */ 9347c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence { 935592a6318SAnthony Koo uint32_t addr; /**< register address */ 936592a6318SAnthony Koo uint32_t modify_mask; /**< modify mask */ 937592a6318SAnthony Koo uint32_t modify_value; /**< modify value */ 9387c008829SNicholas Kazlauskas }; 9397c008829SNicholas Kazlauskas 940592a6318SAnthony Koo /** 941592a6318SAnthony Koo * Maximum number of ops in read modify write sequence. 942592a6318SAnthony Koo */ 9437c008829SNicholas Kazlauskas #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 944592a6318SAnthony Koo 945592a6318SAnthony Koo /** 946592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 947592a6318SAnthony Koo */ 9487c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write { 949592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 950592a6318SAnthony Koo /** 951592a6318SAnthony Koo * Read modify write sequence. 952592a6318SAnthony Koo */ 9537c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 9547c008829SNicholas Kazlauskas }; 9557c008829SNicholas Kazlauskas 9567c008829SNicholas Kazlauskas /* 9577c008829SNicholas Kazlauskas * Update a register with specified masks and values sequeunce 9587c008829SNicholas Kazlauskas * 9597c008829SNicholas Kazlauskas * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 9607c008829SNicholas Kazlauskas * 9617c008829SNicholas Kazlauskas * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 9627c008829SNicholas Kazlauskas * 9637c008829SNicholas Kazlauskas * 9647c008829SNicholas Kazlauskas * USE CASE: 9657c008829SNicholas Kazlauskas * 1. auto-increment register where additional read would update pointer and produce wrong result 9667c008829SNicholas Kazlauskas * 2. toggle a bit without read in the middle 9677c008829SNicholas Kazlauskas */ 9687c008829SNicholas Kazlauskas 9697c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence { 970592a6318SAnthony Koo uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 971592a6318SAnthony Koo uint32_t modify_value; /**< value to update with */ 9727c008829SNicholas Kazlauskas }; 9737c008829SNicholas Kazlauskas 974592a6318SAnthony Koo /** 975592a6318SAnthony Koo * Maximum number of ops in field update sequence. 976592a6318SAnthony Koo */ 9777c008829SNicholas Kazlauskas #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 978592a6318SAnthony Koo 979592a6318SAnthony Koo /** 980592a6318SAnthony Koo * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 981592a6318SAnthony Koo */ 9827c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence { 983592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 984592a6318SAnthony Koo uint32_t addr; /**< register address */ 985592a6318SAnthony Koo /** 986592a6318SAnthony Koo * Field update sequence. 987592a6318SAnthony Koo */ 9887c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 9897c008829SNicholas Kazlauskas }; 9907c008829SNicholas Kazlauskas 991592a6318SAnthony Koo 992592a6318SAnthony Koo /** 993592a6318SAnthony Koo * Maximum number of burst write values. 994592a6318SAnthony Koo */ 995592a6318SAnthony Koo #define DMUB_BURST_WRITE_VALUES__MAX 14 996592a6318SAnthony Koo 9977c008829SNicholas Kazlauskas /* 998592a6318SAnthony Koo * struct dmub_rb_cmd_burst_write - Burst write 9997c008829SNicholas Kazlauskas * 10007c008829SNicholas Kazlauskas * support use case such as writing out LUTs. 10017c008829SNicholas Kazlauskas * 10027c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 14 values to write to given address 10037c008829SNicholas Kazlauskas * 10047c008829SNicholas Kazlauskas * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 10057c008829SNicholas Kazlauskas */ 10067c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write { 1007592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 1008592a6318SAnthony Koo uint32_t addr; /**< register start address */ 1009592a6318SAnthony Koo /** 1010592a6318SAnthony Koo * Burst write register values. 1011592a6318SAnthony Koo */ 10127c008829SNicholas Kazlauskas uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 10137c008829SNicholas Kazlauskas }; 10147c008829SNicholas Kazlauskas 1015592a6318SAnthony Koo /** 1016592a6318SAnthony Koo * struct dmub_rb_cmd_common - Common command header 1017592a6318SAnthony Koo */ 10187c008829SNicholas Kazlauskas struct dmub_rb_cmd_common { 1019592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 1020592a6318SAnthony Koo /** 1021592a6318SAnthony Koo * Padding to RB_CMD_SIZE 1022592a6318SAnthony Koo */ 10237c008829SNicholas Kazlauskas uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 10247c008829SNicholas Kazlauskas }; 10257c008829SNicholas Kazlauskas 1026592a6318SAnthony Koo /** 1027592a6318SAnthony Koo * struct dmub_cmd_reg_wait_data - Register wait data 1028592a6318SAnthony Koo */ 10297c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data { 1030592a6318SAnthony Koo uint32_t addr; /**< Register address */ 1031592a6318SAnthony Koo uint32_t mask; /**< Mask for register bits */ 1032592a6318SAnthony Koo uint32_t condition_field_value; /**< Value to wait for */ 1033592a6318SAnthony Koo uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 10347c008829SNicholas Kazlauskas }; 10357c008829SNicholas Kazlauskas 1036592a6318SAnthony Koo /** 1037592a6318SAnthony Koo * struct dmub_rb_cmd_reg_wait - Register wait command 1038592a6318SAnthony Koo */ 10397c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait { 1040592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 1041592a6318SAnthony Koo struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 10427c008829SNicholas Kazlauskas }; 10437c008829SNicholas Kazlauskas 1044592a6318SAnthony Koo /** 1045592a6318SAnthony Koo * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1046592a6318SAnthony Koo * 1047592a6318SAnthony Koo * Reprograms surface parameters to avoid underflow. 1048592a6318SAnthony Koo */ 1049bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa { 1050592a6318SAnthony Koo uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1051592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1052592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1053592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1054592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 105522aa5614SYongqiang Sun struct { 1056592a6318SAnthony Koo uint8_t hubp_inst : 4; /**< HUBP instance */ 1057592a6318SAnthony Koo uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 1058592a6318SAnthony Koo uint8_t immediate :1; /**< Immediate flip */ 1059592a6318SAnthony Koo uint8_t vmid : 4; /**< VMID */ 1060592a6318SAnthony Koo uint8_t grph_stereo : 1; /**< 1 if stereo */ 1061592a6318SAnthony Koo uint32_t reserved : 21; /**< Reserved */ 1062592a6318SAnthony Koo } flip_params; /**< Pageflip parameters */ 1063d2994b25SAyush Gupta uint32_t reserved[9]; /**< Reserved bits */ 10648c019253SYongqiang Sun }; 10658c019253SYongqiang Sun 1066592a6318SAnthony Koo /** 1067592a6318SAnthony Koo * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1068592a6318SAnthony Koo */ 1069bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa { 1070592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 1071592a6318SAnthony Koo struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 10728c019253SYongqiang Sun }; 10738c019253SYongqiang Sun 1074592a6318SAnthony Koo /** 1075592a6318SAnthony Koo * struct dmub_rb_cmd_mall - MALL command data. 1076592a6318SAnthony Koo */ 107752f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall { 1078592a6318SAnthony Koo struct dmub_cmd_header header; /**< Common command header */ 1079592a6318SAnthony Koo union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1080592a6318SAnthony Koo union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1081592a6318SAnthony Koo uint32_t tmr_delay; /**< Timer delay */ 1082592a6318SAnthony Koo uint32_t tmr_scale; /**< Timer scale */ 1083592a6318SAnthony Koo uint16_t cursor_width; /**< Cursor width in pixels */ 1084592a6318SAnthony Koo uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1085592a6318SAnthony Koo uint16_t cursor_height; /**< Cursor height in pixels */ 1086592a6318SAnthony Koo uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1087592a6318SAnthony Koo uint8_t debug_bits; /**< Debug bits */ 1088ea7154d8SBhawanpreet Lakha 1089592a6318SAnthony Koo uint8_t reserved1; /**< Reserved bits */ 1090592a6318SAnthony Koo uint8_t reserved2; /**< Reserved bits */ 109152f2e83eSBhawanpreet Lakha }; 109252f2e83eSBhawanpreet Lakha 1093b04cb192SNicholas Kazlauskas /** 1094053065a4SAurabindo Pillai * enum dmub_cmd_cab_type - CAB command data. 1095ac2e555eSAurabindo Pillai */ 1096ac2e555eSAurabindo Pillai enum dmub_cmd_cab_type { 1097053065a4SAurabindo Pillai /** 1098053065a4SAurabindo Pillai * No idle optimizations (i.e. no CAB) 1099053065a4SAurabindo Pillai */ 1100ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1101053065a4SAurabindo Pillai /** 1102053065a4SAurabindo Pillai * No DCN requests for memory 1103053065a4SAurabindo Pillai */ 1104ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_DCN_REQ = 1, 1105053065a4SAurabindo Pillai /** 1106053065a4SAurabindo Pillai * Fit surfaces in CAB (i.e. CAB enable) 1107053065a4SAurabindo Pillai */ 1108ac2e555eSAurabindo Pillai DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1109ac2e555eSAurabindo Pillai }; 1110ac2e555eSAurabindo Pillai 1111ac2e555eSAurabindo Pillai /** 1112053065a4SAurabindo Pillai * struct dmub_rb_cmd_cab - CAB command data. 1113ac2e555eSAurabindo Pillai */ 1114ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss { 1115ac2e555eSAurabindo Pillai struct dmub_cmd_header header; 1116ac2e555eSAurabindo Pillai uint8_t cab_alloc_ways; /* total number of ways */ 1117ac2e555eSAurabindo Pillai uint8_t debug_bits; /* debug bits */ 1118ac2e555eSAurabindo Pillai }; 111985f4bc0cSAlvin Lee 1120053065a4SAurabindo Pillai /** 1121053065a4SAurabindo Pillai * Enum for indicating which MCLK switch mode per pipe 1122053065a4SAurabindo Pillai */ 112385f4bc0cSAlvin Lee enum mclk_switch_mode { 112485f4bc0cSAlvin Lee NONE = 0, 112585f4bc0cSAlvin Lee FPO = 1, 112685f4bc0cSAlvin Lee SUBVP = 2, 112785f4bc0cSAlvin Lee VBLANK = 3, 112885f4bc0cSAlvin Lee }; 112985f4bc0cSAlvin Lee 113085f4bc0cSAlvin Lee /* Per pipe struct which stores the MCLK switch mode 113185f4bc0cSAlvin Lee * data to be sent to DMUB. 113285f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 113385f4bc0cSAlvin Lee * the type name can be updated 113485f4bc0cSAlvin Lee */ 113585f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 113685f4bc0cSAlvin Lee union { 113785f4bc0cSAlvin Lee struct { 113885f4bc0cSAlvin Lee uint32_t pix_clk_100hz; 113985f4bc0cSAlvin Lee uint16_t main_vblank_start; 114085f4bc0cSAlvin Lee uint16_t main_vblank_end; 114185f4bc0cSAlvin Lee uint16_t mall_region_lines; 114285f4bc0cSAlvin Lee uint16_t prefetch_lines; 114385f4bc0cSAlvin Lee uint16_t prefetch_to_mall_start_lines; 114485f4bc0cSAlvin Lee uint16_t processing_delay_lines; 114585f4bc0cSAlvin Lee uint16_t htotal; // required to calculate line time for multi-display cases 114685f4bc0cSAlvin Lee uint16_t vtotal; 114785f4bc0cSAlvin Lee uint8_t main_pipe_index; 114885f4bc0cSAlvin Lee uint8_t phantom_pipe_index; 11490acc5b06SAnthony Koo /* Since the microschedule is calculated in terms of OTG lines, 11500acc5b06SAnthony Koo * include any scaling factors to make sure when we get accurate 11510acc5b06SAnthony Koo * conversion when programming MALL_START_LINE (which is in terms 11520acc5b06SAnthony Koo * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 11530acc5b06SAnthony Koo * is 1/2 (numerator = 1, denominator = 2). 11540acc5b06SAnthony Koo */ 11550acc5b06SAnthony Koo uint8_t scale_factor_numerator; 11560acc5b06SAnthony Koo uint8_t scale_factor_denominator; 115781f776b6SAnthony Koo uint8_t is_drr; 11581591a647SAnthony Koo uint8_t main_split_pipe_index; 11591591a647SAnthony Koo uint8_t phantom_split_pipe_index; 116085f4bc0cSAlvin Lee } subvp_data; 116185f4bc0cSAlvin Lee 116285f4bc0cSAlvin Lee struct { 116385f4bc0cSAlvin Lee uint32_t pix_clk_100hz; 116485f4bc0cSAlvin Lee uint16_t vblank_start; 116585f4bc0cSAlvin Lee uint16_t vblank_end; 116685f4bc0cSAlvin Lee uint16_t vstartup_start; 116785f4bc0cSAlvin Lee uint16_t vtotal; 116885f4bc0cSAlvin Lee uint16_t htotal; 116985f4bc0cSAlvin Lee uint8_t vblank_pipe_index; 1170ae7169a9SAlvin Lee uint8_t padding[1]; 117185f4bc0cSAlvin Lee struct { 117285f4bc0cSAlvin Lee uint8_t drr_in_use; 117385f4bc0cSAlvin Lee uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 117485f4bc0cSAlvin Lee uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 117585f4bc0cSAlvin Lee uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 117685f4bc0cSAlvin Lee uint8_t use_ramping; // Use ramping or not 1177ae7169a9SAlvin Lee uint8_t drr_vblank_start_margin; 117885f4bc0cSAlvin Lee } drr_info; // DRR considered as part of SubVP + VBLANK case 117985f4bc0cSAlvin Lee } vblank_data; 118085f4bc0cSAlvin Lee } pipe_config; 118185f4bc0cSAlvin Lee 11820acc5b06SAnthony Koo /* - subvp_data in the union (pipe_config) takes up 27 bytes. 11830acc5b06SAnthony Koo * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 11840acc5b06SAnthony Koo * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 11850acc5b06SAnthony Koo */ 11860acc5b06SAnthony Koo uint8_t mode; // enum mclk_switch_mode 118785f4bc0cSAlvin Lee }; 118885f4bc0cSAlvin Lee 118985f4bc0cSAlvin Lee /** 119085f4bc0cSAlvin Lee * Config data for Sub-VP and FPO 119185f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 119285f4bc0cSAlvin Lee * the type name can be updated 119385f4bc0cSAlvin Lee */ 119485f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 119585f4bc0cSAlvin Lee uint16_t watermark_a_cache; 119685f4bc0cSAlvin Lee uint8_t vertical_int_margin_us; 119785f4bc0cSAlvin Lee uint8_t pstate_allow_width_us; 119885f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 119985f4bc0cSAlvin Lee }; 120085f4bc0cSAlvin Lee 120185f4bc0cSAlvin Lee /** 120285f4bc0cSAlvin Lee * DMUB rb command definition for Sub-VP and FPO 120385f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 120485f4bc0cSAlvin Lee * the type name can be updated 120585f4bc0cSAlvin Lee */ 120685f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 120785f4bc0cSAlvin Lee struct dmub_cmd_header header; 120885f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 120985f4bc0cSAlvin Lee }; 121085f4bc0cSAlvin Lee 1211ac2e555eSAurabindo Pillai /** 1212b04cb192SNicholas Kazlauskas * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1213b04cb192SNicholas Kazlauskas */ 1214b04cb192SNicholas Kazlauskas enum dmub_cmd_idle_opt_type { 1215b04cb192SNicholas Kazlauskas /** 1216b04cb192SNicholas Kazlauskas * DCN hardware restore. 1217b04cb192SNicholas Kazlauskas */ 1218b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1219f586fea8SJake Wang 1220f586fea8SJake Wang /** 1221f586fea8SJake Wang * DCN hardware save. 1222f586fea8SJake Wang */ 12239dce8c2aSAnthony Koo DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 12249dce8c2aSAnthony Koo 12259dce8c2aSAnthony Koo /** 12269dce8c2aSAnthony Koo * DCN hardware notify idle. 12279dce8c2aSAnthony Koo */ 12289dce8c2aSAnthony Koo DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1229b04cb192SNicholas Kazlauskas }; 1230b04cb192SNicholas Kazlauskas 1231b04cb192SNicholas Kazlauskas /** 1232b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1233b04cb192SNicholas Kazlauskas */ 1234b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore { 1235b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1236b04cb192SNicholas Kazlauskas }; 1237b04cb192SNicholas Kazlauskas 1238b04cb192SNicholas Kazlauskas /** 12399dce8c2aSAnthony Koo * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 12409dce8c2aSAnthony Koo */ 12419dce8c2aSAnthony Koo struct dmub_dcn_notify_idle_cntl_data { 12429dce8c2aSAnthony Koo uint8_t driver_idle; 12439dce8c2aSAnthony Koo uint8_t pad[1]; 12449dce8c2aSAnthony Koo }; 12459dce8c2aSAnthony Koo 12469dce8c2aSAnthony Koo /** 12479dce8c2aSAnthony Koo * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 12489dce8c2aSAnthony Koo */ 12499dce8c2aSAnthony Koo struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 12509dce8c2aSAnthony Koo struct dmub_cmd_header header; /**< header */ 12519dce8c2aSAnthony Koo struct dmub_dcn_notify_idle_cntl_data cntl_data; 12529dce8c2aSAnthony Koo }; 12539dce8c2aSAnthony Koo 12549dce8c2aSAnthony Koo /** 1255b04cb192SNicholas Kazlauskas * struct dmub_clocks - Clock update notification. 1256b04cb192SNicholas Kazlauskas */ 1257b04cb192SNicholas Kazlauskas struct dmub_clocks { 1258b04cb192SNicholas Kazlauskas uint32_t dispclk_khz; /**< dispclk kHz */ 1259b04cb192SNicholas Kazlauskas uint32_t dppclk_khz; /**< dppclk kHz */ 1260b04cb192SNicholas Kazlauskas uint32_t dcfclk_khz; /**< dcfclk kHz */ 1261b04cb192SNicholas Kazlauskas uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1262b04cb192SNicholas Kazlauskas }; 1263b04cb192SNicholas Kazlauskas 1264b04cb192SNicholas Kazlauskas /** 1265b04cb192SNicholas Kazlauskas * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1266b04cb192SNicholas Kazlauskas */ 1267b04cb192SNicholas Kazlauskas enum dmub_cmd_clk_mgr_type { 1268b04cb192SNicholas Kazlauskas /** 1269b04cb192SNicholas Kazlauskas * Notify DMCUB of clock update. 1270b04cb192SNicholas Kazlauskas */ 1271b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1272b04cb192SNicholas Kazlauskas }; 1273b04cb192SNicholas Kazlauskas 1274b04cb192SNicholas Kazlauskas /** 1275b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1276b04cb192SNicholas Kazlauskas */ 1277b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks { 1278b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1279b04cb192SNicholas Kazlauskas struct dmub_clocks clocks; /**< clock data */ 1280b04cb192SNicholas Kazlauskas }; 12818fe44c08SAlex Deucher 1282592a6318SAnthony Koo /** 1283592a6318SAnthony Koo * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1284592a6318SAnthony Koo */ 12857c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data { 1286592a6318SAnthony Koo union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 12877c008829SNicholas Kazlauskas }; 12887c008829SNicholas Kazlauskas 1289592a6318SAnthony Koo /** 1290592a6318SAnthony Koo * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1291592a6318SAnthony Koo */ 12927c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control { 1293592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1294592a6318SAnthony Koo struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 12957c008829SNicholas Kazlauskas }; 12967c008829SNicholas Kazlauskas 1297592a6318SAnthony Koo /** 1298592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1299592a6318SAnthony Koo */ 13007c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data { 1301592a6318SAnthony Koo struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 13027c008829SNicholas Kazlauskas }; 13037c008829SNicholas Kazlauskas 1304592a6318SAnthony Koo /** 1305592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1306592a6318SAnthony Koo */ 13077c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock { 1308592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1309592a6318SAnthony Koo struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 13107c008829SNicholas Kazlauskas }; 13117c008829SNicholas Kazlauskas 1312592a6318SAnthony Koo /** 1313592a6318SAnthony Koo * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1314592a6318SAnthony Koo */ 13157c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data { 1316592a6318SAnthony Koo struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 13177c008829SNicholas Kazlauskas }; 13187c008829SNicholas Kazlauskas 1319592a6318SAnthony Koo /** 1320592a6318SAnthony Koo * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1321592a6318SAnthony Koo */ 13227c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating { 1323592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1324592a6318SAnthony Koo struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 13257c008829SNicholas Kazlauskas }; 13267c008829SNicholas Kazlauskas 1327592a6318SAnthony Koo /** 1328592a6318SAnthony Koo * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1329592a6318SAnthony Koo */ 1330d448521eSAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 { 1331d448521eSAnthony Koo uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1332d448521eSAnthony Koo uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1333d448521eSAnthony Koo union { 1334d448521eSAnthony Koo uint8_t digmode; /**< enum atom_encode_mode_def */ 1335d448521eSAnthony Koo uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1336d448521eSAnthony Koo } mode_laneset; 1337d448521eSAnthony Koo uint8_t lanenum; /**< Number of lanes */ 1338d448521eSAnthony Koo union { 1339d448521eSAnthony Koo uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1340d448521eSAnthony Koo } symclk_units; 1341d448521eSAnthony Koo uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1342d448521eSAnthony Koo uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1343d448521eSAnthony Koo uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 13445a2730fcSFangzhi Zuo uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1345d448521eSAnthony Koo uint8_t reserved1; /**< For future use */ 1346d448521eSAnthony Koo uint8_t reserved2[3]; /**< For future use */ 1347d448521eSAnthony Koo uint32_t reserved3[11]; /**< For future use */ 1348d448521eSAnthony Koo }; 1349d448521eSAnthony Koo 1350592a6318SAnthony Koo /** 1351592a6318SAnthony Koo * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1352592a6318SAnthony Koo */ 1353d448521eSAnthony Koo union dmub_cmd_dig1_transmitter_control_data { 1354592a6318SAnthony Koo struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1355592a6318SAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 13567c008829SNicholas Kazlauskas }; 13577c008829SNicholas Kazlauskas 1358592a6318SAnthony Koo /** 1359592a6318SAnthony Koo * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1360592a6318SAnthony Koo */ 13617c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control { 1362592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1363592a6318SAnthony Koo union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 13647c008829SNicholas Kazlauskas }; 13657c008829SNicholas Kazlauskas 1366592a6318SAnthony Koo /** 1367e383b127SNicholas Kazlauskas * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1368e383b127SNicholas Kazlauskas */ 1369e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control_data { 1370e383b127SNicholas Kazlauskas uint8_t inst : 6; /**< DOMAIN instance to control */ 1371e383b127SNicholas Kazlauskas uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1372e383b127SNicholas Kazlauskas uint8_t reserved[3]; /**< Reserved for future use */ 1373e383b127SNicholas Kazlauskas }; 1374e383b127SNicholas Kazlauskas 1375e383b127SNicholas Kazlauskas /** 1376e383b127SNicholas Kazlauskas * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1377e383b127SNicholas Kazlauskas */ 1378e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control { 1379e383b127SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1380e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1381e383b127SNicholas Kazlauskas }; 1382e383b127SNicholas Kazlauskas 1383e383b127SNicholas Kazlauskas /** 138476724b76SJimmy Kizito * DPIA tunnel command parameters. 138576724b76SJimmy Kizito */ 138676724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data { 138776724b76SJimmy Kizito uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 138876724b76SJimmy Kizito uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 138976724b76SJimmy Kizito union { 139076724b76SJimmy Kizito uint8_t digmode; /** enum atom_encode_mode_def */ 139176724b76SJimmy Kizito uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 139276724b76SJimmy Kizito } mode_laneset; 139376724b76SJimmy Kizito uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 139476724b76SJimmy Kizito uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 139576724b76SJimmy Kizito uint8_t hpdsel; /** =0: HPD is not assigned */ 139676724b76SJimmy Kizito uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 139776724b76SJimmy Kizito uint8_t dpia_id; /** Index of DPIA */ 139876724b76SJimmy Kizito uint8_t fec_rdy : 1; 139976724b76SJimmy Kizito uint8_t reserved : 7; 140076724b76SJimmy Kizito uint32_t reserved1; 140176724b76SJimmy Kizito }; 140276724b76SJimmy Kizito 140376724b76SJimmy Kizito /** 140476724b76SJimmy Kizito * DMUB command for DPIA tunnel control. 140576724b76SJimmy Kizito */ 140676724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control { 140776724b76SJimmy Kizito struct dmub_cmd_header header; 140876724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data dpia_control; 140976724b76SJimmy Kizito }; 141076724b76SJimmy Kizito 141176724b76SJimmy Kizito /** 141271af9d46SMeenakshikumar Somasundaram * SET_CONFIG Command Payload 141371af9d46SMeenakshikumar Somasundaram */ 141471af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload { 141571af9d46SMeenakshikumar Somasundaram uint8_t msg_type; /* set config message type */ 141671af9d46SMeenakshikumar Somasundaram uint8_t msg_data; /* set config message data */ 141771af9d46SMeenakshikumar Somasundaram }; 141871af9d46SMeenakshikumar Somasundaram 141971af9d46SMeenakshikumar Somasundaram /** 142071af9d46SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 142171af9d46SMeenakshikumar Somasundaram */ 142271af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data { 142371af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload cmd_pkt; 142471af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */ 142571af9d46SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned in case of error */ 142671af9d46SMeenakshikumar Somasundaram }; 142771af9d46SMeenakshikumar Somasundaram 142871af9d46SMeenakshikumar Somasundaram /** 142971af9d46SMeenakshikumar Somasundaram * DMUB command structure for SET_CONFIG command. 143071af9d46SMeenakshikumar Somasundaram */ 143171af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access { 143271af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 143371af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 143471af9d46SMeenakshikumar Somasundaram }; 143571af9d46SMeenakshikumar Somasundaram 143671af9d46SMeenakshikumar Somasundaram /** 1437139a3311SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1438139a3311SMeenakshikumar Somasundaram */ 1439139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data { 1440139a3311SMeenakshikumar Somasundaram uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1441139a3311SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */ 1442139a3311SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1443139a3311SMeenakshikumar Somasundaram uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1444139a3311SMeenakshikumar Somasundaram }; 1445139a3311SMeenakshikumar Somasundaram 1446139a3311SMeenakshikumar Somasundaram /** 1447139a3311SMeenakshikumar Somasundaram * DMUB command structure for SET_ command. 1448139a3311SMeenakshikumar Somasundaram */ 1449139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots { 1450139a3311SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 1451139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1452139a3311SMeenakshikumar Somasundaram }; 1453139a3311SMeenakshikumar Somasundaram 1454139a3311SMeenakshikumar Somasundaram /** 14556f4f8ff5SMeenakshikumar Somasundaram * DMUB command structure for DPIA HPD int enable control. 14566f4f8ff5SMeenakshikumar Somasundaram */ 14576f4f8ff5SMeenakshikumar Somasundaram struct dmub_rb_cmd_dpia_hpd_int_enable { 14586f4f8ff5SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 14596f4f8ff5SMeenakshikumar Somasundaram uint32_t enable; /* dpia hpd interrupt enable */ 14606f4f8ff5SMeenakshikumar Somasundaram }; 14616f4f8ff5SMeenakshikumar Somasundaram 14626f4f8ff5SMeenakshikumar Somasundaram /** 1463592a6318SAnthony Koo * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1464592a6318SAnthony Koo */ 14657c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init { 1466592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1467592a6318SAnthony Koo uint8_t reserved[60]; /**< reserved bits */ 14687c008829SNicholas Kazlauskas }; 14697c008829SNicholas Kazlauskas 14701a595f28SAnthony Koo /** 14711a595f28SAnthony Koo * enum dp_aux_request_action - DP AUX request command listing. 14721a595f28SAnthony Koo * 14731a595f28SAnthony Koo * 4 AUX request command bits are shifted to high nibble. 14741a595f28SAnthony Koo */ 1475d9beecfcSAnthony Koo enum dp_aux_request_action { 14761a595f28SAnthony Koo /** I2C-over-AUX write request */ 1477d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 14781a595f28SAnthony Koo /** I2C-over-AUX read request */ 1479d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ = 0x10, 14801a595f28SAnthony Koo /** I2C-over-AUX write status request */ 1481d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 14821a595f28SAnthony Koo /** I2C-over-AUX write request with MOT=1 */ 1483d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 14841a595f28SAnthony Koo /** I2C-over-AUX read request with MOT=1 */ 1485d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 14861a595f28SAnthony Koo /** I2C-over-AUX write status request with MOT=1 */ 1487d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 14881a595f28SAnthony Koo /** Native AUX write request */ 1489d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 14901a595f28SAnthony Koo /** Native AUX read request */ 1491d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1492d9beecfcSAnthony Koo }; 1493d9beecfcSAnthony Koo 14941a595f28SAnthony Koo /** 14951a595f28SAnthony Koo * enum aux_return_code_type - DP AUX process return code listing. 14961a595f28SAnthony Koo */ 1497fd0f1d21SAnthony Koo enum aux_return_code_type { 14981a595f28SAnthony Koo /** AUX process succeeded */ 1499fd0f1d21SAnthony Koo AUX_RET_SUCCESS = 0, 15001a595f28SAnthony Koo /** AUX process failed with unknown reason */ 1501b6402afeSAnthony Koo AUX_RET_ERROR_UNKNOWN, 15021a595f28SAnthony Koo /** AUX process completed with invalid reply */ 1503b6402afeSAnthony Koo AUX_RET_ERROR_INVALID_REPLY, 15041a595f28SAnthony Koo /** AUX process timed out */ 1505fd0f1d21SAnthony Koo AUX_RET_ERROR_TIMEOUT, 15061a595f28SAnthony Koo /** HPD was low during AUX process */ 1507b6402afeSAnthony Koo AUX_RET_ERROR_HPD_DISCON, 15081a595f28SAnthony Koo /** Failed to acquire AUX engine */ 1509b6402afeSAnthony Koo AUX_RET_ERROR_ENGINE_ACQUIRE, 15101a595f28SAnthony Koo /** AUX request not supported */ 1511fd0f1d21SAnthony Koo AUX_RET_ERROR_INVALID_OPERATION, 15121a595f28SAnthony Koo /** AUX process not available */ 1513fd0f1d21SAnthony Koo AUX_RET_ERROR_PROTOCOL_ERROR, 1514fd0f1d21SAnthony Koo }; 1515fd0f1d21SAnthony Koo 15161a595f28SAnthony Koo /** 15171a595f28SAnthony Koo * enum aux_channel_type - DP AUX channel type listing. 15181a595f28SAnthony Koo */ 1519b6402afeSAnthony Koo enum aux_channel_type { 15201a595f28SAnthony Koo /** AUX thru Legacy DP AUX */ 1521b6402afeSAnthony Koo AUX_CHANNEL_LEGACY_DDC, 15221a595f28SAnthony Koo /** AUX thru DPIA DP tunneling */ 1523b6402afeSAnthony Koo AUX_CHANNEL_DPIA 1524b6402afeSAnthony Koo }; 1525b6402afeSAnthony Koo 15261a595f28SAnthony Koo /** 15271a595f28SAnthony Koo * struct aux_transaction_parameters - DP AUX request transaction data 15281a595f28SAnthony Koo */ 1529d9beecfcSAnthony Koo struct aux_transaction_parameters { 15301a595f28SAnthony Koo uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 15311a595f28SAnthony Koo uint8_t action; /**< enum dp_aux_request_action */ 15321a595f28SAnthony Koo uint8_t length; /**< DP AUX request data length */ 15331a595f28SAnthony Koo uint8_t reserved; /**< For future use */ 15341a595f28SAnthony Koo uint32_t address; /**< DP AUX address */ 15351a595f28SAnthony Koo uint8_t data[16]; /**< DP AUX write data */ 1536d9beecfcSAnthony Koo }; 1537d9beecfcSAnthony Koo 15381a595f28SAnthony Koo /** 15391a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 15401a595f28SAnthony Koo */ 1541d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data { 15421a595f28SAnthony Koo uint8_t instance; /**< AUX instance or DPIA instance */ 15431a595f28SAnthony Koo uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 15441a595f28SAnthony Koo uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 15451a595f28SAnthony Koo uint8_t reserved0; /**< For future use */ 15461a595f28SAnthony Koo uint16_t timeout; /**< timeout time in us */ 15471a595f28SAnthony Koo uint16_t reserved1; /**< For future use */ 15481a595f28SAnthony Koo enum aux_channel_type type; /**< enum aux_channel_type */ 15491a595f28SAnthony Koo struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1550d9beecfcSAnthony Koo }; 1551d9beecfcSAnthony Koo 15521a595f28SAnthony Koo /** 15531a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 15541a595f28SAnthony Koo */ 1555d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access { 15561a595f28SAnthony Koo /** 15571a595f28SAnthony Koo * Command header. 15581a595f28SAnthony Koo */ 1559d9beecfcSAnthony Koo struct dmub_cmd_header header; 15601a595f28SAnthony Koo /** 15611a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 15621a595f28SAnthony Koo */ 1563d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data aux_control; 1564d9beecfcSAnthony Koo }; 1565d9beecfcSAnthony Koo 15661a595f28SAnthony Koo /** 15671a595f28SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 15681a595f28SAnthony Koo */ 1569d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable { 15701a595f28SAnthony Koo /** 15711a595f28SAnthony Koo * Command header. 15721a595f28SAnthony Koo */ 1573d9beecfcSAnthony Koo struct dmub_cmd_header header; 15741a595f28SAnthony Koo /** 15751a595f28SAnthony Koo * enable: 0x0 -> disable outbox1 notification (default value) 15761a595f28SAnthony Koo * 0x1 -> enable outbox1 notification 15771a595f28SAnthony Koo */ 1578d9beecfcSAnthony Koo uint32_t enable; 1579d9beecfcSAnthony Koo }; 1580d9beecfcSAnthony Koo 1581d9beecfcSAnthony Koo /* DP AUX Reply command - OutBox Cmd */ 15821a595f28SAnthony Koo /** 15831a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 15841a595f28SAnthony Koo */ 1585d9beecfcSAnthony Koo struct aux_reply_data { 15861a595f28SAnthony Koo /** 15871a595f28SAnthony Koo * Aux cmd 15881a595f28SAnthony Koo */ 1589d9beecfcSAnthony Koo uint8_t command; 15901a595f28SAnthony Koo /** 15911a595f28SAnthony Koo * Aux reply data length (max: 16 bytes) 15921a595f28SAnthony Koo */ 1593d9beecfcSAnthony Koo uint8_t length; 15941a595f28SAnthony Koo /** 15951a595f28SAnthony Koo * Alignment only 15961a595f28SAnthony Koo */ 1597d9beecfcSAnthony Koo uint8_t pad[2]; 15981a595f28SAnthony Koo /** 15991a595f28SAnthony Koo * Aux reply data 16001a595f28SAnthony Koo */ 1601d9beecfcSAnthony Koo uint8_t data[16]; 1602d9beecfcSAnthony Koo }; 1603d9beecfcSAnthony Koo 16041a595f28SAnthony Koo /** 16051a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 16061a595f28SAnthony Koo */ 1607d9beecfcSAnthony Koo struct aux_reply_control_data { 16081a595f28SAnthony Koo /** 16091a595f28SAnthony Koo * Reserved for future use 16101a595f28SAnthony Koo */ 1611d9beecfcSAnthony Koo uint32_t handle; 16121a595f28SAnthony Koo /** 16131a595f28SAnthony Koo * Aux Instance 16141a595f28SAnthony Koo */ 1615b6402afeSAnthony Koo uint8_t instance; 16161a595f28SAnthony Koo /** 16171a595f28SAnthony Koo * Aux transaction result: definition in enum aux_return_code_type 16181a595f28SAnthony Koo */ 1619d9beecfcSAnthony Koo uint8_t result; 16201a595f28SAnthony Koo /** 16211a595f28SAnthony Koo * Alignment only 16221a595f28SAnthony Koo */ 1623d9beecfcSAnthony Koo uint16_t pad; 1624d9beecfcSAnthony Koo }; 1625d9beecfcSAnthony Koo 16261a595f28SAnthony Koo /** 16271a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 16281a595f28SAnthony Koo */ 1629d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply { 16301a595f28SAnthony Koo /** 16311a595f28SAnthony Koo * Command header. 16321a595f28SAnthony Koo */ 1633d9beecfcSAnthony Koo struct dmub_cmd_header header; 16341a595f28SAnthony Koo /** 16351a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 16361a595f28SAnthony Koo */ 1637d9beecfcSAnthony Koo struct aux_reply_control_data control; 16381a595f28SAnthony Koo /** 16391a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 16401a595f28SAnthony Koo */ 1641d9beecfcSAnthony Koo struct aux_reply_data reply_data; 1642d9beecfcSAnthony Koo }; 1643d9beecfcSAnthony Koo 1644fd0f1d21SAnthony Koo /* DP HPD Notify command - OutBox Cmd */ 16451a595f28SAnthony Koo /** 16461a595f28SAnthony Koo * DP HPD Type 16471a595f28SAnthony Koo */ 1648fd0f1d21SAnthony Koo enum dp_hpd_type { 16491a595f28SAnthony Koo /** 16501a595f28SAnthony Koo * Normal DP HPD 16511a595f28SAnthony Koo */ 1652fd0f1d21SAnthony Koo DP_HPD = 0, 16531a595f28SAnthony Koo /** 16541a595f28SAnthony Koo * DP HPD short pulse 16551a595f28SAnthony Koo */ 1656fd0f1d21SAnthony Koo DP_IRQ 1657fd0f1d21SAnthony Koo }; 1658fd0f1d21SAnthony Koo 16591a595f28SAnthony Koo /** 16601a595f28SAnthony Koo * DP HPD Status 16611a595f28SAnthony Koo */ 1662fd0f1d21SAnthony Koo enum dp_hpd_status { 16631a595f28SAnthony Koo /** 16641a595f28SAnthony Koo * DP_HPD status low 16651a595f28SAnthony Koo */ 1666fd0f1d21SAnthony Koo DP_HPD_UNPLUG = 0, 16671a595f28SAnthony Koo /** 16681a595f28SAnthony Koo * DP_HPD status high 16691a595f28SAnthony Koo */ 1670fd0f1d21SAnthony Koo DP_HPD_PLUG 1671fd0f1d21SAnthony Koo }; 1672fd0f1d21SAnthony Koo 16731a595f28SAnthony Koo /** 16741a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 16751a595f28SAnthony Koo */ 1676d9beecfcSAnthony Koo struct dp_hpd_data { 16771a595f28SAnthony Koo /** 16781a595f28SAnthony Koo * DP HPD instance 16791a595f28SAnthony Koo */ 1680b6402afeSAnthony Koo uint8_t instance; 16811a595f28SAnthony Koo /** 16821a595f28SAnthony Koo * HPD type 16831a595f28SAnthony Koo */ 1684d9beecfcSAnthony Koo uint8_t hpd_type; 16851a595f28SAnthony Koo /** 16861a595f28SAnthony Koo * HPD status: only for type: DP_HPD to indicate status 16871a595f28SAnthony Koo */ 1688d9beecfcSAnthony Koo uint8_t hpd_status; 16891a595f28SAnthony Koo /** 16901a595f28SAnthony Koo * Alignment only 16911a595f28SAnthony Koo */ 1692d9beecfcSAnthony Koo uint8_t pad; 1693d9beecfcSAnthony Koo }; 1694d9beecfcSAnthony Koo 16951a595f28SAnthony Koo /** 16961a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 16971a595f28SAnthony Koo */ 1698d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify { 16991a595f28SAnthony Koo /** 17001a595f28SAnthony Koo * Command header. 17011a595f28SAnthony Koo */ 1702d9beecfcSAnthony Koo struct dmub_cmd_header header; 17031a595f28SAnthony Koo /** 17041a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 17051a595f28SAnthony Koo */ 1706d9beecfcSAnthony Koo struct dp_hpd_data hpd_data; 1707d9beecfcSAnthony Koo }; 1708d9beecfcSAnthony Koo 170971af9d46SMeenakshikumar Somasundaram /** 171071af9d46SMeenakshikumar Somasundaram * Definition of a SET_CONFIG reply from DPOA. 171171af9d46SMeenakshikumar Somasundaram */ 171271af9d46SMeenakshikumar Somasundaram enum set_config_status { 171371af9d46SMeenakshikumar Somasundaram SET_CONFIG_PENDING = 0, 171471af9d46SMeenakshikumar Somasundaram SET_CONFIG_ACK_RECEIVED, 171571af9d46SMeenakshikumar Somasundaram SET_CONFIG_RX_TIMEOUT, 171671af9d46SMeenakshikumar Somasundaram SET_CONFIG_UNKNOWN_ERROR, 171771af9d46SMeenakshikumar Somasundaram }; 171871af9d46SMeenakshikumar Somasundaram 171971af9d46SMeenakshikumar Somasundaram /** 172071af9d46SMeenakshikumar Somasundaram * Definition of a set_config reply 172171af9d46SMeenakshikumar Somasundaram */ 172271af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data { 172371af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA Instance */ 172471af9d46SMeenakshikumar Somasundaram uint8_t status; /* Set Config reply */ 172571af9d46SMeenakshikumar Somasundaram uint16_t pad; /* Alignment */ 172671af9d46SMeenakshikumar Somasundaram }; 172771af9d46SMeenakshikumar Somasundaram 172871af9d46SMeenakshikumar Somasundaram /** 172971af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 173071af9d46SMeenakshikumar Somasundaram */ 173171af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply { 173271af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; 173371af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data set_config_reply_control; 173471af9d46SMeenakshikumar Somasundaram }; 173571af9d46SMeenakshikumar Somasundaram 1736ea5a4db9SAnthony Koo /** 17378af54c61SMustapha Ghaddar * Definition of a DPIA notification header 17388af54c61SMustapha Ghaddar */ 17398af54c61SMustapha Ghaddar struct dpia_notification_header { 17408af54c61SMustapha Ghaddar uint8_t instance; /**< DPIA Instance */ 17418af54c61SMustapha Ghaddar uint8_t reserved[3]; 17428af54c61SMustapha Ghaddar enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 17438af54c61SMustapha Ghaddar }; 17448af54c61SMustapha Ghaddar 17458af54c61SMustapha Ghaddar /** 17468af54c61SMustapha Ghaddar * Definition of the common data struct of DPIA notification 17478af54c61SMustapha Ghaddar */ 17488af54c61SMustapha Ghaddar struct dpia_notification_common { 17498af54c61SMustapha Ghaddar uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 17508af54c61SMustapha Ghaddar - sizeof(struct dpia_notification_header)]; 17518af54c61SMustapha Ghaddar }; 17528af54c61SMustapha Ghaddar 17538af54c61SMustapha Ghaddar /** 17548af54c61SMustapha Ghaddar * Definition of a DPIA notification data 17558af54c61SMustapha Ghaddar */ 17568af54c61SMustapha Ghaddar struct dpia_bw_allocation_notify_data { 17578af54c61SMustapha Ghaddar union { 17588af54c61SMustapha Ghaddar struct { 17598af54c61SMustapha Ghaddar uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 17608af54c61SMustapha Ghaddar uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 17618af54c61SMustapha Ghaddar uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 17628af54c61SMustapha Ghaddar uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 17638af54c61SMustapha Ghaddar uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 17648af54c61SMustapha Ghaddar uint16_t reserved: 11; /**< Reserved */ 17658af54c61SMustapha Ghaddar } bits; 17668af54c61SMustapha Ghaddar 17678af54c61SMustapha Ghaddar uint16_t flags; 17688af54c61SMustapha Ghaddar }; 17698af54c61SMustapha Ghaddar 17708af54c61SMustapha Ghaddar uint8_t cm_id; /**< CM ID */ 17718af54c61SMustapha Ghaddar uint8_t group_id; /**< Group ID */ 17728af54c61SMustapha Ghaddar uint8_t granularity; /**< BW Allocation Granularity */ 17738af54c61SMustapha Ghaddar uint8_t estimated_bw; /**< Estimated_BW */ 17748af54c61SMustapha Ghaddar uint8_t allocated_bw; /**< Allocated_BW */ 17758af54c61SMustapha Ghaddar uint8_t reserved; 17768af54c61SMustapha Ghaddar }; 17778af54c61SMustapha Ghaddar 17788af54c61SMustapha Ghaddar /** 17798af54c61SMustapha Ghaddar * union dpia_notify_data_type - DPIA Notification in Outbox command 17808af54c61SMustapha Ghaddar */ 17818af54c61SMustapha Ghaddar union dpia_notification_data { 17828af54c61SMustapha Ghaddar /** 17838af54c61SMustapha Ghaddar * DPIA Notification for common data struct 17848af54c61SMustapha Ghaddar */ 17858af54c61SMustapha Ghaddar struct dpia_notification_common common_data; 17868af54c61SMustapha Ghaddar 17878af54c61SMustapha Ghaddar /** 17888af54c61SMustapha Ghaddar * DPIA Notification for DP BW Allocation support 17898af54c61SMustapha Ghaddar */ 17908af54c61SMustapha Ghaddar struct dpia_bw_allocation_notify_data dpia_bw_alloc; 17918af54c61SMustapha Ghaddar }; 17928af54c61SMustapha Ghaddar 17938af54c61SMustapha Ghaddar /** 17948af54c61SMustapha Ghaddar * Definition of a DPIA notification payload 17958af54c61SMustapha Ghaddar */ 17968af54c61SMustapha Ghaddar struct dpia_notification_payload { 17978af54c61SMustapha Ghaddar struct dpia_notification_header header; 17988af54c61SMustapha Ghaddar union dpia_notification_data data; /**< DPIA notification payload data */ 17998af54c61SMustapha Ghaddar }; 18008af54c61SMustapha Ghaddar 18018af54c61SMustapha Ghaddar /** 18028af54c61SMustapha Ghaddar * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 18038af54c61SMustapha Ghaddar */ 18048af54c61SMustapha Ghaddar struct dmub_rb_cmd_dpia_notification { 18058af54c61SMustapha Ghaddar struct dmub_cmd_header header; /**< DPIA notification header */ 18068af54c61SMustapha Ghaddar struct dpia_notification_payload payload; /**< DPIA notification payload */ 18078af54c61SMustapha Ghaddar }; 18088af54c61SMustapha Ghaddar 18098af54c61SMustapha Ghaddar /** 1810ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1811ea5a4db9SAnthony Koo */ 1812ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data { 1813ea5a4db9SAnthony Koo uint8_t instance; /**< HPD instance or DPIA instance */ 1814ea5a4db9SAnthony Koo uint8_t result; /**< For returning HPD state */ 1815874714feSAnthony Koo uint16_t pad; /** < Alignment */ 1816ea5a4db9SAnthony Koo enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1817ea5a4db9SAnthony Koo enum aux_return_code_type status; /**< for returning the status of command */ 1818ea5a4db9SAnthony Koo }; 1819ea5a4db9SAnthony Koo 1820ea5a4db9SAnthony Koo /** 1821ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1822ea5a4db9SAnthony Koo */ 1823ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state { 1824ea5a4db9SAnthony Koo /** 1825ea5a4db9SAnthony Koo * Command header. 1826ea5a4db9SAnthony Koo */ 1827ea5a4db9SAnthony Koo struct dmub_cmd_header header; 1828ea5a4db9SAnthony Koo /** 1829ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1830ea5a4db9SAnthony Koo */ 1831ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data data; 1832ea5a4db9SAnthony Koo }; 1833ea5a4db9SAnthony Koo 183484034ad4SAnthony Koo /* 183584034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 183684034ad4SAnthony Koo * Do not reuse or modify IDs. 183784034ad4SAnthony Koo */ 183884034ad4SAnthony Koo 18391a595f28SAnthony Koo /** 18401a595f28SAnthony Koo * PSR command sub-types. 18411a595f28SAnthony Koo */ 184284034ad4SAnthony Koo enum dmub_cmd_psr_type { 18431a595f28SAnthony Koo /** 18441a595f28SAnthony Koo * Set PSR version support. 18451a595f28SAnthony Koo */ 184684034ad4SAnthony Koo DMUB_CMD__PSR_SET_VERSION = 0, 18471a595f28SAnthony Koo /** 18481a595f28SAnthony Koo * Copy driver-calculated parameters to PSR state. 18491a595f28SAnthony Koo */ 185084034ad4SAnthony Koo DMUB_CMD__PSR_COPY_SETTINGS = 1, 18511a595f28SAnthony Koo /** 18521a595f28SAnthony Koo * Enable PSR. 18531a595f28SAnthony Koo */ 185484034ad4SAnthony Koo DMUB_CMD__PSR_ENABLE = 2, 18551a595f28SAnthony Koo 18561a595f28SAnthony Koo /** 18571a595f28SAnthony Koo * Disable PSR. 18581a595f28SAnthony Koo */ 185984034ad4SAnthony Koo DMUB_CMD__PSR_DISABLE = 3, 18601a595f28SAnthony Koo 18611a595f28SAnthony Koo /** 18621a595f28SAnthony Koo * Set PSR level. 18631a595f28SAnthony Koo * PSR level is a 16-bit value dicated by driver that 18641a595f28SAnthony Koo * will enable/disable different functionality. 18651a595f28SAnthony Koo */ 186684034ad4SAnthony Koo DMUB_CMD__PSR_SET_LEVEL = 4, 18671a595f28SAnthony Koo 18681a595f28SAnthony Koo /** 18691a595f28SAnthony Koo * Forces PSR enabled until an explicit PSR disable call. 18701a595f28SAnthony Koo */ 1871672251b2SAnthony Koo DMUB_CMD__PSR_FORCE_STATIC = 5, 1872e5dfcd27SRobin Chen /** 187383eb5385SDavid Zhang * Set vtotal in psr active for FreeSync PSR. 187483eb5385SDavid Zhang */ 187583eb5385SDavid Zhang DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 187683eb5385SDavid Zhang /** 1877e5dfcd27SRobin Chen * Set PSR power option 1878e5dfcd27SRobin Chen */ 1879e5dfcd27SRobin Chen DMUB_CMD__SET_PSR_POWER_OPT = 7, 188084034ad4SAnthony Koo }; 188184034ad4SAnthony Koo 188285f4bc0cSAlvin Lee enum dmub_cmd_fams_type { 188385f4bc0cSAlvin Lee DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 188485f4bc0cSAlvin Lee DMUB_CMD__FAMS_DRR_UPDATE = 1, 188585f4bc0cSAlvin Lee DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 188681f776b6SAnthony Koo /** 188781f776b6SAnthony Koo * For SubVP set manual trigger in FW because it 188881f776b6SAnthony Koo * triggers DRR_UPDATE_PENDING which SubVP relies 188981f776b6SAnthony Koo * on (for any SubVP cases that use a DRR display) 189081f776b6SAnthony Koo */ 189181f776b6SAnthony Koo DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 189285f4bc0cSAlvin Lee }; 189385f4bc0cSAlvin Lee 18941a595f28SAnthony Koo /** 18951a595f28SAnthony Koo * PSR versions. 18961a595f28SAnthony Koo */ 189784034ad4SAnthony Koo enum psr_version { 18981a595f28SAnthony Koo /** 18991a595f28SAnthony Koo * PSR version 1. 19001a595f28SAnthony Koo */ 190184034ad4SAnthony Koo PSR_VERSION_1 = 0, 19021a595f28SAnthony Koo /** 190383eb5385SDavid Zhang * Freesync PSR SU. 190483eb5385SDavid Zhang */ 190583eb5385SDavid Zhang PSR_VERSION_SU_1 = 1, 190683eb5385SDavid Zhang /** 19071a595f28SAnthony Koo * PSR not supported. 19081a595f28SAnthony Koo */ 190984034ad4SAnthony Koo PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 191084034ad4SAnthony Koo }; 191184034ad4SAnthony Koo 1912592a6318SAnthony Koo /** 1913592a6318SAnthony Koo * enum dmub_cmd_mall_type - MALL commands 1914592a6318SAnthony Koo */ 191552f2e83eSBhawanpreet Lakha enum dmub_cmd_mall_type { 1916592a6318SAnthony Koo /** 1917592a6318SAnthony Koo * Allows display refresh from MALL. 1918592a6318SAnthony Koo */ 191952f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_ALLOW = 0, 1920592a6318SAnthony Koo /** 1921592a6318SAnthony Koo * Disallows display refresh from MALL. 1922592a6318SAnthony Koo */ 192352f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1924592a6318SAnthony Koo /** 1925592a6318SAnthony Koo * Cursor copy for MALL. 1926592a6318SAnthony Koo */ 192752f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1928592a6318SAnthony Koo /** 1929592a6318SAnthony Koo * Controls DF requests. 1930592a6318SAnthony Koo */ 1931ea7154d8SBhawanpreet Lakha DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 193252f2e83eSBhawanpreet Lakha }; 193352f2e83eSBhawanpreet Lakha 1934a91b402dSCharlene Liu /** 193578174f47SAnthony Koo * PHY Link rate for DP. 193678174f47SAnthony Koo */ 193778174f47SAnthony Koo enum phy_link_rate { 193878174f47SAnthony Koo /** 193978174f47SAnthony Koo * not supported. 194078174f47SAnthony Koo */ 194178174f47SAnthony Koo PHY_RATE_UNKNOWN = 0, 194278174f47SAnthony Koo /** 194378174f47SAnthony Koo * Rate_1 (RBR) - 1.62 Gbps/Lane 194478174f47SAnthony Koo */ 194578174f47SAnthony Koo PHY_RATE_162 = 1, 194678174f47SAnthony Koo /** 194778174f47SAnthony Koo * Rate_2 - 2.16 Gbps/Lane 194878174f47SAnthony Koo */ 194978174f47SAnthony Koo PHY_RATE_216 = 2, 195078174f47SAnthony Koo /** 195178174f47SAnthony Koo * Rate_3 - 2.43 Gbps/Lane 195278174f47SAnthony Koo */ 195378174f47SAnthony Koo PHY_RATE_243 = 3, 195478174f47SAnthony Koo /** 195578174f47SAnthony Koo * Rate_4 (HBR) - 2.70 Gbps/Lane 195678174f47SAnthony Koo */ 195778174f47SAnthony Koo PHY_RATE_270 = 4, 195878174f47SAnthony Koo /** 195978174f47SAnthony Koo * Rate_5 (RBR2)- 3.24 Gbps/Lane 196078174f47SAnthony Koo */ 196178174f47SAnthony Koo PHY_RATE_324 = 5, 196278174f47SAnthony Koo /** 196378174f47SAnthony Koo * Rate_6 - 4.32 Gbps/Lane 196478174f47SAnthony Koo */ 196578174f47SAnthony Koo PHY_RATE_432 = 6, 196678174f47SAnthony Koo /** 196778174f47SAnthony Koo * Rate_7 (HBR2)- 5.40 Gbps/Lane 196878174f47SAnthony Koo */ 196978174f47SAnthony Koo PHY_RATE_540 = 7, 197078174f47SAnthony Koo /** 197178174f47SAnthony Koo * Rate_8 (HBR3)- 8.10 Gbps/Lane 197278174f47SAnthony Koo */ 197378174f47SAnthony Koo PHY_RATE_810 = 8, 197478174f47SAnthony Koo /** 197578174f47SAnthony Koo * UHBR10 - 10.0 Gbps/Lane 197678174f47SAnthony Koo */ 197778174f47SAnthony Koo PHY_RATE_1000 = 9, 197878174f47SAnthony Koo /** 197978174f47SAnthony Koo * UHBR13.5 - 13.5 Gbps/Lane 198078174f47SAnthony Koo */ 198178174f47SAnthony Koo PHY_RATE_1350 = 10, 198278174f47SAnthony Koo /** 198378174f47SAnthony Koo * UHBR10 - 20.0 Gbps/Lane 198478174f47SAnthony Koo */ 198578174f47SAnthony Koo PHY_RATE_2000 = 11, 198678174f47SAnthony Koo }; 198778174f47SAnthony Koo 198878174f47SAnthony Koo /** 198978174f47SAnthony Koo * enum dmub_phy_fsm_state - PHY FSM states. 199078174f47SAnthony Koo * PHY FSM state to transit to during PSR enable/disable. 199178174f47SAnthony Koo */ 199278174f47SAnthony Koo enum dmub_phy_fsm_state { 199378174f47SAnthony Koo DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 199478174f47SAnthony Koo DMUB_PHY_FSM_RESET, 199578174f47SAnthony Koo DMUB_PHY_FSM_RESET_RELEASED, 199678174f47SAnthony Koo DMUB_PHY_FSM_SRAM_LOAD_DONE, 199778174f47SAnthony Koo DMUB_PHY_FSM_INITIALIZED, 199878174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED, 199978174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_LP, 200078174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_PG, 200178174f47SAnthony Koo DMUB_PHY_FSM_POWER_DOWN, 200278174f47SAnthony Koo DMUB_PHY_FSM_PLL_EN, 200378174f47SAnthony Koo DMUB_PHY_FSM_TX_EN, 200478174f47SAnthony Koo DMUB_PHY_FSM_FAST_LP, 200578174f47SAnthony Koo }; 200678174f47SAnthony Koo 200778174f47SAnthony Koo /** 20081a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 20091a595f28SAnthony Koo */ 20107c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data { 20111a595f28SAnthony Koo /** 20121a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 20131a595f28SAnthony Koo */ 20147b8a6362SAnthony Koo union dmub_psr_debug_flags debug; 20151a595f28SAnthony Koo /** 20161a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 20171a595f28SAnthony Koo */ 20184c1a1335SWyatt Wood uint16_t psr_level; 20191a595f28SAnthony Koo /** 20201a595f28SAnthony Koo * DPP HW instance. 20211a595f28SAnthony Koo */ 20224c1a1335SWyatt Wood uint8_t dpp_inst; 20231a595f28SAnthony Koo /** 20241a595f28SAnthony Koo * MPCC HW instance. 20251a595f28SAnthony Koo * Not used in dmub fw, 202634ba432cSAnthony Koo * dmub fw will get active opp by reading odm registers. 202734ba432cSAnthony Koo */ 20284c1a1335SWyatt Wood uint8_t mpcc_inst; 20291a595f28SAnthony Koo /** 20301a595f28SAnthony Koo * OPP HW instance. 20311a595f28SAnthony Koo * Not used in dmub fw, 20321a595f28SAnthony Koo * dmub fw will get active opp by reading odm registers. 20331a595f28SAnthony Koo */ 20344c1a1335SWyatt Wood uint8_t opp_inst; 20351a595f28SAnthony Koo /** 20361a595f28SAnthony Koo * OTG HW instance. 20371a595f28SAnthony Koo */ 20384c1a1335SWyatt Wood uint8_t otg_inst; 20391a595f28SAnthony Koo /** 20401a595f28SAnthony Koo * DIG FE HW instance. 20411a595f28SAnthony Koo */ 20424c1a1335SWyatt Wood uint8_t digfe_inst; 20431a595f28SAnthony Koo /** 20441a595f28SAnthony Koo * DIG BE HW instance. 20451a595f28SAnthony Koo */ 20464c1a1335SWyatt Wood uint8_t digbe_inst; 20471a595f28SAnthony Koo /** 20481a595f28SAnthony Koo * DP PHY HW instance. 20491a595f28SAnthony Koo */ 20504c1a1335SWyatt Wood uint8_t dpphy_inst; 20511a595f28SAnthony Koo /** 20521a595f28SAnthony Koo * AUX HW instance. 20531a595f28SAnthony Koo */ 20544c1a1335SWyatt Wood uint8_t aux_inst; 20551a595f28SAnthony Koo /** 20561a595f28SAnthony Koo * Determines if SMU optimzations are enabled/disabled. 20571a595f28SAnthony Koo */ 20584c1a1335SWyatt Wood uint8_t smu_optimizations_en; 20591a595f28SAnthony Koo /** 20601a595f28SAnthony Koo * Unused. 20611a595f28SAnthony Koo * TODO: Remove. 20621a595f28SAnthony Koo */ 20634c1a1335SWyatt Wood uint8_t frame_delay; 20641a595f28SAnthony Koo /** 20651a595f28SAnthony Koo * If RFB setup time is greater than the total VBLANK time, 20661a595f28SAnthony Koo * it is not possible for the sink to capture the video frame 20671a595f28SAnthony Koo * in the same frame the SDP is sent. In this case, 20681a595f28SAnthony Koo * the frame capture indication bit should be set and an extra 20691a595f28SAnthony Koo * static frame should be transmitted to the sink. 20701a595f28SAnthony Koo */ 20714c1a1335SWyatt Wood uint8_t frame_cap_ind; 20721a595f28SAnthony Koo /** 207383eb5385SDavid Zhang * Granularity of Y offset supported by sink. 20741a595f28SAnthony Koo */ 207583eb5385SDavid Zhang uint8_t su_y_granularity; 207683eb5385SDavid Zhang /** 207783eb5385SDavid Zhang * Indicates whether sink should start capturing 207883eb5385SDavid Zhang * immediately following active scan line, 207983eb5385SDavid Zhang * or starting with the 2nd active scan line. 208083eb5385SDavid Zhang */ 208183eb5385SDavid Zhang uint8_t line_capture_indication; 20821a595f28SAnthony Koo /** 20831a595f28SAnthony Koo * Multi-display optimizations are implemented on certain ASICs. 20841a595f28SAnthony Koo */ 2085175f0971SYongqiang Sun uint8_t multi_disp_optimizations_en; 20861a595f28SAnthony Koo /** 20871a595f28SAnthony Koo * The last possible line SDP may be transmitted without violating 20881a595f28SAnthony Koo * the RFB setup time or entering the active video frame. 20891a595f28SAnthony Koo */ 209078ead771SAnthony Koo uint16_t init_sdp_deadline; 20911a595f28SAnthony Koo /** 209283eb5385SDavid Zhang * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 20931a595f28SAnthony Koo */ 209483eb5385SDavid Zhang uint8_t rate_control_caps ; 209583eb5385SDavid Zhang /* 209683eb5385SDavid Zhang * Force PSRSU always doing full frame update 209783eb5385SDavid Zhang */ 209883eb5385SDavid Zhang uint8_t force_ffu_mode; 20991a595f28SAnthony Koo /** 21001a595f28SAnthony Koo * Length of each horizontal line in us. 21011a595f28SAnthony Koo */ 21029b56f6bcSAnthony Koo uint32_t line_time_in_us; 2103ecc11601SAnthony Koo /** 2104ecc11601SAnthony Koo * FEC enable status in driver 2105ecc11601SAnthony Koo */ 2106ecc11601SAnthony Koo uint8_t fec_enable_status; 2107ecc11601SAnthony Koo /** 2108ecc11601SAnthony Koo * FEC re-enable delay when PSR exit. 2109ecc11601SAnthony Koo * unit is 100us, range form 0~255(0xFF). 2110ecc11601SAnthony Koo */ 2111ecc11601SAnthony Koo uint8_t fec_enable_delay_in100us; 2112ecc11601SAnthony Koo /** 2113f56c837aSMikita Lipski * PSR control version. 2114ecc11601SAnthony Koo */ 2115f56c837aSMikita Lipski uint8_t cmd_version; 2116f56c837aSMikita Lipski /** 2117f56c837aSMikita Lipski * Panel Instance. 211836e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2119f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2120f56c837aSMikita Lipski */ 2121f56c837aSMikita Lipski uint8_t panel_inst; 21222665f63aSMikita Lipski /* 21232665f63aSMikita Lipski * DSC enable status in driver 2124360d1b65SIan Chen */ 21252665f63aSMikita Lipski uint8_t dsc_enable_status; 2126b5175966SShah Dharati /* 2127b5175966SShah Dharati * Use FSM state for PSR power up/down 21282665f63aSMikita Lipski */ 2129b5175966SShah Dharati uint8_t use_phy_fsm; 2130b5175966SShah Dharati /** 21311a2b886bSRyan Lin * frame delay for frame re-lock 21321a2b886bSRyan Lin */ 21331a2b886bSRyan Lin uint8_t relock_delay_frame_cnt; 21341a2b886bSRyan Lin /** 2135b5175966SShah Dharati * Explicit padding to 2 byte boundary. 2136b5175966SShah Dharati */ 21371a2b886bSRyan Lin uint8_t pad3; 2138c84ff24aSRobin Chen /** 2139c84ff24aSRobin Chen * DSC Slice height. 2140c84ff24aSRobin Chen */ 2141c84ff24aSRobin Chen uint16_t dsc_slice_height; 2142c84ff24aSRobin Chen /** 2143c84ff24aSRobin Chen * Explicit padding to 4 byte boundary. 2144c84ff24aSRobin Chen */ 2145c84ff24aSRobin Chen uint16_t pad; 21467c008829SNicholas Kazlauskas }; 21477c008829SNicholas Kazlauskas 21481a595f28SAnthony Koo /** 21491a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 21501a595f28SAnthony Koo */ 21517c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings { 21521a595f28SAnthony Koo /** 21531a595f28SAnthony Koo * Command header. 21541a595f28SAnthony Koo */ 21557c008829SNicholas Kazlauskas struct dmub_cmd_header header; 21561a595f28SAnthony Koo /** 21571a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 21581a595f28SAnthony Koo */ 21597c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 21607c008829SNicholas Kazlauskas }; 21617c008829SNicholas Kazlauskas 21621a595f28SAnthony Koo /** 21631a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 21641a595f28SAnthony Koo */ 21657c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data { 21661a595f28SAnthony Koo /** 21671a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 21681a595f28SAnthony Koo */ 21697c008829SNicholas Kazlauskas uint16_t psr_level; 21701a595f28SAnthony Koo /** 2171f56c837aSMikita Lipski * PSR control version. 21721a595f28SAnthony Koo */ 2173f56c837aSMikita Lipski uint8_t cmd_version; 2174f56c837aSMikita Lipski /** 2175f56c837aSMikita Lipski * Panel Instance. 217636e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2177f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2178f56c837aSMikita Lipski */ 2179f56c837aSMikita Lipski uint8_t panel_inst; 21807c008829SNicholas Kazlauskas }; 21817c008829SNicholas Kazlauskas 21821a595f28SAnthony Koo /** 21831a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 21841a595f28SAnthony Koo */ 21857c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level { 21861a595f28SAnthony Koo /** 21871a595f28SAnthony Koo * Command header. 21881a595f28SAnthony Koo */ 21897c008829SNicholas Kazlauskas struct dmub_cmd_header header; 21901a595f28SAnthony Koo /** 21911a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 21921a595f28SAnthony Koo */ 21937c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data psr_set_level_data; 21947c008829SNicholas Kazlauskas }; 21957c008829SNicholas Kazlauskas 2196f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data { 2197f56c837aSMikita Lipski /** 2198f56c837aSMikita Lipski * PSR control version. 2199f56c837aSMikita Lipski */ 2200f56c837aSMikita Lipski uint8_t cmd_version; 2201f56c837aSMikita Lipski /** 2202f56c837aSMikita Lipski * Panel Instance. 220336e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2204f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2205f56c837aSMikita Lipski */ 2206f56c837aSMikita Lipski uint8_t panel_inst; 2207f56c837aSMikita Lipski /** 220878174f47SAnthony Koo * Phy state to enter. 220978174f47SAnthony Koo * Values to use are defined in dmub_phy_fsm_state 2210f56c837aSMikita Lipski */ 221178174f47SAnthony Koo uint8_t phy_fsm_state; 221278174f47SAnthony Koo /** 221378174f47SAnthony Koo * Phy rate for DP - RBR/HBR/HBR2/HBR3. 221478174f47SAnthony Koo * Set this using enum phy_link_rate. 221578174f47SAnthony Koo * This does not support HDMI/DP2 for now. 221678174f47SAnthony Koo */ 221778174f47SAnthony Koo uint8_t phy_rate; 2218f56c837aSMikita Lipski }; 2219f56c837aSMikita Lipski 22201a595f28SAnthony Koo /** 22211a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 22221a595f28SAnthony Koo * PSR enable/disable is controlled using the sub_type. 22231a595f28SAnthony Koo */ 22247c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_enable { 22251a595f28SAnthony Koo /** 22261a595f28SAnthony Koo * Command header. 22271a595f28SAnthony Koo */ 22287c008829SNicholas Kazlauskas struct dmub_cmd_header header; 2229f56c837aSMikita Lipski 2230f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data data; 22317c008829SNicholas Kazlauskas }; 22327c008829SNicholas Kazlauskas 22331a595f28SAnthony Koo /** 22341a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 22351a595f28SAnthony Koo */ 2236d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data { 22371a595f28SAnthony Koo /** 22381a595f28SAnthony Koo * PSR version that FW should implement. 22391a595f28SAnthony Koo */ 22401a595f28SAnthony Koo enum psr_version version; 2241f56c837aSMikita Lipski /** 2242f56c837aSMikita Lipski * PSR control version. 2243f56c837aSMikita Lipski */ 2244f56c837aSMikita Lipski uint8_t cmd_version; 2245f56c837aSMikita Lipski /** 2246f56c837aSMikita Lipski * Panel Instance. 224736e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2248f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2249f56c837aSMikita Lipski */ 2250f56c837aSMikita Lipski uint8_t panel_inst; 2251f56c837aSMikita Lipski /** 2252f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 2253f56c837aSMikita Lipski */ 2254f56c837aSMikita Lipski uint8_t pad[2]; 22557c008829SNicholas Kazlauskas }; 22567c008829SNicholas Kazlauskas 22571a595f28SAnthony Koo /** 22581a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 22591a595f28SAnthony Koo */ 2260d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version { 22611a595f28SAnthony Koo /** 22621a595f28SAnthony Koo * Command header. 22631a595f28SAnthony Koo */ 22647c008829SNicholas Kazlauskas struct dmub_cmd_header header; 22651a595f28SAnthony Koo /** 22661a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 22671a595f28SAnthony Koo */ 2268d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data psr_set_version_data; 22697c008829SNicholas Kazlauskas }; 22707c008829SNicholas Kazlauskas 2271f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data { 2272f56c837aSMikita Lipski /** 2273f56c837aSMikita Lipski * PSR control version. 2274f56c837aSMikita Lipski */ 2275f56c837aSMikita Lipski uint8_t cmd_version; 2276f56c837aSMikita Lipski /** 2277f56c837aSMikita Lipski * Panel Instance. 227836e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2279f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2280f56c837aSMikita Lipski */ 2281f56c837aSMikita Lipski uint8_t panel_inst; 2282f56c837aSMikita Lipski /** 2283ad371c8aSAnthony Koo * Explicit padding to 4 byte boundary. 2284f56c837aSMikita Lipski */ 2285ad371c8aSAnthony Koo uint8_t pad[2]; 2286f56c837aSMikita Lipski }; 2287f56c837aSMikita Lipski 22881a595f28SAnthony Koo /** 22891a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 22901a595f28SAnthony Koo */ 2291672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static { 22921a595f28SAnthony Koo /** 22931a595f28SAnthony Koo * Command header. 22941a595f28SAnthony Koo */ 2295672251b2SAnthony Koo struct dmub_cmd_header header; 2296f56c837aSMikita Lipski /** 2297f56c837aSMikita Lipski * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2298f56c837aSMikita Lipski */ 2299f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data psr_force_static_data; 2300672251b2SAnthony Koo }; 2301672251b2SAnthony Koo 23021a595f28SAnthony Koo /** 230383eb5385SDavid Zhang * PSR SU debug flags. 230483eb5385SDavid Zhang */ 230583eb5385SDavid Zhang union dmub_psr_su_debug_flags { 230683eb5385SDavid Zhang /** 230783eb5385SDavid Zhang * PSR SU debug flags. 230883eb5385SDavid Zhang */ 230983eb5385SDavid Zhang struct { 231083eb5385SDavid Zhang /** 231183eb5385SDavid Zhang * Update dirty rect in SW only. 231283eb5385SDavid Zhang */ 231383eb5385SDavid Zhang uint8_t update_dirty_rect_only : 1; 231483eb5385SDavid Zhang /** 231583eb5385SDavid Zhang * Reset the cursor/plane state before processing the call. 231683eb5385SDavid Zhang */ 231783eb5385SDavid Zhang uint8_t reset_state : 1; 231883eb5385SDavid Zhang } bitfields; 231983eb5385SDavid Zhang 232083eb5385SDavid Zhang /** 232183eb5385SDavid Zhang * Union for debug flags. 232283eb5385SDavid Zhang */ 232383eb5385SDavid Zhang uint32_t u32All; 232483eb5385SDavid Zhang }; 232583eb5385SDavid Zhang 232683eb5385SDavid Zhang /** 232783eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 232883eb5385SDavid Zhang * This triggers a selective update for PSR SU. 232983eb5385SDavid Zhang */ 233083eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data { 233183eb5385SDavid Zhang /** 233283eb5385SDavid Zhang * Dirty rects from OS. 233383eb5385SDavid Zhang */ 233483eb5385SDavid Zhang struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 233583eb5385SDavid Zhang /** 233683eb5385SDavid Zhang * PSR SU debug flags. 233783eb5385SDavid Zhang */ 233883eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags; 233983eb5385SDavid Zhang /** 234083eb5385SDavid Zhang * OTG HW instance. 234183eb5385SDavid Zhang */ 234283eb5385SDavid Zhang uint8_t pipe_idx; 234383eb5385SDavid Zhang /** 234483eb5385SDavid Zhang * Number of dirty rects. 234583eb5385SDavid Zhang */ 234683eb5385SDavid Zhang uint8_t dirty_rect_count; 234783eb5385SDavid Zhang /** 234883eb5385SDavid Zhang * PSR control version. 234983eb5385SDavid Zhang */ 235083eb5385SDavid Zhang uint8_t cmd_version; 235183eb5385SDavid Zhang /** 235283eb5385SDavid Zhang * Panel Instance. 235336e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 235483eb5385SDavid Zhang * Currently the support is only for 0 or 1 235583eb5385SDavid Zhang */ 235683eb5385SDavid Zhang uint8_t panel_inst; 235783eb5385SDavid Zhang }; 235883eb5385SDavid Zhang 235983eb5385SDavid Zhang /** 236083eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 236183eb5385SDavid Zhang */ 236283eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect { 236383eb5385SDavid Zhang /** 236483eb5385SDavid Zhang * Command header. 236583eb5385SDavid Zhang */ 236683eb5385SDavid Zhang struct dmub_cmd_header header; 236783eb5385SDavid Zhang /** 236883eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 236983eb5385SDavid Zhang */ 237083eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 237183eb5385SDavid Zhang }; 237283eb5385SDavid Zhang 237383eb5385SDavid Zhang /** 237483eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 237583eb5385SDavid Zhang */ 2376b73353f7SMax Tseng union dmub_reg_cursor_control_cfg { 2377b73353f7SMax Tseng struct { 2378b73353f7SMax Tseng uint32_t cur_enable: 1; 2379b73353f7SMax Tseng uint32_t reser0: 3; 2380b73353f7SMax Tseng uint32_t cur_2x_magnify: 1; 2381b73353f7SMax Tseng uint32_t reser1: 3; 2382b73353f7SMax Tseng uint32_t mode: 3; 2383b73353f7SMax Tseng uint32_t reser2: 5; 2384b73353f7SMax Tseng uint32_t pitch: 2; 2385b73353f7SMax Tseng uint32_t reser3: 6; 2386b73353f7SMax Tseng uint32_t line_per_chunk: 5; 2387b73353f7SMax Tseng uint32_t reser4: 3; 2388b73353f7SMax Tseng } bits; 2389b73353f7SMax Tseng uint32_t raw; 2390b73353f7SMax Tseng }; 2391b73353f7SMax Tseng struct dmub_cursor_position_cache_hubp { 2392b73353f7SMax Tseng union dmub_reg_cursor_control_cfg cur_ctl; 2393b73353f7SMax Tseng union dmub_reg_position_cfg { 2394b73353f7SMax Tseng struct { 2395b73353f7SMax Tseng uint32_t cur_x_pos: 16; 2396b73353f7SMax Tseng uint32_t cur_y_pos: 16; 2397b73353f7SMax Tseng } bits; 2398b73353f7SMax Tseng uint32_t raw; 2399b73353f7SMax Tseng } position; 2400b73353f7SMax Tseng union dmub_reg_hot_spot_cfg { 2401b73353f7SMax Tseng struct { 2402b73353f7SMax Tseng uint32_t hot_x: 16; 2403b73353f7SMax Tseng uint32_t hot_y: 16; 2404b73353f7SMax Tseng } bits; 2405b73353f7SMax Tseng uint32_t raw; 2406b73353f7SMax Tseng } hot_spot; 2407b73353f7SMax Tseng union dmub_reg_dst_offset_cfg { 2408b73353f7SMax Tseng struct { 2409b73353f7SMax Tseng uint32_t dst_x_offset: 13; 2410b73353f7SMax Tseng uint32_t reserved: 19; 2411b73353f7SMax Tseng } bits; 2412b73353f7SMax Tseng uint32_t raw; 2413b73353f7SMax Tseng } dst_offset; 2414b73353f7SMax Tseng }; 2415b73353f7SMax Tseng 2416b73353f7SMax Tseng union dmub_reg_cur0_control_cfg { 2417b73353f7SMax Tseng struct { 2418b73353f7SMax Tseng uint32_t cur0_enable: 1; 2419b73353f7SMax Tseng uint32_t expansion_mode: 1; 2420b73353f7SMax Tseng uint32_t reser0: 1; 2421b73353f7SMax Tseng uint32_t cur0_rom_en: 1; 2422b73353f7SMax Tseng uint32_t mode: 3; 2423b73353f7SMax Tseng uint32_t reserved: 25; 2424b73353f7SMax Tseng } bits; 2425b73353f7SMax Tseng uint32_t raw; 2426b73353f7SMax Tseng }; 2427b73353f7SMax Tseng struct dmub_cursor_position_cache_dpp { 2428b73353f7SMax Tseng union dmub_reg_cur0_control_cfg cur0_ctl; 2429b73353f7SMax Tseng }; 2430b73353f7SMax Tseng struct dmub_cursor_position_cfg { 2431b73353f7SMax Tseng struct dmub_cursor_position_cache_hubp pHubp; 2432b73353f7SMax Tseng struct dmub_cursor_position_cache_dpp pDpp; 2433b73353f7SMax Tseng uint8_t pipe_idx; 2434b73353f7SMax Tseng /* 2435b73353f7SMax Tseng * Padding is required. To be 4 Bytes Aligned. 2436b73353f7SMax Tseng */ 2437b73353f7SMax Tseng uint8_t padding[3]; 2438b73353f7SMax Tseng }; 2439b73353f7SMax Tseng 2440b73353f7SMax Tseng struct dmub_cursor_attribute_cache_hubp { 2441b73353f7SMax Tseng uint32_t SURFACE_ADDR_HIGH; 2442b73353f7SMax Tseng uint32_t SURFACE_ADDR; 2443b73353f7SMax Tseng union dmub_reg_cursor_control_cfg cur_ctl; 2444b73353f7SMax Tseng union dmub_reg_cursor_size_cfg { 2445b73353f7SMax Tseng struct { 2446b73353f7SMax Tseng uint32_t width: 16; 2447b73353f7SMax Tseng uint32_t height: 16; 2448b73353f7SMax Tseng } bits; 2449b73353f7SMax Tseng uint32_t raw; 2450b73353f7SMax Tseng } size; 2451b73353f7SMax Tseng union dmub_reg_cursor_settings_cfg { 2452b73353f7SMax Tseng struct { 2453b73353f7SMax Tseng uint32_t dst_y_offset: 8; 2454b73353f7SMax Tseng uint32_t chunk_hdl_adjust: 2; 2455b73353f7SMax Tseng uint32_t reserved: 22; 2456b73353f7SMax Tseng } bits; 2457b73353f7SMax Tseng uint32_t raw; 2458b73353f7SMax Tseng } settings; 2459b73353f7SMax Tseng }; 2460b73353f7SMax Tseng struct dmub_cursor_attribute_cache_dpp { 2461b73353f7SMax Tseng union dmub_reg_cur0_control_cfg cur0_ctl; 2462b73353f7SMax Tseng }; 2463b73353f7SMax Tseng struct dmub_cursor_attributes_cfg { 2464b73353f7SMax Tseng struct dmub_cursor_attribute_cache_hubp aHubp; 2465b73353f7SMax Tseng struct dmub_cursor_attribute_cache_dpp aDpp; 2466b73353f7SMax Tseng }; 2467b73353f7SMax Tseng 2468b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 { 246983eb5385SDavid Zhang /** 247083eb5385SDavid Zhang * Cursor dirty rects. 247183eb5385SDavid Zhang */ 247283eb5385SDavid Zhang struct dmub_rect cursor_rect; 247383eb5385SDavid Zhang /** 247483eb5385SDavid Zhang * PSR SU debug flags. 247583eb5385SDavid Zhang */ 247683eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags; 247783eb5385SDavid Zhang /** 247883eb5385SDavid Zhang * Cursor enable/disable. 247983eb5385SDavid Zhang */ 248083eb5385SDavid Zhang uint8_t enable; 248183eb5385SDavid Zhang /** 248283eb5385SDavid Zhang * OTG HW instance. 248383eb5385SDavid Zhang */ 248483eb5385SDavid Zhang uint8_t pipe_idx; 248583eb5385SDavid Zhang /** 248683eb5385SDavid Zhang * PSR control version. 248783eb5385SDavid Zhang */ 248883eb5385SDavid Zhang uint8_t cmd_version; 248983eb5385SDavid Zhang /** 249083eb5385SDavid Zhang * Panel Instance. 249136e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 249283eb5385SDavid Zhang * Currently the support is only for 0 or 1 249383eb5385SDavid Zhang */ 249483eb5385SDavid Zhang uint8_t panel_inst; 2495b73353f7SMax Tseng /** 2496b73353f7SMax Tseng * Cursor Position Register. 2497b73353f7SMax Tseng * Registers contains Hubp & Dpp modules 2498b73353f7SMax Tseng */ 2499b73353f7SMax Tseng struct dmub_cursor_position_cfg position_cfg; 2500b73353f7SMax Tseng }; 2501b73353f7SMax Tseng 2502b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload1 { 2503b73353f7SMax Tseng struct dmub_cursor_attributes_cfg attribute_cfg; 2504b73353f7SMax Tseng }; 2505b73353f7SMax Tseng 2506b73353f7SMax Tseng union dmub_cmd_update_cursor_info_data { 2507b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 payload0; 2508b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload1 payload1; 250983eb5385SDavid Zhang }; 251083eb5385SDavid Zhang /** 251183eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 251283eb5385SDavid Zhang */ 251383eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info { 251483eb5385SDavid Zhang /** 251583eb5385SDavid Zhang * Command header. 251683eb5385SDavid Zhang */ 251783eb5385SDavid Zhang struct dmub_cmd_header header; 251883eb5385SDavid Zhang /** 251983eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 252083eb5385SDavid Zhang */ 2521b73353f7SMax Tseng union dmub_cmd_update_cursor_info_data update_cursor_info_data; 252283eb5385SDavid Zhang }; 252383eb5385SDavid Zhang 252483eb5385SDavid Zhang /** 252583eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 252683eb5385SDavid Zhang */ 252783eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data { 252883eb5385SDavid Zhang /** 252983eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 253083eb5385SDavid Zhang */ 253183eb5385SDavid Zhang uint16_t psr_vtotal_idle; 253283eb5385SDavid Zhang /** 253383eb5385SDavid Zhang * PSR control version. 253483eb5385SDavid Zhang */ 253583eb5385SDavid Zhang uint8_t cmd_version; 253683eb5385SDavid Zhang /** 253783eb5385SDavid Zhang * Panel Instance. 253836e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 253983eb5385SDavid Zhang * Currently the support is only for 0 or 1 254083eb5385SDavid Zhang */ 254183eb5385SDavid Zhang uint8_t panel_inst; 254283eb5385SDavid Zhang /* 254383eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 254483eb5385SDavid Zhang */ 254583eb5385SDavid Zhang uint16_t psr_vtotal_su; 254683eb5385SDavid Zhang /** 254783eb5385SDavid Zhang * Explicit padding to 4 byte boundary. 254883eb5385SDavid Zhang */ 254983eb5385SDavid Zhang uint8_t pad2[2]; 255083eb5385SDavid Zhang }; 255183eb5385SDavid Zhang 255283eb5385SDavid Zhang /** 255383eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 255483eb5385SDavid Zhang */ 255583eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal { 255683eb5385SDavid Zhang /** 255783eb5385SDavid Zhang * Command header. 255883eb5385SDavid Zhang */ 255983eb5385SDavid Zhang struct dmub_cmd_header header; 256083eb5385SDavid Zhang /** 256183eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 256283eb5385SDavid Zhang */ 256383eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 256483eb5385SDavid Zhang }; 256583eb5385SDavid Zhang 256683eb5385SDavid Zhang /** 2567e5dfcd27SRobin Chen * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2568e5dfcd27SRobin Chen */ 2569e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data { 2570e5dfcd27SRobin Chen /** 2571e5dfcd27SRobin Chen * PSR control version. 2572e5dfcd27SRobin Chen */ 2573e5dfcd27SRobin Chen uint8_t cmd_version; 2574e5dfcd27SRobin Chen /** 2575e5dfcd27SRobin Chen * Panel Instance. 257636e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2577e5dfcd27SRobin Chen * Currently the support is only for 0 or 1 2578e5dfcd27SRobin Chen */ 2579e5dfcd27SRobin Chen uint8_t panel_inst; 2580e5dfcd27SRobin Chen /** 2581e5dfcd27SRobin Chen * Explicit padding to 4 byte boundary. 2582e5dfcd27SRobin Chen */ 2583e5dfcd27SRobin Chen uint8_t pad[2]; 2584e5dfcd27SRobin Chen /** 2585e5dfcd27SRobin Chen * PSR power option 2586e5dfcd27SRobin Chen */ 2587e5dfcd27SRobin Chen uint32_t power_opt; 2588e5dfcd27SRobin Chen }; 2589e5dfcd27SRobin Chen 2590e5dfcd27SRobin Chen /** 2591e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2592e5dfcd27SRobin Chen */ 2593e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt { 2594e5dfcd27SRobin Chen /** 2595e5dfcd27SRobin Chen * Command header. 2596e5dfcd27SRobin Chen */ 2597e5dfcd27SRobin Chen struct dmub_cmd_header header; 2598e5dfcd27SRobin Chen /** 2599e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2600e5dfcd27SRobin Chen */ 2601e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2602e5dfcd27SRobin Chen }; 2603e5dfcd27SRobin Chen 2604e5dfcd27SRobin Chen /** 26051a595f28SAnthony Koo * Set of HW components that can be locked. 26060b51e7e8SAnthony Koo * 26070b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 26080b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 26091a595f28SAnthony Koo */ 2610788408b7SAnthony Koo union dmub_hw_lock_flags { 26111a595f28SAnthony Koo /** 26121a595f28SAnthony Koo * Set of HW components that can be locked. 26131a595f28SAnthony Koo */ 2614788408b7SAnthony Koo struct { 26151a595f28SAnthony Koo /** 26161a595f28SAnthony Koo * Lock/unlock OTG master update lock. 26171a595f28SAnthony Koo */ 2618788408b7SAnthony Koo uint8_t lock_pipe : 1; 26191a595f28SAnthony Koo /** 26201a595f28SAnthony Koo * Lock/unlock cursor. 26211a595f28SAnthony Koo */ 2622788408b7SAnthony Koo uint8_t lock_cursor : 1; 26231a595f28SAnthony Koo /** 26241a595f28SAnthony Koo * Lock/unlock global update lock. 26251a595f28SAnthony Koo */ 2626788408b7SAnthony Koo uint8_t lock_dig : 1; 26271a595f28SAnthony Koo /** 26281a595f28SAnthony Koo * Triple buffer lock requires additional hw programming to usual OTG master lock. 26291a595f28SAnthony Koo */ 2630788408b7SAnthony Koo uint8_t triple_buffer_lock : 1; 2631788408b7SAnthony Koo } bits; 2632788408b7SAnthony Koo 26331a595f28SAnthony Koo /** 26341a595f28SAnthony Koo * Union for HW Lock flags. 26351a595f28SAnthony Koo */ 2636788408b7SAnthony Koo uint8_t u8All; 2637788408b7SAnthony Koo }; 2638788408b7SAnthony Koo 26391a595f28SAnthony Koo /** 26401a595f28SAnthony Koo * Instances of HW to be locked. 26410b51e7e8SAnthony Koo * 26420b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 26430b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 26441a595f28SAnthony Koo */ 2645788408b7SAnthony Koo struct dmub_hw_lock_inst_flags { 26461a595f28SAnthony Koo /** 26471a595f28SAnthony Koo * OTG HW instance for OTG master update lock. 26481a595f28SAnthony Koo */ 2649788408b7SAnthony Koo uint8_t otg_inst; 26501a595f28SAnthony Koo /** 26511a595f28SAnthony Koo * OPP instance for cursor lock. 26521a595f28SAnthony Koo */ 2653788408b7SAnthony Koo uint8_t opp_inst; 26541a595f28SAnthony Koo /** 26551a595f28SAnthony Koo * OTG HW instance for global update lock. 26561a595f28SAnthony Koo * TODO: Remove, and re-use otg_inst. 26571a595f28SAnthony Koo */ 2658788408b7SAnthony Koo uint8_t dig_inst; 26591a595f28SAnthony Koo /** 26601a595f28SAnthony Koo * Explicit pad to 4 byte boundary. 26611a595f28SAnthony Koo */ 2662788408b7SAnthony Koo uint8_t pad; 2663788408b7SAnthony Koo }; 2664788408b7SAnthony Koo 26651a595f28SAnthony Koo /** 26661a595f28SAnthony Koo * Clients that can acquire the HW Lock Manager. 26670b51e7e8SAnthony Koo * 26680b51e7e8SAnthony Koo * Note: If updating with more clients, fields in 26690b51e7e8SAnthony Koo * dmub_inbox0_cmd_lock_hw must be updated to match. 26701a595f28SAnthony Koo */ 2671788408b7SAnthony Koo enum hw_lock_client { 26721a595f28SAnthony Koo /** 26731a595f28SAnthony Koo * Driver is the client of HW Lock Manager. 26741a595f28SAnthony Koo */ 2675788408b7SAnthony Koo HW_LOCK_CLIENT_DRIVER = 0, 26761a595f28SAnthony Koo /** 267783eb5385SDavid Zhang * PSR SU is the client of HW Lock Manager. 267883eb5385SDavid Zhang */ 267983eb5385SDavid Zhang HW_LOCK_CLIENT_PSR_SU = 1, 268083eb5385SDavid Zhang /** 26811a595f28SAnthony Koo * Invalid client. 26821a595f28SAnthony Koo */ 2683788408b7SAnthony Koo HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2684788408b7SAnthony Koo }; 2685788408b7SAnthony Koo 26861a595f28SAnthony Koo /** 26871a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 26881a595f28SAnthony Koo */ 2689788408b7SAnthony Koo struct dmub_cmd_lock_hw_data { 26901a595f28SAnthony Koo /** 26911a595f28SAnthony Koo * Specifies the client accessing HW Lock Manager. 26921a595f28SAnthony Koo */ 2693788408b7SAnthony Koo enum hw_lock_client client; 26941a595f28SAnthony Koo /** 26951a595f28SAnthony Koo * HW instances to be locked. 26961a595f28SAnthony Koo */ 2697788408b7SAnthony Koo struct dmub_hw_lock_inst_flags inst_flags; 26981a595f28SAnthony Koo /** 26991a595f28SAnthony Koo * Which components to be locked. 27001a595f28SAnthony Koo */ 2701788408b7SAnthony Koo union dmub_hw_lock_flags hw_locks; 27021a595f28SAnthony Koo /** 27031a595f28SAnthony Koo * Specifies lock/unlock. 27041a595f28SAnthony Koo */ 2705788408b7SAnthony Koo uint8_t lock; 27061a595f28SAnthony Koo /** 27071a595f28SAnthony Koo * HW can be unlocked separately from releasing the HW Lock Mgr. 27081a595f28SAnthony Koo * This flag is set if the client wishes to release the object. 27091a595f28SAnthony Koo */ 2710788408b7SAnthony Koo uint8_t should_release; 27111a595f28SAnthony Koo /** 27121a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 27131a595f28SAnthony Koo */ 2714788408b7SAnthony Koo uint8_t pad; 2715788408b7SAnthony Koo }; 2716788408b7SAnthony Koo 27171a595f28SAnthony Koo /** 27181a595f28SAnthony Koo * Definition of a DMUB_CMD__HW_LOCK command. 27191a595f28SAnthony Koo * Command is used by driver and FW. 27201a595f28SAnthony Koo */ 2721788408b7SAnthony Koo struct dmub_rb_cmd_lock_hw { 27221a595f28SAnthony Koo /** 27231a595f28SAnthony Koo * Command header. 27241a595f28SAnthony Koo */ 2725788408b7SAnthony Koo struct dmub_cmd_header header; 27261a595f28SAnthony Koo /** 27271a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 27281a595f28SAnthony Koo */ 2729788408b7SAnthony Koo struct dmub_cmd_lock_hw_data lock_hw_data; 2730788408b7SAnthony Koo }; 2731788408b7SAnthony Koo 27321a595f28SAnthony Koo /** 27331a595f28SAnthony Koo * ABM command sub-types. 27341a595f28SAnthony Koo */ 273584034ad4SAnthony Koo enum dmub_cmd_abm_type { 27361a595f28SAnthony Koo /** 27371a595f28SAnthony Koo * Initialize parameters for ABM algorithm. 27381a595f28SAnthony Koo * Data is passed through an indirect buffer. 27391a595f28SAnthony Koo */ 274084034ad4SAnthony Koo DMUB_CMD__ABM_INIT_CONFIG = 0, 27411a595f28SAnthony Koo /** 27421a595f28SAnthony Koo * Set OTG and panel HW instance. 27431a595f28SAnthony Koo */ 274484034ad4SAnthony Koo DMUB_CMD__ABM_SET_PIPE = 1, 27451a595f28SAnthony Koo /** 27461a595f28SAnthony Koo * Set user requested backklight level. 27471a595f28SAnthony Koo */ 274884034ad4SAnthony Koo DMUB_CMD__ABM_SET_BACKLIGHT = 2, 27491a595f28SAnthony Koo /** 27501a595f28SAnthony Koo * Set ABM operating/aggression level. 27511a595f28SAnthony Koo */ 275284034ad4SAnthony Koo DMUB_CMD__ABM_SET_LEVEL = 3, 27531a595f28SAnthony Koo /** 27541a595f28SAnthony Koo * Set ambient light level. 27551a595f28SAnthony Koo */ 275684034ad4SAnthony Koo DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 27571a595f28SAnthony Koo /** 27581a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 27591a595f28SAnthony Koo */ 276084034ad4SAnthony Koo DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2761b629a824SEric Yang 2762b629a824SEric Yang /** 2763b629a824SEric Yang * unregister vertical interrupt after steady state is reached 2764b629a824SEric Yang */ 2765b629a824SEric Yang DMUB_CMD__ABM_PAUSE = 6, 2766da915efaSReza Amini 2767da915efaSReza Amini /** 2768*519e3637SReza Amini * Save and Restore ABM state. On save we save parameters, and 2769da915efaSReza Amini * on restore we update state with passed in data. 2770da915efaSReza Amini */ 2771da915efaSReza Amini DMUB_CMD__ABM_SAVE_RESTORE = 7, 277284034ad4SAnthony Koo }; 277384034ad4SAnthony Koo 27741a595f28SAnthony Koo /** 27751a595f28SAnthony Koo * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 27761a595f28SAnthony Koo * Requirements: 27771a595f28SAnthony Koo * - Padded explicitly to 32-bit boundary. 27781a595f28SAnthony Koo * - Must ensure this structure matches the one on driver-side, 27791a595f28SAnthony Koo * otherwise it won't be aligned. 278084034ad4SAnthony Koo */ 278184034ad4SAnthony Koo struct abm_config_table { 27821a595f28SAnthony Koo /** 27831a595f28SAnthony Koo * Gamma curve thresholds, used for crgb conversion. 27841a595f28SAnthony Koo */ 278584034ad4SAnthony Koo uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 27861a595f28SAnthony Koo /** 27871a595f28SAnthony Koo * Gamma curve offsets, used for crgb conversion. 27881a595f28SAnthony Koo */ 2789b6402afeSAnthony Koo uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 27901a595f28SAnthony Koo /** 27911a595f28SAnthony Koo * Gamma curve slopes, used for crgb conversion. 27921a595f28SAnthony Koo */ 2793b6402afeSAnthony Koo uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 27941a595f28SAnthony Koo /** 27951a595f28SAnthony Koo * Custom backlight curve thresholds. 27961a595f28SAnthony Koo */ 2797b6402afeSAnthony Koo uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 27981a595f28SAnthony Koo /** 27991a595f28SAnthony Koo * Custom backlight curve offsets. 28001a595f28SAnthony Koo */ 2801b6402afeSAnthony Koo uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 28021a595f28SAnthony Koo /** 28031a595f28SAnthony Koo * Ambient light thresholds. 28041a595f28SAnthony Koo */ 2805b6402afeSAnthony Koo uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 28061a595f28SAnthony Koo /** 28071a595f28SAnthony Koo * Minimum programmable backlight. 28081a595f28SAnthony Koo */ 2809b6402afeSAnthony Koo uint16_t min_abm_backlight; // 122B 28101a595f28SAnthony Koo /** 28111a595f28SAnthony Koo * Minimum reduction values. 28121a595f28SAnthony Koo */ 2813b6402afeSAnthony Koo uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 28141a595f28SAnthony Koo /** 28151a595f28SAnthony Koo * Maximum reduction values. 28161a595f28SAnthony Koo */ 2817b6402afeSAnthony Koo uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 28181a595f28SAnthony Koo /** 28191a595f28SAnthony Koo * Bright positive gain. 28201a595f28SAnthony Koo */ 2821b6402afeSAnthony Koo uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 28221a595f28SAnthony Koo /** 28231a595f28SAnthony Koo * Dark negative gain. 28241a595f28SAnthony Koo */ 2825b6402afeSAnthony Koo uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 28261a595f28SAnthony Koo /** 28271a595f28SAnthony Koo * Hybrid factor. 28281a595f28SAnthony Koo */ 2829b6402afeSAnthony Koo uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 28301a595f28SAnthony Koo /** 28311a595f28SAnthony Koo * Contrast factor. 28321a595f28SAnthony Koo */ 2833b6402afeSAnthony Koo uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 28341a595f28SAnthony Koo /** 28351a595f28SAnthony Koo * Deviation gain. 28361a595f28SAnthony Koo */ 2837b6402afeSAnthony Koo uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 28381a595f28SAnthony Koo /** 28391a595f28SAnthony Koo * Minimum knee. 28401a595f28SAnthony Koo */ 2841b6402afeSAnthony Koo uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 28421a595f28SAnthony Koo /** 28431a595f28SAnthony Koo * Maximum knee. 28441a595f28SAnthony Koo */ 2845b6402afeSAnthony Koo uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 28461a595f28SAnthony Koo /** 28471a595f28SAnthony Koo * Unused. 28481a595f28SAnthony Koo */ 2849b6402afeSAnthony Koo uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 28501a595f28SAnthony Koo /** 28511a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 28521a595f28SAnthony Koo */ 2853b6402afeSAnthony Koo uint8_t pad3[3]; // 229B 28541a595f28SAnthony Koo /** 28551a595f28SAnthony Koo * Backlight ramp reduction. 28561a595f28SAnthony Koo */ 2857b6402afeSAnthony Koo uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 28581a595f28SAnthony Koo /** 28591a595f28SAnthony Koo * Backlight ramp start. 28601a595f28SAnthony Koo */ 2861b6402afeSAnthony Koo uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 286284034ad4SAnthony Koo }; 286384034ad4SAnthony Koo 28641a595f28SAnthony Koo /** 28651a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 28661a595f28SAnthony Koo */ 2867e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data { 28681a595f28SAnthony Koo /** 28691a595f28SAnthony Koo * OTG HW instance. 28701a595f28SAnthony Koo */ 28717b8a6362SAnthony Koo uint8_t otg_inst; 28721a595f28SAnthony Koo 28731a595f28SAnthony Koo /** 28741a595f28SAnthony Koo * Panel Control HW instance. 28751a595f28SAnthony Koo */ 28767b8a6362SAnthony Koo uint8_t panel_inst; 28771a595f28SAnthony Koo 28781a595f28SAnthony Koo /** 28791a595f28SAnthony Koo * Controls how ABM will interpret a set pipe or set level command. 28801a595f28SAnthony Koo */ 28817b8a6362SAnthony Koo uint8_t set_pipe_option; 28821a595f28SAnthony Koo 28831a595f28SAnthony Koo /** 28841a595f28SAnthony Koo * Unused. 28851a595f28SAnthony Koo * TODO: Remove. 28861a595f28SAnthony Koo */ 28871a595f28SAnthony Koo uint8_t ramping_boundary; 2888e6ea8c34SWyatt Wood }; 2889e6ea8c34SWyatt Wood 28901a595f28SAnthony Koo /** 28911a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 28921a595f28SAnthony Koo */ 2893e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe { 28941a595f28SAnthony Koo /** 28951a595f28SAnthony Koo * Command header. 28961a595f28SAnthony Koo */ 2897e6ea8c34SWyatt Wood struct dmub_cmd_header header; 28981a595f28SAnthony Koo 28991a595f28SAnthony Koo /** 29001a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 29011a595f28SAnthony Koo */ 2902e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2903e6ea8c34SWyatt Wood }; 2904e6ea8c34SWyatt Wood 29051a595f28SAnthony Koo /** 29061a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 29071a595f28SAnthony Koo */ 2908e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data { 29091a595f28SAnthony Koo /** 29101a595f28SAnthony Koo * Number of frames to ramp to backlight user level. 29111a595f28SAnthony Koo */ 2912e6ea8c34SWyatt Wood uint32_t frame_ramp; 29131a595f28SAnthony Koo 29141a595f28SAnthony Koo /** 29151a595f28SAnthony Koo * Requested backlight level from user. 29161a595f28SAnthony Koo */ 2917474ac4a8SYongqiang Sun uint32_t backlight_user_level; 2918e922057bSJake Wang 2919e922057bSJake Wang /** 292063de4f04SJake Wang * ABM control version. 2921e922057bSJake Wang */ 2922e922057bSJake Wang uint8_t version; 2923e922057bSJake Wang 2924e922057bSJake Wang /** 2925e922057bSJake Wang * Panel Control HW instance mask. 2926e922057bSJake Wang * Bit 0 is Panel Control HW instance 0. 2927e922057bSJake Wang * Bit 1 is Panel Control HW instance 1. 2928e922057bSJake Wang */ 2929e922057bSJake Wang uint8_t panel_mask; 2930e922057bSJake Wang 2931e922057bSJake Wang /** 2932e922057bSJake Wang * Explicit padding to 4 byte boundary. 2933e922057bSJake Wang */ 2934e922057bSJake Wang uint8_t pad[2]; 2935e6ea8c34SWyatt Wood }; 2936e6ea8c34SWyatt Wood 29371a595f28SAnthony Koo /** 29381a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 29391a595f28SAnthony Koo */ 2940e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight { 29411a595f28SAnthony Koo /** 29421a595f28SAnthony Koo * Command header. 29431a595f28SAnthony Koo */ 2944e6ea8c34SWyatt Wood struct dmub_cmd_header header; 29451a595f28SAnthony Koo 29461a595f28SAnthony Koo /** 29471a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 29481a595f28SAnthony Koo */ 2949e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2950e6ea8c34SWyatt Wood }; 2951e6ea8c34SWyatt Wood 29521a595f28SAnthony Koo /** 29531a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 29541a595f28SAnthony Koo */ 2955e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data { 29561a595f28SAnthony Koo /** 29571a595f28SAnthony Koo * Set current ABM operating/aggression level. 29581a595f28SAnthony Koo */ 2959e6ea8c34SWyatt Wood uint32_t level; 296063de4f04SJake Wang 296163de4f04SJake Wang /** 296263de4f04SJake Wang * ABM control version. 296363de4f04SJake Wang */ 296463de4f04SJake Wang uint8_t version; 296563de4f04SJake Wang 296663de4f04SJake Wang /** 296763de4f04SJake Wang * Panel Control HW instance mask. 296863de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 296963de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 297063de4f04SJake Wang */ 297163de4f04SJake Wang uint8_t panel_mask; 297263de4f04SJake Wang 297363de4f04SJake Wang /** 297463de4f04SJake Wang * Explicit padding to 4 byte boundary. 297563de4f04SJake Wang */ 297663de4f04SJake Wang uint8_t pad[2]; 2977e6ea8c34SWyatt Wood }; 2978e6ea8c34SWyatt Wood 29791a595f28SAnthony Koo /** 29801a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 29811a595f28SAnthony Koo */ 2982e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level { 29831a595f28SAnthony Koo /** 29841a595f28SAnthony Koo * Command header. 29851a595f28SAnthony Koo */ 2986e6ea8c34SWyatt Wood struct dmub_cmd_header header; 29871a595f28SAnthony Koo 29881a595f28SAnthony Koo /** 29891a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 29901a595f28SAnthony Koo */ 2991e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data abm_set_level_data; 2992e6ea8c34SWyatt Wood }; 2993e6ea8c34SWyatt Wood 29941a595f28SAnthony Koo /** 29951a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 29961a595f28SAnthony Koo */ 2997e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data { 29981a595f28SAnthony Koo /** 29991a595f28SAnthony Koo * Ambient light sensor reading from OS. 30001a595f28SAnthony Koo */ 3001e6ea8c34SWyatt Wood uint32_t ambient_lux; 300263de4f04SJake Wang 300363de4f04SJake Wang /** 300463de4f04SJake Wang * ABM control version. 300563de4f04SJake Wang */ 300663de4f04SJake Wang uint8_t version; 300763de4f04SJake Wang 300863de4f04SJake Wang /** 300963de4f04SJake Wang * Panel Control HW instance mask. 301063de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 301163de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 301263de4f04SJake Wang */ 301363de4f04SJake Wang uint8_t panel_mask; 301463de4f04SJake Wang 301563de4f04SJake Wang /** 301663de4f04SJake Wang * Explicit padding to 4 byte boundary. 301763de4f04SJake Wang */ 301863de4f04SJake Wang uint8_t pad[2]; 3019e6ea8c34SWyatt Wood }; 3020e6ea8c34SWyatt Wood 30211a595f28SAnthony Koo /** 30221a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 30231a595f28SAnthony Koo */ 3024e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level { 30251a595f28SAnthony Koo /** 30261a595f28SAnthony Koo * Command header. 30271a595f28SAnthony Koo */ 3028e6ea8c34SWyatt Wood struct dmub_cmd_header header; 30291a595f28SAnthony Koo 30301a595f28SAnthony Koo /** 30311a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 30321a595f28SAnthony Koo */ 3033e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 3034e6ea8c34SWyatt Wood }; 3035e6ea8c34SWyatt Wood 30361a595f28SAnthony Koo /** 30371a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 30381a595f28SAnthony Koo */ 3039e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data { 30401a595f28SAnthony Koo /** 30411a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 30421a595f28SAnthony Koo * TODO: Convert to uint8_t. 30431a595f28SAnthony Koo */ 3044e6ea8c34SWyatt Wood uint32_t fractional_pwm; 304563de4f04SJake Wang 304663de4f04SJake Wang /** 304763de4f04SJake Wang * ABM control version. 304863de4f04SJake Wang */ 304963de4f04SJake Wang uint8_t version; 305063de4f04SJake Wang 305163de4f04SJake Wang /** 305263de4f04SJake Wang * Panel Control HW instance mask. 305363de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 305463de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 305563de4f04SJake Wang */ 305663de4f04SJake Wang uint8_t panel_mask; 305763de4f04SJake Wang 305863de4f04SJake Wang /** 305963de4f04SJake Wang * Explicit padding to 4 byte boundary. 306063de4f04SJake Wang */ 306163de4f04SJake Wang uint8_t pad[2]; 3062e6ea8c34SWyatt Wood }; 3063e6ea8c34SWyatt Wood 30641a595f28SAnthony Koo /** 30651a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 30661a595f28SAnthony Koo */ 3067e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac { 30681a595f28SAnthony Koo /** 30691a595f28SAnthony Koo * Command header. 30701a595f28SAnthony Koo */ 3071e6ea8c34SWyatt Wood struct dmub_cmd_header header; 30721a595f28SAnthony Koo 30731a595f28SAnthony Koo /** 30741a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 30751a595f28SAnthony Koo */ 3076e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 3077e6ea8c34SWyatt Wood }; 3078e6ea8c34SWyatt Wood 30791a595f28SAnthony Koo /** 30801a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 30811a595f28SAnthony Koo */ 308216012806SWyatt Wood struct dmub_cmd_abm_init_config_data { 30831a595f28SAnthony Koo /** 30841a595f28SAnthony Koo * Location of indirect buffer used to pass init data to ABM. 30851a595f28SAnthony Koo */ 308616012806SWyatt Wood union dmub_addr src; 30871a595f28SAnthony Koo 30881a595f28SAnthony Koo /** 30891a595f28SAnthony Koo * Indirect buffer length. 30901a595f28SAnthony Koo */ 309116012806SWyatt Wood uint16_t bytes; 309263de4f04SJake Wang 309363de4f04SJake Wang 309463de4f04SJake Wang /** 309563de4f04SJake Wang * ABM control version. 309663de4f04SJake Wang */ 309763de4f04SJake Wang uint8_t version; 309863de4f04SJake Wang 309963de4f04SJake Wang /** 310063de4f04SJake Wang * Panel Control HW instance mask. 310163de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 310263de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 310363de4f04SJake Wang */ 310463de4f04SJake Wang uint8_t panel_mask; 310563de4f04SJake Wang 310663de4f04SJake Wang /** 310763de4f04SJake Wang * Explicit padding to 4 byte boundary. 310863de4f04SJake Wang */ 310963de4f04SJake Wang uint8_t pad[2]; 311016012806SWyatt Wood }; 311116012806SWyatt Wood 31121a595f28SAnthony Koo /** 31131a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 31141a595f28SAnthony Koo */ 311516012806SWyatt Wood struct dmub_rb_cmd_abm_init_config { 31161a595f28SAnthony Koo /** 31171a595f28SAnthony Koo * Command header. 31181a595f28SAnthony Koo */ 311916012806SWyatt Wood struct dmub_cmd_header header; 31201a595f28SAnthony Koo 31211a595f28SAnthony Koo /** 31221a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 31231a595f28SAnthony Koo */ 312416012806SWyatt Wood struct dmub_cmd_abm_init_config_data abm_init_config_data; 312516012806SWyatt Wood }; 312616012806SWyatt Wood 31271a595f28SAnthony Koo /** 3128b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3129b629a824SEric Yang */ 3130b629a824SEric Yang 3131b629a824SEric Yang struct dmub_cmd_abm_pause_data { 3132b629a824SEric Yang 3133b629a824SEric Yang /** 3134b629a824SEric Yang * Panel Control HW instance mask. 3135b629a824SEric Yang * Bit 0 is Panel Control HW instance 0. 3136b629a824SEric Yang * Bit 1 is Panel Control HW instance 1. 3137b629a824SEric Yang */ 3138b629a824SEric Yang uint8_t panel_mask; 3139b629a824SEric Yang 3140b629a824SEric Yang /** 3141b629a824SEric Yang * OTG hw instance 3142b629a824SEric Yang */ 3143b629a824SEric Yang uint8_t otg_inst; 3144b629a824SEric Yang 3145b629a824SEric Yang /** 3146b629a824SEric Yang * Enable or disable ABM pause 3147b629a824SEric Yang */ 3148b629a824SEric Yang uint8_t enable; 3149b629a824SEric Yang 3150b629a824SEric Yang /** 3151b629a824SEric Yang * Explicit padding to 4 byte boundary. 3152b629a824SEric Yang */ 3153b629a824SEric Yang uint8_t pad[1]; 3154b629a824SEric Yang }; 3155b629a824SEric Yang 3156*519e3637SReza Amini 3157b629a824SEric Yang /** 3158b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 3159b629a824SEric Yang */ 3160b629a824SEric Yang struct dmub_rb_cmd_abm_pause { 3161b629a824SEric Yang /** 3162b629a824SEric Yang * Command header. 3163b629a824SEric Yang */ 3164b629a824SEric Yang struct dmub_cmd_header header; 3165b629a824SEric Yang 3166b629a824SEric Yang /** 3167b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3168b629a824SEric Yang */ 3169b629a824SEric Yang struct dmub_cmd_abm_pause_data abm_pause_data; 3170b629a824SEric Yang }; 3171b629a824SEric Yang 3172b629a824SEric Yang /** 3173da915efaSReza Amini * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 3174da915efaSReza Amini */ 3175da915efaSReza Amini struct dmub_rb_cmd_abm_save_restore { 3176da915efaSReza Amini /** 3177da915efaSReza Amini * Command header. 3178da915efaSReza Amini */ 3179da915efaSReza Amini struct dmub_cmd_header header; 3180da915efaSReza Amini 3181da915efaSReza Amini /** 3182da915efaSReza Amini * OTG hw instance 3183da915efaSReza Amini */ 3184da915efaSReza Amini uint8_t otg_inst; 3185da915efaSReza Amini 3186da915efaSReza Amini /** 3187da915efaSReza Amini * Enable or disable ABM pause 3188da915efaSReza Amini */ 3189da915efaSReza Amini uint8_t freeze; 3190da915efaSReza Amini 3191da915efaSReza Amini /** 3192da915efaSReza Amini * Explicit padding to 4 byte boundary. 3193da915efaSReza Amini */ 3194da915efaSReza Amini uint8_t debug; 3195da915efaSReza Amini 3196da915efaSReza Amini /** 3197da915efaSReza Amini * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3198da915efaSReza Amini */ 3199da915efaSReza Amini struct dmub_cmd_abm_init_config_data abm_init_config_data; 3200da915efaSReza Amini }; 3201da915efaSReza Amini 3202da915efaSReza Amini /** 32031a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 32041a595f28SAnthony Koo */ 320534ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data { 32061a595f28SAnthony Koo /** 32071a595f28SAnthony Koo * DMUB feature capabilities. 32081a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features. 32091a595f28SAnthony Koo */ 321034ba432cSAnthony Koo struct dmub_feature_caps feature_caps; 321134ba432cSAnthony Koo }; 321234ba432cSAnthony Koo 32131a595f28SAnthony Koo /** 32141a595f28SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 32151a595f28SAnthony Koo */ 321634ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps { 32171a595f28SAnthony Koo /** 32181a595f28SAnthony Koo * Command header. 32191a595f28SAnthony Koo */ 322034ba432cSAnthony Koo struct dmub_cmd_header header; 32211a595f28SAnthony Koo /** 32221a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 32231a595f28SAnthony Koo */ 322434ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 322534ba432cSAnthony Koo }; 322634ba432cSAnthony Koo 3227b09c1fffSLeo (Hanghong) Ma /** 3228b09c1fffSLeo (Hanghong) Ma * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3229b09c1fffSLeo (Hanghong) Ma */ 3230b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_visual_confirm_color_data { 3231b09c1fffSLeo (Hanghong) Ma /** 3232b09c1fffSLeo (Hanghong) Ma * DMUB feature capabilities. 3233b09c1fffSLeo (Hanghong) Ma * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3234b09c1fffSLeo (Hanghong) Ma */ 3235b09c1fffSLeo (Hanghong) Ma struct dmub_visual_confirm_color visual_confirm_color; 3236b09c1fffSLeo (Hanghong) Ma }; 3237b09c1fffSLeo (Hanghong) Ma 3238b09c1fffSLeo (Hanghong) Ma /** 3239b09c1fffSLeo (Hanghong) Ma * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3240b09c1fffSLeo (Hanghong) Ma */ 3241b09c1fffSLeo (Hanghong) Ma struct dmub_rb_cmd_get_visual_confirm_color { 3242b09c1fffSLeo (Hanghong) Ma /** 3243b09c1fffSLeo (Hanghong) Ma * Command header. 3244b09c1fffSLeo (Hanghong) Ma */ 3245b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_header header; 3246b09c1fffSLeo (Hanghong) Ma /** 3247b09c1fffSLeo (Hanghong) Ma * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3248b09c1fffSLeo (Hanghong) Ma */ 3249b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3250b09c1fffSLeo (Hanghong) Ma }; 3251b09c1fffSLeo (Hanghong) Ma 3252592a6318SAnthony Koo struct dmub_optc_state { 3253592a6318SAnthony Koo uint32_t v_total_max; 3254592a6318SAnthony Koo uint32_t v_total_min; 3255592a6318SAnthony Koo uint32_t tg_inst; 3256592a6318SAnthony Koo }; 3257592a6318SAnthony Koo 3258592a6318SAnthony Koo struct dmub_rb_cmd_drr_update { 3259592a6318SAnthony Koo struct dmub_cmd_header header; 3260592a6318SAnthony Koo struct dmub_optc_state dmub_optc_state_req; 3261592a6318SAnthony Koo }; 3262592a6318SAnthony Koo 326300fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 326400fa7f03SRodrigo Siqueira uint32_t pix_clk_100hz; 326500fa7f03SRodrigo Siqueira uint8_t max_ramp_step; 326600fa7f03SRodrigo Siqueira uint8_t pipes; 326700fa7f03SRodrigo Siqueira uint8_t min_refresh_in_hz; 3268d3981ee7SAnthony Koo uint8_t pipe_count; 3269d3981ee7SAnthony Koo uint8_t pipe_index[4]; 327000fa7f03SRodrigo Siqueira }; 327100fa7f03SRodrigo Siqueira 327200fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config { 327300fa7f03SRodrigo Siqueira uint8_t fams_enabled; 327400fa7f03SRodrigo Siqueira uint8_t visual_confirm_enabled; 3275d3981ee7SAnthony Koo uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 3276d3981ee7SAnthony Koo struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 327700fa7f03SRodrigo Siqueira }; 327800fa7f03SRodrigo Siqueira 327900fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch { 328000fa7f03SRodrigo Siqueira struct dmub_cmd_header header; 328100fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 328200fa7f03SRodrigo Siqueira }; 328300fa7f03SRodrigo Siqueira 3284b04cb192SNicholas Kazlauskas /** 3285b04cb192SNicholas Kazlauskas * enum dmub_cmd_panel_cntl_type - Panel control command. 3286b04cb192SNicholas Kazlauskas */ 3287b04cb192SNicholas Kazlauskas enum dmub_cmd_panel_cntl_type { 3288b04cb192SNicholas Kazlauskas /** 3289b04cb192SNicholas Kazlauskas * Initializes embedded panel hardware blocks. 3290b04cb192SNicholas Kazlauskas */ 3291b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3292b04cb192SNicholas Kazlauskas /** 3293b04cb192SNicholas Kazlauskas * Queries backlight info for the embedded panel. 3294b04cb192SNicholas Kazlauskas */ 3295b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3296b04cb192SNicholas Kazlauskas }; 3297b04cb192SNicholas Kazlauskas 3298b04cb192SNicholas Kazlauskas /** 3299b04cb192SNicholas Kazlauskas * struct dmub_cmd_panel_cntl_data - Panel control data. 3300b04cb192SNicholas Kazlauskas */ 3301b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data { 3302b04cb192SNicholas Kazlauskas uint32_t inst; /**< panel instance */ 3303b04cb192SNicholas Kazlauskas uint32_t current_backlight; /* in/out */ 3304b04cb192SNicholas Kazlauskas uint32_t bl_pwm_cntl; /* in/out */ 3305b04cb192SNicholas Kazlauskas uint32_t bl_pwm_period_cntl; /* in/out */ 3306b04cb192SNicholas Kazlauskas uint32_t bl_pwm_ref_div1; /* in/out */ 3307b04cb192SNicholas Kazlauskas uint8_t is_backlight_on : 1; /* in/out */ 3308b04cb192SNicholas Kazlauskas uint8_t is_powered_on : 1; /* in/out */ 3309a91b402dSCharlene Liu uint8_t padding[3]; 3310a91b402dSCharlene Liu uint32_t bl_pwm_ref_div2; /* in/out */ 3311a91b402dSCharlene Liu uint8_t reserved[4]; 3312b04cb192SNicholas Kazlauskas }; 3313b04cb192SNicholas Kazlauskas 3314b04cb192SNicholas Kazlauskas /** 3315b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_panel_cntl - Panel control command. 3316b04cb192SNicholas Kazlauskas */ 3317b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl { 3318b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 3319b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data data; /**< payload */ 3320b04cb192SNicholas Kazlauskas }; 3321b04cb192SNicholas Kazlauskas 33221a595f28SAnthony Koo /** 33231a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 33241a595f28SAnthony Koo */ 33251a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data { 33261a595f28SAnthony Koo uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3327e0886e1fSTony Tascioglu uint8_t bypass_panel_control_wait; 33280888aa30SAnthony Koo uint8_t reserved_0[2]; /**< For future use */ 33291a595f28SAnthony Koo uint8_t panel_inst; /**< LVTMA control instance */ 33301a595f28SAnthony Koo uint8_t reserved_1[3]; /**< For future use */ 33311a595f28SAnthony Koo }; 33321a595f28SAnthony Koo 33331a595f28SAnthony Koo /** 33341a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 33351a595f28SAnthony Koo */ 33361a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control { 33371a595f28SAnthony Koo /** 33381a595f28SAnthony Koo * Command header. 33391a595f28SAnthony Koo */ 33401a595f28SAnthony Koo struct dmub_cmd_header header; 33411a595f28SAnthony Koo /** 33421a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 33431a595f28SAnthony Koo */ 33441a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data data; 33451a595f28SAnthony Koo }; 33461a595f28SAnthony Koo 3347592a6318SAnthony Koo /** 334841f91315SNicholas Kazlauskas * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 334941f91315SNicholas Kazlauskas */ 335041f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data { 335141f91315SNicholas Kazlauskas uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 335241f91315SNicholas Kazlauskas uint8_t is_usb; /**< is phy is usb */ 335341f91315SNicholas Kazlauskas uint8_t is_dp_alt_disable; /**< is dp alt disable */ 335441f91315SNicholas Kazlauskas uint8_t is_dp4; /**< is dp in 4 lane */ 335541f91315SNicholas Kazlauskas }; 335641f91315SNicholas Kazlauskas 335741f91315SNicholas Kazlauskas /** 335841f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 335941f91315SNicholas Kazlauskas */ 336041f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt { 336141f91315SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 336241f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 336341f91315SNicholas Kazlauskas }; 336441f91315SNicholas Kazlauskas 336541f91315SNicholas Kazlauskas /** 3366021eaef8SAnthony Koo * Maximum number of bytes a chunk sent to DMUB for parsing 3367021eaef8SAnthony Koo */ 3368021eaef8SAnthony Koo #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3369021eaef8SAnthony Koo 3370021eaef8SAnthony Koo /** 3371021eaef8SAnthony Koo * Represent a chunk of CEA blocks sent to DMUB for parsing 3372021eaef8SAnthony Koo */ 3373021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea { 3374021eaef8SAnthony Koo uint16_t offset; /**< offset into the CEA block */ 3375021eaef8SAnthony Koo uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3376eb9e59ebSOliver Logush uint16_t cea_total_length; /**< total length of the CEA block */ 3377021eaef8SAnthony Koo uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3378021eaef8SAnthony Koo uint8_t pad[3]; /**< padding and for future expansion */ 3379021eaef8SAnthony Koo }; 3380021eaef8SAnthony Koo 3381021eaef8SAnthony Koo /** 3382021eaef8SAnthony Koo * Result of VSDB parsing from CEA block 3383021eaef8SAnthony Koo */ 3384021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb { 3385021eaef8SAnthony Koo uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3386021eaef8SAnthony Koo uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3387021eaef8SAnthony Koo uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3388021eaef8SAnthony Koo uint16_t min_frame_rate; /**< Maximum frame rate */ 3389021eaef8SAnthony Koo uint16_t max_frame_rate; /**< Minimum frame rate */ 3390021eaef8SAnthony Koo }; 3391021eaef8SAnthony Koo 3392021eaef8SAnthony Koo /** 3393021eaef8SAnthony Koo * Result of sending a CEA chunk 3394021eaef8SAnthony Koo */ 3395021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack { 3396021eaef8SAnthony Koo uint16_t offset; /**< offset of the chunk into the CEA block */ 3397021eaef8SAnthony Koo uint8_t success; /**< 1 if this sending of chunk succeeded */ 3398021eaef8SAnthony Koo uint8_t pad; /**< padding and for future expansion */ 3399021eaef8SAnthony Koo }; 3400021eaef8SAnthony Koo 3401021eaef8SAnthony Koo /** 3402021eaef8SAnthony Koo * Specify whether the result is an ACK/NACK or the parsing has finished 3403021eaef8SAnthony Koo */ 3404021eaef8SAnthony Koo enum dmub_cmd_edid_cea_reply_type { 3405021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3406021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3407021eaef8SAnthony Koo }; 3408021eaef8SAnthony Koo 3409021eaef8SAnthony Koo /** 3410021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 3411021eaef8SAnthony Koo */ 3412021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea { 3413021eaef8SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 3414021eaef8SAnthony Koo union dmub_cmd_edid_cea_data { 3415021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3416021eaef8SAnthony Koo struct dmub_cmd_edid_cea_output { /**< output with results */ 3417021eaef8SAnthony Koo uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3418021eaef8SAnthony Koo union { 3419021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3420021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack ack; 3421021eaef8SAnthony Koo }; 3422021eaef8SAnthony Koo } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3423021eaef8SAnthony Koo } data; /**< Command data */ 3424021eaef8SAnthony Koo 3425021eaef8SAnthony Koo }; 3426021eaef8SAnthony Koo 3427021eaef8SAnthony Koo /** 3428c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3429c595fb05SWenjing Liu */ 3430c595fb05SWenjing Liu struct dmub_cmd_cable_id_input { 3431c595fb05SWenjing Liu uint8_t phy_inst; /**< phy inst for cable id data */ 3432c595fb05SWenjing Liu }; 3433c595fb05SWenjing Liu 3434c595fb05SWenjing Liu /** 3435c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3436c595fb05SWenjing Liu */ 3437c595fb05SWenjing Liu struct dmub_cmd_cable_id_output { 3438c595fb05SWenjing Liu uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3439c595fb05SWenjing Liu uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3440c595fb05SWenjing Liu uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3441c595fb05SWenjing Liu uint8_t RESERVED :2; /**< reserved means not defined */ 3442c595fb05SWenjing Liu }; 3443c595fb05SWenjing Liu 3444c595fb05SWenjing Liu /** 3445c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3446c595fb05SWenjing Liu */ 3447c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id { 3448c595fb05SWenjing Liu struct dmub_cmd_header header; /**< Command header */ 3449c595fb05SWenjing Liu /** 3450c595fb05SWenjing Liu * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3451c595fb05SWenjing Liu */ 3452c595fb05SWenjing Liu union dmub_cmd_cable_id_data { 3453c595fb05SWenjing Liu struct dmub_cmd_cable_id_input input; /**< Input */ 3454c595fb05SWenjing Liu struct dmub_cmd_cable_id_output output; /**< Output */ 3455c595fb05SWenjing Liu uint8_t output_raw; /**< Raw data output */ 3456c595fb05SWenjing Liu } data; 3457c595fb05SWenjing Liu }; 3458c595fb05SWenjing Liu 34591fb695d9SAnthony Koo /** 34601fb695d9SAnthony Koo * Command type of a DMUB_CMD__SECURE_DISPLAY command 34611fb695d9SAnthony Koo */ 3462c0459bddSAlan Liu enum dmub_cmd_secure_display_type { 34631fb695d9SAnthony Koo DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3464c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3465c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3466c0459bddSAlan Liu }; 3467c0459bddSAlan Liu 34681fb695d9SAnthony Koo /** 34691fb695d9SAnthony Koo * Definition of a DMUB_CMD__SECURE_DISPLAY command 34701fb695d9SAnthony Koo */ 3471c0459bddSAlan Liu struct dmub_rb_cmd_secure_display { 3472c0459bddSAlan Liu struct dmub_cmd_header header; 34731fb695d9SAnthony Koo /** 34741fb695d9SAnthony Koo * Data passed from driver to dmub firmware. 34751fb695d9SAnthony Koo */ 3476c0459bddSAlan Liu struct dmub_cmd_roi_info { 3477c0459bddSAlan Liu uint16_t x_start; 3478c0459bddSAlan Liu uint16_t x_end; 3479c0459bddSAlan Liu uint16_t y_start; 3480c0459bddSAlan Liu uint16_t y_end; 3481c0459bddSAlan Liu uint8_t otg_id; 3482c0459bddSAlan Liu uint8_t phy_id; 3483c0459bddSAlan Liu } roi_info; 3484c0459bddSAlan Liu }; 3485c0459bddSAlan Liu 3486c595fb05SWenjing Liu /** 3487592a6318SAnthony Koo * union dmub_rb_cmd - DMUB inbox command. 3488592a6318SAnthony Koo */ 34897c008829SNicholas Kazlauskas union dmub_rb_cmd { 3490592a6318SAnthony Koo /** 3491592a6318SAnthony Koo * Elements shared with all commands. 3492592a6318SAnthony Koo */ 34937c008829SNicholas Kazlauskas struct dmub_rb_cmd_common cmd_common; 3494592a6318SAnthony Koo /** 3495592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3496592a6318SAnthony Koo */ 3497592a6318SAnthony Koo struct dmub_rb_cmd_read_modify_write read_modify_write; 3498592a6318SAnthony Koo /** 3499592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3500592a6318SAnthony Koo */ 3501592a6318SAnthony Koo struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3502592a6318SAnthony Koo /** 3503592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3504592a6318SAnthony Koo */ 3505592a6318SAnthony Koo struct dmub_rb_cmd_burst_write burst_write; 3506592a6318SAnthony Koo /** 3507592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_REG_WAIT command. 3508592a6318SAnthony Koo */ 3509592a6318SAnthony Koo struct dmub_rb_cmd_reg_wait reg_wait; 3510592a6318SAnthony Koo /** 3511592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3512592a6318SAnthony Koo */ 35137c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3514592a6318SAnthony Koo /** 3515592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3516592a6318SAnthony Koo */ 35177c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3518592a6318SAnthony Koo /** 3519592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3520592a6318SAnthony Koo */ 35217c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3522592a6318SAnthony Koo /** 3523592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3524592a6318SAnthony Koo */ 35257c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init dpphy_init; 3526592a6318SAnthony Koo /** 3527592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3528592a6318SAnthony Koo */ 35297c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 35301a595f28SAnthony Koo /** 3531e383b127SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3532e383b127SNicholas Kazlauskas */ 3533e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control domain_control; 3534e383b127SNicholas Kazlauskas /** 35351a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 35361a595f28SAnthony Koo */ 3537d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version psr_set_version; 35381a595f28SAnthony Koo /** 35391a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 35401a595f28SAnthony Koo */ 35417c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 35421a595f28SAnthony Koo /** 35431a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 35441a595f28SAnthony Koo */ 3545d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_enable psr_enable; 35461a595f28SAnthony Koo /** 35471a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 35481a595f28SAnthony Koo */ 35497c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level psr_set_level; 35501a595f28SAnthony Koo /** 35511a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 35521a595f28SAnthony Koo */ 3553672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static psr_force_static; 3554592a6318SAnthony Koo /** 355583eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 355683eb5385SDavid Zhang */ 355783eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 355883eb5385SDavid Zhang /** 355983eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 356083eb5385SDavid Zhang */ 356183eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info update_cursor_info; 356283eb5385SDavid Zhang /** 356383eb5385SDavid Zhang * Definition of a DMUB_CMD__HW_LOCK command. 356483eb5385SDavid Zhang * Command is used by driver and FW. 356583eb5385SDavid Zhang */ 356683eb5385SDavid Zhang struct dmub_rb_cmd_lock_hw lock_hw; 356783eb5385SDavid Zhang /** 356883eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 356983eb5385SDavid Zhang */ 357083eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 357183eb5385SDavid Zhang /** 3572e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3573e5dfcd27SRobin Chen */ 3574e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3575e5dfcd27SRobin Chen /** 3576592a6318SAnthony Koo * Definition of a DMUB_CMD__PLAT_54186_WA command. 3577592a6318SAnthony Koo */ 3578bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3579592a6318SAnthony Koo /** 3580592a6318SAnthony Koo * Definition of a DMUB_CMD__MALL command. 3581592a6318SAnthony Koo */ 358252f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall mall; 3583b04cb192SNicholas Kazlauskas /** 3584ac2e555eSAurabindo Pillai * Definition of a DMUB_CMD__CAB command. 3585ac2e555eSAurabindo Pillai */ 3586ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss cab; 358785f4bc0cSAlvin Lee 358885f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 358985f4bc0cSAlvin Lee 3590ac2e555eSAurabindo Pillai /** 3591b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3592b04cb192SNicholas Kazlauskas */ 3593b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3594b04cb192SNicholas Kazlauskas 3595b04cb192SNicholas Kazlauskas /** 3596b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3597b04cb192SNicholas Kazlauskas */ 3598b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3599b04cb192SNicholas Kazlauskas 3600b04cb192SNicholas Kazlauskas /** 3601b04cb192SNicholas Kazlauskas * Definition of DMUB_CMD__PANEL_CNTL commands. 3602b04cb192SNicholas Kazlauskas */ 3603b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl panel_cntl; 36041a595f28SAnthony Koo /** 36051a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 36061a595f28SAnthony Koo */ 3607e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 36081a595f28SAnthony Koo 36091a595f28SAnthony Koo /** 36101a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 36111a595f28SAnthony Koo */ 3612e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 36131a595f28SAnthony Koo 36141a595f28SAnthony Koo /** 36151a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 36161a595f28SAnthony Koo */ 3617e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level abm_set_level; 36181a595f28SAnthony Koo 36191a595f28SAnthony Koo /** 36201a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 36211a595f28SAnthony Koo */ 3622e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 36231a595f28SAnthony Koo 36241a595f28SAnthony Koo /** 36251a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 36261a595f28SAnthony Koo */ 3627e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 36281a595f28SAnthony Koo 36291a595f28SAnthony Koo /** 36301a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 36311a595f28SAnthony Koo */ 363216012806SWyatt Wood struct dmub_rb_cmd_abm_init_config abm_init_config; 36331a595f28SAnthony Koo 36341a595f28SAnthony Koo /** 3635b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 3636b629a824SEric Yang */ 3637b629a824SEric Yang struct dmub_rb_cmd_abm_pause abm_pause; 3638b629a824SEric Yang 3639b629a824SEric Yang /** 3640da915efaSReza Amini * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 3641da915efaSReza Amini */ 3642da915efaSReza Amini struct dmub_rb_cmd_abm_save_restore abm_save_restore; 3643da915efaSReza Amini 3644da915efaSReza Amini /** 36451a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 36461a595f28SAnthony Koo */ 3647d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access dp_aux_access; 36481a595f28SAnthony Koo 36491a595f28SAnthony Koo /** 3650592a6318SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3651592a6318SAnthony Koo */ 3652592a6318SAnthony Koo struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3653592a6318SAnthony Koo 3654592a6318SAnthony Koo /** 3655592a6318SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 36561a595f28SAnthony Koo */ 365734ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3658b09c1fffSLeo (Hanghong) Ma 3659b09c1fffSLeo (Hanghong) Ma /** 3660b09c1fffSLeo (Hanghong) Ma * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3661b09c1fffSLeo (Hanghong) Ma */ 3662b09c1fffSLeo (Hanghong) Ma struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3663592a6318SAnthony Koo struct dmub_rb_cmd_drr_update drr_update; 366400fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 366500fa7f03SRodrigo Siqueira 36661a595f28SAnthony Koo /** 36671a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 36681a595f28SAnthony Koo */ 36691a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control lvtma_control; 3670021eaef8SAnthony Koo /** 367141f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 367241f91315SNicholas Kazlauskas */ 367341f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 367441f91315SNicholas Kazlauskas /** 367576724b76SJimmy Kizito * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 367676724b76SJimmy Kizito */ 367776724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 367876724b76SJimmy Kizito /** 367971af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 368071af9d46SMeenakshikumar Somasundaram */ 368171af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access set_config_access; 368271af9d46SMeenakshikumar Somasundaram /** 3683139a3311SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3684139a3311SMeenakshikumar Somasundaram */ 3685139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3686139a3311SMeenakshikumar Somasundaram /** 3687021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 3688021eaef8SAnthony Koo */ 3689021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea edid_cea; 3690c595fb05SWenjing Liu /** 3691c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3692c595fb05SWenjing Liu */ 3693c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3694ea5a4db9SAnthony Koo 3695ea5a4db9SAnthony Koo /** 3696ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3697ea5a4db9SAnthony Koo */ 3698ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state query_hpd; 36996f4f8ff5SMeenakshikumar Somasundaram /** 3700c0459bddSAlan Liu * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3701c0459bddSAlan Liu */ 3702c0459bddSAlan Liu struct dmub_rb_cmd_secure_display secure_display; 37031fb695d9SAnthony Koo 3704c0459bddSAlan Liu /** 37056f4f8ff5SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 37066f4f8ff5SMeenakshikumar Somasundaram */ 37076f4f8ff5SMeenakshikumar Somasundaram struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 370827664177SAnthony Koo /** 370927664177SAnthony Koo * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 371027664177SAnthony Koo */ 371127664177SAnthony Koo struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 37127c008829SNicholas Kazlauskas }; 37137c008829SNicholas Kazlauskas 3714592a6318SAnthony Koo /** 3715592a6318SAnthony Koo * union dmub_rb_out_cmd - Outbox command 3716592a6318SAnthony Koo */ 3717d9beecfcSAnthony Koo union dmub_rb_out_cmd { 3718592a6318SAnthony Koo /** 3719592a6318SAnthony Koo * Parameters common to every command. 3720592a6318SAnthony Koo */ 3721d9beecfcSAnthony Koo struct dmub_rb_cmd_common cmd_common; 3722592a6318SAnthony Koo /** 3723592a6318SAnthony Koo * AUX reply command. 3724592a6318SAnthony Koo */ 3725d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3726592a6318SAnthony Koo /** 3727592a6318SAnthony Koo * HPD notify command. 3728592a6318SAnthony Koo */ 3729d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 373071af9d46SMeenakshikumar Somasundaram /** 373171af9d46SMeenakshikumar Somasundaram * SET_CONFIG reply command. 373271af9d46SMeenakshikumar Somasundaram */ 373371af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3734669018a9SMustapha Ghaddar /** 37358af54c61SMustapha Ghaddar * DPIA notification command. 3736669018a9SMustapha Ghaddar */ 37378af54c61SMustapha Ghaddar struct dmub_rb_cmd_dpia_notification dpia_notification; 3738d9beecfcSAnthony Koo }; 37397c008829SNicholas Kazlauskas #pragma pack(pop) 37407c008829SNicholas Kazlauskas 374184034ad4SAnthony Koo 374284034ad4SAnthony Koo //============================================================================== 374384034ad4SAnthony Koo //</DMUB_CMD>=================================================================== 374484034ad4SAnthony Koo //============================================================================== 374584034ad4SAnthony Koo //< DMUB_RB>==================================================================== 374684034ad4SAnthony Koo //============================================================================== 374784034ad4SAnthony Koo 374884034ad4SAnthony Koo #if defined(__cplusplus) 374984034ad4SAnthony Koo extern "C" { 375084034ad4SAnthony Koo #endif 375184034ad4SAnthony Koo 3752592a6318SAnthony Koo /** 3753592a6318SAnthony Koo * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3754592a6318SAnthony Koo */ 375584034ad4SAnthony Koo struct dmub_rb_init_params { 3756592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 3757592a6318SAnthony Koo void *base_address; /**< CPU base address for ring's data */ 3758592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3759592a6318SAnthony Koo uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3760592a6318SAnthony Koo uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 376184034ad4SAnthony Koo }; 376284034ad4SAnthony Koo 3763592a6318SAnthony Koo /** 3764592a6318SAnthony Koo * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3765592a6318SAnthony Koo */ 376684034ad4SAnthony Koo struct dmub_rb { 3767592a6318SAnthony Koo void *base_address; /**< CPU address for the ring's data */ 3768592a6318SAnthony Koo uint32_t rptr; /**< Read pointer for consumer in bytes */ 3769592a6318SAnthony Koo uint32_t wrpt; /**< Write pointer for producer in bytes */ 3770592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 377184034ad4SAnthony Koo 3772592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 3773592a6318SAnthony Koo void *dmub; /**< Pointer to the DMUB interface */ 377484034ad4SAnthony Koo }; 377584034ad4SAnthony Koo 3776592a6318SAnthony Koo /** 3777592a6318SAnthony Koo * @brief Checks if the ringbuffer is empty. 3778592a6318SAnthony Koo * 3779592a6318SAnthony Koo * @param rb DMUB Ringbuffer 3780592a6318SAnthony Koo * @return true if empty 3781592a6318SAnthony Koo * @return false otherwise 3782592a6318SAnthony Koo */ 378384034ad4SAnthony Koo static inline bool dmub_rb_empty(struct dmub_rb *rb) 378484034ad4SAnthony Koo { 378584034ad4SAnthony Koo return (rb->wrpt == rb->rptr); 378684034ad4SAnthony Koo } 378784034ad4SAnthony Koo 3788592a6318SAnthony Koo /** 3789592a6318SAnthony Koo * @brief Checks if the ringbuffer is full 3790592a6318SAnthony Koo * 3791592a6318SAnthony Koo * @param rb DMUB Ringbuffer 3792592a6318SAnthony Koo * @return true if full 3793592a6318SAnthony Koo * @return false otherwise 3794592a6318SAnthony Koo */ 379584034ad4SAnthony Koo static inline bool dmub_rb_full(struct dmub_rb *rb) 379684034ad4SAnthony Koo { 379784034ad4SAnthony Koo uint32_t data_count; 379884034ad4SAnthony Koo 379984034ad4SAnthony Koo if (rb->wrpt >= rb->rptr) 380084034ad4SAnthony Koo data_count = rb->wrpt - rb->rptr; 380184034ad4SAnthony Koo else 380284034ad4SAnthony Koo data_count = rb->capacity - (rb->rptr - rb->wrpt); 380384034ad4SAnthony Koo 380484034ad4SAnthony Koo return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 380584034ad4SAnthony Koo } 380684034ad4SAnthony Koo 3807592a6318SAnthony Koo /** 3808592a6318SAnthony Koo * @brief Pushes a command into the ringbuffer 3809592a6318SAnthony Koo * 3810592a6318SAnthony Koo * @param rb DMUB ringbuffer 3811592a6318SAnthony Koo * @param cmd The command to push 3812592a6318SAnthony Koo * @return true if the ringbuffer was not full 3813592a6318SAnthony Koo * @return false otherwise 3814592a6318SAnthony Koo */ 381584034ad4SAnthony Koo static inline bool dmub_rb_push_front(struct dmub_rb *rb, 381684034ad4SAnthony Koo const union dmub_rb_cmd *cmd) 381784034ad4SAnthony Koo { 38183f232a0fSAnthony Koo uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 38193a9d5b0bSAnthony Koo const uint64_t *src = (const uint64_t *)cmd; 38203a9d5b0bSAnthony Koo uint8_t i; 382184034ad4SAnthony Koo 382284034ad4SAnthony Koo if (dmub_rb_full(rb)) 382384034ad4SAnthony Koo return false; 382484034ad4SAnthony Koo 382584034ad4SAnthony Koo // copying data 38263a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 38273a9d5b0bSAnthony Koo *dst++ = *src++; 382884034ad4SAnthony Koo 382984034ad4SAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 383084034ad4SAnthony Koo 383184034ad4SAnthony Koo if (rb->wrpt >= rb->capacity) 383284034ad4SAnthony Koo rb->wrpt %= rb->capacity; 383384034ad4SAnthony Koo 383484034ad4SAnthony Koo return true; 383584034ad4SAnthony Koo } 383684034ad4SAnthony Koo 3837592a6318SAnthony Koo /** 3838592a6318SAnthony Koo * @brief Pushes a command into the DMUB outbox ringbuffer 3839592a6318SAnthony Koo * 3840592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 3841592a6318SAnthony Koo * @param cmd Outbox command 3842592a6318SAnthony Koo * @return true if not full 3843592a6318SAnthony Koo * @return false otherwise 3844592a6318SAnthony Koo */ 3845d9beecfcSAnthony Koo static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3846d9beecfcSAnthony Koo const union dmub_rb_out_cmd *cmd) 3847d9beecfcSAnthony Koo { 3848d9beecfcSAnthony Koo uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3849d459b79bSAnthony Koo const uint8_t *src = (const uint8_t *)cmd; 3850d9beecfcSAnthony Koo 3851d9beecfcSAnthony Koo if (dmub_rb_full(rb)) 3852d9beecfcSAnthony Koo return false; 3853d9beecfcSAnthony Koo 3854d9beecfcSAnthony Koo dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3855d9beecfcSAnthony Koo 3856d9beecfcSAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 3857d9beecfcSAnthony Koo 3858d9beecfcSAnthony Koo if (rb->wrpt >= rb->capacity) 3859d9beecfcSAnthony Koo rb->wrpt %= rb->capacity; 3860d9beecfcSAnthony Koo 3861d9beecfcSAnthony Koo return true; 3862d9beecfcSAnthony Koo } 3863d9beecfcSAnthony Koo 3864592a6318SAnthony Koo /** 3865592a6318SAnthony Koo * @brief Returns the next unprocessed command in the ringbuffer. 3866592a6318SAnthony Koo * 3867592a6318SAnthony Koo * @param rb DMUB ringbuffer 3868592a6318SAnthony Koo * @param cmd The command to return 3869592a6318SAnthony Koo * @return true if not empty 3870592a6318SAnthony Koo * @return false otherwise 3871592a6318SAnthony Koo */ 387284034ad4SAnthony Koo static inline bool dmub_rb_front(struct dmub_rb *rb, 387334ba432cSAnthony Koo union dmub_rb_cmd **cmd) 387484034ad4SAnthony Koo { 387534ba432cSAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 387684034ad4SAnthony Koo 387784034ad4SAnthony Koo if (dmub_rb_empty(rb)) 387884034ad4SAnthony Koo return false; 387984034ad4SAnthony Koo 388034ba432cSAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 388184034ad4SAnthony Koo 388284034ad4SAnthony Koo return true; 388384034ad4SAnthony Koo } 388484034ad4SAnthony Koo 3885592a6318SAnthony Koo /** 38860b51e7e8SAnthony Koo * @brief Determines the next ringbuffer offset. 38870b51e7e8SAnthony Koo * 38880b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 38890b51e7e8SAnthony Koo * @param num_cmds Number of commands 38900b51e7e8SAnthony Koo * @param next_rptr The next offset in the ringbuffer 38910b51e7e8SAnthony Koo */ 38920b51e7e8SAnthony Koo static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 38930b51e7e8SAnthony Koo uint32_t num_cmds, 38940b51e7e8SAnthony Koo uint32_t *next_rptr) 38950b51e7e8SAnthony Koo { 38960b51e7e8SAnthony Koo *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 38970b51e7e8SAnthony Koo 38980b51e7e8SAnthony Koo if (*next_rptr >= rb->capacity) 38990b51e7e8SAnthony Koo *next_rptr %= rb->capacity; 39000b51e7e8SAnthony Koo } 39010b51e7e8SAnthony Koo 39020b51e7e8SAnthony Koo /** 39030b51e7e8SAnthony Koo * @brief Returns a pointer to a command in the inbox. 39040b51e7e8SAnthony Koo * 39050b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 39060b51e7e8SAnthony Koo * @param cmd The inbox command to return 39070b51e7e8SAnthony Koo * @param rptr The ringbuffer offset 39080b51e7e8SAnthony Koo * @return true if not empty 39090b51e7e8SAnthony Koo * @return false otherwise 39100b51e7e8SAnthony Koo */ 39110b51e7e8SAnthony Koo static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 39120b51e7e8SAnthony Koo union dmub_rb_cmd **cmd, 39130b51e7e8SAnthony Koo uint32_t rptr) 39140b51e7e8SAnthony Koo { 39150b51e7e8SAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 39160b51e7e8SAnthony Koo 39170b51e7e8SAnthony Koo if (dmub_rb_empty(rb)) 39180b51e7e8SAnthony Koo return false; 39190b51e7e8SAnthony Koo 39200b51e7e8SAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 39210b51e7e8SAnthony Koo 39220b51e7e8SAnthony Koo return true; 39230b51e7e8SAnthony Koo } 39240b51e7e8SAnthony Koo 39250b51e7e8SAnthony Koo /** 3926592a6318SAnthony Koo * @brief Returns the next unprocessed command in the outbox. 3927592a6318SAnthony Koo * 3928592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 3929592a6318SAnthony Koo * @param cmd The outbox command to return 3930592a6318SAnthony Koo * @return true if not empty 3931592a6318SAnthony Koo * @return false otherwise 3932592a6318SAnthony Koo */ 3933d9beecfcSAnthony Koo static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3934d9beecfcSAnthony Koo union dmub_rb_out_cmd *cmd) 3935d9beecfcSAnthony Koo { 39363f232a0fSAnthony Koo const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 39373a9d5b0bSAnthony Koo uint64_t *dst = (uint64_t *)cmd; 39383a9d5b0bSAnthony Koo uint8_t i; 3939d9beecfcSAnthony Koo 3940d9beecfcSAnthony Koo if (dmub_rb_empty(rb)) 3941d9beecfcSAnthony Koo return false; 3942d9beecfcSAnthony Koo 3943d9beecfcSAnthony Koo // copying data 39443a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 39453a9d5b0bSAnthony Koo *dst++ = *src++; 3946d9beecfcSAnthony Koo 3947d9beecfcSAnthony Koo return true; 3948d9beecfcSAnthony Koo } 3949d9beecfcSAnthony Koo 3950592a6318SAnthony Koo /** 3951592a6318SAnthony Koo * @brief Removes the front entry in the ringbuffer. 3952592a6318SAnthony Koo * 3953592a6318SAnthony Koo * @param rb DMUB ringbuffer 3954592a6318SAnthony Koo * @return true if the command was removed 3955592a6318SAnthony Koo * @return false if there were no commands 3956592a6318SAnthony Koo */ 395784034ad4SAnthony Koo static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 395884034ad4SAnthony Koo { 395984034ad4SAnthony Koo if (dmub_rb_empty(rb)) 396084034ad4SAnthony Koo return false; 396184034ad4SAnthony Koo 396284034ad4SAnthony Koo rb->rptr += DMUB_RB_CMD_SIZE; 396384034ad4SAnthony Koo 396484034ad4SAnthony Koo if (rb->rptr >= rb->capacity) 396584034ad4SAnthony Koo rb->rptr %= rb->capacity; 396684034ad4SAnthony Koo 396784034ad4SAnthony Koo return true; 396884034ad4SAnthony Koo } 396984034ad4SAnthony Koo 3970592a6318SAnthony Koo /** 3971592a6318SAnthony Koo * @brief Flushes commands in the ringbuffer to framebuffer memory. 3972592a6318SAnthony Koo * 3973592a6318SAnthony Koo * Avoids a race condition where DMCUB accesses memory while 3974592a6318SAnthony Koo * there are still writes in flight to framebuffer. 3975592a6318SAnthony Koo * 3976592a6318SAnthony Koo * @param rb DMUB ringbuffer 3977592a6318SAnthony Koo */ 397884034ad4SAnthony Koo static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 397984034ad4SAnthony Koo { 398084034ad4SAnthony Koo uint32_t rptr = rb->rptr; 398184034ad4SAnthony Koo uint32_t wptr = rb->wrpt; 398284034ad4SAnthony Koo 398384034ad4SAnthony Koo while (rptr != wptr) { 39847da7b02eSAashish Sharma uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 39853a9d5b0bSAnthony Koo uint8_t i; 398684034ad4SAnthony Koo 398723da6e0fSMaíra Canal /* Don't remove this. 398823da6e0fSMaíra Canal * The contents need to actually be read from the ring buffer 398923da6e0fSMaíra Canal * for this function to be effective. 399023da6e0fSMaíra Canal */ 39913a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 39927da7b02eSAashish Sharma (void)READ_ONCE(*data++); 399384034ad4SAnthony Koo 399484034ad4SAnthony Koo rptr += DMUB_RB_CMD_SIZE; 399584034ad4SAnthony Koo if (rptr >= rb->capacity) 399684034ad4SAnthony Koo rptr %= rb->capacity; 399784034ad4SAnthony Koo } 399884034ad4SAnthony Koo } 399984034ad4SAnthony Koo 4000592a6318SAnthony Koo /** 4001592a6318SAnthony Koo * @brief Initializes a DMCUB ringbuffer 4002592a6318SAnthony Koo * 4003592a6318SAnthony Koo * @param rb DMUB ringbuffer 4004592a6318SAnthony Koo * @param init_params initial configuration for the ringbuffer 4005592a6318SAnthony Koo */ 400684034ad4SAnthony Koo static inline void dmub_rb_init(struct dmub_rb *rb, 400784034ad4SAnthony Koo struct dmub_rb_init_params *init_params) 400884034ad4SAnthony Koo { 400984034ad4SAnthony Koo rb->base_address = init_params->base_address; 401084034ad4SAnthony Koo rb->capacity = init_params->capacity; 401184034ad4SAnthony Koo rb->rptr = init_params->read_ptr; 401284034ad4SAnthony Koo rb->wrpt = init_params->write_ptr; 401384034ad4SAnthony Koo } 401484034ad4SAnthony Koo 4015592a6318SAnthony Koo /** 4016592a6318SAnthony Koo * @brief Copies output data from in/out commands into the given command. 4017592a6318SAnthony Koo * 4018592a6318SAnthony Koo * @param rb DMUB ringbuffer 4019592a6318SAnthony Koo * @param cmd Command to copy data into 4020592a6318SAnthony Koo */ 402134ba432cSAnthony Koo static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 402234ba432cSAnthony Koo union dmub_rb_cmd *cmd) 402334ba432cSAnthony Koo { 402434ba432cSAnthony Koo // Copy rb entry back into command 402534ba432cSAnthony Koo uint8_t *rd_ptr = (rb->rptr == 0) ? 402634ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 402734ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 402834ba432cSAnthony Koo 402934ba432cSAnthony Koo dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 403034ba432cSAnthony Koo } 403134ba432cSAnthony Koo 403284034ad4SAnthony Koo #if defined(__cplusplus) 403384034ad4SAnthony Koo } 403484034ad4SAnthony Koo #endif 403584034ad4SAnthony Koo 403684034ad4SAnthony Koo //============================================================================== 403784034ad4SAnthony Koo //</DMUB_RB>==================================================================== 403884034ad4SAnthony Koo //============================================================================== 403984034ad4SAnthony Koo 40407c008829SNicholas Kazlauskas #endif /* _DMUB_CMD_H_ */ 4041