17c008829SNicholas Kazlauskas /* 27c008829SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 37c008829SNicholas Kazlauskas * 47c008829SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 57c008829SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 67c008829SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 77c008829SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87c008829SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 97c008829SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 107c008829SNicholas Kazlauskas * 117c008829SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 127c008829SNicholas Kazlauskas * all copies or substantial portions of the Software. 137c008829SNicholas Kazlauskas * 147c008829SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157c008829SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167c008829SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177c008829SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187c008829SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197c008829SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207c008829SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 217c008829SNicholas Kazlauskas * 227c008829SNicholas Kazlauskas * Authors: AMD 237c008829SNicholas Kazlauskas * 247c008829SNicholas Kazlauskas */ 257c008829SNicholas Kazlauskas 265624c345SAnthony Koo #ifndef DMUB_CMD_H 275624c345SAnthony Koo #define DMUB_CMD_H 287c008829SNicholas Kazlauskas 298b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 308b19a4e3SAnthony Koo #include "dmub_fw_types.h" 318b19a4e3SAnthony Koo #include "include_legacy/atomfirmware.h" 328b19a4e3SAnthony Koo 338b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) 348b19a4e3SAnthony Koo #include <string.h> 358b19a4e3SAnthony Koo #endif 368b19a4e3SAnthony Koo #else 378b19a4e3SAnthony Koo 3884034ad4SAnthony Koo #include <asm/byteorder.h> 3984034ad4SAnthony Koo #include <linux/types.h> 4084034ad4SAnthony Koo #include <linux/string.h> 4184034ad4SAnthony Koo #include <linux/delay.h> 4284034ad4SAnthony Koo 437c008829SNicholas Kazlauskas #include "atomfirmware.h" 4422aa5614SYongqiang Sun 458b19a4e3SAnthony Koo #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 468b19a4e3SAnthony Koo 4784034ad4SAnthony Koo //<DMUB_TYPES>================================================================== 4884034ad4SAnthony Koo /* Basic type definitions. */ 4984034ad4SAnthony Koo 508b19a4e3SAnthony Koo #define __forceinline inline 518b19a4e3SAnthony Koo 521a595f28SAnthony Koo /** 531a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled gradually 541a595f28SAnthony Koo * by slowly reversing all backlight programming and pixel compensation. 551a595f28SAnthony Koo */ 5684034ad4SAnthony Koo #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 571a595f28SAnthony Koo 581a595f28SAnthony Koo /** 591a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 601a595f28SAnthony Koo * and undo all backlight programming and pixel compensation. 611a595f28SAnthony Koo */ 6284034ad4SAnthony Koo #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 631a595f28SAnthony Koo 641a595f28SAnthony Koo /** 651a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 661a595f28SAnthony Koo * and keep the current backlight programming and pixel compensation. 671a595f28SAnthony Koo */ 68d9beecfcSAnthony Koo #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 691a595f28SAnthony Koo 701a595f28SAnthony Koo /** 711a595f28SAnthony Koo * Flag from driver to set the current ABM pipe index or ABM operating level. 721a595f28SAnthony Koo */ 7384034ad4SAnthony Koo #define SET_ABM_PIPE_NORMAL 1 7484034ad4SAnthony Koo 751a595f28SAnthony Koo /** 761a595f28SAnthony Koo * Number of ambient light levels in ABM algorithm. 771a595f28SAnthony Koo */ 781a595f28SAnthony Koo #define NUM_AMBI_LEVEL 5 791a595f28SAnthony Koo 801a595f28SAnthony Koo /** 811a595f28SAnthony Koo * Number of operating/aggression levels in ABM algorithm. 821a595f28SAnthony Koo */ 831a595f28SAnthony Koo #define NUM_AGGR_LEVEL 4 841a595f28SAnthony Koo 851a595f28SAnthony Koo /** 861a595f28SAnthony Koo * Number of segments in the gamma curve. 871a595f28SAnthony Koo */ 881a595f28SAnthony Koo #define NUM_POWER_FN_SEGS 8 891a595f28SAnthony Koo 901a595f28SAnthony Koo /** 911a595f28SAnthony Koo * Number of segments in the backlight curve. 921a595f28SAnthony Koo */ 931a595f28SAnthony Koo #define NUM_BL_CURVE_SEGS 16 941a595f28SAnthony Koo 9585f4bc0cSAlvin Lee /* Maximum number of SubVP streams */ 9685f4bc0cSAlvin Lee #define DMUB_MAX_SUBVP_STREAMS 2 9785f4bc0cSAlvin Lee 9884034ad4SAnthony Koo /* Maximum number of streams on any ASIC. */ 9984034ad4SAnthony Koo #define DMUB_MAX_STREAMS 6 10084034ad4SAnthony Koo 10184034ad4SAnthony Koo /* Maximum number of planes on any ASIC. */ 10284034ad4SAnthony Koo #define DMUB_MAX_PLANES 6 10384034ad4SAnthony Koo 10470732504SYongqiang Sun /* Trace buffer offset for entry */ 10570732504SYongqiang Sun #define TRACE_BUFFER_ENTRY_OFFSET 16 10670732504SYongqiang Sun 107592a6318SAnthony Koo /** 10883eb5385SDavid Zhang * Maximum number of dirty rects supported by FW. 10983eb5385SDavid Zhang */ 11083eb5385SDavid Zhang #define DMUB_MAX_DIRTY_RECTS 3 11183eb5385SDavid Zhang 11283eb5385SDavid Zhang /** 113f56c837aSMikita Lipski * 114f56c837aSMikita Lipski * PSR control version legacy 115f56c837aSMikita Lipski */ 116f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117f56c837aSMikita Lipski /** 118f56c837aSMikita Lipski * PSR control version with multi edp support 119f56c837aSMikita Lipski */ 120f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121f56c837aSMikita Lipski 122f56c837aSMikita Lipski 123f56c837aSMikita Lipski /** 12463de4f04SJake Wang * ABM control version legacy 125e922057bSJake Wang */ 12663de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127e922057bSJake Wang 128e922057bSJake Wang /** 12963de4f04SJake Wang * ABM control version with multi edp support 130e922057bSJake Wang */ 13163de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132e922057bSJake Wang 133e922057bSJake Wang /** 134592a6318SAnthony Koo * Physical framebuffer address location, 64-bit. 135592a6318SAnthony Koo */ 13684034ad4SAnthony Koo #ifndef PHYSICAL_ADDRESS_LOC 13784034ad4SAnthony Koo #define PHYSICAL_ADDRESS_LOC union large_integer 13884034ad4SAnthony Koo #endif 13984034ad4SAnthony Koo 140592a6318SAnthony Koo /** 141592a6318SAnthony Koo * OS/FW agnostic memcpy 142592a6318SAnthony Koo */ 14384034ad4SAnthony Koo #ifndef dmub_memcpy 14484034ad4SAnthony Koo #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 14584034ad4SAnthony Koo #endif 14684034ad4SAnthony Koo 147592a6318SAnthony Koo /** 148592a6318SAnthony Koo * OS/FW agnostic memset 149592a6318SAnthony Koo */ 15084034ad4SAnthony Koo #ifndef dmub_memset 15184034ad4SAnthony Koo #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 15284034ad4SAnthony Koo #endif 15384034ad4SAnthony Koo 154d9beecfcSAnthony Koo #if defined(__cplusplus) 155d9beecfcSAnthony Koo extern "C" { 156d9beecfcSAnthony Koo #endif 157d9beecfcSAnthony Koo 158592a6318SAnthony Koo /** 159592a6318SAnthony Koo * OS/FW agnostic udelay 160592a6318SAnthony Koo */ 16184034ad4SAnthony Koo #ifndef dmub_udelay 16284034ad4SAnthony Koo #define dmub_udelay(microseconds) udelay(microseconds) 16384034ad4SAnthony Koo #endif 16484034ad4SAnthony Koo 1656e60cba6SJonathan Gray #pragma pack(push, 1) 166592a6318SAnthony Koo /** 167592a6318SAnthony Koo * union dmub_addr - DMUB physical/virtual 64-bit address. 168592a6318SAnthony Koo */ 16984034ad4SAnthony Koo union dmub_addr { 17084034ad4SAnthony Koo struct { 171592a6318SAnthony Koo uint32_t low_part; /**< Lower 32 bits */ 172592a6318SAnthony Koo uint32_t high_part; /**< Upper 32 bits */ 173592a6318SAnthony Koo } u; /*<< Low/high bit access */ 174592a6318SAnthony Koo uint64_t quad_part; /*<< 64 bit address */ 17584034ad4SAnthony Koo }; 1766e60cba6SJonathan Gray #pragma pack(pop) 17784034ad4SAnthony Koo 1781a595f28SAnthony Koo /** 17983eb5385SDavid Zhang * Dirty rect definition. 18083eb5385SDavid Zhang */ 18183eb5385SDavid Zhang struct dmub_rect { 18283eb5385SDavid Zhang /** 18383eb5385SDavid Zhang * Dirty rect x offset. 18483eb5385SDavid Zhang */ 18583eb5385SDavid Zhang uint32_t x; 18683eb5385SDavid Zhang 18783eb5385SDavid Zhang /** 18883eb5385SDavid Zhang * Dirty rect y offset. 18983eb5385SDavid Zhang */ 19083eb5385SDavid Zhang uint32_t y; 19183eb5385SDavid Zhang 19283eb5385SDavid Zhang /** 19383eb5385SDavid Zhang * Dirty rect width. 19483eb5385SDavid Zhang */ 19583eb5385SDavid Zhang uint32_t width; 19683eb5385SDavid Zhang 19783eb5385SDavid Zhang /** 19883eb5385SDavid Zhang * Dirty rect height. 19983eb5385SDavid Zhang */ 20083eb5385SDavid Zhang uint32_t height; 20183eb5385SDavid Zhang }; 20283eb5385SDavid Zhang 20383eb5385SDavid Zhang /** 2041a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 2051a595f28SAnthony Koo */ 20684034ad4SAnthony Koo union dmub_psr_debug_flags { 2071a595f28SAnthony Koo /** 2081a595f28SAnthony Koo * Debug flags. 2091a595f28SAnthony Koo */ 21084034ad4SAnthony Koo struct { 2111a595f28SAnthony Koo /** 2121a595f28SAnthony Koo * Enable visual confirm in FW. 2131a595f28SAnthony Koo */ 214447f3d0fSAnthony Koo uint32_t visual_confirm : 1; 21583eb5385SDavid Zhang 21683eb5385SDavid Zhang /** 21783eb5385SDavid Zhang * Force all selective updates to bw full frame updates. 21883eb5385SDavid Zhang */ 21983eb5385SDavid Zhang uint32_t force_full_frame_update : 1; 22083eb5385SDavid Zhang 2211a595f28SAnthony Koo /** 2221a595f28SAnthony Koo * Use HW Lock Mgr object to do HW locking in FW. 2231a595f28SAnthony Koo */ 224447f3d0fSAnthony Koo uint32_t use_hw_lock_mgr : 1; 2251a595f28SAnthony Koo 2261a595f28SAnthony Koo /** 227548f2125SRobin Chen * Use TPS3 signal when restore main link. 2281a595f28SAnthony Koo */ 229548f2125SRobin Chen uint32_t force_wakeup_by_tps3 : 1; 230cf472dbdSAnthony Koo 231cf472dbdSAnthony Koo /** 232cf472dbdSAnthony Koo * Back to back flip, therefore cannot power down PHY 233cf472dbdSAnthony Koo */ 234cf472dbdSAnthony Koo uint32_t back_to_back_flip : 1; 235cf472dbdSAnthony Koo 23684034ad4SAnthony Koo } bitfields; 23784034ad4SAnthony Koo 2381a595f28SAnthony Koo /** 2391a595f28SAnthony Koo * Union for debug flags. 2401a595f28SAnthony Koo */ 241447f3d0fSAnthony Koo uint32_t u32All; 24284034ad4SAnthony Koo }; 24384034ad4SAnthony Koo 2441a595f28SAnthony Koo /** 2450991f44cSAnthony Koo * DMUB visual confirm color 2461a595f28SAnthony Koo */ 24734ba432cSAnthony Koo struct dmub_feature_caps { 2481a595f28SAnthony Koo /** 2491a595f28SAnthony Koo * Max PSR version supported by FW. 2501a595f28SAnthony Koo */ 25134ba432cSAnthony Koo uint8_t psr; 25200fa7f03SRodrigo Siqueira uint8_t fw_assisted_mclk_switch; 25300fa7f03SRodrigo Siqueira uint8_t reserved[6]; 25434ba432cSAnthony Koo }; 25534ba432cSAnthony Koo 256b09c1fffSLeo (Hanghong) Ma struct dmub_visual_confirm_color { 257b09c1fffSLeo (Hanghong) Ma /** 258b09c1fffSLeo (Hanghong) Ma * Maximum 10 bits color value 259b09c1fffSLeo (Hanghong) Ma */ 260b09c1fffSLeo (Hanghong) Ma uint16_t color_r_cr; 261b09c1fffSLeo (Hanghong) Ma uint16_t color_g_y; 262b09c1fffSLeo (Hanghong) Ma uint16_t color_b_cb; 263b09c1fffSLeo (Hanghong) Ma uint16_t panel_inst; 264b09c1fffSLeo (Hanghong) Ma }; 265b09c1fffSLeo (Hanghong) Ma 26684034ad4SAnthony Koo #if defined(__cplusplus) 26784034ad4SAnthony Koo } 26884034ad4SAnthony Koo #endif 26984034ad4SAnthony Koo 27084034ad4SAnthony Koo //============================================================================== 27184034ad4SAnthony Koo //</DMUB_TYPES>================================================================= 27284034ad4SAnthony Koo //============================================================================== 27384034ad4SAnthony Koo //< DMUB_META>================================================================== 27484034ad4SAnthony Koo //============================================================================== 27584034ad4SAnthony Koo #pragma pack(push, 1) 27684034ad4SAnthony Koo 27784034ad4SAnthony Koo /* Magic value for identifying dmub_fw_meta_info */ 27884034ad4SAnthony Koo #define DMUB_FW_META_MAGIC 0x444D5542 27984034ad4SAnthony Koo 28084034ad4SAnthony Koo /* Offset from the end of the file to the dmub_fw_meta_info */ 28184034ad4SAnthony Koo #define DMUB_FW_META_OFFSET 0x24 28284034ad4SAnthony Koo 28384034ad4SAnthony Koo /** 28484034ad4SAnthony Koo * struct dmub_fw_meta_info - metadata associated with fw binary 28584034ad4SAnthony Koo * 28684034ad4SAnthony Koo * NOTE: This should be considered a stable API. Fields should 28784034ad4SAnthony Koo * not be repurposed or reordered. New fields should be 28884034ad4SAnthony Koo * added instead to extend the structure. 28984034ad4SAnthony Koo * 29084034ad4SAnthony Koo * @magic_value: magic value identifying DMUB firmware meta info 29184034ad4SAnthony Koo * @fw_region_size: size of the firmware state region 29284034ad4SAnthony Koo * @trace_buffer_size: size of the tracebuffer region 29384034ad4SAnthony Koo * @fw_version: the firmware version information 294b2265774SAnthony Koo * @dal_fw: 1 if the firmware is DAL 29584034ad4SAnthony Koo */ 29684034ad4SAnthony Koo struct dmub_fw_meta_info { 297592a6318SAnthony Koo uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 298592a6318SAnthony Koo uint32_t fw_region_size; /**< size of the firmware state region */ 299592a6318SAnthony Koo uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 300592a6318SAnthony Koo uint32_t fw_version; /**< the firmware version information */ 301592a6318SAnthony Koo uint8_t dal_fw; /**< 1 if the firmware is DAL */ 302592a6318SAnthony Koo uint8_t reserved[3]; /**< padding bits */ 30384034ad4SAnthony Koo }; 30484034ad4SAnthony Koo 305592a6318SAnthony Koo /** 306592a6318SAnthony Koo * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 307592a6318SAnthony Koo */ 30884034ad4SAnthony Koo union dmub_fw_meta { 309592a6318SAnthony Koo struct dmub_fw_meta_info info; /**< metadata info */ 310592a6318SAnthony Koo uint8_t reserved[64]; /**< padding bits */ 31184034ad4SAnthony Koo }; 31284034ad4SAnthony Koo 31384034ad4SAnthony Koo #pragma pack(pop) 314788408b7SAnthony Koo 31584034ad4SAnthony Koo //============================================================================== 3166b66208fSYongqiang Sun //< DMUB Trace Buffer>================================================================ 3176b66208fSYongqiang Sun //============================================================================== 318592a6318SAnthony Koo /** 319592a6318SAnthony Koo * dmub_trace_code_t - firmware trace code, 32-bits 320592a6318SAnthony Koo */ 3216b66208fSYongqiang Sun typedef uint32_t dmub_trace_code_t; 3226b66208fSYongqiang Sun 323592a6318SAnthony Koo /** 324592a6318SAnthony Koo * struct dmcub_trace_buf_entry - Firmware trace entry 325592a6318SAnthony Koo */ 3266b66208fSYongqiang Sun struct dmcub_trace_buf_entry { 327592a6318SAnthony Koo dmub_trace_code_t trace_code; /**< trace code for the event */ 328592a6318SAnthony Koo uint32_t tick_count; /**< the tick count at time of trace */ 329592a6318SAnthony Koo uint32_t param0; /**< trace defined parameter 0 */ 330592a6318SAnthony Koo uint32_t param1; /**< trace defined parameter 1 */ 3316b66208fSYongqiang Sun }; 3326b66208fSYongqiang Sun 3336b66208fSYongqiang Sun //============================================================================== 334788408b7SAnthony Koo //< DMUB_STATUS>================================================================ 335788408b7SAnthony Koo //============================================================================== 336788408b7SAnthony Koo 337788408b7SAnthony Koo /** 338788408b7SAnthony Koo * DMCUB scratch registers can be used to determine firmware status. 339788408b7SAnthony Koo * Current scratch register usage is as follows: 340788408b7SAnthony Koo * 341492dd8a8SAnthony Koo * SCRATCH0: FW Boot Status register 342021eaef8SAnthony Koo * SCRATCH5: LVTMA Status Register 343492dd8a8SAnthony Koo * SCRATCH15: FW Boot Options register 344788408b7SAnthony Koo */ 345788408b7SAnthony Koo 346592a6318SAnthony Koo /** 347592a6318SAnthony Koo * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 348592a6318SAnthony Koo */ 349492dd8a8SAnthony Koo union dmub_fw_boot_status { 350492dd8a8SAnthony Koo struct { 351592a6318SAnthony Koo uint32_t dal_fw : 1; /**< 1 if DAL FW */ 352592a6318SAnthony Koo uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 353592a6318SAnthony Koo uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 354592a6318SAnthony Koo uint32_t restore_required : 1; /**< 1 if driver should call restore */ 35501934c30SAnthony Koo uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 35601934c30SAnthony Koo uint32_t reserved : 1; 35701934c30SAnthony Koo uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 35801934c30SAnthony Koo 359592a6318SAnthony Koo } bits; /**< status bits */ 360592a6318SAnthony Koo uint32_t all; /**< 32-bit access to status bits */ 361492dd8a8SAnthony Koo }; 362492dd8a8SAnthony Koo 363592a6318SAnthony Koo /** 364592a6318SAnthony Koo * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 365592a6318SAnthony Koo */ 366492dd8a8SAnthony Koo enum dmub_fw_boot_status_bit { 367592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 368592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 369592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 370592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 3711e0958bbSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 37201934c30SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 373492dd8a8SAnthony Koo }; 374492dd8a8SAnthony Koo 375021eaef8SAnthony Koo /* Register bit definition for SCRATCH5 */ 376021eaef8SAnthony Koo union dmub_lvtma_status { 377021eaef8SAnthony Koo struct { 378021eaef8SAnthony Koo uint32_t psp_ok : 1; 379021eaef8SAnthony Koo uint32_t edp_on : 1; 380021eaef8SAnthony Koo uint32_t reserved : 30; 381021eaef8SAnthony Koo } bits; 382021eaef8SAnthony Koo uint32_t all; 383021eaef8SAnthony Koo }; 384021eaef8SAnthony Koo 385021eaef8SAnthony Koo enum dmub_lvtma_status_bit { 386021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 387021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 388021eaef8SAnthony Koo }; 389021eaef8SAnthony Koo 390592a6318SAnthony Koo /** 3911e0958bbSAnthony Koo * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 392592a6318SAnthony Koo */ 393492dd8a8SAnthony Koo union dmub_fw_boot_options { 394492dd8a8SAnthony Koo struct { 395592a6318SAnthony Koo uint32_t pemu_env : 1; /**< 1 if PEMU */ 396592a6318SAnthony Koo uint32_t fpga_env : 1; /**< 1 if FPGA */ 397592a6318SAnthony Koo uint32_t optimized_init : 1; /**< 1 if optimized init */ 398592a6318SAnthony Koo uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 399592a6318SAnthony Koo uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 400592a6318SAnthony Koo uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 401b04cb192SNicholas Kazlauskas uint32_t z10_disable: 1; /**< 1 to disable z10 */ 402b0ce6272SMeenakshikumar Somasundaram uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 4031e0958bbSAnthony Koo uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 4043137f792SHansen uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 4053137f792SHansen uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 4063137f792SHansen /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 4073137f792SHansen uint32_t power_optimization: 1; 408b129c94eSAnthony Koo uint32_t diag_env: 1; /* 1 if diagnostic environment */ 4095cef7e8eSAnthony Koo uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 410ea5a4db9SAnthony Koo uint32_t usb4_cm_version: 1; /**< 1 CM support */ 4116f4f8ff5SMeenakshikumar Somasundaram uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 41273f73741SAnthony Koo uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 413b129c94eSAnthony Koo 41473f73741SAnthony Koo uint32_t reserved : 15; /**< reserved */ 415592a6318SAnthony Koo } bits; /**< boot bits */ 416592a6318SAnthony Koo uint32_t all; /**< 32-bit access to bits */ 417492dd8a8SAnthony Koo }; 418492dd8a8SAnthony Koo 419492dd8a8SAnthony Koo enum dmub_fw_boot_options_bit { 420592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 421592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 422592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 423492dd8a8SAnthony Koo }; 424492dd8a8SAnthony Koo 425788408b7SAnthony Koo //============================================================================== 426788408b7SAnthony Koo //</DMUB_STATUS>================================================================ 42784034ad4SAnthony Koo //============================================================================== 42884034ad4SAnthony Koo //< DMUB_VBIOS>================================================================= 42984034ad4SAnthony Koo //============================================================================== 43084034ad4SAnthony Koo 43184034ad4SAnthony Koo /* 432592a6318SAnthony Koo * enum dmub_cmd_vbios_type - VBIOS commands. 433592a6318SAnthony Koo * 43484034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 43584034ad4SAnthony Koo * Do not reuse or modify IDs. 43684034ad4SAnthony Koo */ 43784034ad4SAnthony Koo enum dmub_cmd_vbios_type { 438592a6318SAnthony Koo /** 439592a6318SAnthony Koo * Configures the DIG encoder. 440592a6318SAnthony Koo */ 44184034ad4SAnthony Koo DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 442592a6318SAnthony Koo /** 443592a6318SAnthony Koo * Controls the PHY. 444592a6318SAnthony Koo */ 44584034ad4SAnthony Koo DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 446592a6318SAnthony Koo /** 447592a6318SAnthony Koo * Sets the pixel clock/symbol clock. 448592a6318SAnthony Koo */ 44984034ad4SAnthony Koo DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 450592a6318SAnthony Koo /** 451592a6318SAnthony Koo * Enables or disables power gating. 452592a6318SAnthony Koo */ 45384034ad4SAnthony Koo DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 45441f91315SNicholas Kazlauskas /** 45541f91315SNicholas Kazlauskas * Controls embedded panels. 45641f91315SNicholas Kazlauskas */ 4572ac685bfSAnthony Koo DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 45841f91315SNicholas Kazlauskas /** 45941f91315SNicholas Kazlauskas * Query DP alt status on a transmitter. 46041f91315SNicholas Kazlauskas */ 46141f91315SNicholas Kazlauskas DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 462e383b127SNicholas Kazlauskas /** 463e383b127SNicholas Kazlauskas * Controls domain power gating 464e383b127SNicholas Kazlauskas */ 465e383b127SNicholas Kazlauskas DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 46684034ad4SAnthony Koo }; 46784034ad4SAnthony Koo 46884034ad4SAnthony Koo //============================================================================== 46984034ad4SAnthony Koo //</DMUB_VBIOS>================================================================= 47084034ad4SAnthony Koo //============================================================================== 47184034ad4SAnthony Koo //< DMUB_GPINT>================================================================= 47284034ad4SAnthony Koo //============================================================================== 47384034ad4SAnthony Koo 47484034ad4SAnthony Koo /** 47584034ad4SAnthony Koo * The shifts and masks below may alternatively be used to format and read 47684034ad4SAnthony Koo * the command register bits. 47784034ad4SAnthony Koo */ 47884034ad4SAnthony Koo 47984034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 48084034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_SHIFT 0 48184034ad4SAnthony Koo 48284034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 48384034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 48484034ad4SAnthony Koo 48584034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_MASK 0xF 48684034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_SHIFT 28 48784034ad4SAnthony Koo 48884034ad4SAnthony Koo /** 48984034ad4SAnthony Koo * Command responses. 49084034ad4SAnthony Koo */ 49184034ad4SAnthony Koo 492592a6318SAnthony Koo /** 493592a6318SAnthony Koo * Return response for DMUB_GPINT__STOP_FW command. 494592a6318SAnthony Koo */ 49584034ad4SAnthony Koo #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 49684034ad4SAnthony Koo 49784034ad4SAnthony Koo /** 498592a6318SAnthony Koo * union dmub_gpint_data_register - Format for sending a command via the GPINT. 49984034ad4SAnthony Koo */ 50084034ad4SAnthony Koo union dmub_gpint_data_register { 50184034ad4SAnthony Koo struct { 502592a6318SAnthony Koo uint32_t param : 16; /**< 16-bit parameter */ 503592a6318SAnthony Koo uint32_t command_code : 12; /**< GPINT command */ 504592a6318SAnthony Koo uint32_t status : 4; /**< Command status bit */ 505592a6318SAnthony Koo } bits; /**< GPINT bit access */ 506592a6318SAnthony Koo uint32_t all; /**< GPINT 32-bit access */ 50784034ad4SAnthony Koo }; 50884034ad4SAnthony Koo 50984034ad4SAnthony Koo /* 510592a6318SAnthony Koo * enum dmub_gpint_command - GPINT command to DMCUB FW 511592a6318SAnthony Koo * 51284034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 51384034ad4SAnthony Koo * Do not reuse or modify IDs. 51484034ad4SAnthony Koo */ 51584034ad4SAnthony Koo enum dmub_gpint_command { 516592a6318SAnthony Koo /** 517592a6318SAnthony Koo * Invalid command, ignored. 518592a6318SAnthony Koo */ 51984034ad4SAnthony Koo DMUB_GPINT__INVALID_COMMAND = 0, 520592a6318SAnthony Koo /** 521592a6318SAnthony Koo * DESC: Queries the firmware version. 522592a6318SAnthony Koo * RETURN: Firmware version. 523592a6318SAnthony Koo */ 52484034ad4SAnthony Koo DMUB_GPINT__GET_FW_VERSION = 1, 525592a6318SAnthony Koo /** 526592a6318SAnthony Koo * DESC: Halts the firmware. 527592a6318SAnthony Koo * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 528592a6318SAnthony Koo */ 52984034ad4SAnthony Koo DMUB_GPINT__STOP_FW = 2, 5301a595f28SAnthony Koo /** 5311a595f28SAnthony Koo * DESC: Get PSR state from FW. 5321a595f28SAnthony Koo * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 5331a595f28SAnthony Koo */ 53484034ad4SAnthony Koo DMUB_GPINT__GET_PSR_STATE = 7, 53580eba958SAnthony Koo /** 53680eba958SAnthony Koo * DESC: Notifies DMCUB of the currently active streams. 53780eba958SAnthony Koo * ARGS: Stream mask, 1 bit per active stream index. 53880eba958SAnthony Koo */ 53980eba958SAnthony Koo DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 5401a595f28SAnthony Koo /** 5411a595f28SAnthony Koo * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 5421a595f28SAnthony Koo * ARGS: We can measure residency from various points. The argument will specify the residency mode. 5431a595f28SAnthony Koo * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 5441a595f28SAnthony Koo * RETURN: PSR residency in milli-percent. 5451a595f28SAnthony Koo */ 546672251b2SAnthony Koo DMUB_GPINT__PSR_RESIDENCY = 9, 54701934c30SAnthony Koo 54801934c30SAnthony Koo /** 54901934c30SAnthony Koo * DESC: Notifies DMCUB detection is done so detection required can be cleared. 55001934c30SAnthony Koo */ 55101934c30SAnthony Koo DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 55284034ad4SAnthony Koo }; 55384034ad4SAnthony Koo 5540b51e7e8SAnthony Koo /** 5550b51e7e8SAnthony Koo * INBOX0 generic command definition 5560b51e7e8SAnthony Koo */ 5570b51e7e8SAnthony Koo union dmub_inbox0_cmd_common { 5580b51e7e8SAnthony Koo struct { 5590b51e7e8SAnthony Koo uint32_t command_code: 8; /**< INBOX0 command code */ 5600b51e7e8SAnthony Koo uint32_t param: 24; /**< 24-bit parameter */ 5610b51e7e8SAnthony Koo } bits; 5620b51e7e8SAnthony Koo uint32_t all; 5630b51e7e8SAnthony Koo }; 5640b51e7e8SAnthony Koo 5650b51e7e8SAnthony Koo /** 5660b51e7e8SAnthony Koo * INBOX0 hw_lock command definition 5670b51e7e8SAnthony Koo */ 5680b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw { 5690b51e7e8SAnthony Koo struct { 5700b51e7e8SAnthony Koo uint32_t command_code: 8; 5710b51e7e8SAnthony Koo 5720b51e7e8SAnthony Koo /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 5732412d339SAnthony Koo uint32_t hw_lock_client: 2; 5740b51e7e8SAnthony Koo 5750b51e7e8SAnthony Koo /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 5760b51e7e8SAnthony Koo uint32_t otg_inst: 3; 5770b51e7e8SAnthony Koo uint32_t opp_inst: 3; 5780b51e7e8SAnthony Koo uint32_t dig_inst: 3; 5790b51e7e8SAnthony Koo 5800b51e7e8SAnthony Koo /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 5810b51e7e8SAnthony Koo uint32_t lock_pipe: 1; 5820b51e7e8SAnthony Koo uint32_t lock_cursor: 1; 5830b51e7e8SAnthony Koo uint32_t lock_dig: 1; 5840b51e7e8SAnthony Koo uint32_t triple_buffer_lock: 1; 5850b51e7e8SAnthony Koo 5860b51e7e8SAnthony Koo uint32_t lock: 1; /**< Lock */ 5870b51e7e8SAnthony Koo uint32_t should_release: 1; /**< Release */ 5882412d339SAnthony Koo uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 5890b51e7e8SAnthony Koo } bits; 5900b51e7e8SAnthony Koo uint32_t all; 5910b51e7e8SAnthony Koo }; 5920b51e7e8SAnthony Koo 5930b51e7e8SAnthony Koo union dmub_inbox0_data_register { 5940b51e7e8SAnthony Koo union dmub_inbox0_cmd_common inbox0_cmd_common; 5950b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 5960b51e7e8SAnthony Koo }; 5970b51e7e8SAnthony Koo 5980b51e7e8SAnthony Koo enum dmub_inbox0_command { 5990b51e7e8SAnthony Koo /** 6000b51e7e8SAnthony Koo * DESC: Invalid command, ignored. 6010b51e7e8SAnthony Koo */ 6020b51e7e8SAnthony Koo DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 6030b51e7e8SAnthony Koo /** 6040b51e7e8SAnthony Koo * DESC: Notification to acquire/release HW lock 6050b51e7e8SAnthony Koo * ARGS: 6060b51e7e8SAnthony Koo */ 6070b51e7e8SAnthony Koo DMUB_INBOX0_CMD__HW_LOCK = 1, 6080b51e7e8SAnthony Koo }; 60984034ad4SAnthony Koo //============================================================================== 61084034ad4SAnthony Koo //</DMUB_GPINT>================================================================= 61184034ad4SAnthony Koo //============================================================================== 61284034ad4SAnthony Koo //< DMUB_CMD>=================================================================== 61384034ad4SAnthony Koo //============================================================================== 61484034ad4SAnthony Koo 615592a6318SAnthony Koo /** 616592a6318SAnthony Koo * Size in bytes of each DMUB command. 617592a6318SAnthony Koo */ 6187c008829SNicholas Kazlauskas #define DMUB_RB_CMD_SIZE 64 619592a6318SAnthony Koo 620592a6318SAnthony Koo /** 621592a6318SAnthony Koo * Maximum number of items in the DMUB ringbuffer. 622592a6318SAnthony Koo */ 6237c008829SNicholas Kazlauskas #define DMUB_RB_MAX_ENTRY 128 624592a6318SAnthony Koo 625592a6318SAnthony Koo /** 626592a6318SAnthony Koo * Ringbuffer size in bytes. 627592a6318SAnthony Koo */ 6287c008829SNicholas Kazlauskas #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 629592a6318SAnthony Koo 630592a6318SAnthony Koo /** 631592a6318SAnthony Koo * REG_SET mask for reg offload. 632592a6318SAnthony Koo */ 6337c008829SNicholas Kazlauskas #define REG_SET_MASK 0xFFFF 6347c008829SNicholas Kazlauskas 635d4bbcecbSNicholas Kazlauskas /* 636592a6318SAnthony Koo * enum dmub_cmd_type - DMUB inbox command. 637592a6318SAnthony Koo * 638d4bbcecbSNicholas Kazlauskas * Command IDs should be treated as stable ABI. 639d4bbcecbSNicholas Kazlauskas * Do not reuse or modify IDs. 640d4bbcecbSNicholas Kazlauskas */ 641d4bbcecbSNicholas Kazlauskas enum dmub_cmd_type { 642592a6318SAnthony Koo /** 643592a6318SAnthony Koo * Invalid command. 644592a6318SAnthony Koo */ 645d4bbcecbSNicholas Kazlauskas DMUB_CMD__NULL = 0, 646592a6318SAnthony Koo /** 647592a6318SAnthony Koo * Read modify write register sequence offload. 648592a6318SAnthony Koo */ 649d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 650592a6318SAnthony Koo /** 651592a6318SAnthony Koo * Field update register sequence offload. 652592a6318SAnthony Koo */ 653d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 654592a6318SAnthony Koo /** 655592a6318SAnthony Koo * Burst write sequence offload. 656592a6318SAnthony Koo */ 657d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 658592a6318SAnthony Koo /** 659592a6318SAnthony Koo * Reg wait sequence offload. 660592a6318SAnthony Koo */ 661d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_REG_WAIT = 4, 662592a6318SAnthony Koo /** 663592a6318SAnthony Koo * Workaround to avoid HUBP underflow during NV12 playback. 664592a6318SAnthony Koo */ 665bae9c49bSYongqiang Sun DMUB_CMD__PLAT_54186_WA = 5, 6661a595f28SAnthony Koo /** 6671a595f28SAnthony Koo * Command type used to query FW feature caps. 6681a595f28SAnthony Koo */ 66934ba432cSAnthony Koo DMUB_CMD__QUERY_FEATURE_CAPS = 6, 6701a595f28SAnthony Koo /** 671b09c1fffSLeo (Hanghong) Ma * Command type used to get visual confirm color. 672b09c1fffSLeo (Hanghong) Ma */ 673b09c1fffSLeo (Hanghong) Ma DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 674b09c1fffSLeo (Hanghong) Ma /** 6751a595f28SAnthony Koo * Command type used for all PSR commands. 6761a595f28SAnthony Koo */ 677d4bbcecbSNicholas Kazlauskas DMUB_CMD__PSR = 64, 678592a6318SAnthony Koo /** 679592a6318SAnthony Koo * Command type used for all MALL commands. 680592a6318SAnthony Koo */ 68152f2e83eSBhawanpreet Lakha DMUB_CMD__MALL = 65, 6821a595f28SAnthony Koo /** 6831a595f28SAnthony Koo * Command type used for all ABM commands. 6841a595f28SAnthony Koo */ 685e6ea8c34SWyatt Wood DMUB_CMD__ABM = 66, 6861a595f28SAnthony Koo /** 68783eb5385SDavid Zhang * Command type used to update dirty rects in FW. 68883eb5385SDavid Zhang */ 68983eb5385SDavid Zhang DMUB_CMD__UPDATE_DIRTY_RECT = 67, 69083eb5385SDavid Zhang /** 69183eb5385SDavid Zhang * Command type used to update cursor info in FW. 69283eb5385SDavid Zhang */ 69383eb5385SDavid Zhang DMUB_CMD__UPDATE_CURSOR_INFO = 68, 69483eb5385SDavid Zhang /** 6951a595f28SAnthony Koo * Command type used for HW locking in FW. 6961a595f28SAnthony Koo */ 697788408b7SAnthony Koo DMUB_CMD__HW_LOCK = 69, 6981a595f28SAnthony Koo /** 6991a595f28SAnthony Koo * Command type used to access DP AUX. 7001a595f28SAnthony Koo */ 701d9beecfcSAnthony Koo DMUB_CMD__DP_AUX_ACCESS = 70, 7021a595f28SAnthony Koo /** 7031a595f28SAnthony Koo * Command type used for OUTBOX1 notification enable 7041a595f28SAnthony Koo */ 705d9beecfcSAnthony Koo DMUB_CMD__OUTBOX1_ENABLE = 71, 7065cef7e8eSAnthony Koo 707b04cb192SNicholas Kazlauskas /** 708b04cb192SNicholas Kazlauskas * Command type used for all idle optimization commands. 709b04cb192SNicholas Kazlauskas */ 710b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT = 72, 711b04cb192SNicholas Kazlauskas /** 712b04cb192SNicholas Kazlauskas * Command type used for all clock manager commands. 713b04cb192SNicholas Kazlauskas */ 714b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR = 73, 715b04cb192SNicholas Kazlauskas /** 716b04cb192SNicholas Kazlauskas * Command type used for all panel control commands. 717b04cb192SNicholas Kazlauskas */ 718b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL = 74, 719ac2e555eSAurabindo Pillai /** 720ac2e555eSAurabindo Pillai * Command type used for <TODO:description> 721ac2e555eSAurabindo Pillai */ 722ac2e555eSAurabindo Pillai DMUB_CMD__CAB_FOR_SS = 75, 72385f4bc0cSAlvin Lee 72485f4bc0cSAlvin Lee DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 72585f4bc0cSAlvin Lee 726592a6318SAnthony Koo /** 72776724b76SJimmy Kizito * Command type used for interfacing with DPIA. 72876724b76SJimmy Kizito */ 72976724b76SJimmy Kizito DMUB_CMD__DPIA = 77, 73076724b76SJimmy Kizito /** 731021eaef8SAnthony Koo * Command type used for EDID CEA parsing 732021eaef8SAnthony Koo */ 733021eaef8SAnthony Koo DMUB_CMD__EDID_CEA = 79, 734021eaef8SAnthony Koo /** 735c595fb05SWenjing Liu * Command type used for getting usbc cable ID 736c595fb05SWenjing Liu */ 737c595fb05SWenjing Liu DMUB_CMD_GET_USBC_CABLE_ID = 81, 738c595fb05SWenjing Liu /** 739ea5a4db9SAnthony Koo * Command type used to query HPD state. 740ea5a4db9SAnthony Koo */ 741ea5a4db9SAnthony Koo DMUB_CMD__QUERY_HPD_STATE = 82, 742ea5a4db9SAnthony Koo /** 743592a6318SAnthony Koo * Command type used for all VBIOS interface commands. 744592a6318SAnthony Koo */ 7451fb695d9SAnthony Koo 746c0459bddSAlan Liu /** 747c0459bddSAlan Liu * Command type used for all SECURE_DISPLAY commands. 748c0459bddSAlan Liu */ 749c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY = 85, 7506f4f8ff5SMeenakshikumar Somasundaram 7516f4f8ff5SMeenakshikumar Somasundaram /** 7526f4f8ff5SMeenakshikumar Somasundaram * Command type used to set DPIA HPD interrupt state 7536f4f8ff5SMeenakshikumar Somasundaram */ 7546f4f8ff5SMeenakshikumar Somasundaram DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 7556f4f8ff5SMeenakshikumar Somasundaram 756d4bbcecbSNicholas Kazlauskas DMUB_CMD__VBIOS = 128, 7577c008829SNicholas Kazlauskas }; 7587c008829SNicholas Kazlauskas 759592a6318SAnthony Koo /** 760592a6318SAnthony Koo * enum dmub_out_cmd_type - DMUB outbox commands. 761592a6318SAnthony Koo */ 7623b37260bSAnthony Koo enum dmub_out_cmd_type { 763592a6318SAnthony Koo /** 764592a6318SAnthony Koo * Invalid outbox command, ignored. 765592a6318SAnthony Koo */ 7663b37260bSAnthony Koo DMUB_OUT_CMD__NULL = 0, 7671a595f28SAnthony Koo /** 7681a595f28SAnthony Koo * Command type used for DP AUX Reply data notification 7691a595f28SAnthony Koo */ 770d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_AUX_REPLY = 1, 771892b74a6SMeenakshikumar Somasundaram /** 772892b74a6SMeenakshikumar Somasundaram * Command type used for DP HPD event notification 773892b74a6SMeenakshikumar Somasundaram */ 774892b74a6SMeenakshikumar Somasundaram DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 77571af9d46SMeenakshikumar Somasundaram /** 77671af9d46SMeenakshikumar Somasundaram * Command type used for SET_CONFIG Reply notification 77771af9d46SMeenakshikumar Somasundaram */ 77871af9d46SMeenakshikumar Somasundaram DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 7798af54c61SMustapha Ghaddar /** 7808af54c61SMustapha Ghaddar * Command type used for USB4 DPIA notification 7818af54c61SMustapha Ghaddar */ 7828af54c61SMustapha Ghaddar DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 7833b37260bSAnthony Koo }; 7843b37260bSAnthony Koo 78576724b76SJimmy Kizito /* DMUB_CMD__DPIA command sub-types. */ 78676724b76SJimmy Kizito enum dmub_cmd_dpia_type { 78776724b76SJimmy Kizito DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 78871af9d46SMeenakshikumar Somasundaram DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 789139a3311SMeenakshikumar Somasundaram DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 79076724b76SJimmy Kizito }; 79176724b76SJimmy Kizito 7928af54c61SMustapha Ghaddar /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 7938af54c61SMustapha Ghaddar enum dmub_cmd_dpia_notification_type { 7948af54c61SMustapha Ghaddar DPIA_NOTIFY__BW_ALLOCATION = 0, 7958af54c61SMustapha Ghaddar }; 7968af54c61SMustapha Ghaddar 7977c008829SNicholas Kazlauskas #pragma pack(push, 1) 7987c008829SNicholas Kazlauskas 799592a6318SAnthony Koo /** 800592a6318SAnthony Koo * struct dmub_cmd_header - Common command header fields. 801592a6318SAnthony Koo */ 8027c008829SNicholas Kazlauskas struct dmub_cmd_header { 803592a6318SAnthony Koo unsigned int type : 8; /**< command type */ 804592a6318SAnthony Koo unsigned int sub_type : 8; /**< command sub type */ 805592a6318SAnthony Koo unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 8060b51e7e8SAnthony Koo unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 8070b51e7e8SAnthony Koo unsigned int reserved0 : 6; /**< reserved bits */ 808592a6318SAnthony Koo unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 809592a6318SAnthony Koo unsigned int reserved1 : 2; /**< reserved bits */ 8107c008829SNicholas Kazlauskas }; 8117c008829SNicholas Kazlauskas 8127c008829SNicholas Kazlauskas /* 813592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write 8147c008829SNicholas Kazlauskas * 8157c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 5 sets of read modify writes, 8167c008829SNicholas Kazlauskas * each take 3 dwords. 8177c008829SNicholas Kazlauskas * 8187c008829SNicholas Kazlauskas * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 8197c008829SNicholas Kazlauskas * 8207c008829SNicholas Kazlauskas * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 8217c008829SNicholas Kazlauskas * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 8227c008829SNicholas Kazlauskas */ 8237c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence { 824592a6318SAnthony Koo uint32_t addr; /**< register address */ 825592a6318SAnthony Koo uint32_t modify_mask; /**< modify mask */ 826592a6318SAnthony Koo uint32_t modify_value; /**< modify value */ 8277c008829SNicholas Kazlauskas }; 8287c008829SNicholas Kazlauskas 829592a6318SAnthony Koo /** 830592a6318SAnthony Koo * Maximum number of ops in read modify write sequence. 831592a6318SAnthony Koo */ 8327c008829SNicholas Kazlauskas #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 833592a6318SAnthony Koo 834592a6318SAnthony Koo /** 835592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 836592a6318SAnthony Koo */ 8377c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write { 838592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 839592a6318SAnthony Koo /** 840592a6318SAnthony Koo * Read modify write sequence. 841592a6318SAnthony Koo */ 8427c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 8437c008829SNicholas Kazlauskas }; 8447c008829SNicholas Kazlauskas 8457c008829SNicholas Kazlauskas /* 8467c008829SNicholas Kazlauskas * Update a register with specified masks and values sequeunce 8477c008829SNicholas Kazlauskas * 8487c008829SNicholas Kazlauskas * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 8497c008829SNicholas Kazlauskas * 8507c008829SNicholas Kazlauskas * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 8517c008829SNicholas Kazlauskas * 8527c008829SNicholas Kazlauskas * 8537c008829SNicholas Kazlauskas * USE CASE: 8547c008829SNicholas Kazlauskas * 1. auto-increment register where additional read would update pointer and produce wrong result 8557c008829SNicholas Kazlauskas * 2. toggle a bit without read in the middle 8567c008829SNicholas Kazlauskas */ 8577c008829SNicholas Kazlauskas 8587c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence { 859592a6318SAnthony Koo uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 860592a6318SAnthony Koo uint32_t modify_value; /**< value to update with */ 8617c008829SNicholas Kazlauskas }; 8627c008829SNicholas Kazlauskas 863592a6318SAnthony Koo /** 864592a6318SAnthony Koo * Maximum number of ops in field update sequence. 865592a6318SAnthony Koo */ 8667c008829SNicholas Kazlauskas #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 867592a6318SAnthony Koo 868592a6318SAnthony Koo /** 869592a6318SAnthony Koo * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 870592a6318SAnthony Koo */ 8717c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence { 872592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 873592a6318SAnthony Koo uint32_t addr; /**< register address */ 874592a6318SAnthony Koo /** 875592a6318SAnthony Koo * Field update sequence. 876592a6318SAnthony Koo */ 8777c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 8787c008829SNicholas Kazlauskas }; 8797c008829SNicholas Kazlauskas 880592a6318SAnthony Koo 881592a6318SAnthony Koo /** 882592a6318SAnthony Koo * Maximum number of burst write values. 883592a6318SAnthony Koo */ 884592a6318SAnthony Koo #define DMUB_BURST_WRITE_VALUES__MAX 14 885592a6318SAnthony Koo 8867c008829SNicholas Kazlauskas /* 887592a6318SAnthony Koo * struct dmub_rb_cmd_burst_write - Burst write 8887c008829SNicholas Kazlauskas * 8897c008829SNicholas Kazlauskas * support use case such as writing out LUTs. 8907c008829SNicholas Kazlauskas * 8917c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 14 values to write to given address 8927c008829SNicholas Kazlauskas * 8937c008829SNicholas Kazlauskas * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 8947c008829SNicholas Kazlauskas */ 8957c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write { 896592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 897592a6318SAnthony Koo uint32_t addr; /**< register start address */ 898592a6318SAnthony Koo /** 899592a6318SAnthony Koo * Burst write register values. 900592a6318SAnthony Koo */ 9017c008829SNicholas Kazlauskas uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 9027c008829SNicholas Kazlauskas }; 9037c008829SNicholas Kazlauskas 904592a6318SAnthony Koo /** 905592a6318SAnthony Koo * struct dmub_rb_cmd_common - Common command header 906592a6318SAnthony Koo */ 9077c008829SNicholas Kazlauskas struct dmub_rb_cmd_common { 908592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 909592a6318SAnthony Koo /** 910592a6318SAnthony Koo * Padding to RB_CMD_SIZE 911592a6318SAnthony Koo */ 9127c008829SNicholas Kazlauskas uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 9137c008829SNicholas Kazlauskas }; 9147c008829SNicholas Kazlauskas 915592a6318SAnthony Koo /** 916592a6318SAnthony Koo * struct dmub_cmd_reg_wait_data - Register wait data 917592a6318SAnthony Koo */ 9187c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data { 919592a6318SAnthony Koo uint32_t addr; /**< Register address */ 920592a6318SAnthony Koo uint32_t mask; /**< Mask for register bits */ 921592a6318SAnthony Koo uint32_t condition_field_value; /**< Value to wait for */ 922592a6318SAnthony Koo uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 9237c008829SNicholas Kazlauskas }; 9247c008829SNicholas Kazlauskas 925592a6318SAnthony Koo /** 926592a6318SAnthony Koo * struct dmub_rb_cmd_reg_wait - Register wait command 927592a6318SAnthony Koo */ 9287c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait { 929592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 930592a6318SAnthony Koo struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 9317c008829SNicholas Kazlauskas }; 9327c008829SNicholas Kazlauskas 933592a6318SAnthony Koo /** 934592a6318SAnthony Koo * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 935592a6318SAnthony Koo * 936592a6318SAnthony Koo * Reprograms surface parameters to avoid underflow. 937592a6318SAnthony Koo */ 938bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa { 939592a6318SAnthony Koo uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 940592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 941592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 942592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 943592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 94422aa5614SYongqiang Sun struct { 945592a6318SAnthony Koo uint8_t hubp_inst : 4; /**< HUBP instance */ 946592a6318SAnthony Koo uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 947592a6318SAnthony Koo uint8_t immediate :1; /**< Immediate flip */ 948592a6318SAnthony Koo uint8_t vmid : 4; /**< VMID */ 949592a6318SAnthony Koo uint8_t grph_stereo : 1; /**< 1 if stereo */ 950592a6318SAnthony Koo uint32_t reserved : 21; /**< Reserved */ 951592a6318SAnthony Koo } flip_params; /**< Pageflip parameters */ 952d2994b25SAyush Gupta uint32_t reserved[9]; /**< Reserved bits */ 9538c019253SYongqiang Sun }; 9548c019253SYongqiang Sun 955592a6318SAnthony Koo /** 956592a6318SAnthony Koo * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 957592a6318SAnthony Koo */ 958bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa { 959592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 960592a6318SAnthony Koo struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 9618c019253SYongqiang Sun }; 9628c019253SYongqiang Sun 963592a6318SAnthony Koo /** 964592a6318SAnthony Koo * struct dmub_rb_cmd_mall - MALL command data. 965592a6318SAnthony Koo */ 96652f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall { 967592a6318SAnthony Koo struct dmub_cmd_header header; /**< Common command header */ 968592a6318SAnthony Koo union dmub_addr cursor_copy_src; /**< Cursor copy address */ 969592a6318SAnthony Koo union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 970592a6318SAnthony Koo uint32_t tmr_delay; /**< Timer delay */ 971592a6318SAnthony Koo uint32_t tmr_scale; /**< Timer scale */ 972592a6318SAnthony Koo uint16_t cursor_width; /**< Cursor width in pixels */ 973592a6318SAnthony Koo uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 974592a6318SAnthony Koo uint16_t cursor_height; /**< Cursor height in pixels */ 975592a6318SAnthony Koo uint8_t cursor_bpp; /**< Cursor bits per pixel */ 976592a6318SAnthony Koo uint8_t debug_bits; /**< Debug bits */ 977ea7154d8SBhawanpreet Lakha 978592a6318SAnthony Koo uint8_t reserved1; /**< Reserved bits */ 979592a6318SAnthony Koo uint8_t reserved2; /**< Reserved bits */ 98052f2e83eSBhawanpreet Lakha }; 98152f2e83eSBhawanpreet Lakha 982b04cb192SNicholas Kazlauskas /** 983ac2e555eSAurabindo Pillai * enum dmub_cmd_cab_type - TODO: 984ac2e555eSAurabindo Pillai */ 985ac2e555eSAurabindo Pillai enum dmub_cmd_cab_type { 986ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 987ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_DCN_REQ = 1, 988ac2e555eSAurabindo Pillai DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 989ac2e555eSAurabindo Pillai }; 990ac2e555eSAurabindo Pillai 991ac2e555eSAurabindo Pillai /** 992ac2e555eSAurabindo Pillai * struct dmub_rb_cmd_cab_for_ss - TODO: 993ac2e555eSAurabindo Pillai */ 994ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss { 995ac2e555eSAurabindo Pillai struct dmub_cmd_header header; 996ac2e555eSAurabindo Pillai uint8_t cab_alloc_ways; /* total number of ways */ 997ac2e555eSAurabindo Pillai uint8_t debug_bits; /* debug bits */ 998ac2e555eSAurabindo Pillai }; 99985f4bc0cSAlvin Lee 100085f4bc0cSAlvin Lee enum mclk_switch_mode { 100185f4bc0cSAlvin Lee NONE = 0, 100285f4bc0cSAlvin Lee FPO = 1, 100385f4bc0cSAlvin Lee SUBVP = 2, 100485f4bc0cSAlvin Lee VBLANK = 3, 100585f4bc0cSAlvin Lee }; 100685f4bc0cSAlvin Lee 100785f4bc0cSAlvin Lee /* Per pipe struct which stores the MCLK switch mode 100885f4bc0cSAlvin Lee * data to be sent to DMUB. 100985f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 101085f4bc0cSAlvin Lee * the type name can be updated 101185f4bc0cSAlvin Lee */ 101285f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 101385f4bc0cSAlvin Lee union { 101485f4bc0cSAlvin Lee struct { 101585f4bc0cSAlvin Lee uint32_t pix_clk_100hz; 101685f4bc0cSAlvin Lee uint16_t main_vblank_start; 101785f4bc0cSAlvin Lee uint16_t main_vblank_end; 101885f4bc0cSAlvin Lee uint16_t mall_region_lines; 101985f4bc0cSAlvin Lee uint16_t prefetch_lines; 102085f4bc0cSAlvin Lee uint16_t prefetch_to_mall_start_lines; 102185f4bc0cSAlvin Lee uint16_t processing_delay_lines; 102285f4bc0cSAlvin Lee uint16_t htotal; // required to calculate line time for multi-display cases 102385f4bc0cSAlvin Lee uint16_t vtotal; 102485f4bc0cSAlvin Lee uint8_t main_pipe_index; 102585f4bc0cSAlvin Lee uint8_t phantom_pipe_index; 10260acc5b06SAnthony Koo /* Since the microschedule is calculated in terms of OTG lines, 10270acc5b06SAnthony Koo * include any scaling factors to make sure when we get accurate 10280acc5b06SAnthony Koo * conversion when programming MALL_START_LINE (which is in terms 10290acc5b06SAnthony Koo * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 10300acc5b06SAnthony Koo * is 1/2 (numerator = 1, denominator = 2). 10310acc5b06SAnthony Koo */ 10320acc5b06SAnthony Koo uint8_t scale_factor_numerator; 10330acc5b06SAnthony Koo uint8_t scale_factor_denominator; 103481f776b6SAnthony Koo uint8_t is_drr; 10351591a647SAnthony Koo uint8_t main_split_pipe_index; 10361591a647SAnthony Koo uint8_t phantom_split_pipe_index; 103785f4bc0cSAlvin Lee } subvp_data; 103885f4bc0cSAlvin Lee 103985f4bc0cSAlvin Lee struct { 104085f4bc0cSAlvin Lee uint32_t pix_clk_100hz; 104185f4bc0cSAlvin Lee uint16_t vblank_start; 104285f4bc0cSAlvin Lee uint16_t vblank_end; 104385f4bc0cSAlvin Lee uint16_t vstartup_start; 104485f4bc0cSAlvin Lee uint16_t vtotal; 104585f4bc0cSAlvin Lee uint16_t htotal; 104685f4bc0cSAlvin Lee uint8_t vblank_pipe_index; 1047ae7169a9SAlvin Lee uint8_t padding[1]; 104885f4bc0cSAlvin Lee struct { 104985f4bc0cSAlvin Lee uint8_t drr_in_use; 105085f4bc0cSAlvin Lee uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 105185f4bc0cSAlvin Lee uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 105285f4bc0cSAlvin Lee uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 105385f4bc0cSAlvin Lee uint8_t use_ramping; // Use ramping or not 1054ae7169a9SAlvin Lee uint8_t drr_vblank_start_margin; 105585f4bc0cSAlvin Lee } drr_info; // DRR considered as part of SubVP + VBLANK case 105685f4bc0cSAlvin Lee } vblank_data; 105785f4bc0cSAlvin Lee } pipe_config; 105885f4bc0cSAlvin Lee 10590acc5b06SAnthony Koo /* - subvp_data in the union (pipe_config) takes up 27 bytes. 10600acc5b06SAnthony Koo * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 10610acc5b06SAnthony Koo * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 10620acc5b06SAnthony Koo */ 10630acc5b06SAnthony Koo uint8_t mode; // enum mclk_switch_mode 106485f4bc0cSAlvin Lee }; 106585f4bc0cSAlvin Lee 106685f4bc0cSAlvin Lee /** 106785f4bc0cSAlvin Lee * Config data for Sub-VP and FPO 106885f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 106985f4bc0cSAlvin Lee * the type name can be updated 107085f4bc0cSAlvin Lee */ 107185f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 107285f4bc0cSAlvin Lee uint16_t watermark_a_cache; 107385f4bc0cSAlvin Lee uint8_t vertical_int_margin_us; 107485f4bc0cSAlvin Lee uint8_t pstate_allow_width_us; 107585f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 107685f4bc0cSAlvin Lee }; 107785f4bc0cSAlvin Lee 107885f4bc0cSAlvin Lee /** 107985f4bc0cSAlvin Lee * DMUB rb command definition for Sub-VP and FPO 108085f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 108185f4bc0cSAlvin Lee * the type name can be updated 108285f4bc0cSAlvin Lee */ 108385f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 108485f4bc0cSAlvin Lee struct dmub_cmd_header header; 108585f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 108685f4bc0cSAlvin Lee }; 108785f4bc0cSAlvin Lee 1088ac2e555eSAurabindo Pillai /** 1089b04cb192SNicholas Kazlauskas * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1090b04cb192SNicholas Kazlauskas */ 1091b04cb192SNicholas Kazlauskas enum dmub_cmd_idle_opt_type { 1092b04cb192SNicholas Kazlauskas /** 1093b04cb192SNicholas Kazlauskas * DCN hardware restore. 1094b04cb192SNicholas Kazlauskas */ 1095b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1096f586fea8SJake Wang 1097f586fea8SJake Wang /** 1098f586fea8SJake Wang * DCN hardware save. 1099f586fea8SJake Wang */ 1100f586fea8SJake Wang DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1101b04cb192SNicholas Kazlauskas }; 1102b04cb192SNicholas Kazlauskas 1103b04cb192SNicholas Kazlauskas /** 1104b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1105b04cb192SNicholas Kazlauskas */ 1106b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore { 1107b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1108b04cb192SNicholas Kazlauskas }; 1109b04cb192SNicholas Kazlauskas 1110b04cb192SNicholas Kazlauskas /** 1111b04cb192SNicholas Kazlauskas * struct dmub_clocks - Clock update notification. 1112b04cb192SNicholas Kazlauskas */ 1113b04cb192SNicholas Kazlauskas struct dmub_clocks { 1114b04cb192SNicholas Kazlauskas uint32_t dispclk_khz; /**< dispclk kHz */ 1115b04cb192SNicholas Kazlauskas uint32_t dppclk_khz; /**< dppclk kHz */ 1116b04cb192SNicholas Kazlauskas uint32_t dcfclk_khz; /**< dcfclk kHz */ 1117b04cb192SNicholas Kazlauskas uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1118b04cb192SNicholas Kazlauskas }; 1119b04cb192SNicholas Kazlauskas 1120b04cb192SNicholas Kazlauskas /** 1121b04cb192SNicholas Kazlauskas * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1122b04cb192SNicholas Kazlauskas */ 1123b04cb192SNicholas Kazlauskas enum dmub_cmd_clk_mgr_type { 1124b04cb192SNicholas Kazlauskas /** 1125b04cb192SNicholas Kazlauskas * Notify DMCUB of clock update. 1126b04cb192SNicholas Kazlauskas */ 1127b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1128b04cb192SNicholas Kazlauskas }; 1129b04cb192SNicholas Kazlauskas 1130b04cb192SNicholas Kazlauskas /** 1131b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1132b04cb192SNicholas Kazlauskas */ 1133b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks { 1134b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1135b04cb192SNicholas Kazlauskas struct dmub_clocks clocks; /**< clock data */ 1136b04cb192SNicholas Kazlauskas }; 11378fe44c08SAlex Deucher 1138592a6318SAnthony Koo /** 1139592a6318SAnthony Koo * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1140592a6318SAnthony Koo */ 11417c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data { 1142592a6318SAnthony Koo union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 11437c008829SNicholas Kazlauskas }; 11447c008829SNicholas Kazlauskas 1145592a6318SAnthony Koo /** 1146592a6318SAnthony Koo * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1147592a6318SAnthony Koo */ 11487c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control { 1149592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1150592a6318SAnthony Koo struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 11517c008829SNicholas Kazlauskas }; 11527c008829SNicholas Kazlauskas 1153592a6318SAnthony Koo /** 1154592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1155592a6318SAnthony Koo */ 11567c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data { 1157592a6318SAnthony Koo struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 11587c008829SNicholas Kazlauskas }; 11597c008829SNicholas Kazlauskas 1160592a6318SAnthony Koo /** 1161592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1162592a6318SAnthony Koo */ 11637c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock { 1164592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1165592a6318SAnthony Koo struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 11667c008829SNicholas Kazlauskas }; 11677c008829SNicholas Kazlauskas 1168592a6318SAnthony Koo /** 1169592a6318SAnthony Koo * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1170592a6318SAnthony Koo */ 11717c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data { 1172592a6318SAnthony Koo struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 11737c008829SNicholas Kazlauskas }; 11747c008829SNicholas Kazlauskas 1175592a6318SAnthony Koo /** 1176592a6318SAnthony Koo * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1177592a6318SAnthony Koo */ 11787c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating { 1179592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1180592a6318SAnthony Koo struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 11817c008829SNicholas Kazlauskas }; 11827c008829SNicholas Kazlauskas 1183592a6318SAnthony Koo /** 1184592a6318SAnthony Koo * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1185592a6318SAnthony Koo */ 1186d448521eSAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 { 1187d448521eSAnthony Koo uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1188d448521eSAnthony Koo uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1189d448521eSAnthony Koo union { 1190d448521eSAnthony Koo uint8_t digmode; /**< enum atom_encode_mode_def */ 1191d448521eSAnthony Koo uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1192d448521eSAnthony Koo } mode_laneset; 1193d448521eSAnthony Koo uint8_t lanenum; /**< Number of lanes */ 1194d448521eSAnthony Koo union { 1195d448521eSAnthony Koo uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1196d448521eSAnthony Koo } symclk_units; 1197d448521eSAnthony Koo uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1198d448521eSAnthony Koo uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1199d448521eSAnthony Koo uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 12005a2730fcSFangzhi Zuo uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1201d448521eSAnthony Koo uint8_t reserved1; /**< For future use */ 1202d448521eSAnthony Koo uint8_t reserved2[3]; /**< For future use */ 1203d448521eSAnthony Koo uint32_t reserved3[11]; /**< For future use */ 1204d448521eSAnthony Koo }; 1205d448521eSAnthony Koo 1206592a6318SAnthony Koo /** 1207592a6318SAnthony Koo * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1208592a6318SAnthony Koo */ 1209d448521eSAnthony Koo union dmub_cmd_dig1_transmitter_control_data { 1210592a6318SAnthony Koo struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1211592a6318SAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 12127c008829SNicholas Kazlauskas }; 12137c008829SNicholas Kazlauskas 1214592a6318SAnthony Koo /** 1215592a6318SAnthony Koo * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1216592a6318SAnthony Koo */ 12177c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control { 1218592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1219592a6318SAnthony Koo union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 12207c008829SNicholas Kazlauskas }; 12217c008829SNicholas Kazlauskas 1222592a6318SAnthony Koo /** 1223e383b127SNicholas Kazlauskas * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1224e383b127SNicholas Kazlauskas */ 1225e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control_data { 1226e383b127SNicholas Kazlauskas uint8_t inst : 6; /**< DOMAIN instance to control */ 1227e383b127SNicholas Kazlauskas uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1228e383b127SNicholas Kazlauskas uint8_t reserved[3]; /**< Reserved for future use */ 1229e383b127SNicholas Kazlauskas }; 1230e383b127SNicholas Kazlauskas 1231e383b127SNicholas Kazlauskas /** 1232e383b127SNicholas Kazlauskas * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1233e383b127SNicholas Kazlauskas */ 1234e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control { 1235e383b127SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1236e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1237e383b127SNicholas Kazlauskas }; 1238e383b127SNicholas Kazlauskas 1239e383b127SNicholas Kazlauskas /** 124076724b76SJimmy Kizito * DPIA tunnel command parameters. 124176724b76SJimmy Kizito */ 124276724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data { 124376724b76SJimmy Kizito uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 124476724b76SJimmy Kizito uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 124576724b76SJimmy Kizito union { 124676724b76SJimmy Kizito uint8_t digmode; /** enum atom_encode_mode_def */ 124776724b76SJimmy Kizito uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 124876724b76SJimmy Kizito } mode_laneset; 124976724b76SJimmy Kizito uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 125076724b76SJimmy Kizito uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 125176724b76SJimmy Kizito uint8_t hpdsel; /** =0: HPD is not assigned */ 125276724b76SJimmy Kizito uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 125376724b76SJimmy Kizito uint8_t dpia_id; /** Index of DPIA */ 125476724b76SJimmy Kizito uint8_t fec_rdy : 1; 125576724b76SJimmy Kizito uint8_t reserved : 7; 125676724b76SJimmy Kizito uint32_t reserved1; 125776724b76SJimmy Kizito }; 125876724b76SJimmy Kizito 125976724b76SJimmy Kizito /** 126076724b76SJimmy Kizito * DMUB command for DPIA tunnel control. 126176724b76SJimmy Kizito */ 126276724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control { 126376724b76SJimmy Kizito struct dmub_cmd_header header; 126476724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data dpia_control; 126576724b76SJimmy Kizito }; 126676724b76SJimmy Kizito 126776724b76SJimmy Kizito /** 126871af9d46SMeenakshikumar Somasundaram * SET_CONFIG Command Payload 126971af9d46SMeenakshikumar Somasundaram */ 127071af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload { 127171af9d46SMeenakshikumar Somasundaram uint8_t msg_type; /* set config message type */ 127271af9d46SMeenakshikumar Somasundaram uint8_t msg_data; /* set config message data */ 127371af9d46SMeenakshikumar Somasundaram }; 127471af9d46SMeenakshikumar Somasundaram 127571af9d46SMeenakshikumar Somasundaram /** 127671af9d46SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 127771af9d46SMeenakshikumar Somasundaram */ 127871af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data { 127971af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload cmd_pkt; 128071af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */ 128171af9d46SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned in case of error */ 128271af9d46SMeenakshikumar Somasundaram }; 128371af9d46SMeenakshikumar Somasundaram 128471af9d46SMeenakshikumar Somasundaram /** 128571af9d46SMeenakshikumar Somasundaram * DMUB command structure for SET_CONFIG command. 128671af9d46SMeenakshikumar Somasundaram */ 128771af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access { 128871af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 128971af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 129071af9d46SMeenakshikumar Somasundaram }; 129171af9d46SMeenakshikumar Somasundaram 129271af9d46SMeenakshikumar Somasundaram /** 1293139a3311SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1294139a3311SMeenakshikumar Somasundaram */ 1295139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data { 1296139a3311SMeenakshikumar Somasundaram uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1297139a3311SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */ 1298139a3311SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1299139a3311SMeenakshikumar Somasundaram uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1300139a3311SMeenakshikumar Somasundaram }; 1301139a3311SMeenakshikumar Somasundaram 1302139a3311SMeenakshikumar Somasundaram /** 1303139a3311SMeenakshikumar Somasundaram * DMUB command structure for SET_ command. 1304139a3311SMeenakshikumar Somasundaram */ 1305139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots { 1306139a3311SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 1307139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1308139a3311SMeenakshikumar Somasundaram }; 1309139a3311SMeenakshikumar Somasundaram 1310139a3311SMeenakshikumar Somasundaram /** 13116f4f8ff5SMeenakshikumar Somasundaram * DMUB command structure for DPIA HPD int enable control. 13126f4f8ff5SMeenakshikumar Somasundaram */ 13136f4f8ff5SMeenakshikumar Somasundaram struct dmub_rb_cmd_dpia_hpd_int_enable { 13146f4f8ff5SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 13156f4f8ff5SMeenakshikumar Somasundaram uint32_t enable; /* dpia hpd interrupt enable */ 13166f4f8ff5SMeenakshikumar Somasundaram }; 13176f4f8ff5SMeenakshikumar Somasundaram 13186f4f8ff5SMeenakshikumar Somasundaram /** 1319592a6318SAnthony Koo * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1320592a6318SAnthony Koo */ 13217c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init { 1322592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1323592a6318SAnthony Koo uint8_t reserved[60]; /**< reserved bits */ 13247c008829SNicholas Kazlauskas }; 13257c008829SNicholas Kazlauskas 13261a595f28SAnthony Koo /** 13271a595f28SAnthony Koo * enum dp_aux_request_action - DP AUX request command listing. 13281a595f28SAnthony Koo * 13291a595f28SAnthony Koo * 4 AUX request command bits are shifted to high nibble. 13301a595f28SAnthony Koo */ 1331d9beecfcSAnthony Koo enum dp_aux_request_action { 13321a595f28SAnthony Koo /** I2C-over-AUX write request */ 1333d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 13341a595f28SAnthony Koo /** I2C-over-AUX read request */ 1335d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ = 0x10, 13361a595f28SAnthony Koo /** I2C-over-AUX write status request */ 1337d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 13381a595f28SAnthony Koo /** I2C-over-AUX write request with MOT=1 */ 1339d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 13401a595f28SAnthony Koo /** I2C-over-AUX read request with MOT=1 */ 1341d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 13421a595f28SAnthony Koo /** I2C-over-AUX write status request with MOT=1 */ 1343d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 13441a595f28SAnthony Koo /** Native AUX write request */ 1345d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 13461a595f28SAnthony Koo /** Native AUX read request */ 1347d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1348d9beecfcSAnthony Koo }; 1349d9beecfcSAnthony Koo 13501a595f28SAnthony Koo /** 13511a595f28SAnthony Koo * enum aux_return_code_type - DP AUX process return code listing. 13521a595f28SAnthony Koo */ 1353fd0f1d21SAnthony Koo enum aux_return_code_type { 13541a595f28SAnthony Koo /** AUX process succeeded */ 1355fd0f1d21SAnthony Koo AUX_RET_SUCCESS = 0, 13561a595f28SAnthony Koo /** AUX process failed with unknown reason */ 1357b6402afeSAnthony Koo AUX_RET_ERROR_UNKNOWN, 13581a595f28SAnthony Koo /** AUX process completed with invalid reply */ 1359b6402afeSAnthony Koo AUX_RET_ERROR_INVALID_REPLY, 13601a595f28SAnthony Koo /** AUX process timed out */ 1361fd0f1d21SAnthony Koo AUX_RET_ERROR_TIMEOUT, 13621a595f28SAnthony Koo /** HPD was low during AUX process */ 1363b6402afeSAnthony Koo AUX_RET_ERROR_HPD_DISCON, 13641a595f28SAnthony Koo /** Failed to acquire AUX engine */ 1365b6402afeSAnthony Koo AUX_RET_ERROR_ENGINE_ACQUIRE, 13661a595f28SAnthony Koo /** AUX request not supported */ 1367fd0f1d21SAnthony Koo AUX_RET_ERROR_INVALID_OPERATION, 13681a595f28SAnthony Koo /** AUX process not available */ 1369fd0f1d21SAnthony Koo AUX_RET_ERROR_PROTOCOL_ERROR, 1370fd0f1d21SAnthony Koo }; 1371fd0f1d21SAnthony Koo 13721a595f28SAnthony Koo /** 13731a595f28SAnthony Koo * enum aux_channel_type - DP AUX channel type listing. 13741a595f28SAnthony Koo */ 1375b6402afeSAnthony Koo enum aux_channel_type { 13761a595f28SAnthony Koo /** AUX thru Legacy DP AUX */ 1377b6402afeSAnthony Koo AUX_CHANNEL_LEGACY_DDC, 13781a595f28SAnthony Koo /** AUX thru DPIA DP tunneling */ 1379b6402afeSAnthony Koo AUX_CHANNEL_DPIA 1380b6402afeSAnthony Koo }; 1381b6402afeSAnthony Koo 13821a595f28SAnthony Koo /** 13831a595f28SAnthony Koo * struct aux_transaction_parameters - DP AUX request transaction data 13841a595f28SAnthony Koo */ 1385d9beecfcSAnthony Koo struct aux_transaction_parameters { 13861a595f28SAnthony Koo uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 13871a595f28SAnthony Koo uint8_t action; /**< enum dp_aux_request_action */ 13881a595f28SAnthony Koo uint8_t length; /**< DP AUX request data length */ 13891a595f28SAnthony Koo uint8_t reserved; /**< For future use */ 13901a595f28SAnthony Koo uint32_t address; /**< DP AUX address */ 13911a595f28SAnthony Koo uint8_t data[16]; /**< DP AUX write data */ 1392d9beecfcSAnthony Koo }; 1393d9beecfcSAnthony Koo 13941a595f28SAnthony Koo /** 13951a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 13961a595f28SAnthony Koo */ 1397d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data { 13981a595f28SAnthony Koo uint8_t instance; /**< AUX instance or DPIA instance */ 13991a595f28SAnthony Koo uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 14001a595f28SAnthony Koo uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 14011a595f28SAnthony Koo uint8_t reserved0; /**< For future use */ 14021a595f28SAnthony Koo uint16_t timeout; /**< timeout time in us */ 14031a595f28SAnthony Koo uint16_t reserved1; /**< For future use */ 14041a595f28SAnthony Koo enum aux_channel_type type; /**< enum aux_channel_type */ 14051a595f28SAnthony Koo struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1406d9beecfcSAnthony Koo }; 1407d9beecfcSAnthony Koo 14081a595f28SAnthony Koo /** 14091a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 14101a595f28SAnthony Koo */ 1411d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access { 14121a595f28SAnthony Koo /** 14131a595f28SAnthony Koo * Command header. 14141a595f28SAnthony Koo */ 1415d9beecfcSAnthony Koo struct dmub_cmd_header header; 14161a595f28SAnthony Koo /** 14171a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 14181a595f28SAnthony Koo */ 1419d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data aux_control; 1420d9beecfcSAnthony Koo }; 1421d9beecfcSAnthony Koo 14221a595f28SAnthony Koo /** 14231a595f28SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 14241a595f28SAnthony Koo */ 1425d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable { 14261a595f28SAnthony Koo /** 14271a595f28SAnthony Koo * Command header. 14281a595f28SAnthony Koo */ 1429d9beecfcSAnthony Koo struct dmub_cmd_header header; 14301a595f28SAnthony Koo /** 14311a595f28SAnthony Koo * enable: 0x0 -> disable outbox1 notification (default value) 14321a595f28SAnthony Koo * 0x1 -> enable outbox1 notification 14331a595f28SAnthony Koo */ 1434d9beecfcSAnthony Koo uint32_t enable; 1435d9beecfcSAnthony Koo }; 1436d9beecfcSAnthony Koo 1437d9beecfcSAnthony Koo /* DP AUX Reply command - OutBox Cmd */ 14381a595f28SAnthony Koo /** 14391a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14401a595f28SAnthony Koo */ 1441d9beecfcSAnthony Koo struct aux_reply_data { 14421a595f28SAnthony Koo /** 14431a595f28SAnthony Koo * Aux cmd 14441a595f28SAnthony Koo */ 1445d9beecfcSAnthony Koo uint8_t command; 14461a595f28SAnthony Koo /** 14471a595f28SAnthony Koo * Aux reply data length (max: 16 bytes) 14481a595f28SAnthony Koo */ 1449d9beecfcSAnthony Koo uint8_t length; 14501a595f28SAnthony Koo /** 14511a595f28SAnthony Koo * Alignment only 14521a595f28SAnthony Koo */ 1453d9beecfcSAnthony Koo uint8_t pad[2]; 14541a595f28SAnthony Koo /** 14551a595f28SAnthony Koo * Aux reply data 14561a595f28SAnthony Koo */ 1457d9beecfcSAnthony Koo uint8_t data[16]; 1458d9beecfcSAnthony Koo }; 1459d9beecfcSAnthony Koo 14601a595f28SAnthony Koo /** 14611a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14621a595f28SAnthony Koo */ 1463d9beecfcSAnthony Koo struct aux_reply_control_data { 14641a595f28SAnthony Koo /** 14651a595f28SAnthony Koo * Reserved for future use 14661a595f28SAnthony Koo */ 1467d9beecfcSAnthony Koo uint32_t handle; 14681a595f28SAnthony Koo /** 14691a595f28SAnthony Koo * Aux Instance 14701a595f28SAnthony Koo */ 1471b6402afeSAnthony Koo uint8_t instance; 14721a595f28SAnthony Koo /** 14731a595f28SAnthony Koo * Aux transaction result: definition in enum aux_return_code_type 14741a595f28SAnthony Koo */ 1475d9beecfcSAnthony Koo uint8_t result; 14761a595f28SAnthony Koo /** 14771a595f28SAnthony Koo * Alignment only 14781a595f28SAnthony Koo */ 1479d9beecfcSAnthony Koo uint16_t pad; 1480d9beecfcSAnthony Koo }; 1481d9beecfcSAnthony Koo 14821a595f28SAnthony Koo /** 14831a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 14841a595f28SAnthony Koo */ 1485d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply { 14861a595f28SAnthony Koo /** 14871a595f28SAnthony Koo * Command header. 14881a595f28SAnthony Koo */ 1489d9beecfcSAnthony Koo struct dmub_cmd_header header; 14901a595f28SAnthony Koo /** 14911a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14921a595f28SAnthony Koo */ 1493d9beecfcSAnthony Koo struct aux_reply_control_data control; 14941a595f28SAnthony Koo /** 14951a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14961a595f28SAnthony Koo */ 1497d9beecfcSAnthony Koo struct aux_reply_data reply_data; 1498d9beecfcSAnthony Koo }; 1499d9beecfcSAnthony Koo 1500fd0f1d21SAnthony Koo /* DP HPD Notify command - OutBox Cmd */ 15011a595f28SAnthony Koo /** 15021a595f28SAnthony Koo * DP HPD Type 15031a595f28SAnthony Koo */ 1504fd0f1d21SAnthony Koo enum dp_hpd_type { 15051a595f28SAnthony Koo /** 15061a595f28SAnthony Koo * Normal DP HPD 15071a595f28SAnthony Koo */ 1508fd0f1d21SAnthony Koo DP_HPD = 0, 15091a595f28SAnthony Koo /** 15101a595f28SAnthony Koo * DP HPD short pulse 15111a595f28SAnthony Koo */ 1512fd0f1d21SAnthony Koo DP_IRQ 1513fd0f1d21SAnthony Koo }; 1514fd0f1d21SAnthony Koo 15151a595f28SAnthony Koo /** 15161a595f28SAnthony Koo * DP HPD Status 15171a595f28SAnthony Koo */ 1518fd0f1d21SAnthony Koo enum dp_hpd_status { 15191a595f28SAnthony Koo /** 15201a595f28SAnthony Koo * DP_HPD status low 15211a595f28SAnthony Koo */ 1522fd0f1d21SAnthony Koo DP_HPD_UNPLUG = 0, 15231a595f28SAnthony Koo /** 15241a595f28SAnthony Koo * DP_HPD status high 15251a595f28SAnthony Koo */ 1526fd0f1d21SAnthony Koo DP_HPD_PLUG 1527fd0f1d21SAnthony Koo }; 1528fd0f1d21SAnthony Koo 15291a595f28SAnthony Koo /** 15301a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 15311a595f28SAnthony Koo */ 1532d9beecfcSAnthony Koo struct dp_hpd_data { 15331a595f28SAnthony Koo /** 15341a595f28SAnthony Koo * DP HPD instance 15351a595f28SAnthony Koo */ 1536b6402afeSAnthony Koo uint8_t instance; 15371a595f28SAnthony Koo /** 15381a595f28SAnthony Koo * HPD type 15391a595f28SAnthony Koo */ 1540d9beecfcSAnthony Koo uint8_t hpd_type; 15411a595f28SAnthony Koo /** 15421a595f28SAnthony Koo * HPD status: only for type: DP_HPD to indicate status 15431a595f28SAnthony Koo */ 1544d9beecfcSAnthony Koo uint8_t hpd_status; 15451a595f28SAnthony Koo /** 15461a595f28SAnthony Koo * Alignment only 15471a595f28SAnthony Koo */ 1548d9beecfcSAnthony Koo uint8_t pad; 1549d9beecfcSAnthony Koo }; 1550d9beecfcSAnthony Koo 15511a595f28SAnthony Koo /** 15521a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 15531a595f28SAnthony Koo */ 1554d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify { 15551a595f28SAnthony Koo /** 15561a595f28SAnthony Koo * Command header. 15571a595f28SAnthony Koo */ 1558d9beecfcSAnthony Koo struct dmub_cmd_header header; 15591a595f28SAnthony Koo /** 15601a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 15611a595f28SAnthony Koo */ 1562d9beecfcSAnthony Koo struct dp_hpd_data hpd_data; 1563d9beecfcSAnthony Koo }; 1564d9beecfcSAnthony Koo 156571af9d46SMeenakshikumar Somasundaram /** 156671af9d46SMeenakshikumar Somasundaram * Definition of a SET_CONFIG reply from DPOA. 156771af9d46SMeenakshikumar Somasundaram */ 156871af9d46SMeenakshikumar Somasundaram enum set_config_status { 156971af9d46SMeenakshikumar Somasundaram SET_CONFIG_PENDING = 0, 157071af9d46SMeenakshikumar Somasundaram SET_CONFIG_ACK_RECEIVED, 157171af9d46SMeenakshikumar Somasundaram SET_CONFIG_RX_TIMEOUT, 157271af9d46SMeenakshikumar Somasundaram SET_CONFIG_UNKNOWN_ERROR, 157371af9d46SMeenakshikumar Somasundaram }; 157471af9d46SMeenakshikumar Somasundaram 157571af9d46SMeenakshikumar Somasundaram /** 157671af9d46SMeenakshikumar Somasundaram * Definition of a set_config reply 157771af9d46SMeenakshikumar Somasundaram */ 157871af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data { 157971af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA Instance */ 158071af9d46SMeenakshikumar Somasundaram uint8_t status; /* Set Config reply */ 158171af9d46SMeenakshikumar Somasundaram uint16_t pad; /* Alignment */ 158271af9d46SMeenakshikumar Somasundaram }; 158371af9d46SMeenakshikumar Somasundaram 158471af9d46SMeenakshikumar Somasundaram /** 158571af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 158671af9d46SMeenakshikumar Somasundaram */ 158771af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply { 158871af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; 158971af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data set_config_reply_control; 159071af9d46SMeenakshikumar Somasundaram }; 159171af9d46SMeenakshikumar Somasundaram 1592ea5a4db9SAnthony Koo /** 15938af54c61SMustapha Ghaddar * Definition of a DPIA notification header 15948af54c61SMustapha Ghaddar */ 15958af54c61SMustapha Ghaddar struct dpia_notification_header { 15968af54c61SMustapha Ghaddar uint8_t instance; /**< DPIA Instance */ 15978af54c61SMustapha Ghaddar uint8_t reserved[3]; 15988af54c61SMustapha Ghaddar enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 15998af54c61SMustapha Ghaddar }; 16008af54c61SMustapha Ghaddar 16018af54c61SMustapha Ghaddar /** 16028af54c61SMustapha Ghaddar * Definition of the common data struct of DPIA notification 16038af54c61SMustapha Ghaddar */ 16048af54c61SMustapha Ghaddar struct dpia_notification_common { 16058af54c61SMustapha Ghaddar uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 16068af54c61SMustapha Ghaddar - sizeof(struct dpia_notification_header)]; 16078af54c61SMustapha Ghaddar }; 16088af54c61SMustapha Ghaddar 16098af54c61SMustapha Ghaddar /** 16108af54c61SMustapha Ghaddar * Definition of a DPIA notification data 16118af54c61SMustapha Ghaddar */ 16128af54c61SMustapha Ghaddar struct dpia_bw_allocation_notify_data { 16138af54c61SMustapha Ghaddar union { 16148af54c61SMustapha Ghaddar struct { 16158af54c61SMustapha Ghaddar uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 16168af54c61SMustapha Ghaddar uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 16178af54c61SMustapha Ghaddar uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 16188af54c61SMustapha Ghaddar uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 16198af54c61SMustapha Ghaddar uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 16208af54c61SMustapha Ghaddar uint16_t reserved: 11; /**< Reserved */ 16218af54c61SMustapha Ghaddar } bits; 16228af54c61SMustapha Ghaddar 16238af54c61SMustapha Ghaddar uint16_t flags; 16248af54c61SMustapha Ghaddar }; 16258af54c61SMustapha Ghaddar 16268af54c61SMustapha Ghaddar uint8_t cm_id; /**< CM ID */ 16278af54c61SMustapha Ghaddar uint8_t group_id; /**< Group ID */ 16288af54c61SMustapha Ghaddar uint8_t granularity; /**< BW Allocation Granularity */ 16298af54c61SMustapha Ghaddar uint8_t estimated_bw; /**< Estimated_BW */ 16308af54c61SMustapha Ghaddar uint8_t allocated_bw; /**< Allocated_BW */ 16318af54c61SMustapha Ghaddar uint8_t reserved; 16328af54c61SMustapha Ghaddar }; 16338af54c61SMustapha Ghaddar 16348af54c61SMustapha Ghaddar /** 16358af54c61SMustapha Ghaddar * union dpia_notify_data_type - DPIA Notification in Outbox command 16368af54c61SMustapha Ghaddar */ 16378af54c61SMustapha Ghaddar union dpia_notification_data { 16388af54c61SMustapha Ghaddar /** 16398af54c61SMustapha Ghaddar * DPIA Notification for common data struct 16408af54c61SMustapha Ghaddar */ 16418af54c61SMustapha Ghaddar struct dpia_notification_common common_data; 16428af54c61SMustapha Ghaddar 16438af54c61SMustapha Ghaddar /** 16448af54c61SMustapha Ghaddar * DPIA Notification for DP BW Allocation support 16458af54c61SMustapha Ghaddar */ 16468af54c61SMustapha Ghaddar struct dpia_bw_allocation_notify_data dpia_bw_alloc; 16478af54c61SMustapha Ghaddar }; 16488af54c61SMustapha Ghaddar 16498af54c61SMustapha Ghaddar /** 16508af54c61SMustapha Ghaddar * Definition of a DPIA notification payload 16518af54c61SMustapha Ghaddar */ 16528af54c61SMustapha Ghaddar struct dpia_notification_payload { 16538af54c61SMustapha Ghaddar struct dpia_notification_header header; 16548af54c61SMustapha Ghaddar union dpia_notification_data data; /**< DPIA notification payload data */ 16558af54c61SMustapha Ghaddar }; 16568af54c61SMustapha Ghaddar 16578af54c61SMustapha Ghaddar /** 16588af54c61SMustapha Ghaddar * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 16598af54c61SMustapha Ghaddar */ 16608af54c61SMustapha Ghaddar struct dmub_rb_cmd_dpia_notification { 16618af54c61SMustapha Ghaddar struct dmub_cmd_header header; /**< DPIA notification header */ 16628af54c61SMustapha Ghaddar struct dpia_notification_payload payload; /**< DPIA notification payload */ 16638af54c61SMustapha Ghaddar }; 16648af54c61SMustapha Ghaddar 16658af54c61SMustapha Ghaddar /** 1666ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1667ea5a4db9SAnthony Koo */ 1668ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data { 1669ea5a4db9SAnthony Koo uint8_t instance; /**< HPD instance or DPIA instance */ 1670ea5a4db9SAnthony Koo uint8_t result; /**< For returning HPD state */ 1671874714feSAnthony Koo uint16_t pad; /** < Alignment */ 1672ea5a4db9SAnthony Koo enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1673ea5a4db9SAnthony Koo enum aux_return_code_type status; /**< for returning the status of command */ 1674ea5a4db9SAnthony Koo }; 1675ea5a4db9SAnthony Koo 1676ea5a4db9SAnthony Koo /** 1677ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1678ea5a4db9SAnthony Koo */ 1679ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state { 1680ea5a4db9SAnthony Koo /** 1681ea5a4db9SAnthony Koo * Command header. 1682ea5a4db9SAnthony Koo */ 1683ea5a4db9SAnthony Koo struct dmub_cmd_header header; 1684ea5a4db9SAnthony Koo /** 1685ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1686ea5a4db9SAnthony Koo */ 1687ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data data; 1688ea5a4db9SAnthony Koo }; 1689ea5a4db9SAnthony Koo 169084034ad4SAnthony Koo /* 169184034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 169284034ad4SAnthony Koo * Do not reuse or modify IDs. 169384034ad4SAnthony Koo */ 169484034ad4SAnthony Koo 16951a595f28SAnthony Koo /** 16961a595f28SAnthony Koo * PSR command sub-types. 16971a595f28SAnthony Koo */ 169884034ad4SAnthony Koo enum dmub_cmd_psr_type { 16991a595f28SAnthony Koo /** 17001a595f28SAnthony Koo * Set PSR version support. 17011a595f28SAnthony Koo */ 170284034ad4SAnthony Koo DMUB_CMD__PSR_SET_VERSION = 0, 17031a595f28SAnthony Koo /** 17041a595f28SAnthony Koo * Copy driver-calculated parameters to PSR state. 17051a595f28SAnthony Koo */ 170684034ad4SAnthony Koo DMUB_CMD__PSR_COPY_SETTINGS = 1, 17071a595f28SAnthony Koo /** 17081a595f28SAnthony Koo * Enable PSR. 17091a595f28SAnthony Koo */ 171084034ad4SAnthony Koo DMUB_CMD__PSR_ENABLE = 2, 17111a595f28SAnthony Koo 17121a595f28SAnthony Koo /** 17131a595f28SAnthony Koo * Disable PSR. 17141a595f28SAnthony Koo */ 171584034ad4SAnthony Koo DMUB_CMD__PSR_DISABLE = 3, 17161a595f28SAnthony Koo 17171a595f28SAnthony Koo /** 17181a595f28SAnthony Koo * Set PSR level. 17191a595f28SAnthony Koo * PSR level is a 16-bit value dicated by driver that 17201a595f28SAnthony Koo * will enable/disable different functionality. 17211a595f28SAnthony Koo */ 172284034ad4SAnthony Koo DMUB_CMD__PSR_SET_LEVEL = 4, 17231a595f28SAnthony Koo 17241a595f28SAnthony Koo /** 17251a595f28SAnthony Koo * Forces PSR enabled until an explicit PSR disable call. 17261a595f28SAnthony Koo */ 1727672251b2SAnthony Koo DMUB_CMD__PSR_FORCE_STATIC = 5, 1728e5dfcd27SRobin Chen /** 172983eb5385SDavid Zhang * Set vtotal in psr active for FreeSync PSR. 173083eb5385SDavid Zhang */ 173183eb5385SDavid Zhang DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 173283eb5385SDavid Zhang /** 1733e5dfcd27SRobin Chen * Set PSR power option 1734e5dfcd27SRobin Chen */ 1735e5dfcd27SRobin Chen DMUB_CMD__SET_PSR_POWER_OPT = 7, 173684034ad4SAnthony Koo }; 173784034ad4SAnthony Koo 173885f4bc0cSAlvin Lee enum dmub_cmd_fams_type { 173985f4bc0cSAlvin Lee DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 174085f4bc0cSAlvin Lee DMUB_CMD__FAMS_DRR_UPDATE = 1, 174185f4bc0cSAlvin Lee DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 174281f776b6SAnthony Koo /** 174381f776b6SAnthony Koo * For SubVP set manual trigger in FW because it 174481f776b6SAnthony Koo * triggers DRR_UPDATE_PENDING which SubVP relies 174581f776b6SAnthony Koo * on (for any SubVP cases that use a DRR display) 174681f776b6SAnthony Koo */ 174781f776b6SAnthony Koo DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 174885f4bc0cSAlvin Lee }; 174985f4bc0cSAlvin Lee 17501a595f28SAnthony Koo /** 17511a595f28SAnthony Koo * PSR versions. 17521a595f28SAnthony Koo */ 175384034ad4SAnthony Koo enum psr_version { 17541a595f28SAnthony Koo /** 17551a595f28SAnthony Koo * PSR version 1. 17561a595f28SAnthony Koo */ 175784034ad4SAnthony Koo PSR_VERSION_1 = 0, 17581a595f28SAnthony Koo /** 175983eb5385SDavid Zhang * Freesync PSR SU. 176083eb5385SDavid Zhang */ 176183eb5385SDavid Zhang PSR_VERSION_SU_1 = 1, 176283eb5385SDavid Zhang /** 17631a595f28SAnthony Koo * PSR not supported. 17641a595f28SAnthony Koo */ 176584034ad4SAnthony Koo PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 176684034ad4SAnthony Koo }; 176784034ad4SAnthony Koo 1768592a6318SAnthony Koo /** 1769592a6318SAnthony Koo * enum dmub_cmd_mall_type - MALL commands 1770592a6318SAnthony Koo */ 177152f2e83eSBhawanpreet Lakha enum dmub_cmd_mall_type { 1772592a6318SAnthony Koo /** 1773592a6318SAnthony Koo * Allows display refresh from MALL. 1774592a6318SAnthony Koo */ 177552f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_ALLOW = 0, 1776592a6318SAnthony Koo /** 1777592a6318SAnthony Koo * Disallows display refresh from MALL. 1778592a6318SAnthony Koo */ 177952f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1780592a6318SAnthony Koo /** 1781592a6318SAnthony Koo * Cursor copy for MALL. 1782592a6318SAnthony Koo */ 178352f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1784592a6318SAnthony Koo /** 1785592a6318SAnthony Koo * Controls DF requests. 1786592a6318SAnthony Koo */ 1787ea7154d8SBhawanpreet Lakha DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 178852f2e83eSBhawanpreet Lakha }; 178952f2e83eSBhawanpreet Lakha 1790a91b402dSCharlene Liu /** 179178174f47SAnthony Koo * PHY Link rate for DP. 179278174f47SAnthony Koo */ 179378174f47SAnthony Koo enum phy_link_rate { 179478174f47SAnthony Koo /** 179578174f47SAnthony Koo * not supported. 179678174f47SAnthony Koo */ 179778174f47SAnthony Koo PHY_RATE_UNKNOWN = 0, 179878174f47SAnthony Koo /** 179978174f47SAnthony Koo * Rate_1 (RBR) - 1.62 Gbps/Lane 180078174f47SAnthony Koo */ 180178174f47SAnthony Koo PHY_RATE_162 = 1, 180278174f47SAnthony Koo /** 180378174f47SAnthony Koo * Rate_2 - 2.16 Gbps/Lane 180478174f47SAnthony Koo */ 180578174f47SAnthony Koo PHY_RATE_216 = 2, 180678174f47SAnthony Koo /** 180778174f47SAnthony Koo * Rate_3 - 2.43 Gbps/Lane 180878174f47SAnthony Koo */ 180978174f47SAnthony Koo PHY_RATE_243 = 3, 181078174f47SAnthony Koo /** 181178174f47SAnthony Koo * Rate_4 (HBR) - 2.70 Gbps/Lane 181278174f47SAnthony Koo */ 181378174f47SAnthony Koo PHY_RATE_270 = 4, 181478174f47SAnthony Koo /** 181578174f47SAnthony Koo * Rate_5 (RBR2)- 3.24 Gbps/Lane 181678174f47SAnthony Koo */ 181778174f47SAnthony Koo PHY_RATE_324 = 5, 181878174f47SAnthony Koo /** 181978174f47SAnthony Koo * Rate_6 - 4.32 Gbps/Lane 182078174f47SAnthony Koo */ 182178174f47SAnthony Koo PHY_RATE_432 = 6, 182278174f47SAnthony Koo /** 182378174f47SAnthony Koo * Rate_7 (HBR2)- 5.40 Gbps/Lane 182478174f47SAnthony Koo */ 182578174f47SAnthony Koo PHY_RATE_540 = 7, 182678174f47SAnthony Koo /** 182778174f47SAnthony Koo * Rate_8 (HBR3)- 8.10 Gbps/Lane 182878174f47SAnthony Koo */ 182978174f47SAnthony Koo PHY_RATE_810 = 8, 183078174f47SAnthony Koo /** 183178174f47SAnthony Koo * UHBR10 - 10.0 Gbps/Lane 183278174f47SAnthony Koo */ 183378174f47SAnthony Koo PHY_RATE_1000 = 9, 183478174f47SAnthony Koo /** 183578174f47SAnthony Koo * UHBR13.5 - 13.5 Gbps/Lane 183678174f47SAnthony Koo */ 183778174f47SAnthony Koo PHY_RATE_1350 = 10, 183878174f47SAnthony Koo /** 183978174f47SAnthony Koo * UHBR10 - 20.0 Gbps/Lane 184078174f47SAnthony Koo */ 184178174f47SAnthony Koo PHY_RATE_2000 = 11, 184278174f47SAnthony Koo }; 184378174f47SAnthony Koo 184478174f47SAnthony Koo /** 184578174f47SAnthony Koo * enum dmub_phy_fsm_state - PHY FSM states. 184678174f47SAnthony Koo * PHY FSM state to transit to during PSR enable/disable. 184778174f47SAnthony Koo */ 184878174f47SAnthony Koo enum dmub_phy_fsm_state { 184978174f47SAnthony Koo DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 185078174f47SAnthony Koo DMUB_PHY_FSM_RESET, 185178174f47SAnthony Koo DMUB_PHY_FSM_RESET_RELEASED, 185278174f47SAnthony Koo DMUB_PHY_FSM_SRAM_LOAD_DONE, 185378174f47SAnthony Koo DMUB_PHY_FSM_INITIALIZED, 185478174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED, 185578174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_LP, 185678174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_PG, 185778174f47SAnthony Koo DMUB_PHY_FSM_POWER_DOWN, 185878174f47SAnthony Koo DMUB_PHY_FSM_PLL_EN, 185978174f47SAnthony Koo DMUB_PHY_FSM_TX_EN, 186078174f47SAnthony Koo DMUB_PHY_FSM_FAST_LP, 186178174f47SAnthony Koo }; 186278174f47SAnthony Koo 186378174f47SAnthony Koo /** 18641a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 18651a595f28SAnthony Koo */ 18667c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data { 18671a595f28SAnthony Koo /** 18681a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 18691a595f28SAnthony Koo */ 18707b8a6362SAnthony Koo union dmub_psr_debug_flags debug; 18711a595f28SAnthony Koo /** 18721a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 18731a595f28SAnthony Koo */ 18744c1a1335SWyatt Wood uint16_t psr_level; 18751a595f28SAnthony Koo /** 18761a595f28SAnthony Koo * DPP HW instance. 18771a595f28SAnthony Koo */ 18784c1a1335SWyatt Wood uint8_t dpp_inst; 18791a595f28SAnthony Koo /** 18801a595f28SAnthony Koo * MPCC HW instance. 18811a595f28SAnthony Koo * Not used in dmub fw, 188234ba432cSAnthony Koo * dmub fw will get active opp by reading odm registers. 188334ba432cSAnthony Koo */ 18844c1a1335SWyatt Wood uint8_t mpcc_inst; 18851a595f28SAnthony Koo /** 18861a595f28SAnthony Koo * OPP HW instance. 18871a595f28SAnthony Koo * Not used in dmub fw, 18881a595f28SAnthony Koo * dmub fw will get active opp by reading odm registers. 18891a595f28SAnthony Koo */ 18904c1a1335SWyatt Wood uint8_t opp_inst; 18911a595f28SAnthony Koo /** 18921a595f28SAnthony Koo * OTG HW instance. 18931a595f28SAnthony Koo */ 18944c1a1335SWyatt Wood uint8_t otg_inst; 18951a595f28SAnthony Koo /** 18961a595f28SAnthony Koo * DIG FE HW instance. 18971a595f28SAnthony Koo */ 18984c1a1335SWyatt Wood uint8_t digfe_inst; 18991a595f28SAnthony Koo /** 19001a595f28SAnthony Koo * DIG BE HW instance. 19011a595f28SAnthony Koo */ 19024c1a1335SWyatt Wood uint8_t digbe_inst; 19031a595f28SAnthony Koo /** 19041a595f28SAnthony Koo * DP PHY HW instance. 19051a595f28SAnthony Koo */ 19064c1a1335SWyatt Wood uint8_t dpphy_inst; 19071a595f28SAnthony Koo /** 19081a595f28SAnthony Koo * AUX HW instance. 19091a595f28SAnthony Koo */ 19104c1a1335SWyatt Wood uint8_t aux_inst; 19111a595f28SAnthony Koo /** 19121a595f28SAnthony Koo * Determines if SMU optimzations are enabled/disabled. 19131a595f28SAnthony Koo */ 19144c1a1335SWyatt Wood uint8_t smu_optimizations_en; 19151a595f28SAnthony Koo /** 19161a595f28SAnthony Koo * Unused. 19171a595f28SAnthony Koo * TODO: Remove. 19181a595f28SAnthony Koo */ 19194c1a1335SWyatt Wood uint8_t frame_delay; 19201a595f28SAnthony Koo /** 19211a595f28SAnthony Koo * If RFB setup time is greater than the total VBLANK time, 19221a595f28SAnthony Koo * it is not possible for the sink to capture the video frame 19231a595f28SAnthony Koo * in the same frame the SDP is sent. In this case, 19241a595f28SAnthony Koo * the frame capture indication bit should be set and an extra 19251a595f28SAnthony Koo * static frame should be transmitted to the sink. 19261a595f28SAnthony Koo */ 19274c1a1335SWyatt Wood uint8_t frame_cap_ind; 19281a595f28SAnthony Koo /** 192983eb5385SDavid Zhang * Granularity of Y offset supported by sink. 19301a595f28SAnthony Koo */ 193183eb5385SDavid Zhang uint8_t su_y_granularity; 193283eb5385SDavid Zhang /** 193383eb5385SDavid Zhang * Indicates whether sink should start capturing 193483eb5385SDavid Zhang * immediately following active scan line, 193583eb5385SDavid Zhang * or starting with the 2nd active scan line. 193683eb5385SDavid Zhang */ 193783eb5385SDavid Zhang uint8_t line_capture_indication; 19381a595f28SAnthony Koo /** 19391a595f28SAnthony Koo * Multi-display optimizations are implemented on certain ASICs. 19401a595f28SAnthony Koo */ 1941175f0971SYongqiang Sun uint8_t multi_disp_optimizations_en; 19421a595f28SAnthony Koo /** 19431a595f28SAnthony Koo * The last possible line SDP may be transmitted without violating 19441a595f28SAnthony Koo * the RFB setup time or entering the active video frame. 19451a595f28SAnthony Koo */ 194678ead771SAnthony Koo uint16_t init_sdp_deadline; 19471a595f28SAnthony Koo /** 194883eb5385SDavid Zhang * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 19491a595f28SAnthony Koo */ 195083eb5385SDavid Zhang uint8_t rate_control_caps ; 195183eb5385SDavid Zhang /* 195283eb5385SDavid Zhang * Force PSRSU always doing full frame update 195383eb5385SDavid Zhang */ 195483eb5385SDavid Zhang uint8_t force_ffu_mode; 19551a595f28SAnthony Koo /** 19561a595f28SAnthony Koo * Length of each horizontal line in us. 19571a595f28SAnthony Koo */ 19589b56f6bcSAnthony Koo uint32_t line_time_in_us; 1959ecc11601SAnthony Koo /** 1960ecc11601SAnthony Koo * FEC enable status in driver 1961ecc11601SAnthony Koo */ 1962ecc11601SAnthony Koo uint8_t fec_enable_status; 1963ecc11601SAnthony Koo /** 1964ecc11601SAnthony Koo * FEC re-enable delay when PSR exit. 1965ecc11601SAnthony Koo * unit is 100us, range form 0~255(0xFF). 1966ecc11601SAnthony Koo */ 1967ecc11601SAnthony Koo uint8_t fec_enable_delay_in100us; 1968ecc11601SAnthony Koo /** 1969f56c837aSMikita Lipski * PSR control version. 1970ecc11601SAnthony Koo */ 1971f56c837aSMikita Lipski uint8_t cmd_version; 1972f56c837aSMikita Lipski /** 1973f56c837aSMikita Lipski * Panel Instance. 1974*36e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 1975f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1976f56c837aSMikita Lipski */ 1977f56c837aSMikita Lipski uint8_t panel_inst; 19782665f63aSMikita Lipski /* 19792665f63aSMikita Lipski * DSC enable status in driver 1980360d1b65SIan Chen */ 19812665f63aSMikita Lipski uint8_t dsc_enable_status; 1982b5175966SShah Dharati /* 1983b5175966SShah Dharati * Use FSM state for PSR power up/down 19842665f63aSMikita Lipski */ 1985b5175966SShah Dharati uint8_t use_phy_fsm; 1986b5175966SShah Dharati /** 19871a2b886bSRyan Lin * frame delay for frame re-lock 19881a2b886bSRyan Lin */ 19891a2b886bSRyan Lin uint8_t relock_delay_frame_cnt; 19901a2b886bSRyan Lin /** 1991b5175966SShah Dharati * Explicit padding to 2 byte boundary. 1992b5175966SShah Dharati */ 19931a2b886bSRyan Lin uint8_t pad3; 1994c84ff24aSRobin Chen /** 1995c84ff24aSRobin Chen * DSC Slice height. 1996c84ff24aSRobin Chen */ 1997c84ff24aSRobin Chen uint16_t dsc_slice_height; 1998c84ff24aSRobin Chen /** 1999c84ff24aSRobin Chen * Explicit padding to 4 byte boundary. 2000c84ff24aSRobin Chen */ 2001c84ff24aSRobin Chen uint16_t pad; 20027c008829SNicholas Kazlauskas }; 20037c008829SNicholas Kazlauskas 20041a595f28SAnthony Koo /** 20051a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 20061a595f28SAnthony Koo */ 20077c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings { 20081a595f28SAnthony Koo /** 20091a595f28SAnthony Koo * Command header. 20101a595f28SAnthony Koo */ 20117c008829SNicholas Kazlauskas struct dmub_cmd_header header; 20121a595f28SAnthony Koo /** 20131a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 20141a595f28SAnthony Koo */ 20157c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 20167c008829SNicholas Kazlauskas }; 20177c008829SNicholas Kazlauskas 20181a595f28SAnthony Koo /** 20191a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 20201a595f28SAnthony Koo */ 20217c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data { 20221a595f28SAnthony Koo /** 20231a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 20241a595f28SAnthony Koo */ 20257c008829SNicholas Kazlauskas uint16_t psr_level; 20261a595f28SAnthony Koo /** 2027f56c837aSMikita Lipski * PSR control version. 20281a595f28SAnthony Koo */ 2029f56c837aSMikita Lipski uint8_t cmd_version; 2030f56c837aSMikita Lipski /** 2031f56c837aSMikita Lipski * Panel Instance. 2032*36e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2033f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2034f56c837aSMikita Lipski */ 2035f56c837aSMikita Lipski uint8_t panel_inst; 20367c008829SNicholas Kazlauskas }; 20377c008829SNicholas Kazlauskas 20381a595f28SAnthony Koo /** 20391a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 20401a595f28SAnthony Koo */ 20417c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level { 20421a595f28SAnthony Koo /** 20431a595f28SAnthony Koo * Command header. 20441a595f28SAnthony Koo */ 20457c008829SNicholas Kazlauskas struct dmub_cmd_header header; 20461a595f28SAnthony Koo /** 20471a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 20481a595f28SAnthony Koo */ 20497c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data psr_set_level_data; 20507c008829SNicholas Kazlauskas }; 20517c008829SNicholas Kazlauskas 2052f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data { 2053f56c837aSMikita Lipski /** 2054f56c837aSMikita Lipski * PSR control version. 2055f56c837aSMikita Lipski */ 2056f56c837aSMikita Lipski uint8_t cmd_version; 2057f56c837aSMikita Lipski /** 2058f56c837aSMikita Lipski * Panel Instance. 2059*36e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2060f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2061f56c837aSMikita Lipski */ 2062f56c837aSMikita Lipski uint8_t panel_inst; 2063f56c837aSMikita Lipski /** 206478174f47SAnthony Koo * Phy state to enter. 206578174f47SAnthony Koo * Values to use are defined in dmub_phy_fsm_state 2066f56c837aSMikita Lipski */ 206778174f47SAnthony Koo uint8_t phy_fsm_state; 206878174f47SAnthony Koo /** 206978174f47SAnthony Koo * Phy rate for DP - RBR/HBR/HBR2/HBR3. 207078174f47SAnthony Koo * Set this using enum phy_link_rate. 207178174f47SAnthony Koo * This does not support HDMI/DP2 for now. 207278174f47SAnthony Koo */ 207378174f47SAnthony Koo uint8_t phy_rate; 2074f56c837aSMikita Lipski }; 2075f56c837aSMikita Lipski 20761a595f28SAnthony Koo /** 20771a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 20781a595f28SAnthony Koo * PSR enable/disable is controlled using the sub_type. 20791a595f28SAnthony Koo */ 20807c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_enable { 20811a595f28SAnthony Koo /** 20821a595f28SAnthony Koo * Command header. 20831a595f28SAnthony Koo */ 20847c008829SNicholas Kazlauskas struct dmub_cmd_header header; 2085f56c837aSMikita Lipski 2086f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data data; 20877c008829SNicholas Kazlauskas }; 20887c008829SNicholas Kazlauskas 20891a595f28SAnthony Koo /** 20901a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 20911a595f28SAnthony Koo */ 2092d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data { 20931a595f28SAnthony Koo /** 20941a595f28SAnthony Koo * PSR version that FW should implement. 20951a595f28SAnthony Koo */ 20961a595f28SAnthony Koo enum psr_version version; 2097f56c837aSMikita Lipski /** 2098f56c837aSMikita Lipski * PSR control version. 2099f56c837aSMikita Lipski */ 2100f56c837aSMikita Lipski uint8_t cmd_version; 2101f56c837aSMikita Lipski /** 2102f56c837aSMikita Lipski * Panel Instance. 2103*36e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2104f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2105f56c837aSMikita Lipski */ 2106f56c837aSMikita Lipski uint8_t panel_inst; 2107f56c837aSMikita Lipski /** 2108f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 2109f56c837aSMikita Lipski */ 2110f56c837aSMikita Lipski uint8_t pad[2]; 21117c008829SNicholas Kazlauskas }; 21127c008829SNicholas Kazlauskas 21131a595f28SAnthony Koo /** 21141a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 21151a595f28SAnthony Koo */ 2116d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version { 21171a595f28SAnthony Koo /** 21181a595f28SAnthony Koo * Command header. 21191a595f28SAnthony Koo */ 21207c008829SNicholas Kazlauskas struct dmub_cmd_header header; 21211a595f28SAnthony Koo /** 21221a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 21231a595f28SAnthony Koo */ 2124d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data psr_set_version_data; 21257c008829SNicholas Kazlauskas }; 21267c008829SNicholas Kazlauskas 2127f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data { 2128f56c837aSMikita Lipski /** 2129f56c837aSMikita Lipski * PSR control version. 2130f56c837aSMikita Lipski */ 2131f56c837aSMikita Lipski uint8_t cmd_version; 2132f56c837aSMikita Lipski /** 2133f56c837aSMikita Lipski * Panel Instance. 2134*36e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2135f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2136f56c837aSMikita Lipski */ 2137f56c837aSMikita Lipski uint8_t panel_inst; 2138f56c837aSMikita Lipski /** 2139ad371c8aSAnthony Koo * Explicit padding to 4 byte boundary. 2140f56c837aSMikita Lipski */ 2141ad371c8aSAnthony Koo uint8_t pad[2]; 2142f56c837aSMikita Lipski }; 2143f56c837aSMikita Lipski 21441a595f28SAnthony Koo /** 21451a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 21461a595f28SAnthony Koo */ 2147672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static { 21481a595f28SAnthony Koo /** 21491a595f28SAnthony Koo * Command header. 21501a595f28SAnthony Koo */ 2151672251b2SAnthony Koo struct dmub_cmd_header header; 2152f56c837aSMikita Lipski /** 2153f56c837aSMikita Lipski * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2154f56c837aSMikita Lipski */ 2155f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data psr_force_static_data; 2156672251b2SAnthony Koo }; 2157672251b2SAnthony Koo 21581a595f28SAnthony Koo /** 215983eb5385SDavid Zhang * PSR SU debug flags. 216083eb5385SDavid Zhang */ 216183eb5385SDavid Zhang union dmub_psr_su_debug_flags { 216283eb5385SDavid Zhang /** 216383eb5385SDavid Zhang * PSR SU debug flags. 216483eb5385SDavid Zhang */ 216583eb5385SDavid Zhang struct { 216683eb5385SDavid Zhang /** 216783eb5385SDavid Zhang * Update dirty rect in SW only. 216883eb5385SDavid Zhang */ 216983eb5385SDavid Zhang uint8_t update_dirty_rect_only : 1; 217083eb5385SDavid Zhang /** 217183eb5385SDavid Zhang * Reset the cursor/plane state before processing the call. 217283eb5385SDavid Zhang */ 217383eb5385SDavid Zhang uint8_t reset_state : 1; 217483eb5385SDavid Zhang } bitfields; 217583eb5385SDavid Zhang 217683eb5385SDavid Zhang /** 217783eb5385SDavid Zhang * Union for debug flags. 217883eb5385SDavid Zhang */ 217983eb5385SDavid Zhang uint32_t u32All; 218083eb5385SDavid Zhang }; 218183eb5385SDavid Zhang 218283eb5385SDavid Zhang /** 218383eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 218483eb5385SDavid Zhang * This triggers a selective update for PSR SU. 218583eb5385SDavid Zhang */ 218683eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data { 218783eb5385SDavid Zhang /** 218883eb5385SDavid Zhang * Dirty rects from OS. 218983eb5385SDavid Zhang */ 219083eb5385SDavid Zhang struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 219183eb5385SDavid Zhang /** 219283eb5385SDavid Zhang * PSR SU debug flags. 219383eb5385SDavid Zhang */ 219483eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags; 219583eb5385SDavid Zhang /** 219683eb5385SDavid Zhang * OTG HW instance. 219783eb5385SDavid Zhang */ 219883eb5385SDavid Zhang uint8_t pipe_idx; 219983eb5385SDavid Zhang /** 220083eb5385SDavid Zhang * Number of dirty rects. 220183eb5385SDavid Zhang */ 220283eb5385SDavid Zhang uint8_t dirty_rect_count; 220383eb5385SDavid Zhang /** 220483eb5385SDavid Zhang * PSR control version. 220583eb5385SDavid Zhang */ 220683eb5385SDavid Zhang uint8_t cmd_version; 220783eb5385SDavid Zhang /** 220883eb5385SDavid Zhang * Panel Instance. 2209*36e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 221083eb5385SDavid Zhang * Currently the support is only for 0 or 1 221183eb5385SDavid Zhang */ 221283eb5385SDavid Zhang uint8_t panel_inst; 221383eb5385SDavid Zhang }; 221483eb5385SDavid Zhang 221583eb5385SDavid Zhang /** 221683eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 221783eb5385SDavid Zhang */ 221883eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect { 221983eb5385SDavid Zhang /** 222083eb5385SDavid Zhang * Command header. 222183eb5385SDavid Zhang */ 222283eb5385SDavid Zhang struct dmub_cmd_header header; 222383eb5385SDavid Zhang /** 222483eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 222583eb5385SDavid Zhang */ 222683eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 222783eb5385SDavid Zhang }; 222883eb5385SDavid Zhang 222983eb5385SDavid Zhang /** 223083eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 223183eb5385SDavid Zhang */ 2232b73353f7SMax Tseng union dmub_reg_cursor_control_cfg { 2233b73353f7SMax Tseng struct { 2234b73353f7SMax Tseng uint32_t cur_enable: 1; 2235b73353f7SMax Tseng uint32_t reser0: 3; 2236b73353f7SMax Tseng uint32_t cur_2x_magnify: 1; 2237b73353f7SMax Tseng uint32_t reser1: 3; 2238b73353f7SMax Tseng uint32_t mode: 3; 2239b73353f7SMax Tseng uint32_t reser2: 5; 2240b73353f7SMax Tseng uint32_t pitch: 2; 2241b73353f7SMax Tseng uint32_t reser3: 6; 2242b73353f7SMax Tseng uint32_t line_per_chunk: 5; 2243b73353f7SMax Tseng uint32_t reser4: 3; 2244b73353f7SMax Tseng } bits; 2245b73353f7SMax Tseng uint32_t raw; 2246b73353f7SMax Tseng }; 2247b73353f7SMax Tseng struct dmub_cursor_position_cache_hubp { 2248b73353f7SMax Tseng union dmub_reg_cursor_control_cfg cur_ctl; 2249b73353f7SMax Tseng union dmub_reg_position_cfg { 2250b73353f7SMax Tseng struct { 2251b73353f7SMax Tseng uint32_t cur_x_pos: 16; 2252b73353f7SMax Tseng uint32_t cur_y_pos: 16; 2253b73353f7SMax Tseng } bits; 2254b73353f7SMax Tseng uint32_t raw; 2255b73353f7SMax Tseng } position; 2256b73353f7SMax Tseng union dmub_reg_hot_spot_cfg { 2257b73353f7SMax Tseng struct { 2258b73353f7SMax Tseng uint32_t hot_x: 16; 2259b73353f7SMax Tseng uint32_t hot_y: 16; 2260b73353f7SMax Tseng } bits; 2261b73353f7SMax Tseng uint32_t raw; 2262b73353f7SMax Tseng } hot_spot; 2263b73353f7SMax Tseng union dmub_reg_dst_offset_cfg { 2264b73353f7SMax Tseng struct { 2265b73353f7SMax Tseng uint32_t dst_x_offset: 13; 2266b73353f7SMax Tseng uint32_t reserved: 19; 2267b73353f7SMax Tseng } bits; 2268b73353f7SMax Tseng uint32_t raw; 2269b73353f7SMax Tseng } dst_offset; 2270b73353f7SMax Tseng }; 2271b73353f7SMax Tseng 2272b73353f7SMax Tseng union dmub_reg_cur0_control_cfg { 2273b73353f7SMax Tseng struct { 2274b73353f7SMax Tseng uint32_t cur0_enable: 1; 2275b73353f7SMax Tseng uint32_t expansion_mode: 1; 2276b73353f7SMax Tseng uint32_t reser0: 1; 2277b73353f7SMax Tseng uint32_t cur0_rom_en: 1; 2278b73353f7SMax Tseng uint32_t mode: 3; 2279b73353f7SMax Tseng uint32_t reserved: 25; 2280b73353f7SMax Tseng } bits; 2281b73353f7SMax Tseng uint32_t raw; 2282b73353f7SMax Tseng }; 2283b73353f7SMax Tseng struct dmub_cursor_position_cache_dpp { 2284b73353f7SMax Tseng union dmub_reg_cur0_control_cfg cur0_ctl; 2285b73353f7SMax Tseng }; 2286b73353f7SMax Tseng struct dmub_cursor_position_cfg { 2287b73353f7SMax Tseng struct dmub_cursor_position_cache_hubp pHubp; 2288b73353f7SMax Tseng struct dmub_cursor_position_cache_dpp pDpp; 2289b73353f7SMax Tseng uint8_t pipe_idx; 2290b73353f7SMax Tseng /* 2291b73353f7SMax Tseng * Padding is required. To be 4 Bytes Aligned. 2292b73353f7SMax Tseng */ 2293b73353f7SMax Tseng uint8_t padding[3]; 2294b73353f7SMax Tseng }; 2295b73353f7SMax Tseng 2296b73353f7SMax Tseng struct dmub_cursor_attribute_cache_hubp { 2297b73353f7SMax Tseng uint32_t SURFACE_ADDR_HIGH; 2298b73353f7SMax Tseng uint32_t SURFACE_ADDR; 2299b73353f7SMax Tseng union dmub_reg_cursor_control_cfg cur_ctl; 2300b73353f7SMax Tseng union dmub_reg_cursor_size_cfg { 2301b73353f7SMax Tseng struct { 2302b73353f7SMax Tseng uint32_t width: 16; 2303b73353f7SMax Tseng uint32_t height: 16; 2304b73353f7SMax Tseng } bits; 2305b73353f7SMax Tseng uint32_t raw; 2306b73353f7SMax Tseng } size; 2307b73353f7SMax Tseng union dmub_reg_cursor_settings_cfg { 2308b73353f7SMax Tseng struct { 2309b73353f7SMax Tseng uint32_t dst_y_offset: 8; 2310b73353f7SMax Tseng uint32_t chunk_hdl_adjust: 2; 2311b73353f7SMax Tseng uint32_t reserved: 22; 2312b73353f7SMax Tseng } bits; 2313b73353f7SMax Tseng uint32_t raw; 2314b73353f7SMax Tseng } settings; 2315b73353f7SMax Tseng }; 2316b73353f7SMax Tseng struct dmub_cursor_attribute_cache_dpp { 2317b73353f7SMax Tseng union dmub_reg_cur0_control_cfg cur0_ctl; 2318b73353f7SMax Tseng }; 2319b73353f7SMax Tseng struct dmub_cursor_attributes_cfg { 2320b73353f7SMax Tseng struct dmub_cursor_attribute_cache_hubp aHubp; 2321b73353f7SMax Tseng struct dmub_cursor_attribute_cache_dpp aDpp; 2322b73353f7SMax Tseng }; 2323b73353f7SMax Tseng 2324b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 { 232583eb5385SDavid Zhang /** 232683eb5385SDavid Zhang * Cursor dirty rects. 232783eb5385SDavid Zhang */ 232883eb5385SDavid Zhang struct dmub_rect cursor_rect; 232983eb5385SDavid Zhang /** 233083eb5385SDavid Zhang * PSR SU debug flags. 233183eb5385SDavid Zhang */ 233283eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags; 233383eb5385SDavid Zhang /** 233483eb5385SDavid Zhang * Cursor enable/disable. 233583eb5385SDavid Zhang */ 233683eb5385SDavid Zhang uint8_t enable; 233783eb5385SDavid Zhang /** 233883eb5385SDavid Zhang * OTG HW instance. 233983eb5385SDavid Zhang */ 234083eb5385SDavid Zhang uint8_t pipe_idx; 234183eb5385SDavid Zhang /** 234283eb5385SDavid Zhang * PSR control version. 234383eb5385SDavid Zhang */ 234483eb5385SDavid Zhang uint8_t cmd_version; 234583eb5385SDavid Zhang /** 234683eb5385SDavid Zhang * Panel Instance. 2347*36e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 234883eb5385SDavid Zhang * Currently the support is only for 0 or 1 234983eb5385SDavid Zhang */ 235083eb5385SDavid Zhang uint8_t panel_inst; 2351b73353f7SMax Tseng /** 2352b73353f7SMax Tseng * Cursor Position Register. 2353b73353f7SMax Tseng * Registers contains Hubp & Dpp modules 2354b73353f7SMax Tseng */ 2355b73353f7SMax Tseng struct dmub_cursor_position_cfg position_cfg; 2356b73353f7SMax Tseng }; 2357b73353f7SMax Tseng 2358b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload1 { 2359b73353f7SMax Tseng struct dmub_cursor_attributes_cfg attribute_cfg; 2360b73353f7SMax Tseng }; 2361b73353f7SMax Tseng 2362b73353f7SMax Tseng union dmub_cmd_update_cursor_info_data { 2363b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 payload0; 2364b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload1 payload1; 236583eb5385SDavid Zhang }; 236683eb5385SDavid Zhang /** 236783eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 236883eb5385SDavid Zhang */ 236983eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info { 237083eb5385SDavid Zhang /** 237183eb5385SDavid Zhang * Command header. 237283eb5385SDavid Zhang */ 237383eb5385SDavid Zhang struct dmub_cmd_header header; 237483eb5385SDavid Zhang /** 237583eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 237683eb5385SDavid Zhang */ 2377b73353f7SMax Tseng union dmub_cmd_update_cursor_info_data update_cursor_info_data; 237883eb5385SDavid Zhang }; 237983eb5385SDavid Zhang 238083eb5385SDavid Zhang /** 238183eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 238283eb5385SDavid Zhang */ 238383eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data { 238483eb5385SDavid Zhang /** 238583eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 238683eb5385SDavid Zhang */ 238783eb5385SDavid Zhang uint16_t psr_vtotal_idle; 238883eb5385SDavid Zhang /** 238983eb5385SDavid Zhang * PSR control version. 239083eb5385SDavid Zhang */ 239183eb5385SDavid Zhang uint8_t cmd_version; 239283eb5385SDavid Zhang /** 239383eb5385SDavid Zhang * Panel Instance. 2394*36e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 239583eb5385SDavid Zhang * Currently the support is only for 0 or 1 239683eb5385SDavid Zhang */ 239783eb5385SDavid Zhang uint8_t panel_inst; 239883eb5385SDavid Zhang /* 239983eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 240083eb5385SDavid Zhang */ 240183eb5385SDavid Zhang uint16_t psr_vtotal_su; 240283eb5385SDavid Zhang /** 240383eb5385SDavid Zhang * Explicit padding to 4 byte boundary. 240483eb5385SDavid Zhang */ 240583eb5385SDavid Zhang uint8_t pad2[2]; 240683eb5385SDavid Zhang }; 240783eb5385SDavid Zhang 240883eb5385SDavid Zhang /** 240983eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 241083eb5385SDavid Zhang */ 241183eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal { 241283eb5385SDavid Zhang /** 241383eb5385SDavid Zhang * Command header. 241483eb5385SDavid Zhang */ 241583eb5385SDavid Zhang struct dmub_cmd_header header; 241683eb5385SDavid Zhang /** 241783eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 241883eb5385SDavid Zhang */ 241983eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 242083eb5385SDavid Zhang }; 242183eb5385SDavid Zhang 242283eb5385SDavid Zhang /** 2423e5dfcd27SRobin Chen * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2424e5dfcd27SRobin Chen */ 2425e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data { 2426e5dfcd27SRobin Chen /** 2427e5dfcd27SRobin Chen * PSR control version. 2428e5dfcd27SRobin Chen */ 2429e5dfcd27SRobin Chen uint8_t cmd_version; 2430e5dfcd27SRobin Chen /** 2431e5dfcd27SRobin Chen * Panel Instance. 2432*36e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2433e5dfcd27SRobin Chen * Currently the support is only for 0 or 1 2434e5dfcd27SRobin Chen */ 2435e5dfcd27SRobin Chen uint8_t panel_inst; 2436e5dfcd27SRobin Chen /** 2437e5dfcd27SRobin Chen * Explicit padding to 4 byte boundary. 2438e5dfcd27SRobin Chen */ 2439e5dfcd27SRobin Chen uint8_t pad[2]; 2440e5dfcd27SRobin Chen /** 2441e5dfcd27SRobin Chen * PSR power option 2442e5dfcd27SRobin Chen */ 2443e5dfcd27SRobin Chen uint32_t power_opt; 2444e5dfcd27SRobin Chen }; 2445e5dfcd27SRobin Chen 2446e5dfcd27SRobin Chen /** 2447e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2448e5dfcd27SRobin Chen */ 2449e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt { 2450e5dfcd27SRobin Chen /** 2451e5dfcd27SRobin Chen * Command header. 2452e5dfcd27SRobin Chen */ 2453e5dfcd27SRobin Chen struct dmub_cmd_header header; 2454e5dfcd27SRobin Chen /** 2455e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2456e5dfcd27SRobin Chen */ 2457e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2458e5dfcd27SRobin Chen }; 2459e5dfcd27SRobin Chen 2460e5dfcd27SRobin Chen /** 24611a595f28SAnthony Koo * Set of HW components that can be locked. 24620b51e7e8SAnthony Koo * 24630b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 24640b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 24651a595f28SAnthony Koo */ 2466788408b7SAnthony Koo union dmub_hw_lock_flags { 24671a595f28SAnthony Koo /** 24681a595f28SAnthony Koo * Set of HW components that can be locked. 24691a595f28SAnthony Koo */ 2470788408b7SAnthony Koo struct { 24711a595f28SAnthony Koo /** 24721a595f28SAnthony Koo * Lock/unlock OTG master update lock. 24731a595f28SAnthony Koo */ 2474788408b7SAnthony Koo uint8_t lock_pipe : 1; 24751a595f28SAnthony Koo /** 24761a595f28SAnthony Koo * Lock/unlock cursor. 24771a595f28SAnthony Koo */ 2478788408b7SAnthony Koo uint8_t lock_cursor : 1; 24791a595f28SAnthony Koo /** 24801a595f28SAnthony Koo * Lock/unlock global update lock. 24811a595f28SAnthony Koo */ 2482788408b7SAnthony Koo uint8_t lock_dig : 1; 24831a595f28SAnthony Koo /** 24841a595f28SAnthony Koo * Triple buffer lock requires additional hw programming to usual OTG master lock. 24851a595f28SAnthony Koo */ 2486788408b7SAnthony Koo uint8_t triple_buffer_lock : 1; 2487788408b7SAnthony Koo } bits; 2488788408b7SAnthony Koo 24891a595f28SAnthony Koo /** 24901a595f28SAnthony Koo * Union for HW Lock flags. 24911a595f28SAnthony Koo */ 2492788408b7SAnthony Koo uint8_t u8All; 2493788408b7SAnthony Koo }; 2494788408b7SAnthony Koo 24951a595f28SAnthony Koo /** 24961a595f28SAnthony Koo * Instances of HW to be locked. 24970b51e7e8SAnthony Koo * 24980b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 24990b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 25001a595f28SAnthony Koo */ 2501788408b7SAnthony Koo struct dmub_hw_lock_inst_flags { 25021a595f28SAnthony Koo /** 25031a595f28SAnthony Koo * OTG HW instance for OTG master update lock. 25041a595f28SAnthony Koo */ 2505788408b7SAnthony Koo uint8_t otg_inst; 25061a595f28SAnthony Koo /** 25071a595f28SAnthony Koo * OPP instance for cursor lock. 25081a595f28SAnthony Koo */ 2509788408b7SAnthony Koo uint8_t opp_inst; 25101a595f28SAnthony Koo /** 25111a595f28SAnthony Koo * OTG HW instance for global update lock. 25121a595f28SAnthony Koo * TODO: Remove, and re-use otg_inst. 25131a595f28SAnthony Koo */ 2514788408b7SAnthony Koo uint8_t dig_inst; 25151a595f28SAnthony Koo /** 25161a595f28SAnthony Koo * Explicit pad to 4 byte boundary. 25171a595f28SAnthony Koo */ 2518788408b7SAnthony Koo uint8_t pad; 2519788408b7SAnthony Koo }; 2520788408b7SAnthony Koo 25211a595f28SAnthony Koo /** 25221a595f28SAnthony Koo * Clients that can acquire the HW Lock Manager. 25230b51e7e8SAnthony Koo * 25240b51e7e8SAnthony Koo * Note: If updating with more clients, fields in 25250b51e7e8SAnthony Koo * dmub_inbox0_cmd_lock_hw must be updated to match. 25261a595f28SAnthony Koo */ 2527788408b7SAnthony Koo enum hw_lock_client { 25281a595f28SAnthony Koo /** 25291a595f28SAnthony Koo * Driver is the client of HW Lock Manager. 25301a595f28SAnthony Koo */ 2531788408b7SAnthony Koo HW_LOCK_CLIENT_DRIVER = 0, 25321a595f28SAnthony Koo /** 253383eb5385SDavid Zhang * PSR SU is the client of HW Lock Manager. 253483eb5385SDavid Zhang */ 253583eb5385SDavid Zhang HW_LOCK_CLIENT_PSR_SU = 1, 253683eb5385SDavid Zhang /** 25371a595f28SAnthony Koo * Invalid client. 25381a595f28SAnthony Koo */ 2539788408b7SAnthony Koo HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2540788408b7SAnthony Koo }; 2541788408b7SAnthony Koo 25421a595f28SAnthony Koo /** 25431a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 25441a595f28SAnthony Koo */ 2545788408b7SAnthony Koo struct dmub_cmd_lock_hw_data { 25461a595f28SAnthony Koo /** 25471a595f28SAnthony Koo * Specifies the client accessing HW Lock Manager. 25481a595f28SAnthony Koo */ 2549788408b7SAnthony Koo enum hw_lock_client client; 25501a595f28SAnthony Koo /** 25511a595f28SAnthony Koo * HW instances to be locked. 25521a595f28SAnthony Koo */ 2553788408b7SAnthony Koo struct dmub_hw_lock_inst_flags inst_flags; 25541a595f28SAnthony Koo /** 25551a595f28SAnthony Koo * Which components to be locked. 25561a595f28SAnthony Koo */ 2557788408b7SAnthony Koo union dmub_hw_lock_flags hw_locks; 25581a595f28SAnthony Koo /** 25591a595f28SAnthony Koo * Specifies lock/unlock. 25601a595f28SAnthony Koo */ 2561788408b7SAnthony Koo uint8_t lock; 25621a595f28SAnthony Koo /** 25631a595f28SAnthony Koo * HW can be unlocked separately from releasing the HW Lock Mgr. 25641a595f28SAnthony Koo * This flag is set if the client wishes to release the object. 25651a595f28SAnthony Koo */ 2566788408b7SAnthony Koo uint8_t should_release; 25671a595f28SAnthony Koo /** 25681a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 25691a595f28SAnthony Koo */ 2570788408b7SAnthony Koo uint8_t pad; 2571788408b7SAnthony Koo }; 2572788408b7SAnthony Koo 25731a595f28SAnthony Koo /** 25741a595f28SAnthony Koo * Definition of a DMUB_CMD__HW_LOCK command. 25751a595f28SAnthony Koo * Command is used by driver and FW. 25761a595f28SAnthony Koo */ 2577788408b7SAnthony Koo struct dmub_rb_cmd_lock_hw { 25781a595f28SAnthony Koo /** 25791a595f28SAnthony Koo * Command header. 25801a595f28SAnthony Koo */ 2581788408b7SAnthony Koo struct dmub_cmd_header header; 25821a595f28SAnthony Koo /** 25831a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 25841a595f28SAnthony Koo */ 2585788408b7SAnthony Koo struct dmub_cmd_lock_hw_data lock_hw_data; 2586788408b7SAnthony Koo }; 2587788408b7SAnthony Koo 25881a595f28SAnthony Koo /** 25891a595f28SAnthony Koo * ABM command sub-types. 25901a595f28SAnthony Koo */ 259184034ad4SAnthony Koo enum dmub_cmd_abm_type { 25921a595f28SAnthony Koo /** 25931a595f28SAnthony Koo * Initialize parameters for ABM algorithm. 25941a595f28SAnthony Koo * Data is passed through an indirect buffer. 25951a595f28SAnthony Koo */ 259684034ad4SAnthony Koo DMUB_CMD__ABM_INIT_CONFIG = 0, 25971a595f28SAnthony Koo /** 25981a595f28SAnthony Koo * Set OTG and panel HW instance. 25991a595f28SAnthony Koo */ 260084034ad4SAnthony Koo DMUB_CMD__ABM_SET_PIPE = 1, 26011a595f28SAnthony Koo /** 26021a595f28SAnthony Koo * Set user requested backklight level. 26031a595f28SAnthony Koo */ 260484034ad4SAnthony Koo DMUB_CMD__ABM_SET_BACKLIGHT = 2, 26051a595f28SAnthony Koo /** 26061a595f28SAnthony Koo * Set ABM operating/aggression level. 26071a595f28SAnthony Koo */ 260884034ad4SAnthony Koo DMUB_CMD__ABM_SET_LEVEL = 3, 26091a595f28SAnthony Koo /** 26101a595f28SAnthony Koo * Set ambient light level. 26111a595f28SAnthony Koo */ 261284034ad4SAnthony Koo DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 26131a595f28SAnthony Koo /** 26141a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 26151a595f28SAnthony Koo */ 261684034ad4SAnthony Koo DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2617b629a824SEric Yang 2618b629a824SEric Yang /** 2619b629a824SEric Yang * unregister vertical interrupt after steady state is reached 2620b629a824SEric Yang */ 2621b629a824SEric Yang DMUB_CMD__ABM_PAUSE = 6, 262284034ad4SAnthony Koo }; 262384034ad4SAnthony Koo 26241a595f28SAnthony Koo /** 26251a595f28SAnthony Koo * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 26261a595f28SAnthony Koo * Requirements: 26271a595f28SAnthony Koo * - Padded explicitly to 32-bit boundary. 26281a595f28SAnthony Koo * - Must ensure this structure matches the one on driver-side, 26291a595f28SAnthony Koo * otherwise it won't be aligned. 263084034ad4SAnthony Koo */ 263184034ad4SAnthony Koo struct abm_config_table { 26321a595f28SAnthony Koo /** 26331a595f28SAnthony Koo * Gamma curve thresholds, used for crgb conversion. 26341a595f28SAnthony Koo */ 263584034ad4SAnthony Koo uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 26361a595f28SAnthony Koo /** 26371a595f28SAnthony Koo * Gamma curve offsets, used for crgb conversion. 26381a595f28SAnthony Koo */ 2639b6402afeSAnthony Koo uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 26401a595f28SAnthony Koo /** 26411a595f28SAnthony Koo * Gamma curve slopes, used for crgb conversion. 26421a595f28SAnthony Koo */ 2643b6402afeSAnthony Koo uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 26441a595f28SAnthony Koo /** 26451a595f28SAnthony Koo * Custom backlight curve thresholds. 26461a595f28SAnthony Koo */ 2647b6402afeSAnthony Koo uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 26481a595f28SAnthony Koo /** 26491a595f28SAnthony Koo * Custom backlight curve offsets. 26501a595f28SAnthony Koo */ 2651b6402afeSAnthony Koo uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 26521a595f28SAnthony Koo /** 26531a595f28SAnthony Koo * Ambient light thresholds. 26541a595f28SAnthony Koo */ 2655b6402afeSAnthony Koo uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 26561a595f28SAnthony Koo /** 26571a595f28SAnthony Koo * Minimum programmable backlight. 26581a595f28SAnthony Koo */ 2659b6402afeSAnthony Koo uint16_t min_abm_backlight; // 122B 26601a595f28SAnthony Koo /** 26611a595f28SAnthony Koo * Minimum reduction values. 26621a595f28SAnthony Koo */ 2663b6402afeSAnthony Koo uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 26641a595f28SAnthony Koo /** 26651a595f28SAnthony Koo * Maximum reduction values. 26661a595f28SAnthony Koo */ 2667b6402afeSAnthony Koo uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 26681a595f28SAnthony Koo /** 26691a595f28SAnthony Koo * Bright positive gain. 26701a595f28SAnthony Koo */ 2671b6402afeSAnthony Koo uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 26721a595f28SAnthony Koo /** 26731a595f28SAnthony Koo * Dark negative gain. 26741a595f28SAnthony Koo */ 2675b6402afeSAnthony Koo uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 26761a595f28SAnthony Koo /** 26771a595f28SAnthony Koo * Hybrid factor. 26781a595f28SAnthony Koo */ 2679b6402afeSAnthony Koo uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 26801a595f28SAnthony Koo /** 26811a595f28SAnthony Koo * Contrast factor. 26821a595f28SAnthony Koo */ 2683b6402afeSAnthony Koo uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 26841a595f28SAnthony Koo /** 26851a595f28SAnthony Koo * Deviation gain. 26861a595f28SAnthony Koo */ 2687b6402afeSAnthony Koo uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 26881a595f28SAnthony Koo /** 26891a595f28SAnthony Koo * Minimum knee. 26901a595f28SAnthony Koo */ 2691b6402afeSAnthony Koo uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 26921a595f28SAnthony Koo /** 26931a595f28SAnthony Koo * Maximum knee. 26941a595f28SAnthony Koo */ 2695b6402afeSAnthony Koo uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 26961a595f28SAnthony Koo /** 26971a595f28SAnthony Koo * Unused. 26981a595f28SAnthony Koo */ 2699b6402afeSAnthony Koo uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 27001a595f28SAnthony Koo /** 27011a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 27021a595f28SAnthony Koo */ 2703b6402afeSAnthony Koo uint8_t pad3[3]; // 229B 27041a595f28SAnthony Koo /** 27051a595f28SAnthony Koo * Backlight ramp reduction. 27061a595f28SAnthony Koo */ 2707b6402afeSAnthony Koo uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 27081a595f28SAnthony Koo /** 27091a595f28SAnthony Koo * Backlight ramp start. 27101a595f28SAnthony Koo */ 2711b6402afeSAnthony Koo uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 271284034ad4SAnthony Koo }; 271384034ad4SAnthony Koo 27141a595f28SAnthony Koo /** 27151a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 27161a595f28SAnthony Koo */ 2717e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data { 27181a595f28SAnthony Koo /** 27191a595f28SAnthony Koo * OTG HW instance. 27201a595f28SAnthony Koo */ 27217b8a6362SAnthony Koo uint8_t otg_inst; 27221a595f28SAnthony Koo 27231a595f28SAnthony Koo /** 27241a595f28SAnthony Koo * Panel Control HW instance. 27251a595f28SAnthony Koo */ 27267b8a6362SAnthony Koo uint8_t panel_inst; 27271a595f28SAnthony Koo 27281a595f28SAnthony Koo /** 27291a595f28SAnthony Koo * Controls how ABM will interpret a set pipe or set level command. 27301a595f28SAnthony Koo */ 27317b8a6362SAnthony Koo uint8_t set_pipe_option; 27321a595f28SAnthony Koo 27331a595f28SAnthony Koo /** 27341a595f28SAnthony Koo * Unused. 27351a595f28SAnthony Koo * TODO: Remove. 27361a595f28SAnthony Koo */ 27371a595f28SAnthony Koo uint8_t ramping_boundary; 2738e6ea8c34SWyatt Wood }; 2739e6ea8c34SWyatt Wood 27401a595f28SAnthony Koo /** 27411a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 27421a595f28SAnthony Koo */ 2743e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe { 27441a595f28SAnthony Koo /** 27451a595f28SAnthony Koo * Command header. 27461a595f28SAnthony Koo */ 2747e6ea8c34SWyatt Wood struct dmub_cmd_header header; 27481a595f28SAnthony Koo 27491a595f28SAnthony Koo /** 27501a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 27511a595f28SAnthony Koo */ 2752e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2753e6ea8c34SWyatt Wood }; 2754e6ea8c34SWyatt Wood 27551a595f28SAnthony Koo /** 27561a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 27571a595f28SAnthony Koo */ 2758e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data { 27591a595f28SAnthony Koo /** 27601a595f28SAnthony Koo * Number of frames to ramp to backlight user level. 27611a595f28SAnthony Koo */ 2762e6ea8c34SWyatt Wood uint32_t frame_ramp; 27631a595f28SAnthony Koo 27641a595f28SAnthony Koo /** 27651a595f28SAnthony Koo * Requested backlight level from user. 27661a595f28SAnthony Koo */ 2767474ac4a8SYongqiang Sun uint32_t backlight_user_level; 2768e922057bSJake Wang 2769e922057bSJake Wang /** 277063de4f04SJake Wang * ABM control version. 2771e922057bSJake Wang */ 2772e922057bSJake Wang uint8_t version; 2773e922057bSJake Wang 2774e922057bSJake Wang /** 2775e922057bSJake Wang * Panel Control HW instance mask. 2776e922057bSJake Wang * Bit 0 is Panel Control HW instance 0. 2777e922057bSJake Wang * Bit 1 is Panel Control HW instance 1. 2778e922057bSJake Wang */ 2779e922057bSJake Wang uint8_t panel_mask; 2780e922057bSJake Wang 2781e922057bSJake Wang /** 2782e922057bSJake Wang * Explicit padding to 4 byte boundary. 2783e922057bSJake Wang */ 2784e922057bSJake Wang uint8_t pad[2]; 2785e6ea8c34SWyatt Wood }; 2786e6ea8c34SWyatt Wood 27871a595f28SAnthony Koo /** 27881a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 27891a595f28SAnthony Koo */ 2790e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight { 27911a595f28SAnthony Koo /** 27921a595f28SAnthony Koo * Command header. 27931a595f28SAnthony Koo */ 2794e6ea8c34SWyatt Wood struct dmub_cmd_header header; 27951a595f28SAnthony Koo 27961a595f28SAnthony Koo /** 27971a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 27981a595f28SAnthony Koo */ 2799e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2800e6ea8c34SWyatt Wood }; 2801e6ea8c34SWyatt Wood 28021a595f28SAnthony Koo /** 28031a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 28041a595f28SAnthony Koo */ 2805e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data { 28061a595f28SAnthony Koo /** 28071a595f28SAnthony Koo * Set current ABM operating/aggression level. 28081a595f28SAnthony Koo */ 2809e6ea8c34SWyatt Wood uint32_t level; 281063de4f04SJake Wang 281163de4f04SJake Wang /** 281263de4f04SJake Wang * ABM control version. 281363de4f04SJake Wang */ 281463de4f04SJake Wang uint8_t version; 281563de4f04SJake Wang 281663de4f04SJake Wang /** 281763de4f04SJake Wang * Panel Control HW instance mask. 281863de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 281963de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 282063de4f04SJake Wang */ 282163de4f04SJake Wang uint8_t panel_mask; 282263de4f04SJake Wang 282363de4f04SJake Wang /** 282463de4f04SJake Wang * Explicit padding to 4 byte boundary. 282563de4f04SJake Wang */ 282663de4f04SJake Wang uint8_t pad[2]; 2827e6ea8c34SWyatt Wood }; 2828e6ea8c34SWyatt Wood 28291a595f28SAnthony Koo /** 28301a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 28311a595f28SAnthony Koo */ 2832e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level { 28331a595f28SAnthony Koo /** 28341a595f28SAnthony Koo * Command header. 28351a595f28SAnthony Koo */ 2836e6ea8c34SWyatt Wood struct dmub_cmd_header header; 28371a595f28SAnthony Koo 28381a595f28SAnthony Koo /** 28391a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 28401a595f28SAnthony Koo */ 2841e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data abm_set_level_data; 2842e6ea8c34SWyatt Wood }; 2843e6ea8c34SWyatt Wood 28441a595f28SAnthony Koo /** 28451a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 28461a595f28SAnthony Koo */ 2847e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data { 28481a595f28SAnthony Koo /** 28491a595f28SAnthony Koo * Ambient light sensor reading from OS. 28501a595f28SAnthony Koo */ 2851e6ea8c34SWyatt Wood uint32_t ambient_lux; 285263de4f04SJake Wang 285363de4f04SJake Wang /** 285463de4f04SJake Wang * ABM control version. 285563de4f04SJake Wang */ 285663de4f04SJake Wang uint8_t version; 285763de4f04SJake Wang 285863de4f04SJake Wang /** 285963de4f04SJake Wang * Panel Control HW instance mask. 286063de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 286163de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 286263de4f04SJake Wang */ 286363de4f04SJake Wang uint8_t panel_mask; 286463de4f04SJake Wang 286563de4f04SJake Wang /** 286663de4f04SJake Wang * Explicit padding to 4 byte boundary. 286763de4f04SJake Wang */ 286863de4f04SJake Wang uint8_t pad[2]; 2869e6ea8c34SWyatt Wood }; 2870e6ea8c34SWyatt Wood 28711a595f28SAnthony Koo /** 28721a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 28731a595f28SAnthony Koo */ 2874e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level { 28751a595f28SAnthony Koo /** 28761a595f28SAnthony Koo * Command header. 28771a595f28SAnthony Koo */ 2878e6ea8c34SWyatt Wood struct dmub_cmd_header header; 28791a595f28SAnthony Koo 28801a595f28SAnthony Koo /** 28811a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 28821a595f28SAnthony Koo */ 2883e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2884e6ea8c34SWyatt Wood }; 2885e6ea8c34SWyatt Wood 28861a595f28SAnthony Koo /** 28871a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 28881a595f28SAnthony Koo */ 2889e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data { 28901a595f28SAnthony Koo /** 28911a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 28921a595f28SAnthony Koo * TODO: Convert to uint8_t. 28931a595f28SAnthony Koo */ 2894e6ea8c34SWyatt Wood uint32_t fractional_pwm; 289563de4f04SJake Wang 289663de4f04SJake Wang /** 289763de4f04SJake Wang * ABM control version. 289863de4f04SJake Wang */ 289963de4f04SJake Wang uint8_t version; 290063de4f04SJake Wang 290163de4f04SJake Wang /** 290263de4f04SJake Wang * Panel Control HW instance mask. 290363de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 290463de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 290563de4f04SJake Wang */ 290663de4f04SJake Wang uint8_t panel_mask; 290763de4f04SJake Wang 290863de4f04SJake Wang /** 290963de4f04SJake Wang * Explicit padding to 4 byte boundary. 291063de4f04SJake Wang */ 291163de4f04SJake Wang uint8_t pad[2]; 2912e6ea8c34SWyatt Wood }; 2913e6ea8c34SWyatt Wood 29141a595f28SAnthony Koo /** 29151a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 29161a595f28SAnthony Koo */ 2917e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac { 29181a595f28SAnthony Koo /** 29191a595f28SAnthony Koo * Command header. 29201a595f28SAnthony Koo */ 2921e6ea8c34SWyatt Wood struct dmub_cmd_header header; 29221a595f28SAnthony Koo 29231a595f28SAnthony Koo /** 29241a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 29251a595f28SAnthony Koo */ 2926e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2927e6ea8c34SWyatt Wood }; 2928e6ea8c34SWyatt Wood 29291a595f28SAnthony Koo /** 29301a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 29311a595f28SAnthony Koo */ 293216012806SWyatt Wood struct dmub_cmd_abm_init_config_data { 29331a595f28SAnthony Koo /** 29341a595f28SAnthony Koo * Location of indirect buffer used to pass init data to ABM. 29351a595f28SAnthony Koo */ 293616012806SWyatt Wood union dmub_addr src; 29371a595f28SAnthony Koo 29381a595f28SAnthony Koo /** 29391a595f28SAnthony Koo * Indirect buffer length. 29401a595f28SAnthony Koo */ 294116012806SWyatt Wood uint16_t bytes; 294263de4f04SJake Wang 294363de4f04SJake Wang 294463de4f04SJake Wang /** 294563de4f04SJake Wang * ABM control version. 294663de4f04SJake Wang */ 294763de4f04SJake Wang uint8_t version; 294863de4f04SJake Wang 294963de4f04SJake Wang /** 295063de4f04SJake Wang * Panel Control HW instance mask. 295163de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 295263de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 295363de4f04SJake Wang */ 295463de4f04SJake Wang uint8_t panel_mask; 295563de4f04SJake Wang 295663de4f04SJake Wang /** 295763de4f04SJake Wang * Explicit padding to 4 byte boundary. 295863de4f04SJake Wang */ 295963de4f04SJake Wang uint8_t pad[2]; 296016012806SWyatt Wood }; 296116012806SWyatt Wood 29621a595f28SAnthony Koo /** 29631a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 29641a595f28SAnthony Koo */ 296516012806SWyatt Wood struct dmub_rb_cmd_abm_init_config { 29661a595f28SAnthony Koo /** 29671a595f28SAnthony Koo * Command header. 29681a595f28SAnthony Koo */ 296916012806SWyatt Wood struct dmub_cmd_header header; 29701a595f28SAnthony Koo 29711a595f28SAnthony Koo /** 29721a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 29731a595f28SAnthony Koo */ 297416012806SWyatt Wood struct dmub_cmd_abm_init_config_data abm_init_config_data; 297516012806SWyatt Wood }; 297616012806SWyatt Wood 29771a595f28SAnthony Koo /** 2978b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2979b629a824SEric Yang */ 2980b629a824SEric Yang 2981b629a824SEric Yang struct dmub_cmd_abm_pause_data { 2982b629a824SEric Yang 2983b629a824SEric Yang /** 2984b629a824SEric Yang * Panel Control HW instance mask. 2985b629a824SEric Yang * Bit 0 is Panel Control HW instance 0. 2986b629a824SEric Yang * Bit 1 is Panel Control HW instance 1. 2987b629a824SEric Yang */ 2988b629a824SEric Yang uint8_t panel_mask; 2989b629a824SEric Yang 2990b629a824SEric Yang /** 2991b629a824SEric Yang * OTG hw instance 2992b629a824SEric Yang */ 2993b629a824SEric Yang uint8_t otg_inst; 2994b629a824SEric Yang 2995b629a824SEric Yang /** 2996b629a824SEric Yang * Enable or disable ABM pause 2997b629a824SEric Yang */ 2998b629a824SEric Yang uint8_t enable; 2999b629a824SEric Yang 3000b629a824SEric Yang /** 3001b629a824SEric Yang * Explicit padding to 4 byte boundary. 3002b629a824SEric Yang */ 3003b629a824SEric Yang uint8_t pad[1]; 3004b629a824SEric Yang }; 3005b629a824SEric Yang 3006b629a824SEric Yang /** 3007b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 3008b629a824SEric Yang */ 3009b629a824SEric Yang struct dmub_rb_cmd_abm_pause { 3010b629a824SEric Yang /** 3011b629a824SEric Yang * Command header. 3012b629a824SEric Yang */ 3013b629a824SEric Yang struct dmub_cmd_header header; 3014b629a824SEric Yang 3015b629a824SEric Yang /** 3016b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3017b629a824SEric Yang */ 3018b629a824SEric Yang struct dmub_cmd_abm_pause_data abm_pause_data; 3019b629a824SEric Yang }; 3020b629a824SEric Yang 3021b629a824SEric Yang /** 30221a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 30231a595f28SAnthony Koo */ 302434ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data { 30251a595f28SAnthony Koo /** 30261a595f28SAnthony Koo * DMUB feature capabilities. 30271a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features. 30281a595f28SAnthony Koo */ 302934ba432cSAnthony Koo struct dmub_feature_caps feature_caps; 303034ba432cSAnthony Koo }; 303134ba432cSAnthony Koo 30321a595f28SAnthony Koo /** 30331a595f28SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 30341a595f28SAnthony Koo */ 303534ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps { 30361a595f28SAnthony Koo /** 30371a595f28SAnthony Koo * Command header. 30381a595f28SAnthony Koo */ 303934ba432cSAnthony Koo struct dmub_cmd_header header; 30401a595f28SAnthony Koo /** 30411a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 30421a595f28SAnthony Koo */ 304334ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 304434ba432cSAnthony Koo }; 304534ba432cSAnthony Koo 3046b09c1fffSLeo (Hanghong) Ma /** 3047b09c1fffSLeo (Hanghong) Ma * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3048b09c1fffSLeo (Hanghong) Ma */ 3049b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_visual_confirm_color_data { 3050b09c1fffSLeo (Hanghong) Ma /** 3051b09c1fffSLeo (Hanghong) Ma * DMUB feature capabilities. 3052b09c1fffSLeo (Hanghong) Ma * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3053b09c1fffSLeo (Hanghong) Ma */ 3054b09c1fffSLeo (Hanghong) Ma struct dmub_visual_confirm_color visual_confirm_color; 3055b09c1fffSLeo (Hanghong) Ma }; 3056b09c1fffSLeo (Hanghong) Ma 3057b09c1fffSLeo (Hanghong) Ma /** 3058b09c1fffSLeo (Hanghong) Ma * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3059b09c1fffSLeo (Hanghong) Ma */ 3060b09c1fffSLeo (Hanghong) Ma struct dmub_rb_cmd_get_visual_confirm_color { 3061b09c1fffSLeo (Hanghong) Ma /** 3062b09c1fffSLeo (Hanghong) Ma * Command header. 3063b09c1fffSLeo (Hanghong) Ma */ 3064b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_header header; 3065b09c1fffSLeo (Hanghong) Ma /** 3066b09c1fffSLeo (Hanghong) Ma * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3067b09c1fffSLeo (Hanghong) Ma */ 3068b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3069b09c1fffSLeo (Hanghong) Ma }; 3070b09c1fffSLeo (Hanghong) Ma 3071592a6318SAnthony Koo struct dmub_optc_state { 3072592a6318SAnthony Koo uint32_t v_total_max; 3073592a6318SAnthony Koo uint32_t v_total_min; 3074592a6318SAnthony Koo uint32_t tg_inst; 3075592a6318SAnthony Koo }; 3076592a6318SAnthony Koo 3077592a6318SAnthony Koo struct dmub_rb_cmd_drr_update { 3078592a6318SAnthony Koo struct dmub_cmd_header header; 3079592a6318SAnthony Koo struct dmub_optc_state dmub_optc_state_req; 3080592a6318SAnthony Koo }; 3081592a6318SAnthony Koo 308200fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 308300fa7f03SRodrigo Siqueira uint32_t pix_clk_100hz; 308400fa7f03SRodrigo Siqueira uint8_t max_ramp_step; 308500fa7f03SRodrigo Siqueira uint8_t pipes; 308600fa7f03SRodrigo Siqueira uint8_t min_refresh_in_hz; 308700fa7f03SRodrigo Siqueira uint8_t padding[1]; 308800fa7f03SRodrigo Siqueira }; 308900fa7f03SRodrigo Siqueira 309000fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config { 309100fa7f03SRodrigo Siqueira uint8_t fams_enabled; 309200fa7f03SRodrigo Siqueira uint8_t visual_confirm_enabled; 309300fa7f03SRodrigo Siqueira uint8_t padding[2]; 309400fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 309500fa7f03SRodrigo Siqueira }; 309600fa7f03SRodrigo Siqueira 309700fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch { 309800fa7f03SRodrigo Siqueira struct dmub_cmd_header header; 309900fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 310000fa7f03SRodrigo Siqueira }; 310100fa7f03SRodrigo Siqueira 3102b04cb192SNicholas Kazlauskas /** 3103b04cb192SNicholas Kazlauskas * enum dmub_cmd_panel_cntl_type - Panel control command. 3104b04cb192SNicholas Kazlauskas */ 3105b04cb192SNicholas Kazlauskas enum dmub_cmd_panel_cntl_type { 3106b04cb192SNicholas Kazlauskas /** 3107b04cb192SNicholas Kazlauskas * Initializes embedded panel hardware blocks. 3108b04cb192SNicholas Kazlauskas */ 3109b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3110b04cb192SNicholas Kazlauskas /** 3111b04cb192SNicholas Kazlauskas * Queries backlight info for the embedded panel. 3112b04cb192SNicholas Kazlauskas */ 3113b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3114b04cb192SNicholas Kazlauskas }; 3115b04cb192SNicholas Kazlauskas 3116b04cb192SNicholas Kazlauskas /** 3117b04cb192SNicholas Kazlauskas * struct dmub_cmd_panel_cntl_data - Panel control data. 3118b04cb192SNicholas Kazlauskas */ 3119b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data { 3120b04cb192SNicholas Kazlauskas uint32_t inst; /**< panel instance */ 3121b04cb192SNicholas Kazlauskas uint32_t current_backlight; /* in/out */ 3122b04cb192SNicholas Kazlauskas uint32_t bl_pwm_cntl; /* in/out */ 3123b04cb192SNicholas Kazlauskas uint32_t bl_pwm_period_cntl; /* in/out */ 3124b04cb192SNicholas Kazlauskas uint32_t bl_pwm_ref_div1; /* in/out */ 3125b04cb192SNicholas Kazlauskas uint8_t is_backlight_on : 1; /* in/out */ 3126b04cb192SNicholas Kazlauskas uint8_t is_powered_on : 1; /* in/out */ 3127a91b402dSCharlene Liu uint8_t padding[3]; 3128a91b402dSCharlene Liu uint32_t bl_pwm_ref_div2; /* in/out */ 3129a91b402dSCharlene Liu uint8_t reserved[4]; 3130b04cb192SNicholas Kazlauskas }; 3131b04cb192SNicholas Kazlauskas 3132b04cb192SNicholas Kazlauskas /** 3133b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_panel_cntl - Panel control command. 3134b04cb192SNicholas Kazlauskas */ 3135b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl { 3136b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 3137b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data data; /**< payload */ 3138b04cb192SNicholas Kazlauskas }; 3139b04cb192SNicholas Kazlauskas 31401a595f28SAnthony Koo /** 31411a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 31421a595f28SAnthony Koo */ 31431a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data { 31441a595f28SAnthony Koo uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3145e0886e1fSTony Tascioglu uint8_t bypass_panel_control_wait; 31460888aa30SAnthony Koo uint8_t reserved_0[2]; /**< For future use */ 31471a595f28SAnthony Koo uint8_t panel_inst; /**< LVTMA control instance */ 31481a595f28SAnthony Koo uint8_t reserved_1[3]; /**< For future use */ 31491a595f28SAnthony Koo }; 31501a595f28SAnthony Koo 31511a595f28SAnthony Koo /** 31521a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 31531a595f28SAnthony Koo */ 31541a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control { 31551a595f28SAnthony Koo /** 31561a595f28SAnthony Koo * Command header. 31571a595f28SAnthony Koo */ 31581a595f28SAnthony Koo struct dmub_cmd_header header; 31591a595f28SAnthony Koo /** 31601a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 31611a595f28SAnthony Koo */ 31621a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data data; 31631a595f28SAnthony Koo }; 31641a595f28SAnthony Koo 3165592a6318SAnthony Koo /** 316641f91315SNicholas Kazlauskas * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 316741f91315SNicholas Kazlauskas */ 316841f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data { 316941f91315SNicholas Kazlauskas uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 317041f91315SNicholas Kazlauskas uint8_t is_usb; /**< is phy is usb */ 317141f91315SNicholas Kazlauskas uint8_t is_dp_alt_disable; /**< is dp alt disable */ 317241f91315SNicholas Kazlauskas uint8_t is_dp4; /**< is dp in 4 lane */ 317341f91315SNicholas Kazlauskas }; 317441f91315SNicholas Kazlauskas 317541f91315SNicholas Kazlauskas /** 317641f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 317741f91315SNicholas Kazlauskas */ 317841f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt { 317941f91315SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 318041f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 318141f91315SNicholas Kazlauskas }; 318241f91315SNicholas Kazlauskas 318341f91315SNicholas Kazlauskas /** 3184021eaef8SAnthony Koo * Maximum number of bytes a chunk sent to DMUB for parsing 3185021eaef8SAnthony Koo */ 3186021eaef8SAnthony Koo #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3187021eaef8SAnthony Koo 3188021eaef8SAnthony Koo /** 3189021eaef8SAnthony Koo * Represent a chunk of CEA blocks sent to DMUB for parsing 3190021eaef8SAnthony Koo */ 3191021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea { 3192021eaef8SAnthony Koo uint16_t offset; /**< offset into the CEA block */ 3193021eaef8SAnthony Koo uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3194eb9e59ebSOliver Logush uint16_t cea_total_length; /**< total length of the CEA block */ 3195021eaef8SAnthony Koo uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3196021eaef8SAnthony Koo uint8_t pad[3]; /**< padding and for future expansion */ 3197021eaef8SAnthony Koo }; 3198021eaef8SAnthony Koo 3199021eaef8SAnthony Koo /** 3200021eaef8SAnthony Koo * Result of VSDB parsing from CEA block 3201021eaef8SAnthony Koo */ 3202021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb { 3203021eaef8SAnthony Koo uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3204021eaef8SAnthony Koo uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3205021eaef8SAnthony Koo uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3206021eaef8SAnthony Koo uint16_t min_frame_rate; /**< Maximum frame rate */ 3207021eaef8SAnthony Koo uint16_t max_frame_rate; /**< Minimum frame rate */ 3208021eaef8SAnthony Koo }; 3209021eaef8SAnthony Koo 3210021eaef8SAnthony Koo /** 3211021eaef8SAnthony Koo * Result of sending a CEA chunk 3212021eaef8SAnthony Koo */ 3213021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack { 3214021eaef8SAnthony Koo uint16_t offset; /**< offset of the chunk into the CEA block */ 3215021eaef8SAnthony Koo uint8_t success; /**< 1 if this sending of chunk succeeded */ 3216021eaef8SAnthony Koo uint8_t pad; /**< padding and for future expansion */ 3217021eaef8SAnthony Koo }; 3218021eaef8SAnthony Koo 3219021eaef8SAnthony Koo /** 3220021eaef8SAnthony Koo * Specify whether the result is an ACK/NACK or the parsing has finished 3221021eaef8SAnthony Koo */ 3222021eaef8SAnthony Koo enum dmub_cmd_edid_cea_reply_type { 3223021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3224021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3225021eaef8SAnthony Koo }; 3226021eaef8SAnthony Koo 3227021eaef8SAnthony Koo /** 3228021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 3229021eaef8SAnthony Koo */ 3230021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea { 3231021eaef8SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 3232021eaef8SAnthony Koo union dmub_cmd_edid_cea_data { 3233021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3234021eaef8SAnthony Koo struct dmub_cmd_edid_cea_output { /**< output with results */ 3235021eaef8SAnthony Koo uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3236021eaef8SAnthony Koo union { 3237021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3238021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack ack; 3239021eaef8SAnthony Koo }; 3240021eaef8SAnthony Koo } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3241021eaef8SAnthony Koo } data; /**< Command data */ 3242021eaef8SAnthony Koo 3243021eaef8SAnthony Koo }; 3244021eaef8SAnthony Koo 3245021eaef8SAnthony Koo /** 3246c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3247c595fb05SWenjing Liu */ 3248c595fb05SWenjing Liu struct dmub_cmd_cable_id_input { 3249c595fb05SWenjing Liu uint8_t phy_inst; /**< phy inst for cable id data */ 3250c595fb05SWenjing Liu }; 3251c595fb05SWenjing Liu 3252c595fb05SWenjing Liu /** 3253c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3254c595fb05SWenjing Liu */ 3255c595fb05SWenjing Liu struct dmub_cmd_cable_id_output { 3256c595fb05SWenjing Liu uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3257c595fb05SWenjing Liu uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3258c595fb05SWenjing Liu uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3259c595fb05SWenjing Liu uint8_t RESERVED :2; /**< reserved means not defined */ 3260c595fb05SWenjing Liu }; 3261c595fb05SWenjing Liu 3262c595fb05SWenjing Liu /** 3263c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3264c595fb05SWenjing Liu */ 3265c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id { 3266c595fb05SWenjing Liu struct dmub_cmd_header header; /**< Command header */ 3267c595fb05SWenjing Liu /** 3268c595fb05SWenjing Liu * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3269c595fb05SWenjing Liu */ 3270c595fb05SWenjing Liu union dmub_cmd_cable_id_data { 3271c595fb05SWenjing Liu struct dmub_cmd_cable_id_input input; /**< Input */ 3272c595fb05SWenjing Liu struct dmub_cmd_cable_id_output output; /**< Output */ 3273c595fb05SWenjing Liu uint8_t output_raw; /**< Raw data output */ 3274c595fb05SWenjing Liu } data; 3275c595fb05SWenjing Liu }; 3276c595fb05SWenjing Liu 32771fb695d9SAnthony Koo /** 32781fb695d9SAnthony Koo * Command type of a DMUB_CMD__SECURE_DISPLAY command 32791fb695d9SAnthony Koo */ 3280c0459bddSAlan Liu enum dmub_cmd_secure_display_type { 32811fb695d9SAnthony Koo DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3282c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3283c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3284c0459bddSAlan Liu }; 3285c0459bddSAlan Liu 32861fb695d9SAnthony Koo /** 32871fb695d9SAnthony Koo * Definition of a DMUB_CMD__SECURE_DISPLAY command 32881fb695d9SAnthony Koo */ 3289c0459bddSAlan Liu struct dmub_rb_cmd_secure_display { 3290c0459bddSAlan Liu struct dmub_cmd_header header; 32911fb695d9SAnthony Koo /** 32921fb695d9SAnthony Koo * Data passed from driver to dmub firmware. 32931fb695d9SAnthony Koo */ 3294c0459bddSAlan Liu struct dmub_cmd_roi_info { 3295c0459bddSAlan Liu uint16_t x_start; 3296c0459bddSAlan Liu uint16_t x_end; 3297c0459bddSAlan Liu uint16_t y_start; 3298c0459bddSAlan Liu uint16_t y_end; 3299c0459bddSAlan Liu uint8_t otg_id; 3300c0459bddSAlan Liu uint8_t phy_id; 3301c0459bddSAlan Liu } roi_info; 3302c0459bddSAlan Liu }; 3303c0459bddSAlan Liu 3304c595fb05SWenjing Liu /** 3305592a6318SAnthony Koo * union dmub_rb_cmd - DMUB inbox command. 3306592a6318SAnthony Koo */ 33077c008829SNicholas Kazlauskas union dmub_rb_cmd { 3308592a6318SAnthony Koo /** 3309592a6318SAnthony Koo * Elements shared with all commands. 3310592a6318SAnthony Koo */ 33117c008829SNicholas Kazlauskas struct dmub_rb_cmd_common cmd_common; 3312592a6318SAnthony Koo /** 3313592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3314592a6318SAnthony Koo */ 3315592a6318SAnthony Koo struct dmub_rb_cmd_read_modify_write read_modify_write; 3316592a6318SAnthony Koo /** 3317592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3318592a6318SAnthony Koo */ 3319592a6318SAnthony Koo struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3320592a6318SAnthony Koo /** 3321592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3322592a6318SAnthony Koo */ 3323592a6318SAnthony Koo struct dmub_rb_cmd_burst_write burst_write; 3324592a6318SAnthony Koo /** 3325592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_REG_WAIT command. 3326592a6318SAnthony Koo */ 3327592a6318SAnthony Koo struct dmub_rb_cmd_reg_wait reg_wait; 3328592a6318SAnthony Koo /** 3329592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3330592a6318SAnthony Koo */ 33317c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3332592a6318SAnthony Koo /** 3333592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3334592a6318SAnthony Koo */ 33357c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3336592a6318SAnthony Koo /** 3337592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3338592a6318SAnthony Koo */ 33397c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3340592a6318SAnthony Koo /** 3341592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3342592a6318SAnthony Koo */ 33437c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init dpphy_init; 3344592a6318SAnthony Koo /** 3345592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3346592a6318SAnthony Koo */ 33477c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 33481a595f28SAnthony Koo /** 3349e383b127SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3350e383b127SNicholas Kazlauskas */ 3351e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control domain_control; 3352e383b127SNicholas Kazlauskas /** 33531a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 33541a595f28SAnthony Koo */ 3355d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version psr_set_version; 33561a595f28SAnthony Koo /** 33571a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 33581a595f28SAnthony Koo */ 33597c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 33601a595f28SAnthony Koo /** 33611a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 33621a595f28SAnthony Koo */ 3363d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_enable psr_enable; 33641a595f28SAnthony Koo /** 33651a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 33661a595f28SAnthony Koo */ 33677c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level psr_set_level; 33681a595f28SAnthony Koo /** 33691a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 33701a595f28SAnthony Koo */ 3371672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static psr_force_static; 3372592a6318SAnthony Koo /** 337383eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 337483eb5385SDavid Zhang */ 337583eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 337683eb5385SDavid Zhang /** 337783eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 337883eb5385SDavid Zhang */ 337983eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info update_cursor_info; 338083eb5385SDavid Zhang /** 338183eb5385SDavid Zhang * Definition of a DMUB_CMD__HW_LOCK command. 338283eb5385SDavid Zhang * Command is used by driver and FW. 338383eb5385SDavid Zhang */ 338483eb5385SDavid Zhang struct dmub_rb_cmd_lock_hw lock_hw; 338583eb5385SDavid Zhang /** 338683eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 338783eb5385SDavid Zhang */ 338883eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 338983eb5385SDavid Zhang /** 3390e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3391e5dfcd27SRobin Chen */ 3392e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3393e5dfcd27SRobin Chen /** 3394592a6318SAnthony Koo * Definition of a DMUB_CMD__PLAT_54186_WA command. 3395592a6318SAnthony Koo */ 3396bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3397592a6318SAnthony Koo /** 3398592a6318SAnthony Koo * Definition of a DMUB_CMD__MALL command. 3399592a6318SAnthony Koo */ 340052f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall mall; 3401b04cb192SNicholas Kazlauskas /** 3402ac2e555eSAurabindo Pillai * Definition of a DMUB_CMD__CAB command. 3403ac2e555eSAurabindo Pillai */ 3404ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss cab; 340585f4bc0cSAlvin Lee 340685f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 340785f4bc0cSAlvin Lee 3408ac2e555eSAurabindo Pillai /** 3409b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3410b04cb192SNicholas Kazlauskas */ 3411b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3412b04cb192SNicholas Kazlauskas 3413b04cb192SNicholas Kazlauskas /** 3414b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3415b04cb192SNicholas Kazlauskas */ 3416b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3417b04cb192SNicholas Kazlauskas 3418b04cb192SNicholas Kazlauskas /** 3419b04cb192SNicholas Kazlauskas * Definition of DMUB_CMD__PANEL_CNTL commands. 3420b04cb192SNicholas Kazlauskas */ 3421b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl panel_cntl; 34221a595f28SAnthony Koo /** 34231a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 34241a595f28SAnthony Koo */ 3425e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 34261a595f28SAnthony Koo 34271a595f28SAnthony Koo /** 34281a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 34291a595f28SAnthony Koo */ 3430e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 34311a595f28SAnthony Koo 34321a595f28SAnthony Koo /** 34331a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 34341a595f28SAnthony Koo */ 3435e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level abm_set_level; 34361a595f28SAnthony Koo 34371a595f28SAnthony Koo /** 34381a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 34391a595f28SAnthony Koo */ 3440e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 34411a595f28SAnthony Koo 34421a595f28SAnthony Koo /** 34431a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 34441a595f28SAnthony Koo */ 3445e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 34461a595f28SAnthony Koo 34471a595f28SAnthony Koo /** 34481a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 34491a595f28SAnthony Koo */ 345016012806SWyatt Wood struct dmub_rb_cmd_abm_init_config abm_init_config; 34511a595f28SAnthony Koo 34521a595f28SAnthony Koo /** 3453b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 3454b629a824SEric Yang */ 3455b629a824SEric Yang struct dmub_rb_cmd_abm_pause abm_pause; 3456b629a824SEric Yang 3457b629a824SEric Yang /** 34581a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 34591a595f28SAnthony Koo */ 3460d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access dp_aux_access; 34611a595f28SAnthony Koo 34621a595f28SAnthony Koo /** 3463592a6318SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3464592a6318SAnthony Koo */ 3465592a6318SAnthony Koo struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3466592a6318SAnthony Koo 3467592a6318SAnthony Koo /** 3468592a6318SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 34691a595f28SAnthony Koo */ 347034ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3471b09c1fffSLeo (Hanghong) Ma 3472b09c1fffSLeo (Hanghong) Ma /** 3473b09c1fffSLeo (Hanghong) Ma * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3474b09c1fffSLeo (Hanghong) Ma */ 3475b09c1fffSLeo (Hanghong) Ma struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3476592a6318SAnthony Koo struct dmub_rb_cmd_drr_update drr_update; 347700fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 347800fa7f03SRodrigo Siqueira 34791a595f28SAnthony Koo /** 34801a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 34811a595f28SAnthony Koo */ 34821a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control lvtma_control; 3483021eaef8SAnthony Koo /** 348441f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 348541f91315SNicholas Kazlauskas */ 348641f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 348741f91315SNicholas Kazlauskas /** 348876724b76SJimmy Kizito * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 348976724b76SJimmy Kizito */ 349076724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 349176724b76SJimmy Kizito /** 349271af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 349371af9d46SMeenakshikumar Somasundaram */ 349471af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access set_config_access; 349571af9d46SMeenakshikumar Somasundaram /** 3496139a3311SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3497139a3311SMeenakshikumar Somasundaram */ 3498139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3499139a3311SMeenakshikumar Somasundaram /** 3500021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 3501021eaef8SAnthony Koo */ 3502021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea edid_cea; 3503c595fb05SWenjing Liu /** 3504c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3505c595fb05SWenjing Liu */ 3506c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3507ea5a4db9SAnthony Koo 3508ea5a4db9SAnthony Koo /** 3509ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3510ea5a4db9SAnthony Koo */ 3511ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state query_hpd; 35126f4f8ff5SMeenakshikumar Somasundaram /** 3513c0459bddSAlan Liu * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3514c0459bddSAlan Liu */ 3515c0459bddSAlan Liu struct dmub_rb_cmd_secure_display secure_display; 35161fb695d9SAnthony Koo 3517c0459bddSAlan Liu /** 35186f4f8ff5SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 35196f4f8ff5SMeenakshikumar Somasundaram */ 35206f4f8ff5SMeenakshikumar Somasundaram struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 35217c008829SNicholas Kazlauskas }; 35227c008829SNicholas Kazlauskas 3523592a6318SAnthony Koo /** 3524592a6318SAnthony Koo * union dmub_rb_out_cmd - Outbox command 3525592a6318SAnthony Koo */ 3526d9beecfcSAnthony Koo union dmub_rb_out_cmd { 3527592a6318SAnthony Koo /** 3528592a6318SAnthony Koo * Parameters common to every command. 3529592a6318SAnthony Koo */ 3530d9beecfcSAnthony Koo struct dmub_rb_cmd_common cmd_common; 3531592a6318SAnthony Koo /** 3532592a6318SAnthony Koo * AUX reply command. 3533592a6318SAnthony Koo */ 3534d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3535592a6318SAnthony Koo /** 3536592a6318SAnthony Koo * HPD notify command. 3537592a6318SAnthony Koo */ 3538d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 353971af9d46SMeenakshikumar Somasundaram /** 354071af9d46SMeenakshikumar Somasundaram * SET_CONFIG reply command. 354171af9d46SMeenakshikumar Somasundaram */ 354271af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3543669018a9SMustapha Ghaddar /** 35448af54c61SMustapha Ghaddar * DPIA notification command. 3545669018a9SMustapha Ghaddar */ 35468af54c61SMustapha Ghaddar struct dmub_rb_cmd_dpia_notification dpia_notification; 3547d9beecfcSAnthony Koo }; 35487c008829SNicholas Kazlauskas #pragma pack(pop) 35497c008829SNicholas Kazlauskas 355084034ad4SAnthony Koo 355184034ad4SAnthony Koo //============================================================================== 355284034ad4SAnthony Koo //</DMUB_CMD>=================================================================== 355384034ad4SAnthony Koo //============================================================================== 355484034ad4SAnthony Koo //< DMUB_RB>==================================================================== 355584034ad4SAnthony Koo //============================================================================== 355684034ad4SAnthony Koo 355784034ad4SAnthony Koo #if defined(__cplusplus) 355884034ad4SAnthony Koo extern "C" { 355984034ad4SAnthony Koo #endif 356084034ad4SAnthony Koo 3561592a6318SAnthony Koo /** 3562592a6318SAnthony Koo * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3563592a6318SAnthony Koo */ 356484034ad4SAnthony Koo struct dmub_rb_init_params { 3565592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 3566592a6318SAnthony Koo void *base_address; /**< CPU base address for ring's data */ 3567592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3568592a6318SAnthony Koo uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3569592a6318SAnthony Koo uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 357084034ad4SAnthony Koo }; 357184034ad4SAnthony Koo 3572592a6318SAnthony Koo /** 3573592a6318SAnthony Koo * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3574592a6318SAnthony Koo */ 357584034ad4SAnthony Koo struct dmub_rb { 3576592a6318SAnthony Koo void *base_address; /**< CPU address for the ring's data */ 3577592a6318SAnthony Koo uint32_t rptr; /**< Read pointer for consumer in bytes */ 3578592a6318SAnthony Koo uint32_t wrpt; /**< Write pointer for producer in bytes */ 3579592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 358084034ad4SAnthony Koo 3581592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 3582592a6318SAnthony Koo void *dmub; /**< Pointer to the DMUB interface */ 358384034ad4SAnthony Koo }; 358484034ad4SAnthony Koo 3585592a6318SAnthony Koo /** 3586592a6318SAnthony Koo * @brief Checks if the ringbuffer is empty. 3587592a6318SAnthony Koo * 3588592a6318SAnthony Koo * @param rb DMUB Ringbuffer 3589592a6318SAnthony Koo * @return true if empty 3590592a6318SAnthony Koo * @return false otherwise 3591592a6318SAnthony Koo */ 359284034ad4SAnthony Koo static inline bool dmub_rb_empty(struct dmub_rb *rb) 359384034ad4SAnthony Koo { 359484034ad4SAnthony Koo return (rb->wrpt == rb->rptr); 359584034ad4SAnthony Koo } 359684034ad4SAnthony Koo 3597592a6318SAnthony Koo /** 3598592a6318SAnthony Koo * @brief Checks if the ringbuffer is full 3599592a6318SAnthony Koo * 3600592a6318SAnthony Koo * @param rb DMUB Ringbuffer 3601592a6318SAnthony Koo * @return true if full 3602592a6318SAnthony Koo * @return false otherwise 3603592a6318SAnthony Koo */ 360484034ad4SAnthony Koo static inline bool dmub_rb_full(struct dmub_rb *rb) 360584034ad4SAnthony Koo { 360684034ad4SAnthony Koo uint32_t data_count; 360784034ad4SAnthony Koo 360884034ad4SAnthony Koo if (rb->wrpt >= rb->rptr) 360984034ad4SAnthony Koo data_count = rb->wrpt - rb->rptr; 361084034ad4SAnthony Koo else 361184034ad4SAnthony Koo data_count = rb->capacity - (rb->rptr - rb->wrpt); 361284034ad4SAnthony Koo 361384034ad4SAnthony Koo return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 361484034ad4SAnthony Koo } 361584034ad4SAnthony Koo 3616592a6318SAnthony Koo /** 3617592a6318SAnthony Koo * @brief Pushes a command into the ringbuffer 3618592a6318SAnthony Koo * 3619592a6318SAnthony Koo * @param rb DMUB ringbuffer 3620592a6318SAnthony Koo * @param cmd The command to push 3621592a6318SAnthony Koo * @return true if the ringbuffer was not full 3622592a6318SAnthony Koo * @return false otherwise 3623592a6318SAnthony Koo */ 362484034ad4SAnthony Koo static inline bool dmub_rb_push_front(struct dmub_rb *rb, 362584034ad4SAnthony Koo const union dmub_rb_cmd *cmd) 362684034ad4SAnthony Koo { 36273f232a0fSAnthony Koo uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 36283a9d5b0bSAnthony Koo const uint64_t *src = (const uint64_t *)cmd; 36293a9d5b0bSAnthony Koo uint8_t i; 363084034ad4SAnthony Koo 363184034ad4SAnthony Koo if (dmub_rb_full(rb)) 363284034ad4SAnthony Koo return false; 363384034ad4SAnthony Koo 363484034ad4SAnthony Koo // copying data 36353a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 36363a9d5b0bSAnthony Koo *dst++ = *src++; 363784034ad4SAnthony Koo 363884034ad4SAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 363984034ad4SAnthony Koo 364084034ad4SAnthony Koo if (rb->wrpt >= rb->capacity) 364184034ad4SAnthony Koo rb->wrpt %= rb->capacity; 364284034ad4SAnthony Koo 364384034ad4SAnthony Koo return true; 364484034ad4SAnthony Koo } 364584034ad4SAnthony Koo 3646592a6318SAnthony Koo /** 3647592a6318SAnthony Koo * @brief Pushes a command into the DMUB outbox ringbuffer 3648592a6318SAnthony Koo * 3649592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 3650592a6318SAnthony Koo * @param cmd Outbox command 3651592a6318SAnthony Koo * @return true if not full 3652592a6318SAnthony Koo * @return false otherwise 3653592a6318SAnthony Koo */ 3654d9beecfcSAnthony Koo static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3655d9beecfcSAnthony Koo const union dmub_rb_out_cmd *cmd) 3656d9beecfcSAnthony Koo { 3657d9beecfcSAnthony Koo uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3658d459b79bSAnthony Koo const uint8_t *src = (const uint8_t *)cmd; 3659d9beecfcSAnthony Koo 3660d9beecfcSAnthony Koo if (dmub_rb_full(rb)) 3661d9beecfcSAnthony Koo return false; 3662d9beecfcSAnthony Koo 3663d9beecfcSAnthony Koo dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3664d9beecfcSAnthony Koo 3665d9beecfcSAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 3666d9beecfcSAnthony Koo 3667d9beecfcSAnthony Koo if (rb->wrpt >= rb->capacity) 3668d9beecfcSAnthony Koo rb->wrpt %= rb->capacity; 3669d9beecfcSAnthony Koo 3670d9beecfcSAnthony Koo return true; 3671d9beecfcSAnthony Koo } 3672d9beecfcSAnthony Koo 3673592a6318SAnthony Koo /** 3674592a6318SAnthony Koo * @brief Returns the next unprocessed command in the ringbuffer. 3675592a6318SAnthony Koo * 3676592a6318SAnthony Koo * @param rb DMUB ringbuffer 3677592a6318SAnthony Koo * @param cmd The command to return 3678592a6318SAnthony Koo * @return true if not empty 3679592a6318SAnthony Koo * @return false otherwise 3680592a6318SAnthony Koo */ 368184034ad4SAnthony Koo static inline bool dmub_rb_front(struct dmub_rb *rb, 368234ba432cSAnthony Koo union dmub_rb_cmd **cmd) 368384034ad4SAnthony Koo { 368434ba432cSAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 368584034ad4SAnthony Koo 368684034ad4SAnthony Koo if (dmub_rb_empty(rb)) 368784034ad4SAnthony Koo return false; 368884034ad4SAnthony Koo 368934ba432cSAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 369084034ad4SAnthony Koo 369184034ad4SAnthony Koo return true; 369284034ad4SAnthony Koo } 369384034ad4SAnthony Koo 3694592a6318SAnthony Koo /** 36950b51e7e8SAnthony Koo * @brief Determines the next ringbuffer offset. 36960b51e7e8SAnthony Koo * 36970b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 36980b51e7e8SAnthony Koo * @param num_cmds Number of commands 36990b51e7e8SAnthony Koo * @param next_rptr The next offset in the ringbuffer 37000b51e7e8SAnthony Koo */ 37010b51e7e8SAnthony Koo static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 37020b51e7e8SAnthony Koo uint32_t num_cmds, 37030b51e7e8SAnthony Koo uint32_t *next_rptr) 37040b51e7e8SAnthony Koo { 37050b51e7e8SAnthony Koo *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 37060b51e7e8SAnthony Koo 37070b51e7e8SAnthony Koo if (*next_rptr >= rb->capacity) 37080b51e7e8SAnthony Koo *next_rptr %= rb->capacity; 37090b51e7e8SAnthony Koo } 37100b51e7e8SAnthony Koo 37110b51e7e8SAnthony Koo /** 37120b51e7e8SAnthony Koo * @brief Returns a pointer to a command in the inbox. 37130b51e7e8SAnthony Koo * 37140b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 37150b51e7e8SAnthony Koo * @param cmd The inbox command to return 37160b51e7e8SAnthony Koo * @param rptr The ringbuffer offset 37170b51e7e8SAnthony Koo * @return true if not empty 37180b51e7e8SAnthony Koo * @return false otherwise 37190b51e7e8SAnthony Koo */ 37200b51e7e8SAnthony Koo static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 37210b51e7e8SAnthony Koo union dmub_rb_cmd **cmd, 37220b51e7e8SAnthony Koo uint32_t rptr) 37230b51e7e8SAnthony Koo { 37240b51e7e8SAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 37250b51e7e8SAnthony Koo 37260b51e7e8SAnthony Koo if (dmub_rb_empty(rb)) 37270b51e7e8SAnthony Koo return false; 37280b51e7e8SAnthony Koo 37290b51e7e8SAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 37300b51e7e8SAnthony Koo 37310b51e7e8SAnthony Koo return true; 37320b51e7e8SAnthony Koo } 37330b51e7e8SAnthony Koo 37340b51e7e8SAnthony Koo /** 3735592a6318SAnthony Koo * @brief Returns the next unprocessed command in the outbox. 3736592a6318SAnthony Koo * 3737592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 3738592a6318SAnthony Koo * @param cmd The outbox command to return 3739592a6318SAnthony Koo * @return true if not empty 3740592a6318SAnthony Koo * @return false otherwise 3741592a6318SAnthony Koo */ 3742d9beecfcSAnthony Koo static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3743d9beecfcSAnthony Koo union dmub_rb_out_cmd *cmd) 3744d9beecfcSAnthony Koo { 37453f232a0fSAnthony Koo const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 37463a9d5b0bSAnthony Koo uint64_t *dst = (uint64_t *)cmd; 37473a9d5b0bSAnthony Koo uint8_t i; 3748d9beecfcSAnthony Koo 3749d9beecfcSAnthony Koo if (dmub_rb_empty(rb)) 3750d9beecfcSAnthony Koo return false; 3751d9beecfcSAnthony Koo 3752d9beecfcSAnthony Koo // copying data 37533a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 37543a9d5b0bSAnthony Koo *dst++ = *src++; 3755d9beecfcSAnthony Koo 3756d9beecfcSAnthony Koo return true; 3757d9beecfcSAnthony Koo } 3758d9beecfcSAnthony Koo 3759592a6318SAnthony Koo /** 3760592a6318SAnthony Koo * @brief Removes the front entry in the ringbuffer. 3761592a6318SAnthony Koo * 3762592a6318SAnthony Koo * @param rb DMUB ringbuffer 3763592a6318SAnthony Koo * @return true if the command was removed 3764592a6318SAnthony Koo * @return false if there were no commands 3765592a6318SAnthony Koo */ 376684034ad4SAnthony Koo static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 376784034ad4SAnthony Koo { 376884034ad4SAnthony Koo if (dmub_rb_empty(rb)) 376984034ad4SAnthony Koo return false; 377084034ad4SAnthony Koo 377184034ad4SAnthony Koo rb->rptr += DMUB_RB_CMD_SIZE; 377284034ad4SAnthony Koo 377384034ad4SAnthony Koo if (rb->rptr >= rb->capacity) 377484034ad4SAnthony Koo rb->rptr %= rb->capacity; 377584034ad4SAnthony Koo 377684034ad4SAnthony Koo return true; 377784034ad4SAnthony Koo } 377884034ad4SAnthony Koo 3779592a6318SAnthony Koo /** 3780592a6318SAnthony Koo * @brief Flushes commands in the ringbuffer to framebuffer memory. 3781592a6318SAnthony Koo * 3782592a6318SAnthony Koo * Avoids a race condition where DMCUB accesses memory while 3783592a6318SAnthony Koo * there are still writes in flight to framebuffer. 3784592a6318SAnthony Koo * 3785592a6318SAnthony Koo * @param rb DMUB ringbuffer 3786592a6318SAnthony Koo */ 378784034ad4SAnthony Koo static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 378884034ad4SAnthony Koo { 378984034ad4SAnthony Koo uint32_t rptr = rb->rptr; 379084034ad4SAnthony Koo uint32_t wptr = rb->wrpt; 379184034ad4SAnthony Koo 379284034ad4SAnthony Koo while (rptr != wptr) { 37937da7b02eSAashish Sharma uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 37943a9d5b0bSAnthony Koo uint8_t i; 379584034ad4SAnthony Koo 379623da6e0fSMaíra Canal /* Don't remove this. 379723da6e0fSMaíra Canal * The contents need to actually be read from the ring buffer 379823da6e0fSMaíra Canal * for this function to be effective. 379923da6e0fSMaíra Canal */ 38003a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 38017da7b02eSAashish Sharma (void)READ_ONCE(*data++); 380284034ad4SAnthony Koo 380384034ad4SAnthony Koo rptr += DMUB_RB_CMD_SIZE; 380484034ad4SAnthony Koo if (rptr >= rb->capacity) 380584034ad4SAnthony Koo rptr %= rb->capacity; 380684034ad4SAnthony Koo } 380784034ad4SAnthony Koo } 380884034ad4SAnthony Koo 3809592a6318SAnthony Koo /** 3810592a6318SAnthony Koo * @brief Initializes a DMCUB ringbuffer 3811592a6318SAnthony Koo * 3812592a6318SAnthony Koo * @param rb DMUB ringbuffer 3813592a6318SAnthony Koo * @param init_params initial configuration for the ringbuffer 3814592a6318SAnthony Koo */ 381584034ad4SAnthony Koo static inline void dmub_rb_init(struct dmub_rb *rb, 381684034ad4SAnthony Koo struct dmub_rb_init_params *init_params) 381784034ad4SAnthony Koo { 381884034ad4SAnthony Koo rb->base_address = init_params->base_address; 381984034ad4SAnthony Koo rb->capacity = init_params->capacity; 382084034ad4SAnthony Koo rb->rptr = init_params->read_ptr; 382184034ad4SAnthony Koo rb->wrpt = init_params->write_ptr; 382284034ad4SAnthony Koo } 382384034ad4SAnthony Koo 3824592a6318SAnthony Koo /** 3825592a6318SAnthony Koo * @brief Copies output data from in/out commands into the given command. 3826592a6318SAnthony Koo * 3827592a6318SAnthony Koo * @param rb DMUB ringbuffer 3828592a6318SAnthony Koo * @param cmd Command to copy data into 3829592a6318SAnthony Koo */ 383034ba432cSAnthony Koo static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 383134ba432cSAnthony Koo union dmub_rb_cmd *cmd) 383234ba432cSAnthony Koo { 383334ba432cSAnthony Koo // Copy rb entry back into command 383434ba432cSAnthony Koo uint8_t *rd_ptr = (rb->rptr == 0) ? 383534ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 383634ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 383734ba432cSAnthony Koo 383834ba432cSAnthony Koo dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 383934ba432cSAnthony Koo } 384034ba432cSAnthony Koo 384184034ad4SAnthony Koo #if defined(__cplusplus) 384284034ad4SAnthony Koo } 384384034ad4SAnthony Koo #endif 384484034ad4SAnthony Koo 384584034ad4SAnthony Koo //============================================================================== 384684034ad4SAnthony Koo //</DMUB_RB>==================================================================== 384784034ad4SAnthony Koo //============================================================================== 384884034ad4SAnthony Koo 38497c008829SNicholas Kazlauskas #endif /* _DMUB_CMD_H_ */ 3850