17c008829SNicholas Kazlauskas /* 27c008829SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 37c008829SNicholas Kazlauskas * 47c008829SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 57c008829SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 67c008829SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 77c008829SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87c008829SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 97c008829SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 107c008829SNicholas Kazlauskas * 117c008829SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 127c008829SNicholas Kazlauskas * all copies or substantial portions of the Software. 137c008829SNicholas Kazlauskas * 147c008829SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157c008829SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167c008829SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177c008829SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187c008829SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197c008829SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207c008829SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 217c008829SNicholas Kazlauskas * 227c008829SNicholas Kazlauskas * Authors: AMD 237c008829SNicholas Kazlauskas * 247c008829SNicholas Kazlauskas */ 257c008829SNicholas Kazlauskas 265624c345SAnthony Koo #ifndef DMUB_CMD_H 275624c345SAnthony Koo #define DMUB_CMD_H 287c008829SNicholas Kazlauskas 298b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 308b19a4e3SAnthony Koo #include "dmub_fw_types.h" 318b19a4e3SAnthony Koo #include "include_legacy/atomfirmware.h" 328b19a4e3SAnthony Koo 338b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) 348b19a4e3SAnthony Koo #include <string.h> 358b19a4e3SAnthony Koo #endif 368b19a4e3SAnthony Koo #else 378b19a4e3SAnthony Koo 3884034ad4SAnthony Koo #include <asm/byteorder.h> 3984034ad4SAnthony Koo #include <linux/types.h> 4084034ad4SAnthony Koo #include <linux/string.h> 4184034ad4SAnthony Koo #include <linux/delay.h> 4284034ad4SAnthony Koo 437c008829SNicholas Kazlauskas #include "atomfirmware.h" 4422aa5614SYongqiang Sun 458b19a4e3SAnthony Koo #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 468b19a4e3SAnthony Koo 4784034ad4SAnthony Koo //<DMUB_TYPES>================================================================== 4884034ad4SAnthony Koo /* Basic type definitions. */ 4984034ad4SAnthony Koo 508b19a4e3SAnthony Koo #define __forceinline inline 518b19a4e3SAnthony Koo 521a595f28SAnthony Koo /** 531a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled gradually 541a595f28SAnthony Koo * by slowly reversing all backlight programming and pixel compensation. 551a595f28SAnthony Koo */ 5684034ad4SAnthony Koo #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 571a595f28SAnthony Koo 581a595f28SAnthony Koo /** 591a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 601a595f28SAnthony Koo * and undo all backlight programming and pixel compensation. 611a595f28SAnthony Koo */ 6284034ad4SAnthony Koo #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 631a595f28SAnthony Koo 641a595f28SAnthony Koo /** 651a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 661a595f28SAnthony Koo * and keep the current backlight programming and pixel compensation. 671a595f28SAnthony Koo */ 68d9beecfcSAnthony Koo #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 691a595f28SAnthony Koo 701a595f28SAnthony Koo /** 711a595f28SAnthony Koo * Flag from driver to set the current ABM pipe index or ABM operating level. 721a595f28SAnthony Koo */ 7384034ad4SAnthony Koo #define SET_ABM_PIPE_NORMAL 1 7484034ad4SAnthony Koo 751a595f28SAnthony Koo /** 761a595f28SAnthony Koo * Number of ambient light levels in ABM algorithm. 771a595f28SAnthony Koo */ 781a595f28SAnthony Koo #define NUM_AMBI_LEVEL 5 791a595f28SAnthony Koo 801a595f28SAnthony Koo /** 811a595f28SAnthony Koo * Number of operating/aggression levels in ABM algorithm. 821a595f28SAnthony Koo */ 831a595f28SAnthony Koo #define NUM_AGGR_LEVEL 4 841a595f28SAnthony Koo 851a595f28SAnthony Koo /** 861a595f28SAnthony Koo * Number of segments in the gamma curve. 871a595f28SAnthony Koo */ 881a595f28SAnthony Koo #define NUM_POWER_FN_SEGS 8 891a595f28SAnthony Koo 901a595f28SAnthony Koo /** 911a595f28SAnthony Koo * Number of segments in the backlight curve. 921a595f28SAnthony Koo */ 931a595f28SAnthony Koo #define NUM_BL_CURVE_SEGS 16 941a595f28SAnthony Koo 9585f4bc0cSAlvin Lee /* Maximum number of SubVP streams */ 9685f4bc0cSAlvin Lee #define DMUB_MAX_SUBVP_STREAMS 2 9785f4bc0cSAlvin Lee 98d3981ee7SAnthony Koo /* Define max FPO streams as 4 for now. Current implementation today 99d3981ee7SAnthony Koo * only supports 1, but could be more in the future. Reduce array 100d3981ee7SAnthony Koo * size to ensure the command size remains less than 64 bytes if 101d3981ee7SAnthony Koo * adding new fields. 102d3981ee7SAnthony Koo */ 103d3981ee7SAnthony Koo #define DMUB_MAX_FPO_STREAMS 4 104d3981ee7SAnthony Koo 10584034ad4SAnthony Koo /* Maximum number of streams on any ASIC. */ 10684034ad4SAnthony Koo #define DMUB_MAX_STREAMS 6 10784034ad4SAnthony Koo 10884034ad4SAnthony Koo /* Maximum number of planes on any ASIC. */ 10984034ad4SAnthony Koo #define DMUB_MAX_PLANES 6 11084034ad4SAnthony Koo 11170732504SYongqiang Sun /* Trace buffer offset for entry */ 11270732504SYongqiang Sun #define TRACE_BUFFER_ENTRY_OFFSET 16 11370732504SYongqiang Sun 114592a6318SAnthony Koo /** 11583eb5385SDavid Zhang * Maximum number of dirty rects supported by FW. 11683eb5385SDavid Zhang */ 11783eb5385SDavid Zhang #define DMUB_MAX_DIRTY_RECTS 3 11883eb5385SDavid Zhang 11983eb5385SDavid Zhang /** 120f56c837aSMikita Lipski * 121f56c837aSMikita Lipski * PSR control version legacy 122f56c837aSMikita Lipski */ 123f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 124f56c837aSMikita Lipski /** 125f56c837aSMikita Lipski * PSR control version with multi edp support 126f56c837aSMikita Lipski */ 127f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 128f56c837aSMikita Lipski 129f56c837aSMikita Lipski 130f56c837aSMikita Lipski /** 13163de4f04SJake Wang * ABM control version legacy 132e922057bSJake Wang */ 13363de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 134e922057bSJake Wang 135e922057bSJake Wang /** 13663de4f04SJake Wang * ABM control version with multi edp support 137e922057bSJake Wang */ 13863de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 139e922057bSJake Wang 140e922057bSJake Wang /** 141592a6318SAnthony Koo * Physical framebuffer address location, 64-bit. 142592a6318SAnthony Koo */ 14384034ad4SAnthony Koo #ifndef PHYSICAL_ADDRESS_LOC 14484034ad4SAnthony Koo #define PHYSICAL_ADDRESS_LOC union large_integer 14584034ad4SAnthony Koo #endif 14684034ad4SAnthony Koo 147592a6318SAnthony Koo /** 148592a6318SAnthony Koo * OS/FW agnostic memcpy 149592a6318SAnthony Koo */ 15084034ad4SAnthony Koo #ifndef dmub_memcpy 15184034ad4SAnthony Koo #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 15284034ad4SAnthony Koo #endif 15384034ad4SAnthony Koo 154592a6318SAnthony Koo /** 155592a6318SAnthony Koo * OS/FW agnostic memset 156592a6318SAnthony Koo */ 15784034ad4SAnthony Koo #ifndef dmub_memset 15884034ad4SAnthony Koo #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 15984034ad4SAnthony Koo #endif 16084034ad4SAnthony Koo 161d9beecfcSAnthony Koo #if defined(__cplusplus) 162d9beecfcSAnthony Koo extern "C" { 163d9beecfcSAnthony Koo #endif 164d9beecfcSAnthony Koo 165592a6318SAnthony Koo /** 166592a6318SAnthony Koo * OS/FW agnostic udelay 167592a6318SAnthony Koo */ 16884034ad4SAnthony Koo #ifndef dmub_udelay 16984034ad4SAnthony Koo #define dmub_udelay(microseconds) udelay(microseconds) 17084034ad4SAnthony Koo #endif 17184034ad4SAnthony Koo 1726e60cba6SJonathan Gray #pragma pack(push, 1) 173592a6318SAnthony Koo /** 174592a6318SAnthony Koo * union dmub_addr - DMUB physical/virtual 64-bit address. 175592a6318SAnthony Koo */ 17684034ad4SAnthony Koo union dmub_addr { 17784034ad4SAnthony Koo struct { 178592a6318SAnthony Koo uint32_t low_part; /**< Lower 32 bits */ 179592a6318SAnthony Koo uint32_t high_part; /**< Upper 32 bits */ 180592a6318SAnthony Koo } u; /*<< Low/high bit access */ 181592a6318SAnthony Koo uint64_t quad_part; /*<< 64 bit address */ 18284034ad4SAnthony Koo }; 1836e60cba6SJonathan Gray #pragma pack(pop) 18484034ad4SAnthony Koo 1851a595f28SAnthony Koo /** 18683eb5385SDavid Zhang * Dirty rect definition. 18783eb5385SDavid Zhang */ 18883eb5385SDavid Zhang struct dmub_rect { 18983eb5385SDavid Zhang /** 19083eb5385SDavid Zhang * Dirty rect x offset. 19183eb5385SDavid Zhang */ 19283eb5385SDavid Zhang uint32_t x; 19383eb5385SDavid Zhang 19483eb5385SDavid Zhang /** 19583eb5385SDavid Zhang * Dirty rect y offset. 19683eb5385SDavid Zhang */ 19783eb5385SDavid Zhang uint32_t y; 19883eb5385SDavid Zhang 19983eb5385SDavid Zhang /** 20083eb5385SDavid Zhang * Dirty rect width. 20183eb5385SDavid Zhang */ 20283eb5385SDavid Zhang uint32_t width; 20383eb5385SDavid Zhang 20483eb5385SDavid Zhang /** 20583eb5385SDavid Zhang * Dirty rect height. 20683eb5385SDavid Zhang */ 20783eb5385SDavid Zhang uint32_t height; 20883eb5385SDavid Zhang }; 20983eb5385SDavid Zhang 21083eb5385SDavid Zhang /** 2111a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 2121a595f28SAnthony Koo */ 21384034ad4SAnthony Koo union dmub_psr_debug_flags { 2141a595f28SAnthony Koo /** 2151a595f28SAnthony Koo * Debug flags. 2161a595f28SAnthony Koo */ 21784034ad4SAnthony Koo struct { 2181a595f28SAnthony Koo /** 2191a595f28SAnthony Koo * Enable visual confirm in FW. 2201a595f28SAnthony Koo */ 221447f3d0fSAnthony Koo uint32_t visual_confirm : 1; 22283eb5385SDavid Zhang 22383eb5385SDavid Zhang /** 22483eb5385SDavid Zhang * Force all selective updates to bw full frame updates. 22583eb5385SDavid Zhang */ 22683eb5385SDavid Zhang uint32_t force_full_frame_update : 1; 22783eb5385SDavid Zhang 2281a595f28SAnthony Koo /** 2291a595f28SAnthony Koo * Use HW Lock Mgr object to do HW locking in FW. 2301a595f28SAnthony Koo */ 231447f3d0fSAnthony Koo uint32_t use_hw_lock_mgr : 1; 2321a595f28SAnthony Koo 2331a595f28SAnthony Koo /** 234548f2125SRobin Chen * Use TPS3 signal when restore main link. 2351a595f28SAnthony Koo */ 236548f2125SRobin Chen uint32_t force_wakeup_by_tps3 : 1; 237cf472dbdSAnthony Koo 238cf472dbdSAnthony Koo /** 239cf472dbdSAnthony Koo * Back to back flip, therefore cannot power down PHY 240cf472dbdSAnthony Koo */ 241cf472dbdSAnthony Koo uint32_t back_to_back_flip : 1; 242cf472dbdSAnthony Koo 24384034ad4SAnthony Koo } bitfields; 24484034ad4SAnthony Koo 2451a595f28SAnthony Koo /** 2461a595f28SAnthony Koo * Union for debug flags. 2471a595f28SAnthony Koo */ 248447f3d0fSAnthony Koo uint32_t u32All; 24984034ad4SAnthony Koo }; 25084034ad4SAnthony Koo 2511a595f28SAnthony Koo /** 2520991f44cSAnthony Koo * DMUB visual confirm color 2531a595f28SAnthony Koo */ 25434ba432cSAnthony Koo struct dmub_feature_caps { 2551a595f28SAnthony Koo /** 2561a595f28SAnthony Koo * Max PSR version supported by FW. 2571a595f28SAnthony Koo */ 25834ba432cSAnthony Koo uint8_t psr; 25900fa7f03SRodrigo Siqueira uint8_t fw_assisted_mclk_switch; 26000fa7f03SRodrigo Siqueira uint8_t reserved[6]; 26134ba432cSAnthony Koo }; 26234ba432cSAnthony Koo 263b09c1fffSLeo (Hanghong) Ma struct dmub_visual_confirm_color { 264b09c1fffSLeo (Hanghong) Ma /** 265b09c1fffSLeo (Hanghong) Ma * Maximum 10 bits color value 266b09c1fffSLeo (Hanghong) Ma */ 267b09c1fffSLeo (Hanghong) Ma uint16_t color_r_cr; 268b09c1fffSLeo (Hanghong) Ma uint16_t color_g_y; 269b09c1fffSLeo (Hanghong) Ma uint16_t color_b_cb; 270b09c1fffSLeo (Hanghong) Ma uint16_t panel_inst; 271b09c1fffSLeo (Hanghong) Ma }; 272b09c1fffSLeo (Hanghong) Ma 27384034ad4SAnthony Koo #if defined(__cplusplus) 27484034ad4SAnthony Koo } 27584034ad4SAnthony Koo #endif 27684034ad4SAnthony Koo 27784034ad4SAnthony Koo //============================================================================== 27884034ad4SAnthony Koo //</DMUB_TYPES>================================================================= 27984034ad4SAnthony Koo //============================================================================== 28084034ad4SAnthony Koo //< DMUB_META>================================================================== 28184034ad4SAnthony Koo //============================================================================== 28284034ad4SAnthony Koo #pragma pack(push, 1) 28384034ad4SAnthony Koo 28484034ad4SAnthony Koo /* Magic value for identifying dmub_fw_meta_info */ 28584034ad4SAnthony Koo #define DMUB_FW_META_MAGIC 0x444D5542 28684034ad4SAnthony Koo 28784034ad4SAnthony Koo /* Offset from the end of the file to the dmub_fw_meta_info */ 28884034ad4SAnthony Koo #define DMUB_FW_META_OFFSET 0x24 28984034ad4SAnthony Koo 29084034ad4SAnthony Koo /** 29184034ad4SAnthony Koo * struct dmub_fw_meta_info - metadata associated with fw binary 29284034ad4SAnthony Koo * 29384034ad4SAnthony Koo * NOTE: This should be considered a stable API. Fields should 29484034ad4SAnthony Koo * not be repurposed or reordered. New fields should be 29584034ad4SAnthony Koo * added instead to extend the structure. 29684034ad4SAnthony Koo * 29784034ad4SAnthony Koo * @magic_value: magic value identifying DMUB firmware meta info 29884034ad4SAnthony Koo * @fw_region_size: size of the firmware state region 29984034ad4SAnthony Koo * @trace_buffer_size: size of the tracebuffer region 30084034ad4SAnthony Koo * @fw_version: the firmware version information 301b2265774SAnthony Koo * @dal_fw: 1 if the firmware is DAL 30284034ad4SAnthony Koo */ 30384034ad4SAnthony Koo struct dmub_fw_meta_info { 304592a6318SAnthony Koo uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 305592a6318SAnthony Koo uint32_t fw_region_size; /**< size of the firmware state region */ 306592a6318SAnthony Koo uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 307592a6318SAnthony Koo uint32_t fw_version; /**< the firmware version information */ 308592a6318SAnthony Koo uint8_t dal_fw; /**< 1 if the firmware is DAL */ 309592a6318SAnthony Koo uint8_t reserved[3]; /**< padding bits */ 31084034ad4SAnthony Koo }; 31184034ad4SAnthony Koo 312592a6318SAnthony Koo /** 313592a6318SAnthony Koo * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 314592a6318SAnthony Koo */ 31584034ad4SAnthony Koo union dmub_fw_meta { 316592a6318SAnthony Koo struct dmub_fw_meta_info info; /**< metadata info */ 317592a6318SAnthony Koo uint8_t reserved[64]; /**< padding bits */ 31884034ad4SAnthony Koo }; 31984034ad4SAnthony Koo 32084034ad4SAnthony Koo #pragma pack(pop) 321788408b7SAnthony Koo 32284034ad4SAnthony Koo //============================================================================== 3236b66208fSYongqiang Sun //< DMUB Trace Buffer>================================================================ 3246b66208fSYongqiang Sun //============================================================================== 325592a6318SAnthony Koo /** 326592a6318SAnthony Koo * dmub_trace_code_t - firmware trace code, 32-bits 327592a6318SAnthony Koo */ 3286b66208fSYongqiang Sun typedef uint32_t dmub_trace_code_t; 3296b66208fSYongqiang Sun 330592a6318SAnthony Koo /** 331592a6318SAnthony Koo * struct dmcub_trace_buf_entry - Firmware trace entry 332592a6318SAnthony Koo */ 3336b66208fSYongqiang Sun struct dmcub_trace_buf_entry { 334592a6318SAnthony Koo dmub_trace_code_t trace_code; /**< trace code for the event */ 335592a6318SAnthony Koo uint32_t tick_count; /**< the tick count at time of trace */ 336592a6318SAnthony Koo uint32_t param0; /**< trace defined parameter 0 */ 337592a6318SAnthony Koo uint32_t param1; /**< trace defined parameter 1 */ 3386b66208fSYongqiang Sun }; 3396b66208fSYongqiang Sun 3406b66208fSYongqiang Sun //============================================================================== 341788408b7SAnthony Koo //< DMUB_STATUS>================================================================ 342788408b7SAnthony Koo //============================================================================== 343788408b7SAnthony Koo 344788408b7SAnthony Koo /** 345788408b7SAnthony Koo * DMCUB scratch registers can be used to determine firmware status. 346788408b7SAnthony Koo * Current scratch register usage is as follows: 347788408b7SAnthony Koo * 348492dd8a8SAnthony Koo * SCRATCH0: FW Boot Status register 349021eaef8SAnthony Koo * SCRATCH5: LVTMA Status Register 350492dd8a8SAnthony Koo * SCRATCH15: FW Boot Options register 351788408b7SAnthony Koo */ 352788408b7SAnthony Koo 353592a6318SAnthony Koo /** 354592a6318SAnthony Koo * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 355592a6318SAnthony Koo */ 356492dd8a8SAnthony Koo union dmub_fw_boot_status { 357492dd8a8SAnthony Koo struct { 358592a6318SAnthony Koo uint32_t dal_fw : 1; /**< 1 if DAL FW */ 359592a6318SAnthony Koo uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 360592a6318SAnthony Koo uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 361592a6318SAnthony Koo uint32_t restore_required : 1; /**< 1 if driver should call restore */ 36201934c30SAnthony Koo uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 363e3416e87SRodrigo Siqueira uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 36401934c30SAnthony Koo uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 3659dce8c2aSAnthony Koo uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 366592a6318SAnthony Koo } bits; /**< status bits */ 367592a6318SAnthony Koo uint32_t all; /**< 32-bit access to status bits */ 368492dd8a8SAnthony Koo }; 369492dd8a8SAnthony Koo 370592a6318SAnthony Koo /** 371592a6318SAnthony Koo * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 372592a6318SAnthony Koo */ 373492dd8a8SAnthony Koo enum dmub_fw_boot_status_bit { 374592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 375592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 376592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 377592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 3781e0958bbSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 37901934c30SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 3809dce8c2aSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 381492dd8a8SAnthony Koo }; 382492dd8a8SAnthony Koo 383021eaef8SAnthony Koo /* Register bit definition for SCRATCH5 */ 384021eaef8SAnthony Koo union dmub_lvtma_status { 385021eaef8SAnthony Koo struct { 386021eaef8SAnthony Koo uint32_t psp_ok : 1; 387021eaef8SAnthony Koo uint32_t edp_on : 1; 388021eaef8SAnthony Koo uint32_t reserved : 30; 389021eaef8SAnthony Koo } bits; 390021eaef8SAnthony Koo uint32_t all; 391021eaef8SAnthony Koo }; 392021eaef8SAnthony Koo 393021eaef8SAnthony Koo enum dmub_lvtma_status_bit { 394021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 395021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 396021eaef8SAnthony Koo }; 397021eaef8SAnthony Koo 398592a6318SAnthony Koo /** 3991e0958bbSAnthony Koo * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 400592a6318SAnthony Koo */ 401492dd8a8SAnthony Koo union dmub_fw_boot_options { 402492dd8a8SAnthony Koo struct { 403592a6318SAnthony Koo uint32_t pemu_env : 1; /**< 1 if PEMU */ 404592a6318SAnthony Koo uint32_t fpga_env : 1; /**< 1 if FPGA */ 405592a6318SAnthony Koo uint32_t optimized_init : 1; /**< 1 if optimized init */ 406592a6318SAnthony Koo uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 407592a6318SAnthony Koo uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 408592a6318SAnthony Koo uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 409b04cb192SNicholas Kazlauskas uint32_t z10_disable: 1; /**< 1 to disable z10 */ 410b0ce6272SMeenakshikumar Somasundaram uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 4111e0958bbSAnthony Koo uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 4123137f792SHansen uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 4133137f792SHansen uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 4143137f792SHansen /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 4153137f792SHansen uint32_t power_optimization: 1; 416b129c94eSAnthony Koo uint32_t diag_env: 1; /* 1 if diagnostic environment */ 4175cef7e8eSAnthony Koo uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 418ea5a4db9SAnthony Koo uint32_t usb4_cm_version: 1; /**< 1 CM support */ 4196f4f8ff5SMeenakshikumar Somasundaram uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 42073f73741SAnthony Koo uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */ 421c79503dcSAnthony Koo uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 422*27664177SAnthony Koo uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 423*27664177SAnthony Koo uint32_t reserved : 13; /**< reserved */ 424592a6318SAnthony Koo } bits; /**< boot bits */ 425592a6318SAnthony Koo uint32_t all; /**< 32-bit access to bits */ 426492dd8a8SAnthony Koo }; 427492dd8a8SAnthony Koo 428492dd8a8SAnthony Koo enum dmub_fw_boot_options_bit { 429592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 430592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 431592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 432492dd8a8SAnthony Koo }; 433492dd8a8SAnthony Koo 434788408b7SAnthony Koo //============================================================================== 435788408b7SAnthony Koo //</DMUB_STATUS>================================================================ 43684034ad4SAnthony Koo //============================================================================== 43784034ad4SAnthony Koo //< DMUB_VBIOS>================================================================= 43884034ad4SAnthony Koo //============================================================================== 43984034ad4SAnthony Koo 44084034ad4SAnthony Koo /* 441592a6318SAnthony Koo * enum dmub_cmd_vbios_type - VBIOS commands. 442592a6318SAnthony Koo * 44384034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 44484034ad4SAnthony Koo * Do not reuse or modify IDs. 44584034ad4SAnthony Koo */ 44684034ad4SAnthony Koo enum dmub_cmd_vbios_type { 447592a6318SAnthony Koo /** 448592a6318SAnthony Koo * Configures the DIG encoder. 449592a6318SAnthony Koo */ 45084034ad4SAnthony Koo DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 451592a6318SAnthony Koo /** 452592a6318SAnthony Koo * Controls the PHY. 453592a6318SAnthony Koo */ 45484034ad4SAnthony Koo DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 455592a6318SAnthony Koo /** 456592a6318SAnthony Koo * Sets the pixel clock/symbol clock. 457592a6318SAnthony Koo */ 45884034ad4SAnthony Koo DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 459592a6318SAnthony Koo /** 460592a6318SAnthony Koo * Enables or disables power gating. 461592a6318SAnthony Koo */ 46284034ad4SAnthony Koo DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 46341f91315SNicholas Kazlauskas /** 46441f91315SNicholas Kazlauskas * Controls embedded panels. 46541f91315SNicholas Kazlauskas */ 4662ac685bfSAnthony Koo DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 46741f91315SNicholas Kazlauskas /** 46841f91315SNicholas Kazlauskas * Query DP alt status on a transmitter. 46941f91315SNicholas Kazlauskas */ 47041f91315SNicholas Kazlauskas DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 471e383b127SNicholas Kazlauskas /** 472e383b127SNicholas Kazlauskas * Controls domain power gating 473e383b127SNicholas Kazlauskas */ 474e383b127SNicholas Kazlauskas DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 47584034ad4SAnthony Koo }; 47684034ad4SAnthony Koo 47784034ad4SAnthony Koo //============================================================================== 47884034ad4SAnthony Koo //</DMUB_VBIOS>================================================================= 47984034ad4SAnthony Koo //============================================================================== 48084034ad4SAnthony Koo //< DMUB_GPINT>================================================================= 48184034ad4SAnthony Koo //============================================================================== 48284034ad4SAnthony Koo 48384034ad4SAnthony Koo /** 48484034ad4SAnthony Koo * The shifts and masks below may alternatively be used to format and read 48584034ad4SAnthony Koo * the command register bits. 48684034ad4SAnthony Koo */ 48784034ad4SAnthony Koo 48884034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 48984034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_SHIFT 0 49084034ad4SAnthony Koo 49184034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 49284034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 49384034ad4SAnthony Koo 49484034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_MASK 0xF 49584034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_SHIFT 28 49684034ad4SAnthony Koo 49784034ad4SAnthony Koo /** 49884034ad4SAnthony Koo * Command responses. 49984034ad4SAnthony Koo */ 50084034ad4SAnthony Koo 501592a6318SAnthony Koo /** 502592a6318SAnthony Koo * Return response for DMUB_GPINT__STOP_FW command. 503592a6318SAnthony Koo */ 50484034ad4SAnthony Koo #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 50584034ad4SAnthony Koo 50684034ad4SAnthony Koo /** 507592a6318SAnthony Koo * union dmub_gpint_data_register - Format for sending a command via the GPINT. 50884034ad4SAnthony Koo */ 50984034ad4SAnthony Koo union dmub_gpint_data_register { 51084034ad4SAnthony Koo struct { 511592a6318SAnthony Koo uint32_t param : 16; /**< 16-bit parameter */ 512592a6318SAnthony Koo uint32_t command_code : 12; /**< GPINT command */ 513592a6318SAnthony Koo uint32_t status : 4; /**< Command status bit */ 514592a6318SAnthony Koo } bits; /**< GPINT bit access */ 515592a6318SAnthony Koo uint32_t all; /**< GPINT 32-bit access */ 51684034ad4SAnthony Koo }; 51784034ad4SAnthony Koo 51884034ad4SAnthony Koo /* 519592a6318SAnthony Koo * enum dmub_gpint_command - GPINT command to DMCUB FW 520592a6318SAnthony Koo * 52184034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 52284034ad4SAnthony Koo * Do not reuse or modify IDs. 52384034ad4SAnthony Koo */ 52484034ad4SAnthony Koo enum dmub_gpint_command { 525592a6318SAnthony Koo /** 526592a6318SAnthony Koo * Invalid command, ignored. 527592a6318SAnthony Koo */ 52884034ad4SAnthony Koo DMUB_GPINT__INVALID_COMMAND = 0, 529592a6318SAnthony Koo /** 530592a6318SAnthony Koo * DESC: Queries the firmware version. 531592a6318SAnthony Koo * RETURN: Firmware version. 532592a6318SAnthony Koo */ 53384034ad4SAnthony Koo DMUB_GPINT__GET_FW_VERSION = 1, 534592a6318SAnthony Koo /** 535592a6318SAnthony Koo * DESC: Halts the firmware. 536592a6318SAnthony Koo * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 537592a6318SAnthony Koo */ 53884034ad4SAnthony Koo DMUB_GPINT__STOP_FW = 2, 5391a595f28SAnthony Koo /** 5401a595f28SAnthony Koo * DESC: Get PSR state from FW. 5411a595f28SAnthony Koo * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 5421a595f28SAnthony Koo */ 54384034ad4SAnthony Koo DMUB_GPINT__GET_PSR_STATE = 7, 54480eba958SAnthony Koo /** 54580eba958SAnthony Koo * DESC: Notifies DMCUB of the currently active streams. 54680eba958SAnthony Koo * ARGS: Stream mask, 1 bit per active stream index. 54780eba958SAnthony Koo */ 54880eba958SAnthony Koo DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 5491a595f28SAnthony Koo /** 5501a595f28SAnthony Koo * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 5511a595f28SAnthony Koo * ARGS: We can measure residency from various points. The argument will specify the residency mode. 5521a595f28SAnthony Koo * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 5531a595f28SAnthony Koo * RETURN: PSR residency in milli-percent. 5541a595f28SAnthony Koo */ 555672251b2SAnthony Koo DMUB_GPINT__PSR_RESIDENCY = 9, 55601934c30SAnthony Koo 55701934c30SAnthony Koo /** 55801934c30SAnthony Koo * DESC: Notifies DMCUB detection is done so detection required can be cleared. 55901934c30SAnthony Koo */ 56001934c30SAnthony Koo DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 56184034ad4SAnthony Koo }; 56284034ad4SAnthony Koo 5630b51e7e8SAnthony Koo /** 5640b51e7e8SAnthony Koo * INBOX0 generic command definition 5650b51e7e8SAnthony Koo */ 5660b51e7e8SAnthony Koo union dmub_inbox0_cmd_common { 5670b51e7e8SAnthony Koo struct { 5680b51e7e8SAnthony Koo uint32_t command_code: 8; /**< INBOX0 command code */ 5690b51e7e8SAnthony Koo uint32_t param: 24; /**< 24-bit parameter */ 5700b51e7e8SAnthony Koo } bits; 5710b51e7e8SAnthony Koo uint32_t all; 5720b51e7e8SAnthony Koo }; 5730b51e7e8SAnthony Koo 5740b51e7e8SAnthony Koo /** 5750b51e7e8SAnthony Koo * INBOX0 hw_lock command definition 5760b51e7e8SAnthony Koo */ 5770b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw { 5780b51e7e8SAnthony Koo struct { 5790b51e7e8SAnthony Koo uint32_t command_code: 8; 5800b51e7e8SAnthony Koo 5810b51e7e8SAnthony Koo /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 5822412d339SAnthony Koo uint32_t hw_lock_client: 2; 5830b51e7e8SAnthony Koo 5840b51e7e8SAnthony Koo /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 5850b51e7e8SAnthony Koo uint32_t otg_inst: 3; 5860b51e7e8SAnthony Koo uint32_t opp_inst: 3; 5870b51e7e8SAnthony Koo uint32_t dig_inst: 3; 5880b51e7e8SAnthony Koo 5890b51e7e8SAnthony Koo /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 5900b51e7e8SAnthony Koo uint32_t lock_pipe: 1; 5910b51e7e8SAnthony Koo uint32_t lock_cursor: 1; 5920b51e7e8SAnthony Koo uint32_t lock_dig: 1; 5930b51e7e8SAnthony Koo uint32_t triple_buffer_lock: 1; 5940b51e7e8SAnthony Koo 5950b51e7e8SAnthony Koo uint32_t lock: 1; /**< Lock */ 5960b51e7e8SAnthony Koo uint32_t should_release: 1; /**< Release */ 5972412d339SAnthony Koo uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 5980b51e7e8SAnthony Koo } bits; 5990b51e7e8SAnthony Koo uint32_t all; 6000b51e7e8SAnthony Koo }; 6010b51e7e8SAnthony Koo 6020b51e7e8SAnthony Koo union dmub_inbox0_data_register { 6030b51e7e8SAnthony Koo union dmub_inbox0_cmd_common inbox0_cmd_common; 6040b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 6050b51e7e8SAnthony Koo }; 6060b51e7e8SAnthony Koo 6070b51e7e8SAnthony Koo enum dmub_inbox0_command { 6080b51e7e8SAnthony Koo /** 6090b51e7e8SAnthony Koo * DESC: Invalid command, ignored. 6100b51e7e8SAnthony Koo */ 6110b51e7e8SAnthony Koo DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 6120b51e7e8SAnthony Koo /** 6130b51e7e8SAnthony Koo * DESC: Notification to acquire/release HW lock 6140b51e7e8SAnthony Koo * ARGS: 6150b51e7e8SAnthony Koo */ 6160b51e7e8SAnthony Koo DMUB_INBOX0_CMD__HW_LOCK = 1, 6170b51e7e8SAnthony Koo }; 61884034ad4SAnthony Koo //============================================================================== 61984034ad4SAnthony Koo //</DMUB_GPINT>================================================================= 62084034ad4SAnthony Koo //============================================================================== 62184034ad4SAnthony Koo //< DMUB_CMD>=================================================================== 62284034ad4SAnthony Koo //============================================================================== 62384034ad4SAnthony Koo 624592a6318SAnthony Koo /** 625592a6318SAnthony Koo * Size in bytes of each DMUB command. 626592a6318SAnthony Koo */ 6277c008829SNicholas Kazlauskas #define DMUB_RB_CMD_SIZE 64 628592a6318SAnthony Koo 629592a6318SAnthony Koo /** 630592a6318SAnthony Koo * Maximum number of items in the DMUB ringbuffer. 631592a6318SAnthony Koo */ 6327c008829SNicholas Kazlauskas #define DMUB_RB_MAX_ENTRY 128 633592a6318SAnthony Koo 634592a6318SAnthony Koo /** 635592a6318SAnthony Koo * Ringbuffer size in bytes. 636592a6318SAnthony Koo */ 6377c008829SNicholas Kazlauskas #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 638592a6318SAnthony Koo 639592a6318SAnthony Koo /** 640592a6318SAnthony Koo * REG_SET mask for reg offload. 641592a6318SAnthony Koo */ 6427c008829SNicholas Kazlauskas #define REG_SET_MASK 0xFFFF 6437c008829SNicholas Kazlauskas 644d4bbcecbSNicholas Kazlauskas /* 645592a6318SAnthony Koo * enum dmub_cmd_type - DMUB inbox command. 646592a6318SAnthony Koo * 647d4bbcecbSNicholas Kazlauskas * Command IDs should be treated as stable ABI. 648d4bbcecbSNicholas Kazlauskas * Do not reuse or modify IDs. 649d4bbcecbSNicholas Kazlauskas */ 650d4bbcecbSNicholas Kazlauskas enum dmub_cmd_type { 651592a6318SAnthony Koo /** 652592a6318SAnthony Koo * Invalid command. 653592a6318SAnthony Koo */ 654d4bbcecbSNicholas Kazlauskas DMUB_CMD__NULL = 0, 655592a6318SAnthony Koo /** 656592a6318SAnthony Koo * Read modify write register sequence offload. 657592a6318SAnthony Koo */ 658d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 659592a6318SAnthony Koo /** 660592a6318SAnthony Koo * Field update register sequence offload. 661592a6318SAnthony Koo */ 662d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 663592a6318SAnthony Koo /** 664592a6318SAnthony Koo * Burst write sequence offload. 665592a6318SAnthony Koo */ 666d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 667592a6318SAnthony Koo /** 668592a6318SAnthony Koo * Reg wait sequence offload. 669592a6318SAnthony Koo */ 670d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_REG_WAIT = 4, 671592a6318SAnthony Koo /** 672592a6318SAnthony Koo * Workaround to avoid HUBP underflow during NV12 playback. 673592a6318SAnthony Koo */ 674bae9c49bSYongqiang Sun DMUB_CMD__PLAT_54186_WA = 5, 6751a595f28SAnthony Koo /** 6761a595f28SAnthony Koo * Command type used to query FW feature caps. 6771a595f28SAnthony Koo */ 67834ba432cSAnthony Koo DMUB_CMD__QUERY_FEATURE_CAPS = 6, 6791a595f28SAnthony Koo /** 680b09c1fffSLeo (Hanghong) Ma * Command type used to get visual confirm color. 681b09c1fffSLeo (Hanghong) Ma */ 682b09c1fffSLeo (Hanghong) Ma DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 683b09c1fffSLeo (Hanghong) Ma /** 6841a595f28SAnthony Koo * Command type used for all PSR commands. 6851a595f28SAnthony Koo */ 686d4bbcecbSNicholas Kazlauskas DMUB_CMD__PSR = 64, 687592a6318SAnthony Koo /** 688592a6318SAnthony Koo * Command type used for all MALL commands. 689592a6318SAnthony Koo */ 69052f2e83eSBhawanpreet Lakha DMUB_CMD__MALL = 65, 6911a595f28SAnthony Koo /** 6921a595f28SAnthony Koo * Command type used for all ABM commands. 6931a595f28SAnthony Koo */ 694e6ea8c34SWyatt Wood DMUB_CMD__ABM = 66, 6951a595f28SAnthony Koo /** 69683eb5385SDavid Zhang * Command type used to update dirty rects in FW. 69783eb5385SDavid Zhang */ 69883eb5385SDavid Zhang DMUB_CMD__UPDATE_DIRTY_RECT = 67, 69983eb5385SDavid Zhang /** 70083eb5385SDavid Zhang * Command type used to update cursor info in FW. 70183eb5385SDavid Zhang */ 70283eb5385SDavid Zhang DMUB_CMD__UPDATE_CURSOR_INFO = 68, 70383eb5385SDavid Zhang /** 7041a595f28SAnthony Koo * Command type used for HW locking in FW. 7051a595f28SAnthony Koo */ 706788408b7SAnthony Koo DMUB_CMD__HW_LOCK = 69, 7071a595f28SAnthony Koo /** 7081a595f28SAnthony Koo * Command type used to access DP AUX. 7091a595f28SAnthony Koo */ 710d9beecfcSAnthony Koo DMUB_CMD__DP_AUX_ACCESS = 70, 7111a595f28SAnthony Koo /** 7121a595f28SAnthony Koo * Command type used for OUTBOX1 notification enable 7131a595f28SAnthony Koo */ 714d9beecfcSAnthony Koo DMUB_CMD__OUTBOX1_ENABLE = 71, 7155cef7e8eSAnthony Koo 716b04cb192SNicholas Kazlauskas /** 717b04cb192SNicholas Kazlauskas * Command type used for all idle optimization commands. 718b04cb192SNicholas Kazlauskas */ 719b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT = 72, 720b04cb192SNicholas Kazlauskas /** 721b04cb192SNicholas Kazlauskas * Command type used for all clock manager commands. 722b04cb192SNicholas Kazlauskas */ 723b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR = 73, 724b04cb192SNicholas Kazlauskas /** 725b04cb192SNicholas Kazlauskas * Command type used for all panel control commands. 726b04cb192SNicholas Kazlauskas */ 727b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL = 74, 728ac2e555eSAurabindo Pillai /** 729ac2e555eSAurabindo Pillai * Command type used for <TODO:description> 730ac2e555eSAurabindo Pillai */ 731ac2e555eSAurabindo Pillai DMUB_CMD__CAB_FOR_SS = 75, 73285f4bc0cSAlvin Lee 73385f4bc0cSAlvin Lee DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 73485f4bc0cSAlvin Lee 735592a6318SAnthony Koo /** 73676724b76SJimmy Kizito * Command type used for interfacing with DPIA. 73776724b76SJimmy Kizito */ 73876724b76SJimmy Kizito DMUB_CMD__DPIA = 77, 73976724b76SJimmy Kizito /** 740021eaef8SAnthony Koo * Command type used for EDID CEA parsing 741021eaef8SAnthony Koo */ 742021eaef8SAnthony Koo DMUB_CMD__EDID_CEA = 79, 743021eaef8SAnthony Koo /** 744c595fb05SWenjing Liu * Command type used for getting usbc cable ID 745c595fb05SWenjing Liu */ 746c595fb05SWenjing Liu DMUB_CMD_GET_USBC_CABLE_ID = 81, 747c595fb05SWenjing Liu /** 748ea5a4db9SAnthony Koo * Command type used to query HPD state. 749ea5a4db9SAnthony Koo */ 750ea5a4db9SAnthony Koo DMUB_CMD__QUERY_HPD_STATE = 82, 751ea5a4db9SAnthony Koo /** 752592a6318SAnthony Koo * Command type used for all VBIOS interface commands. 753592a6318SAnthony Koo */ 7541fb695d9SAnthony Koo 755c0459bddSAlan Liu /** 756c0459bddSAlan Liu * Command type used for all SECURE_DISPLAY commands. 757c0459bddSAlan Liu */ 758c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY = 85, 7596f4f8ff5SMeenakshikumar Somasundaram 7606f4f8ff5SMeenakshikumar Somasundaram /** 7616f4f8ff5SMeenakshikumar Somasundaram * Command type used to set DPIA HPD interrupt state 7626f4f8ff5SMeenakshikumar Somasundaram */ 7636f4f8ff5SMeenakshikumar Somasundaram DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 7646f4f8ff5SMeenakshikumar Somasundaram 765d4bbcecbSNicholas Kazlauskas DMUB_CMD__VBIOS = 128, 7667c008829SNicholas Kazlauskas }; 7677c008829SNicholas Kazlauskas 768592a6318SAnthony Koo /** 769592a6318SAnthony Koo * enum dmub_out_cmd_type - DMUB outbox commands. 770592a6318SAnthony Koo */ 7713b37260bSAnthony Koo enum dmub_out_cmd_type { 772592a6318SAnthony Koo /** 773592a6318SAnthony Koo * Invalid outbox command, ignored. 774592a6318SAnthony Koo */ 7753b37260bSAnthony Koo DMUB_OUT_CMD__NULL = 0, 7761a595f28SAnthony Koo /** 7771a595f28SAnthony Koo * Command type used for DP AUX Reply data notification 7781a595f28SAnthony Koo */ 779d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_AUX_REPLY = 1, 780892b74a6SMeenakshikumar Somasundaram /** 781892b74a6SMeenakshikumar Somasundaram * Command type used for DP HPD event notification 782892b74a6SMeenakshikumar Somasundaram */ 783892b74a6SMeenakshikumar Somasundaram DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 78471af9d46SMeenakshikumar Somasundaram /** 78571af9d46SMeenakshikumar Somasundaram * Command type used for SET_CONFIG Reply notification 78671af9d46SMeenakshikumar Somasundaram */ 78771af9d46SMeenakshikumar Somasundaram DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 7888af54c61SMustapha Ghaddar /** 7898af54c61SMustapha Ghaddar * Command type used for USB4 DPIA notification 7908af54c61SMustapha Ghaddar */ 7918af54c61SMustapha Ghaddar DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 7923b37260bSAnthony Koo }; 7933b37260bSAnthony Koo 79476724b76SJimmy Kizito /* DMUB_CMD__DPIA command sub-types. */ 79576724b76SJimmy Kizito enum dmub_cmd_dpia_type { 79676724b76SJimmy Kizito DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 79771af9d46SMeenakshikumar Somasundaram DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 798139a3311SMeenakshikumar Somasundaram DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 79976724b76SJimmy Kizito }; 80076724b76SJimmy Kizito 8018af54c61SMustapha Ghaddar /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 8028af54c61SMustapha Ghaddar enum dmub_cmd_dpia_notification_type { 8038af54c61SMustapha Ghaddar DPIA_NOTIFY__BW_ALLOCATION = 0, 8048af54c61SMustapha Ghaddar }; 8058af54c61SMustapha Ghaddar 8067c008829SNicholas Kazlauskas #pragma pack(push, 1) 8077c008829SNicholas Kazlauskas 808592a6318SAnthony Koo /** 809592a6318SAnthony Koo * struct dmub_cmd_header - Common command header fields. 810592a6318SAnthony Koo */ 8117c008829SNicholas Kazlauskas struct dmub_cmd_header { 812592a6318SAnthony Koo unsigned int type : 8; /**< command type */ 813592a6318SAnthony Koo unsigned int sub_type : 8; /**< command sub type */ 814592a6318SAnthony Koo unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 8150b51e7e8SAnthony Koo unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 8160b51e7e8SAnthony Koo unsigned int reserved0 : 6; /**< reserved bits */ 817592a6318SAnthony Koo unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 818592a6318SAnthony Koo unsigned int reserved1 : 2; /**< reserved bits */ 8197c008829SNicholas Kazlauskas }; 8207c008829SNicholas Kazlauskas 8217c008829SNicholas Kazlauskas /* 822592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write 8237c008829SNicholas Kazlauskas * 8247c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 5 sets of read modify writes, 8257c008829SNicholas Kazlauskas * each take 3 dwords. 8267c008829SNicholas Kazlauskas * 8277c008829SNicholas Kazlauskas * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 8287c008829SNicholas Kazlauskas * 8297c008829SNicholas Kazlauskas * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 8307c008829SNicholas Kazlauskas * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 8317c008829SNicholas Kazlauskas */ 8327c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence { 833592a6318SAnthony Koo uint32_t addr; /**< register address */ 834592a6318SAnthony Koo uint32_t modify_mask; /**< modify mask */ 835592a6318SAnthony Koo uint32_t modify_value; /**< modify value */ 8367c008829SNicholas Kazlauskas }; 8377c008829SNicholas Kazlauskas 838592a6318SAnthony Koo /** 839592a6318SAnthony Koo * Maximum number of ops in read modify write sequence. 840592a6318SAnthony Koo */ 8417c008829SNicholas Kazlauskas #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 842592a6318SAnthony Koo 843592a6318SAnthony Koo /** 844592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 845592a6318SAnthony Koo */ 8467c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write { 847592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 848592a6318SAnthony Koo /** 849592a6318SAnthony Koo * Read modify write sequence. 850592a6318SAnthony Koo */ 8517c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 8527c008829SNicholas Kazlauskas }; 8537c008829SNicholas Kazlauskas 8547c008829SNicholas Kazlauskas /* 8557c008829SNicholas Kazlauskas * Update a register with specified masks and values sequeunce 8567c008829SNicholas Kazlauskas * 8577c008829SNicholas Kazlauskas * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 8587c008829SNicholas Kazlauskas * 8597c008829SNicholas Kazlauskas * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 8607c008829SNicholas Kazlauskas * 8617c008829SNicholas Kazlauskas * 8627c008829SNicholas Kazlauskas * USE CASE: 8637c008829SNicholas Kazlauskas * 1. auto-increment register where additional read would update pointer and produce wrong result 8647c008829SNicholas Kazlauskas * 2. toggle a bit without read in the middle 8657c008829SNicholas Kazlauskas */ 8667c008829SNicholas Kazlauskas 8677c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence { 868592a6318SAnthony Koo uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 869592a6318SAnthony Koo uint32_t modify_value; /**< value to update with */ 8707c008829SNicholas Kazlauskas }; 8717c008829SNicholas Kazlauskas 872592a6318SAnthony Koo /** 873592a6318SAnthony Koo * Maximum number of ops in field update sequence. 874592a6318SAnthony Koo */ 8757c008829SNicholas Kazlauskas #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 876592a6318SAnthony Koo 877592a6318SAnthony Koo /** 878592a6318SAnthony Koo * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 879592a6318SAnthony Koo */ 8807c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence { 881592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 882592a6318SAnthony Koo uint32_t addr; /**< register address */ 883592a6318SAnthony Koo /** 884592a6318SAnthony Koo * Field update sequence. 885592a6318SAnthony Koo */ 8867c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 8877c008829SNicholas Kazlauskas }; 8887c008829SNicholas Kazlauskas 889592a6318SAnthony Koo 890592a6318SAnthony Koo /** 891592a6318SAnthony Koo * Maximum number of burst write values. 892592a6318SAnthony Koo */ 893592a6318SAnthony Koo #define DMUB_BURST_WRITE_VALUES__MAX 14 894592a6318SAnthony Koo 8957c008829SNicholas Kazlauskas /* 896592a6318SAnthony Koo * struct dmub_rb_cmd_burst_write - Burst write 8977c008829SNicholas Kazlauskas * 8987c008829SNicholas Kazlauskas * support use case such as writing out LUTs. 8997c008829SNicholas Kazlauskas * 9007c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 14 values to write to given address 9017c008829SNicholas Kazlauskas * 9027c008829SNicholas Kazlauskas * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 9037c008829SNicholas Kazlauskas */ 9047c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write { 905592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 906592a6318SAnthony Koo uint32_t addr; /**< register start address */ 907592a6318SAnthony Koo /** 908592a6318SAnthony Koo * Burst write register values. 909592a6318SAnthony Koo */ 9107c008829SNicholas Kazlauskas uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 9117c008829SNicholas Kazlauskas }; 9127c008829SNicholas Kazlauskas 913592a6318SAnthony Koo /** 914592a6318SAnthony Koo * struct dmub_rb_cmd_common - Common command header 915592a6318SAnthony Koo */ 9167c008829SNicholas Kazlauskas struct dmub_rb_cmd_common { 917592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 918592a6318SAnthony Koo /** 919592a6318SAnthony Koo * Padding to RB_CMD_SIZE 920592a6318SAnthony Koo */ 9217c008829SNicholas Kazlauskas uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 9227c008829SNicholas Kazlauskas }; 9237c008829SNicholas Kazlauskas 924592a6318SAnthony Koo /** 925592a6318SAnthony Koo * struct dmub_cmd_reg_wait_data - Register wait data 926592a6318SAnthony Koo */ 9277c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data { 928592a6318SAnthony Koo uint32_t addr; /**< Register address */ 929592a6318SAnthony Koo uint32_t mask; /**< Mask for register bits */ 930592a6318SAnthony Koo uint32_t condition_field_value; /**< Value to wait for */ 931592a6318SAnthony Koo uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 9327c008829SNicholas Kazlauskas }; 9337c008829SNicholas Kazlauskas 934592a6318SAnthony Koo /** 935592a6318SAnthony Koo * struct dmub_rb_cmd_reg_wait - Register wait command 936592a6318SAnthony Koo */ 9377c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait { 938592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 939592a6318SAnthony Koo struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 9407c008829SNicholas Kazlauskas }; 9417c008829SNicholas Kazlauskas 942592a6318SAnthony Koo /** 943592a6318SAnthony Koo * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 944592a6318SAnthony Koo * 945592a6318SAnthony Koo * Reprograms surface parameters to avoid underflow. 946592a6318SAnthony Koo */ 947bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa { 948592a6318SAnthony Koo uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 949592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 950592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 951592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 952592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 95322aa5614SYongqiang Sun struct { 954592a6318SAnthony Koo uint8_t hubp_inst : 4; /**< HUBP instance */ 955592a6318SAnthony Koo uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 956592a6318SAnthony Koo uint8_t immediate :1; /**< Immediate flip */ 957592a6318SAnthony Koo uint8_t vmid : 4; /**< VMID */ 958592a6318SAnthony Koo uint8_t grph_stereo : 1; /**< 1 if stereo */ 959592a6318SAnthony Koo uint32_t reserved : 21; /**< Reserved */ 960592a6318SAnthony Koo } flip_params; /**< Pageflip parameters */ 961d2994b25SAyush Gupta uint32_t reserved[9]; /**< Reserved bits */ 9628c019253SYongqiang Sun }; 9638c019253SYongqiang Sun 964592a6318SAnthony Koo /** 965592a6318SAnthony Koo * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 966592a6318SAnthony Koo */ 967bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa { 968592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 969592a6318SAnthony Koo struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 9708c019253SYongqiang Sun }; 9718c019253SYongqiang Sun 972592a6318SAnthony Koo /** 973592a6318SAnthony Koo * struct dmub_rb_cmd_mall - MALL command data. 974592a6318SAnthony Koo */ 97552f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall { 976592a6318SAnthony Koo struct dmub_cmd_header header; /**< Common command header */ 977592a6318SAnthony Koo union dmub_addr cursor_copy_src; /**< Cursor copy address */ 978592a6318SAnthony Koo union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 979592a6318SAnthony Koo uint32_t tmr_delay; /**< Timer delay */ 980592a6318SAnthony Koo uint32_t tmr_scale; /**< Timer scale */ 981592a6318SAnthony Koo uint16_t cursor_width; /**< Cursor width in pixels */ 982592a6318SAnthony Koo uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 983592a6318SAnthony Koo uint16_t cursor_height; /**< Cursor height in pixels */ 984592a6318SAnthony Koo uint8_t cursor_bpp; /**< Cursor bits per pixel */ 985592a6318SAnthony Koo uint8_t debug_bits; /**< Debug bits */ 986ea7154d8SBhawanpreet Lakha 987592a6318SAnthony Koo uint8_t reserved1; /**< Reserved bits */ 988592a6318SAnthony Koo uint8_t reserved2; /**< Reserved bits */ 98952f2e83eSBhawanpreet Lakha }; 99052f2e83eSBhawanpreet Lakha 991b04cb192SNicholas Kazlauskas /** 992ac2e555eSAurabindo Pillai * enum dmub_cmd_cab_type - TODO: 993ac2e555eSAurabindo Pillai */ 994ac2e555eSAurabindo Pillai enum dmub_cmd_cab_type { 995ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 996ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_DCN_REQ = 1, 997ac2e555eSAurabindo Pillai DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 998ac2e555eSAurabindo Pillai }; 999ac2e555eSAurabindo Pillai 1000ac2e555eSAurabindo Pillai /** 1001ac2e555eSAurabindo Pillai * struct dmub_rb_cmd_cab_for_ss - TODO: 1002ac2e555eSAurabindo Pillai */ 1003ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss { 1004ac2e555eSAurabindo Pillai struct dmub_cmd_header header; 1005ac2e555eSAurabindo Pillai uint8_t cab_alloc_ways; /* total number of ways */ 1006ac2e555eSAurabindo Pillai uint8_t debug_bits; /* debug bits */ 1007ac2e555eSAurabindo Pillai }; 100885f4bc0cSAlvin Lee 100985f4bc0cSAlvin Lee enum mclk_switch_mode { 101085f4bc0cSAlvin Lee NONE = 0, 101185f4bc0cSAlvin Lee FPO = 1, 101285f4bc0cSAlvin Lee SUBVP = 2, 101385f4bc0cSAlvin Lee VBLANK = 3, 101485f4bc0cSAlvin Lee }; 101585f4bc0cSAlvin Lee 101685f4bc0cSAlvin Lee /* Per pipe struct which stores the MCLK switch mode 101785f4bc0cSAlvin Lee * data to be sent to DMUB. 101885f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 101985f4bc0cSAlvin Lee * the type name can be updated 102085f4bc0cSAlvin Lee */ 102185f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 102285f4bc0cSAlvin Lee union { 102385f4bc0cSAlvin Lee struct { 102485f4bc0cSAlvin Lee uint32_t pix_clk_100hz; 102585f4bc0cSAlvin Lee uint16_t main_vblank_start; 102685f4bc0cSAlvin Lee uint16_t main_vblank_end; 102785f4bc0cSAlvin Lee uint16_t mall_region_lines; 102885f4bc0cSAlvin Lee uint16_t prefetch_lines; 102985f4bc0cSAlvin Lee uint16_t prefetch_to_mall_start_lines; 103085f4bc0cSAlvin Lee uint16_t processing_delay_lines; 103185f4bc0cSAlvin Lee uint16_t htotal; // required to calculate line time for multi-display cases 103285f4bc0cSAlvin Lee uint16_t vtotal; 103385f4bc0cSAlvin Lee uint8_t main_pipe_index; 103485f4bc0cSAlvin Lee uint8_t phantom_pipe_index; 10350acc5b06SAnthony Koo /* Since the microschedule is calculated in terms of OTG lines, 10360acc5b06SAnthony Koo * include any scaling factors to make sure when we get accurate 10370acc5b06SAnthony Koo * conversion when programming MALL_START_LINE (which is in terms 10380acc5b06SAnthony Koo * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 10390acc5b06SAnthony Koo * is 1/2 (numerator = 1, denominator = 2). 10400acc5b06SAnthony Koo */ 10410acc5b06SAnthony Koo uint8_t scale_factor_numerator; 10420acc5b06SAnthony Koo uint8_t scale_factor_denominator; 104381f776b6SAnthony Koo uint8_t is_drr; 10441591a647SAnthony Koo uint8_t main_split_pipe_index; 10451591a647SAnthony Koo uint8_t phantom_split_pipe_index; 104685f4bc0cSAlvin Lee } subvp_data; 104785f4bc0cSAlvin Lee 104885f4bc0cSAlvin Lee struct { 104985f4bc0cSAlvin Lee uint32_t pix_clk_100hz; 105085f4bc0cSAlvin Lee uint16_t vblank_start; 105185f4bc0cSAlvin Lee uint16_t vblank_end; 105285f4bc0cSAlvin Lee uint16_t vstartup_start; 105385f4bc0cSAlvin Lee uint16_t vtotal; 105485f4bc0cSAlvin Lee uint16_t htotal; 105585f4bc0cSAlvin Lee uint8_t vblank_pipe_index; 1056ae7169a9SAlvin Lee uint8_t padding[1]; 105785f4bc0cSAlvin Lee struct { 105885f4bc0cSAlvin Lee uint8_t drr_in_use; 105985f4bc0cSAlvin Lee uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 106085f4bc0cSAlvin Lee uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 106185f4bc0cSAlvin Lee uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 106285f4bc0cSAlvin Lee uint8_t use_ramping; // Use ramping or not 1063ae7169a9SAlvin Lee uint8_t drr_vblank_start_margin; 106485f4bc0cSAlvin Lee } drr_info; // DRR considered as part of SubVP + VBLANK case 106585f4bc0cSAlvin Lee } vblank_data; 106685f4bc0cSAlvin Lee } pipe_config; 106785f4bc0cSAlvin Lee 10680acc5b06SAnthony Koo /* - subvp_data in the union (pipe_config) takes up 27 bytes. 10690acc5b06SAnthony Koo * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 10700acc5b06SAnthony Koo * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 10710acc5b06SAnthony Koo */ 10720acc5b06SAnthony Koo uint8_t mode; // enum mclk_switch_mode 107385f4bc0cSAlvin Lee }; 107485f4bc0cSAlvin Lee 107585f4bc0cSAlvin Lee /** 107685f4bc0cSAlvin Lee * Config data for Sub-VP and FPO 107785f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 107885f4bc0cSAlvin Lee * the type name can be updated 107985f4bc0cSAlvin Lee */ 108085f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 108185f4bc0cSAlvin Lee uint16_t watermark_a_cache; 108285f4bc0cSAlvin Lee uint8_t vertical_int_margin_us; 108385f4bc0cSAlvin Lee uint8_t pstate_allow_width_us; 108485f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 108585f4bc0cSAlvin Lee }; 108685f4bc0cSAlvin Lee 108785f4bc0cSAlvin Lee /** 108885f4bc0cSAlvin Lee * DMUB rb command definition for Sub-VP and FPO 108985f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 109085f4bc0cSAlvin Lee * the type name can be updated 109185f4bc0cSAlvin Lee */ 109285f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 109385f4bc0cSAlvin Lee struct dmub_cmd_header header; 109485f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 109585f4bc0cSAlvin Lee }; 109685f4bc0cSAlvin Lee 1097ac2e555eSAurabindo Pillai /** 1098b04cb192SNicholas Kazlauskas * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1099b04cb192SNicholas Kazlauskas */ 1100b04cb192SNicholas Kazlauskas enum dmub_cmd_idle_opt_type { 1101b04cb192SNicholas Kazlauskas /** 1102b04cb192SNicholas Kazlauskas * DCN hardware restore. 1103b04cb192SNicholas Kazlauskas */ 1104b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1105f586fea8SJake Wang 1106f586fea8SJake Wang /** 1107f586fea8SJake Wang * DCN hardware save. 1108f586fea8SJake Wang */ 11099dce8c2aSAnthony Koo DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 11109dce8c2aSAnthony Koo 11119dce8c2aSAnthony Koo /** 11129dce8c2aSAnthony Koo * DCN hardware notify idle. 11139dce8c2aSAnthony Koo */ 11149dce8c2aSAnthony Koo DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1115b04cb192SNicholas Kazlauskas }; 1116b04cb192SNicholas Kazlauskas 1117b04cb192SNicholas Kazlauskas /** 1118b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1119b04cb192SNicholas Kazlauskas */ 1120b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore { 1121b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1122b04cb192SNicholas Kazlauskas }; 1123b04cb192SNicholas Kazlauskas 1124b04cb192SNicholas Kazlauskas /** 11259dce8c2aSAnthony Koo * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 11269dce8c2aSAnthony Koo */ 11279dce8c2aSAnthony Koo struct dmub_dcn_notify_idle_cntl_data { 11289dce8c2aSAnthony Koo uint8_t driver_idle; 11299dce8c2aSAnthony Koo uint8_t pad[1]; 11309dce8c2aSAnthony Koo }; 11319dce8c2aSAnthony Koo 11329dce8c2aSAnthony Koo /** 11339dce8c2aSAnthony Koo * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 11349dce8c2aSAnthony Koo */ 11359dce8c2aSAnthony Koo struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 11369dce8c2aSAnthony Koo struct dmub_cmd_header header; /**< header */ 11379dce8c2aSAnthony Koo struct dmub_dcn_notify_idle_cntl_data cntl_data; 11389dce8c2aSAnthony Koo }; 11399dce8c2aSAnthony Koo 11409dce8c2aSAnthony Koo /** 1141b04cb192SNicholas Kazlauskas * struct dmub_clocks - Clock update notification. 1142b04cb192SNicholas Kazlauskas */ 1143b04cb192SNicholas Kazlauskas struct dmub_clocks { 1144b04cb192SNicholas Kazlauskas uint32_t dispclk_khz; /**< dispclk kHz */ 1145b04cb192SNicholas Kazlauskas uint32_t dppclk_khz; /**< dppclk kHz */ 1146b04cb192SNicholas Kazlauskas uint32_t dcfclk_khz; /**< dcfclk kHz */ 1147b04cb192SNicholas Kazlauskas uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1148b04cb192SNicholas Kazlauskas }; 1149b04cb192SNicholas Kazlauskas 1150b04cb192SNicholas Kazlauskas /** 1151b04cb192SNicholas Kazlauskas * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1152b04cb192SNicholas Kazlauskas */ 1153b04cb192SNicholas Kazlauskas enum dmub_cmd_clk_mgr_type { 1154b04cb192SNicholas Kazlauskas /** 1155b04cb192SNicholas Kazlauskas * Notify DMCUB of clock update. 1156b04cb192SNicholas Kazlauskas */ 1157b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1158b04cb192SNicholas Kazlauskas }; 1159b04cb192SNicholas Kazlauskas 1160b04cb192SNicholas Kazlauskas /** 1161b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1162b04cb192SNicholas Kazlauskas */ 1163b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks { 1164b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1165b04cb192SNicholas Kazlauskas struct dmub_clocks clocks; /**< clock data */ 1166b04cb192SNicholas Kazlauskas }; 11678fe44c08SAlex Deucher 1168592a6318SAnthony Koo /** 1169592a6318SAnthony Koo * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1170592a6318SAnthony Koo */ 11717c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data { 1172592a6318SAnthony Koo union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 11737c008829SNicholas Kazlauskas }; 11747c008829SNicholas Kazlauskas 1175592a6318SAnthony Koo /** 1176592a6318SAnthony Koo * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1177592a6318SAnthony Koo */ 11787c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control { 1179592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1180592a6318SAnthony Koo struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 11817c008829SNicholas Kazlauskas }; 11827c008829SNicholas Kazlauskas 1183592a6318SAnthony Koo /** 1184592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1185592a6318SAnthony Koo */ 11867c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data { 1187592a6318SAnthony Koo struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 11887c008829SNicholas Kazlauskas }; 11897c008829SNicholas Kazlauskas 1190592a6318SAnthony Koo /** 1191592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1192592a6318SAnthony Koo */ 11937c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock { 1194592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1195592a6318SAnthony Koo struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 11967c008829SNicholas Kazlauskas }; 11977c008829SNicholas Kazlauskas 1198592a6318SAnthony Koo /** 1199592a6318SAnthony Koo * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1200592a6318SAnthony Koo */ 12017c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data { 1202592a6318SAnthony Koo struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 12037c008829SNicholas Kazlauskas }; 12047c008829SNicholas Kazlauskas 1205592a6318SAnthony Koo /** 1206592a6318SAnthony Koo * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1207592a6318SAnthony Koo */ 12087c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating { 1209592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1210592a6318SAnthony Koo struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 12117c008829SNicholas Kazlauskas }; 12127c008829SNicholas Kazlauskas 1213592a6318SAnthony Koo /** 1214592a6318SAnthony Koo * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1215592a6318SAnthony Koo */ 1216d448521eSAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 { 1217d448521eSAnthony Koo uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1218d448521eSAnthony Koo uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1219d448521eSAnthony Koo union { 1220d448521eSAnthony Koo uint8_t digmode; /**< enum atom_encode_mode_def */ 1221d448521eSAnthony Koo uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1222d448521eSAnthony Koo } mode_laneset; 1223d448521eSAnthony Koo uint8_t lanenum; /**< Number of lanes */ 1224d448521eSAnthony Koo union { 1225d448521eSAnthony Koo uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1226d448521eSAnthony Koo } symclk_units; 1227d448521eSAnthony Koo uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1228d448521eSAnthony Koo uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1229d448521eSAnthony Koo uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 12305a2730fcSFangzhi Zuo uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1231d448521eSAnthony Koo uint8_t reserved1; /**< For future use */ 1232d448521eSAnthony Koo uint8_t reserved2[3]; /**< For future use */ 1233d448521eSAnthony Koo uint32_t reserved3[11]; /**< For future use */ 1234d448521eSAnthony Koo }; 1235d448521eSAnthony Koo 1236592a6318SAnthony Koo /** 1237592a6318SAnthony Koo * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1238592a6318SAnthony Koo */ 1239d448521eSAnthony Koo union dmub_cmd_dig1_transmitter_control_data { 1240592a6318SAnthony Koo struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1241592a6318SAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 12427c008829SNicholas Kazlauskas }; 12437c008829SNicholas Kazlauskas 1244592a6318SAnthony Koo /** 1245592a6318SAnthony Koo * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1246592a6318SAnthony Koo */ 12477c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control { 1248592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1249592a6318SAnthony Koo union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 12507c008829SNicholas Kazlauskas }; 12517c008829SNicholas Kazlauskas 1252592a6318SAnthony Koo /** 1253e383b127SNicholas Kazlauskas * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1254e383b127SNicholas Kazlauskas */ 1255e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control_data { 1256e383b127SNicholas Kazlauskas uint8_t inst : 6; /**< DOMAIN instance to control */ 1257e383b127SNicholas Kazlauskas uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1258e383b127SNicholas Kazlauskas uint8_t reserved[3]; /**< Reserved for future use */ 1259e383b127SNicholas Kazlauskas }; 1260e383b127SNicholas Kazlauskas 1261e383b127SNicholas Kazlauskas /** 1262e383b127SNicholas Kazlauskas * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1263e383b127SNicholas Kazlauskas */ 1264e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control { 1265e383b127SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1266e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1267e383b127SNicholas Kazlauskas }; 1268e383b127SNicholas Kazlauskas 1269e383b127SNicholas Kazlauskas /** 127076724b76SJimmy Kizito * DPIA tunnel command parameters. 127176724b76SJimmy Kizito */ 127276724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data { 127376724b76SJimmy Kizito uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 127476724b76SJimmy Kizito uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 127576724b76SJimmy Kizito union { 127676724b76SJimmy Kizito uint8_t digmode; /** enum atom_encode_mode_def */ 127776724b76SJimmy Kizito uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 127876724b76SJimmy Kizito } mode_laneset; 127976724b76SJimmy Kizito uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 128076724b76SJimmy Kizito uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 128176724b76SJimmy Kizito uint8_t hpdsel; /** =0: HPD is not assigned */ 128276724b76SJimmy Kizito uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 128376724b76SJimmy Kizito uint8_t dpia_id; /** Index of DPIA */ 128476724b76SJimmy Kizito uint8_t fec_rdy : 1; 128576724b76SJimmy Kizito uint8_t reserved : 7; 128676724b76SJimmy Kizito uint32_t reserved1; 128776724b76SJimmy Kizito }; 128876724b76SJimmy Kizito 128976724b76SJimmy Kizito /** 129076724b76SJimmy Kizito * DMUB command for DPIA tunnel control. 129176724b76SJimmy Kizito */ 129276724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control { 129376724b76SJimmy Kizito struct dmub_cmd_header header; 129476724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data dpia_control; 129576724b76SJimmy Kizito }; 129676724b76SJimmy Kizito 129776724b76SJimmy Kizito /** 129871af9d46SMeenakshikumar Somasundaram * SET_CONFIG Command Payload 129971af9d46SMeenakshikumar Somasundaram */ 130071af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload { 130171af9d46SMeenakshikumar Somasundaram uint8_t msg_type; /* set config message type */ 130271af9d46SMeenakshikumar Somasundaram uint8_t msg_data; /* set config message data */ 130371af9d46SMeenakshikumar Somasundaram }; 130471af9d46SMeenakshikumar Somasundaram 130571af9d46SMeenakshikumar Somasundaram /** 130671af9d46SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 130771af9d46SMeenakshikumar Somasundaram */ 130871af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data { 130971af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload cmd_pkt; 131071af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */ 131171af9d46SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned in case of error */ 131271af9d46SMeenakshikumar Somasundaram }; 131371af9d46SMeenakshikumar Somasundaram 131471af9d46SMeenakshikumar Somasundaram /** 131571af9d46SMeenakshikumar Somasundaram * DMUB command structure for SET_CONFIG command. 131671af9d46SMeenakshikumar Somasundaram */ 131771af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access { 131871af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 131971af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 132071af9d46SMeenakshikumar Somasundaram }; 132171af9d46SMeenakshikumar Somasundaram 132271af9d46SMeenakshikumar Somasundaram /** 1323139a3311SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1324139a3311SMeenakshikumar Somasundaram */ 1325139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data { 1326139a3311SMeenakshikumar Somasundaram uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1327139a3311SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */ 1328139a3311SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1329139a3311SMeenakshikumar Somasundaram uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1330139a3311SMeenakshikumar Somasundaram }; 1331139a3311SMeenakshikumar Somasundaram 1332139a3311SMeenakshikumar Somasundaram /** 1333139a3311SMeenakshikumar Somasundaram * DMUB command structure for SET_ command. 1334139a3311SMeenakshikumar Somasundaram */ 1335139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots { 1336139a3311SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 1337139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1338139a3311SMeenakshikumar Somasundaram }; 1339139a3311SMeenakshikumar Somasundaram 1340139a3311SMeenakshikumar Somasundaram /** 13416f4f8ff5SMeenakshikumar Somasundaram * DMUB command structure for DPIA HPD int enable control. 13426f4f8ff5SMeenakshikumar Somasundaram */ 13436f4f8ff5SMeenakshikumar Somasundaram struct dmub_rb_cmd_dpia_hpd_int_enable { 13446f4f8ff5SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 13456f4f8ff5SMeenakshikumar Somasundaram uint32_t enable; /* dpia hpd interrupt enable */ 13466f4f8ff5SMeenakshikumar Somasundaram }; 13476f4f8ff5SMeenakshikumar Somasundaram 13486f4f8ff5SMeenakshikumar Somasundaram /** 1349592a6318SAnthony Koo * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1350592a6318SAnthony Koo */ 13517c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init { 1352592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1353592a6318SAnthony Koo uint8_t reserved[60]; /**< reserved bits */ 13547c008829SNicholas Kazlauskas }; 13557c008829SNicholas Kazlauskas 13561a595f28SAnthony Koo /** 13571a595f28SAnthony Koo * enum dp_aux_request_action - DP AUX request command listing. 13581a595f28SAnthony Koo * 13591a595f28SAnthony Koo * 4 AUX request command bits are shifted to high nibble. 13601a595f28SAnthony Koo */ 1361d9beecfcSAnthony Koo enum dp_aux_request_action { 13621a595f28SAnthony Koo /** I2C-over-AUX write request */ 1363d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 13641a595f28SAnthony Koo /** I2C-over-AUX read request */ 1365d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ = 0x10, 13661a595f28SAnthony Koo /** I2C-over-AUX write status request */ 1367d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 13681a595f28SAnthony Koo /** I2C-over-AUX write request with MOT=1 */ 1369d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 13701a595f28SAnthony Koo /** I2C-over-AUX read request with MOT=1 */ 1371d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 13721a595f28SAnthony Koo /** I2C-over-AUX write status request with MOT=1 */ 1373d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 13741a595f28SAnthony Koo /** Native AUX write request */ 1375d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 13761a595f28SAnthony Koo /** Native AUX read request */ 1377d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1378d9beecfcSAnthony Koo }; 1379d9beecfcSAnthony Koo 13801a595f28SAnthony Koo /** 13811a595f28SAnthony Koo * enum aux_return_code_type - DP AUX process return code listing. 13821a595f28SAnthony Koo */ 1383fd0f1d21SAnthony Koo enum aux_return_code_type { 13841a595f28SAnthony Koo /** AUX process succeeded */ 1385fd0f1d21SAnthony Koo AUX_RET_SUCCESS = 0, 13861a595f28SAnthony Koo /** AUX process failed with unknown reason */ 1387b6402afeSAnthony Koo AUX_RET_ERROR_UNKNOWN, 13881a595f28SAnthony Koo /** AUX process completed with invalid reply */ 1389b6402afeSAnthony Koo AUX_RET_ERROR_INVALID_REPLY, 13901a595f28SAnthony Koo /** AUX process timed out */ 1391fd0f1d21SAnthony Koo AUX_RET_ERROR_TIMEOUT, 13921a595f28SAnthony Koo /** HPD was low during AUX process */ 1393b6402afeSAnthony Koo AUX_RET_ERROR_HPD_DISCON, 13941a595f28SAnthony Koo /** Failed to acquire AUX engine */ 1395b6402afeSAnthony Koo AUX_RET_ERROR_ENGINE_ACQUIRE, 13961a595f28SAnthony Koo /** AUX request not supported */ 1397fd0f1d21SAnthony Koo AUX_RET_ERROR_INVALID_OPERATION, 13981a595f28SAnthony Koo /** AUX process not available */ 1399fd0f1d21SAnthony Koo AUX_RET_ERROR_PROTOCOL_ERROR, 1400fd0f1d21SAnthony Koo }; 1401fd0f1d21SAnthony Koo 14021a595f28SAnthony Koo /** 14031a595f28SAnthony Koo * enum aux_channel_type - DP AUX channel type listing. 14041a595f28SAnthony Koo */ 1405b6402afeSAnthony Koo enum aux_channel_type { 14061a595f28SAnthony Koo /** AUX thru Legacy DP AUX */ 1407b6402afeSAnthony Koo AUX_CHANNEL_LEGACY_DDC, 14081a595f28SAnthony Koo /** AUX thru DPIA DP tunneling */ 1409b6402afeSAnthony Koo AUX_CHANNEL_DPIA 1410b6402afeSAnthony Koo }; 1411b6402afeSAnthony Koo 14121a595f28SAnthony Koo /** 14131a595f28SAnthony Koo * struct aux_transaction_parameters - DP AUX request transaction data 14141a595f28SAnthony Koo */ 1415d9beecfcSAnthony Koo struct aux_transaction_parameters { 14161a595f28SAnthony Koo uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 14171a595f28SAnthony Koo uint8_t action; /**< enum dp_aux_request_action */ 14181a595f28SAnthony Koo uint8_t length; /**< DP AUX request data length */ 14191a595f28SAnthony Koo uint8_t reserved; /**< For future use */ 14201a595f28SAnthony Koo uint32_t address; /**< DP AUX address */ 14211a595f28SAnthony Koo uint8_t data[16]; /**< DP AUX write data */ 1422d9beecfcSAnthony Koo }; 1423d9beecfcSAnthony Koo 14241a595f28SAnthony Koo /** 14251a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 14261a595f28SAnthony Koo */ 1427d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data { 14281a595f28SAnthony Koo uint8_t instance; /**< AUX instance or DPIA instance */ 14291a595f28SAnthony Koo uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 14301a595f28SAnthony Koo uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 14311a595f28SAnthony Koo uint8_t reserved0; /**< For future use */ 14321a595f28SAnthony Koo uint16_t timeout; /**< timeout time in us */ 14331a595f28SAnthony Koo uint16_t reserved1; /**< For future use */ 14341a595f28SAnthony Koo enum aux_channel_type type; /**< enum aux_channel_type */ 14351a595f28SAnthony Koo struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1436d9beecfcSAnthony Koo }; 1437d9beecfcSAnthony Koo 14381a595f28SAnthony Koo /** 14391a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 14401a595f28SAnthony Koo */ 1441d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access { 14421a595f28SAnthony Koo /** 14431a595f28SAnthony Koo * Command header. 14441a595f28SAnthony Koo */ 1445d9beecfcSAnthony Koo struct dmub_cmd_header header; 14461a595f28SAnthony Koo /** 14471a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 14481a595f28SAnthony Koo */ 1449d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data aux_control; 1450d9beecfcSAnthony Koo }; 1451d9beecfcSAnthony Koo 14521a595f28SAnthony Koo /** 14531a595f28SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 14541a595f28SAnthony Koo */ 1455d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable { 14561a595f28SAnthony Koo /** 14571a595f28SAnthony Koo * Command header. 14581a595f28SAnthony Koo */ 1459d9beecfcSAnthony Koo struct dmub_cmd_header header; 14601a595f28SAnthony Koo /** 14611a595f28SAnthony Koo * enable: 0x0 -> disable outbox1 notification (default value) 14621a595f28SAnthony Koo * 0x1 -> enable outbox1 notification 14631a595f28SAnthony Koo */ 1464d9beecfcSAnthony Koo uint32_t enable; 1465d9beecfcSAnthony Koo }; 1466d9beecfcSAnthony Koo 1467d9beecfcSAnthony Koo /* DP AUX Reply command - OutBox Cmd */ 14681a595f28SAnthony Koo /** 14691a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14701a595f28SAnthony Koo */ 1471d9beecfcSAnthony Koo struct aux_reply_data { 14721a595f28SAnthony Koo /** 14731a595f28SAnthony Koo * Aux cmd 14741a595f28SAnthony Koo */ 1475d9beecfcSAnthony Koo uint8_t command; 14761a595f28SAnthony Koo /** 14771a595f28SAnthony Koo * Aux reply data length (max: 16 bytes) 14781a595f28SAnthony Koo */ 1479d9beecfcSAnthony Koo uint8_t length; 14801a595f28SAnthony Koo /** 14811a595f28SAnthony Koo * Alignment only 14821a595f28SAnthony Koo */ 1483d9beecfcSAnthony Koo uint8_t pad[2]; 14841a595f28SAnthony Koo /** 14851a595f28SAnthony Koo * Aux reply data 14861a595f28SAnthony Koo */ 1487d9beecfcSAnthony Koo uint8_t data[16]; 1488d9beecfcSAnthony Koo }; 1489d9beecfcSAnthony Koo 14901a595f28SAnthony Koo /** 14911a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14921a595f28SAnthony Koo */ 1493d9beecfcSAnthony Koo struct aux_reply_control_data { 14941a595f28SAnthony Koo /** 14951a595f28SAnthony Koo * Reserved for future use 14961a595f28SAnthony Koo */ 1497d9beecfcSAnthony Koo uint32_t handle; 14981a595f28SAnthony Koo /** 14991a595f28SAnthony Koo * Aux Instance 15001a595f28SAnthony Koo */ 1501b6402afeSAnthony Koo uint8_t instance; 15021a595f28SAnthony Koo /** 15031a595f28SAnthony Koo * Aux transaction result: definition in enum aux_return_code_type 15041a595f28SAnthony Koo */ 1505d9beecfcSAnthony Koo uint8_t result; 15061a595f28SAnthony Koo /** 15071a595f28SAnthony Koo * Alignment only 15081a595f28SAnthony Koo */ 1509d9beecfcSAnthony Koo uint16_t pad; 1510d9beecfcSAnthony Koo }; 1511d9beecfcSAnthony Koo 15121a595f28SAnthony Koo /** 15131a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 15141a595f28SAnthony Koo */ 1515d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply { 15161a595f28SAnthony Koo /** 15171a595f28SAnthony Koo * Command header. 15181a595f28SAnthony Koo */ 1519d9beecfcSAnthony Koo struct dmub_cmd_header header; 15201a595f28SAnthony Koo /** 15211a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 15221a595f28SAnthony Koo */ 1523d9beecfcSAnthony Koo struct aux_reply_control_data control; 15241a595f28SAnthony Koo /** 15251a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 15261a595f28SAnthony Koo */ 1527d9beecfcSAnthony Koo struct aux_reply_data reply_data; 1528d9beecfcSAnthony Koo }; 1529d9beecfcSAnthony Koo 1530fd0f1d21SAnthony Koo /* DP HPD Notify command - OutBox Cmd */ 15311a595f28SAnthony Koo /** 15321a595f28SAnthony Koo * DP HPD Type 15331a595f28SAnthony Koo */ 1534fd0f1d21SAnthony Koo enum dp_hpd_type { 15351a595f28SAnthony Koo /** 15361a595f28SAnthony Koo * Normal DP HPD 15371a595f28SAnthony Koo */ 1538fd0f1d21SAnthony Koo DP_HPD = 0, 15391a595f28SAnthony Koo /** 15401a595f28SAnthony Koo * DP HPD short pulse 15411a595f28SAnthony Koo */ 1542fd0f1d21SAnthony Koo DP_IRQ 1543fd0f1d21SAnthony Koo }; 1544fd0f1d21SAnthony Koo 15451a595f28SAnthony Koo /** 15461a595f28SAnthony Koo * DP HPD Status 15471a595f28SAnthony Koo */ 1548fd0f1d21SAnthony Koo enum dp_hpd_status { 15491a595f28SAnthony Koo /** 15501a595f28SAnthony Koo * DP_HPD status low 15511a595f28SAnthony Koo */ 1552fd0f1d21SAnthony Koo DP_HPD_UNPLUG = 0, 15531a595f28SAnthony Koo /** 15541a595f28SAnthony Koo * DP_HPD status high 15551a595f28SAnthony Koo */ 1556fd0f1d21SAnthony Koo DP_HPD_PLUG 1557fd0f1d21SAnthony Koo }; 1558fd0f1d21SAnthony Koo 15591a595f28SAnthony Koo /** 15601a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 15611a595f28SAnthony Koo */ 1562d9beecfcSAnthony Koo struct dp_hpd_data { 15631a595f28SAnthony Koo /** 15641a595f28SAnthony Koo * DP HPD instance 15651a595f28SAnthony Koo */ 1566b6402afeSAnthony Koo uint8_t instance; 15671a595f28SAnthony Koo /** 15681a595f28SAnthony Koo * HPD type 15691a595f28SAnthony Koo */ 1570d9beecfcSAnthony Koo uint8_t hpd_type; 15711a595f28SAnthony Koo /** 15721a595f28SAnthony Koo * HPD status: only for type: DP_HPD to indicate status 15731a595f28SAnthony Koo */ 1574d9beecfcSAnthony Koo uint8_t hpd_status; 15751a595f28SAnthony Koo /** 15761a595f28SAnthony Koo * Alignment only 15771a595f28SAnthony Koo */ 1578d9beecfcSAnthony Koo uint8_t pad; 1579d9beecfcSAnthony Koo }; 1580d9beecfcSAnthony Koo 15811a595f28SAnthony Koo /** 15821a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 15831a595f28SAnthony Koo */ 1584d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify { 15851a595f28SAnthony Koo /** 15861a595f28SAnthony Koo * Command header. 15871a595f28SAnthony Koo */ 1588d9beecfcSAnthony Koo struct dmub_cmd_header header; 15891a595f28SAnthony Koo /** 15901a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 15911a595f28SAnthony Koo */ 1592d9beecfcSAnthony Koo struct dp_hpd_data hpd_data; 1593d9beecfcSAnthony Koo }; 1594d9beecfcSAnthony Koo 159571af9d46SMeenakshikumar Somasundaram /** 159671af9d46SMeenakshikumar Somasundaram * Definition of a SET_CONFIG reply from DPOA. 159771af9d46SMeenakshikumar Somasundaram */ 159871af9d46SMeenakshikumar Somasundaram enum set_config_status { 159971af9d46SMeenakshikumar Somasundaram SET_CONFIG_PENDING = 0, 160071af9d46SMeenakshikumar Somasundaram SET_CONFIG_ACK_RECEIVED, 160171af9d46SMeenakshikumar Somasundaram SET_CONFIG_RX_TIMEOUT, 160271af9d46SMeenakshikumar Somasundaram SET_CONFIG_UNKNOWN_ERROR, 160371af9d46SMeenakshikumar Somasundaram }; 160471af9d46SMeenakshikumar Somasundaram 160571af9d46SMeenakshikumar Somasundaram /** 160671af9d46SMeenakshikumar Somasundaram * Definition of a set_config reply 160771af9d46SMeenakshikumar Somasundaram */ 160871af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data { 160971af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA Instance */ 161071af9d46SMeenakshikumar Somasundaram uint8_t status; /* Set Config reply */ 161171af9d46SMeenakshikumar Somasundaram uint16_t pad; /* Alignment */ 161271af9d46SMeenakshikumar Somasundaram }; 161371af9d46SMeenakshikumar Somasundaram 161471af9d46SMeenakshikumar Somasundaram /** 161571af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 161671af9d46SMeenakshikumar Somasundaram */ 161771af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply { 161871af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; 161971af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data set_config_reply_control; 162071af9d46SMeenakshikumar Somasundaram }; 162171af9d46SMeenakshikumar Somasundaram 1622ea5a4db9SAnthony Koo /** 16238af54c61SMustapha Ghaddar * Definition of a DPIA notification header 16248af54c61SMustapha Ghaddar */ 16258af54c61SMustapha Ghaddar struct dpia_notification_header { 16268af54c61SMustapha Ghaddar uint8_t instance; /**< DPIA Instance */ 16278af54c61SMustapha Ghaddar uint8_t reserved[3]; 16288af54c61SMustapha Ghaddar enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 16298af54c61SMustapha Ghaddar }; 16308af54c61SMustapha Ghaddar 16318af54c61SMustapha Ghaddar /** 16328af54c61SMustapha Ghaddar * Definition of the common data struct of DPIA notification 16338af54c61SMustapha Ghaddar */ 16348af54c61SMustapha Ghaddar struct dpia_notification_common { 16358af54c61SMustapha Ghaddar uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 16368af54c61SMustapha Ghaddar - sizeof(struct dpia_notification_header)]; 16378af54c61SMustapha Ghaddar }; 16388af54c61SMustapha Ghaddar 16398af54c61SMustapha Ghaddar /** 16408af54c61SMustapha Ghaddar * Definition of a DPIA notification data 16418af54c61SMustapha Ghaddar */ 16428af54c61SMustapha Ghaddar struct dpia_bw_allocation_notify_data { 16438af54c61SMustapha Ghaddar union { 16448af54c61SMustapha Ghaddar struct { 16458af54c61SMustapha Ghaddar uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 16468af54c61SMustapha Ghaddar uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 16478af54c61SMustapha Ghaddar uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 16488af54c61SMustapha Ghaddar uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 16498af54c61SMustapha Ghaddar uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 16508af54c61SMustapha Ghaddar uint16_t reserved: 11; /**< Reserved */ 16518af54c61SMustapha Ghaddar } bits; 16528af54c61SMustapha Ghaddar 16538af54c61SMustapha Ghaddar uint16_t flags; 16548af54c61SMustapha Ghaddar }; 16558af54c61SMustapha Ghaddar 16568af54c61SMustapha Ghaddar uint8_t cm_id; /**< CM ID */ 16578af54c61SMustapha Ghaddar uint8_t group_id; /**< Group ID */ 16588af54c61SMustapha Ghaddar uint8_t granularity; /**< BW Allocation Granularity */ 16598af54c61SMustapha Ghaddar uint8_t estimated_bw; /**< Estimated_BW */ 16608af54c61SMustapha Ghaddar uint8_t allocated_bw; /**< Allocated_BW */ 16618af54c61SMustapha Ghaddar uint8_t reserved; 16628af54c61SMustapha Ghaddar }; 16638af54c61SMustapha Ghaddar 16648af54c61SMustapha Ghaddar /** 16658af54c61SMustapha Ghaddar * union dpia_notify_data_type - DPIA Notification in Outbox command 16668af54c61SMustapha Ghaddar */ 16678af54c61SMustapha Ghaddar union dpia_notification_data { 16688af54c61SMustapha Ghaddar /** 16698af54c61SMustapha Ghaddar * DPIA Notification for common data struct 16708af54c61SMustapha Ghaddar */ 16718af54c61SMustapha Ghaddar struct dpia_notification_common common_data; 16728af54c61SMustapha Ghaddar 16738af54c61SMustapha Ghaddar /** 16748af54c61SMustapha Ghaddar * DPIA Notification for DP BW Allocation support 16758af54c61SMustapha Ghaddar */ 16768af54c61SMustapha Ghaddar struct dpia_bw_allocation_notify_data dpia_bw_alloc; 16778af54c61SMustapha Ghaddar }; 16788af54c61SMustapha Ghaddar 16798af54c61SMustapha Ghaddar /** 16808af54c61SMustapha Ghaddar * Definition of a DPIA notification payload 16818af54c61SMustapha Ghaddar */ 16828af54c61SMustapha Ghaddar struct dpia_notification_payload { 16838af54c61SMustapha Ghaddar struct dpia_notification_header header; 16848af54c61SMustapha Ghaddar union dpia_notification_data data; /**< DPIA notification payload data */ 16858af54c61SMustapha Ghaddar }; 16868af54c61SMustapha Ghaddar 16878af54c61SMustapha Ghaddar /** 16888af54c61SMustapha Ghaddar * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 16898af54c61SMustapha Ghaddar */ 16908af54c61SMustapha Ghaddar struct dmub_rb_cmd_dpia_notification { 16918af54c61SMustapha Ghaddar struct dmub_cmd_header header; /**< DPIA notification header */ 16928af54c61SMustapha Ghaddar struct dpia_notification_payload payload; /**< DPIA notification payload */ 16938af54c61SMustapha Ghaddar }; 16948af54c61SMustapha Ghaddar 16958af54c61SMustapha Ghaddar /** 1696ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1697ea5a4db9SAnthony Koo */ 1698ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data { 1699ea5a4db9SAnthony Koo uint8_t instance; /**< HPD instance or DPIA instance */ 1700ea5a4db9SAnthony Koo uint8_t result; /**< For returning HPD state */ 1701874714feSAnthony Koo uint16_t pad; /** < Alignment */ 1702ea5a4db9SAnthony Koo enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1703ea5a4db9SAnthony Koo enum aux_return_code_type status; /**< for returning the status of command */ 1704ea5a4db9SAnthony Koo }; 1705ea5a4db9SAnthony Koo 1706ea5a4db9SAnthony Koo /** 1707ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1708ea5a4db9SAnthony Koo */ 1709ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state { 1710ea5a4db9SAnthony Koo /** 1711ea5a4db9SAnthony Koo * Command header. 1712ea5a4db9SAnthony Koo */ 1713ea5a4db9SAnthony Koo struct dmub_cmd_header header; 1714ea5a4db9SAnthony Koo /** 1715ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1716ea5a4db9SAnthony Koo */ 1717ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data data; 1718ea5a4db9SAnthony Koo }; 1719ea5a4db9SAnthony Koo 172084034ad4SAnthony Koo /* 172184034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 172284034ad4SAnthony Koo * Do not reuse or modify IDs. 172384034ad4SAnthony Koo */ 172484034ad4SAnthony Koo 17251a595f28SAnthony Koo /** 17261a595f28SAnthony Koo * PSR command sub-types. 17271a595f28SAnthony Koo */ 172884034ad4SAnthony Koo enum dmub_cmd_psr_type { 17291a595f28SAnthony Koo /** 17301a595f28SAnthony Koo * Set PSR version support. 17311a595f28SAnthony Koo */ 173284034ad4SAnthony Koo DMUB_CMD__PSR_SET_VERSION = 0, 17331a595f28SAnthony Koo /** 17341a595f28SAnthony Koo * Copy driver-calculated parameters to PSR state. 17351a595f28SAnthony Koo */ 173684034ad4SAnthony Koo DMUB_CMD__PSR_COPY_SETTINGS = 1, 17371a595f28SAnthony Koo /** 17381a595f28SAnthony Koo * Enable PSR. 17391a595f28SAnthony Koo */ 174084034ad4SAnthony Koo DMUB_CMD__PSR_ENABLE = 2, 17411a595f28SAnthony Koo 17421a595f28SAnthony Koo /** 17431a595f28SAnthony Koo * Disable PSR. 17441a595f28SAnthony Koo */ 174584034ad4SAnthony Koo DMUB_CMD__PSR_DISABLE = 3, 17461a595f28SAnthony Koo 17471a595f28SAnthony Koo /** 17481a595f28SAnthony Koo * Set PSR level. 17491a595f28SAnthony Koo * PSR level is a 16-bit value dicated by driver that 17501a595f28SAnthony Koo * will enable/disable different functionality. 17511a595f28SAnthony Koo */ 175284034ad4SAnthony Koo DMUB_CMD__PSR_SET_LEVEL = 4, 17531a595f28SAnthony Koo 17541a595f28SAnthony Koo /** 17551a595f28SAnthony Koo * Forces PSR enabled until an explicit PSR disable call. 17561a595f28SAnthony Koo */ 1757672251b2SAnthony Koo DMUB_CMD__PSR_FORCE_STATIC = 5, 1758e5dfcd27SRobin Chen /** 175983eb5385SDavid Zhang * Set vtotal in psr active for FreeSync PSR. 176083eb5385SDavid Zhang */ 176183eb5385SDavid Zhang DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 176283eb5385SDavid Zhang /** 1763e5dfcd27SRobin Chen * Set PSR power option 1764e5dfcd27SRobin Chen */ 1765e5dfcd27SRobin Chen DMUB_CMD__SET_PSR_POWER_OPT = 7, 176684034ad4SAnthony Koo }; 176784034ad4SAnthony Koo 176885f4bc0cSAlvin Lee enum dmub_cmd_fams_type { 176985f4bc0cSAlvin Lee DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 177085f4bc0cSAlvin Lee DMUB_CMD__FAMS_DRR_UPDATE = 1, 177185f4bc0cSAlvin Lee DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 177281f776b6SAnthony Koo /** 177381f776b6SAnthony Koo * For SubVP set manual trigger in FW because it 177481f776b6SAnthony Koo * triggers DRR_UPDATE_PENDING which SubVP relies 177581f776b6SAnthony Koo * on (for any SubVP cases that use a DRR display) 177681f776b6SAnthony Koo */ 177781f776b6SAnthony Koo DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 177885f4bc0cSAlvin Lee }; 177985f4bc0cSAlvin Lee 17801a595f28SAnthony Koo /** 17811a595f28SAnthony Koo * PSR versions. 17821a595f28SAnthony Koo */ 178384034ad4SAnthony Koo enum psr_version { 17841a595f28SAnthony Koo /** 17851a595f28SAnthony Koo * PSR version 1. 17861a595f28SAnthony Koo */ 178784034ad4SAnthony Koo PSR_VERSION_1 = 0, 17881a595f28SAnthony Koo /** 178983eb5385SDavid Zhang * Freesync PSR SU. 179083eb5385SDavid Zhang */ 179183eb5385SDavid Zhang PSR_VERSION_SU_1 = 1, 179283eb5385SDavid Zhang /** 17931a595f28SAnthony Koo * PSR not supported. 17941a595f28SAnthony Koo */ 179584034ad4SAnthony Koo PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 179684034ad4SAnthony Koo }; 179784034ad4SAnthony Koo 1798592a6318SAnthony Koo /** 1799592a6318SAnthony Koo * enum dmub_cmd_mall_type - MALL commands 1800592a6318SAnthony Koo */ 180152f2e83eSBhawanpreet Lakha enum dmub_cmd_mall_type { 1802592a6318SAnthony Koo /** 1803592a6318SAnthony Koo * Allows display refresh from MALL. 1804592a6318SAnthony Koo */ 180552f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_ALLOW = 0, 1806592a6318SAnthony Koo /** 1807592a6318SAnthony Koo * Disallows display refresh from MALL. 1808592a6318SAnthony Koo */ 180952f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1810592a6318SAnthony Koo /** 1811592a6318SAnthony Koo * Cursor copy for MALL. 1812592a6318SAnthony Koo */ 181352f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1814592a6318SAnthony Koo /** 1815592a6318SAnthony Koo * Controls DF requests. 1816592a6318SAnthony Koo */ 1817ea7154d8SBhawanpreet Lakha DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 181852f2e83eSBhawanpreet Lakha }; 181952f2e83eSBhawanpreet Lakha 1820a91b402dSCharlene Liu /** 182178174f47SAnthony Koo * PHY Link rate for DP. 182278174f47SAnthony Koo */ 182378174f47SAnthony Koo enum phy_link_rate { 182478174f47SAnthony Koo /** 182578174f47SAnthony Koo * not supported. 182678174f47SAnthony Koo */ 182778174f47SAnthony Koo PHY_RATE_UNKNOWN = 0, 182878174f47SAnthony Koo /** 182978174f47SAnthony Koo * Rate_1 (RBR) - 1.62 Gbps/Lane 183078174f47SAnthony Koo */ 183178174f47SAnthony Koo PHY_RATE_162 = 1, 183278174f47SAnthony Koo /** 183378174f47SAnthony Koo * Rate_2 - 2.16 Gbps/Lane 183478174f47SAnthony Koo */ 183578174f47SAnthony Koo PHY_RATE_216 = 2, 183678174f47SAnthony Koo /** 183778174f47SAnthony Koo * Rate_3 - 2.43 Gbps/Lane 183878174f47SAnthony Koo */ 183978174f47SAnthony Koo PHY_RATE_243 = 3, 184078174f47SAnthony Koo /** 184178174f47SAnthony Koo * Rate_4 (HBR) - 2.70 Gbps/Lane 184278174f47SAnthony Koo */ 184378174f47SAnthony Koo PHY_RATE_270 = 4, 184478174f47SAnthony Koo /** 184578174f47SAnthony Koo * Rate_5 (RBR2)- 3.24 Gbps/Lane 184678174f47SAnthony Koo */ 184778174f47SAnthony Koo PHY_RATE_324 = 5, 184878174f47SAnthony Koo /** 184978174f47SAnthony Koo * Rate_6 - 4.32 Gbps/Lane 185078174f47SAnthony Koo */ 185178174f47SAnthony Koo PHY_RATE_432 = 6, 185278174f47SAnthony Koo /** 185378174f47SAnthony Koo * Rate_7 (HBR2)- 5.40 Gbps/Lane 185478174f47SAnthony Koo */ 185578174f47SAnthony Koo PHY_RATE_540 = 7, 185678174f47SAnthony Koo /** 185778174f47SAnthony Koo * Rate_8 (HBR3)- 8.10 Gbps/Lane 185878174f47SAnthony Koo */ 185978174f47SAnthony Koo PHY_RATE_810 = 8, 186078174f47SAnthony Koo /** 186178174f47SAnthony Koo * UHBR10 - 10.0 Gbps/Lane 186278174f47SAnthony Koo */ 186378174f47SAnthony Koo PHY_RATE_1000 = 9, 186478174f47SAnthony Koo /** 186578174f47SAnthony Koo * UHBR13.5 - 13.5 Gbps/Lane 186678174f47SAnthony Koo */ 186778174f47SAnthony Koo PHY_RATE_1350 = 10, 186878174f47SAnthony Koo /** 186978174f47SAnthony Koo * UHBR10 - 20.0 Gbps/Lane 187078174f47SAnthony Koo */ 187178174f47SAnthony Koo PHY_RATE_2000 = 11, 187278174f47SAnthony Koo }; 187378174f47SAnthony Koo 187478174f47SAnthony Koo /** 187578174f47SAnthony Koo * enum dmub_phy_fsm_state - PHY FSM states. 187678174f47SAnthony Koo * PHY FSM state to transit to during PSR enable/disable. 187778174f47SAnthony Koo */ 187878174f47SAnthony Koo enum dmub_phy_fsm_state { 187978174f47SAnthony Koo DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 188078174f47SAnthony Koo DMUB_PHY_FSM_RESET, 188178174f47SAnthony Koo DMUB_PHY_FSM_RESET_RELEASED, 188278174f47SAnthony Koo DMUB_PHY_FSM_SRAM_LOAD_DONE, 188378174f47SAnthony Koo DMUB_PHY_FSM_INITIALIZED, 188478174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED, 188578174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_LP, 188678174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_PG, 188778174f47SAnthony Koo DMUB_PHY_FSM_POWER_DOWN, 188878174f47SAnthony Koo DMUB_PHY_FSM_PLL_EN, 188978174f47SAnthony Koo DMUB_PHY_FSM_TX_EN, 189078174f47SAnthony Koo DMUB_PHY_FSM_FAST_LP, 189178174f47SAnthony Koo }; 189278174f47SAnthony Koo 189378174f47SAnthony Koo /** 18941a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 18951a595f28SAnthony Koo */ 18967c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data { 18971a595f28SAnthony Koo /** 18981a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 18991a595f28SAnthony Koo */ 19007b8a6362SAnthony Koo union dmub_psr_debug_flags debug; 19011a595f28SAnthony Koo /** 19021a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 19031a595f28SAnthony Koo */ 19044c1a1335SWyatt Wood uint16_t psr_level; 19051a595f28SAnthony Koo /** 19061a595f28SAnthony Koo * DPP HW instance. 19071a595f28SAnthony Koo */ 19084c1a1335SWyatt Wood uint8_t dpp_inst; 19091a595f28SAnthony Koo /** 19101a595f28SAnthony Koo * MPCC HW instance. 19111a595f28SAnthony Koo * Not used in dmub fw, 191234ba432cSAnthony Koo * dmub fw will get active opp by reading odm registers. 191334ba432cSAnthony Koo */ 19144c1a1335SWyatt Wood uint8_t mpcc_inst; 19151a595f28SAnthony Koo /** 19161a595f28SAnthony Koo * OPP HW instance. 19171a595f28SAnthony Koo * Not used in dmub fw, 19181a595f28SAnthony Koo * dmub fw will get active opp by reading odm registers. 19191a595f28SAnthony Koo */ 19204c1a1335SWyatt Wood uint8_t opp_inst; 19211a595f28SAnthony Koo /** 19221a595f28SAnthony Koo * OTG HW instance. 19231a595f28SAnthony Koo */ 19244c1a1335SWyatt Wood uint8_t otg_inst; 19251a595f28SAnthony Koo /** 19261a595f28SAnthony Koo * DIG FE HW instance. 19271a595f28SAnthony Koo */ 19284c1a1335SWyatt Wood uint8_t digfe_inst; 19291a595f28SAnthony Koo /** 19301a595f28SAnthony Koo * DIG BE HW instance. 19311a595f28SAnthony Koo */ 19324c1a1335SWyatt Wood uint8_t digbe_inst; 19331a595f28SAnthony Koo /** 19341a595f28SAnthony Koo * DP PHY HW instance. 19351a595f28SAnthony Koo */ 19364c1a1335SWyatt Wood uint8_t dpphy_inst; 19371a595f28SAnthony Koo /** 19381a595f28SAnthony Koo * AUX HW instance. 19391a595f28SAnthony Koo */ 19404c1a1335SWyatt Wood uint8_t aux_inst; 19411a595f28SAnthony Koo /** 19421a595f28SAnthony Koo * Determines if SMU optimzations are enabled/disabled. 19431a595f28SAnthony Koo */ 19444c1a1335SWyatt Wood uint8_t smu_optimizations_en; 19451a595f28SAnthony Koo /** 19461a595f28SAnthony Koo * Unused. 19471a595f28SAnthony Koo * TODO: Remove. 19481a595f28SAnthony Koo */ 19494c1a1335SWyatt Wood uint8_t frame_delay; 19501a595f28SAnthony Koo /** 19511a595f28SAnthony Koo * If RFB setup time is greater than the total VBLANK time, 19521a595f28SAnthony Koo * it is not possible for the sink to capture the video frame 19531a595f28SAnthony Koo * in the same frame the SDP is sent. In this case, 19541a595f28SAnthony Koo * the frame capture indication bit should be set and an extra 19551a595f28SAnthony Koo * static frame should be transmitted to the sink. 19561a595f28SAnthony Koo */ 19574c1a1335SWyatt Wood uint8_t frame_cap_ind; 19581a595f28SAnthony Koo /** 195983eb5385SDavid Zhang * Granularity of Y offset supported by sink. 19601a595f28SAnthony Koo */ 196183eb5385SDavid Zhang uint8_t su_y_granularity; 196283eb5385SDavid Zhang /** 196383eb5385SDavid Zhang * Indicates whether sink should start capturing 196483eb5385SDavid Zhang * immediately following active scan line, 196583eb5385SDavid Zhang * or starting with the 2nd active scan line. 196683eb5385SDavid Zhang */ 196783eb5385SDavid Zhang uint8_t line_capture_indication; 19681a595f28SAnthony Koo /** 19691a595f28SAnthony Koo * Multi-display optimizations are implemented on certain ASICs. 19701a595f28SAnthony Koo */ 1971175f0971SYongqiang Sun uint8_t multi_disp_optimizations_en; 19721a595f28SAnthony Koo /** 19731a595f28SAnthony Koo * The last possible line SDP may be transmitted without violating 19741a595f28SAnthony Koo * the RFB setup time or entering the active video frame. 19751a595f28SAnthony Koo */ 197678ead771SAnthony Koo uint16_t init_sdp_deadline; 19771a595f28SAnthony Koo /** 197883eb5385SDavid Zhang * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 19791a595f28SAnthony Koo */ 198083eb5385SDavid Zhang uint8_t rate_control_caps ; 198183eb5385SDavid Zhang /* 198283eb5385SDavid Zhang * Force PSRSU always doing full frame update 198383eb5385SDavid Zhang */ 198483eb5385SDavid Zhang uint8_t force_ffu_mode; 19851a595f28SAnthony Koo /** 19861a595f28SAnthony Koo * Length of each horizontal line in us. 19871a595f28SAnthony Koo */ 19889b56f6bcSAnthony Koo uint32_t line_time_in_us; 1989ecc11601SAnthony Koo /** 1990ecc11601SAnthony Koo * FEC enable status in driver 1991ecc11601SAnthony Koo */ 1992ecc11601SAnthony Koo uint8_t fec_enable_status; 1993ecc11601SAnthony Koo /** 1994ecc11601SAnthony Koo * FEC re-enable delay when PSR exit. 1995ecc11601SAnthony Koo * unit is 100us, range form 0~255(0xFF). 1996ecc11601SAnthony Koo */ 1997ecc11601SAnthony Koo uint8_t fec_enable_delay_in100us; 1998ecc11601SAnthony Koo /** 1999f56c837aSMikita Lipski * PSR control version. 2000ecc11601SAnthony Koo */ 2001f56c837aSMikita Lipski uint8_t cmd_version; 2002f56c837aSMikita Lipski /** 2003f56c837aSMikita Lipski * Panel Instance. 200436e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2005f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2006f56c837aSMikita Lipski */ 2007f56c837aSMikita Lipski uint8_t panel_inst; 20082665f63aSMikita Lipski /* 20092665f63aSMikita Lipski * DSC enable status in driver 2010360d1b65SIan Chen */ 20112665f63aSMikita Lipski uint8_t dsc_enable_status; 2012b5175966SShah Dharati /* 2013b5175966SShah Dharati * Use FSM state for PSR power up/down 20142665f63aSMikita Lipski */ 2015b5175966SShah Dharati uint8_t use_phy_fsm; 2016b5175966SShah Dharati /** 20171a2b886bSRyan Lin * frame delay for frame re-lock 20181a2b886bSRyan Lin */ 20191a2b886bSRyan Lin uint8_t relock_delay_frame_cnt; 20201a2b886bSRyan Lin /** 2021b5175966SShah Dharati * Explicit padding to 2 byte boundary. 2022b5175966SShah Dharati */ 20231a2b886bSRyan Lin uint8_t pad3; 2024c84ff24aSRobin Chen /** 2025c84ff24aSRobin Chen * DSC Slice height. 2026c84ff24aSRobin Chen */ 2027c84ff24aSRobin Chen uint16_t dsc_slice_height; 2028c84ff24aSRobin Chen /** 2029c84ff24aSRobin Chen * Explicit padding to 4 byte boundary. 2030c84ff24aSRobin Chen */ 2031c84ff24aSRobin Chen uint16_t pad; 20327c008829SNicholas Kazlauskas }; 20337c008829SNicholas Kazlauskas 20341a595f28SAnthony Koo /** 20351a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 20361a595f28SAnthony Koo */ 20377c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings { 20381a595f28SAnthony Koo /** 20391a595f28SAnthony Koo * Command header. 20401a595f28SAnthony Koo */ 20417c008829SNicholas Kazlauskas struct dmub_cmd_header header; 20421a595f28SAnthony Koo /** 20431a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 20441a595f28SAnthony Koo */ 20457c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 20467c008829SNicholas Kazlauskas }; 20477c008829SNicholas Kazlauskas 20481a595f28SAnthony Koo /** 20491a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 20501a595f28SAnthony Koo */ 20517c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data { 20521a595f28SAnthony Koo /** 20531a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 20541a595f28SAnthony Koo */ 20557c008829SNicholas Kazlauskas uint16_t psr_level; 20561a595f28SAnthony Koo /** 2057f56c837aSMikita Lipski * PSR control version. 20581a595f28SAnthony Koo */ 2059f56c837aSMikita Lipski uint8_t cmd_version; 2060f56c837aSMikita Lipski /** 2061f56c837aSMikita Lipski * Panel Instance. 206236e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2063f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2064f56c837aSMikita Lipski */ 2065f56c837aSMikita Lipski uint8_t panel_inst; 20667c008829SNicholas Kazlauskas }; 20677c008829SNicholas Kazlauskas 20681a595f28SAnthony Koo /** 20691a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 20701a595f28SAnthony Koo */ 20717c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level { 20721a595f28SAnthony Koo /** 20731a595f28SAnthony Koo * Command header. 20741a595f28SAnthony Koo */ 20757c008829SNicholas Kazlauskas struct dmub_cmd_header header; 20761a595f28SAnthony Koo /** 20771a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 20781a595f28SAnthony Koo */ 20797c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data psr_set_level_data; 20807c008829SNicholas Kazlauskas }; 20817c008829SNicholas Kazlauskas 2082f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data { 2083f56c837aSMikita Lipski /** 2084f56c837aSMikita Lipski * PSR control version. 2085f56c837aSMikita Lipski */ 2086f56c837aSMikita Lipski uint8_t cmd_version; 2087f56c837aSMikita Lipski /** 2088f56c837aSMikita Lipski * Panel Instance. 208936e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2090f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2091f56c837aSMikita Lipski */ 2092f56c837aSMikita Lipski uint8_t panel_inst; 2093f56c837aSMikita Lipski /** 209478174f47SAnthony Koo * Phy state to enter. 209578174f47SAnthony Koo * Values to use are defined in dmub_phy_fsm_state 2096f56c837aSMikita Lipski */ 209778174f47SAnthony Koo uint8_t phy_fsm_state; 209878174f47SAnthony Koo /** 209978174f47SAnthony Koo * Phy rate for DP - RBR/HBR/HBR2/HBR3. 210078174f47SAnthony Koo * Set this using enum phy_link_rate. 210178174f47SAnthony Koo * This does not support HDMI/DP2 for now. 210278174f47SAnthony Koo */ 210378174f47SAnthony Koo uint8_t phy_rate; 2104f56c837aSMikita Lipski }; 2105f56c837aSMikita Lipski 21061a595f28SAnthony Koo /** 21071a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 21081a595f28SAnthony Koo * PSR enable/disable is controlled using the sub_type. 21091a595f28SAnthony Koo */ 21107c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_enable { 21111a595f28SAnthony Koo /** 21121a595f28SAnthony Koo * Command header. 21131a595f28SAnthony Koo */ 21147c008829SNicholas Kazlauskas struct dmub_cmd_header header; 2115f56c837aSMikita Lipski 2116f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data data; 21177c008829SNicholas Kazlauskas }; 21187c008829SNicholas Kazlauskas 21191a595f28SAnthony Koo /** 21201a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 21211a595f28SAnthony Koo */ 2122d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data { 21231a595f28SAnthony Koo /** 21241a595f28SAnthony Koo * PSR version that FW should implement. 21251a595f28SAnthony Koo */ 21261a595f28SAnthony Koo enum psr_version version; 2127f56c837aSMikita Lipski /** 2128f56c837aSMikita Lipski * PSR control version. 2129f56c837aSMikita Lipski */ 2130f56c837aSMikita Lipski uint8_t cmd_version; 2131f56c837aSMikita Lipski /** 2132f56c837aSMikita Lipski * Panel Instance. 213336e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2134f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2135f56c837aSMikita Lipski */ 2136f56c837aSMikita Lipski uint8_t panel_inst; 2137f56c837aSMikita Lipski /** 2138f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 2139f56c837aSMikita Lipski */ 2140f56c837aSMikita Lipski uint8_t pad[2]; 21417c008829SNicholas Kazlauskas }; 21427c008829SNicholas Kazlauskas 21431a595f28SAnthony Koo /** 21441a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 21451a595f28SAnthony Koo */ 2146d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version { 21471a595f28SAnthony Koo /** 21481a595f28SAnthony Koo * Command header. 21491a595f28SAnthony Koo */ 21507c008829SNicholas Kazlauskas struct dmub_cmd_header header; 21511a595f28SAnthony Koo /** 21521a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 21531a595f28SAnthony Koo */ 2154d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data psr_set_version_data; 21557c008829SNicholas Kazlauskas }; 21567c008829SNicholas Kazlauskas 2157f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data { 2158f56c837aSMikita Lipski /** 2159f56c837aSMikita Lipski * PSR control version. 2160f56c837aSMikita Lipski */ 2161f56c837aSMikita Lipski uint8_t cmd_version; 2162f56c837aSMikita Lipski /** 2163f56c837aSMikita Lipski * Panel Instance. 216436e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2165f56c837aSMikita Lipski * Currently the support is only for 0 or 1 2166f56c837aSMikita Lipski */ 2167f56c837aSMikita Lipski uint8_t panel_inst; 2168f56c837aSMikita Lipski /** 2169ad371c8aSAnthony Koo * Explicit padding to 4 byte boundary. 2170f56c837aSMikita Lipski */ 2171ad371c8aSAnthony Koo uint8_t pad[2]; 2172f56c837aSMikita Lipski }; 2173f56c837aSMikita Lipski 21741a595f28SAnthony Koo /** 21751a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 21761a595f28SAnthony Koo */ 2177672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static { 21781a595f28SAnthony Koo /** 21791a595f28SAnthony Koo * Command header. 21801a595f28SAnthony Koo */ 2181672251b2SAnthony Koo struct dmub_cmd_header header; 2182f56c837aSMikita Lipski /** 2183f56c837aSMikita Lipski * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2184f56c837aSMikita Lipski */ 2185f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data psr_force_static_data; 2186672251b2SAnthony Koo }; 2187672251b2SAnthony Koo 21881a595f28SAnthony Koo /** 218983eb5385SDavid Zhang * PSR SU debug flags. 219083eb5385SDavid Zhang */ 219183eb5385SDavid Zhang union dmub_psr_su_debug_flags { 219283eb5385SDavid Zhang /** 219383eb5385SDavid Zhang * PSR SU debug flags. 219483eb5385SDavid Zhang */ 219583eb5385SDavid Zhang struct { 219683eb5385SDavid Zhang /** 219783eb5385SDavid Zhang * Update dirty rect in SW only. 219883eb5385SDavid Zhang */ 219983eb5385SDavid Zhang uint8_t update_dirty_rect_only : 1; 220083eb5385SDavid Zhang /** 220183eb5385SDavid Zhang * Reset the cursor/plane state before processing the call. 220283eb5385SDavid Zhang */ 220383eb5385SDavid Zhang uint8_t reset_state : 1; 220483eb5385SDavid Zhang } bitfields; 220583eb5385SDavid Zhang 220683eb5385SDavid Zhang /** 220783eb5385SDavid Zhang * Union for debug flags. 220883eb5385SDavid Zhang */ 220983eb5385SDavid Zhang uint32_t u32All; 221083eb5385SDavid Zhang }; 221183eb5385SDavid Zhang 221283eb5385SDavid Zhang /** 221383eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 221483eb5385SDavid Zhang * This triggers a selective update for PSR SU. 221583eb5385SDavid Zhang */ 221683eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data { 221783eb5385SDavid Zhang /** 221883eb5385SDavid Zhang * Dirty rects from OS. 221983eb5385SDavid Zhang */ 222083eb5385SDavid Zhang struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 222183eb5385SDavid Zhang /** 222283eb5385SDavid Zhang * PSR SU debug flags. 222383eb5385SDavid Zhang */ 222483eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags; 222583eb5385SDavid Zhang /** 222683eb5385SDavid Zhang * OTG HW instance. 222783eb5385SDavid Zhang */ 222883eb5385SDavid Zhang uint8_t pipe_idx; 222983eb5385SDavid Zhang /** 223083eb5385SDavid Zhang * Number of dirty rects. 223183eb5385SDavid Zhang */ 223283eb5385SDavid Zhang uint8_t dirty_rect_count; 223383eb5385SDavid Zhang /** 223483eb5385SDavid Zhang * PSR control version. 223583eb5385SDavid Zhang */ 223683eb5385SDavid Zhang uint8_t cmd_version; 223783eb5385SDavid Zhang /** 223883eb5385SDavid Zhang * Panel Instance. 223936e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 224083eb5385SDavid Zhang * Currently the support is only for 0 or 1 224183eb5385SDavid Zhang */ 224283eb5385SDavid Zhang uint8_t panel_inst; 224383eb5385SDavid Zhang }; 224483eb5385SDavid Zhang 224583eb5385SDavid Zhang /** 224683eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 224783eb5385SDavid Zhang */ 224883eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect { 224983eb5385SDavid Zhang /** 225083eb5385SDavid Zhang * Command header. 225183eb5385SDavid Zhang */ 225283eb5385SDavid Zhang struct dmub_cmd_header header; 225383eb5385SDavid Zhang /** 225483eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 225583eb5385SDavid Zhang */ 225683eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 225783eb5385SDavid Zhang }; 225883eb5385SDavid Zhang 225983eb5385SDavid Zhang /** 226083eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 226183eb5385SDavid Zhang */ 2262b73353f7SMax Tseng union dmub_reg_cursor_control_cfg { 2263b73353f7SMax Tseng struct { 2264b73353f7SMax Tseng uint32_t cur_enable: 1; 2265b73353f7SMax Tseng uint32_t reser0: 3; 2266b73353f7SMax Tseng uint32_t cur_2x_magnify: 1; 2267b73353f7SMax Tseng uint32_t reser1: 3; 2268b73353f7SMax Tseng uint32_t mode: 3; 2269b73353f7SMax Tseng uint32_t reser2: 5; 2270b73353f7SMax Tseng uint32_t pitch: 2; 2271b73353f7SMax Tseng uint32_t reser3: 6; 2272b73353f7SMax Tseng uint32_t line_per_chunk: 5; 2273b73353f7SMax Tseng uint32_t reser4: 3; 2274b73353f7SMax Tseng } bits; 2275b73353f7SMax Tseng uint32_t raw; 2276b73353f7SMax Tseng }; 2277b73353f7SMax Tseng struct dmub_cursor_position_cache_hubp { 2278b73353f7SMax Tseng union dmub_reg_cursor_control_cfg cur_ctl; 2279b73353f7SMax Tseng union dmub_reg_position_cfg { 2280b73353f7SMax Tseng struct { 2281b73353f7SMax Tseng uint32_t cur_x_pos: 16; 2282b73353f7SMax Tseng uint32_t cur_y_pos: 16; 2283b73353f7SMax Tseng } bits; 2284b73353f7SMax Tseng uint32_t raw; 2285b73353f7SMax Tseng } position; 2286b73353f7SMax Tseng union dmub_reg_hot_spot_cfg { 2287b73353f7SMax Tseng struct { 2288b73353f7SMax Tseng uint32_t hot_x: 16; 2289b73353f7SMax Tseng uint32_t hot_y: 16; 2290b73353f7SMax Tseng } bits; 2291b73353f7SMax Tseng uint32_t raw; 2292b73353f7SMax Tseng } hot_spot; 2293b73353f7SMax Tseng union dmub_reg_dst_offset_cfg { 2294b73353f7SMax Tseng struct { 2295b73353f7SMax Tseng uint32_t dst_x_offset: 13; 2296b73353f7SMax Tseng uint32_t reserved: 19; 2297b73353f7SMax Tseng } bits; 2298b73353f7SMax Tseng uint32_t raw; 2299b73353f7SMax Tseng } dst_offset; 2300b73353f7SMax Tseng }; 2301b73353f7SMax Tseng 2302b73353f7SMax Tseng union dmub_reg_cur0_control_cfg { 2303b73353f7SMax Tseng struct { 2304b73353f7SMax Tseng uint32_t cur0_enable: 1; 2305b73353f7SMax Tseng uint32_t expansion_mode: 1; 2306b73353f7SMax Tseng uint32_t reser0: 1; 2307b73353f7SMax Tseng uint32_t cur0_rom_en: 1; 2308b73353f7SMax Tseng uint32_t mode: 3; 2309b73353f7SMax Tseng uint32_t reserved: 25; 2310b73353f7SMax Tseng } bits; 2311b73353f7SMax Tseng uint32_t raw; 2312b73353f7SMax Tseng }; 2313b73353f7SMax Tseng struct dmub_cursor_position_cache_dpp { 2314b73353f7SMax Tseng union dmub_reg_cur0_control_cfg cur0_ctl; 2315b73353f7SMax Tseng }; 2316b73353f7SMax Tseng struct dmub_cursor_position_cfg { 2317b73353f7SMax Tseng struct dmub_cursor_position_cache_hubp pHubp; 2318b73353f7SMax Tseng struct dmub_cursor_position_cache_dpp pDpp; 2319b73353f7SMax Tseng uint8_t pipe_idx; 2320b73353f7SMax Tseng /* 2321b73353f7SMax Tseng * Padding is required. To be 4 Bytes Aligned. 2322b73353f7SMax Tseng */ 2323b73353f7SMax Tseng uint8_t padding[3]; 2324b73353f7SMax Tseng }; 2325b73353f7SMax Tseng 2326b73353f7SMax Tseng struct dmub_cursor_attribute_cache_hubp { 2327b73353f7SMax Tseng uint32_t SURFACE_ADDR_HIGH; 2328b73353f7SMax Tseng uint32_t SURFACE_ADDR; 2329b73353f7SMax Tseng union dmub_reg_cursor_control_cfg cur_ctl; 2330b73353f7SMax Tseng union dmub_reg_cursor_size_cfg { 2331b73353f7SMax Tseng struct { 2332b73353f7SMax Tseng uint32_t width: 16; 2333b73353f7SMax Tseng uint32_t height: 16; 2334b73353f7SMax Tseng } bits; 2335b73353f7SMax Tseng uint32_t raw; 2336b73353f7SMax Tseng } size; 2337b73353f7SMax Tseng union dmub_reg_cursor_settings_cfg { 2338b73353f7SMax Tseng struct { 2339b73353f7SMax Tseng uint32_t dst_y_offset: 8; 2340b73353f7SMax Tseng uint32_t chunk_hdl_adjust: 2; 2341b73353f7SMax Tseng uint32_t reserved: 22; 2342b73353f7SMax Tseng } bits; 2343b73353f7SMax Tseng uint32_t raw; 2344b73353f7SMax Tseng } settings; 2345b73353f7SMax Tseng }; 2346b73353f7SMax Tseng struct dmub_cursor_attribute_cache_dpp { 2347b73353f7SMax Tseng union dmub_reg_cur0_control_cfg cur0_ctl; 2348b73353f7SMax Tseng }; 2349b73353f7SMax Tseng struct dmub_cursor_attributes_cfg { 2350b73353f7SMax Tseng struct dmub_cursor_attribute_cache_hubp aHubp; 2351b73353f7SMax Tseng struct dmub_cursor_attribute_cache_dpp aDpp; 2352b73353f7SMax Tseng }; 2353b73353f7SMax Tseng 2354b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 { 235583eb5385SDavid Zhang /** 235683eb5385SDavid Zhang * Cursor dirty rects. 235783eb5385SDavid Zhang */ 235883eb5385SDavid Zhang struct dmub_rect cursor_rect; 235983eb5385SDavid Zhang /** 236083eb5385SDavid Zhang * PSR SU debug flags. 236183eb5385SDavid Zhang */ 236283eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags; 236383eb5385SDavid Zhang /** 236483eb5385SDavid Zhang * Cursor enable/disable. 236583eb5385SDavid Zhang */ 236683eb5385SDavid Zhang uint8_t enable; 236783eb5385SDavid Zhang /** 236883eb5385SDavid Zhang * OTG HW instance. 236983eb5385SDavid Zhang */ 237083eb5385SDavid Zhang uint8_t pipe_idx; 237183eb5385SDavid Zhang /** 237283eb5385SDavid Zhang * PSR control version. 237383eb5385SDavid Zhang */ 237483eb5385SDavid Zhang uint8_t cmd_version; 237583eb5385SDavid Zhang /** 237683eb5385SDavid Zhang * Panel Instance. 237736e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 237883eb5385SDavid Zhang * Currently the support is only for 0 or 1 237983eb5385SDavid Zhang */ 238083eb5385SDavid Zhang uint8_t panel_inst; 2381b73353f7SMax Tseng /** 2382b73353f7SMax Tseng * Cursor Position Register. 2383b73353f7SMax Tseng * Registers contains Hubp & Dpp modules 2384b73353f7SMax Tseng */ 2385b73353f7SMax Tseng struct dmub_cursor_position_cfg position_cfg; 2386b73353f7SMax Tseng }; 2387b73353f7SMax Tseng 2388b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload1 { 2389b73353f7SMax Tseng struct dmub_cursor_attributes_cfg attribute_cfg; 2390b73353f7SMax Tseng }; 2391b73353f7SMax Tseng 2392b73353f7SMax Tseng union dmub_cmd_update_cursor_info_data { 2393b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 payload0; 2394b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload1 payload1; 239583eb5385SDavid Zhang }; 239683eb5385SDavid Zhang /** 239783eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 239883eb5385SDavid Zhang */ 239983eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info { 240083eb5385SDavid Zhang /** 240183eb5385SDavid Zhang * Command header. 240283eb5385SDavid Zhang */ 240383eb5385SDavid Zhang struct dmub_cmd_header header; 240483eb5385SDavid Zhang /** 240583eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 240683eb5385SDavid Zhang */ 2407b73353f7SMax Tseng union dmub_cmd_update_cursor_info_data update_cursor_info_data; 240883eb5385SDavid Zhang }; 240983eb5385SDavid Zhang 241083eb5385SDavid Zhang /** 241183eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 241283eb5385SDavid Zhang */ 241383eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data { 241483eb5385SDavid Zhang /** 241583eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 241683eb5385SDavid Zhang */ 241783eb5385SDavid Zhang uint16_t psr_vtotal_idle; 241883eb5385SDavid Zhang /** 241983eb5385SDavid Zhang * PSR control version. 242083eb5385SDavid Zhang */ 242183eb5385SDavid Zhang uint8_t cmd_version; 242283eb5385SDavid Zhang /** 242383eb5385SDavid Zhang * Panel Instance. 242436e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 242583eb5385SDavid Zhang * Currently the support is only for 0 or 1 242683eb5385SDavid Zhang */ 242783eb5385SDavid Zhang uint8_t panel_inst; 242883eb5385SDavid Zhang /* 242983eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 243083eb5385SDavid Zhang */ 243183eb5385SDavid Zhang uint16_t psr_vtotal_su; 243283eb5385SDavid Zhang /** 243383eb5385SDavid Zhang * Explicit padding to 4 byte boundary. 243483eb5385SDavid Zhang */ 243583eb5385SDavid Zhang uint8_t pad2[2]; 243683eb5385SDavid Zhang }; 243783eb5385SDavid Zhang 243883eb5385SDavid Zhang /** 243983eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 244083eb5385SDavid Zhang */ 244183eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal { 244283eb5385SDavid Zhang /** 244383eb5385SDavid Zhang * Command header. 244483eb5385SDavid Zhang */ 244583eb5385SDavid Zhang struct dmub_cmd_header header; 244683eb5385SDavid Zhang /** 244783eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 244883eb5385SDavid Zhang */ 244983eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 245083eb5385SDavid Zhang }; 245183eb5385SDavid Zhang 245283eb5385SDavid Zhang /** 2453e5dfcd27SRobin Chen * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2454e5dfcd27SRobin Chen */ 2455e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data { 2456e5dfcd27SRobin Chen /** 2457e5dfcd27SRobin Chen * PSR control version. 2458e5dfcd27SRobin Chen */ 2459e5dfcd27SRobin Chen uint8_t cmd_version; 2460e5dfcd27SRobin Chen /** 2461e5dfcd27SRobin Chen * Panel Instance. 246236e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use 2463e5dfcd27SRobin Chen * Currently the support is only for 0 or 1 2464e5dfcd27SRobin Chen */ 2465e5dfcd27SRobin Chen uint8_t panel_inst; 2466e5dfcd27SRobin Chen /** 2467e5dfcd27SRobin Chen * Explicit padding to 4 byte boundary. 2468e5dfcd27SRobin Chen */ 2469e5dfcd27SRobin Chen uint8_t pad[2]; 2470e5dfcd27SRobin Chen /** 2471e5dfcd27SRobin Chen * PSR power option 2472e5dfcd27SRobin Chen */ 2473e5dfcd27SRobin Chen uint32_t power_opt; 2474e5dfcd27SRobin Chen }; 2475e5dfcd27SRobin Chen 2476e5dfcd27SRobin Chen /** 2477e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2478e5dfcd27SRobin Chen */ 2479e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt { 2480e5dfcd27SRobin Chen /** 2481e5dfcd27SRobin Chen * Command header. 2482e5dfcd27SRobin Chen */ 2483e5dfcd27SRobin Chen struct dmub_cmd_header header; 2484e5dfcd27SRobin Chen /** 2485e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2486e5dfcd27SRobin Chen */ 2487e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2488e5dfcd27SRobin Chen }; 2489e5dfcd27SRobin Chen 2490e5dfcd27SRobin Chen /** 24911a595f28SAnthony Koo * Set of HW components that can be locked. 24920b51e7e8SAnthony Koo * 24930b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 24940b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 24951a595f28SAnthony Koo */ 2496788408b7SAnthony Koo union dmub_hw_lock_flags { 24971a595f28SAnthony Koo /** 24981a595f28SAnthony Koo * Set of HW components that can be locked. 24991a595f28SAnthony Koo */ 2500788408b7SAnthony Koo struct { 25011a595f28SAnthony Koo /** 25021a595f28SAnthony Koo * Lock/unlock OTG master update lock. 25031a595f28SAnthony Koo */ 2504788408b7SAnthony Koo uint8_t lock_pipe : 1; 25051a595f28SAnthony Koo /** 25061a595f28SAnthony Koo * Lock/unlock cursor. 25071a595f28SAnthony Koo */ 2508788408b7SAnthony Koo uint8_t lock_cursor : 1; 25091a595f28SAnthony Koo /** 25101a595f28SAnthony Koo * Lock/unlock global update lock. 25111a595f28SAnthony Koo */ 2512788408b7SAnthony Koo uint8_t lock_dig : 1; 25131a595f28SAnthony Koo /** 25141a595f28SAnthony Koo * Triple buffer lock requires additional hw programming to usual OTG master lock. 25151a595f28SAnthony Koo */ 2516788408b7SAnthony Koo uint8_t triple_buffer_lock : 1; 2517788408b7SAnthony Koo } bits; 2518788408b7SAnthony Koo 25191a595f28SAnthony Koo /** 25201a595f28SAnthony Koo * Union for HW Lock flags. 25211a595f28SAnthony Koo */ 2522788408b7SAnthony Koo uint8_t u8All; 2523788408b7SAnthony Koo }; 2524788408b7SAnthony Koo 25251a595f28SAnthony Koo /** 25261a595f28SAnthony Koo * Instances of HW to be locked. 25270b51e7e8SAnthony Koo * 25280b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 25290b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 25301a595f28SAnthony Koo */ 2531788408b7SAnthony Koo struct dmub_hw_lock_inst_flags { 25321a595f28SAnthony Koo /** 25331a595f28SAnthony Koo * OTG HW instance for OTG master update lock. 25341a595f28SAnthony Koo */ 2535788408b7SAnthony Koo uint8_t otg_inst; 25361a595f28SAnthony Koo /** 25371a595f28SAnthony Koo * OPP instance for cursor lock. 25381a595f28SAnthony Koo */ 2539788408b7SAnthony Koo uint8_t opp_inst; 25401a595f28SAnthony Koo /** 25411a595f28SAnthony Koo * OTG HW instance for global update lock. 25421a595f28SAnthony Koo * TODO: Remove, and re-use otg_inst. 25431a595f28SAnthony Koo */ 2544788408b7SAnthony Koo uint8_t dig_inst; 25451a595f28SAnthony Koo /** 25461a595f28SAnthony Koo * Explicit pad to 4 byte boundary. 25471a595f28SAnthony Koo */ 2548788408b7SAnthony Koo uint8_t pad; 2549788408b7SAnthony Koo }; 2550788408b7SAnthony Koo 25511a595f28SAnthony Koo /** 25521a595f28SAnthony Koo * Clients that can acquire the HW Lock Manager. 25530b51e7e8SAnthony Koo * 25540b51e7e8SAnthony Koo * Note: If updating with more clients, fields in 25550b51e7e8SAnthony Koo * dmub_inbox0_cmd_lock_hw must be updated to match. 25561a595f28SAnthony Koo */ 2557788408b7SAnthony Koo enum hw_lock_client { 25581a595f28SAnthony Koo /** 25591a595f28SAnthony Koo * Driver is the client of HW Lock Manager. 25601a595f28SAnthony Koo */ 2561788408b7SAnthony Koo HW_LOCK_CLIENT_DRIVER = 0, 25621a595f28SAnthony Koo /** 256383eb5385SDavid Zhang * PSR SU is the client of HW Lock Manager. 256483eb5385SDavid Zhang */ 256583eb5385SDavid Zhang HW_LOCK_CLIENT_PSR_SU = 1, 256683eb5385SDavid Zhang /** 25671a595f28SAnthony Koo * Invalid client. 25681a595f28SAnthony Koo */ 2569788408b7SAnthony Koo HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2570788408b7SAnthony Koo }; 2571788408b7SAnthony Koo 25721a595f28SAnthony Koo /** 25731a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 25741a595f28SAnthony Koo */ 2575788408b7SAnthony Koo struct dmub_cmd_lock_hw_data { 25761a595f28SAnthony Koo /** 25771a595f28SAnthony Koo * Specifies the client accessing HW Lock Manager. 25781a595f28SAnthony Koo */ 2579788408b7SAnthony Koo enum hw_lock_client client; 25801a595f28SAnthony Koo /** 25811a595f28SAnthony Koo * HW instances to be locked. 25821a595f28SAnthony Koo */ 2583788408b7SAnthony Koo struct dmub_hw_lock_inst_flags inst_flags; 25841a595f28SAnthony Koo /** 25851a595f28SAnthony Koo * Which components to be locked. 25861a595f28SAnthony Koo */ 2587788408b7SAnthony Koo union dmub_hw_lock_flags hw_locks; 25881a595f28SAnthony Koo /** 25891a595f28SAnthony Koo * Specifies lock/unlock. 25901a595f28SAnthony Koo */ 2591788408b7SAnthony Koo uint8_t lock; 25921a595f28SAnthony Koo /** 25931a595f28SAnthony Koo * HW can be unlocked separately from releasing the HW Lock Mgr. 25941a595f28SAnthony Koo * This flag is set if the client wishes to release the object. 25951a595f28SAnthony Koo */ 2596788408b7SAnthony Koo uint8_t should_release; 25971a595f28SAnthony Koo /** 25981a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 25991a595f28SAnthony Koo */ 2600788408b7SAnthony Koo uint8_t pad; 2601788408b7SAnthony Koo }; 2602788408b7SAnthony Koo 26031a595f28SAnthony Koo /** 26041a595f28SAnthony Koo * Definition of a DMUB_CMD__HW_LOCK command. 26051a595f28SAnthony Koo * Command is used by driver and FW. 26061a595f28SAnthony Koo */ 2607788408b7SAnthony Koo struct dmub_rb_cmd_lock_hw { 26081a595f28SAnthony Koo /** 26091a595f28SAnthony Koo * Command header. 26101a595f28SAnthony Koo */ 2611788408b7SAnthony Koo struct dmub_cmd_header header; 26121a595f28SAnthony Koo /** 26131a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 26141a595f28SAnthony Koo */ 2615788408b7SAnthony Koo struct dmub_cmd_lock_hw_data lock_hw_data; 2616788408b7SAnthony Koo }; 2617788408b7SAnthony Koo 26181a595f28SAnthony Koo /** 26191a595f28SAnthony Koo * ABM command sub-types. 26201a595f28SAnthony Koo */ 262184034ad4SAnthony Koo enum dmub_cmd_abm_type { 26221a595f28SAnthony Koo /** 26231a595f28SAnthony Koo * Initialize parameters for ABM algorithm. 26241a595f28SAnthony Koo * Data is passed through an indirect buffer. 26251a595f28SAnthony Koo */ 262684034ad4SAnthony Koo DMUB_CMD__ABM_INIT_CONFIG = 0, 26271a595f28SAnthony Koo /** 26281a595f28SAnthony Koo * Set OTG and panel HW instance. 26291a595f28SAnthony Koo */ 263084034ad4SAnthony Koo DMUB_CMD__ABM_SET_PIPE = 1, 26311a595f28SAnthony Koo /** 26321a595f28SAnthony Koo * Set user requested backklight level. 26331a595f28SAnthony Koo */ 263484034ad4SAnthony Koo DMUB_CMD__ABM_SET_BACKLIGHT = 2, 26351a595f28SAnthony Koo /** 26361a595f28SAnthony Koo * Set ABM operating/aggression level. 26371a595f28SAnthony Koo */ 263884034ad4SAnthony Koo DMUB_CMD__ABM_SET_LEVEL = 3, 26391a595f28SAnthony Koo /** 26401a595f28SAnthony Koo * Set ambient light level. 26411a595f28SAnthony Koo */ 264284034ad4SAnthony Koo DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 26431a595f28SAnthony Koo /** 26441a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 26451a595f28SAnthony Koo */ 264684034ad4SAnthony Koo DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2647b629a824SEric Yang 2648b629a824SEric Yang /** 2649b629a824SEric Yang * unregister vertical interrupt after steady state is reached 2650b629a824SEric Yang */ 2651b629a824SEric Yang DMUB_CMD__ABM_PAUSE = 6, 265284034ad4SAnthony Koo }; 265384034ad4SAnthony Koo 26541a595f28SAnthony Koo /** 26551a595f28SAnthony Koo * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 26561a595f28SAnthony Koo * Requirements: 26571a595f28SAnthony Koo * - Padded explicitly to 32-bit boundary. 26581a595f28SAnthony Koo * - Must ensure this structure matches the one on driver-side, 26591a595f28SAnthony Koo * otherwise it won't be aligned. 266084034ad4SAnthony Koo */ 266184034ad4SAnthony Koo struct abm_config_table { 26621a595f28SAnthony Koo /** 26631a595f28SAnthony Koo * Gamma curve thresholds, used for crgb conversion. 26641a595f28SAnthony Koo */ 266584034ad4SAnthony Koo uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 26661a595f28SAnthony Koo /** 26671a595f28SAnthony Koo * Gamma curve offsets, used for crgb conversion. 26681a595f28SAnthony Koo */ 2669b6402afeSAnthony Koo uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 26701a595f28SAnthony Koo /** 26711a595f28SAnthony Koo * Gamma curve slopes, used for crgb conversion. 26721a595f28SAnthony Koo */ 2673b6402afeSAnthony Koo uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 26741a595f28SAnthony Koo /** 26751a595f28SAnthony Koo * Custom backlight curve thresholds. 26761a595f28SAnthony Koo */ 2677b6402afeSAnthony Koo uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 26781a595f28SAnthony Koo /** 26791a595f28SAnthony Koo * Custom backlight curve offsets. 26801a595f28SAnthony Koo */ 2681b6402afeSAnthony Koo uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 26821a595f28SAnthony Koo /** 26831a595f28SAnthony Koo * Ambient light thresholds. 26841a595f28SAnthony Koo */ 2685b6402afeSAnthony Koo uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 26861a595f28SAnthony Koo /** 26871a595f28SAnthony Koo * Minimum programmable backlight. 26881a595f28SAnthony Koo */ 2689b6402afeSAnthony Koo uint16_t min_abm_backlight; // 122B 26901a595f28SAnthony Koo /** 26911a595f28SAnthony Koo * Minimum reduction values. 26921a595f28SAnthony Koo */ 2693b6402afeSAnthony Koo uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 26941a595f28SAnthony Koo /** 26951a595f28SAnthony Koo * Maximum reduction values. 26961a595f28SAnthony Koo */ 2697b6402afeSAnthony Koo uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 26981a595f28SAnthony Koo /** 26991a595f28SAnthony Koo * Bright positive gain. 27001a595f28SAnthony Koo */ 2701b6402afeSAnthony Koo uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 27021a595f28SAnthony Koo /** 27031a595f28SAnthony Koo * Dark negative gain. 27041a595f28SAnthony Koo */ 2705b6402afeSAnthony Koo uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 27061a595f28SAnthony Koo /** 27071a595f28SAnthony Koo * Hybrid factor. 27081a595f28SAnthony Koo */ 2709b6402afeSAnthony Koo uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 27101a595f28SAnthony Koo /** 27111a595f28SAnthony Koo * Contrast factor. 27121a595f28SAnthony Koo */ 2713b6402afeSAnthony Koo uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 27141a595f28SAnthony Koo /** 27151a595f28SAnthony Koo * Deviation gain. 27161a595f28SAnthony Koo */ 2717b6402afeSAnthony Koo uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 27181a595f28SAnthony Koo /** 27191a595f28SAnthony Koo * Minimum knee. 27201a595f28SAnthony Koo */ 2721b6402afeSAnthony Koo uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 27221a595f28SAnthony Koo /** 27231a595f28SAnthony Koo * Maximum knee. 27241a595f28SAnthony Koo */ 2725b6402afeSAnthony Koo uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 27261a595f28SAnthony Koo /** 27271a595f28SAnthony Koo * Unused. 27281a595f28SAnthony Koo */ 2729b6402afeSAnthony Koo uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 27301a595f28SAnthony Koo /** 27311a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 27321a595f28SAnthony Koo */ 2733b6402afeSAnthony Koo uint8_t pad3[3]; // 229B 27341a595f28SAnthony Koo /** 27351a595f28SAnthony Koo * Backlight ramp reduction. 27361a595f28SAnthony Koo */ 2737b6402afeSAnthony Koo uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 27381a595f28SAnthony Koo /** 27391a595f28SAnthony Koo * Backlight ramp start. 27401a595f28SAnthony Koo */ 2741b6402afeSAnthony Koo uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 274284034ad4SAnthony Koo }; 274384034ad4SAnthony Koo 27441a595f28SAnthony Koo /** 27451a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 27461a595f28SAnthony Koo */ 2747e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data { 27481a595f28SAnthony Koo /** 27491a595f28SAnthony Koo * OTG HW instance. 27501a595f28SAnthony Koo */ 27517b8a6362SAnthony Koo uint8_t otg_inst; 27521a595f28SAnthony Koo 27531a595f28SAnthony Koo /** 27541a595f28SAnthony Koo * Panel Control HW instance. 27551a595f28SAnthony Koo */ 27567b8a6362SAnthony Koo uint8_t panel_inst; 27571a595f28SAnthony Koo 27581a595f28SAnthony Koo /** 27591a595f28SAnthony Koo * Controls how ABM will interpret a set pipe or set level command. 27601a595f28SAnthony Koo */ 27617b8a6362SAnthony Koo uint8_t set_pipe_option; 27621a595f28SAnthony Koo 27631a595f28SAnthony Koo /** 27641a595f28SAnthony Koo * Unused. 27651a595f28SAnthony Koo * TODO: Remove. 27661a595f28SAnthony Koo */ 27671a595f28SAnthony Koo uint8_t ramping_boundary; 2768e6ea8c34SWyatt Wood }; 2769e6ea8c34SWyatt Wood 27701a595f28SAnthony Koo /** 27711a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 27721a595f28SAnthony Koo */ 2773e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe { 27741a595f28SAnthony Koo /** 27751a595f28SAnthony Koo * Command header. 27761a595f28SAnthony Koo */ 2777e6ea8c34SWyatt Wood struct dmub_cmd_header header; 27781a595f28SAnthony Koo 27791a595f28SAnthony Koo /** 27801a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 27811a595f28SAnthony Koo */ 2782e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2783e6ea8c34SWyatt Wood }; 2784e6ea8c34SWyatt Wood 27851a595f28SAnthony Koo /** 27861a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 27871a595f28SAnthony Koo */ 2788e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data { 27891a595f28SAnthony Koo /** 27901a595f28SAnthony Koo * Number of frames to ramp to backlight user level. 27911a595f28SAnthony Koo */ 2792e6ea8c34SWyatt Wood uint32_t frame_ramp; 27931a595f28SAnthony Koo 27941a595f28SAnthony Koo /** 27951a595f28SAnthony Koo * Requested backlight level from user. 27961a595f28SAnthony Koo */ 2797474ac4a8SYongqiang Sun uint32_t backlight_user_level; 2798e922057bSJake Wang 2799e922057bSJake Wang /** 280063de4f04SJake Wang * ABM control version. 2801e922057bSJake Wang */ 2802e922057bSJake Wang uint8_t version; 2803e922057bSJake Wang 2804e922057bSJake Wang /** 2805e922057bSJake Wang * Panel Control HW instance mask. 2806e922057bSJake Wang * Bit 0 is Panel Control HW instance 0. 2807e922057bSJake Wang * Bit 1 is Panel Control HW instance 1. 2808e922057bSJake Wang */ 2809e922057bSJake Wang uint8_t panel_mask; 2810e922057bSJake Wang 2811e922057bSJake Wang /** 2812e922057bSJake Wang * Explicit padding to 4 byte boundary. 2813e922057bSJake Wang */ 2814e922057bSJake Wang uint8_t pad[2]; 2815e6ea8c34SWyatt Wood }; 2816e6ea8c34SWyatt Wood 28171a595f28SAnthony Koo /** 28181a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 28191a595f28SAnthony Koo */ 2820e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight { 28211a595f28SAnthony Koo /** 28221a595f28SAnthony Koo * Command header. 28231a595f28SAnthony Koo */ 2824e6ea8c34SWyatt Wood struct dmub_cmd_header header; 28251a595f28SAnthony Koo 28261a595f28SAnthony Koo /** 28271a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 28281a595f28SAnthony Koo */ 2829e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2830e6ea8c34SWyatt Wood }; 2831e6ea8c34SWyatt Wood 28321a595f28SAnthony Koo /** 28331a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 28341a595f28SAnthony Koo */ 2835e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data { 28361a595f28SAnthony Koo /** 28371a595f28SAnthony Koo * Set current ABM operating/aggression level. 28381a595f28SAnthony Koo */ 2839e6ea8c34SWyatt Wood uint32_t level; 284063de4f04SJake Wang 284163de4f04SJake Wang /** 284263de4f04SJake Wang * ABM control version. 284363de4f04SJake Wang */ 284463de4f04SJake Wang uint8_t version; 284563de4f04SJake Wang 284663de4f04SJake Wang /** 284763de4f04SJake Wang * Panel Control HW instance mask. 284863de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 284963de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 285063de4f04SJake Wang */ 285163de4f04SJake Wang uint8_t panel_mask; 285263de4f04SJake Wang 285363de4f04SJake Wang /** 285463de4f04SJake Wang * Explicit padding to 4 byte boundary. 285563de4f04SJake Wang */ 285663de4f04SJake Wang uint8_t pad[2]; 2857e6ea8c34SWyatt Wood }; 2858e6ea8c34SWyatt Wood 28591a595f28SAnthony Koo /** 28601a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 28611a595f28SAnthony Koo */ 2862e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level { 28631a595f28SAnthony Koo /** 28641a595f28SAnthony Koo * Command header. 28651a595f28SAnthony Koo */ 2866e6ea8c34SWyatt Wood struct dmub_cmd_header header; 28671a595f28SAnthony Koo 28681a595f28SAnthony Koo /** 28691a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 28701a595f28SAnthony Koo */ 2871e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data abm_set_level_data; 2872e6ea8c34SWyatt Wood }; 2873e6ea8c34SWyatt Wood 28741a595f28SAnthony Koo /** 28751a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 28761a595f28SAnthony Koo */ 2877e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data { 28781a595f28SAnthony Koo /** 28791a595f28SAnthony Koo * Ambient light sensor reading from OS. 28801a595f28SAnthony Koo */ 2881e6ea8c34SWyatt Wood uint32_t ambient_lux; 288263de4f04SJake Wang 288363de4f04SJake Wang /** 288463de4f04SJake Wang * ABM control version. 288563de4f04SJake Wang */ 288663de4f04SJake Wang uint8_t version; 288763de4f04SJake Wang 288863de4f04SJake Wang /** 288963de4f04SJake Wang * Panel Control HW instance mask. 289063de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 289163de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 289263de4f04SJake Wang */ 289363de4f04SJake Wang uint8_t panel_mask; 289463de4f04SJake Wang 289563de4f04SJake Wang /** 289663de4f04SJake Wang * Explicit padding to 4 byte boundary. 289763de4f04SJake Wang */ 289863de4f04SJake Wang uint8_t pad[2]; 2899e6ea8c34SWyatt Wood }; 2900e6ea8c34SWyatt Wood 29011a595f28SAnthony Koo /** 29021a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 29031a595f28SAnthony Koo */ 2904e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level { 29051a595f28SAnthony Koo /** 29061a595f28SAnthony Koo * Command header. 29071a595f28SAnthony Koo */ 2908e6ea8c34SWyatt Wood struct dmub_cmd_header header; 29091a595f28SAnthony Koo 29101a595f28SAnthony Koo /** 29111a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 29121a595f28SAnthony Koo */ 2913e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2914e6ea8c34SWyatt Wood }; 2915e6ea8c34SWyatt Wood 29161a595f28SAnthony Koo /** 29171a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 29181a595f28SAnthony Koo */ 2919e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data { 29201a595f28SAnthony Koo /** 29211a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 29221a595f28SAnthony Koo * TODO: Convert to uint8_t. 29231a595f28SAnthony Koo */ 2924e6ea8c34SWyatt Wood uint32_t fractional_pwm; 292563de4f04SJake Wang 292663de4f04SJake Wang /** 292763de4f04SJake Wang * ABM control version. 292863de4f04SJake Wang */ 292963de4f04SJake Wang uint8_t version; 293063de4f04SJake Wang 293163de4f04SJake Wang /** 293263de4f04SJake Wang * Panel Control HW instance mask. 293363de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 293463de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 293563de4f04SJake Wang */ 293663de4f04SJake Wang uint8_t panel_mask; 293763de4f04SJake Wang 293863de4f04SJake Wang /** 293963de4f04SJake Wang * Explicit padding to 4 byte boundary. 294063de4f04SJake Wang */ 294163de4f04SJake Wang uint8_t pad[2]; 2942e6ea8c34SWyatt Wood }; 2943e6ea8c34SWyatt Wood 29441a595f28SAnthony Koo /** 29451a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 29461a595f28SAnthony Koo */ 2947e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac { 29481a595f28SAnthony Koo /** 29491a595f28SAnthony Koo * Command header. 29501a595f28SAnthony Koo */ 2951e6ea8c34SWyatt Wood struct dmub_cmd_header header; 29521a595f28SAnthony Koo 29531a595f28SAnthony Koo /** 29541a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 29551a595f28SAnthony Koo */ 2956e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2957e6ea8c34SWyatt Wood }; 2958e6ea8c34SWyatt Wood 29591a595f28SAnthony Koo /** 29601a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 29611a595f28SAnthony Koo */ 296216012806SWyatt Wood struct dmub_cmd_abm_init_config_data { 29631a595f28SAnthony Koo /** 29641a595f28SAnthony Koo * Location of indirect buffer used to pass init data to ABM. 29651a595f28SAnthony Koo */ 296616012806SWyatt Wood union dmub_addr src; 29671a595f28SAnthony Koo 29681a595f28SAnthony Koo /** 29691a595f28SAnthony Koo * Indirect buffer length. 29701a595f28SAnthony Koo */ 297116012806SWyatt Wood uint16_t bytes; 297263de4f04SJake Wang 297363de4f04SJake Wang 297463de4f04SJake Wang /** 297563de4f04SJake Wang * ABM control version. 297663de4f04SJake Wang */ 297763de4f04SJake Wang uint8_t version; 297863de4f04SJake Wang 297963de4f04SJake Wang /** 298063de4f04SJake Wang * Panel Control HW instance mask. 298163de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 298263de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 298363de4f04SJake Wang */ 298463de4f04SJake Wang uint8_t panel_mask; 298563de4f04SJake Wang 298663de4f04SJake Wang /** 298763de4f04SJake Wang * Explicit padding to 4 byte boundary. 298863de4f04SJake Wang */ 298963de4f04SJake Wang uint8_t pad[2]; 299016012806SWyatt Wood }; 299116012806SWyatt Wood 29921a595f28SAnthony Koo /** 29931a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 29941a595f28SAnthony Koo */ 299516012806SWyatt Wood struct dmub_rb_cmd_abm_init_config { 29961a595f28SAnthony Koo /** 29971a595f28SAnthony Koo * Command header. 29981a595f28SAnthony Koo */ 299916012806SWyatt Wood struct dmub_cmd_header header; 30001a595f28SAnthony Koo 30011a595f28SAnthony Koo /** 30021a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 30031a595f28SAnthony Koo */ 300416012806SWyatt Wood struct dmub_cmd_abm_init_config_data abm_init_config_data; 300516012806SWyatt Wood }; 300616012806SWyatt Wood 30071a595f28SAnthony Koo /** 3008b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3009b629a824SEric Yang */ 3010b629a824SEric Yang 3011b629a824SEric Yang struct dmub_cmd_abm_pause_data { 3012b629a824SEric Yang 3013b629a824SEric Yang /** 3014b629a824SEric Yang * Panel Control HW instance mask. 3015b629a824SEric Yang * Bit 0 is Panel Control HW instance 0. 3016b629a824SEric Yang * Bit 1 is Panel Control HW instance 1. 3017b629a824SEric Yang */ 3018b629a824SEric Yang uint8_t panel_mask; 3019b629a824SEric Yang 3020b629a824SEric Yang /** 3021b629a824SEric Yang * OTG hw instance 3022b629a824SEric Yang */ 3023b629a824SEric Yang uint8_t otg_inst; 3024b629a824SEric Yang 3025b629a824SEric Yang /** 3026b629a824SEric Yang * Enable or disable ABM pause 3027b629a824SEric Yang */ 3028b629a824SEric Yang uint8_t enable; 3029b629a824SEric Yang 3030b629a824SEric Yang /** 3031b629a824SEric Yang * Explicit padding to 4 byte boundary. 3032b629a824SEric Yang */ 3033b629a824SEric Yang uint8_t pad[1]; 3034b629a824SEric Yang }; 3035b629a824SEric Yang 3036b629a824SEric Yang /** 3037b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 3038b629a824SEric Yang */ 3039b629a824SEric Yang struct dmub_rb_cmd_abm_pause { 3040b629a824SEric Yang /** 3041b629a824SEric Yang * Command header. 3042b629a824SEric Yang */ 3043b629a824SEric Yang struct dmub_cmd_header header; 3044b629a824SEric Yang 3045b629a824SEric Yang /** 3046b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3047b629a824SEric Yang */ 3048b629a824SEric Yang struct dmub_cmd_abm_pause_data abm_pause_data; 3049b629a824SEric Yang }; 3050b629a824SEric Yang 3051b629a824SEric Yang /** 30521a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 30531a595f28SAnthony Koo */ 305434ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data { 30551a595f28SAnthony Koo /** 30561a595f28SAnthony Koo * DMUB feature capabilities. 30571a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features. 30581a595f28SAnthony Koo */ 305934ba432cSAnthony Koo struct dmub_feature_caps feature_caps; 306034ba432cSAnthony Koo }; 306134ba432cSAnthony Koo 30621a595f28SAnthony Koo /** 30631a595f28SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 30641a595f28SAnthony Koo */ 306534ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps { 30661a595f28SAnthony Koo /** 30671a595f28SAnthony Koo * Command header. 30681a595f28SAnthony Koo */ 306934ba432cSAnthony Koo struct dmub_cmd_header header; 30701a595f28SAnthony Koo /** 30711a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 30721a595f28SAnthony Koo */ 307334ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 307434ba432cSAnthony Koo }; 307534ba432cSAnthony Koo 3076b09c1fffSLeo (Hanghong) Ma /** 3077b09c1fffSLeo (Hanghong) Ma * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3078b09c1fffSLeo (Hanghong) Ma */ 3079b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_visual_confirm_color_data { 3080b09c1fffSLeo (Hanghong) Ma /** 3081b09c1fffSLeo (Hanghong) Ma * DMUB feature capabilities. 3082b09c1fffSLeo (Hanghong) Ma * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3083b09c1fffSLeo (Hanghong) Ma */ 3084b09c1fffSLeo (Hanghong) Ma struct dmub_visual_confirm_color visual_confirm_color; 3085b09c1fffSLeo (Hanghong) Ma }; 3086b09c1fffSLeo (Hanghong) Ma 3087b09c1fffSLeo (Hanghong) Ma /** 3088b09c1fffSLeo (Hanghong) Ma * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3089b09c1fffSLeo (Hanghong) Ma */ 3090b09c1fffSLeo (Hanghong) Ma struct dmub_rb_cmd_get_visual_confirm_color { 3091b09c1fffSLeo (Hanghong) Ma /** 3092b09c1fffSLeo (Hanghong) Ma * Command header. 3093b09c1fffSLeo (Hanghong) Ma */ 3094b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_header header; 3095b09c1fffSLeo (Hanghong) Ma /** 3096b09c1fffSLeo (Hanghong) Ma * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3097b09c1fffSLeo (Hanghong) Ma */ 3098b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 3099b09c1fffSLeo (Hanghong) Ma }; 3100b09c1fffSLeo (Hanghong) Ma 3101592a6318SAnthony Koo struct dmub_optc_state { 3102592a6318SAnthony Koo uint32_t v_total_max; 3103592a6318SAnthony Koo uint32_t v_total_min; 3104592a6318SAnthony Koo uint32_t tg_inst; 3105592a6318SAnthony Koo }; 3106592a6318SAnthony Koo 3107592a6318SAnthony Koo struct dmub_rb_cmd_drr_update { 3108592a6318SAnthony Koo struct dmub_cmd_header header; 3109592a6318SAnthony Koo struct dmub_optc_state dmub_optc_state_req; 3110592a6318SAnthony Koo }; 3111592a6318SAnthony Koo 311200fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 311300fa7f03SRodrigo Siqueira uint32_t pix_clk_100hz; 311400fa7f03SRodrigo Siqueira uint8_t max_ramp_step; 311500fa7f03SRodrigo Siqueira uint8_t pipes; 311600fa7f03SRodrigo Siqueira uint8_t min_refresh_in_hz; 3117d3981ee7SAnthony Koo uint8_t pipe_count; 3118d3981ee7SAnthony Koo uint8_t pipe_index[4]; 311900fa7f03SRodrigo Siqueira }; 312000fa7f03SRodrigo Siqueira 312100fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config { 312200fa7f03SRodrigo Siqueira uint8_t fams_enabled; 312300fa7f03SRodrigo Siqueira uint8_t visual_confirm_enabled; 3124d3981ee7SAnthony Koo uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 3125d3981ee7SAnthony Koo struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 312600fa7f03SRodrigo Siqueira }; 312700fa7f03SRodrigo Siqueira 312800fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch { 312900fa7f03SRodrigo Siqueira struct dmub_cmd_header header; 313000fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 313100fa7f03SRodrigo Siqueira }; 313200fa7f03SRodrigo Siqueira 3133b04cb192SNicholas Kazlauskas /** 3134b04cb192SNicholas Kazlauskas * enum dmub_cmd_panel_cntl_type - Panel control command. 3135b04cb192SNicholas Kazlauskas */ 3136b04cb192SNicholas Kazlauskas enum dmub_cmd_panel_cntl_type { 3137b04cb192SNicholas Kazlauskas /** 3138b04cb192SNicholas Kazlauskas * Initializes embedded panel hardware blocks. 3139b04cb192SNicholas Kazlauskas */ 3140b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 3141b04cb192SNicholas Kazlauskas /** 3142b04cb192SNicholas Kazlauskas * Queries backlight info for the embedded panel. 3143b04cb192SNicholas Kazlauskas */ 3144b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 3145b04cb192SNicholas Kazlauskas }; 3146b04cb192SNicholas Kazlauskas 3147b04cb192SNicholas Kazlauskas /** 3148b04cb192SNicholas Kazlauskas * struct dmub_cmd_panel_cntl_data - Panel control data. 3149b04cb192SNicholas Kazlauskas */ 3150b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data { 3151b04cb192SNicholas Kazlauskas uint32_t inst; /**< panel instance */ 3152b04cb192SNicholas Kazlauskas uint32_t current_backlight; /* in/out */ 3153b04cb192SNicholas Kazlauskas uint32_t bl_pwm_cntl; /* in/out */ 3154b04cb192SNicholas Kazlauskas uint32_t bl_pwm_period_cntl; /* in/out */ 3155b04cb192SNicholas Kazlauskas uint32_t bl_pwm_ref_div1; /* in/out */ 3156b04cb192SNicholas Kazlauskas uint8_t is_backlight_on : 1; /* in/out */ 3157b04cb192SNicholas Kazlauskas uint8_t is_powered_on : 1; /* in/out */ 3158a91b402dSCharlene Liu uint8_t padding[3]; 3159a91b402dSCharlene Liu uint32_t bl_pwm_ref_div2; /* in/out */ 3160a91b402dSCharlene Liu uint8_t reserved[4]; 3161b04cb192SNicholas Kazlauskas }; 3162b04cb192SNicholas Kazlauskas 3163b04cb192SNicholas Kazlauskas /** 3164b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_panel_cntl - Panel control command. 3165b04cb192SNicholas Kazlauskas */ 3166b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl { 3167b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 3168b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data data; /**< payload */ 3169b04cb192SNicholas Kazlauskas }; 3170b04cb192SNicholas Kazlauskas 31711a595f28SAnthony Koo /** 31721a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 31731a595f28SAnthony Koo */ 31741a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data { 31751a595f28SAnthony Koo uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3176e0886e1fSTony Tascioglu uint8_t bypass_panel_control_wait; 31770888aa30SAnthony Koo uint8_t reserved_0[2]; /**< For future use */ 31781a595f28SAnthony Koo uint8_t panel_inst; /**< LVTMA control instance */ 31791a595f28SAnthony Koo uint8_t reserved_1[3]; /**< For future use */ 31801a595f28SAnthony Koo }; 31811a595f28SAnthony Koo 31821a595f28SAnthony Koo /** 31831a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 31841a595f28SAnthony Koo */ 31851a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control { 31861a595f28SAnthony Koo /** 31871a595f28SAnthony Koo * Command header. 31881a595f28SAnthony Koo */ 31891a595f28SAnthony Koo struct dmub_cmd_header header; 31901a595f28SAnthony Koo /** 31911a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 31921a595f28SAnthony Koo */ 31931a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data data; 31941a595f28SAnthony Koo }; 31951a595f28SAnthony Koo 3196592a6318SAnthony Koo /** 319741f91315SNicholas Kazlauskas * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 319841f91315SNicholas Kazlauskas */ 319941f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data { 320041f91315SNicholas Kazlauskas uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 320141f91315SNicholas Kazlauskas uint8_t is_usb; /**< is phy is usb */ 320241f91315SNicholas Kazlauskas uint8_t is_dp_alt_disable; /**< is dp alt disable */ 320341f91315SNicholas Kazlauskas uint8_t is_dp4; /**< is dp in 4 lane */ 320441f91315SNicholas Kazlauskas }; 320541f91315SNicholas Kazlauskas 320641f91315SNicholas Kazlauskas /** 320741f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 320841f91315SNicholas Kazlauskas */ 320941f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt { 321041f91315SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 321141f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 321241f91315SNicholas Kazlauskas }; 321341f91315SNicholas Kazlauskas 321441f91315SNicholas Kazlauskas /** 3215021eaef8SAnthony Koo * Maximum number of bytes a chunk sent to DMUB for parsing 3216021eaef8SAnthony Koo */ 3217021eaef8SAnthony Koo #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3218021eaef8SAnthony Koo 3219021eaef8SAnthony Koo /** 3220021eaef8SAnthony Koo * Represent a chunk of CEA blocks sent to DMUB for parsing 3221021eaef8SAnthony Koo */ 3222021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea { 3223021eaef8SAnthony Koo uint16_t offset; /**< offset into the CEA block */ 3224021eaef8SAnthony Koo uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3225eb9e59ebSOliver Logush uint16_t cea_total_length; /**< total length of the CEA block */ 3226021eaef8SAnthony Koo uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3227021eaef8SAnthony Koo uint8_t pad[3]; /**< padding and for future expansion */ 3228021eaef8SAnthony Koo }; 3229021eaef8SAnthony Koo 3230021eaef8SAnthony Koo /** 3231021eaef8SAnthony Koo * Result of VSDB parsing from CEA block 3232021eaef8SAnthony Koo */ 3233021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb { 3234021eaef8SAnthony Koo uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3235021eaef8SAnthony Koo uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3236021eaef8SAnthony Koo uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3237021eaef8SAnthony Koo uint16_t min_frame_rate; /**< Maximum frame rate */ 3238021eaef8SAnthony Koo uint16_t max_frame_rate; /**< Minimum frame rate */ 3239021eaef8SAnthony Koo }; 3240021eaef8SAnthony Koo 3241021eaef8SAnthony Koo /** 3242021eaef8SAnthony Koo * Result of sending a CEA chunk 3243021eaef8SAnthony Koo */ 3244021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack { 3245021eaef8SAnthony Koo uint16_t offset; /**< offset of the chunk into the CEA block */ 3246021eaef8SAnthony Koo uint8_t success; /**< 1 if this sending of chunk succeeded */ 3247021eaef8SAnthony Koo uint8_t pad; /**< padding and for future expansion */ 3248021eaef8SAnthony Koo }; 3249021eaef8SAnthony Koo 3250021eaef8SAnthony Koo /** 3251021eaef8SAnthony Koo * Specify whether the result is an ACK/NACK or the parsing has finished 3252021eaef8SAnthony Koo */ 3253021eaef8SAnthony Koo enum dmub_cmd_edid_cea_reply_type { 3254021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3255021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3256021eaef8SAnthony Koo }; 3257021eaef8SAnthony Koo 3258021eaef8SAnthony Koo /** 3259021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 3260021eaef8SAnthony Koo */ 3261021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea { 3262021eaef8SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 3263021eaef8SAnthony Koo union dmub_cmd_edid_cea_data { 3264021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3265021eaef8SAnthony Koo struct dmub_cmd_edid_cea_output { /**< output with results */ 3266021eaef8SAnthony Koo uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3267021eaef8SAnthony Koo union { 3268021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3269021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack ack; 3270021eaef8SAnthony Koo }; 3271021eaef8SAnthony Koo } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3272021eaef8SAnthony Koo } data; /**< Command data */ 3273021eaef8SAnthony Koo 3274021eaef8SAnthony Koo }; 3275021eaef8SAnthony Koo 3276021eaef8SAnthony Koo /** 3277c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3278c595fb05SWenjing Liu */ 3279c595fb05SWenjing Liu struct dmub_cmd_cable_id_input { 3280c595fb05SWenjing Liu uint8_t phy_inst; /**< phy inst for cable id data */ 3281c595fb05SWenjing Liu }; 3282c595fb05SWenjing Liu 3283c595fb05SWenjing Liu /** 3284c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3285c595fb05SWenjing Liu */ 3286c595fb05SWenjing Liu struct dmub_cmd_cable_id_output { 3287c595fb05SWenjing Liu uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3288c595fb05SWenjing Liu uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3289c595fb05SWenjing Liu uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3290c595fb05SWenjing Liu uint8_t RESERVED :2; /**< reserved means not defined */ 3291c595fb05SWenjing Liu }; 3292c595fb05SWenjing Liu 3293c595fb05SWenjing Liu /** 3294c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3295c595fb05SWenjing Liu */ 3296c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id { 3297c595fb05SWenjing Liu struct dmub_cmd_header header; /**< Command header */ 3298c595fb05SWenjing Liu /** 3299c595fb05SWenjing Liu * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3300c595fb05SWenjing Liu */ 3301c595fb05SWenjing Liu union dmub_cmd_cable_id_data { 3302c595fb05SWenjing Liu struct dmub_cmd_cable_id_input input; /**< Input */ 3303c595fb05SWenjing Liu struct dmub_cmd_cable_id_output output; /**< Output */ 3304c595fb05SWenjing Liu uint8_t output_raw; /**< Raw data output */ 3305c595fb05SWenjing Liu } data; 3306c595fb05SWenjing Liu }; 3307c595fb05SWenjing Liu 33081fb695d9SAnthony Koo /** 33091fb695d9SAnthony Koo * Command type of a DMUB_CMD__SECURE_DISPLAY command 33101fb695d9SAnthony Koo */ 3311c0459bddSAlan Liu enum dmub_cmd_secure_display_type { 33121fb695d9SAnthony Koo DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3313c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3314c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3315c0459bddSAlan Liu }; 3316c0459bddSAlan Liu 33171fb695d9SAnthony Koo /** 33181fb695d9SAnthony Koo * Definition of a DMUB_CMD__SECURE_DISPLAY command 33191fb695d9SAnthony Koo */ 3320c0459bddSAlan Liu struct dmub_rb_cmd_secure_display { 3321c0459bddSAlan Liu struct dmub_cmd_header header; 33221fb695d9SAnthony Koo /** 33231fb695d9SAnthony Koo * Data passed from driver to dmub firmware. 33241fb695d9SAnthony Koo */ 3325c0459bddSAlan Liu struct dmub_cmd_roi_info { 3326c0459bddSAlan Liu uint16_t x_start; 3327c0459bddSAlan Liu uint16_t x_end; 3328c0459bddSAlan Liu uint16_t y_start; 3329c0459bddSAlan Liu uint16_t y_end; 3330c0459bddSAlan Liu uint8_t otg_id; 3331c0459bddSAlan Liu uint8_t phy_id; 3332c0459bddSAlan Liu } roi_info; 3333c0459bddSAlan Liu }; 3334c0459bddSAlan Liu 3335c595fb05SWenjing Liu /** 3336592a6318SAnthony Koo * union dmub_rb_cmd - DMUB inbox command. 3337592a6318SAnthony Koo */ 33387c008829SNicholas Kazlauskas union dmub_rb_cmd { 3339592a6318SAnthony Koo /** 3340592a6318SAnthony Koo * Elements shared with all commands. 3341592a6318SAnthony Koo */ 33427c008829SNicholas Kazlauskas struct dmub_rb_cmd_common cmd_common; 3343592a6318SAnthony Koo /** 3344592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3345592a6318SAnthony Koo */ 3346592a6318SAnthony Koo struct dmub_rb_cmd_read_modify_write read_modify_write; 3347592a6318SAnthony Koo /** 3348592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3349592a6318SAnthony Koo */ 3350592a6318SAnthony Koo struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3351592a6318SAnthony Koo /** 3352592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3353592a6318SAnthony Koo */ 3354592a6318SAnthony Koo struct dmub_rb_cmd_burst_write burst_write; 3355592a6318SAnthony Koo /** 3356592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_REG_WAIT command. 3357592a6318SAnthony Koo */ 3358592a6318SAnthony Koo struct dmub_rb_cmd_reg_wait reg_wait; 3359592a6318SAnthony Koo /** 3360592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3361592a6318SAnthony Koo */ 33627c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3363592a6318SAnthony Koo /** 3364592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3365592a6318SAnthony Koo */ 33667c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3367592a6318SAnthony Koo /** 3368592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3369592a6318SAnthony Koo */ 33707c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3371592a6318SAnthony Koo /** 3372592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3373592a6318SAnthony Koo */ 33747c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init dpphy_init; 3375592a6318SAnthony Koo /** 3376592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3377592a6318SAnthony Koo */ 33787c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 33791a595f28SAnthony Koo /** 3380e383b127SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 3381e383b127SNicholas Kazlauskas */ 3382e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control domain_control; 3383e383b127SNicholas Kazlauskas /** 33841a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 33851a595f28SAnthony Koo */ 3386d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version psr_set_version; 33871a595f28SAnthony Koo /** 33881a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 33891a595f28SAnthony Koo */ 33907c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 33911a595f28SAnthony Koo /** 33921a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 33931a595f28SAnthony Koo */ 3394d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_enable psr_enable; 33951a595f28SAnthony Koo /** 33961a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 33971a595f28SAnthony Koo */ 33987c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level psr_set_level; 33991a595f28SAnthony Koo /** 34001a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 34011a595f28SAnthony Koo */ 3402672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static psr_force_static; 3403592a6318SAnthony Koo /** 340483eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 340583eb5385SDavid Zhang */ 340683eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 340783eb5385SDavid Zhang /** 340883eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 340983eb5385SDavid Zhang */ 341083eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info update_cursor_info; 341183eb5385SDavid Zhang /** 341283eb5385SDavid Zhang * Definition of a DMUB_CMD__HW_LOCK command. 341383eb5385SDavid Zhang * Command is used by driver and FW. 341483eb5385SDavid Zhang */ 341583eb5385SDavid Zhang struct dmub_rb_cmd_lock_hw lock_hw; 341683eb5385SDavid Zhang /** 341783eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 341883eb5385SDavid Zhang */ 341983eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 342083eb5385SDavid Zhang /** 3421e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3422e5dfcd27SRobin Chen */ 3423e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3424e5dfcd27SRobin Chen /** 3425592a6318SAnthony Koo * Definition of a DMUB_CMD__PLAT_54186_WA command. 3426592a6318SAnthony Koo */ 3427bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3428592a6318SAnthony Koo /** 3429592a6318SAnthony Koo * Definition of a DMUB_CMD__MALL command. 3430592a6318SAnthony Koo */ 343152f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall mall; 3432b04cb192SNicholas Kazlauskas /** 3433ac2e555eSAurabindo Pillai * Definition of a DMUB_CMD__CAB command. 3434ac2e555eSAurabindo Pillai */ 3435ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss cab; 343685f4bc0cSAlvin Lee 343785f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 343885f4bc0cSAlvin Lee 3439ac2e555eSAurabindo Pillai /** 3440b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3441b04cb192SNicholas Kazlauskas */ 3442b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3443b04cb192SNicholas Kazlauskas 3444b04cb192SNicholas Kazlauskas /** 3445b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3446b04cb192SNicholas Kazlauskas */ 3447b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3448b04cb192SNicholas Kazlauskas 3449b04cb192SNicholas Kazlauskas /** 3450b04cb192SNicholas Kazlauskas * Definition of DMUB_CMD__PANEL_CNTL commands. 3451b04cb192SNicholas Kazlauskas */ 3452b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl panel_cntl; 34531a595f28SAnthony Koo /** 34541a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 34551a595f28SAnthony Koo */ 3456e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 34571a595f28SAnthony Koo 34581a595f28SAnthony Koo /** 34591a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 34601a595f28SAnthony Koo */ 3461e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 34621a595f28SAnthony Koo 34631a595f28SAnthony Koo /** 34641a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 34651a595f28SAnthony Koo */ 3466e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level abm_set_level; 34671a595f28SAnthony Koo 34681a595f28SAnthony Koo /** 34691a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 34701a595f28SAnthony Koo */ 3471e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 34721a595f28SAnthony Koo 34731a595f28SAnthony Koo /** 34741a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 34751a595f28SAnthony Koo */ 3476e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 34771a595f28SAnthony Koo 34781a595f28SAnthony Koo /** 34791a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 34801a595f28SAnthony Koo */ 348116012806SWyatt Wood struct dmub_rb_cmd_abm_init_config abm_init_config; 34821a595f28SAnthony Koo 34831a595f28SAnthony Koo /** 3484b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 3485b629a824SEric Yang */ 3486b629a824SEric Yang struct dmub_rb_cmd_abm_pause abm_pause; 3487b629a824SEric Yang 3488b629a824SEric Yang /** 34891a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 34901a595f28SAnthony Koo */ 3491d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access dp_aux_access; 34921a595f28SAnthony Koo 34931a595f28SAnthony Koo /** 3494592a6318SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3495592a6318SAnthony Koo */ 3496592a6318SAnthony Koo struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3497592a6318SAnthony Koo 3498592a6318SAnthony Koo /** 3499592a6318SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 35001a595f28SAnthony Koo */ 350134ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3502b09c1fffSLeo (Hanghong) Ma 3503b09c1fffSLeo (Hanghong) Ma /** 3504b09c1fffSLeo (Hanghong) Ma * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3505b09c1fffSLeo (Hanghong) Ma */ 3506b09c1fffSLeo (Hanghong) Ma struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3507592a6318SAnthony Koo struct dmub_rb_cmd_drr_update drr_update; 350800fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 350900fa7f03SRodrigo Siqueira 35101a595f28SAnthony Koo /** 35111a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 35121a595f28SAnthony Koo */ 35131a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control lvtma_control; 3514021eaef8SAnthony Koo /** 351541f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 351641f91315SNicholas Kazlauskas */ 351741f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 351841f91315SNicholas Kazlauskas /** 351976724b76SJimmy Kizito * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 352076724b76SJimmy Kizito */ 352176724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 352276724b76SJimmy Kizito /** 352371af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 352471af9d46SMeenakshikumar Somasundaram */ 352571af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access set_config_access; 352671af9d46SMeenakshikumar Somasundaram /** 3527139a3311SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3528139a3311SMeenakshikumar Somasundaram */ 3529139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3530139a3311SMeenakshikumar Somasundaram /** 3531021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 3532021eaef8SAnthony Koo */ 3533021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea edid_cea; 3534c595fb05SWenjing Liu /** 3535c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3536c595fb05SWenjing Liu */ 3537c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3538ea5a4db9SAnthony Koo 3539ea5a4db9SAnthony Koo /** 3540ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3541ea5a4db9SAnthony Koo */ 3542ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state query_hpd; 35436f4f8ff5SMeenakshikumar Somasundaram /** 3544c0459bddSAlan Liu * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3545c0459bddSAlan Liu */ 3546c0459bddSAlan Liu struct dmub_rb_cmd_secure_display secure_display; 35471fb695d9SAnthony Koo 3548c0459bddSAlan Liu /** 35496f4f8ff5SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 35506f4f8ff5SMeenakshikumar Somasundaram */ 35516f4f8ff5SMeenakshikumar Somasundaram struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3552*27664177SAnthony Koo /** 3553*27664177SAnthony Koo * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 3554*27664177SAnthony Koo */ 3555*27664177SAnthony Koo struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 35567c008829SNicholas Kazlauskas }; 35577c008829SNicholas Kazlauskas 3558592a6318SAnthony Koo /** 3559592a6318SAnthony Koo * union dmub_rb_out_cmd - Outbox command 3560592a6318SAnthony Koo */ 3561d9beecfcSAnthony Koo union dmub_rb_out_cmd { 3562592a6318SAnthony Koo /** 3563592a6318SAnthony Koo * Parameters common to every command. 3564592a6318SAnthony Koo */ 3565d9beecfcSAnthony Koo struct dmub_rb_cmd_common cmd_common; 3566592a6318SAnthony Koo /** 3567592a6318SAnthony Koo * AUX reply command. 3568592a6318SAnthony Koo */ 3569d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3570592a6318SAnthony Koo /** 3571592a6318SAnthony Koo * HPD notify command. 3572592a6318SAnthony Koo */ 3573d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 357471af9d46SMeenakshikumar Somasundaram /** 357571af9d46SMeenakshikumar Somasundaram * SET_CONFIG reply command. 357671af9d46SMeenakshikumar Somasundaram */ 357771af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3578669018a9SMustapha Ghaddar /** 35798af54c61SMustapha Ghaddar * DPIA notification command. 3580669018a9SMustapha Ghaddar */ 35818af54c61SMustapha Ghaddar struct dmub_rb_cmd_dpia_notification dpia_notification; 3582d9beecfcSAnthony Koo }; 35837c008829SNicholas Kazlauskas #pragma pack(pop) 35847c008829SNicholas Kazlauskas 358584034ad4SAnthony Koo 358684034ad4SAnthony Koo //============================================================================== 358784034ad4SAnthony Koo //</DMUB_CMD>=================================================================== 358884034ad4SAnthony Koo //============================================================================== 358984034ad4SAnthony Koo //< DMUB_RB>==================================================================== 359084034ad4SAnthony Koo //============================================================================== 359184034ad4SAnthony Koo 359284034ad4SAnthony Koo #if defined(__cplusplus) 359384034ad4SAnthony Koo extern "C" { 359484034ad4SAnthony Koo #endif 359584034ad4SAnthony Koo 3596592a6318SAnthony Koo /** 3597592a6318SAnthony Koo * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3598592a6318SAnthony Koo */ 359984034ad4SAnthony Koo struct dmub_rb_init_params { 3600592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 3601592a6318SAnthony Koo void *base_address; /**< CPU base address for ring's data */ 3602592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3603592a6318SAnthony Koo uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3604592a6318SAnthony Koo uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 360584034ad4SAnthony Koo }; 360684034ad4SAnthony Koo 3607592a6318SAnthony Koo /** 3608592a6318SAnthony Koo * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3609592a6318SAnthony Koo */ 361084034ad4SAnthony Koo struct dmub_rb { 3611592a6318SAnthony Koo void *base_address; /**< CPU address for the ring's data */ 3612592a6318SAnthony Koo uint32_t rptr; /**< Read pointer for consumer in bytes */ 3613592a6318SAnthony Koo uint32_t wrpt; /**< Write pointer for producer in bytes */ 3614592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 361584034ad4SAnthony Koo 3616592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 3617592a6318SAnthony Koo void *dmub; /**< Pointer to the DMUB interface */ 361884034ad4SAnthony Koo }; 361984034ad4SAnthony Koo 3620592a6318SAnthony Koo /** 3621592a6318SAnthony Koo * @brief Checks if the ringbuffer is empty. 3622592a6318SAnthony Koo * 3623592a6318SAnthony Koo * @param rb DMUB Ringbuffer 3624592a6318SAnthony Koo * @return true if empty 3625592a6318SAnthony Koo * @return false otherwise 3626592a6318SAnthony Koo */ 362784034ad4SAnthony Koo static inline bool dmub_rb_empty(struct dmub_rb *rb) 362884034ad4SAnthony Koo { 362984034ad4SAnthony Koo return (rb->wrpt == rb->rptr); 363084034ad4SAnthony Koo } 363184034ad4SAnthony Koo 3632592a6318SAnthony Koo /** 3633592a6318SAnthony Koo * @brief Checks if the ringbuffer is full 3634592a6318SAnthony Koo * 3635592a6318SAnthony Koo * @param rb DMUB Ringbuffer 3636592a6318SAnthony Koo * @return true if full 3637592a6318SAnthony Koo * @return false otherwise 3638592a6318SAnthony Koo */ 363984034ad4SAnthony Koo static inline bool dmub_rb_full(struct dmub_rb *rb) 364084034ad4SAnthony Koo { 364184034ad4SAnthony Koo uint32_t data_count; 364284034ad4SAnthony Koo 364384034ad4SAnthony Koo if (rb->wrpt >= rb->rptr) 364484034ad4SAnthony Koo data_count = rb->wrpt - rb->rptr; 364584034ad4SAnthony Koo else 364684034ad4SAnthony Koo data_count = rb->capacity - (rb->rptr - rb->wrpt); 364784034ad4SAnthony Koo 364884034ad4SAnthony Koo return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 364984034ad4SAnthony Koo } 365084034ad4SAnthony Koo 3651592a6318SAnthony Koo /** 3652592a6318SAnthony Koo * @brief Pushes a command into the ringbuffer 3653592a6318SAnthony Koo * 3654592a6318SAnthony Koo * @param rb DMUB ringbuffer 3655592a6318SAnthony Koo * @param cmd The command to push 3656592a6318SAnthony Koo * @return true if the ringbuffer was not full 3657592a6318SAnthony Koo * @return false otherwise 3658592a6318SAnthony Koo */ 365984034ad4SAnthony Koo static inline bool dmub_rb_push_front(struct dmub_rb *rb, 366084034ad4SAnthony Koo const union dmub_rb_cmd *cmd) 366184034ad4SAnthony Koo { 36623f232a0fSAnthony Koo uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 36633a9d5b0bSAnthony Koo const uint64_t *src = (const uint64_t *)cmd; 36643a9d5b0bSAnthony Koo uint8_t i; 366584034ad4SAnthony Koo 366684034ad4SAnthony Koo if (dmub_rb_full(rb)) 366784034ad4SAnthony Koo return false; 366884034ad4SAnthony Koo 366984034ad4SAnthony Koo // copying data 36703a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 36713a9d5b0bSAnthony Koo *dst++ = *src++; 367284034ad4SAnthony Koo 367384034ad4SAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 367484034ad4SAnthony Koo 367584034ad4SAnthony Koo if (rb->wrpt >= rb->capacity) 367684034ad4SAnthony Koo rb->wrpt %= rb->capacity; 367784034ad4SAnthony Koo 367884034ad4SAnthony Koo return true; 367984034ad4SAnthony Koo } 368084034ad4SAnthony Koo 3681592a6318SAnthony Koo /** 3682592a6318SAnthony Koo * @brief Pushes a command into the DMUB outbox ringbuffer 3683592a6318SAnthony Koo * 3684592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 3685592a6318SAnthony Koo * @param cmd Outbox command 3686592a6318SAnthony Koo * @return true if not full 3687592a6318SAnthony Koo * @return false otherwise 3688592a6318SAnthony Koo */ 3689d9beecfcSAnthony Koo static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3690d9beecfcSAnthony Koo const union dmub_rb_out_cmd *cmd) 3691d9beecfcSAnthony Koo { 3692d9beecfcSAnthony Koo uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3693d459b79bSAnthony Koo const uint8_t *src = (const uint8_t *)cmd; 3694d9beecfcSAnthony Koo 3695d9beecfcSAnthony Koo if (dmub_rb_full(rb)) 3696d9beecfcSAnthony Koo return false; 3697d9beecfcSAnthony Koo 3698d9beecfcSAnthony Koo dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3699d9beecfcSAnthony Koo 3700d9beecfcSAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 3701d9beecfcSAnthony Koo 3702d9beecfcSAnthony Koo if (rb->wrpt >= rb->capacity) 3703d9beecfcSAnthony Koo rb->wrpt %= rb->capacity; 3704d9beecfcSAnthony Koo 3705d9beecfcSAnthony Koo return true; 3706d9beecfcSAnthony Koo } 3707d9beecfcSAnthony Koo 3708592a6318SAnthony Koo /** 3709592a6318SAnthony Koo * @brief Returns the next unprocessed command in the ringbuffer. 3710592a6318SAnthony Koo * 3711592a6318SAnthony Koo * @param rb DMUB ringbuffer 3712592a6318SAnthony Koo * @param cmd The command to return 3713592a6318SAnthony Koo * @return true if not empty 3714592a6318SAnthony Koo * @return false otherwise 3715592a6318SAnthony Koo */ 371684034ad4SAnthony Koo static inline bool dmub_rb_front(struct dmub_rb *rb, 371734ba432cSAnthony Koo union dmub_rb_cmd **cmd) 371884034ad4SAnthony Koo { 371934ba432cSAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 372084034ad4SAnthony Koo 372184034ad4SAnthony Koo if (dmub_rb_empty(rb)) 372284034ad4SAnthony Koo return false; 372384034ad4SAnthony Koo 372434ba432cSAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 372584034ad4SAnthony Koo 372684034ad4SAnthony Koo return true; 372784034ad4SAnthony Koo } 372884034ad4SAnthony Koo 3729592a6318SAnthony Koo /** 37300b51e7e8SAnthony Koo * @brief Determines the next ringbuffer offset. 37310b51e7e8SAnthony Koo * 37320b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 37330b51e7e8SAnthony Koo * @param num_cmds Number of commands 37340b51e7e8SAnthony Koo * @param next_rptr The next offset in the ringbuffer 37350b51e7e8SAnthony Koo */ 37360b51e7e8SAnthony Koo static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 37370b51e7e8SAnthony Koo uint32_t num_cmds, 37380b51e7e8SAnthony Koo uint32_t *next_rptr) 37390b51e7e8SAnthony Koo { 37400b51e7e8SAnthony Koo *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 37410b51e7e8SAnthony Koo 37420b51e7e8SAnthony Koo if (*next_rptr >= rb->capacity) 37430b51e7e8SAnthony Koo *next_rptr %= rb->capacity; 37440b51e7e8SAnthony Koo } 37450b51e7e8SAnthony Koo 37460b51e7e8SAnthony Koo /** 37470b51e7e8SAnthony Koo * @brief Returns a pointer to a command in the inbox. 37480b51e7e8SAnthony Koo * 37490b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 37500b51e7e8SAnthony Koo * @param cmd The inbox command to return 37510b51e7e8SAnthony Koo * @param rptr The ringbuffer offset 37520b51e7e8SAnthony Koo * @return true if not empty 37530b51e7e8SAnthony Koo * @return false otherwise 37540b51e7e8SAnthony Koo */ 37550b51e7e8SAnthony Koo static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 37560b51e7e8SAnthony Koo union dmub_rb_cmd **cmd, 37570b51e7e8SAnthony Koo uint32_t rptr) 37580b51e7e8SAnthony Koo { 37590b51e7e8SAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 37600b51e7e8SAnthony Koo 37610b51e7e8SAnthony Koo if (dmub_rb_empty(rb)) 37620b51e7e8SAnthony Koo return false; 37630b51e7e8SAnthony Koo 37640b51e7e8SAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 37650b51e7e8SAnthony Koo 37660b51e7e8SAnthony Koo return true; 37670b51e7e8SAnthony Koo } 37680b51e7e8SAnthony Koo 37690b51e7e8SAnthony Koo /** 3770592a6318SAnthony Koo * @brief Returns the next unprocessed command in the outbox. 3771592a6318SAnthony Koo * 3772592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 3773592a6318SAnthony Koo * @param cmd The outbox command to return 3774592a6318SAnthony Koo * @return true if not empty 3775592a6318SAnthony Koo * @return false otherwise 3776592a6318SAnthony Koo */ 3777d9beecfcSAnthony Koo static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3778d9beecfcSAnthony Koo union dmub_rb_out_cmd *cmd) 3779d9beecfcSAnthony Koo { 37803f232a0fSAnthony Koo const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 37813a9d5b0bSAnthony Koo uint64_t *dst = (uint64_t *)cmd; 37823a9d5b0bSAnthony Koo uint8_t i; 3783d9beecfcSAnthony Koo 3784d9beecfcSAnthony Koo if (dmub_rb_empty(rb)) 3785d9beecfcSAnthony Koo return false; 3786d9beecfcSAnthony Koo 3787d9beecfcSAnthony Koo // copying data 37883a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 37893a9d5b0bSAnthony Koo *dst++ = *src++; 3790d9beecfcSAnthony Koo 3791d9beecfcSAnthony Koo return true; 3792d9beecfcSAnthony Koo } 3793d9beecfcSAnthony Koo 3794592a6318SAnthony Koo /** 3795592a6318SAnthony Koo * @brief Removes the front entry in the ringbuffer. 3796592a6318SAnthony Koo * 3797592a6318SAnthony Koo * @param rb DMUB ringbuffer 3798592a6318SAnthony Koo * @return true if the command was removed 3799592a6318SAnthony Koo * @return false if there were no commands 3800592a6318SAnthony Koo */ 380184034ad4SAnthony Koo static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 380284034ad4SAnthony Koo { 380384034ad4SAnthony Koo if (dmub_rb_empty(rb)) 380484034ad4SAnthony Koo return false; 380584034ad4SAnthony Koo 380684034ad4SAnthony Koo rb->rptr += DMUB_RB_CMD_SIZE; 380784034ad4SAnthony Koo 380884034ad4SAnthony Koo if (rb->rptr >= rb->capacity) 380984034ad4SAnthony Koo rb->rptr %= rb->capacity; 381084034ad4SAnthony Koo 381184034ad4SAnthony Koo return true; 381284034ad4SAnthony Koo } 381384034ad4SAnthony Koo 3814592a6318SAnthony Koo /** 3815592a6318SAnthony Koo * @brief Flushes commands in the ringbuffer to framebuffer memory. 3816592a6318SAnthony Koo * 3817592a6318SAnthony Koo * Avoids a race condition where DMCUB accesses memory while 3818592a6318SAnthony Koo * there are still writes in flight to framebuffer. 3819592a6318SAnthony Koo * 3820592a6318SAnthony Koo * @param rb DMUB ringbuffer 3821592a6318SAnthony Koo */ 382284034ad4SAnthony Koo static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 382384034ad4SAnthony Koo { 382484034ad4SAnthony Koo uint32_t rptr = rb->rptr; 382584034ad4SAnthony Koo uint32_t wptr = rb->wrpt; 382684034ad4SAnthony Koo 382784034ad4SAnthony Koo while (rptr != wptr) { 38287da7b02eSAashish Sharma uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 38293a9d5b0bSAnthony Koo uint8_t i; 383084034ad4SAnthony Koo 383123da6e0fSMaíra Canal /* Don't remove this. 383223da6e0fSMaíra Canal * The contents need to actually be read from the ring buffer 383323da6e0fSMaíra Canal * for this function to be effective. 383423da6e0fSMaíra Canal */ 38353a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 38367da7b02eSAashish Sharma (void)READ_ONCE(*data++); 383784034ad4SAnthony Koo 383884034ad4SAnthony Koo rptr += DMUB_RB_CMD_SIZE; 383984034ad4SAnthony Koo if (rptr >= rb->capacity) 384084034ad4SAnthony Koo rptr %= rb->capacity; 384184034ad4SAnthony Koo } 384284034ad4SAnthony Koo } 384384034ad4SAnthony Koo 3844592a6318SAnthony Koo /** 3845592a6318SAnthony Koo * @brief Initializes a DMCUB ringbuffer 3846592a6318SAnthony Koo * 3847592a6318SAnthony Koo * @param rb DMUB ringbuffer 3848592a6318SAnthony Koo * @param init_params initial configuration for the ringbuffer 3849592a6318SAnthony Koo */ 385084034ad4SAnthony Koo static inline void dmub_rb_init(struct dmub_rb *rb, 385184034ad4SAnthony Koo struct dmub_rb_init_params *init_params) 385284034ad4SAnthony Koo { 385384034ad4SAnthony Koo rb->base_address = init_params->base_address; 385484034ad4SAnthony Koo rb->capacity = init_params->capacity; 385584034ad4SAnthony Koo rb->rptr = init_params->read_ptr; 385684034ad4SAnthony Koo rb->wrpt = init_params->write_ptr; 385784034ad4SAnthony Koo } 385884034ad4SAnthony Koo 3859592a6318SAnthony Koo /** 3860592a6318SAnthony Koo * @brief Copies output data from in/out commands into the given command. 3861592a6318SAnthony Koo * 3862592a6318SAnthony Koo * @param rb DMUB ringbuffer 3863592a6318SAnthony Koo * @param cmd Command to copy data into 3864592a6318SAnthony Koo */ 386534ba432cSAnthony Koo static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 386634ba432cSAnthony Koo union dmub_rb_cmd *cmd) 386734ba432cSAnthony Koo { 386834ba432cSAnthony Koo // Copy rb entry back into command 386934ba432cSAnthony Koo uint8_t *rd_ptr = (rb->rptr == 0) ? 387034ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 387134ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 387234ba432cSAnthony Koo 387334ba432cSAnthony Koo dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 387434ba432cSAnthony Koo } 387534ba432cSAnthony Koo 387684034ad4SAnthony Koo #if defined(__cplusplus) 387784034ad4SAnthony Koo } 387884034ad4SAnthony Koo #endif 387984034ad4SAnthony Koo 388084034ad4SAnthony Koo //============================================================================== 388184034ad4SAnthony Koo //</DMUB_RB>==================================================================== 388284034ad4SAnthony Koo //============================================================================== 388384034ad4SAnthony Koo 38847c008829SNicholas Kazlauskas #endif /* _DMUB_CMD_H_ */ 3885