17c008829SNicholas Kazlauskas /* 27c008829SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 37c008829SNicholas Kazlauskas * 47c008829SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 57c008829SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 67c008829SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 77c008829SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87c008829SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 97c008829SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 107c008829SNicholas Kazlauskas * 117c008829SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 127c008829SNicholas Kazlauskas * all copies or substantial portions of the Software. 137c008829SNicholas Kazlauskas * 147c008829SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157c008829SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167c008829SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177c008829SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187c008829SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197c008829SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207c008829SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 217c008829SNicholas Kazlauskas * 227c008829SNicholas Kazlauskas * Authors: AMD 237c008829SNicholas Kazlauskas * 247c008829SNicholas Kazlauskas */ 257c008829SNicholas Kazlauskas 267c008829SNicholas Kazlauskas #ifndef _DMUB_CMD_H_ 277c008829SNicholas Kazlauskas #define _DMUB_CMD_H_ 287c008829SNicholas Kazlauskas 2984034ad4SAnthony Koo #include <asm/byteorder.h> 3084034ad4SAnthony Koo #include <linux/types.h> 3184034ad4SAnthony Koo #include <linux/string.h> 3284034ad4SAnthony Koo #include <linux/delay.h> 3384034ad4SAnthony Koo #include <stdarg.h> 3484034ad4SAnthony Koo 357c008829SNicholas Kazlauskas #include "atomfirmware.h" 3622aa5614SYongqiang Sun 378598a722SAnthony Koo /* Firmware versioning. */ 388598a722SAnthony Koo #ifdef DMUB_EXPOSE_VERSION 3945b790ddSAnthony Koo #define DMUB_FW_VERSION_GIT_HASH 0x821097815 40b2265774SAnthony Koo #define DMUB_FW_VERSION_MAJOR 0 418598a722SAnthony Koo #define DMUB_FW_VERSION_MINOR 0 4245b790ddSAnthony Koo #define DMUB_FW_VERSION_REVISION 41 43ded750e6SAnthony Koo #define DMUB_FW_VERSION_TEST 0 44ded750e6SAnthony Koo #define DMUB_FW_VERSION_VBIOS 0 45ded750e6SAnthony Koo #define DMUB_FW_VERSION_HOTFIX 0 46ded750e6SAnthony Koo #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \ 47ded750e6SAnthony Koo ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \ 48ded750e6SAnthony Koo ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \ 49ded750e6SAnthony Koo ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \ 50ded750e6SAnthony Koo ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \ 51ded750e6SAnthony Koo (DMUB_FW_VERSION_HOTFIX & 0x3F)) 52ded750e6SAnthony Koo 538598a722SAnthony Koo #endif 5484034ad4SAnthony Koo 5584034ad4SAnthony Koo //<DMUB_TYPES>================================================================== 5684034ad4SAnthony Koo /* Basic type definitions. */ 5784034ad4SAnthony Koo 5884034ad4SAnthony Koo #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 5984034ad4SAnthony Koo #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 60d9beecfcSAnthony Koo #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 6184034ad4SAnthony Koo #define SET_ABM_PIPE_NORMAL 1 6284034ad4SAnthony Koo 6384034ad4SAnthony Koo /* Maximum number of streams on any ASIC. */ 6484034ad4SAnthony Koo #define DMUB_MAX_STREAMS 6 6584034ad4SAnthony Koo 6684034ad4SAnthony Koo /* Maximum number of planes on any ASIC. */ 6784034ad4SAnthony Koo #define DMUB_MAX_PLANES 6 6884034ad4SAnthony Koo 6984034ad4SAnthony Koo #ifndef PHYSICAL_ADDRESS_LOC 7084034ad4SAnthony Koo #define PHYSICAL_ADDRESS_LOC union large_integer 7184034ad4SAnthony Koo #endif 7284034ad4SAnthony Koo 7384034ad4SAnthony Koo #ifndef dmub_memcpy 7484034ad4SAnthony Koo #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 7584034ad4SAnthony Koo #endif 7684034ad4SAnthony Koo 7784034ad4SAnthony Koo #ifndef dmub_memset 7884034ad4SAnthony Koo #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 7984034ad4SAnthony Koo #endif 8084034ad4SAnthony Koo 81d9beecfcSAnthony Koo #if defined(__cplusplus) 82d9beecfcSAnthony Koo extern "C" { 83d9beecfcSAnthony Koo #endif 84d9beecfcSAnthony Koo 8584034ad4SAnthony Koo #ifndef dmub_udelay 8684034ad4SAnthony Koo #define dmub_udelay(microseconds) udelay(microseconds) 8784034ad4SAnthony Koo #endif 8884034ad4SAnthony Koo 8984034ad4SAnthony Koo union dmub_addr { 9084034ad4SAnthony Koo struct { 9184034ad4SAnthony Koo uint32_t low_part; 9284034ad4SAnthony Koo uint32_t high_part; 9384034ad4SAnthony Koo } u; 9484034ad4SAnthony Koo uint64_t quad_part; 9584034ad4SAnthony Koo }; 9684034ad4SAnthony Koo 9784034ad4SAnthony Koo union dmub_psr_debug_flags { 9884034ad4SAnthony Koo struct { 99447f3d0fSAnthony Koo uint32_t visual_confirm : 1; 100447f3d0fSAnthony Koo uint32_t use_hw_lock_mgr : 1; 1018b3f6b98SAnthony Koo uint32_t log_line_nums : 1; 10284034ad4SAnthony Koo } bitfields; 10384034ad4SAnthony Koo 104447f3d0fSAnthony Koo uint32_t u32All; 10584034ad4SAnthony Koo }; 10684034ad4SAnthony Koo 10784034ad4SAnthony Koo #if defined(__cplusplus) 10884034ad4SAnthony Koo } 10984034ad4SAnthony Koo #endif 11084034ad4SAnthony Koo 11184034ad4SAnthony Koo 11284034ad4SAnthony Koo 11384034ad4SAnthony Koo //============================================================================== 11484034ad4SAnthony Koo //</DMUB_TYPES>================================================================= 11584034ad4SAnthony Koo //============================================================================== 11684034ad4SAnthony Koo //< DMUB_META>================================================================== 11784034ad4SAnthony Koo //============================================================================== 11884034ad4SAnthony Koo #pragma pack(push, 1) 11984034ad4SAnthony Koo 12084034ad4SAnthony Koo /* Magic value for identifying dmub_fw_meta_info */ 12184034ad4SAnthony Koo #define DMUB_FW_META_MAGIC 0x444D5542 12284034ad4SAnthony Koo 12384034ad4SAnthony Koo /* Offset from the end of the file to the dmub_fw_meta_info */ 12484034ad4SAnthony Koo #define DMUB_FW_META_OFFSET 0x24 12584034ad4SAnthony Koo 12684034ad4SAnthony Koo /** 12784034ad4SAnthony Koo * struct dmub_fw_meta_info - metadata associated with fw binary 12884034ad4SAnthony Koo * 12984034ad4SAnthony Koo * NOTE: This should be considered a stable API. Fields should 13084034ad4SAnthony Koo * not be repurposed or reordered. New fields should be 13184034ad4SAnthony Koo * added instead to extend the structure. 13284034ad4SAnthony Koo * 13384034ad4SAnthony Koo * @magic_value: magic value identifying DMUB firmware meta info 13484034ad4SAnthony Koo * @fw_region_size: size of the firmware state region 13584034ad4SAnthony Koo * @trace_buffer_size: size of the tracebuffer region 13684034ad4SAnthony Koo * @fw_version: the firmware version information 137b2265774SAnthony Koo * @dal_fw: 1 if the firmware is DAL 13884034ad4SAnthony Koo */ 13984034ad4SAnthony Koo struct dmub_fw_meta_info { 14084034ad4SAnthony Koo uint32_t magic_value; 14184034ad4SAnthony Koo uint32_t fw_region_size; 14284034ad4SAnthony Koo uint32_t trace_buffer_size; 14384034ad4SAnthony Koo uint32_t fw_version; 144b2265774SAnthony Koo uint8_t dal_fw; 145b2265774SAnthony Koo uint8_t reserved[3]; 14684034ad4SAnthony Koo }; 14784034ad4SAnthony Koo 14884034ad4SAnthony Koo /* Ensure that the structure remains 64 bytes. */ 14984034ad4SAnthony Koo union dmub_fw_meta { 15084034ad4SAnthony Koo struct dmub_fw_meta_info info; 15184034ad4SAnthony Koo uint8_t reserved[64]; 15284034ad4SAnthony Koo }; 15384034ad4SAnthony Koo 15484034ad4SAnthony Koo #pragma pack(pop) 155788408b7SAnthony Koo 15684034ad4SAnthony Koo //============================================================================== 157788408b7SAnthony Koo //< DMUB_STATUS>================================================================ 158788408b7SAnthony Koo //============================================================================== 159788408b7SAnthony Koo 160788408b7SAnthony Koo /** 161788408b7SAnthony Koo * DMCUB scratch registers can be used to determine firmware status. 162788408b7SAnthony Koo * Current scratch register usage is as follows: 163788408b7SAnthony Koo * 164492dd8a8SAnthony Koo * SCRATCH0: FW Boot Status register 165492dd8a8SAnthony Koo * SCRATCH15: FW Boot Options register 166788408b7SAnthony Koo */ 167788408b7SAnthony Koo 168492dd8a8SAnthony Koo /* Register bit definition for SCRATCH0 */ 169492dd8a8SAnthony Koo union dmub_fw_boot_status { 170492dd8a8SAnthony Koo struct { 171492dd8a8SAnthony Koo uint32_t dal_fw : 1; 172492dd8a8SAnthony Koo uint32_t mailbox_rdy : 1; 173492dd8a8SAnthony Koo uint32_t optimized_init_done : 1; 1743b37260bSAnthony Koo uint32_t restore_required : 1; 175492dd8a8SAnthony Koo } bits; 176492dd8a8SAnthony Koo uint32_t all; 177492dd8a8SAnthony Koo }; 178492dd8a8SAnthony Koo 179492dd8a8SAnthony Koo enum dmub_fw_boot_status_bit { 180492dd8a8SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), 181492dd8a8SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), 182492dd8a8SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 1833b37260bSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), 184492dd8a8SAnthony Koo }; 185492dd8a8SAnthony Koo 186492dd8a8SAnthony Koo /* Register bit definition for SCRATCH15 */ 187492dd8a8SAnthony Koo union dmub_fw_boot_options { 188492dd8a8SAnthony Koo struct { 189492dd8a8SAnthony Koo uint32_t pemu_env : 1; 190492dd8a8SAnthony Koo uint32_t fpga_env : 1; 191492dd8a8SAnthony Koo uint32_t optimized_init : 1; 192fd0f1d21SAnthony Koo uint32_t skip_phy_access : 1; 193fd0f1d21SAnthony Koo uint32_t disable_clk_gate: 1; 1945fe6b98aSBhawanpreet Lakha uint32_t skip_phy_init_panel_sequence: 1; 1955fe6b98aSBhawanpreet Lakha uint32_t reserved : 26; 196492dd8a8SAnthony Koo } bits; 197492dd8a8SAnthony Koo uint32_t all; 198492dd8a8SAnthony Koo }; 199492dd8a8SAnthony Koo 200492dd8a8SAnthony Koo enum dmub_fw_boot_options_bit { 201492dd8a8SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), 202492dd8a8SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), 203492dd8a8SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), 204492dd8a8SAnthony Koo }; 205492dd8a8SAnthony Koo 206788408b7SAnthony Koo //============================================================================== 207788408b7SAnthony Koo //</DMUB_STATUS>================================================================ 20884034ad4SAnthony Koo //============================================================================== 20984034ad4SAnthony Koo //< DMUB_VBIOS>================================================================= 21084034ad4SAnthony Koo //============================================================================== 21184034ad4SAnthony Koo 21284034ad4SAnthony Koo /* 21384034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 21484034ad4SAnthony Koo * Do not reuse or modify IDs. 21584034ad4SAnthony Koo */ 21684034ad4SAnthony Koo 21784034ad4SAnthony Koo enum dmub_cmd_vbios_type { 21884034ad4SAnthony Koo DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 21984034ad4SAnthony Koo DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 22084034ad4SAnthony Koo DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 22184034ad4SAnthony Koo DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 2222ac685bfSAnthony Koo DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 22384034ad4SAnthony Koo }; 22484034ad4SAnthony Koo 22584034ad4SAnthony Koo //============================================================================== 22684034ad4SAnthony Koo //</DMUB_VBIOS>================================================================= 22784034ad4SAnthony Koo //============================================================================== 22884034ad4SAnthony Koo //< DMUB_GPINT>================================================================= 22984034ad4SAnthony Koo //============================================================================== 23084034ad4SAnthony Koo 23184034ad4SAnthony Koo /** 23284034ad4SAnthony Koo * The shifts and masks below may alternatively be used to format and read 23384034ad4SAnthony Koo * the command register bits. 23484034ad4SAnthony Koo */ 23584034ad4SAnthony Koo 23684034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 23784034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_SHIFT 0 23884034ad4SAnthony Koo 23984034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 24084034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 24184034ad4SAnthony Koo 24284034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_MASK 0xF 24384034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_SHIFT 28 24484034ad4SAnthony Koo 24584034ad4SAnthony Koo /** 24684034ad4SAnthony Koo * Command responses. 24784034ad4SAnthony Koo */ 24884034ad4SAnthony Koo 24984034ad4SAnthony Koo #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 25084034ad4SAnthony Koo 25184034ad4SAnthony Koo /** 25284034ad4SAnthony Koo * The register format for sending a command via the GPINT. 25384034ad4SAnthony Koo */ 25484034ad4SAnthony Koo union dmub_gpint_data_register { 25584034ad4SAnthony Koo struct { 25684034ad4SAnthony Koo uint32_t param : 16; 25784034ad4SAnthony Koo uint32_t command_code : 12; 25884034ad4SAnthony Koo uint32_t status : 4; 25984034ad4SAnthony Koo } bits; 26084034ad4SAnthony Koo uint32_t all; 26184034ad4SAnthony Koo }; 26284034ad4SAnthony Koo 26384034ad4SAnthony Koo /* 26484034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 26584034ad4SAnthony Koo * Do not reuse or modify IDs. 26684034ad4SAnthony Koo */ 26784034ad4SAnthony Koo 26884034ad4SAnthony Koo enum dmub_gpint_command { 26984034ad4SAnthony Koo DMUB_GPINT__INVALID_COMMAND = 0, 27084034ad4SAnthony Koo DMUB_GPINT__GET_FW_VERSION = 1, 27184034ad4SAnthony Koo DMUB_GPINT__STOP_FW = 2, 27284034ad4SAnthony Koo DMUB_GPINT__GET_PSR_STATE = 7, 27380eba958SAnthony Koo /** 27480eba958SAnthony Koo * DESC: Notifies DMCUB of the currently active streams. 27580eba958SAnthony Koo * ARGS: Stream mask, 1 bit per active stream index. 27680eba958SAnthony Koo */ 27780eba958SAnthony Koo DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 278672251b2SAnthony Koo DMUB_GPINT__PSR_RESIDENCY = 9, 27984034ad4SAnthony Koo }; 28084034ad4SAnthony Koo 28184034ad4SAnthony Koo //============================================================================== 28284034ad4SAnthony Koo //</DMUB_GPINT>================================================================= 28384034ad4SAnthony Koo //============================================================================== 28484034ad4SAnthony Koo //< DMUB_CMD>=================================================================== 28584034ad4SAnthony Koo //============================================================================== 28684034ad4SAnthony Koo 2877c008829SNicholas Kazlauskas #define DMUB_RB_CMD_SIZE 64 2887c008829SNicholas Kazlauskas #define DMUB_RB_MAX_ENTRY 128 2897c008829SNicholas Kazlauskas #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 2907c008829SNicholas Kazlauskas #define REG_SET_MASK 0xFFFF 2917c008829SNicholas Kazlauskas 292d4bbcecbSNicholas Kazlauskas /* 293d4bbcecbSNicholas Kazlauskas * Command IDs should be treated as stable ABI. 294d4bbcecbSNicholas Kazlauskas * Do not reuse or modify IDs. 295d4bbcecbSNicholas Kazlauskas */ 2967c008829SNicholas Kazlauskas 297d4bbcecbSNicholas Kazlauskas enum dmub_cmd_type { 298d4bbcecbSNicholas Kazlauskas DMUB_CMD__NULL = 0, 299d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 300d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 301d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 302d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_REG_WAIT = 4, 303bae9c49bSYongqiang Sun DMUB_CMD__PLAT_54186_WA = 5, 304d4bbcecbSNicholas Kazlauskas DMUB_CMD__PSR = 64, 30552f2e83eSBhawanpreet Lakha DMUB_CMD__MALL = 65, 306e6ea8c34SWyatt Wood DMUB_CMD__ABM = 66, 307788408b7SAnthony Koo DMUB_CMD__HW_LOCK = 69, 308d9beecfcSAnthony Koo DMUB_CMD__DP_AUX_ACCESS = 70, 309d9beecfcSAnthony Koo DMUB_CMD__OUTBOX1_ENABLE = 71, 310d4bbcecbSNicholas Kazlauskas DMUB_CMD__VBIOS = 128, 3117c008829SNicholas Kazlauskas }; 3127c008829SNicholas Kazlauskas 3133b37260bSAnthony Koo enum dmub_out_cmd_type { 3143b37260bSAnthony Koo DMUB_OUT_CMD__NULL = 0, 315d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_AUX_REPLY = 1, 316d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 3173b37260bSAnthony Koo }; 3183b37260bSAnthony Koo 3197c008829SNicholas Kazlauskas #pragma pack(push, 1) 3207c008829SNicholas Kazlauskas 3217c008829SNicholas Kazlauskas struct dmub_cmd_header { 322d4bbcecbSNicholas Kazlauskas unsigned int type : 8; 323d4bbcecbSNicholas Kazlauskas unsigned int sub_type : 8; 324d4bbcecbSNicholas Kazlauskas unsigned int reserved0 : 8; 3257c008829SNicholas Kazlauskas unsigned int payload_bytes : 6; /* up to 60 bytes */ 326d4bbcecbSNicholas Kazlauskas unsigned int reserved1 : 2; 3277c008829SNicholas Kazlauskas }; 3287c008829SNicholas Kazlauskas 3297c008829SNicholas Kazlauskas /* 3307c008829SNicholas Kazlauskas * Read modify write 3317c008829SNicholas Kazlauskas * 3327c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 5 sets of read modify writes, 3337c008829SNicholas Kazlauskas * each take 3 dwords. 3347c008829SNicholas Kazlauskas * 3357c008829SNicholas Kazlauskas * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 3367c008829SNicholas Kazlauskas * 3377c008829SNicholas Kazlauskas * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 3387c008829SNicholas Kazlauskas * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 3397c008829SNicholas Kazlauskas */ 3407c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence { 3417c008829SNicholas Kazlauskas uint32_t addr; 3427c008829SNicholas Kazlauskas uint32_t modify_mask; 3437c008829SNicholas Kazlauskas uint32_t modify_value; 3447c008829SNicholas Kazlauskas }; 3457c008829SNicholas Kazlauskas 3467c008829SNicholas Kazlauskas #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 3477c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write { 3487c008829SNicholas Kazlauskas struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 3497c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 3507c008829SNicholas Kazlauskas }; 3517c008829SNicholas Kazlauskas 3527c008829SNicholas Kazlauskas /* 3537c008829SNicholas Kazlauskas * Update a register with specified masks and values sequeunce 3547c008829SNicholas Kazlauskas * 3557c008829SNicholas Kazlauskas * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 3567c008829SNicholas Kazlauskas * 3577c008829SNicholas Kazlauskas * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 3587c008829SNicholas Kazlauskas * 3597c008829SNicholas Kazlauskas * 3607c008829SNicholas Kazlauskas * USE CASE: 3617c008829SNicholas Kazlauskas * 1. auto-increment register where additional read would update pointer and produce wrong result 3627c008829SNicholas Kazlauskas * 2. toggle a bit without read in the middle 3637c008829SNicholas Kazlauskas */ 3647c008829SNicholas Kazlauskas 3657c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence { 3667c008829SNicholas Kazlauskas uint32_t modify_mask; // 0xffff'ffff to skip initial read 3677c008829SNicholas Kazlauskas uint32_t modify_value; 3687c008829SNicholas Kazlauskas }; 3697c008829SNicholas Kazlauskas 3707c008829SNicholas Kazlauskas #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 3717c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence { 3727c008829SNicholas Kazlauskas struct dmub_cmd_header header; 3737c008829SNicholas Kazlauskas uint32_t addr; 3747c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 3757c008829SNicholas Kazlauskas }; 3767c008829SNicholas Kazlauskas 3777c008829SNicholas Kazlauskas /* 3787c008829SNicholas Kazlauskas * Burst write 3797c008829SNicholas Kazlauskas * 3807c008829SNicholas Kazlauskas * support use case such as writing out LUTs. 3817c008829SNicholas Kazlauskas * 3827c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 14 values to write to given address 3837c008829SNicholas Kazlauskas * 3847c008829SNicholas Kazlauskas * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 3857c008829SNicholas Kazlauskas */ 3867c008829SNicholas Kazlauskas #define DMUB_BURST_WRITE_VALUES__MAX 14 3877c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write { 3887c008829SNicholas Kazlauskas struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 3897c008829SNicholas Kazlauskas uint32_t addr; 3907c008829SNicholas Kazlauskas uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 3917c008829SNicholas Kazlauskas }; 3927c008829SNicholas Kazlauskas 3937c008829SNicholas Kazlauskas 3947c008829SNicholas Kazlauskas struct dmub_rb_cmd_common { 3957c008829SNicholas Kazlauskas struct dmub_cmd_header header; 3967c008829SNicholas Kazlauskas uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 3977c008829SNicholas Kazlauskas }; 3987c008829SNicholas Kazlauskas 3997c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data { 4007c008829SNicholas Kazlauskas uint32_t addr; 4017c008829SNicholas Kazlauskas uint32_t mask; 4027c008829SNicholas Kazlauskas uint32_t condition_field_value; 4037c008829SNicholas Kazlauskas uint32_t time_out_us; 4047c008829SNicholas Kazlauskas }; 4057c008829SNicholas Kazlauskas 4067c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait { 4077c008829SNicholas Kazlauskas struct dmub_cmd_header header; 4087c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data reg_wait; 4097c008829SNicholas Kazlauskas }; 4107c008829SNicholas Kazlauskas 411bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa { 4128c019253SYongqiang Sun uint32_t DCSURF_SURFACE_CONTROL; 4138c019253SYongqiang Sun uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 4148c019253SYongqiang Sun uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 4158c019253SYongqiang Sun uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 4168c019253SYongqiang Sun uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 41722aa5614SYongqiang Sun struct { 41822aa5614SYongqiang Sun uint8_t hubp_inst : 4; 41922aa5614SYongqiang Sun uint8_t tmz_surface : 1; 42022aa5614SYongqiang Sun uint8_t immediate :1; 42122aa5614SYongqiang Sun uint8_t vmid : 4; 42222aa5614SYongqiang Sun uint8_t grph_stereo : 1; 42322aa5614SYongqiang Sun uint32_t reserved : 21; 42422aa5614SYongqiang Sun } flip_params; 425bae9c49bSYongqiang Sun uint32_t reserved[9]; 4268c019253SYongqiang Sun }; 4278c019253SYongqiang Sun 428bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa { 4298c019253SYongqiang Sun struct dmub_cmd_header header; 430bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa flip; 4318c019253SYongqiang Sun }; 4328c019253SYongqiang Sun 43352f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall { 43452f2e83eSBhawanpreet Lakha struct dmub_cmd_header header; 43552f2e83eSBhawanpreet Lakha union dmub_addr cursor_copy_src; 43652f2e83eSBhawanpreet Lakha union dmub_addr cursor_copy_dst; 43752f2e83eSBhawanpreet Lakha uint32_t tmr_delay; 43852f2e83eSBhawanpreet Lakha uint32_t tmr_scale; 43952f2e83eSBhawanpreet Lakha uint16_t cursor_width; 44052f2e83eSBhawanpreet Lakha uint16_t cursor_pitch; 44152f2e83eSBhawanpreet Lakha uint16_t cursor_height; 44252f2e83eSBhawanpreet Lakha uint8_t cursor_bpp; 44352f2e83eSBhawanpreet Lakha }; 44452f2e83eSBhawanpreet Lakha 4457c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data { 4467c008829SNicholas Kazlauskas union dig_encoder_control_parameters_v1_5 dig; 4477c008829SNicholas Kazlauskas }; 4487c008829SNicholas Kazlauskas 4497c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control { 4507c008829SNicholas Kazlauskas struct dmub_cmd_header header; 4517c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data encoder_control; 4527c008829SNicholas Kazlauskas }; 4537c008829SNicholas Kazlauskas 4547c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data { 4557c008829SNicholas Kazlauskas struct set_pixel_clock_parameter_v1_7 clk; 4567c008829SNicholas Kazlauskas }; 4577c008829SNicholas Kazlauskas 4587c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock { 4597c008829SNicholas Kazlauskas struct dmub_cmd_header header; 4607c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data pixel_clock; 4617c008829SNicholas Kazlauskas }; 4627c008829SNicholas Kazlauskas 4637c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data { 4647c008829SNicholas Kazlauskas struct enable_disp_power_gating_parameters_v2_1 pwr; 4657c008829SNicholas Kazlauskas }; 4667c008829SNicholas Kazlauskas 4677c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating { 4687c008829SNicholas Kazlauskas struct dmub_cmd_header header; 4697c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data power_gating; 4707c008829SNicholas Kazlauskas }; 4717c008829SNicholas Kazlauskas 4727c008829SNicholas Kazlauskas struct dmub_cmd_dig1_transmitter_control_data { 4737c008829SNicholas Kazlauskas struct dig_transmitter_control_parameters_v1_6 dig; 4747c008829SNicholas Kazlauskas }; 4757c008829SNicholas Kazlauskas 4767c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control { 4777c008829SNicholas Kazlauskas struct dmub_cmd_header header; 4787c008829SNicholas Kazlauskas struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 4797c008829SNicholas Kazlauskas }; 4807c008829SNicholas Kazlauskas 4817c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init { 4827c008829SNicholas Kazlauskas struct dmub_cmd_header header; 4837c008829SNicholas Kazlauskas uint8_t reserved[60]; 4847c008829SNicholas Kazlauskas }; 4857c008829SNicholas Kazlauskas 486d9beecfcSAnthony Koo enum dp_aux_request_action { 487d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 488d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ = 0x10, 489d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 490d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 491d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 492d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 493d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 494d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_READ = 0x90 495d9beecfcSAnthony Koo }; 496d9beecfcSAnthony Koo 497fd0f1d21SAnthony Koo enum aux_return_code_type { 498fd0f1d21SAnthony Koo AUX_RET_SUCCESS = 0, 499fd0f1d21SAnthony Koo AUX_RET_ERROR_TIMEOUT, 500fd0f1d21SAnthony Koo AUX_RET_ERROR_NO_DATA, 501fd0f1d21SAnthony Koo AUX_RET_ERROR_INVALID_OPERATION, 502fd0f1d21SAnthony Koo AUX_RET_ERROR_PROTOCOL_ERROR, 503fd0f1d21SAnthony Koo }; 504fd0f1d21SAnthony Koo 505d9beecfcSAnthony Koo /* DP AUX command */ 506d9beecfcSAnthony Koo struct aux_transaction_parameters { 507d9beecfcSAnthony Koo uint8_t is_i2c_over_aux; 508d9beecfcSAnthony Koo uint8_t action; 509d9beecfcSAnthony Koo uint8_t length; 510d9beecfcSAnthony Koo uint8_t pad; 511d9beecfcSAnthony Koo uint32_t address; 512d9beecfcSAnthony Koo uint8_t data[16]; 513d9beecfcSAnthony Koo }; 514d9beecfcSAnthony Koo 515d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data { 516d9beecfcSAnthony Koo uint32_t handle; 517d9beecfcSAnthony Koo uint8_t port_index; 518d9beecfcSAnthony Koo uint8_t sw_crc_enabled; 519d9beecfcSAnthony Koo uint16_t timeout; 520d9beecfcSAnthony Koo struct aux_transaction_parameters dpaux; 521d9beecfcSAnthony Koo }; 522d9beecfcSAnthony Koo 523d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access { 524d9beecfcSAnthony Koo struct dmub_cmd_header header; 525d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data aux_control; 526d9beecfcSAnthony Koo }; 527d9beecfcSAnthony Koo 528d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable { 529d9beecfcSAnthony Koo struct dmub_cmd_header header; 530d9beecfcSAnthony Koo uint32_t enable; 531d9beecfcSAnthony Koo }; 532d9beecfcSAnthony Koo 533d9beecfcSAnthony Koo /* DP AUX Reply command - OutBox Cmd */ 534d9beecfcSAnthony Koo struct aux_reply_data { 535d9beecfcSAnthony Koo uint8_t command; 536d9beecfcSAnthony Koo uint8_t length; 537d9beecfcSAnthony Koo uint8_t pad[2]; 538d9beecfcSAnthony Koo uint8_t data[16]; 539d9beecfcSAnthony Koo }; 540d9beecfcSAnthony Koo 541d9beecfcSAnthony Koo struct aux_reply_control_data { 542d9beecfcSAnthony Koo uint32_t handle; 543d9beecfcSAnthony Koo uint8_t phy_port_index; 544d9beecfcSAnthony Koo uint8_t result; 545d9beecfcSAnthony Koo uint16_t pad; 546d9beecfcSAnthony Koo }; 547d9beecfcSAnthony Koo 548d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply { 549d9beecfcSAnthony Koo struct dmub_cmd_header header; 550d9beecfcSAnthony Koo struct aux_reply_control_data control; 551d9beecfcSAnthony Koo struct aux_reply_data reply_data; 552d9beecfcSAnthony Koo }; 553d9beecfcSAnthony Koo 554fd0f1d21SAnthony Koo /* DP HPD Notify command - OutBox Cmd */ 555fd0f1d21SAnthony Koo enum dp_hpd_type { 556fd0f1d21SAnthony Koo DP_HPD = 0, 557fd0f1d21SAnthony Koo DP_IRQ 558fd0f1d21SAnthony Koo }; 559fd0f1d21SAnthony Koo 560fd0f1d21SAnthony Koo enum dp_hpd_status { 561fd0f1d21SAnthony Koo DP_HPD_UNPLUG = 0, 562fd0f1d21SAnthony Koo DP_HPD_PLUG 563fd0f1d21SAnthony Koo }; 564fd0f1d21SAnthony Koo 565d9beecfcSAnthony Koo struct dp_hpd_data { 566d9beecfcSAnthony Koo uint8_t phy_port_index; 567d9beecfcSAnthony Koo uint8_t hpd_type; 568d9beecfcSAnthony Koo uint8_t hpd_status; 569d9beecfcSAnthony Koo uint8_t pad; 570d9beecfcSAnthony Koo }; 571d9beecfcSAnthony Koo 572d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify { 573d9beecfcSAnthony Koo struct dmub_cmd_header header; 574d9beecfcSAnthony Koo struct dp_hpd_data hpd_data; 575d9beecfcSAnthony Koo }; 576d9beecfcSAnthony Koo 57784034ad4SAnthony Koo /* 57884034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 57984034ad4SAnthony Koo * Do not reuse or modify IDs. 58084034ad4SAnthony Koo */ 58184034ad4SAnthony Koo 58284034ad4SAnthony Koo enum dmub_cmd_psr_type { 58384034ad4SAnthony Koo DMUB_CMD__PSR_SET_VERSION = 0, 58484034ad4SAnthony Koo DMUB_CMD__PSR_COPY_SETTINGS = 1, 58584034ad4SAnthony Koo DMUB_CMD__PSR_ENABLE = 2, 58684034ad4SAnthony Koo DMUB_CMD__PSR_DISABLE = 3, 58784034ad4SAnthony Koo DMUB_CMD__PSR_SET_LEVEL = 4, 588672251b2SAnthony Koo DMUB_CMD__PSR_FORCE_STATIC = 5, 58984034ad4SAnthony Koo }; 59084034ad4SAnthony Koo 59184034ad4SAnthony Koo enum psr_version { 59284034ad4SAnthony Koo PSR_VERSION_1 = 0, 59384034ad4SAnthony Koo PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 59484034ad4SAnthony Koo }; 59584034ad4SAnthony Koo 59652f2e83eSBhawanpreet Lakha enum dmub_cmd_mall_type { 59752f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_ALLOW = 0, 59852f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_DISALLOW = 1, 59952f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 60052f2e83eSBhawanpreet Lakha }; 60152f2e83eSBhawanpreet Lakha 6027c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data { 6037b8a6362SAnthony Koo union dmub_psr_debug_flags debug; 6044c1a1335SWyatt Wood uint16_t psr_level; 6054c1a1335SWyatt Wood uint8_t dpp_inst; 6064c1a1335SWyatt Wood uint8_t mpcc_inst; 6074c1a1335SWyatt Wood uint8_t opp_inst; 6084c1a1335SWyatt Wood uint8_t otg_inst; 6094c1a1335SWyatt Wood uint8_t digfe_inst; 6104c1a1335SWyatt Wood uint8_t digbe_inst; 6114c1a1335SWyatt Wood uint8_t dpphy_inst; 6124c1a1335SWyatt Wood uint8_t aux_inst; 6134c1a1335SWyatt Wood uint8_t smu_optimizations_en; 6144c1a1335SWyatt Wood uint8_t frame_delay; 6154c1a1335SWyatt Wood uint8_t frame_cap_ind; 616*175f0971SYongqiang Sun uint8_t pad[2]; 617*175f0971SYongqiang Sun uint8_t multi_disp_optimizations_en; 61878ead771SAnthony Koo uint16_t init_sdp_deadline; 61978ead771SAnthony Koo uint16_t pad2; 6207c008829SNicholas Kazlauskas }; 6217c008829SNicholas Kazlauskas 6227c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings { 6237c008829SNicholas Kazlauskas struct dmub_cmd_header header; 6247c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 6257c008829SNicholas Kazlauskas }; 6267c008829SNicholas Kazlauskas 6277c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data { 6287c008829SNicholas Kazlauskas uint16_t psr_level; 6297b8a6362SAnthony Koo uint8_t pad[2]; 6307c008829SNicholas Kazlauskas }; 6317c008829SNicholas Kazlauskas 6327c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level { 6337c008829SNicholas Kazlauskas struct dmub_cmd_header header; 6347c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data psr_set_level_data; 6357c008829SNicholas Kazlauskas }; 6367c008829SNicholas Kazlauskas 6377c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_enable { 6387c008829SNicholas Kazlauskas struct dmub_cmd_header header; 6397c008829SNicholas Kazlauskas }; 6407c008829SNicholas Kazlauskas 641d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data { 642ec256f44SWyatt Wood enum psr_version version; // PSR version 1 or 2 6437c008829SNicholas Kazlauskas }; 6447c008829SNicholas Kazlauskas 645d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version { 6467c008829SNicholas Kazlauskas struct dmub_cmd_header header; 647d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data psr_set_version_data; 6487c008829SNicholas Kazlauskas }; 6497c008829SNicholas Kazlauskas 650672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static { 651672251b2SAnthony Koo struct dmub_cmd_header header; 652672251b2SAnthony Koo }; 653672251b2SAnthony Koo 654788408b7SAnthony Koo union dmub_hw_lock_flags { 655788408b7SAnthony Koo struct { 656788408b7SAnthony Koo uint8_t lock_pipe : 1; 657788408b7SAnthony Koo uint8_t lock_cursor : 1; 658788408b7SAnthony Koo uint8_t lock_dig : 1; 659788408b7SAnthony Koo uint8_t triple_buffer_lock : 1; 660788408b7SAnthony Koo } bits; 661788408b7SAnthony Koo 662788408b7SAnthony Koo uint8_t u8All; 663788408b7SAnthony Koo }; 664788408b7SAnthony Koo 665788408b7SAnthony Koo struct dmub_hw_lock_inst_flags { 666788408b7SAnthony Koo uint8_t otg_inst; 667788408b7SAnthony Koo uint8_t opp_inst; 668788408b7SAnthony Koo uint8_t dig_inst; 669788408b7SAnthony Koo uint8_t pad; 670788408b7SAnthony Koo }; 671788408b7SAnthony Koo 672788408b7SAnthony Koo enum hw_lock_client { 673788408b7SAnthony Koo HW_LOCK_CLIENT_DRIVER = 0, 674788408b7SAnthony Koo HW_LOCK_CLIENT_FW, 675788408b7SAnthony Koo HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 676788408b7SAnthony Koo }; 677788408b7SAnthony Koo 678788408b7SAnthony Koo struct dmub_cmd_lock_hw_data { 679788408b7SAnthony Koo enum hw_lock_client client; 680788408b7SAnthony Koo struct dmub_hw_lock_inst_flags inst_flags; 681788408b7SAnthony Koo union dmub_hw_lock_flags hw_locks; 682788408b7SAnthony Koo uint8_t lock; 683788408b7SAnthony Koo uint8_t should_release; 684788408b7SAnthony Koo uint8_t pad; 685788408b7SAnthony Koo }; 686788408b7SAnthony Koo 687788408b7SAnthony Koo struct dmub_rb_cmd_lock_hw { 688788408b7SAnthony Koo struct dmub_cmd_header header; 689788408b7SAnthony Koo struct dmub_cmd_lock_hw_data lock_hw_data; 690788408b7SAnthony Koo }; 691788408b7SAnthony Koo 69284034ad4SAnthony Koo enum dmub_cmd_abm_type { 69384034ad4SAnthony Koo DMUB_CMD__ABM_INIT_CONFIG = 0, 69484034ad4SAnthony Koo DMUB_CMD__ABM_SET_PIPE = 1, 69584034ad4SAnthony Koo DMUB_CMD__ABM_SET_BACKLIGHT = 2, 69684034ad4SAnthony Koo DMUB_CMD__ABM_SET_LEVEL = 3, 69784034ad4SAnthony Koo DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 69884034ad4SAnthony Koo DMUB_CMD__ABM_SET_PWM_FRAC = 5, 69984034ad4SAnthony Koo }; 70084034ad4SAnthony Koo 70184034ad4SAnthony Koo #define NUM_AMBI_LEVEL 5 70284034ad4SAnthony Koo #define NUM_AGGR_LEVEL 4 70384034ad4SAnthony Koo #define NUM_POWER_FN_SEGS 8 70484034ad4SAnthony Koo #define NUM_BL_CURVE_SEGS 16 70584034ad4SAnthony Koo 70684034ad4SAnthony Koo /* 70784034ad4SAnthony Koo * Parameters for ABM2.4 algorithm. 70884034ad4SAnthony Koo * Padded explicitly to 32-bit boundary. 70984034ad4SAnthony Koo */ 71084034ad4SAnthony Koo struct abm_config_table { 71184034ad4SAnthony Koo /* Parameters for crgb conversion */ 71284034ad4SAnthony Koo uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 71384034ad4SAnthony Koo uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 15B 71484034ad4SAnthony Koo uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 31B 71584034ad4SAnthony Koo 71684034ad4SAnthony Koo /* Parameters for custom curve */ 71784034ad4SAnthony Koo uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 47B 71884034ad4SAnthony Koo uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 79B 71984034ad4SAnthony Koo 72084034ad4SAnthony Koo uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 111B 72184034ad4SAnthony Koo uint16_t min_abm_backlight; // 121B 72284034ad4SAnthony Koo 72384034ad4SAnthony Koo uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 123B 72484034ad4SAnthony Koo uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 143B 72584034ad4SAnthony Koo uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 163B 72684034ad4SAnthony Koo uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 183B 72784034ad4SAnthony Koo uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 203B 72884034ad4SAnthony Koo uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 207B 72984034ad4SAnthony Koo uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 211B 73084034ad4SAnthony Koo uint8_t min_knee[NUM_AGGR_LEVEL]; // 215B 73184034ad4SAnthony Koo uint8_t max_knee[NUM_AGGR_LEVEL]; // 219B 73284034ad4SAnthony Koo uint8_t iir_curve[NUM_AMBI_LEVEL]; // 223B 73384034ad4SAnthony Koo uint8_t pad3[3]; // 228B 73484034ad4SAnthony Koo }; 73584034ad4SAnthony Koo 736e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data { 7377b8a6362SAnthony Koo uint8_t otg_inst; 7387b8a6362SAnthony Koo uint8_t panel_inst; 7397b8a6362SAnthony Koo uint8_t set_pipe_option; 7407b8a6362SAnthony Koo uint8_t ramping_boundary; // TODO: Remove this 741e6ea8c34SWyatt Wood }; 742e6ea8c34SWyatt Wood 743e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe { 744e6ea8c34SWyatt Wood struct dmub_cmd_header header; 745e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 746e6ea8c34SWyatt Wood }; 747e6ea8c34SWyatt Wood 748e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data { 749e6ea8c34SWyatt Wood uint32_t frame_ramp; 750474ac4a8SYongqiang Sun uint32_t backlight_user_level; 751e6ea8c34SWyatt Wood }; 752e6ea8c34SWyatt Wood 753e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight { 754e6ea8c34SWyatt Wood struct dmub_cmd_header header; 755e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 756e6ea8c34SWyatt Wood }; 757e6ea8c34SWyatt Wood 758e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data { 759e6ea8c34SWyatt Wood uint32_t level; 760e6ea8c34SWyatt Wood }; 761e6ea8c34SWyatt Wood 762e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level { 763e6ea8c34SWyatt Wood struct dmub_cmd_header header; 764e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data abm_set_level_data; 765e6ea8c34SWyatt Wood }; 766e6ea8c34SWyatt Wood 767e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data { 768e6ea8c34SWyatt Wood uint32_t ambient_lux; 769e6ea8c34SWyatt Wood }; 770e6ea8c34SWyatt Wood 771e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level { 772e6ea8c34SWyatt Wood struct dmub_cmd_header header; 773e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 774e6ea8c34SWyatt Wood }; 775e6ea8c34SWyatt Wood 776e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data { 777e6ea8c34SWyatt Wood uint32_t fractional_pwm; 778e6ea8c34SWyatt Wood }; 779e6ea8c34SWyatt Wood 780e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac { 781e6ea8c34SWyatt Wood struct dmub_cmd_header header; 782e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 783e6ea8c34SWyatt Wood }; 784e6ea8c34SWyatt Wood 78516012806SWyatt Wood struct dmub_cmd_abm_init_config_data { 78616012806SWyatt Wood union dmub_addr src; 78716012806SWyatt Wood uint16_t bytes; 78816012806SWyatt Wood }; 78916012806SWyatt Wood 79016012806SWyatt Wood struct dmub_rb_cmd_abm_init_config { 79116012806SWyatt Wood struct dmub_cmd_header header; 79216012806SWyatt Wood struct dmub_cmd_abm_init_config_data abm_init_config_data; 79316012806SWyatt Wood }; 79416012806SWyatt Wood 7957c008829SNicholas Kazlauskas union dmub_rb_cmd { 796dc6e2448SWyatt Wood struct dmub_rb_cmd_lock_hw lock_hw; 7977c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write read_modify_write; 7987c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 7997c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write burst_write; 8007c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait reg_wait; 8017c008829SNicholas Kazlauskas struct dmub_rb_cmd_common cmd_common; 8027c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 8037c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 8047c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 8057c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init dpphy_init; 8067c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 807d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version psr_set_version; 8087c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 809d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_enable psr_enable; 8107c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level psr_set_level; 811672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static psr_force_static; 812bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 81352f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall mall; 814e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 815e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 816e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level abm_set_level; 817e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 818e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 81916012806SWyatt Wood struct dmub_rb_cmd_abm_init_config abm_init_config; 820d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access dp_aux_access; 821d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable outbox1_enable; 8227c008829SNicholas Kazlauskas }; 8237c008829SNicholas Kazlauskas 824d9beecfcSAnthony Koo union dmub_rb_out_cmd { 825d9beecfcSAnthony Koo struct dmub_rb_cmd_common cmd_common; 826d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 827d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 828d9beecfcSAnthony Koo }; 8297c008829SNicholas Kazlauskas #pragma pack(pop) 8307c008829SNicholas Kazlauskas 83184034ad4SAnthony Koo 83284034ad4SAnthony Koo //============================================================================== 83384034ad4SAnthony Koo //</DMUB_CMD>=================================================================== 83484034ad4SAnthony Koo //============================================================================== 83584034ad4SAnthony Koo //< DMUB_RB>==================================================================== 83684034ad4SAnthony Koo //============================================================================== 83784034ad4SAnthony Koo 83884034ad4SAnthony Koo #if defined(__cplusplus) 83984034ad4SAnthony Koo extern "C" { 84084034ad4SAnthony Koo #endif 84184034ad4SAnthony Koo 84284034ad4SAnthony Koo struct dmub_rb_init_params { 84384034ad4SAnthony Koo void *ctx; 84484034ad4SAnthony Koo void *base_address; 84584034ad4SAnthony Koo uint32_t capacity; 84684034ad4SAnthony Koo uint32_t read_ptr; 84784034ad4SAnthony Koo uint32_t write_ptr; 84884034ad4SAnthony Koo }; 84984034ad4SAnthony Koo 85084034ad4SAnthony Koo struct dmub_rb { 85184034ad4SAnthony Koo void *base_address; 85284034ad4SAnthony Koo uint32_t data_count; 85384034ad4SAnthony Koo uint32_t rptr; 85484034ad4SAnthony Koo uint32_t wrpt; 85584034ad4SAnthony Koo uint32_t capacity; 85684034ad4SAnthony Koo 85784034ad4SAnthony Koo void *ctx; 85884034ad4SAnthony Koo void *dmub; 85984034ad4SAnthony Koo }; 86084034ad4SAnthony Koo 86184034ad4SAnthony Koo 86284034ad4SAnthony Koo static inline bool dmub_rb_empty(struct dmub_rb *rb) 86384034ad4SAnthony Koo { 86484034ad4SAnthony Koo return (rb->wrpt == rb->rptr); 86584034ad4SAnthony Koo } 86684034ad4SAnthony Koo 86784034ad4SAnthony Koo static inline bool dmub_rb_full(struct dmub_rb *rb) 86884034ad4SAnthony Koo { 86984034ad4SAnthony Koo uint32_t data_count; 87084034ad4SAnthony Koo 87184034ad4SAnthony Koo if (rb->wrpt >= rb->rptr) 87284034ad4SAnthony Koo data_count = rb->wrpt - rb->rptr; 87384034ad4SAnthony Koo else 87484034ad4SAnthony Koo data_count = rb->capacity - (rb->rptr - rb->wrpt); 87584034ad4SAnthony Koo 87684034ad4SAnthony Koo return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 87784034ad4SAnthony Koo } 87884034ad4SAnthony Koo 87984034ad4SAnthony Koo static inline bool dmub_rb_push_front(struct dmub_rb *rb, 88084034ad4SAnthony Koo const union dmub_rb_cmd *cmd) 88184034ad4SAnthony Koo { 88284034ad4SAnthony Koo uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t); 88384034ad4SAnthony Koo const uint64_t *src = (const uint64_t *)cmd; 88484034ad4SAnthony Koo int i; 88584034ad4SAnthony Koo 88684034ad4SAnthony Koo if (dmub_rb_full(rb)) 88784034ad4SAnthony Koo return false; 88884034ad4SAnthony Koo 88984034ad4SAnthony Koo // copying data 89084034ad4SAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 89184034ad4SAnthony Koo *dst++ = *src++; 89284034ad4SAnthony Koo 89384034ad4SAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 89484034ad4SAnthony Koo 89584034ad4SAnthony Koo if (rb->wrpt >= rb->capacity) 89684034ad4SAnthony Koo rb->wrpt %= rb->capacity; 89784034ad4SAnthony Koo 89884034ad4SAnthony Koo return true; 89984034ad4SAnthony Koo } 90084034ad4SAnthony Koo 901d9beecfcSAnthony Koo static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 902d9beecfcSAnthony Koo const union dmub_rb_out_cmd *cmd) 903d9beecfcSAnthony Koo { 904d9beecfcSAnthony Koo uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 905d9beecfcSAnthony Koo const uint8_t *src = (uint8_t *)cmd; 906d9beecfcSAnthony Koo 907d9beecfcSAnthony Koo if (dmub_rb_full(rb)) 908d9beecfcSAnthony Koo return false; 909d9beecfcSAnthony Koo 910d9beecfcSAnthony Koo dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 911d9beecfcSAnthony Koo 912d9beecfcSAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 913d9beecfcSAnthony Koo 914d9beecfcSAnthony Koo if (rb->wrpt >= rb->capacity) 915d9beecfcSAnthony Koo rb->wrpt %= rb->capacity; 916d9beecfcSAnthony Koo 917d9beecfcSAnthony Koo return true; 918d9beecfcSAnthony Koo } 919d9beecfcSAnthony Koo 92084034ad4SAnthony Koo static inline bool dmub_rb_front(struct dmub_rb *rb, 92184034ad4SAnthony Koo union dmub_rb_cmd *cmd) 92284034ad4SAnthony Koo { 92384034ad4SAnthony Koo uint8_t *rd_ptr = (uint8_t *)rb->base_address + rb->rptr; 92484034ad4SAnthony Koo 92584034ad4SAnthony Koo if (dmub_rb_empty(rb)) 92684034ad4SAnthony Koo return false; 92784034ad4SAnthony Koo 92884034ad4SAnthony Koo dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 92984034ad4SAnthony Koo 93084034ad4SAnthony Koo return true; 93184034ad4SAnthony Koo } 93284034ad4SAnthony Koo 933d9beecfcSAnthony Koo static inline bool dmub_rb_out_front(struct dmub_rb *rb, 934d9beecfcSAnthony Koo union dmub_rb_out_cmd *cmd) 935d9beecfcSAnthony Koo { 936d9beecfcSAnthony Koo const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 937d9beecfcSAnthony Koo uint64_t *dst = (uint64_t *)cmd; 938d9beecfcSAnthony Koo int i; 939d9beecfcSAnthony Koo 940d9beecfcSAnthony Koo if (dmub_rb_empty(rb)) 941d9beecfcSAnthony Koo return false; 942d9beecfcSAnthony Koo 943d9beecfcSAnthony Koo // copying data 944d9beecfcSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 945d9beecfcSAnthony Koo *dst++ = *src++; 946d9beecfcSAnthony Koo 947d9beecfcSAnthony Koo return true; 948d9beecfcSAnthony Koo } 949d9beecfcSAnthony Koo 95084034ad4SAnthony Koo static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 95184034ad4SAnthony Koo { 95284034ad4SAnthony Koo if (dmub_rb_empty(rb)) 95384034ad4SAnthony Koo return false; 95484034ad4SAnthony Koo 95584034ad4SAnthony Koo rb->rptr += DMUB_RB_CMD_SIZE; 95684034ad4SAnthony Koo 95784034ad4SAnthony Koo if (rb->rptr >= rb->capacity) 95884034ad4SAnthony Koo rb->rptr %= rb->capacity; 95984034ad4SAnthony Koo 96084034ad4SAnthony Koo return true; 96184034ad4SAnthony Koo } 96284034ad4SAnthony Koo 96384034ad4SAnthony Koo static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 96484034ad4SAnthony Koo { 96584034ad4SAnthony Koo uint32_t rptr = rb->rptr; 96684034ad4SAnthony Koo uint32_t wptr = rb->wrpt; 96784034ad4SAnthony Koo 96884034ad4SAnthony Koo while (rptr != wptr) { 96984034ad4SAnthony Koo uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t); 97084034ad4SAnthony Koo int i; 97184034ad4SAnthony Koo 97284034ad4SAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 9738906e5bcSYe Bin *data++; 97484034ad4SAnthony Koo 97584034ad4SAnthony Koo rptr += DMUB_RB_CMD_SIZE; 97684034ad4SAnthony Koo if (rptr >= rb->capacity) 97784034ad4SAnthony Koo rptr %= rb->capacity; 97884034ad4SAnthony Koo } 97984034ad4SAnthony Koo } 98084034ad4SAnthony Koo 98184034ad4SAnthony Koo static inline void dmub_rb_init(struct dmub_rb *rb, 98284034ad4SAnthony Koo struct dmub_rb_init_params *init_params) 98384034ad4SAnthony Koo { 98484034ad4SAnthony Koo rb->base_address = init_params->base_address; 98584034ad4SAnthony Koo rb->capacity = init_params->capacity; 98684034ad4SAnthony Koo rb->rptr = init_params->read_ptr; 98784034ad4SAnthony Koo rb->wrpt = init_params->write_ptr; 98884034ad4SAnthony Koo } 98984034ad4SAnthony Koo 99084034ad4SAnthony Koo #if defined(__cplusplus) 99184034ad4SAnthony Koo } 99284034ad4SAnthony Koo #endif 99384034ad4SAnthony Koo 99484034ad4SAnthony Koo //============================================================================== 99584034ad4SAnthony Koo //</DMUB_RB>==================================================================== 99684034ad4SAnthony Koo //============================================================================== 99784034ad4SAnthony Koo 9987c008829SNicholas Kazlauskas #endif /* _DMUB_CMD_H_ */ 999