17c008829SNicholas Kazlauskas /* 27c008829SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 37c008829SNicholas Kazlauskas * 47c008829SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 57c008829SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 67c008829SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 77c008829SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87c008829SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 97c008829SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 107c008829SNicholas Kazlauskas * 117c008829SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 127c008829SNicholas Kazlauskas * all copies or substantial portions of the Software. 137c008829SNicholas Kazlauskas * 147c008829SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157c008829SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167c008829SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177c008829SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187c008829SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197c008829SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207c008829SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 217c008829SNicholas Kazlauskas * 227c008829SNicholas Kazlauskas * Authors: AMD 237c008829SNicholas Kazlauskas * 247c008829SNicholas Kazlauskas */ 257c008829SNicholas Kazlauskas 265624c345SAnthony Koo #ifndef DMUB_CMD_H 275624c345SAnthony Koo #define DMUB_CMD_H 287c008829SNicholas Kazlauskas 298b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 308b19a4e3SAnthony Koo #include "dmub_fw_types.h" 318b19a4e3SAnthony Koo #include "include_legacy/atomfirmware.h" 328b19a4e3SAnthony Koo 338b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) 348b19a4e3SAnthony Koo #include <string.h> 358b19a4e3SAnthony Koo #endif 368b19a4e3SAnthony Koo #else 378b19a4e3SAnthony Koo 3884034ad4SAnthony Koo #include <asm/byteorder.h> 3984034ad4SAnthony Koo #include <linux/types.h> 4084034ad4SAnthony Koo #include <linux/string.h> 4184034ad4SAnthony Koo #include <linux/delay.h> 4284034ad4SAnthony Koo 437c008829SNicholas Kazlauskas #include "atomfirmware.h" 4422aa5614SYongqiang Sun 458b19a4e3SAnthony Koo #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 468b19a4e3SAnthony Koo 4784034ad4SAnthony Koo //<DMUB_TYPES>================================================================== 4884034ad4SAnthony Koo /* Basic type definitions. */ 4984034ad4SAnthony Koo 508b19a4e3SAnthony Koo #define __forceinline inline 518b19a4e3SAnthony Koo 521a595f28SAnthony Koo /** 531a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled gradually 541a595f28SAnthony Koo * by slowly reversing all backlight programming and pixel compensation. 551a595f28SAnthony Koo */ 5684034ad4SAnthony Koo #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 571a595f28SAnthony Koo 581a595f28SAnthony Koo /** 591a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 601a595f28SAnthony Koo * and undo all backlight programming and pixel compensation. 611a595f28SAnthony Koo */ 6284034ad4SAnthony Koo #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 631a595f28SAnthony Koo 641a595f28SAnthony Koo /** 651a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately 661a595f28SAnthony Koo * and keep the current backlight programming and pixel compensation. 671a595f28SAnthony Koo */ 68d9beecfcSAnthony Koo #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 691a595f28SAnthony Koo 701a595f28SAnthony Koo /** 711a595f28SAnthony Koo * Flag from driver to set the current ABM pipe index or ABM operating level. 721a595f28SAnthony Koo */ 7384034ad4SAnthony Koo #define SET_ABM_PIPE_NORMAL 1 7484034ad4SAnthony Koo 751a595f28SAnthony Koo /** 761a595f28SAnthony Koo * Number of ambient light levels in ABM algorithm. 771a595f28SAnthony Koo */ 781a595f28SAnthony Koo #define NUM_AMBI_LEVEL 5 791a595f28SAnthony Koo 801a595f28SAnthony Koo /** 811a595f28SAnthony Koo * Number of operating/aggression levels in ABM algorithm. 821a595f28SAnthony Koo */ 831a595f28SAnthony Koo #define NUM_AGGR_LEVEL 4 841a595f28SAnthony Koo 851a595f28SAnthony Koo /** 861a595f28SAnthony Koo * Number of segments in the gamma curve. 871a595f28SAnthony Koo */ 881a595f28SAnthony Koo #define NUM_POWER_FN_SEGS 8 891a595f28SAnthony Koo 901a595f28SAnthony Koo /** 911a595f28SAnthony Koo * Number of segments in the backlight curve. 921a595f28SAnthony Koo */ 931a595f28SAnthony Koo #define NUM_BL_CURVE_SEGS 16 941a595f28SAnthony Koo 9585f4bc0cSAlvin Lee /* Maximum number of SubVP streams */ 9685f4bc0cSAlvin Lee #define DMUB_MAX_SUBVP_STREAMS 2 9785f4bc0cSAlvin Lee 9884034ad4SAnthony Koo /* Maximum number of streams on any ASIC. */ 9984034ad4SAnthony Koo #define DMUB_MAX_STREAMS 6 10084034ad4SAnthony Koo 10184034ad4SAnthony Koo /* Maximum number of planes on any ASIC. */ 10284034ad4SAnthony Koo #define DMUB_MAX_PLANES 6 10384034ad4SAnthony Koo 10470732504SYongqiang Sun /* Trace buffer offset for entry */ 10570732504SYongqiang Sun #define TRACE_BUFFER_ENTRY_OFFSET 16 10670732504SYongqiang Sun 107592a6318SAnthony Koo /** 10883eb5385SDavid Zhang * Maximum number of dirty rects supported by FW. 10983eb5385SDavid Zhang */ 11083eb5385SDavid Zhang #define DMUB_MAX_DIRTY_RECTS 3 11183eb5385SDavid Zhang 11283eb5385SDavid Zhang /** 113f56c837aSMikita Lipski * 114f56c837aSMikita Lipski * PSR control version legacy 115f56c837aSMikita Lipski */ 116f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117f56c837aSMikita Lipski /** 118f56c837aSMikita Lipski * PSR control version with multi edp support 119f56c837aSMikita Lipski */ 120f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121f56c837aSMikita Lipski 122f56c837aSMikita Lipski 123f56c837aSMikita Lipski /** 12463de4f04SJake Wang * ABM control version legacy 125e922057bSJake Wang */ 12663de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127e922057bSJake Wang 128e922057bSJake Wang /** 12963de4f04SJake Wang * ABM control version with multi edp support 130e922057bSJake Wang */ 13163de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132e922057bSJake Wang 133e922057bSJake Wang /** 134592a6318SAnthony Koo * Physical framebuffer address location, 64-bit. 135592a6318SAnthony Koo */ 13684034ad4SAnthony Koo #ifndef PHYSICAL_ADDRESS_LOC 13784034ad4SAnthony Koo #define PHYSICAL_ADDRESS_LOC union large_integer 13884034ad4SAnthony Koo #endif 13984034ad4SAnthony Koo 140592a6318SAnthony Koo /** 141592a6318SAnthony Koo * OS/FW agnostic memcpy 142592a6318SAnthony Koo */ 14384034ad4SAnthony Koo #ifndef dmub_memcpy 14484034ad4SAnthony Koo #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 14584034ad4SAnthony Koo #endif 14684034ad4SAnthony Koo 147592a6318SAnthony Koo /** 148592a6318SAnthony Koo * OS/FW agnostic memset 149592a6318SAnthony Koo */ 15084034ad4SAnthony Koo #ifndef dmub_memset 15184034ad4SAnthony Koo #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 15284034ad4SAnthony Koo #endif 15384034ad4SAnthony Koo 154d9beecfcSAnthony Koo #if defined(__cplusplus) 155d9beecfcSAnthony Koo extern "C" { 156d9beecfcSAnthony Koo #endif 157d9beecfcSAnthony Koo 158592a6318SAnthony Koo /** 159592a6318SAnthony Koo * OS/FW agnostic udelay 160592a6318SAnthony Koo */ 16184034ad4SAnthony Koo #ifndef dmub_udelay 16284034ad4SAnthony Koo #define dmub_udelay(microseconds) udelay(microseconds) 16384034ad4SAnthony Koo #endif 16484034ad4SAnthony Koo 165592a6318SAnthony Koo /** 166592a6318SAnthony Koo * union dmub_addr - DMUB physical/virtual 64-bit address. 167592a6318SAnthony Koo */ 16884034ad4SAnthony Koo union dmub_addr { 16984034ad4SAnthony Koo struct { 170592a6318SAnthony Koo uint32_t low_part; /**< Lower 32 bits */ 171592a6318SAnthony Koo uint32_t high_part; /**< Upper 32 bits */ 172592a6318SAnthony Koo } u; /*<< Low/high bit access */ 173592a6318SAnthony Koo uint64_t quad_part; /*<< 64 bit address */ 17484034ad4SAnthony Koo }; 17584034ad4SAnthony Koo 1761a595f28SAnthony Koo /** 17783eb5385SDavid Zhang * Dirty rect definition. 17883eb5385SDavid Zhang */ 17983eb5385SDavid Zhang struct dmub_rect { 18083eb5385SDavid Zhang /** 18183eb5385SDavid Zhang * Dirty rect x offset. 18283eb5385SDavid Zhang */ 18383eb5385SDavid Zhang uint32_t x; 18483eb5385SDavid Zhang 18583eb5385SDavid Zhang /** 18683eb5385SDavid Zhang * Dirty rect y offset. 18783eb5385SDavid Zhang */ 18883eb5385SDavid Zhang uint32_t y; 18983eb5385SDavid Zhang 19083eb5385SDavid Zhang /** 19183eb5385SDavid Zhang * Dirty rect width. 19283eb5385SDavid Zhang */ 19383eb5385SDavid Zhang uint32_t width; 19483eb5385SDavid Zhang 19583eb5385SDavid Zhang /** 19683eb5385SDavid Zhang * Dirty rect height. 19783eb5385SDavid Zhang */ 19883eb5385SDavid Zhang uint32_t height; 19983eb5385SDavid Zhang }; 20083eb5385SDavid Zhang 20183eb5385SDavid Zhang /** 2021a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 2031a595f28SAnthony Koo */ 20484034ad4SAnthony Koo union dmub_psr_debug_flags { 2051a595f28SAnthony Koo /** 2061a595f28SAnthony Koo * Debug flags. 2071a595f28SAnthony Koo */ 20884034ad4SAnthony Koo struct { 2091a595f28SAnthony Koo /** 2101a595f28SAnthony Koo * Enable visual confirm in FW. 2111a595f28SAnthony Koo */ 212447f3d0fSAnthony Koo uint32_t visual_confirm : 1; 21383eb5385SDavid Zhang 21483eb5385SDavid Zhang /** 21583eb5385SDavid Zhang * Force all selective updates to bw full frame updates. 21683eb5385SDavid Zhang */ 21783eb5385SDavid Zhang uint32_t force_full_frame_update : 1; 21883eb5385SDavid Zhang 2191a595f28SAnthony Koo /** 2201a595f28SAnthony Koo * Use HW Lock Mgr object to do HW locking in FW. 2211a595f28SAnthony Koo */ 222447f3d0fSAnthony Koo uint32_t use_hw_lock_mgr : 1; 2231a595f28SAnthony Koo 2241a595f28SAnthony Koo /** 225548f2125SRobin Chen * Use TPS3 signal when restore main link. 2261a595f28SAnthony Koo */ 227548f2125SRobin Chen uint32_t force_wakeup_by_tps3 : 1; 22884034ad4SAnthony Koo } bitfields; 22984034ad4SAnthony Koo 2301a595f28SAnthony Koo /** 2311a595f28SAnthony Koo * Union for debug flags. 2321a595f28SAnthony Koo */ 233447f3d0fSAnthony Koo uint32_t u32All; 23484034ad4SAnthony Koo }; 23584034ad4SAnthony Koo 2361a595f28SAnthony Koo /** 2371a595f28SAnthony Koo * DMUB feature capabilities. 2381a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2391a595f28SAnthony Koo */ 24034ba432cSAnthony Koo struct dmub_feature_caps { 2411a595f28SAnthony Koo /** 2421a595f28SAnthony Koo * Max PSR version supported by FW. 2431a595f28SAnthony Koo */ 24434ba432cSAnthony Koo uint8_t psr; 24500fa7f03SRodrigo Siqueira uint8_t fw_assisted_mclk_switch; 24600fa7f03SRodrigo Siqueira uint8_t reserved[6]; 24734ba432cSAnthony Koo }; 24834ba432cSAnthony Koo 24984034ad4SAnthony Koo #if defined(__cplusplus) 25084034ad4SAnthony Koo } 25184034ad4SAnthony Koo #endif 25284034ad4SAnthony Koo 25384034ad4SAnthony Koo //============================================================================== 25484034ad4SAnthony Koo //</DMUB_TYPES>================================================================= 25584034ad4SAnthony Koo //============================================================================== 25684034ad4SAnthony Koo //< DMUB_META>================================================================== 25784034ad4SAnthony Koo //============================================================================== 25884034ad4SAnthony Koo #pragma pack(push, 1) 25984034ad4SAnthony Koo 26084034ad4SAnthony Koo /* Magic value for identifying dmub_fw_meta_info */ 26184034ad4SAnthony Koo #define DMUB_FW_META_MAGIC 0x444D5542 26284034ad4SAnthony Koo 26384034ad4SAnthony Koo /* Offset from the end of the file to the dmub_fw_meta_info */ 26484034ad4SAnthony Koo #define DMUB_FW_META_OFFSET 0x24 26584034ad4SAnthony Koo 26684034ad4SAnthony Koo /** 26784034ad4SAnthony Koo * struct dmub_fw_meta_info - metadata associated with fw binary 26884034ad4SAnthony Koo * 26984034ad4SAnthony Koo * NOTE: This should be considered a stable API. Fields should 27084034ad4SAnthony Koo * not be repurposed or reordered. New fields should be 27184034ad4SAnthony Koo * added instead to extend the structure. 27284034ad4SAnthony Koo * 27384034ad4SAnthony Koo * @magic_value: magic value identifying DMUB firmware meta info 27484034ad4SAnthony Koo * @fw_region_size: size of the firmware state region 27584034ad4SAnthony Koo * @trace_buffer_size: size of the tracebuffer region 27684034ad4SAnthony Koo * @fw_version: the firmware version information 277b2265774SAnthony Koo * @dal_fw: 1 if the firmware is DAL 27884034ad4SAnthony Koo */ 27984034ad4SAnthony Koo struct dmub_fw_meta_info { 280592a6318SAnthony Koo uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 281592a6318SAnthony Koo uint32_t fw_region_size; /**< size of the firmware state region */ 282592a6318SAnthony Koo uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 283592a6318SAnthony Koo uint32_t fw_version; /**< the firmware version information */ 284592a6318SAnthony Koo uint8_t dal_fw; /**< 1 if the firmware is DAL */ 285592a6318SAnthony Koo uint8_t reserved[3]; /**< padding bits */ 28684034ad4SAnthony Koo }; 28784034ad4SAnthony Koo 288592a6318SAnthony Koo /** 289592a6318SAnthony Koo * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 290592a6318SAnthony Koo */ 29184034ad4SAnthony Koo union dmub_fw_meta { 292592a6318SAnthony Koo struct dmub_fw_meta_info info; /**< metadata info */ 293592a6318SAnthony Koo uint8_t reserved[64]; /**< padding bits */ 29484034ad4SAnthony Koo }; 29584034ad4SAnthony Koo 29684034ad4SAnthony Koo #pragma pack(pop) 297788408b7SAnthony Koo 29884034ad4SAnthony Koo //============================================================================== 2996b66208fSYongqiang Sun //< DMUB Trace Buffer>================================================================ 3006b66208fSYongqiang Sun //============================================================================== 301592a6318SAnthony Koo /** 302592a6318SAnthony Koo * dmub_trace_code_t - firmware trace code, 32-bits 303592a6318SAnthony Koo */ 3046b66208fSYongqiang Sun typedef uint32_t dmub_trace_code_t; 3056b66208fSYongqiang Sun 306592a6318SAnthony Koo /** 307592a6318SAnthony Koo * struct dmcub_trace_buf_entry - Firmware trace entry 308592a6318SAnthony Koo */ 3096b66208fSYongqiang Sun struct dmcub_trace_buf_entry { 310592a6318SAnthony Koo dmub_trace_code_t trace_code; /**< trace code for the event */ 311592a6318SAnthony Koo uint32_t tick_count; /**< the tick count at time of trace */ 312592a6318SAnthony Koo uint32_t param0; /**< trace defined parameter 0 */ 313592a6318SAnthony Koo uint32_t param1; /**< trace defined parameter 1 */ 3146b66208fSYongqiang Sun }; 3156b66208fSYongqiang Sun 3166b66208fSYongqiang Sun //============================================================================== 317788408b7SAnthony Koo //< DMUB_STATUS>================================================================ 318788408b7SAnthony Koo //============================================================================== 319788408b7SAnthony Koo 320788408b7SAnthony Koo /** 321788408b7SAnthony Koo * DMCUB scratch registers can be used to determine firmware status. 322788408b7SAnthony Koo * Current scratch register usage is as follows: 323788408b7SAnthony Koo * 324492dd8a8SAnthony Koo * SCRATCH0: FW Boot Status register 325021eaef8SAnthony Koo * SCRATCH5: LVTMA Status Register 326492dd8a8SAnthony Koo * SCRATCH15: FW Boot Options register 327788408b7SAnthony Koo */ 328788408b7SAnthony Koo 329592a6318SAnthony Koo /** 330592a6318SAnthony Koo * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 331592a6318SAnthony Koo */ 332492dd8a8SAnthony Koo union dmub_fw_boot_status { 333492dd8a8SAnthony Koo struct { 334592a6318SAnthony Koo uint32_t dal_fw : 1; /**< 1 if DAL FW */ 335592a6318SAnthony Koo uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 336592a6318SAnthony Koo uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 337592a6318SAnthony Koo uint32_t restore_required : 1; /**< 1 if driver should call restore */ 33801934c30SAnthony Koo uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 33901934c30SAnthony Koo uint32_t reserved : 1; 34001934c30SAnthony Koo uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 34101934c30SAnthony Koo 342592a6318SAnthony Koo } bits; /**< status bits */ 343592a6318SAnthony Koo uint32_t all; /**< 32-bit access to status bits */ 344492dd8a8SAnthony Koo }; 345492dd8a8SAnthony Koo 346592a6318SAnthony Koo /** 347592a6318SAnthony Koo * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 348592a6318SAnthony Koo */ 349492dd8a8SAnthony Koo enum dmub_fw_boot_status_bit { 350592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 351592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 352592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 353592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 3541e0958bbSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 35501934c30SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 356492dd8a8SAnthony Koo }; 357492dd8a8SAnthony Koo 358021eaef8SAnthony Koo /* Register bit definition for SCRATCH5 */ 359021eaef8SAnthony Koo union dmub_lvtma_status { 360021eaef8SAnthony Koo struct { 361021eaef8SAnthony Koo uint32_t psp_ok : 1; 362021eaef8SAnthony Koo uint32_t edp_on : 1; 363021eaef8SAnthony Koo uint32_t reserved : 30; 364021eaef8SAnthony Koo } bits; 365021eaef8SAnthony Koo uint32_t all; 366021eaef8SAnthony Koo }; 367021eaef8SAnthony Koo 368021eaef8SAnthony Koo enum dmub_lvtma_status_bit { 369021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 370021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 371021eaef8SAnthony Koo }; 372021eaef8SAnthony Koo 373592a6318SAnthony Koo /** 3741e0958bbSAnthony Koo * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 375592a6318SAnthony Koo */ 376492dd8a8SAnthony Koo union dmub_fw_boot_options { 377492dd8a8SAnthony Koo struct { 378592a6318SAnthony Koo uint32_t pemu_env : 1; /**< 1 if PEMU */ 379592a6318SAnthony Koo uint32_t fpga_env : 1; /**< 1 if FPGA */ 380592a6318SAnthony Koo uint32_t optimized_init : 1; /**< 1 if optimized init */ 381592a6318SAnthony Koo uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 382592a6318SAnthony Koo uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 383592a6318SAnthony Koo uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 384b04cb192SNicholas Kazlauskas uint32_t z10_disable: 1; /**< 1 to disable z10 */ 385b0ce6272SMeenakshikumar Somasundaram uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 3861e0958bbSAnthony Koo uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 3873137f792SHansen uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 3883137f792SHansen uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 3893137f792SHansen /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 3903137f792SHansen uint32_t power_optimization: 1; 391b129c94eSAnthony Koo uint32_t diag_env: 1; /* 1 if diagnostic environment */ 3925cef7e8eSAnthony Koo uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 393ea5a4db9SAnthony Koo uint32_t usb4_cm_version: 1; /**< 1 CM support */ 394b129c94eSAnthony Koo 3950f05c998SJimmy Kizito uint32_t reserved : 17; /**< reserved */ 396592a6318SAnthony Koo } bits; /**< boot bits */ 397592a6318SAnthony Koo uint32_t all; /**< 32-bit access to bits */ 398492dd8a8SAnthony Koo }; 399492dd8a8SAnthony Koo 400492dd8a8SAnthony Koo enum dmub_fw_boot_options_bit { 401592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 402592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 403592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 404492dd8a8SAnthony Koo }; 405492dd8a8SAnthony Koo 406788408b7SAnthony Koo //============================================================================== 407788408b7SAnthony Koo //</DMUB_STATUS>================================================================ 40884034ad4SAnthony Koo //============================================================================== 40984034ad4SAnthony Koo //< DMUB_VBIOS>================================================================= 41084034ad4SAnthony Koo //============================================================================== 41184034ad4SAnthony Koo 41284034ad4SAnthony Koo /* 413592a6318SAnthony Koo * enum dmub_cmd_vbios_type - VBIOS commands. 414592a6318SAnthony Koo * 41584034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 41684034ad4SAnthony Koo * Do not reuse or modify IDs. 41784034ad4SAnthony Koo */ 41884034ad4SAnthony Koo enum dmub_cmd_vbios_type { 419592a6318SAnthony Koo /** 420592a6318SAnthony Koo * Configures the DIG encoder. 421592a6318SAnthony Koo */ 42284034ad4SAnthony Koo DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 423592a6318SAnthony Koo /** 424592a6318SAnthony Koo * Controls the PHY. 425592a6318SAnthony Koo */ 42684034ad4SAnthony Koo DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 427592a6318SAnthony Koo /** 428592a6318SAnthony Koo * Sets the pixel clock/symbol clock. 429592a6318SAnthony Koo */ 43084034ad4SAnthony Koo DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 431592a6318SAnthony Koo /** 432592a6318SAnthony Koo * Enables or disables power gating. 433592a6318SAnthony Koo */ 43484034ad4SAnthony Koo DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 43541f91315SNicholas Kazlauskas /** 43641f91315SNicholas Kazlauskas * Controls embedded panels. 43741f91315SNicholas Kazlauskas */ 4382ac685bfSAnthony Koo DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 43941f91315SNicholas Kazlauskas /** 44041f91315SNicholas Kazlauskas * Query DP alt status on a transmitter. 44141f91315SNicholas Kazlauskas */ 44241f91315SNicholas Kazlauskas DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 44384034ad4SAnthony Koo }; 44484034ad4SAnthony Koo 44584034ad4SAnthony Koo //============================================================================== 44684034ad4SAnthony Koo //</DMUB_VBIOS>================================================================= 44784034ad4SAnthony Koo //============================================================================== 44884034ad4SAnthony Koo //< DMUB_GPINT>================================================================= 44984034ad4SAnthony Koo //============================================================================== 45084034ad4SAnthony Koo 45184034ad4SAnthony Koo /** 45284034ad4SAnthony Koo * The shifts and masks below may alternatively be used to format and read 45384034ad4SAnthony Koo * the command register bits. 45484034ad4SAnthony Koo */ 45584034ad4SAnthony Koo 45684034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 45784034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_SHIFT 0 45884034ad4SAnthony Koo 45984034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 46084034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 46184034ad4SAnthony Koo 46284034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_MASK 0xF 46384034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_SHIFT 28 46484034ad4SAnthony Koo 46584034ad4SAnthony Koo /** 46684034ad4SAnthony Koo * Command responses. 46784034ad4SAnthony Koo */ 46884034ad4SAnthony Koo 469592a6318SAnthony Koo /** 470592a6318SAnthony Koo * Return response for DMUB_GPINT__STOP_FW command. 471592a6318SAnthony Koo */ 47284034ad4SAnthony Koo #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 47384034ad4SAnthony Koo 47484034ad4SAnthony Koo /** 475592a6318SAnthony Koo * union dmub_gpint_data_register - Format for sending a command via the GPINT. 47684034ad4SAnthony Koo */ 47784034ad4SAnthony Koo union dmub_gpint_data_register { 47884034ad4SAnthony Koo struct { 479592a6318SAnthony Koo uint32_t param : 16; /**< 16-bit parameter */ 480592a6318SAnthony Koo uint32_t command_code : 12; /**< GPINT command */ 481592a6318SAnthony Koo uint32_t status : 4; /**< Command status bit */ 482592a6318SAnthony Koo } bits; /**< GPINT bit access */ 483592a6318SAnthony Koo uint32_t all; /**< GPINT 32-bit access */ 48484034ad4SAnthony Koo }; 48584034ad4SAnthony Koo 48684034ad4SAnthony Koo /* 487592a6318SAnthony Koo * enum dmub_gpint_command - GPINT command to DMCUB FW 488592a6318SAnthony Koo * 48984034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 49084034ad4SAnthony Koo * Do not reuse or modify IDs. 49184034ad4SAnthony Koo */ 49284034ad4SAnthony Koo enum dmub_gpint_command { 493592a6318SAnthony Koo /** 494592a6318SAnthony Koo * Invalid command, ignored. 495592a6318SAnthony Koo */ 49684034ad4SAnthony Koo DMUB_GPINT__INVALID_COMMAND = 0, 497592a6318SAnthony Koo /** 498592a6318SAnthony Koo * DESC: Queries the firmware version. 499592a6318SAnthony Koo * RETURN: Firmware version. 500592a6318SAnthony Koo */ 50184034ad4SAnthony Koo DMUB_GPINT__GET_FW_VERSION = 1, 502592a6318SAnthony Koo /** 503592a6318SAnthony Koo * DESC: Halts the firmware. 504592a6318SAnthony Koo * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 505592a6318SAnthony Koo */ 50684034ad4SAnthony Koo DMUB_GPINT__STOP_FW = 2, 5071a595f28SAnthony Koo /** 5081a595f28SAnthony Koo * DESC: Get PSR state from FW. 5091a595f28SAnthony Koo * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 5101a595f28SAnthony Koo */ 51184034ad4SAnthony Koo DMUB_GPINT__GET_PSR_STATE = 7, 51280eba958SAnthony Koo /** 51380eba958SAnthony Koo * DESC: Notifies DMCUB of the currently active streams. 51480eba958SAnthony Koo * ARGS: Stream mask, 1 bit per active stream index. 51580eba958SAnthony Koo */ 51680eba958SAnthony Koo DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 5171a595f28SAnthony Koo /** 5181a595f28SAnthony Koo * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 5191a595f28SAnthony Koo * ARGS: We can measure residency from various points. The argument will specify the residency mode. 5201a595f28SAnthony Koo * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 5211a595f28SAnthony Koo * RETURN: PSR residency in milli-percent. 5221a595f28SAnthony Koo */ 523672251b2SAnthony Koo DMUB_GPINT__PSR_RESIDENCY = 9, 52401934c30SAnthony Koo 52501934c30SAnthony Koo /** 52601934c30SAnthony Koo * DESC: Notifies DMCUB detection is done so detection required can be cleared. 52701934c30SAnthony Koo */ 52801934c30SAnthony Koo DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 52984034ad4SAnthony Koo }; 53084034ad4SAnthony Koo 5310b51e7e8SAnthony Koo /** 5320b51e7e8SAnthony Koo * INBOX0 generic command definition 5330b51e7e8SAnthony Koo */ 5340b51e7e8SAnthony Koo union dmub_inbox0_cmd_common { 5350b51e7e8SAnthony Koo struct { 5360b51e7e8SAnthony Koo uint32_t command_code: 8; /**< INBOX0 command code */ 5370b51e7e8SAnthony Koo uint32_t param: 24; /**< 24-bit parameter */ 5380b51e7e8SAnthony Koo } bits; 5390b51e7e8SAnthony Koo uint32_t all; 5400b51e7e8SAnthony Koo }; 5410b51e7e8SAnthony Koo 5420b51e7e8SAnthony Koo /** 5430b51e7e8SAnthony Koo * INBOX0 hw_lock command definition 5440b51e7e8SAnthony Koo */ 5450b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw { 5460b51e7e8SAnthony Koo struct { 5470b51e7e8SAnthony Koo uint32_t command_code: 8; 5480b51e7e8SAnthony Koo 5490b51e7e8SAnthony Koo /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 5502412d339SAnthony Koo uint32_t hw_lock_client: 2; 5510b51e7e8SAnthony Koo 5520b51e7e8SAnthony Koo /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 5530b51e7e8SAnthony Koo uint32_t otg_inst: 3; 5540b51e7e8SAnthony Koo uint32_t opp_inst: 3; 5550b51e7e8SAnthony Koo uint32_t dig_inst: 3; 5560b51e7e8SAnthony Koo 5570b51e7e8SAnthony Koo /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 5580b51e7e8SAnthony Koo uint32_t lock_pipe: 1; 5590b51e7e8SAnthony Koo uint32_t lock_cursor: 1; 5600b51e7e8SAnthony Koo uint32_t lock_dig: 1; 5610b51e7e8SAnthony Koo uint32_t triple_buffer_lock: 1; 5620b51e7e8SAnthony Koo 5630b51e7e8SAnthony Koo uint32_t lock: 1; /**< Lock */ 5640b51e7e8SAnthony Koo uint32_t should_release: 1; /**< Release */ 5652412d339SAnthony Koo uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 5660b51e7e8SAnthony Koo } bits; 5670b51e7e8SAnthony Koo uint32_t all; 5680b51e7e8SAnthony Koo }; 5690b51e7e8SAnthony Koo 5700b51e7e8SAnthony Koo union dmub_inbox0_data_register { 5710b51e7e8SAnthony Koo union dmub_inbox0_cmd_common inbox0_cmd_common; 5720b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 5730b51e7e8SAnthony Koo }; 5740b51e7e8SAnthony Koo 5750b51e7e8SAnthony Koo enum dmub_inbox0_command { 5760b51e7e8SAnthony Koo /** 5770b51e7e8SAnthony Koo * DESC: Invalid command, ignored. 5780b51e7e8SAnthony Koo */ 5790b51e7e8SAnthony Koo DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 5800b51e7e8SAnthony Koo /** 5810b51e7e8SAnthony Koo * DESC: Notification to acquire/release HW lock 5820b51e7e8SAnthony Koo * ARGS: 5830b51e7e8SAnthony Koo */ 5840b51e7e8SAnthony Koo DMUB_INBOX0_CMD__HW_LOCK = 1, 5850b51e7e8SAnthony Koo }; 58684034ad4SAnthony Koo //============================================================================== 58784034ad4SAnthony Koo //</DMUB_GPINT>================================================================= 58884034ad4SAnthony Koo //============================================================================== 58984034ad4SAnthony Koo //< DMUB_CMD>=================================================================== 59084034ad4SAnthony Koo //============================================================================== 59184034ad4SAnthony Koo 592592a6318SAnthony Koo /** 593592a6318SAnthony Koo * Size in bytes of each DMUB command. 594592a6318SAnthony Koo */ 5957c008829SNicholas Kazlauskas #define DMUB_RB_CMD_SIZE 64 596592a6318SAnthony Koo 597592a6318SAnthony Koo /** 598592a6318SAnthony Koo * Maximum number of items in the DMUB ringbuffer. 599592a6318SAnthony Koo */ 6007c008829SNicholas Kazlauskas #define DMUB_RB_MAX_ENTRY 128 601592a6318SAnthony Koo 602592a6318SAnthony Koo /** 603592a6318SAnthony Koo * Ringbuffer size in bytes. 604592a6318SAnthony Koo */ 6057c008829SNicholas Kazlauskas #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 606592a6318SAnthony Koo 607592a6318SAnthony Koo /** 608592a6318SAnthony Koo * REG_SET mask for reg offload. 609592a6318SAnthony Koo */ 6107c008829SNicholas Kazlauskas #define REG_SET_MASK 0xFFFF 6117c008829SNicholas Kazlauskas 612d4bbcecbSNicholas Kazlauskas /* 613592a6318SAnthony Koo * enum dmub_cmd_type - DMUB inbox command. 614592a6318SAnthony Koo * 615d4bbcecbSNicholas Kazlauskas * Command IDs should be treated as stable ABI. 616d4bbcecbSNicholas Kazlauskas * Do not reuse or modify IDs. 617d4bbcecbSNicholas Kazlauskas */ 618d4bbcecbSNicholas Kazlauskas enum dmub_cmd_type { 619592a6318SAnthony Koo /** 620592a6318SAnthony Koo * Invalid command. 621592a6318SAnthony Koo */ 622d4bbcecbSNicholas Kazlauskas DMUB_CMD__NULL = 0, 623592a6318SAnthony Koo /** 624592a6318SAnthony Koo * Read modify write register sequence offload. 625592a6318SAnthony Koo */ 626d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 627592a6318SAnthony Koo /** 628592a6318SAnthony Koo * Field update register sequence offload. 629592a6318SAnthony Koo */ 630d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 631592a6318SAnthony Koo /** 632592a6318SAnthony Koo * Burst write sequence offload. 633592a6318SAnthony Koo */ 634d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 635592a6318SAnthony Koo /** 636592a6318SAnthony Koo * Reg wait sequence offload. 637592a6318SAnthony Koo */ 638d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_REG_WAIT = 4, 639592a6318SAnthony Koo /** 640592a6318SAnthony Koo * Workaround to avoid HUBP underflow during NV12 playback. 641592a6318SAnthony Koo */ 642bae9c49bSYongqiang Sun DMUB_CMD__PLAT_54186_WA = 5, 6431a595f28SAnthony Koo /** 6441a595f28SAnthony Koo * Command type used to query FW feature caps. 6451a595f28SAnthony Koo */ 64634ba432cSAnthony Koo DMUB_CMD__QUERY_FEATURE_CAPS = 6, 6471a595f28SAnthony Koo /** 6481a595f28SAnthony Koo * Command type used for all PSR commands. 6491a595f28SAnthony Koo */ 650d4bbcecbSNicholas Kazlauskas DMUB_CMD__PSR = 64, 651592a6318SAnthony Koo /** 652592a6318SAnthony Koo * Command type used for all MALL commands. 653592a6318SAnthony Koo */ 65452f2e83eSBhawanpreet Lakha DMUB_CMD__MALL = 65, 6551a595f28SAnthony Koo /** 6561a595f28SAnthony Koo * Command type used for all ABM commands. 6571a595f28SAnthony Koo */ 658e6ea8c34SWyatt Wood DMUB_CMD__ABM = 66, 6591a595f28SAnthony Koo /** 66083eb5385SDavid Zhang * Command type used to update dirty rects in FW. 66183eb5385SDavid Zhang */ 66283eb5385SDavid Zhang DMUB_CMD__UPDATE_DIRTY_RECT = 67, 66383eb5385SDavid Zhang /** 66483eb5385SDavid Zhang * Command type used to update cursor info in FW. 66583eb5385SDavid Zhang */ 66683eb5385SDavid Zhang DMUB_CMD__UPDATE_CURSOR_INFO = 68, 66783eb5385SDavid Zhang /** 6681a595f28SAnthony Koo * Command type used for HW locking in FW. 6691a595f28SAnthony Koo */ 670788408b7SAnthony Koo DMUB_CMD__HW_LOCK = 69, 6711a595f28SAnthony Koo /** 6721a595f28SAnthony Koo * Command type used to access DP AUX. 6731a595f28SAnthony Koo */ 674d9beecfcSAnthony Koo DMUB_CMD__DP_AUX_ACCESS = 70, 6751a595f28SAnthony Koo /** 6761a595f28SAnthony Koo * Command type used for OUTBOX1 notification enable 6771a595f28SAnthony Koo */ 678d9beecfcSAnthony Koo DMUB_CMD__OUTBOX1_ENABLE = 71, 6795cef7e8eSAnthony Koo 680b04cb192SNicholas Kazlauskas /** 681b04cb192SNicholas Kazlauskas * Command type used for all idle optimization commands. 682b04cb192SNicholas Kazlauskas */ 683b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT = 72, 684b04cb192SNicholas Kazlauskas /** 685b04cb192SNicholas Kazlauskas * Command type used for all clock manager commands. 686b04cb192SNicholas Kazlauskas */ 687b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR = 73, 688b04cb192SNicholas Kazlauskas /** 689b04cb192SNicholas Kazlauskas * Command type used for all panel control commands. 690b04cb192SNicholas Kazlauskas */ 691b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL = 74, 692ac2e555eSAurabindo Pillai /** 693ac2e555eSAurabindo Pillai * Command type used for <TODO:description> 694ac2e555eSAurabindo Pillai */ 695ac2e555eSAurabindo Pillai DMUB_CMD__CAB_FOR_SS = 75, 69685f4bc0cSAlvin Lee 69785f4bc0cSAlvin Lee DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 69885f4bc0cSAlvin Lee 699592a6318SAnthony Koo /** 70076724b76SJimmy Kizito * Command type used for interfacing with DPIA. 70176724b76SJimmy Kizito */ 70276724b76SJimmy Kizito DMUB_CMD__DPIA = 77, 70376724b76SJimmy Kizito /** 704021eaef8SAnthony Koo * Command type used for EDID CEA parsing 705021eaef8SAnthony Koo */ 706021eaef8SAnthony Koo DMUB_CMD__EDID_CEA = 79, 707021eaef8SAnthony Koo /** 708c595fb05SWenjing Liu * Command type used for getting usbc cable ID 709c595fb05SWenjing Liu */ 710c595fb05SWenjing Liu DMUB_CMD_GET_USBC_CABLE_ID = 81, 711c595fb05SWenjing Liu /** 712ea5a4db9SAnthony Koo * Command type used to query HPD state. 713ea5a4db9SAnthony Koo */ 714ea5a4db9SAnthony Koo DMUB_CMD__QUERY_HPD_STATE = 82, 715ea5a4db9SAnthony Koo /** 716592a6318SAnthony Koo * Command type used for all VBIOS interface commands. 717592a6318SAnthony Koo */ 718d4bbcecbSNicholas Kazlauskas DMUB_CMD__VBIOS = 128, 7197c008829SNicholas Kazlauskas }; 7207c008829SNicholas Kazlauskas 721592a6318SAnthony Koo /** 722592a6318SAnthony Koo * enum dmub_out_cmd_type - DMUB outbox commands. 723592a6318SAnthony Koo */ 7243b37260bSAnthony Koo enum dmub_out_cmd_type { 725592a6318SAnthony Koo /** 726592a6318SAnthony Koo * Invalid outbox command, ignored. 727592a6318SAnthony Koo */ 7283b37260bSAnthony Koo DMUB_OUT_CMD__NULL = 0, 7291a595f28SAnthony Koo /** 7301a595f28SAnthony Koo * Command type used for DP AUX Reply data notification 7311a595f28SAnthony Koo */ 732d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_AUX_REPLY = 1, 733892b74a6SMeenakshikumar Somasundaram /** 734892b74a6SMeenakshikumar Somasundaram * Command type used for DP HPD event notification 735892b74a6SMeenakshikumar Somasundaram */ 736892b74a6SMeenakshikumar Somasundaram DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 73771af9d46SMeenakshikumar Somasundaram /** 73871af9d46SMeenakshikumar Somasundaram * Command type used for SET_CONFIG Reply notification 73971af9d46SMeenakshikumar Somasundaram */ 74071af9d46SMeenakshikumar Somasundaram DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 7413b37260bSAnthony Koo }; 7423b37260bSAnthony Koo 74376724b76SJimmy Kizito /* DMUB_CMD__DPIA command sub-types. */ 74476724b76SJimmy Kizito enum dmub_cmd_dpia_type { 74576724b76SJimmy Kizito DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 74671af9d46SMeenakshikumar Somasundaram DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 747139a3311SMeenakshikumar Somasundaram DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 74876724b76SJimmy Kizito }; 74976724b76SJimmy Kizito 7507c008829SNicholas Kazlauskas #pragma pack(push, 1) 7517c008829SNicholas Kazlauskas 752592a6318SAnthony Koo /** 753592a6318SAnthony Koo * struct dmub_cmd_header - Common command header fields. 754592a6318SAnthony Koo */ 7557c008829SNicholas Kazlauskas struct dmub_cmd_header { 756592a6318SAnthony Koo unsigned int type : 8; /**< command type */ 757592a6318SAnthony Koo unsigned int sub_type : 8; /**< command sub type */ 758592a6318SAnthony Koo unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 7590b51e7e8SAnthony Koo unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 7600b51e7e8SAnthony Koo unsigned int reserved0 : 6; /**< reserved bits */ 761592a6318SAnthony Koo unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 762592a6318SAnthony Koo unsigned int reserved1 : 2; /**< reserved bits */ 7637c008829SNicholas Kazlauskas }; 7647c008829SNicholas Kazlauskas 7657c008829SNicholas Kazlauskas /* 766592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write 7677c008829SNicholas Kazlauskas * 7687c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 5 sets of read modify writes, 7697c008829SNicholas Kazlauskas * each take 3 dwords. 7707c008829SNicholas Kazlauskas * 7717c008829SNicholas Kazlauskas * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 7727c008829SNicholas Kazlauskas * 7737c008829SNicholas Kazlauskas * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 7747c008829SNicholas Kazlauskas * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 7757c008829SNicholas Kazlauskas */ 7767c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence { 777592a6318SAnthony Koo uint32_t addr; /**< register address */ 778592a6318SAnthony Koo uint32_t modify_mask; /**< modify mask */ 779592a6318SAnthony Koo uint32_t modify_value; /**< modify value */ 7807c008829SNicholas Kazlauskas }; 7817c008829SNicholas Kazlauskas 782592a6318SAnthony Koo /** 783592a6318SAnthony Koo * Maximum number of ops in read modify write sequence. 784592a6318SAnthony Koo */ 7857c008829SNicholas Kazlauskas #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 786592a6318SAnthony Koo 787592a6318SAnthony Koo /** 788592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 789592a6318SAnthony Koo */ 7907c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write { 791592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 792592a6318SAnthony Koo /** 793592a6318SAnthony Koo * Read modify write sequence. 794592a6318SAnthony Koo */ 7957c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 7967c008829SNicholas Kazlauskas }; 7977c008829SNicholas Kazlauskas 7987c008829SNicholas Kazlauskas /* 7997c008829SNicholas Kazlauskas * Update a register with specified masks and values sequeunce 8007c008829SNicholas Kazlauskas * 8017c008829SNicholas Kazlauskas * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 8027c008829SNicholas Kazlauskas * 8037c008829SNicholas Kazlauskas * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 8047c008829SNicholas Kazlauskas * 8057c008829SNicholas Kazlauskas * 8067c008829SNicholas Kazlauskas * USE CASE: 8077c008829SNicholas Kazlauskas * 1. auto-increment register where additional read would update pointer and produce wrong result 8087c008829SNicholas Kazlauskas * 2. toggle a bit without read in the middle 8097c008829SNicholas Kazlauskas */ 8107c008829SNicholas Kazlauskas 8117c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence { 812592a6318SAnthony Koo uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 813592a6318SAnthony Koo uint32_t modify_value; /**< value to update with */ 8147c008829SNicholas Kazlauskas }; 8157c008829SNicholas Kazlauskas 816592a6318SAnthony Koo /** 817592a6318SAnthony Koo * Maximum number of ops in field update sequence. 818592a6318SAnthony Koo */ 8197c008829SNicholas Kazlauskas #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 820592a6318SAnthony Koo 821592a6318SAnthony Koo /** 822592a6318SAnthony Koo * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 823592a6318SAnthony Koo */ 8247c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence { 825592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 826592a6318SAnthony Koo uint32_t addr; /**< register address */ 827592a6318SAnthony Koo /** 828592a6318SAnthony Koo * Field update sequence. 829592a6318SAnthony Koo */ 8307c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 8317c008829SNicholas Kazlauskas }; 8327c008829SNicholas Kazlauskas 833592a6318SAnthony Koo 834592a6318SAnthony Koo /** 835592a6318SAnthony Koo * Maximum number of burst write values. 836592a6318SAnthony Koo */ 837592a6318SAnthony Koo #define DMUB_BURST_WRITE_VALUES__MAX 14 838592a6318SAnthony Koo 8397c008829SNicholas Kazlauskas /* 840592a6318SAnthony Koo * struct dmub_rb_cmd_burst_write - Burst write 8417c008829SNicholas Kazlauskas * 8427c008829SNicholas Kazlauskas * support use case such as writing out LUTs. 8437c008829SNicholas Kazlauskas * 8447c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 14 values to write to given address 8457c008829SNicholas Kazlauskas * 8467c008829SNicholas Kazlauskas * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 8477c008829SNicholas Kazlauskas */ 8487c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write { 849592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 850592a6318SAnthony Koo uint32_t addr; /**< register start address */ 851592a6318SAnthony Koo /** 852592a6318SAnthony Koo * Burst write register values. 853592a6318SAnthony Koo */ 8547c008829SNicholas Kazlauskas uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 8557c008829SNicholas Kazlauskas }; 8567c008829SNicholas Kazlauskas 857592a6318SAnthony Koo /** 858592a6318SAnthony Koo * struct dmub_rb_cmd_common - Common command header 859592a6318SAnthony Koo */ 8607c008829SNicholas Kazlauskas struct dmub_rb_cmd_common { 861592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */ 862592a6318SAnthony Koo /** 863592a6318SAnthony Koo * Padding to RB_CMD_SIZE 864592a6318SAnthony Koo */ 8657c008829SNicholas Kazlauskas uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 8667c008829SNicholas Kazlauskas }; 8677c008829SNicholas Kazlauskas 868592a6318SAnthony Koo /** 869592a6318SAnthony Koo * struct dmub_cmd_reg_wait_data - Register wait data 870592a6318SAnthony Koo */ 8717c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data { 872592a6318SAnthony Koo uint32_t addr; /**< Register address */ 873592a6318SAnthony Koo uint32_t mask; /**< Mask for register bits */ 874592a6318SAnthony Koo uint32_t condition_field_value; /**< Value to wait for */ 875592a6318SAnthony Koo uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 8767c008829SNicholas Kazlauskas }; 8777c008829SNicholas Kazlauskas 878592a6318SAnthony Koo /** 879592a6318SAnthony Koo * struct dmub_rb_cmd_reg_wait - Register wait command 880592a6318SAnthony Koo */ 8817c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait { 882592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 883592a6318SAnthony Koo struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 8847c008829SNicholas Kazlauskas }; 8857c008829SNicholas Kazlauskas 886592a6318SAnthony Koo /** 887592a6318SAnthony Koo * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 888592a6318SAnthony Koo * 889592a6318SAnthony Koo * Reprograms surface parameters to avoid underflow. 890592a6318SAnthony Koo */ 891bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa { 892592a6318SAnthony Koo uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 893592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 894592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 895592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 896592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 89722aa5614SYongqiang Sun struct { 898592a6318SAnthony Koo uint8_t hubp_inst : 4; /**< HUBP instance */ 899592a6318SAnthony Koo uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 900592a6318SAnthony Koo uint8_t immediate :1; /**< Immediate flip */ 901592a6318SAnthony Koo uint8_t vmid : 4; /**< VMID */ 902592a6318SAnthony Koo uint8_t grph_stereo : 1; /**< 1 if stereo */ 903592a6318SAnthony Koo uint32_t reserved : 21; /**< Reserved */ 904592a6318SAnthony Koo } flip_params; /**< Pageflip parameters */ 905592a6318SAnthony Koo uint32_t reserved[9]; /**< Reserved bits */ 9068c019253SYongqiang Sun }; 9078c019253SYongqiang Sun 908592a6318SAnthony Koo /** 909592a6318SAnthony Koo * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 910592a6318SAnthony Koo */ 911bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa { 912592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 913592a6318SAnthony Koo struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 9148c019253SYongqiang Sun }; 9158c019253SYongqiang Sun 916592a6318SAnthony Koo /** 917592a6318SAnthony Koo * struct dmub_rb_cmd_mall - MALL command data. 918592a6318SAnthony Koo */ 91952f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall { 920592a6318SAnthony Koo struct dmub_cmd_header header; /**< Common command header */ 921592a6318SAnthony Koo union dmub_addr cursor_copy_src; /**< Cursor copy address */ 922592a6318SAnthony Koo union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 923592a6318SAnthony Koo uint32_t tmr_delay; /**< Timer delay */ 924592a6318SAnthony Koo uint32_t tmr_scale; /**< Timer scale */ 925592a6318SAnthony Koo uint16_t cursor_width; /**< Cursor width in pixels */ 926592a6318SAnthony Koo uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 927592a6318SAnthony Koo uint16_t cursor_height; /**< Cursor height in pixels */ 928592a6318SAnthony Koo uint8_t cursor_bpp; /**< Cursor bits per pixel */ 929592a6318SAnthony Koo uint8_t debug_bits; /**< Debug bits */ 930ea7154d8SBhawanpreet Lakha 931592a6318SAnthony Koo uint8_t reserved1; /**< Reserved bits */ 932592a6318SAnthony Koo uint8_t reserved2; /**< Reserved bits */ 93352f2e83eSBhawanpreet Lakha }; 93452f2e83eSBhawanpreet Lakha 935b04cb192SNicholas Kazlauskas /** 936ac2e555eSAurabindo Pillai * enum dmub_cmd_cab_type - TODO: 937ac2e555eSAurabindo Pillai */ 938ac2e555eSAurabindo Pillai enum dmub_cmd_cab_type { 939ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 940ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_DCN_REQ = 1, 941ac2e555eSAurabindo Pillai DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 942ac2e555eSAurabindo Pillai }; 943ac2e555eSAurabindo Pillai 944ac2e555eSAurabindo Pillai /** 945ac2e555eSAurabindo Pillai * struct dmub_rb_cmd_cab_for_ss - TODO: 946ac2e555eSAurabindo Pillai */ 947ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss { 948ac2e555eSAurabindo Pillai struct dmub_cmd_header header; 949ac2e555eSAurabindo Pillai uint8_t cab_alloc_ways; /* total number of ways */ 950ac2e555eSAurabindo Pillai uint8_t debug_bits; /* debug bits */ 951ac2e555eSAurabindo Pillai }; 95285f4bc0cSAlvin Lee 95385f4bc0cSAlvin Lee enum mclk_switch_mode { 95485f4bc0cSAlvin Lee NONE = 0, 95585f4bc0cSAlvin Lee FPO = 1, 95685f4bc0cSAlvin Lee SUBVP = 2, 95785f4bc0cSAlvin Lee VBLANK = 3, 95885f4bc0cSAlvin Lee }; 95985f4bc0cSAlvin Lee 96085f4bc0cSAlvin Lee /* Per pipe struct which stores the MCLK switch mode 96185f4bc0cSAlvin Lee * data to be sent to DMUB. 96285f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 96385f4bc0cSAlvin Lee * the type name can be updated 96485f4bc0cSAlvin Lee */ 96585f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 96685f4bc0cSAlvin Lee union { 96785f4bc0cSAlvin Lee struct { 96885f4bc0cSAlvin Lee uint32_t pix_clk_100hz; 96985f4bc0cSAlvin Lee uint16_t main_vblank_start; 97085f4bc0cSAlvin Lee uint16_t main_vblank_end; 97185f4bc0cSAlvin Lee uint16_t mall_region_lines; 97285f4bc0cSAlvin Lee uint16_t prefetch_lines; 97385f4bc0cSAlvin Lee uint16_t prefetch_to_mall_start_lines; 97485f4bc0cSAlvin Lee uint16_t processing_delay_lines; 97585f4bc0cSAlvin Lee uint16_t htotal; // required to calculate line time for multi-display cases 97685f4bc0cSAlvin Lee uint16_t vtotal; 97785f4bc0cSAlvin Lee uint8_t main_pipe_index; 97885f4bc0cSAlvin Lee uint8_t phantom_pipe_index; 979*0acc5b06SAnthony Koo /* Since the microschedule is calculated in terms of OTG lines, 980*0acc5b06SAnthony Koo * include any scaling factors to make sure when we get accurate 981*0acc5b06SAnthony Koo * conversion when programming MALL_START_LINE (which is in terms 982*0acc5b06SAnthony Koo * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 983*0acc5b06SAnthony Koo * is 1/2 (numerator = 1, denominator = 2). 984*0acc5b06SAnthony Koo */ 985*0acc5b06SAnthony Koo uint8_t scale_factor_numerator; 986*0acc5b06SAnthony Koo uint8_t scale_factor_denominator; 98781f776b6SAnthony Koo uint8_t is_drr; 988*0acc5b06SAnthony Koo uint8_t pad[2]; 98985f4bc0cSAlvin Lee } subvp_data; 99085f4bc0cSAlvin Lee 99185f4bc0cSAlvin Lee struct { 99285f4bc0cSAlvin Lee uint32_t pix_clk_100hz; 99385f4bc0cSAlvin Lee uint16_t vblank_start; 99485f4bc0cSAlvin Lee uint16_t vblank_end; 99585f4bc0cSAlvin Lee uint16_t vstartup_start; 99685f4bc0cSAlvin Lee uint16_t vtotal; 99785f4bc0cSAlvin Lee uint16_t htotal; 99885f4bc0cSAlvin Lee uint8_t vblank_pipe_index; 99985f4bc0cSAlvin Lee uint8_t padding[2]; 100085f4bc0cSAlvin Lee struct { 100185f4bc0cSAlvin Lee uint8_t drr_in_use; 100285f4bc0cSAlvin Lee uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 100385f4bc0cSAlvin Lee uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 100485f4bc0cSAlvin Lee uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 100585f4bc0cSAlvin Lee uint8_t use_ramping; // Use ramping or not 100685f4bc0cSAlvin Lee } drr_info; // DRR considered as part of SubVP + VBLANK case 100785f4bc0cSAlvin Lee } vblank_data; 100885f4bc0cSAlvin Lee } pipe_config; 100985f4bc0cSAlvin Lee 1010*0acc5b06SAnthony Koo /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1011*0acc5b06SAnthony Koo * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1012*0acc5b06SAnthony Koo * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1013*0acc5b06SAnthony Koo */ 1014*0acc5b06SAnthony Koo uint8_t mode; // enum mclk_switch_mode 101585f4bc0cSAlvin Lee }; 101685f4bc0cSAlvin Lee 101785f4bc0cSAlvin Lee /** 101885f4bc0cSAlvin Lee * Config data for Sub-VP and FPO 101985f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 102085f4bc0cSAlvin Lee * the type name can be updated 102185f4bc0cSAlvin Lee */ 102285f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 102385f4bc0cSAlvin Lee uint16_t watermark_a_cache; 102485f4bc0cSAlvin Lee uint8_t vertical_int_margin_us; 102585f4bc0cSAlvin Lee uint8_t pstate_allow_width_us; 102685f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 102785f4bc0cSAlvin Lee }; 102885f4bc0cSAlvin Lee 102985f4bc0cSAlvin Lee /** 103085f4bc0cSAlvin Lee * DMUB rb command definition for Sub-VP and FPO 103185f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged 103285f4bc0cSAlvin Lee * the type name can be updated 103385f4bc0cSAlvin Lee */ 103485f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 103585f4bc0cSAlvin Lee struct dmub_cmd_header header; 103685f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 103785f4bc0cSAlvin Lee }; 103885f4bc0cSAlvin Lee 1039ac2e555eSAurabindo Pillai /** 1040b04cb192SNicholas Kazlauskas * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1041b04cb192SNicholas Kazlauskas */ 1042b04cb192SNicholas Kazlauskas enum dmub_cmd_idle_opt_type { 1043b04cb192SNicholas Kazlauskas /** 1044b04cb192SNicholas Kazlauskas * DCN hardware restore. 1045b04cb192SNicholas Kazlauskas */ 1046b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1047f586fea8SJake Wang 1048f586fea8SJake Wang /** 1049f586fea8SJake Wang * DCN hardware save. 1050f586fea8SJake Wang */ 1051f586fea8SJake Wang DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1052b04cb192SNicholas Kazlauskas }; 1053b04cb192SNicholas Kazlauskas 1054b04cb192SNicholas Kazlauskas /** 1055b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1056b04cb192SNicholas Kazlauskas */ 1057b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore { 1058b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1059b04cb192SNicholas Kazlauskas }; 1060b04cb192SNicholas Kazlauskas 1061b04cb192SNicholas Kazlauskas /** 1062b04cb192SNicholas Kazlauskas * struct dmub_clocks - Clock update notification. 1063b04cb192SNicholas Kazlauskas */ 1064b04cb192SNicholas Kazlauskas struct dmub_clocks { 1065b04cb192SNicholas Kazlauskas uint32_t dispclk_khz; /**< dispclk kHz */ 1066b04cb192SNicholas Kazlauskas uint32_t dppclk_khz; /**< dppclk kHz */ 1067b04cb192SNicholas Kazlauskas uint32_t dcfclk_khz; /**< dcfclk kHz */ 1068b04cb192SNicholas Kazlauskas uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1069b04cb192SNicholas Kazlauskas }; 1070b04cb192SNicholas Kazlauskas 1071b04cb192SNicholas Kazlauskas /** 1072b04cb192SNicholas Kazlauskas * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1073b04cb192SNicholas Kazlauskas */ 1074b04cb192SNicholas Kazlauskas enum dmub_cmd_clk_mgr_type { 1075b04cb192SNicholas Kazlauskas /** 1076b04cb192SNicholas Kazlauskas * Notify DMCUB of clock update. 1077b04cb192SNicholas Kazlauskas */ 1078b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1079b04cb192SNicholas Kazlauskas }; 1080b04cb192SNicholas Kazlauskas 1081b04cb192SNicholas Kazlauskas /** 1082b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1083b04cb192SNicholas Kazlauskas */ 1084b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks { 1085b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 1086b04cb192SNicholas Kazlauskas struct dmub_clocks clocks; /**< clock data */ 1087b04cb192SNicholas Kazlauskas }; 10888fe44c08SAlex Deucher 1089592a6318SAnthony Koo /** 1090592a6318SAnthony Koo * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1091592a6318SAnthony Koo */ 10927c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data { 1093592a6318SAnthony Koo union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 10947c008829SNicholas Kazlauskas }; 10957c008829SNicholas Kazlauskas 1096592a6318SAnthony Koo /** 1097592a6318SAnthony Koo * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1098592a6318SAnthony Koo */ 10997c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control { 1100592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1101592a6318SAnthony Koo struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 11027c008829SNicholas Kazlauskas }; 11037c008829SNicholas Kazlauskas 1104592a6318SAnthony Koo /** 1105592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1106592a6318SAnthony Koo */ 11077c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data { 1108592a6318SAnthony Koo struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 11097c008829SNicholas Kazlauskas }; 11107c008829SNicholas Kazlauskas 1111592a6318SAnthony Koo /** 1112592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1113592a6318SAnthony Koo */ 11147c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock { 1115592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1116592a6318SAnthony Koo struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 11177c008829SNicholas Kazlauskas }; 11187c008829SNicholas Kazlauskas 1119592a6318SAnthony Koo /** 1120592a6318SAnthony Koo * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1121592a6318SAnthony Koo */ 11227c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data { 1123592a6318SAnthony Koo struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 11247c008829SNicholas Kazlauskas }; 11257c008829SNicholas Kazlauskas 1126592a6318SAnthony Koo /** 1127592a6318SAnthony Koo * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1128592a6318SAnthony Koo */ 11297c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating { 1130592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1131592a6318SAnthony Koo struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 11327c008829SNicholas Kazlauskas }; 11337c008829SNicholas Kazlauskas 1134592a6318SAnthony Koo /** 1135592a6318SAnthony Koo * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1136592a6318SAnthony Koo */ 1137d448521eSAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 { 1138d448521eSAnthony Koo uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1139d448521eSAnthony Koo uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1140d448521eSAnthony Koo union { 1141d448521eSAnthony Koo uint8_t digmode; /**< enum atom_encode_mode_def */ 1142d448521eSAnthony Koo uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1143d448521eSAnthony Koo } mode_laneset; 1144d448521eSAnthony Koo uint8_t lanenum; /**< Number of lanes */ 1145d448521eSAnthony Koo union { 1146d448521eSAnthony Koo uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1147d448521eSAnthony Koo } symclk_units; 1148d448521eSAnthony Koo uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1149d448521eSAnthony Koo uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1150d448521eSAnthony Koo uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 11515a2730fcSFangzhi Zuo uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1152d448521eSAnthony Koo uint8_t reserved1; /**< For future use */ 1153d448521eSAnthony Koo uint8_t reserved2[3]; /**< For future use */ 1154d448521eSAnthony Koo uint32_t reserved3[11]; /**< For future use */ 1155d448521eSAnthony Koo }; 1156d448521eSAnthony Koo 1157592a6318SAnthony Koo /** 1158592a6318SAnthony Koo * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1159592a6318SAnthony Koo */ 1160d448521eSAnthony Koo union dmub_cmd_dig1_transmitter_control_data { 1161592a6318SAnthony Koo struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1162592a6318SAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 11637c008829SNicholas Kazlauskas }; 11647c008829SNicholas Kazlauskas 1165592a6318SAnthony Koo /** 1166592a6318SAnthony Koo * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1167592a6318SAnthony Koo */ 11687c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control { 1169592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1170592a6318SAnthony Koo union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 11717c008829SNicholas Kazlauskas }; 11727c008829SNicholas Kazlauskas 1173592a6318SAnthony Koo /** 117476724b76SJimmy Kizito * DPIA tunnel command parameters. 117576724b76SJimmy Kizito */ 117676724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data { 117776724b76SJimmy Kizito uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 117876724b76SJimmy Kizito uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 117976724b76SJimmy Kizito union { 118076724b76SJimmy Kizito uint8_t digmode; /** enum atom_encode_mode_def */ 118176724b76SJimmy Kizito uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 118276724b76SJimmy Kizito } mode_laneset; 118376724b76SJimmy Kizito uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 118476724b76SJimmy Kizito uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 118576724b76SJimmy Kizito uint8_t hpdsel; /** =0: HPD is not assigned */ 118676724b76SJimmy Kizito uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 118776724b76SJimmy Kizito uint8_t dpia_id; /** Index of DPIA */ 118876724b76SJimmy Kizito uint8_t fec_rdy : 1; 118976724b76SJimmy Kizito uint8_t reserved : 7; 119076724b76SJimmy Kizito uint32_t reserved1; 119176724b76SJimmy Kizito }; 119276724b76SJimmy Kizito 119376724b76SJimmy Kizito /** 119476724b76SJimmy Kizito * DMUB command for DPIA tunnel control. 119576724b76SJimmy Kizito */ 119676724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control { 119776724b76SJimmy Kizito struct dmub_cmd_header header; 119876724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data dpia_control; 119976724b76SJimmy Kizito }; 120076724b76SJimmy Kizito 120176724b76SJimmy Kizito /** 120271af9d46SMeenakshikumar Somasundaram * SET_CONFIG Command Payload 120371af9d46SMeenakshikumar Somasundaram */ 120471af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload { 120571af9d46SMeenakshikumar Somasundaram uint8_t msg_type; /* set config message type */ 120671af9d46SMeenakshikumar Somasundaram uint8_t msg_data; /* set config message data */ 120771af9d46SMeenakshikumar Somasundaram }; 120871af9d46SMeenakshikumar Somasundaram 120971af9d46SMeenakshikumar Somasundaram /** 121071af9d46SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 121171af9d46SMeenakshikumar Somasundaram */ 121271af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data { 121371af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload cmd_pkt; 121471af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */ 121571af9d46SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned in case of error */ 121671af9d46SMeenakshikumar Somasundaram }; 121771af9d46SMeenakshikumar Somasundaram 121871af9d46SMeenakshikumar Somasundaram /** 121971af9d46SMeenakshikumar Somasundaram * DMUB command structure for SET_CONFIG command. 122071af9d46SMeenakshikumar Somasundaram */ 122171af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access { 122271af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 122371af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 122471af9d46SMeenakshikumar Somasundaram }; 122571af9d46SMeenakshikumar Somasundaram 122671af9d46SMeenakshikumar Somasundaram /** 1227139a3311SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1228139a3311SMeenakshikumar Somasundaram */ 1229139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data { 1230139a3311SMeenakshikumar Somasundaram uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1231139a3311SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */ 1232139a3311SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1233139a3311SMeenakshikumar Somasundaram uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1234139a3311SMeenakshikumar Somasundaram }; 1235139a3311SMeenakshikumar Somasundaram 1236139a3311SMeenakshikumar Somasundaram /** 1237139a3311SMeenakshikumar Somasundaram * DMUB command structure for SET_ command. 1238139a3311SMeenakshikumar Somasundaram */ 1239139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots { 1240139a3311SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */ 1241139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1242139a3311SMeenakshikumar Somasundaram }; 1243139a3311SMeenakshikumar Somasundaram 1244139a3311SMeenakshikumar Somasundaram /** 1245592a6318SAnthony Koo * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1246592a6318SAnthony Koo */ 12477c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init { 1248592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */ 1249592a6318SAnthony Koo uint8_t reserved[60]; /**< reserved bits */ 12507c008829SNicholas Kazlauskas }; 12517c008829SNicholas Kazlauskas 12521a595f28SAnthony Koo /** 12531a595f28SAnthony Koo * enum dp_aux_request_action - DP AUX request command listing. 12541a595f28SAnthony Koo * 12551a595f28SAnthony Koo * 4 AUX request command bits are shifted to high nibble. 12561a595f28SAnthony Koo */ 1257d9beecfcSAnthony Koo enum dp_aux_request_action { 12581a595f28SAnthony Koo /** I2C-over-AUX write request */ 1259d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 12601a595f28SAnthony Koo /** I2C-over-AUX read request */ 1261d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ = 0x10, 12621a595f28SAnthony Koo /** I2C-over-AUX write status request */ 1263d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 12641a595f28SAnthony Koo /** I2C-over-AUX write request with MOT=1 */ 1265d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 12661a595f28SAnthony Koo /** I2C-over-AUX read request with MOT=1 */ 1267d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 12681a595f28SAnthony Koo /** I2C-over-AUX write status request with MOT=1 */ 1269d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 12701a595f28SAnthony Koo /** Native AUX write request */ 1271d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 12721a595f28SAnthony Koo /** Native AUX read request */ 1273d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1274d9beecfcSAnthony Koo }; 1275d9beecfcSAnthony Koo 12761a595f28SAnthony Koo /** 12771a595f28SAnthony Koo * enum aux_return_code_type - DP AUX process return code listing. 12781a595f28SAnthony Koo */ 1279fd0f1d21SAnthony Koo enum aux_return_code_type { 12801a595f28SAnthony Koo /** AUX process succeeded */ 1281fd0f1d21SAnthony Koo AUX_RET_SUCCESS = 0, 12821a595f28SAnthony Koo /** AUX process failed with unknown reason */ 1283b6402afeSAnthony Koo AUX_RET_ERROR_UNKNOWN, 12841a595f28SAnthony Koo /** AUX process completed with invalid reply */ 1285b6402afeSAnthony Koo AUX_RET_ERROR_INVALID_REPLY, 12861a595f28SAnthony Koo /** AUX process timed out */ 1287fd0f1d21SAnthony Koo AUX_RET_ERROR_TIMEOUT, 12881a595f28SAnthony Koo /** HPD was low during AUX process */ 1289b6402afeSAnthony Koo AUX_RET_ERROR_HPD_DISCON, 12901a595f28SAnthony Koo /** Failed to acquire AUX engine */ 1291b6402afeSAnthony Koo AUX_RET_ERROR_ENGINE_ACQUIRE, 12921a595f28SAnthony Koo /** AUX request not supported */ 1293fd0f1d21SAnthony Koo AUX_RET_ERROR_INVALID_OPERATION, 12941a595f28SAnthony Koo /** AUX process not available */ 1295fd0f1d21SAnthony Koo AUX_RET_ERROR_PROTOCOL_ERROR, 1296fd0f1d21SAnthony Koo }; 1297fd0f1d21SAnthony Koo 12981a595f28SAnthony Koo /** 12991a595f28SAnthony Koo * enum aux_channel_type - DP AUX channel type listing. 13001a595f28SAnthony Koo */ 1301b6402afeSAnthony Koo enum aux_channel_type { 13021a595f28SAnthony Koo /** AUX thru Legacy DP AUX */ 1303b6402afeSAnthony Koo AUX_CHANNEL_LEGACY_DDC, 13041a595f28SAnthony Koo /** AUX thru DPIA DP tunneling */ 1305b6402afeSAnthony Koo AUX_CHANNEL_DPIA 1306b6402afeSAnthony Koo }; 1307b6402afeSAnthony Koo 13081a595f28SAnthony Koo /** 13091a595f28SAnthony Koo * struct aux_transaction_parameters - DP AUX request transaction data 13101a595f28SAnthony Koo */ 1311d9beecfcSAnthony Koo struct aux_transaction_parameters { 13121a595f28SAnthony Koo uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 13131a595f28SAnthony Koo uint8_t action; /**< enum dp_aux_request_action */ 13141a595f28SAnthony Koo uint8_t length; /**< DP AUX request data length */ 13151a595f28SAnthony Koo uint8_t reserved; /**< For future use */ 13161a595f28SAnthony Koo uint32_t address; /**< DP AUX address */ 13171a595f28SAnthony Koo uint8_t data[16]; /**< DP AUX write data */ 1318d9beecfcSAnthony Koo }; 1319d9beecfcSAnthony Koo 13201a595f28SAnthony Koo /** 13211a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 13221a595f28SAnthony Koo */ 1323d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data { 13241a595f28SAnthony Koo uint8_t instance; /**< AUX instance or DPIA instance */ 13251a595f28SAnthony Koo uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 13261a595f28SAnthony Koo uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 13271a595f28SAnthony Koo uint8_t reserved0; /**< For future use */ 13281a595f28SAnthony Koo uint16_t timeout; /**< timeout time in us */ 13291a595f28SAnthony Koo uint16_t reserved1; /**< For future use */ 13301a595f28SAnthony Koo enum aux_channel_type type; /**< enum aux_channel_type */ 13311a595f28SAnthony Koo struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1332d9beecfcSAnthony Koo }; 1333d9beecfcSAnthony Koo 13341a595f28SAnthony Koo /** 13351a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 13361a595f28SAnthony Koo */ 1337d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access { 13381a595f28SAnthony Koo /** 13391a595f28SAnthony Koo * Command header. 13401a595f28SAnthony Koo */ 1341d9beecfcSAnthony Koo struct dmub_cmd_header header; 13421a595f28SAnthony Koo /** 13431a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 13441a595f28SAnthony Koo */ 1345d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data aux_control; 1346d9beecfcSAnthony Koo }; 1347d9beecfcSAnthony Koo 13481a595f28SAnthony Koo /** 13491a595f28SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 13501a595f28SAnthony Koo */ 1351d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable { 13521a595f28SAnthony Koo /** 13531a595f28SAnthony Koo * Command header. 13541a595f28SAnthony Koo */ 1355d9beecfcSAnthony Koo struct dmub_cmd_header header; 13561a595f28SAnthony Koo /** 13571a595f28SAnthony Koo * enable: 0x0 -> disable outbox1 notification (default value) 13581a595f28SAnthony Koo * 0x1 -> enable outbox1 notification 13591a595f28SAnthony Koo */ 1360d9beecfcSAnthony Koo uint32_t enable; 1361d9beecfcSAnthony Koo }; 1362d9beecfcSAnthony Koo 1363d9beecfcSAnthony Koo /* DP AUX Reply command - OutBox Cmd */ 13641a595f28SAnthony Koo /** 13651a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 13661a595f28SAnthony Koo */ 1367d9beecfcSAnthony Koo struct aux_reply_data { 13681a595f28SAnthony Koo /** 13691a595f28SAnthony Koo * Aux cmd 13701a595f28SAnthony Koo */ 1371d9beecfcSAnthony Koo uint8_t command; 13721a595f28SAnthony Koo /** 13731a595f28SAnthony Koo * Aux reply data length (max: 16 bytes) 13741a595f28SAnthony Koo */ 1375d9beecfcSAnthony Koo uint8_t length; 13761a595f28SAnthony Koo /** 13771a595f28SAnthony Koo * Alignment only 13781a595f28SAnthony Koo */ 1379d9beecfcSAnthony Koo uint8_t pad[2]; 13801a595f28SAnthony Koo /** 13811a595f28SAnthony Koo * Aux reply data 13821a595f28SAnthony Koo */ 1383d9beecfcSAnthony Koo uint8_t data[16]; 1384d9beecfcSAnthony Koo }; 1385d9beecfcSAnthony Koo 13861a595f28SAnthony Koo /** 13871a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 13881a595f28SAnthony Koo */ 1389d9beecfcSAnthony Koo struct aux_reply_control_data { 13901a595f28SAnthony Koo /** 13911a595f28SAnthony Koo * Reserved for future use 13921a595f28SAnthony Koo */ 1393d9beecfcSAnthony Koo uint32_t handle; 13941a595f28SAnthony Koo /** 13951a595f28SAnthony Koo * Aux Instance 13961a595f28SAnthony Koo */ 1397b6402afeSAnthony Koo uint8_t instance; 13981a595f28SAnthony Koo /** 13991a595f28SAnthony Koo * Aux transaction result: definition in enum aux_return_code_type 14001a595f28SAnthony Koo */ 1401d9beecfcSAnthony Koo uint8_t result; 14021a595f28SAnthony Koo /** 14031a595f28SAnthony Koo * Alignment only 14041a595f28SAnthony Koo */ 1405d9beecfcSAnthony Koo uint16_t pad; 1406d9beecfcSAnthony Koo }; 1407d9beecfcSAnthony Koo 14081a595f28SAnthony Koo /** 14091a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 14101a595f28SAnthony Koo */ 1411d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply { 14121a595f28SAnthony Koo /** 14131a595f28SAnthony Koo * Command header. 14141a595f28SAnthony Koo */ 1415d9beecfcSAnthony Koo struct dmub_cmd_header header; 14161a595f28SAnthony Koo /** 14171a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14181a595f28SAnthony Koo */ 1419d9beecfcSAnthony Koo struct aux_reply_control_data control; 14201a595f28SAnthony Koo /** 14211a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 14221a595f28SAnthony Koo */ 1423d9beecfcSAnthony Koo struct aux_reply_data reply_data; 1424d9beecfcSAnthony Koo }; 1425d9beecfcSAnthony Koo 1426fd0f1d21SAnthony Koo /* DP HPD Notify command - OutBox Cmd */ 14271a595f28SAnthony Koo /** 14281a595f28SAnthony Koo * DP HPD Type 14291a595f28SAnthony Koo */ 1430fd0f1d21SAnthony Koo enum dp_hpd_type { 14311a595f28SAnthony Koo /** 14321a595f28SAnthony Koo * Normal DP HPD 14331a595f28SAnthony Koo */ 1434fd0f1d21SAnthony Koo DP_HPD = 0, 14351a595f28SAnthony Koo /** 14361a595f28SAnthony Koo * DP HPD short pulse 14371a595f28SAnthony Koo */ 1438fd0f1d21SAnthony Koo DP_IRQ 1439fd0f1d21SAnthony Koo }; 1440fd0f1d21SAnthony Koo 14411a595f28SAnthony Koo /** 14421a595f28SAnthony Koo * DP HPD Status 14431a595f28SAnthony Koo */ 1444fd0f1d21SAnthony Koo enum dp_hpd_status { 14451a595f28SAnthony Koo /** 14461a595f28SAnthony Koo * DP_HPD status low 14471a595f28SAnthony Koo */ 1448fd0f1d21SAnthony Koo DP_HPD_UNPLUG = 0, 14491a595f28SAnthony Koo /** 14501a595f28SAnthony Koo * DP_HPD status high 14511a595f28SAnthony Koo */ 1452fd0f1d21SAnthony Koo DP_HPD_PLUG 1453fd0f1d21SAnthony Koo }; 1454fd0f1d21SAnthony Koo 14551a595f28SAnthony Koo /** 14561a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 14571a595f28SAnthony Koo */ 1458d9beecfcSAnthony Koo struct dp_hpd_data { 14591a595f28SAnthony Koo /** 14601a595f28SAnthony Koo * DP HPD instance 14611a595f28SAnthony Koo */ 1462b6402afeSAnthony Koo uint8_t instance; 14631a595f28SAnthony Koo /** 14641a595f28SAnthony Koo * HPD type 14651a595f28SAnthony Koo */ 1466d9beecfcSAnthony Koo uint8_t hpd_type; 14671a595f28SAnthony Koo /** 14681a595f28SAnthony Koo * HPD status: only for type: DP_HPD to indicate status 14691a595f28SAnthony Koo */ 1470d9beecfcSAnthony Koo uint8_t hpd_status; 14711a595f28SAnthony Koo /** 14721a595f28SAnthony Koo * Alignment only 14731a595f28SAnthony Koo */ 1474d9beecfcSAnthony Koo uint8_t pad; 1475d9beecfcSAnthony Koo }; 1476d9beecfcSAnthony Koo 14771a595f28SAnthony Koo /** 14781a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 14791a595f28SAnthony Koo */ 1480d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify { 14811a595f28SAnthony Koo /** 14821a595f28SAnthony Koo * Command header. 14831a595f28SAnthony Koo */ 1484d9beecfcSAnthony Koo struct dmub_cmd_header header; 14851a595f28SAnthony Koo /** 14861a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 14871a595f28SAnthony Koo */ 1488d9beecfcSAnthony Koo struct dp_hpd_data hpd_data; 1489d9beecfcSAnthony Koo }; 1490d9beecfcSAnthony Koo 149171af9d46SMeenakshikumar Somasundaram /** 149271af9d46SMeenakshikumar Somasundaram * Definition of a SET_CONFIG reply from DPOA. 149371af9d46SMeenakshikumar Somasundaram */ 149471af9d46SMeenakshikumar Somasundaram enum set_config_status { 149571af9d46SMeenakshikumar Somasundaram SET_CONFIG_PENDING = 0, 149671af9d46SMeenakshikumar Somasundaram SET_CONFIG_ACK_RECEIVED, 149771af9d46SMeenakshikumar Somasundaram SET_CONFIG_RX_TIMEOUT, 149871af9d46SMeenakshikumar Somasundaram SET_CONFIG_UNKNOWN_ERROR, 149971af9d46SMeenakshikumar Somasundaram }; 150071af9d46SMeenakshikumar Somasundaram 150171af9d46SMeenakshikumar Somasundaram /** 150271af9d46SMeenakshikumar Somasundaram * Definition of a set_config reply 150371af9d46SMeenakshikumar Somasundaram */ 150471af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data { 150571af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA Instance */ 150671af9d46SMeenakshikumar Somasundaram uint8_t status; /* Set Config reply */ 150771af9d46SMeenakshikumar Somasundaram uint16_t pad; /* Alignment */ 150871af9d46SMeenakshikumar Somasundaram }; 150971af9d46SMeenakshikumar Somasundaram 151071af9d46SMeenakshikumar Somasundaram /** 151171af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 151271af9d46SMeenakshikumar Somasundaram */ 151371af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply { 151471af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; 151571af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data set_config_reply_control; 151671af9d46SMeenakshikumar Somasundaram }; 151771af9d46SMeenakshikumar Somasundaram 1518ea5a4db9SAnthony Koo /** 1519ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1520ea5a4db9SAnthony Koo */ 1521ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data { 1522ea5a4db9SAnthony Koo uint8_t instance; /**< HPD instance or DPIA instance */ 1523ea5a4db9SAnthony Koo uint8_t result; /**< For returning HPD state */ 1524874714feSAnthony Koo uint16_t pad; /** < Alignment */ 1525ea5a4db9SAnthony Koo enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1526ea5a4db9SAnthony Koo enum aux_return_code_type status; /**< for returning the status of command */ 1527ea5a4db9SAnthony Koo }; 1528ea5a4db9SAnthony Koo 1529ea5a4db9SAnthony Koo /** 1530ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1531ea5a4db9SAnthony Koo */ 1532ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state { 1533ea5a4db9SAnthony Koo /** 1534ea5a4db9SAnthony Koo * Command header. 1535ea5a4db9SAnthony Koo */ 1536ea5a4db9SAnthony Koo struct dmub_cmd_header header; 1537ea5a4db9SAnthony Koo /** 1538ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1539ea5a4db9SAnthony Koo */ 1540ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data data; 1541ea5a4db9SAnthony Koo }; 1542ea5a4db9SAnthony Koo 154384034ad4SAnthony Koo /* 154484034ad4SAnthony Koo * Command IDs should be treated as stable ABI. 154584034ad4SAnthony Koo * Do not reuse or modify IDs. 154684034ad4SAnthony Koo */ 154784034ad4SAnthony Koo 15481a595f28SAnthony Koo /** 15491a595f28SAnthony Koo * PSR command sub-types. 15501a595f28SAnthony Koo */ 155184034ad4SAnthony Koo enum dmub_cmd_psr_type { 15521a595f28SAnthony Koo /** 15531a595f28SAnthony Koo * Set PSR version support. 15541a595f28SAnthony Koo */ 155584034ad4SAnthony Koo DMUB_CMD__PSR_SET_VERSION = 0, 15561a595f28SAnthony Koo /** 15571a595f28SAnthony Koo * Copy driver-calculated parameters to PSR state. 15581a595f28SAnthony Koo */ 155984034ad4SAnthony Koo DMUB_CMD__PSR_COPY_SETTINGS = 1, 15601a595f28SAnthony Koo /** 15611a595f28SAnthony Koo * Enable PSR. 15621a595f28SAnthony Koo */ 156384034ad4SAnthony Koo DMUB_CMD__PSR_ENABLE = 2, 15641a595f28SAnthony Koo 15651a595f28SAnthony Koo /** 15661a595f28SAnthony Koo * Disable PSR. 15671a595f28SAnthony Koo */ 156884034ad4SAnthony Koo DMUB_CMD__PSR_DISABLE = 3, 15691a595f28SAnthony Koo 15701a595f28SAnthony Koo /** 15711a595f28SAnthony Koo * Set PSR level. 15721a595f28SAnthony Koo * PSR level is a 16-bit value dicated by driver that 15731a595f28SAnthony Koo * will enable/disable different functionality. 15741a595f28SAnthony Koo */ 157584034ad4SAnthony Koo DMUB_CMD__PSR_SET_LEVEL = 4, 15761a595f28SAnthony Koo 15771a595f28SAnthony Koo /** 15781a595f28SAnthony Koo * Forces PSR enabled until an explicit PSR disable call. 15791a595f28SAnthony Koo */ 1580672251b2SAnthony Koo DMUB_CMD__PSR_FORCE_STATIC = 5, 1581e5dfcd27SRobin Chen /** 158283eb5385SDavid Zhang * Set vtotal in psr active for FreeSync PSR. 158383eb5385SDavid Zhang */ 158483eb5385SDavid Zhang DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 158583eb5385SDavid Zhang /** 1586e5dfcd27SRobin Chen * Set PSR power option 1587e5dfcd27SRobin Chen */ 1588e5dfcd27SRobin Chen DMUB_CMD__SET_PSR_POWER_OPT = 7, 158984034ad4SAnthony Koo }; 159084034ad4SAnthony Koo 159185f4bc0cSAlvin Lee enum dmub_cmd_fams_type { 159285f4bc0cSAlvin Lee DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 159385f4bc0cSAlvin Lee DMUB_CMD__FAMS_DRR_UPDATE = 1, 159485f4bc0cSAlvin Lee DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 159581f776b6SAnthony Koo /** 159681f776b6SAnthony Koo * For SubVP set manual trigger in FW because it 159781f776b6SAnthony Koo * triggers DRR_UPDATE_PENDING which SubVP relies 159881f776b6SAnthony Koo * on (for any SubVP cases that use a DRR display) 159981f776b6SAnthony Koo */ 160081f776b6SAnthony Koo DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 160185f4bc0cSAlvin Lee }; 160285f4bc0cSAlvin Lee 16031a595f28SAnthony Koo /** 16041a595f28SAnthony Koo * PSR versions. 16051a595f28SAnthony Koo */ 160684034ad4SAnthony Koo enum psr_version { 16071a595f28SAnthony Koo /** 16081a595f28SAnthony Koo * PSR version 1. 16091a595f28SAnthony Koo */ 161084034ad4SAnthony Koo PSR_VERSION_1 = 0, 16111a595f28SAnthony Koo /** 161283eb5385SDavid Zhang * Freesync PSR SU. 161383eb5385SDavid Zhang */ 161483eb5385SDavid Zhang PSR_VERSION_SU_1 = 1, 161583eb5385SDavid Zhang /** 16161a595f28SAnthony Koo * PSR not supported. 16171a595f28SAnthony Koo */ 161884034ad4SAnthony Koo PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 161984034ad4SAnthony Koo }; 162084034ad4SAnthony Koo 1621592a6318SAnthony Koo /** 1622592a6318SAnthony Koo * enum dmub_cmd_mall_type - MALL commands 1623592a6318SAnthony Koo */ 162452f2e83eSBhawanpreet Lakha enum dmub_cmd_mall_type { 1625592a6318SAnthony Koo /** 1626592a6318SAnthony Koo * Allows display refresh from MALL. 1627592a6318SAnthony Koo */ 162852f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_ALLOW = 0, 1629592a6318SAnthony Koo /** 1630592a6318SAnthony Koo * Disallows display refresh from MALL. 1631592a6318SAnthony Koo */ 163252f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1633592a6318SAnthony Koo /** 1634592a6318SAnthony Koo * Cursor copy for MALL. 1635592a6318SAnthony Koo */ 163652f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1637592a6318SAnthony Koo /** 1638592a6318SAnthony Koo * Controls DF requests. 1639592a6318SAnthony Koo */ 1640ea7154d8SBhawanpreet Lakha DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 164152f2e83eSBhawanpreet Lakha }; 164252f2e83eSBhawanpreet Lakha 1643a91b402dSCharlene Liu /** 164478174f47SAnthony Koo * PHY Link rate for DP. 164578174f47SAnthony Koo */ 164678174f47SAnthony Koo enum phy_link_rate { 164778174f47SAnthony Koo /** 164878174f47SAnthony Koo * not supported. 164978174f47SAnthony Koo */ 165078174f47SAnthony Koo PHY_RATE_UNKNOWN = 0, 165178174f47SAnthony Koo /** 165278174f47SAnthony Koo * Rate_1 (RBR) - 1.62 Gbps/Lane 165378174f47SAnthony Koo */ 165478174f47SAnthony Koo PHY_RATE_162 = 1, 165578174f47SAnthony Koo /** 165678174f47SAnthony Koo * Rate_2 - 2.16 Gbps/Lane 165778174f47SAnthony Koo */ 165878174f47SAnthony Koo PHY_RATE_216 = 2, 165978174f47SAnthony Koo /** 166078174f47SAnthony Koo * Rate_3 - 2.43 Gbps/Lane 166178174f47SAnthony Koo */ 166278174f47SAnthony Koo PHY_RATE_243 = 3, 166378174f47SAnthony Koo /** 166478174f47SAnthony Koo * Rate_4 (HBR) - 2.70 Gbps/Lane 166578174f47SAnthony Koo */ 166678174f47SAnthony Koo PHY_RATE_270 = 4, 166778174f47SAnthony Koo /** 166878174f47SAnthony Koo * Rate_5 (RBR2)- 3.24 Gbps/Lane 166978174f47SAnthony Koo */ 167078174f47SAnthony Koo PHY_RATE_324 = 5, 167178174f47SAnthony Koo /** 167278174f47SAnthony Koo * Rate_6 - 4.32 Gbps/Lane 167378174f47SAnthony Koo */ 167478174f47SAnthony Koo PHY_RATE_432 = 6, 167578174f47SAnthony Koo /** 167678174f47SAnthony Koo * Rate_7 (HBR2)- 5.40 Gbps/Lane 167778174f47SAnthony Koo */ 167878174f47SAnthony Koo PHY_RATE_540 = 7, 167978174f47SAnthony Koo /** 168078174f47SAnthony Koo * Rate_8 (HBR3)- 8.10 Gbps/Lane 168178174f47SAnthony Koo */ 168278174f47SAnthony Koo PHY_RATE_810 = 8, 168378174f47SAnthony Koo /** 168478174f47SAnthony Koo * UHBR10 - 10.0 Gbps/Lane 168578174f47SAnthony Koo */ 168678174f47SAnthony Koo PHY_RATE_1000 = 9, 168778174f47SAnthony Koo /** 168878174f47SAnthony Koo * UHBR13.5 - 13.5 Gbps/Lane 168978174f47SAnthony Koo */ 169078174f47SAnthony Koo PHY_RATE_1350 = 10, 169178174f47SAnthony Koo /** 169278174f47SAnthony Koo * UHBR10 - 20.0 Gbps/Lane 169378174f47SAnthony Koo */ 169478174f47SAnthony Koo PHY_RATE_2000 = 11, 169578174f47SAnthony Koo }; 169678174f47SAnthony Koo 169778174f47SAnthony Koo /** 169878174f47SAnthony Koo * enum dmub_phy_fsm_state - PHY FSM states. 169978174f47SAnthony Koo * PHY FSM state to transit to during PSR enable/disable. 170078174f47SAnthony Koo */ 170178174f47SAnthony Koo enum dmub_phy_fsm_state { 170278174f47SAnthony Koo DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 170378174f47SAnthony Koo DMUB_PHY_FSM_RESET, 170478174f47SAnthony Koo DMUB_PHY_FSM_RESET_RELEASED, 170578174f47SAnthony Koo DMUB_PHY_FSM_SRAM_LOAD_DONE, 170678174f47SAnthony Koo DMUB_PHY_FSM_INITIALIZED, 170778174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED, 170878174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_LP, 170978174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_PG, 171078174f47SAnthony Koo DMUB_PHY_FSM_POWER_DOWN, 171178174f47SAnthony Koo DMUB_PHY_FSM_PLL_EN, 171278174f47SAnthony Koo DMUB_PHY_FSM_TX_EN, 171378174f47SAnthony Koo DMUB_PHY_FSM_FAST_LP, 171478174f47SAnthony Koo }; 171578174f47SAnthony Koo 171678174f47SAnthony Koo /** 17171a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 17181a595f28SAnthony Koo */ 17197c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data { 17201a595f28SAnthony Koo /** 17211a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour. 17221a595f28SAnthony Koo */ 17237b8a6362SAnthony Koo union dmub_psr_debug_flags debug; 17241a595f28SAnthony Koo /** 17251a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 17261a595f28SAnthony Koo */ 17274c1a1335SWyatt Wood uint16_t psr_level; 17281a595f28SAnthony Koo /** 17291a595f28SAnthony Koo * DPP HW instance. 17301a595f28SAnthony Koo */ 17314c1a1335SWyatt Wood uint8_t dpp_inst; 17321a595f28SAnthony Koo /** 17331a595f28SAnthony Koo * MPCC HW instance. 17341a595f28SAnthony Koo * Not used in dmub fw, 173534ba432cSAnthony Koo * dmub fw will get active opp by reading odm registers. 173634ba432cSAnthony Koo */ 17374c1a1335SWyatt Wood uint8_t mpcc_inst; 17381a595f28SAnthony Koo /** 17391a595f28SAnthony Koo * OPP HW instance. 17401a595f28SAnthony Koo * Not used in dmub fw, 17411a595f28SAnthony Koo * dmub fw will get active opp by reading odm registers. 17421a595f28SAnthony Koo */ 17434c1a1335SWyatt Wood uint8_t opp_inst; 17441a595f28SAnthony Koo /** 17451a595f28SAnthony Koo * OTG HW instance. 17461a595f28SAnthony Koo */ 17474c1a1335SWyatt Wood uint8_t otg_inst; 17481a595f28SAnthony Koo /** 17491a595f28SAnthony Koo * DIG FE HW instance. 17501a595f28SAnthony Koo */ 17514c1a1335SWyatt Wood uint8_t digfe_inst; 17521a595f28SAnthony Koo /** 17531a595f28SAnthony Koo * DIG BE HW instance. 17541a595f28SAnthony Koo */ 17554c1a1335SWyatt Wood uint8_t digbe_inst; 17561a595f28SAnthony Koo /** 17571a595f28SAnthony Koo * DP PHY HW instance. 17581a595f28SAnthony Koo */ 17594c1a1335SWyatt Wood uint8_t dpphy_inst; 17601a595f28SAnthony Koo /** 17611a595f28SAnthony Koo * AUX HW instance. 17621a595f28SAnthony Koo */ 17634c1a1335SWyatt Wood uint8_t aux_inst; 17641a595f28SAnthony Koo /** 17651a595f28SAnthony Koo * Determines if SMU optimzations are enabled/disabled. 17661a595f28SAnthony Koo */ 17674c1a1335SWyatt Wood uint8_t smu_optimizations_en; 17681a595f28SAnthony Koo /** 17691a595f28SAnthony Koo * Unused. 17701a595f28SAnthony Koo * TODO: Remove. 17711a595f28SAnthony Koo */ 17724c1a1335SWyatt Wood uint8_t frame_delay; 17731a595f28SAnthony Koo /** 17741a595f28SAnthony Koo * If RFB setup time is greater than the total VBLANK time, 17751a595f28SAnthony Koo * it is not possible for the sink to capture the video frame 17761a595f28SAnthony Koo * in the same frame the SDP is sent. In this case, 17771a595f28SAnthony Koo * the frame capture indication bit should be set and an extra 17781a595f28SAnthony Koo * static frame should be transmitted to the sink. 17791a595f28SAnthony Koo */ 17804c1a1335SWyatt Wood uint8_t frame_cap_ind; 17811a595f28SAnthony Koo /** 178283eb5385SDavid Zhang * Granularity of Y offset supported by sink. 17831a595f28SAnthony Koo */ 178483eb5385SDavid Zhang uint8_t su_y_granularity; 178583eb5385SDavid Zhang /** 178683eb5385SDavid Zhang * Indicates whether sink should start capturing 178783eb5385SDavid Zhang * immediately following active scan line, 178883eb5385SDavid Zhang * or starting with the 2nd active scan line. 178983eb5385SDavid Zhang */ 179083eb5385SDavid Zhang uint8_t line_capture_indication; 17911a595f28SAnthony Koo /** 17921a595f28SAnthony Koo * Multi-display optimizations are implemented on certain ASICs. 17931a595f28SAnthony Koo */ 1794175f0971SYongqiang Sun uint8_t multi_disp_optimizations_en; 17951a595f28SAnthony Koo /** 17961a595f28SAnthony Koo * The last possible line SDP may be transmitted without violating 17971a595f28SAnthony Koo * the RFB setup time or entering the active video frame. 17981a595f28SAnthony Koo */ 179978ead771SAnthony Koo uint16_t init_sdp_deadline; 18001a595f28SAnthony Koo /** 180183eb5385SDavid Zhang * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 18021a595f28SAnthony Koo */ 180383eb5385SDavid Zhang uint8_t rate_control_caps ; 180483eb5385SDavid Zhang /* 180583eb5385SDavid Zhang * Force PSRSU always doing full frame update 180683eb5385SDavid Zhang */ 180783eb5385SDavid Zhang uint8_t force_ffu_mode; 18081a595f28SAnthony Koo /** 18091a595f28SAnthony Koo * Length of each horizontal line in us. 18101a595f28SAnthony Koo */ 18119b56f6bcSAnthony Koo uint32_t line_time_in_us; 1812ecc11601SAnthony Koo /** 1813ecc11601SAnthony Koo * FEC enable status in driver 1814ecc11601SAnthony Koo */ 1815ecc11601SAnthony Koo uint8_t fec_enable_status; 1816ecc11601SAnthony Koo /** 1817ecc11601SAnthony Koo * FEC re-enable delay when PSR exit. 1818ecc11601SAnthony Koo * unit is 100us, range form 0~255(0xFF). 1819ecc11601SAnthony Koo */ 1820ecc11601SAnthony Koo uint8_t fec_enable_delay_in100us; 1821ecc11601SAnthony Koo /** 1822f56c837aSMikita Lipski * PSR control version. 1823ecc11601SAnthony Koo */ 1824f56c837aSMikita Lipski uint8_t cmd_version; 1825f56c837aSMikita Lipski /** 1826f56c837aSMikita Lipski * Panel Instance. 1827f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1828f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1829f56c837aSMikita Lipski */ 1830f56c837aSMikita Lipski uint8_t panel_inst; 18312665f63aSMikita Lipski /* 18322665f63aSMikita Lipski * DSC enable status in driver 1833360d1b65SIan Chen */ 18342665f63aSMikita Lipski uint8_t dsc_enable_status; 1835b5175966SShah Dharati /* 1836b5175966SShah Dharati * Use FSM state for PSR power up/down 18372665f63aSMikita Lipski */ 1838b5175966SShah Dharati uint8_t use_phy_fsm; 1839b5175966SShah Dharati /** 1840b5175966SShah Dharati * Explicit padding to 2 byte boundary. 1841b5175966SShah Dharati */ 1842b5175966SShah Dharati uint8_t pad3[2]; 18437c008829SNicholas Kazlauskas }; 18447c008829SNicholas Kazlauskas 18451a595f28SAnthony Koo /** 18461a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 18471a595f28SAnthony Koo */ 18487c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings { 18491a595f28SAnthony Koo /** 18501a595f28SAnthony Koo * Command header. 18511a595f28SAnthony Koo */ 18527c008829SNicholas Kazlauskas struct dmub_cmd_header header; 18531a595f28SAnthony Koo /** 18541a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 18551a595f28SAnthony Koo */ 18567c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 18577c008829SNicholas Kazlauskas }; 18587c008829SNicholas Kazlauskas 18591a595f28SAnthony Koo /** 18601a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 18611a595f28SAnthony Koo */ 18627c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data { 18631a595f28SAnthony Koo /** 18641a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality. 18651a595f28SAnthony Koo */ 18667c008829SNicholas Kazlauskas uint16_t psr_level; 18671a595f28SAnthony Koo /** 1868f56c837aSMikita Lipski * PSR control version. 18691a595f28SAnthony Koo */ 1870f56c837aSMikita Lipski uint8_t cmd_version; 1871f56c837aSMikita Lipski /** 1872f56c837aSMikita Lipski * Panel Instance. 1873f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1874f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1875f56c837aSMikita Lipski */ 1876f56c837aSMikita Lipski uint8_t panel_inst; 18777c008829SNicholas Kazlauskas }; 18787c008829SNicholas Kazlauskas 18791a595f28SAnthony Koo /** 18801a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 18811a595f28SAnthony Koo */ 18827c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level { 18831a595f28SAnthony Koo /** 18841a595f28SAnthony Koo * Command header. 18851a595f28SAnthony Koo */ 18867c008829SNicholas Kazlauskas struct dmub_cmd_header header; 18871a595f28SAnthony Koo /** 18881a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 18891a595f28SAnthony Koo */ 18907c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data psr_set_level_data; 18917c008829SNicholas Kazlauskas }; 18927c008829SNicholas Kazlauskas 1893f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data { 1894f56c837aSMikita Lipski /** 1895f56c837aSMikita Lipski * PSR control version. 1896f56c837aSMikita Lipski */ 1897f56c837aSMikita Lipski uint8_t cmd_version; 1898f56c837aSMikita Lipski /** 1899f56c837aSMikita Lipski * Panel Instance. 1900f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1901f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1902f56c837aSMikita Lipski */ 1903f56c837aSMikita Lipski uint8_t panel_inst; 1904f56c837aSMikita Lipski /** 190578174f47SAnthony Koo * Phy state to enter. 190678174f47SAnthony Koo * Values to use are defined in dmub_phy_fsm_state 1907f56c837aSMikita Lipski */ 190878174f47SAnthony Koo uint8_t phy_fsm_state; 190978174f47SAnthony Koo /** 191078174f47SAnthony Koo * Phy rate for DP - RBR/HBR/HBR2/HBR3. 191178174f47SAnthony Koo * Set this using enum phy_link_rate. 191278174f47SAnthony Koo * This does not support HDMI/DP2 for now. 191378174f47SAnthony Koo */ 191478174f47SAnthony Koo uint8_t phy_rate; 1915f56c837aSMikita Lipski }; 1916f56c837aSMikita Lipski 19171a595f28SAnthony Koo /** 19181a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 19191a595f28SAnthony Koo * PSR enable/disable is controlled using the sub_type. 19201a595f28SAnthony Koo */ 19217c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_enable { 19221a595f28SAnthony Koo /** 19231a595f28SAnthony Koo * Command header. 19241a595f28SAnthony Koo */ 19257c008829SNicholas Kazlauskas struct dmub_cmd_header header; 1926f56c837aSMikita Lipski 1927f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data data; 19287c008829SNicholas Kazlauskas }; 19297c008829SNicholas Kazlauskas 19301a595f28SAnthony Koo /** 19311a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 19321a595f28SAnthony Koo */ 1933d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data { 19341a595f28SAnthony Koo /** 19351a595f28SAnthony Koo * PSR version that FW should implement. 19361a595f28SAnthony Koo */ 19371a595f28SAnthony Koo enum psr_version version; 1938f56c837aSMikita Lipski /** 1939f56c837aSMikita Lipski * PSR control version. 1940f56c837aSMikita Lipski */ 1941f56c837aSMikita Lipski uint8_t cmd_version; 1942f56c837aSMikita Lipski /** 1943f56c837aSMikita Lipski * Panel Instance. 1944f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1945f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1946f56c837aSMikita Lipski */ 1947f56c837aSMikita Lipski uint8_t panel_inst; 1948f56c837aSMikita Lipski /** 1949f56c837aSMikita Lipski * Explicit padding to 4 byte boundary. 1950f56c837aSMikita Lipski */ 1951f56c837aSMikita Lipski uint8_t pad[2]; 19527c008829SNicholas Kazlauskas }; 19537c008829SNicholas Kazlauskas 19541a595f28SAnthony Koo /** 19551a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 19561a595f28SAnthony Koo */ 1957d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version { 19581a595f28SAnthony Koo /** 19591a595f28SAnthony Koo * Command header. 19601a595f28SAnthony Koo */ 19617c008829SNicholas Kazlauskas struct dmub_cmd_header header; 19621a595f28SAnthony Koo /** 19631a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 19641a595f28SAnthony Koo */ 1965d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data psr_set_version_data; 19667c008829SNicholas Kazlauskas }; 19677c008829SNicholas Kazlauskas 1968f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data { 1969f56c837aSMikita Lipski /** 1970f56c837aSMikita Lipski * PSR control version. 1971f56c837aSMikita Lipski */ 1972f56c837aSMikita Lipski uint8_t cmd_version; 1973f56c837aSMikita Lipski /** 1974f56c837aSMikita Lipski * Panel Instance. 1975f56c837aSMikita Lipski * Panel isntance to identify which psr_state to use 1976f56c837aSMikita Lipski * Currently the support is only for 0 or 1 1977f56c837aSMikita Lipski */ 1978f56c837aSMikita Lipski uint8_t panel_inst; 1979f56c837aSMikita Lipski /** 1980ad371c8aSAnthony Koo * Explicit padding to 4 byte boundary. 1981f56c837aSMikita Lipski */ 1982ad371c8aSAnthony Koo uint8_t pad[2]; 1983f56c837aSMikita Lipski }; 1984f56c837aSMikita Lipski 19851a595f28SAnthony Koo /** 19861a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 19871a595f28SAnthony Koo */ 1988672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static { 19891a595f28SAnthony Koo /** 19901a595f28SAnthony Koo * Command header. 19911a595f28SAnthony Koo */ 1992672251b2SAnthony Koo struct dmub_cmd_header header; 1993f56c837aSMikita Lipski /** 1994f56c837aSMikita Lipski * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 1995f56c837aSMikita Lipski */ 1996f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data psr_force_static_data; 1997672251b2SAnthony Koo }; 1998672251b2SAnthony Koo 19991a595f28SAnthony Koo /** 200083eb5385SDavid Zhang * PSR SU debug flags. 200183eb5385SDavid Zhang */ 200283eb5385SDavid Zhang union dmub_psr_su_debug_flags { 200383eb5385SDavid Zhang /** 200483eb5385SDavid Zhang * PSR SU debug flags. 200583eb5385SDavid Zhang */ 200683eb5385SDavid Zhang struct { 200783eb5385SDavid Zhang /** 200883eb5385SDavid Zhang * Update dirty rect in SW only. 200983eb5385SDavid Zhang */ 201083eb5385SDavid Zhang uint8_t update_dirty_rect_only : 1; 201183eb5385SDavid Zhang /** 201283eb5385SDavid Zhang * Reset the cursor/plane state before processing the call. 201383eb5385SDavid Zhang */ 201483eb5385SDavid Zhang uint8_t reset_state : 1; 201583eb5385SDavid Zhang } bitfields; 201683eb5385SDavid Zhang 201783eb5385SDavid Zhang /** 201883eb5385SDavid Zhang * Union for debug flags. 201983eb5385SDavid Zhang */ 202083eb5385SDavid Zhang uint32_t u32All; 202183eb5385SDavid Zhang }; 202283eb5385SDavid Zhang 202383eb5385SDavid Zhang /** 202483eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 202583eb5385SDavid Zhang * This triggers a selective update for PSR SU. 202683eb5385SDavid Zhang */ 202783eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data { 202883eb5385SDavid Zhang /** 202983eb5385SDavid Zhang * Dirty rects from OS. 203083eb5385SDavid Zhang */ 203183eb5385SDavid Zhang struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 203283eb5385SDavid Zhang /** 203383eb5385SDavid Zhang * PSR SU debug flags. 203483eb5385SDavid Zhang */ 203583eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags; 203683eb5385SDavid Zhang /** 203783eb5385SDavid Zhang * OTG HW instance. 203883eb5385SDavid Zhang */ 203983eb5385SDavid Zhang uint8_t pipe_idx; 204083eb5385SDavid Zhang /** 204183eb5385SDavid Zhang * Number of dirty rects. 204283eb5385SDavid Zhang */ 204383eb5385SDavid Zhang uint8_t dirty_rect_count; 204483eb5385SDavid Zhang /** 204583eb5385SDavid Zhang * PSR control version. 204683eb5385SDavid Zhang */ 204783eb5385SDavid Zhang uint8_t cmd_version; 204883eb5385SDavid Zhang /** 204983eb5385SDavid Zhang * Panel Instance. 205083eb5385SDavid Zhang * Panel isntance to identify which psr_state to use 205183eb5385SDavid Zhang * Currently the support is only for 0 or 1 205283eb5385SDavid Zhang */ 205383eb5385SDavid Zhang uint8_t panel_inst; 205483eb5385SDavid Zhang }; 205583eb5385SDavid Zhang 205683eb5385SDavid Zhang /** 205783eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 205883eb5385SDavid Zhang */ 205983eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect { 206083eb5385SDavid Zhang /** 206183eb5385SDavid Zhang * Command header. 206283eb5385SDavid Zhang */ 206383eb5385SDavid Zhang struct dmub_cmd_header header; 206483eb5385SDavid Zhang /** 206583eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 206683eb5385SDavid Zhang */ 206783eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 206883eb5385SDavid Zhang }; 206983eb5385SDavid Zhang 207083eb5385SDavid Zhang /** 207183eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 207283eb5385SDavid Zhang */ 207383eb5385SDavid Zhang struct dmub_cmd_update_cursor_info_data { 207483eb5385SDavid Zhang /** 207583eb5385SDavid Zhang * Cursor dirty rects. 207683eb5385SDavid Zhang */ 207783eb5385SDavid Zhang struct dmub_rect cursor_rect; 207883eb5385SDavid Zhang /** 207983eb5385SDavid Zhang * PSR SU debug flags. 208083eb5385SDavid Zhang */ 208183eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags; 208283eb5385SDavid Zhang /** 208383eb5385SDavid Zhang * Cursor enable/disable. 208483eb5385SDavid Zhang */ 208583eb5385SDavid Zhang uint8_t enable; 208683eb5385SDavid Zhang /** 208783eb5385SDavid Zhang * OTG HW instance. 208883eb5385SDavid Zhang */ 208983eb5385SDavid Zhang uint8_t pipe_idx; 209083eb5385SDavid Zhang /** 209183eb5385SDavid Zhang * PSR control version. 209283eb5385SDavid Zhang */ 209383eb5385SDavid Zhang uint8_t cmd_version; 209483eb5385SDavid Zhang /** 209583eb5385SDavid Zhang * Panel Instance. 209683eb5385SDavid Zhang * Panel isntance to identify which psr_state to use 209783eb5385SDavid Zhang * Currently the support is only for 0 or 1 209883eb5385SDavid Zhang */ 209983eb5385SDavid Zhang uint8_t panel_inst; 210083eb5385SDavid Zhang }; 210183eb5385SDavid Zhang /** 210283eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 210383eb5385SDavid Zhang */ 210483eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info { 210583eb5385SDavid Zhang /** 210683eb5385SDavid Zhang * Command header. 210783eb5385SDavid Zhang */ 210883eb5385SDavid Zhang struct dmub_cmd_header header; 210983eb5385SDavid Zhang /** 211083eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 211183eb5385SDavid Zhang */ 211283eb5385SDavid Zhang struct dmub_cmd_update_cursor_info_data update_cursor_info_data; 211383eb5385SDavid Zhang }; 211483eb5385SDavid Zhang 211583eb5385SDavid Zhang /** 211683eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 211783eb5385SDavid Zhang */ 211883eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data { 211983eb5385SDavid Zhang /** 212083eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 212183eb5385SDavid Zhang */ 212283eb5385SDavid Zhang uint16_t psr_vtotal_idle; 212383eb5385SDavid Zhang /** 212483eb5385SDavid Zhang * PSR control version. 212583eb5385SDavid Zhang */ 212683eb5385SDavid Zhang uint8_t cmd_version; 212783eb5385SDavid Zhang /** 212883eb5385SDavid Zhang * Panel Instance. 212983eb5385SDavid Zhang * Panel isntance to identify which psr_state to use 213083eb5385SDavid Zhang * Currently the support is only for 0 or 1 213183eb5385SDavid Zhang */ 213283eb5385SDavid Zhang uint8_t panel_inst; 213383eb5385SDavid Zhang /* 213483eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 213583eb5385SDavid Zhang */ 213683eb5385SDavid Zhang uint16_t psr_vtotal_su; 213783eb5385SDavid Zhang /** 213883eb5385SDavid Zhang * Explicit padding to 4 byte boundary. 213983eb5385SDavid Zhang */ 214083eb5385SDavid Zhang uint8_t pad2[2]; 214183eb5385SDavid Zhang }; 214283eb5385SDavid Zhang 214383eb5385SDavid Zhang /** 214483eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 214583eb5385SDavid Zhang */ 214683eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal { 214783eb5385SDavid Zhang /** 214883eb5385SDavid Zhang * Command header. 214983eb5385SDavid Zhang */ 215083eb5385SDavid Zhang struct dmub_cmd_header header; 215183eb5385SDavid Zhang /** 215283eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 215383eb5385SDavid Zhang */ 215483eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 215583eb5385SDavid Zhang }; 215683eb5385SDavid Zhang 215783eb5385SDavid Zhang /** 2158e5dfcd27SRobin Chen * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2159e5dfcd27SRobin Chen */ 2160e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data { 2161e5dfcd27SRobin Chen /** 2162e5dfcd27SRobin Chen * PSR control version. 2163e5dfcd27SRobin Chen */ 2164e5dfcd27SRobin Chen uint8_t cmd_version; 2165e5dfcd27SRobin Chen /** 2166e5dfcd27SRobin Chen * Panel Instance. 2167e5dfcd27SRobin Chen * Panel isntance to identify which psr_state to use 2168e5dfcd27SRobin Chen * Currently the support is only for 0 or 1 2169e5dfcd27SRobin Chen */ 2170e5dfcd27SRobin Chen uint8_t panel_inst; 2171e5dfcd27SRobin Chen /** 2172e5dfcd27SRobin Chen * Explicit padding to 4 byte boundary. 2173e5dfcd27SRobin Chen */ 2174e5dfcd27SRobin Chen uint8_t pad[2]; 2175e5dfcd27SRobin Chen /** 2176e5dfcd27SRobin Chen * PSR power option 2177e5dfcd27SRobin Chen */ 2178e5dfcd27SRobin Chen uint32_t power_opt; 2179e5dfcd27SRobin Chen }; 2180e5dfcd27SRobin Chen 2181e5dfcd27SRobin Chen /** 2182e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2183e5dfcd27SRobin Chen */ 2184e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt { 2185e5dfcd27SRobin Chen /** 2186e5dfcd27SRobin Chen * Command header. 2187e5dfcd27SRobin Chen */ 2188e5dfcd27SRobin Chen struct dmub_cmd_header header; 2189e5dfcd27SRobin Chen /** 2190e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2191e5dfcd27SRobin Chen */ 2192e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2193e5dfcd27SRobin Chen }; 2194e5dfcd27SRobin Chen 2195e5dfcd27SRobin Chen /** 21961a595f28SAnthony Koo * Set of HW components that can be locked. 21970b51e7e8SAnthony Koo * 21980b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 21990b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 22001a595f28SAnthony Koo */ 2201788408b7SAnthony Koo union dmub_hw_lock_flags { 22021a595f28SAnthony Koo /** 22031a595f28SAnthony Koo * Set of HW components that can be locked. 22041a595f28SAnthony Koo */ 2205788408b7SAnthony Koo struct { 22061a595f28SAnthony Koo /** 22071a595f28SAnthony Koo * Lock/unlock OTG master update lock. 22081a595f28SAnthony Koo */ 2209788408b7SAnthony Koo uint8_t lock_pipe : 1; 22101a595f28SAnthony Koo /** 22111a595f28SAnthony Koo * Lock/unlock cursor. 22121a595f28SAnthony Koo */ 2213788408b7SAnthony Koo uint8_t lock_cursor : 1; 22141a595f28SAnthony Koo /** 22151a595f28SAnthony Koo * Lock/unlock global update lock. 22161a595f28SAnthony Koo */ 2217788408b7SAnthony Koo uint8_t lock_dig : 1; 22181a595f28SAnthony Koo /** 22191a595f28SAnthony Koo * Triple buffer lock requires additional hw programming to usual OTG master lock. 22201a595f28SAnthony Koo */ 2221788408b7SAnthony Koo uint8_t triple_buffer_lock : 1; 2222788408b7SAnthony Koo } bits; 2223788408b7SAnthony Koo 22241a595f28SAnthony Koo /** 22251a595f28SAnthony Koo * Union for HW Lock flags. 22261a595f28SAnthony Koo */ 2227788408b7SAnthony Koo uint8_t u8All; 2228788408b7SAnthony Koo }; 2229788408b7SAnthony Koo 22301a595f28SAnthony Koo /** 22311a595f28SAnthony Koo * Instances of HW to be locked. 22320b51e7e8SAnthony Koo * 22330b51e7e8SAnthony Koo * Note: If updating with more HW components, fields 22340b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match. 22351a595f28SAnthony Koo */ 2236788408b7SAnthony Koo struct dmub_hw_lock_inst_flags { 22371a595f28SAnthony Koo /** 22381a595f28SAnthony Koo * OTG HW instance for OTG master update lock. 22391a595f28SAnthony Koo */ 2240788408b7SAnthony Koo uint8_t otg_inst; 22411a595f28SAnthony Koo /** 22421a595f28SAnthony Koo * OPP instance for cursor lock. 22431a595f28SAnthony Koo */ 2244788408b7SAnthony Koo uint8_t opp_inst; 22451a595f28SAnthony Koo /** 22461a595f28SAnthony Koo * OTG HW instance for global update lock. 22471a595f28SAnthony Koo * TODO: Remove, and re-use otg_inst. 22481a595f28SAnthony Koo */ 2249788408b7SAnthony Koo uint8_t dig_inst; 22501a595f28SAnthony Koo /** 22511a595f28SAnthony Koo * Explicit pad to 4 byte boundary. 22521a595f28SAnthony Koo */ 2253788408b7SAnthony Koo uint8_t pad; 2254788408b7SAnthony Koo }; 2255788408b7SAnthony Koo 22561a595f28SAnthony Koo /** 22571a595f28SAnthony Koo * Clients that can acquire the HW Lock Manager. 22580b51e7e8SAnthony Koo * 22590b51e7e8SAnthony Koo * Note: If updating with more clients, fields in 22600b51e7e8SAnthony Koo * dmub_inbox0_cmd_lock_hw must be updated to match. 22611a595f28SAnthony Koo */ 2262788408b7SAnthony Koo enum hw_lock_client { 22631a595f28SAnthony Koo /** 22641a595f28SAnthony Koo * Driver is the client of HW Lock Manager. 22651a595f28SAnthony Koo */ 2266788408b7SAnthony Koo HW_LOCK_CLIENT_DRIVER = 0, 22671a595f28SAnthony Koo /** 226883eb5385SDavid Zhang * PSR SU is the client of HW Lock Manager. 226983eb5385SDavid Zhang */ 227083eb5385SDavid Zhang HW_LOCK_CLIENT_PSR_SU = 1, 227183eb5385SDavid Zhang /** 22721a595f28SAnthony Koo * Invalid client. 22731a595f28SAnthony Koo */ 2274788408b7SAnthony Koo HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2275788408b7SAnthony Koo }; 2276788408b7SAnthony Koo 22771a595f28SAnthony Koo /** 22781a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 22791a595f28SAnthony Koo */ 2280788408b7SAnthony Koo struct dmub_cmd_lock_hw_data { 22811a595f28SAnthony Koo /** 22821a595f28SAnthony Koo * Specifies the client accessing HW Lock Manager. 22831a595f28SAnthony Koo */ 2284788408b7SAnthony Koo enum hw_lock_client client; 22851a595f28SAnthony Koo /** 22861a595f28SAnthony Koo * HW instances to be locked. 22871a595f28SAnthony Koo */ 2288788408b7SAnthony Koo struct dmub_hw_lock_inst_flags inst_flags; 22891a595f28SAnthony Koo /** 22901a595f28SAnthony Koo * Which components to be locked. 22911a595f28SAnthony Koo */ 2292788408b7SAnthony Koo union dmub_hw_lock_flags hw_locks; 22931a595f28SAnthony Koo /** 22941a595f28SAnthony Koo * Specifies lock/unlock. 22951a595f28SAnthony Koo */ 2296788408b7SAnthony Koo uint8_t lock; 22971a595f28SAnthony Koo /** 22981a595f28SAnthony Koo * HW can be unlocked separately from releasing the HW Lock Mgr. 22991a595f28SAnthony Koo * This flag is set if the client wishes to release the object. 23001a595f28SAnthony Koo */ 2301788408b7SAnthony Koo uint8_t should_release; 23021a595f28SAnthony Koo /** 23031a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 23041a595f28SAnthony Koo */ 2305788408b7SAnthony Koo uint8_t pad; 2306788408b7SAnthony Koo }; 2307788408b7SAnthony Koo 23081a595f28SAnthony Koo /** 23091a595f28SAnthony Koo * Definition of a DMUB_CMD__HW_LOCK command. 23101a595f28SAnthony Koo * Command is used by driver and FW. 23111a595f28SAnthony Koo */ 2312788408b7SAnthony Koo struct dmub_rb_cmd_lock_hw { 23131a595f28SAnthony Koo /** 23141a595f28SAnthony Koo * Command header. 23151a595f28SAnthony Koo */ 2316788408b7SAnthony Koo struct dmub_cmd_header header; 23171a595f28SAnthony Koo /** 23181a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 23191a595f28SAnthony Koo */ 2320788408b7SAnthony Koo struct dmub_cmd_lock_hw_data lock_hw_data; 2321788408b7SAnthony Koo }; 2322788408b7SAnthony Koo 23231a595f28SAnthony Koo /** 23241a595f28SAnthony Koo * ABM command sub-types. 23251a595f28SAnthony Koo */ 232684034ad4SAnthony Koo enum dmub_cmd_abm_type { 23271a595f28SAnthony Koo /** 23281a595f28SAnthony Koo * Initialize parameters for ABM algorithm. 23291a595f28SAnthony Koo * Data is passed through an indirect buffer. 23301a595f28SAnthony Koo */ 233184034ad4SAnthony Koo DMUB_CMD__ABM_INIT_CONFIG = 0, 23321a595f28SAnthony Koo /** 23331a595f28SAnthony Koo * Set OTG and panel HW instance. 23341a595f28SAnthony Koo */ 233584034ad4SAnthony Koo DMUB_CMD__ABM_SET_PIPE = 1, 23361a595f28SAnthony Koo /** 23371a595f28SAnthony Koo * Set user requested backklight level. 23381a595f28SAnthony Koo */ 233984034ad4SAnthony Koo DMUB_CMD__ABM_SET_BACKLIGHT = 2, 23401a595f28SAnthony Koo /** 23411a595f28SAnthony Koo * Set ABM operating/aggression level. 23421a595f28SAnthony Koo */ 234384034ad4SAnthony Koo DMUB_CMD__ABM_SET_LEVEL = 3, 23441a595f28SAnthony Koo /** 23451a595f28SAnthony Koo * Set ambient light level. 23461a595f28SAnthony Koo */ 234784034ad4SAnthony Koo DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 23481a595f28SAnthony Koo /** 23491a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 23501a595f28SAnthony Koo */ 235184034ad4SAnthony Koo DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2352b629a824SEric Yang 2353b629a824SEric Yang /** 2354b629a824SEric Yang * unregister vertical interrupt after steady state is reached 2355b629a824SEric Yang */ 2356b629a824SEric Yang DMUB_CMD__ABM_PAUSE = 6, 235784034ad4SAnthony Koo }; 235884034ad4SAnthony Koo 23591a595f28SAnthony Koo /** 23601a595f28SAnthony Koo * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 23611a595f28SAnthony Koo * Requirements: 23621a595f28SAnthony Koo * - Padded explicitly to 32-bit boundary. 23631a595f28SAnthony Koo * - Must ensure this structure matches the one on driver-side, 23641a595f28SAnthony Koo * otherwise it won't be aligned. 236584034ad4SAnthony Koo */ 236684034ad4SAnthony Koo struct abm_config_table { 23671a595f28SAnthony Koo /** 23681a595f28SAnthony Koo * Gamma curve thresholds, used for crgb conversion. 23691a595f28SAnthony Koo */ 237084034ad4SAnthony Koo uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 23711a595f28SAnthony Koo /** 23721a595f28SAnthony Koo * Gamma curve offsets, used for crgb conversion. 23731a595f28SAnthony Koo */ 2374b6402afeSAnthony Koo uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 23751a595f28SAnthony Koo /** 23761a595f28SAnthony Koo * Gamma curve slopes, used for crgb conversion. 23771a595f28SAnthony Koo */ 2378b6402afeSAnthony Koo uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 23791a595f28SAnthony Koo /** 23801a595f28SAnthony Koo * Custom backlight curve thresholds. 23811a595f28SAnthony Koo */ 2382b6402afeSAnthony Koo uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 23831a595f28SAnthony Koo /** 23841a595f28SAnthony Koo * Custom backlight curve offsets. 23851a595f28SAnthony Koo */ 2386b6402afeSAnthony Koo uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 23871a595f28SAnthony Koo /** 23881a595f28SAnthony Koo * Ambient light thresholds. 23891a595f28SAnthony Koo */ 2390b6402afeSAnthony Koo uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 23911a595f28SAnthony Koo /** 23921a595f28SAnthony Koo * Minimum programmable backlight. 23931a595f28SAnthony Koo */ 2394b6402afeSAnthony Koo uint16_t min_abm_backlight; // 122B 23951a595f28SAnthony Koo /** 23961a595f28SAnthony Koo * Minimum reduction values. 23971a595f28SAnthony Koo */ 2398b6402afeSAnthony Koo uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 23991a595f28SAnthony Koo /** 24001a595f28SAnthony Koo * Maximum reduction values. 24011a595f28SAnthony Koo */ 2402b6402afeSAnthony Koo uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 24031a595f28SAnthony Koo /** 24041a595f28SAnthony Koo * Bright positive gain. 24051a595f28SAnthony Koo */ 2406b6402afeSAnthony Koo uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 24071a595f28SAnthony Koo /** 24081a595f28SAnthony Koo * Dark negative gain. 24091a595f28SAnthony Koo */ 2410b6402afeSAnthony Koo uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 24111a595f28SAnthony Koo /** 24121a595f28SAnthony Koo * Hybrid factor. 24131a595f28SAnthony Koo */ 2414b6402afeSAnthony Koo uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 24151a595f28SAnthony Koo /** 24161a595f28SAnthony Koo * Contrast factor. 24171a595f28SAnthony Koo */ 2418b6402afeSAnthony Koo uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 24191a595f28SAnthony Koo /** 24201a595f28SAnthony Koo * Deviation gain. 24211a595f28SAnthony Koo */ 2422b6402afeSAnthony Koo uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 24231a595f28SAnthony Koo /** 24241a595f28SAnthony Koo * Minimum knee. 24251a595f28SAnthony Koo */ 2426b6402afeSAnthony Koo uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 24271a595f28SAnthony Koo /** 24281a595f28SAnthony Koo * Maximum knee. 24291a595f28SAnthony Koo */ 2430b6402afeSAnthony Koo uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 24311a595f28SAnthony Koo /** 24321a595f28SAnthony Koo * Unused. 24331a595f28SAnthony Koo */ 2434b6402afeSAnthony Koo uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 24351a595f28SAnthony Koo /** 24361a595f28SAnthony Koo * Explicit padding to 4 byte boundary. 24371a595f28SAnthony Koo */ 2438b6402afeSAnthony Koo uint8_t pad3[3]; // 229B 24391a595f28SAnthony Koo /** 24401a595f28SAnthony Koo * Backlight ramp reduction. 24411a595f28SAnthony Koo */ 2442b6402afeSAnthony Koo uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 24431a595f28SAnthony Koo /** 24441a595f28SAnthony Koo * Backlight ramp start. 24451a595f28SAnthony Koo */ 2446b6402afeSAnthony Koo uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 244784034ad4SAnthony Koo }; 244884034ad4SAnthony Koo 24491a595f28SAnthony Koo /** 24501a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 24511a595f28SAnthony Koo */ 2452e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data { 24531a595f28SAnthony Koo /** 24541a595f28SAnthony Koo * OTG HW instance. 24551a595f28SAnthony Koo */ 24567b8a6362SAnthony Koo uint8_t otg_inst; 24571a595f28SAnthony Koo 24581a595f28SAnthony Koo /** 24591a595f28SAnthony Koo * Panel Control HW instance. 24601a595f28SAnthony Koo */ 24617b8a6362SAnthony Koo uint8_t panel_inst; 24621a595f28SAnthony Koo 24631a595f28SAnthony Koo /** 24641a595f28SAnthony Koo * Controls how ABM will interpret a set pipe or set level command. 24651a595f28SAnthony Koo */ 24667b8a6362SAnthony Koo uint8_t set_pipe_option; 24671a595f28SAnthony Koo 24681a595f28SAnthony Koo /** 24691a595f28SAnthony Koo * Unused. 24701a595f28SAnthony Koo * TODO: Remove. 24711a595f28SAnthony Koo */ 24721a595f28SAnthony Koo uint8_t ramping_boundary; 2473e6ea8c34SWyatt Wood }; 2474e6ea8c34SWyatt Wood 24751a595f28SAnthony Koo /** 24761a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 24771a595f28SAnthony Koo */ 2478e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe { 24791a595f28SAnthony Koo /** 24801a595f28SAnthony Koo * Command header. 24811a595f28SAnthony Koo */ 2482e6ea8c34SWyatt Wood struct dmub_cmd_header header; 24831a595f28SAnthony Koo 24841a595f28SAnthony Koo /** 24851a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 24861a595f28SAnthony Koo */ 2487e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2488e6ea8c34SWyatt Wood }; 2489e6ea8c34SWyatt Wood 24901a595f28SAnthony Koo /** 24911a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 24921a595f28SAnthony Koo */ 2493e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data { 24941a595f28SAnthony Koo /** 24951a595f28SAnthony Koo * Number of frames to ramp to backlight user level. 24961a595f28SAnthony Koo */ 2497e6ea8c34SWyatt Wood uint32_t frame_ramp; 24981a595f28SAnthony Koo 24991a595f28SAnthony Koo /** 25001a595f28SAnthony Koo * Requested backlight level from user. 25011a595f28SAnthony Koo */ 2502474ac4a8SYongqiang Sun uint32_t backlight_user_level; 2503e922057bSJake Wang 2504e922057bSJake Wang /** 250563de4f04SJake Wang * ABM control version. 2506e922057bSJake Wang */ 2507e922057bSJake Wang uint8_t version; 2508e922057bSJake Wang 2509e922057bSJake Wang /** 2510e922057bSJake Wang * Panel Control HW instance mask. 2511e922057bSJake Wang * Bit 0 is Panel Control HW instance 0. 2512e922057bSJake Wang * Bit 1 is Panel Control HW instance 1. 2513e922057bSJake Wang */ 2514e922057bSJake Wang uint8_t panel_mask; 2515e922057bSJake Wang 2516e922057bSJake Wang /** 2517e922057bSJake Wang * Explicit padding to 4 byte boundary. 2518e922057bSJake Wang */ 2519e922057bSJake Wang uint8_t pad[2]; 2520e6ea8c34SWyatt Wood }; 2521e6ea8c34SWyatt Wood 25221a595f28SAnthony Koo /** 25231a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 25241a595f28SAnthony Koo */ 2525e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight { 25261a595f28SAnthony Koo /** 25271a595f28SAnthony Koo * Command header. 25281a595f28SAnthony Koo */ 2529e6ea8c34SWyatt Wood struct dmub_cmd_header header; 25301a595f28SAnthony Koo 25311a595f28SAnthony Koo /** 25321a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 25331a595f28SAnthony Koo */ 2534e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2535e6ea8c34SWyatt Wood }; 2536e6ea8c34SWyatt Wood 25371a595f28SAnthony Koo /** 25381a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 25391a595f28SAnthony Koo */ 2540e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data { 25411a595f28SAnthony Koo /** 25421a595f28SAnthony Koo * Set current ABM operating/aggression level. 25431a595f28SAnthony Koo */ 2544e6ea8c34SWyatt Wood uint32_t level; 254563de4f04SJake Wang 254663de4f04SJake Wang /** 254763de4f04SJake Wang * ABM control version. 254863de4f04SJake Wang */ 254963de4f04SJake Wang uint8_t version; 255063de4f04SJake Wang 255163de4f04SJake Wang /** 255263de4f04SJake Wang * Panel Control HW instance mask. 255363de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 255463de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 255563de4f04SJake Wang */ 255663de4f04SJake Wang uint8_t panel_mask; 255763de4f04SJake Wang 255863de4f04SJake Wang /** 255963de4f04SJake Wang * Explicit padding to 4 byte boundary. 256063de4f04SJake Wang */ 256163de4f04SJake Wang uint8_t pad[2]; 2562e6ea8c34SWyatt Wood }; 2563e6ea8c34SWyatt Wood 25641a595f28SAnthony Koo /** 25651a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 25661a595f28SAnthony Koo */ 2567e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level { 25681a595f28SAnthony Koo /** 25691a595f28SAnthony Koo * Command header. 25701a595f28SAnthony Koo */ 2571e6ea8c34SWyatt Wood struct dmub_cmd_header header; 25721a595f28SAnthony Koo 25731a595f28SAnthony Koo /** 25741a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 25751a595f28SAnthony Koo */ 2576e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data abm_set_level_data; 2577e6ea8c34SWyatt Wood }; 2578e6ea8c34SWyatt Wood 25791a595f28SAnthony Koo /** 25801a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 25811a595f28SAnthony Koo */ 2582e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data { 25831a595f28SAnthony Koo /** 25841a595f28SAnthony Koo * Ambient light sensor reading from OS. 25851a595f28SAnthony Koo */ 2586e6ea8c34SWyatt Wood uint32_t ambient_lux; 258763de4f04SJake Wang 258863de4f04SJake Wang /** 258963de4f04SJake Wang * ABM control version. 259063de4f04SJake Wang */ 259163de4f04SJake Wang uint8_t version; 259263de4f04SJake Wang 259363de4f04SJake Wang /** 259463de4f04SJake Wang * Panel Control HW instance mask. 259563de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 259663de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 259763de4f04SJake Wang */ 259863de4f04SJake Wang uint8_t panel_mask; 259963de4f04SJake Wang 260063de4f04SJake Wang /** 260163de4f04SJake Wang * Explicit padding to 4 byte boundary. 260263de4f04SJake Wang */ 260363de4f04SJake Wang uint8_t pad[2]; 2604e6ea8c34SWyatt Wood }; 2605e6ea8c34SWyatt Wood 26061a595f28SAnthony Koo /** 26071a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 26081a595f28SAnthony Koo */ 2609e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level { 26101a595f28SAnthony Koo /** 26111a595f28SAnthony Koo * Command header. 26121a595f28SAnthony Koo */ 2613e6ea8c34SWyatt Wood struct dmub_cmd_header header; 26141a595f28SAnthony Koo 26151a595f28SAnthony Koo /** 26161a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 26171a595f28SAnthony Koo */ 2618e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2619e6ea8c34SWyatt Wood }; 2620e6ea8c34SWyatt Wood 26211a595f28SAnthony Koo /** 26221a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 26231a595f28SAnthony Koo */ 2624e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data { 26251a595f28SAnthony Koo /** 26261a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM. 26271a595f28SAnthony Koo * TODO: Convert to uint8_t. 26281a595f28SAnthony Koo */ 2629e6ea8c34SWyatt Wood uint32_t fractional_pwm; 263063de4f04SJake Wang 263163de4f04SJake Wang /** 263263de4f04SJake Wang * ABM control version. 263363de4f04SJake Wang */ 263463de4f04SJake Wang uint8_t version; 263563de4f04SJake Wang 263663de4f04SJake Wang /** 263763de4f04SJake Wang * Panel Control HW instance mask. 263863de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 263963de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 264063de4f04SJake Wang */ 264163de4f04SJake Wang uint8_t panel_mask; 264263de4f04SJake Wang 264363de4f04SJake Wang /** 264463de4f04SJake Wang * Explicit padding to 4 byte boundary. 264563de4f04SJake Wang */ 264663de4f04SJake Wang uint8_t pad[2]; 2647e6ea8c34SWyatt Wood }; 2648e6ea8c34SWyatt Wood 26491a595f28SAnthony Koo /** 26501a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 26511a595f28SAnthony Koo */ 2652e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac { 26531a595f28SAnthony Koo /** 26541a595f28SAnthony Koo * Command header. 26551a595f28SAnthony Koo */ 2656e6ea8c34SWyatt Wood struct dmub_cmd_header header; 26571a595f28SAnthony Koo 26581a595f28SAnthony Koo /** 26591a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 26601a595f28SAnthony Koo */ 2661e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2662e6ea8c34SWyatt Wood }; 2663e6ea8c34SWyatt Wood 26641a595f28SAnthony Koo /** 26651a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 26661a595f28SAnthony Koo */ 266716012806SWyatt Wood struct dmub_cmd_abm_init_config_data { 26681a595f28SAnthony Koo /** 26691a595f28SAnthony Koo * Location of indirect buffer used to pass init data to ABM. 26701a595f28SAnthony Koo */ 267116012806SWyatt Wood union dmub_addr src; 26721a595f28SAnthony Koo 26731a595f28SAnthony Koo /** 26741a595f28SAnthony Koo * Indirect buffer length. 26751a595f28SAnthony Koo */ 267616012806SWyatt Wood uint16_t bytes; 267763de4f04SJake Wang 267863de4f04SJake Wang 267963de4f04SJake Wang /** 268063de4f04SJake Wang * ABM control version. 268163de4f04SJake Wang */ 268263de4f04SJake Wang uint8_t version; 268363de4f04SJake Wang 268463de4f04SJake Wang /** 268563de4f04SJake Wang * Panel Control HW instance mask. 268663de4f04SJake Wang * Bit 0 is Panel Control HW instance 0. 268763de4f04SJake Wang * Bit 1 is Panel Control HW instance 1. 268863de4f04SJake Wang */ 268963de4f04SJake Wang uint8_t panel_mask; 269063de4f04SJake Wang 269163de4f04SJake Wang /** 269263de4f04SJake Wang * Explicit padding to 4 byte boundary. 269363de4f04SJake Wang */ 269463de4f04SJake Wang uint8_t pad[2]; 269516012806SWyatt Wood }; 269616012806SWyatt Wood 26971a595f28SAnthony Koo /** 26981a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 26991a595f28SAnthony Koo */ 270016012806SWyatt Wood struct dmub_rb_cmd_abm_init_config { 27011a595f28SAnthony Koo /** 27021a595f28SAnthony Koo * Command header. 27031a595f28SAnthony Koo */ 270416012806SWyatt Wood struct dmub_cmd_header header; 27051a595f28SAnthony Koo 27061a595f28SAnthony Koo /** 27071a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 27081a595f28SAnthony Koo */ 270916012806SWyatt Wood struct dmub_cmd_abm_init_config_data abm_init_config_data; 271016012806SWyatt Wood }; 271116012806SWyatt Wood 27121a595f28SAnthony Koo /** 2713b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2714b629a824SEric Yang */ 2715b629a824SEric Yang 2716b629a824SEric Yang struct dmub_cmd_abm_pause_data { 2717b629a824SEric Yang 2718b629a824SEric Yang /** 2719b629a824SEric Yang * Panel Control HW instance mask. 2720b629a824SEric Yang * Bit 0 is Panel Control HW instance 0. 2721b629a824SEric Yang * Bit 1 is Panel Control HW instance 1. 2722b629a824SEric Yang */ 2723b629a824SEric Yang uint8_t panel_mask; 2724b629a824SEric Yang 2725b629a824SEric Yang /** 2726b629a824SEric Yang * OTG hw instance 2727b629a824SEric Yang */ 2728b629a824SEric Yang uint8_t otg_inst; 2729b629a824SEric Yang 2730b629a824SEric Yang /** 2731b629a824SEric Yang * Enable or disable ABM pause 2732b629a824SEric Yang */ 2733b629a824SEric Yang uint8_t enable; 2734b629a824SEric Yang 2735b629a824SEric Yang /** 2736b629a824SEric Yang * Explicit padding to 4 byte boundary. 2737b629a824SEric Yang */ 2738b629a824SEric Yang uint8_t pad[1]; 2739b629a824SEric Yang }; 2740b629a824SEric Yang 2741b629a824SEric Yang /** 2742b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 2743b629a824SEric Yang */ 2744b629a824SEric Yang struct dmub_rb_cmd_abm_pause { 2745b629a824SEric Yang /** 2746b629a824SEric Yang * Command header. 2747b629a824SEric Yang */ 2748b629a824SEric Yang struct dmub_cmd_header header; 2749b629a824SEric Yang 2750b629a824SEric Yang /** 2751b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2752b629a824SEric Yang */ 2753b629a824SEric Yang struct dmub_cmd_abm_pause_data abm_pause_data; 2754b629a824SEric Yang }; 2755b629a824SEric Yang 2756b629a824SEric Yang /** 27571a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 27581a595f28SAnthony Koo */ 275934ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data { 27601a595f28SAnthony Koo /** 27611a595f28SAnthony Koo * DMUB feature capabilities. 27621a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features. 27631a595f28SAnthony Koo */ 276434ba432cSAnthony Koo struct dmub_feature_caps feature_caps; 276534ba432cSAnthony Koo }; 276634ba432cSAnthony Koo 27671a595f28SAnthony Koo /** 27681a595f28SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 27691a595f28SAnthony Koo */ 277034ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps { 27711a595f28SAnthony Koo /** 27721a595f28SAnthony Koo * Command header. 27731a595f28SAnthony Koo */ 277434ba432cSAnthony Koo struct dmub_cmd_header header; 27751a595f28SAnthony Koo /** 27761a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 27771a595f28SAnthony Koo */ 277834ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 277934ba432cSAnthony Koo }; 278034ba432cSAnthony Koo 2781592a6318SAnthony Koo struct dmub_optc_state { 2782592a6318SAnthony Koo uint32_t v_total_max; 2783592a6318SAnthony Koo uint32_t v_total_min; 2784592a6318SAnthony Koo uint32_t v_total_mid; 2785592a6318SAnthony Koo uint32_t v_total_mid_frame_num; 2786592a6318SAnthony Koo uint32_t tg_inst; 2787592a6318SAnthony Koo uint32_t enable_manual_trigger; 2788592a6318SAnthony Koo uint32_t clear_force_vsync; 2789592a6318SAnthony Koo }; 2790592a6318SAnthony Koo 2791592a6318SAnthony Koo struct dmub_rb_cmd_drr_update { 2792592a6318SAnthony Koo struct dmub_cmd_header header; 2793592a6318SAnthony Koo struct dmub_optc_state dmub_optc_state_req; 2794592a6318SAnthony Koo }; 2795592a6318SAnthony Koo 279600fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 279700fa7f03SRodrigo Siqueira uint32_t pix_clk_100hz; 279800fa7f03SRodrigo Siqueira uint8_t max_ramp_step; 279900fa7f03SRodrigo Siqueira uint8_t pipes; 280000fa7f03SRodrigo Siqueira uint8_t min_refresh_in_hz; 280100fa7f03SRodrigo Siqueira uint8_t padding[1]; 280200fa7f03SRodrigo Siqueira }; 280300fa7f03SRodrigo Siqueira 280400fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config { 280500fa7f03SRodrigo Siqueira uint8_t fams_enabled; 280600fa7f03SRodrigo Siqueira uint8_t visual_confirm_enabled; 280700fa7f03SRodrigo Siqueira uint8_t padding[2]; 280800fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 280900fa7f03SRodrigo Siqueira }; 281000fa7f03SRodrigo Siqueira 281100fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch { 281200fa7f03SRodrigo Siqueira struct dmub_cmd_header header; 281300fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 281400fa7f03SRodrigo Siqueira }; 281500fa7f03SRodrigo Siqueira 2816b04cb192SNicholas Kazlauskas /** 2817b04cb192SNicholas Kazlauskas * enum dmub_cmd_panel_cntl_type - Panel control command. 2818b04cb192SNicholas Kazlauskas */ 2819b04cb192SNicholas Kazlauskas enum dmub_cmd_panel_cntl_type { 2820b04cb192SNicholas Kazlauskas /** 2821b04cb192SNicholas Kazlauskas * Initializes embedded panel hardware blocks. 2822b04cb192SNicholas Kazlauskas */ 2823b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2824b04cb192SNicholas Kazlauskas /** 2825b04cb192SNicholas Kazlauskas * Queries backlight info for the embedded panel. 2826b04cb192SNicholas Kazlauskas */ 2827b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2828b04cb192SNicholas Kazlauskas }; 2829b04cb192SNicholas Kazlauskas 2830b04cb192SNicholas Kazlauskas /** 2831b04cb192SNicholas Kazlauskas * struct dmub_cmd_panel_cntl_data - Panel control data. 2832b04cb192SNicholas Kazlauskas */ 2833b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data { 2834b04cb192SNicholas Kazlauskas uint32_t inst; /**< panel instance */ 2835b04cb192SNicholas Kazlauskas uint32_t current_backlight; /* in/out */ 2836b04cb192SNicholas Kazlauskas uint32_t bl_pwm_cntl; /* in/out */ 2837b04cb192SNicholas Kazlauskas uint32_t bl_pwm_period_cntl; /* in/out */ 2838b04cb192SNicholas Kazlauskas uint32_t bl_pwm_ref_div1; /* in/out */ 2839b04cb192SNicholas Kazlauskas uint8_t is_backlight_on : 1; /* in/out */ 2840b04cb192SNicholas Kazlauskas uint8_t is_powered_on : 1; /* in/out */ 2841a91b402dSCharlene Liu uint8_t padding[3]; 2842a91b402dSCharlene Liu uint32_t bl_pwm_ref_div2; /* in/out */ 2843a91b402dSCharlene Liu uint8_t reserved[4]; 2844b04cb192SNicholas Kazlauskas }; 2845b04cb192SNicholas Kazlauskas 2846b04cb192SNicholas Kazlauskas /** 2847b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_panel_cntl - Panel control command. 2848b04cb192SNicholas Kazlauskas */ 2849b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl { 2850b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 2851b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data data; /**< payload */ 2852b04cb192SNicholas Kazlauskas }; 2853b04cb192SNicholas Kazlauskas 28541a595f28SAnthony Koo /** 28551a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 28561a595f28SAnthony Koo */ 28571a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data { 28581a595f28SAnthony Koo uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 28591a595f28SAnthony Koo uint8_t reserved_0[3]; /**< For future use */ 28601a595f28SAnthony Koo uint8_t panel_inst; /**< LVTMA control instance */ 28611a595f28SAnthony Koo uint8_t reserved_1[3]; /**< For future use */ 28621a595f28SAnthony Koo }; 28631a595f28SAnthony Koo 28641a595f28SAnthony Koo /** 28651a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 28661a595f28SAnthony Koo */ 28671a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control { 28681a595f28SAnthony Koo /** 28691a595f28SAnthony Koo * Command header. 28701a595f28SAnthony Koo */ 28711a595f28SAnthony Koo struct dmub_cmd_header header; 28721a595f28SAnthony Koo /** 28731a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 28741a595f28SAnthony Koo */ 28751a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data data; 28761a595f28SAnthony Koo }; 28771a595f28SAnthony Koo 2878592a6318SAnthony Koo /** 287941f91315SNicholas Kazlauskas * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 288041f91315SNicholas Kazlauskas */ 288141f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data { 288241f91315SNicholas Kazlauskas uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 288341f91315SNicholas Kazlauskas uint8_t is_usb; /**< is phy is usb */ 288441f91315SNicholas Kazlauskas uint8_t is_dp_alt_disable; /**< is dp alt disable */ 288541f91315SNicholas Kazlauskas uint8_t is_dp4; /**< is dp in 4 lane */ 288641f91315SNicholas Kazlauskas }; 288741f91315SNicholas Kazlauskas 288841f91315SNicholas Kazlauskas /** 288941f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 289041f91315SNicholas Kazlauskas */ 289141f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt { 289241f91315SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */ 289341f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 289441f91315SNicholas Kazlauskas }; 289541f91315SNicholas Kazlauskas 289641f91315SNicholas Kazlauskas /** 2897021eaef8SAnthony Koo * Maximum number of bytes a chunk sent to DMUB for parsing 2898021eaef8SAnthony Koo */ 2899021eaef8SAnthony Koo #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2900021eaef8SAnthony Koo 2901021eaef8SAnthony Koo /** 2902021eaef8SAnthony Koo * Represent a chunk of CEA blocks sent to DMUB for parsing 2903021eaef8SAnthony Koo */ 2904021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea { 2905021eaef8SAnthony Koo uint16_t offset; /**< offset into the CEA block */ 2906021eaef8SAnthony Koo uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2907eb9e59ebSOliver Logush uint16_t cea_total_length; /**< total length of the CEA block */ 2908021eaef8SAnthony Koo uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2909021eaef8SAnthony Koo uint8_t pad[3]; /**< padding and for future expansion */ 2910021eaef8SAnthony Koo }; 2911021eaef8SAnthony Koo 2912021eaef8SAnthony Koo /** 2913021eaef8SAnthony Koo * Result of VSDB parsing from CEA block 2914021eaef8SAnthony Koo */ 2915021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb { 2916021eaef8SAnthony Koo uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2917021eaef8SAnthony Koo uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2918021eaef8SAnthony Koo uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2919021eaef8SAnthony Koo uint16_t min_frame_rate; /**< Maximum frame rate */ 2920021eaef8SAnthony Koo uint16_t max_frame_rate; /**< Minimum frame rate */ 2921021eaef8SAnthony Koo }; 2922021eaef8SAnthony Koo 2923021eaef8SAnthony Koo /** 2924021eaef8SAnthony Koo * Result of sending a CEA chunk 2925021eaef8SAnthony Koo */ 2926021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack { 2927021eaef8SAnthony Koo uint16_t offset; /**< offset of the chunk into the CEA block */ 2928021eaef8SAnthony Koo uint8_t success; /**< 1 if this sending of chunk succeeded */ 2929021eaef8SAnthony Koo uint8_t pad; /**< padding and for future expansion */ 2930021eaef8SAnthony Koo }; 2931021eaef8SAnthony Koo 2932021eaef8SAnthony Koo /** 2933021eaef8SAnthony Koo * Specify whether the result is an ACK/NACK or the parsing has finished 2934021eaef8SAnthony Koo */ 2935021eaef8SAnthony Koo enum dmub_cmd_edid_cea_reply_type { 2936021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2937021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2938021eaef8SAnthony Koo }; 2939021eaef8SAnthony Koo 2940021eaef8SAnthony Koo /** 2941021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 2942021eaef8SAnthony Koo */ 2943021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea { 2944021eaef8SAnthony Koo struct dmub_cmd_header header; /**< Command header */ 2945021eaef8SAnthony Koo union dmub_cmd_edid_cea_data { 2946021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2947021eaef8SAnthony Koo struct dmub_cmd_edid_cea_output { /**< output with results */ 2948021eaef8SAnthony Koo uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2949021eaef8SAnthony Koo union { 2950021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2951021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack ack; 2952021eaef8SAnthony Koo }; 2953021eaef8SAnthony Koo } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2954021eaef8SAnthony Koo } data; /**< Command data */ 2955021eaef8SAnthony Koo 2956021eaef8SAnthony Koo }; 2957021eaef8SAnthony Koo 2958021eaef8SAnthony Koo /** 2959c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 2960c595fb05SWenjing Liu */ 2961c595fb05SWenjing Liu struct dmub_cmd_cable_id_input { 2962c595fb05SWenjing Liu uint8_t phy_inst; /**< phy inst for cable id data */ 2963c595fb05SWenjing Liu }; 2964c595fb05SWenjing Liu 2965c595fb05SWenjing Liu /** 2966c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 2967c595fb05SWenjing Liu */ 2968c595fb05SWenjing Liu struct dmub_cmd_cable_id_output { 2969c595fb05SWenjing Liu uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 2970c595fb05SWenjing Liu uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 2971c595fb05SWenjing Liu uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 2972c595fb05SWenjing Liu uint8_t RESERVED :2; /**< reserved means not defined */ 2973c595fb05SWenjing Liu }; 2974c595fb05SWenjing Liu 2975c595fb05SWenjing Liu /** 2976c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 2977c595fb05SWenjing Liu */ 2978c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id { 2979c595fb05SWenjing Liu struct dmub_cmd_header header; /**< Command header */ 2980c595fb05SWenjing Liu /** 2981c595fb05SWenjing Liu * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 2982c595fb05SWenjing Liu */ 2983c595fb05SWenjing Liu union dmub_cmd_cable_id_data { 2984c595fb05SWenjing Liu struct dmub_cmd_cable_id_input input; /**< Input */ 2985c595fb05SWenjing Liu struct dmub_cmd_cable_id_output output; /**< Output */ 2986c595fb05SWenjing Liu uint8_t output_raw; /**< Raw data output */ 2987c595fb05SWenjing Liu } data; 2988c595fb05SWenjing Liu }; 2989c595fb05SWenjing Liu 2990c595fb05SWenjing Liu /** 2991592a6318SAnthony Koo * union dmub_rb_cmd - DMUB inbox command. 2992592a6318SAnthony Koo */ 29937c008829SNicholas Kazlauskas union dmub_rb_cmd { 2994592a6318SAnthony Koo /** 2995592a6318SAnthony Koo * Elements shared with all commands. 2996592a6318SAnthony Koo */ 29977c008829SNicholas Kazlauskas struct dmub_rb_cmd_common cmd_common; 2998592a6318SAnthony Koo /** 2999592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3000592a6318SAnthony Koo */ 3001592a6318SAnthony Koo struct dmub_rb_cmd_read_modify_write read_modify_write; 3002592a6318SAnthony Koo /** 3003592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3004592a6318SAnthony Koo */ 3005592a6318SAnthony Koo struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3006592a6318SAnthony Koo /** 3007592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3008592a6318SAnthony Koo */ 3009592a6318SAnthony Koo struct dmub_rb_cmd_burst_write burst_write; 3010592a6318SAnthony Koo /** 3011592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_REG_WAIT command. 3012592a6318SAnthony Koo */ 3013592a6318SAnthony Koo struct dmub_rb_cmd_reg_wait reg_wait; 3014592a6318SAnthony Koo /** 3015592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3016592a6318SAnthony Koo */ 30177c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3018592a6318SAnthony Koo /** 3019592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3020592a6318SAnthony Koo */ 30217c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3022592a6318SAnthony Koo /** 3023592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3024592a6318SAnthony Koo */ 30257c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3026592a6318SAnthony Koo /** 3027592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3028592a6318SAnthony Koo */ 30297c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init dpphy_init; 3030592a6318SAnthony Koo /** 3031592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3032592a6318SAnthony Koo */ 30337c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 30341a595f28SAnthony Koo /** 30351a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command. 30361a595f28SAnthony Koo */ 3037d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version psr_set_version; 30381a595f28SAnthony Koo /** 30391a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 30401a595f28SAnthony Koo */ 30417c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 30421a595f28SAnthony Koo /** 30431a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command. 30441a595f28SAnthony Koo */ 3045d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_enable psr_enable; 30461a595f28SAnthony Koo /** 30471a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 30481a595f28SAnthony Koo */ 30497c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level psr_set_level; 30501a595f28SAnthony Koo /** 30511a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 30521a595f28SAnthony Koo */ 3053672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static psr_force_static; 3054592a6318SAnthony Koo /** 305583eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 305683eb5385SDavid Zhang */ 305783eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 305883eb5385SDavid Zhang /** 305983eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 306083eb5385SDavid Zhang */ 306183eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info update_cursor_info; 306283eb5385SDavid Zhang /** 306383eb5385SDavid Zhang * Definition of a DMUB_CMD__HW_LOCK command. 306483eb5385SDavid Zhang * Command is used by driver and FW. 306583eb5385SDavid Zhang */ 306683eb5385SDavid Zhang struct dmub_rb_cmd_lock_hw lock_hw; 306783eb5385SDavid Zhang /** 306883eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 306983eb5385SDavid Zhang */ 307083eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 307183eb5385SDavid Zhang /** 3072e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3073e5dfcd27SRobin Chen */ 3074e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3075e5dfcd27SRobin Chen /** 3076592a6318SAnthony Koo * Definition of a DMUB_CMD__PLAT_54186_WA command. 3077592a6318SAnthony Koo */ 3078bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3079592a6318SAnthony Koo /** 3080592a6318SAnthony Koo * Definition of a DMUB_CMD__MALL command. 3081592a6318SAnthony Koo */ 308252f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall mall; 3083b04cb192SNicholas Kazlauskas /** 3084ac2e555eSAurabindo Pillai * Definition of a DMUB_CMD__CAB command. 3085ac2e555eSAurabindo Pillai */ 3086ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss cab; 308785f4bc0cSAlvin Lee 308885f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 308985f4bc0cSAlvin Lee 3090ac2e555eSAurabindo Pillai /** 3091b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3092b04cb192SNicholas Kazlauskas */ 3093b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3094b04cb192SNicholas Kazlauskas 3095b04cb192SNicholas Kazlauskas /** 3096b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3097b04cb192SNicholas Kazlauskas */ 3098b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3099b04cb192SNicholas Kazlauskas 3100b04cb192SNicholas Kazlauskas /** 3101b04cb192SNicholas Kazlauskas * Definition of DMUB_CMD__PANEL_CNTL commands. 3102b04cb192SNicholas Kazlauskas */ 3103b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl panel_cntl; 31041a595f28SAnthony Koo /** 31051a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command. 31061a595f28SAnthony Koo */ 3107e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 31081a595f28SAnthony Koo 31091a595f28SAnthony Koo /** 31101a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 31111a595f28SAnthony Koo */ 3112e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 31131a595f28SAnthony Koo 31141a595f28SAnthony Koo /** 31151a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 31161a595f28SAnthony Koo */ 3117e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level abm_set_level; 31181a595f28SAnthony Koo 31191a595f28SAnthony Koo /** 31201a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 31211a595f28SAnthony Koo */ 3122e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 31231a595f28SAnthony Koo 31241a595f28SAnthony Koo /** 31251a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 31261a595f28SAnthony Koo */ 3127e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 31281a595f28SAnthony Koo 31291a595f28SAnthony Koo /** 31301a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 31311a595f28SAnthony Koo */ 313216012806SWyatt Wood struct dmub_rb_cmd_abm_init_config abm_init_config; 31331a595f28SAnthony Koo 31341a595f28SAnthony Koo /** 3135b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command. 3136b629a824SEric Yang */ 3137b629a824SEric Yang struct dmub_rb_cmd_abm_pause abm_pause; 3138b629a824SEric Yang 3139b629a824SEric Yang /** 31401a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 31411a595f28SAnthony Koo */ 3142d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access dp_aux_access; 31431a595f28SAnthony Koo 31441a595f28SAnthony Koo /** 3145592a6318SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3146592a6318SAnthony Koo */ 3147592a6318SAnthony Koo struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3148592a6318SAnthony Koo 3149592a6318SAnthony Koo /** 3150592a6318SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 31511a595f28SAnthony Koo */ 315234ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3153592a6318SAnthony Koo struct dmub_rb_cmd_drr_update drr_update; 315400fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 315500fa7f03SRodrigo Siqueira 31561a595f28SAnthony Koo /** 31571a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 31581a595f28SAnthony Koo */ 31591a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control lvtma_control; 3160021eaef8SAnthony Koo /** 316141f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 316241f91315SNicholas Kazlauskas */ 316341f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 316441f91315SNicholas Kazlauskas /** 316576724b76SJimmy Kizito * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 316676724b76SJimmy Kizito */ 316776724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 316876724b76SJimmy Kizito /** 316971af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 317071af9d46SMeenakshikumar Somasundaram */ 317171af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access set_config_access; 317271af9d46SMeenakshikumar Somasundaram /** 3173139a3311SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3174139a3311SMeenakshikumar Somasundaram */ 3175139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3176139a3311SMeenakshikumar Somasundaram /** 3177021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command. 3178021eaef8SAnthony Koo */ 3179021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea edid_cea; 3180c595fb05SWenjing Liu /** 3181c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3182c595fb05SWenjing Liu */ 3183c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3184ea5a4db9SAnthony Koo 3185ea5a4db9SAnthony Koo /** 3186ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3187ea5a4db9SAnthony Koo */ 3188ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state query_hpd; 31897c008829SNicholas Kazlauskas }; 31907c008829SNicholas Kazlauskas 3191592a6318SAnthony Koo /** 3192592a6318SAnthony Koo * union dmub_rb_out_cmd - Outbox command 3193592a6318SAnthony Koo */ 3194d9beecfcSAnthony Koo union dmub_rb_out_cmd { 3195592a6318SAnthony Koo /** 3196592a6318SAnthony Koo * Parameters common to every command. 3197592a6318SAnthony Koo */ 3198d9beecfcSAnthony Koo struct dmub_rb_cmd_common cmd_common; 3199592a6318SAnthony Koo /** 3200592a6318SAnthony Koo * AUX reply command. 3201592a6318SAnthony Koo */ 3202d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3203592a6318SAnthony Koo /** 3204592a6318SAnthony Koo * HPD notify command. 3205592a6318SAnthony Koo */ 3206d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 320771af9d46SMeenakshikumar Somasundaram /** 320871af9d46SMeenakshikumar Somasundaram * SET_CONFIG reply command. 320971af9d46SMeenakshikumar Somasundaram */ 321071af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3211d9beecfcSAnthony Koo }; 32127c008829SNicholas Kazlauskas #pragma pack(pop) 32137c008829SNicholas Kazlauskas 321484034ad4SAnthony Koo 321584034ad4SAnthony Koo //============================================================================== 321684034ad4SAnthony Koo //</DMUB_CMD>=================================================================== 321784034ad4SAnthony Koo //============================================================================== 321884034ad4SAnthony Koo //< DMUB_RB>==================================================================== 321984034ad4SAnthony Koo //============================================================================== 322084034ad4SAnthony Koo 322184034ad4SAnthony Koo #if defined(__cplusplus) 322284034ad4SAnthony Koo extern "C" { 322384034ad4SAnthony Koo #endif 322484034ad4SAnthony Koo 3225592a6318SAnthony Koo /** 3226592a6318SAnthony Koo * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3227592a6318SAnthony Koo */ 322884034ad4SAnthony Koo struct dmub_rb_init_params { 3229592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 3230592a6318SAnthony Koo void *base_address; /**< CPU base address for ring's data */ 3231592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3232592a6318SAnthony Koo uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3233592a6318SAnthony Koo uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 323484034ad4SAnthony Koo }; 323584034ad4SAnthony Koo 3236592a6318SAnthony Koo /** 3237592a6318SAnthony Koo * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3238592a6318SAnthony Koo */ 323984034ad4SAnthony Koo struct dmub_rb { 3240592a6318SAnthony Koo void *base_address; /**< CPU address for the ring's data */ 3241592a6318SAnthony Koo uint32_t rptr; /**< Read pointer for consumer in bytes */ 3242592a6318SAnthony Koo uint32_t wrpt; /**< Write pointer for producer in bytes */ 3243592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */ 324484034ad4SAnthony Koo 3245592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */ 3246592a6318SAnthony Koo void *dmub; /**< Pointer to the DMUB interface */ 324784034ad4SAnthony Koo }; 324884034ad4SAnthony Koo 3249592a6318SAnthony Koo /** 3250592a6318SAnthony Koo * @brief Checks if the ringbuffer is empty. 3251592a6318SAnthony Koo * 3252592a6318SAnthony Koo * @param rb DMUB Ringbuffer 3253592a6318SAnthony Koo * @return true if empty 3254592a6318SAnthony Koo * @return false otherwise 3255592a6318SAnthony Koo */ 325684034ad4SAnthony Koo static inline bool dmub_rb_empty(struct dmub_rb *rb) 325784034ad4SAnthony Koo { 325884034ad4SAnthony Koo return (rb->wrpt == rb->rptr); 325984034ad4SAnthony Koo } 326084034ad4SAnthony Koo 3261592a6318SAnthony Koo /** 3262592a6318SAnthony Koo * @brief Checks if the ringbuffer is full 3263592a6318SAnthony Koo * 3264592a6318SAnthony Koo * @param rb DMUB Ringbuffer 3265592a6318SAnthony Koo * @return true if full 3266592a6318SAnthony Koo * @return false otherwise 3267592a6318SAnthony Koo */ 326884034ad4SAnthony Koo static inline bool dmub_rb_full(struct dmub_rb *rb) 326984034ad4SAnthony Koo { 327084034ad4SAnthony Koo uint32_t data_count; 327184034ad4SAnthony Koo 327284034ad4SAnthony Koo if (rb->wrpt >= rb->rptr) 327384034ad4SAnthony Koo data_count = rb->wrpt - rb->rptr; 327484034ad4SAnthony Koo else 327584034ad4SAnthony Koo data_count = rb->capacity - (rb->rptr - rb->wrpt); 327684034ad4SAnthony Koo 327784034ad4SAnthony Koo return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 327884034ad4SAnthony Koo } 327984034ad4SAnthony Koo 3280592a6318SAnthony Koo /** 3281592a6318SAnthony Koo * @brief Pushes a command into the ringbuffer 3282592a6318SAnthony Koo * 3283592a6318SAnthony Koo * @param rb DMUB ringbuffer 3284592a6318SAnthony Koo * @param cmd The command to push 3285592a6318SAnthony Koo * @return true if the ringbuffer was not full 3286592a6318SAnthony Koo * @return false otherwise 3287592a6318SAnthony Koo */ 328884034ad4SAnthony Koo static inline bool dmub_rb_push_front(struct dmub_rb *rb, 328984034ad4SAnthony Koo const union dmub_rb_cmd *cmd) 329084034ad4SAnthony Koo { 32913f232a0fSAnthony Koo uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 32923a9d5b0bSAnthony Koo const uint64_t *src = (const uint64_t *)cmd; 32933a9d5b0bSAnthony Koo uint8_t i; 329484034ad4SAnthony Koo 329584034ad4SAnthony Koo if (dmub_rb_full(rb)) 329684034ad4SAnthony Koo return false; 329784034ad4SAnthony Koo 329884034ad4SAnthony Koo // copying data 32993a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 33003a9d5b0bSAnthony Koo *dst++ = *src++; 330184034ad4SAnthony Koo 330284034ad4SAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 330384034ad4SAnthony Koo 330484034ad4SAnthony Koo if (rb->wrpt >= rb->capacity) 330584034ad4SAnthony Koo rb->wrpt %= rb->capacity; 330684034ad4SAnthony Koo 330784034ad4SAnthony Koo return true; 330884034ad4SAnthony Koo } 330984034ad4SAnthony Koo 3310592a6318SAnthony Koo /** 3311592a6318SAnthony Koo * @brief Pushes a command into the DMUB outbox ringbuffer 3312592a6318SAnthony Koo * 3313592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 3314592a6318SAnthony Koo * @param cmd Outbox command 3315592a6318SAnthony Koo * @return true if not full 3316592a6318SAnthony Koo * @return false otherwise 3317592a6318SAnthony Koo */ 3318d9beecfcSAnthony Koo static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3319d9beecfcSAnthony Koo const union dmub_rb_out_cmd *cmd) 3320d9beecfcSAnthony Koo { 3321d9beecfcSAnthony Koo uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3322d459b79bSAnthony Koo const uint8_t *src = (const uint8_t *)cmd; 3323d9beecfcSAnthony Koo 3324d9beecfcSAnthony Koo if (dmub_rb_full(rb)) 3325d9beecfcSAnthony Koo return false; 3326d9beecfcSAnthony Koo 3327d9beecfcSAnthony Koo dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3328d9beecfcSAnthony Koo 3329d9beecfcSAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE; 3330d9beecfcSAnthony Koo 3331d9beecfcSAnthony Koo if (rb->wrpt >= rb->capacity) 3332d9beecfcSAnthony Koo rb->wrpt %= rb->capacity; 3333d9beecfcSAnthony Koo 3334d9beecfcSAnthony Koo return true; 3335d9beecfcSAnthony Koo } 3336d9beecfcSAnthony Koo 3337592a6318SAnthony Koo /** 3338592a6318SAnthony Koo * @brief Returns the next unprocessed command in the ringbuffer. 3339592a6318SAnthony Koo * 3340592a6318SAnthony Koo * @param rb DMUB ringbuffer 3341592a6318SAnthony Koo * @param cmd The command to return 3342592a6318SAnthony Koo * @return true if not empty 3343592a6318SAnthony Koo * @return false otherwise 3344592a6318SAnthony Koo */ 334584034ad4SAnthony Koo static inline bool dmub_rb_front(struct dmub_rb *rb, 334634ba432cSAnthony Koo union dmub_rb_cmd **cmd) 334784034ad4SAnthony Koo { 334834ba432cSAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 334984034ad4SAnthony Koo 335084034ad4SAnthony Koo if (dmub_rb_empty(rb)) 335184034ad4SAnthony Koo return false; 335284034ad4SAnthony Koo 335334ba432cSAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 335484034ad4SAnthony Koo 335584034ad4SAnthony Koo return true; 335684034ad4SAnthony Koo } 335784034ad4SAnthony Koo 3358592a6318SAnthony Koo /** 33590b51e7e8SAnthony Koo * @brief Determines the next ringbuffer offset. 33600b51e7e8SAnthony Koo * 33610b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 33620b51e7e8SAnthony Koo * @param num_cmds Number of commands 33630b51e7e8SAnthony Koo * @param next_rptr The next offset in the ringbuffer 33640b51e7e8SAnthony Koo */ 33650b51e7e8SAnthony Koo static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 33660b51e7e8SAnthony Koo uint32_t num_cmds, 33670b51e7e8SAnthony Koo uint32_t *next_rptr) 33680b51e7e8SAnthony Koo { 33690b51e7e8SAnthony Koo *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 33700b51e7e8SAnthony Koo 33710b51e7e8SAnthony Koo if (*next_rptr >= rb->capacity) 33720b51e7e8SAnthony Koo *next_rptr %= rb->capacity; 33730b51e7e8SAnthony Koo } 33740b51e7e8SAnthony Koo 33750b51e7e8SAnthony Koo /** 33760b51e7e8SAnthony Koo * @brief Returns a pointer to a command in the inbox. 33770b51e7e8SAnthony Koo * 33780b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer 33790b51e7e8SAnthony Koo * @param cmd The inbox command to return 33800b51e7e8SAnthony Koo * @param rptr The ringbuffer offset 33810b51e7e8SAnthony Koo * @return true if not empty 33820b51e7e8SAnthony Koo * @return false otherwise 33830b51e7e8SAnthony Koo */ 33840b51e7e8SAnthony Koo static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 33850b51e7e8SAnthony Koo union dmub_rb_cmd **cmd, 33860b51e7e8SAnthony Koo uint32_t rptr) 33870b51e7e8SAnthony Koo { 33880b51e7e8SAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 33890b51e7e8SAnthony Koo 33900b51e7e8SAnthony Koo if (dmub_rb_empty(rb)) 33910b51e7e8SAnthony Koo return false; 33920b51e7e8SAnthony Koo 33930b51e7e8SAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd; 33940b51e7e8SAnthony Koo 33950b51e7e8SAnthony Koo return true; 33960b51e7e8SAnthony Koo } 33970b51e7e8SAnthony Koo 33980b51e7e8SAnthony Koo /** 3399592a6318SAnthony Koo * @brief Returns the next unprocessed command in the outbox. 3400592a6318SAnthony Koo * 3401592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer 3402592a6318SAnthony Koo * @param cmd The outbox command to return 3403592a6318SAnthony Koo * @return true if not empty 3404592a6318SAnthony Koo * @return false otherwise 3405592a6318SAnthony Koo */ 3406d9beecfcSAnthony Koo static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3407d9beecfcSAnthony Koo union dmub_rb_out_cmd *cmd) 3408d9beecfcSAnthony Koo { 34093f232a0fSAnthony Koo const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 34103a9d5b0bSAnthony Koo uint64_t *dst = (uint64_t *)cmd; 34113a9d5b0bSAnthony Koo uint8_t i; 3412d9beecfcSAnthony Koo 3413d9beecfcSAnthony Koo if (dmub_rb_empty(rb)) 3414d9beecfcSAnthony Koo return false; 3415d9beecfcSAnthony Koo 3416d9beecfcSAnthony Koo // copying data 34173a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 34183a9d5b0bSAnthony Koo *dst++ = *src++; 3419d9beecfcSAnthony Koo 3420d9beecfcSAnthony Koo return true; 3421d9beecfcSAnthony Koo } 3422d9beecfcSAnthony Koo 3423592a6318SAnthony Koo /** 3424592a6318SAnthony Koo * @brief Removes the front entry in the ringbuffer. 3425592a6318SAnthony Koo * 3426592a6318SAnthony Koo * @param rb DMUB ringbuffer 3427592a6318SAnthony Koo * @return true if the command was removed 3428592a6318SAnthony Koo * @return false if there were no commands 3429592a6318SAnthony Koo */ 343084034ad4SAnthony Koo static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 343184034ad4SAnthony Koo { 343284034ad4SAnthony Koo if (dmub_rb_empty(rb)) 343384034ad4SAnthony Koo return false; 343484034ad4SAnthony Koo 343584034ad4SAnthony Koo rb->rptr += DMUB_RB_CMD_SIZE; 343684034ad4SAnthony Koo 343784034ad4SAnthony Koo if (rb->rptr >= rb->capacity) 343884034ad4SAnthony Koo rb->rptr %= rb->capacity; 343984034ad4SAnthony Koo 344084034ad4SAnthony Koo return true; 344184034ad4SAnthony Koo } 344284034ad4SAnthony Koo 3443592a6318SAnthony Koo /** 3444592a6318SAnthony Koo * @brief Flushes commands in the ringbuffer to framebuffer memory. 3445592a6318SAnthony Koo * 3446592a6318SAnthony Koo * Avoids a race condition where DMCUB accesses memory while 3447592a6318SAnthony Koo * there are still writes in flight to framebuffer. 3448592a6318SAnthony Koo * 3449592a6318SAnthony Koo * @param rb DMUB ringbuffer 3450592a6318SAnthony Koo */ 345184034ad4SAnthony Koo static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 345284034ad4SAnthony Koo { 345384034ad4SAnthony Koo uint32_t rptr = rb->rptr; 345484034ad4SAnthony Koo uint32_t wptr = rb->wrpt; 345584034ad4SAnthony Koo 345684034ad4SAnthony Koo while (rptr != wptr) { 34577da7b02eSAashish Sharma uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 34583a9d5b0bSAnthony Koo uint8_t i; 345984034ad4SAnthony Koo 346023da6e0fSMaíra Canal /* Don't remove this. 346123da6e0fSMaíra Canal * The contents need to actually be read from the ring buffer 346223da6e0fSMaíra Canal * for this function to be effective. 346323da6e0fSMaíra Canal */ 34643a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 34657da7b02eSAashish Sharma (void)READ_ONCE(*data++); 346684034ad4SAnthony Koo 346784034ad4SAnthony Koo rptr += DMUB_RB_CMD_SIZE; 346884034ad4SAnthony Koo if (rptr >= rb->capacity) 346984034ad4SAnthony Koo rptr %= rb->capacity; 347084034ad4SAnthony Koo } 347184034ad4SAnthony Koo } 347284034ad4SAnthony Koo 3473592a6318SAnthony Koo /** 3474592a6318SAnthony Koo * @brief Initializes a DMCUB ringbuffer 3475592a6318SAnthony Koo * 3476592a6318SAnthony Koo * @param rb DMUB ringbuffer 3477592a6318SAnthony Koo * @param init_params initial configuration for the ringbuffer 3478592a6318SAnthony Koo */ 347984034ad4SAnthony Koo static inline void dmub_rb_init(struct dmub_rb *rb, 348084034ad4SAnthony Koo struct dmub_rb_init_params *init_params) 348184034ad4SAnthony Koo { 348284034ad4SAnthony Koo rb->base_address = init_params->base_address; 348384034ad4SAnthony Koo rb->capacity = init_params->capacity; 348484034ad4SAnthony Koo rb->rptr = init_params->read_ptr; 348584034ad4SAnthony Koo rb->wrpt = init_params->write_ptr; 348684034ad4SAnthony Koo } 348784034ad4SAnthony Koo 3488592a6318SAnthony Koo /** 3489592a6318SAnthony Koo * @brief Copies output data from in/out commands into the given command. 3490592a6318SAnthony Koo * 3491592a6318SAnthony Koo * @param rb DMUB ringbuffer 3492592a6318SAnthony Koo * @param cmd Command to copy data into 3493592a6318SAnthony Koo */ 349434ba432cSAnthony Koo static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 349534ba432cSAnthony Koo union dmub_rb_cmd *cmd) 349634ba432cSAnthony Koo { 349734ba432cSAnthony Koo // Copy rb entry back into command 349834ba432cSAnthony Koo uint8_t *rd_ptr = (rb->rptr == 0) ? 349934ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 350034ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 350134ba432cSAnthony Koo 350234ba432cSAnthony Koo dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 350334ba432cSAnthony Koo } 350434ba432cSAnthony Koo 350584034ad4SAnthony Koo #if defined(__cplusplus) 350684034ad4SAnthony Koo } 350784034ad4SAnthony Koo #endif 350884034ad4SAnthony Koo 350984034ad4SAnthony Koo //============================================================================== 351084034ad4SAnthony Koo //</DMUB_RB>==================================================================== 351184034ad4SAnthony Koo //============================================================================== 351284034ad4SAnthony Koo 35137c008829SNicholas Kazlauskas #endif /* _DMUB_CMD_H_ */ 3514