1bc33f5e5SWenjing Liu /*
2bc33f5e5SWenjing Liu  * Copyright 2022 Advanced Micro Devices, Inc.
3bc33f5e5SWenjing Liu  *
4bc33f5e5SWenjing Liu  * Permission is hereby granted, free of charge, to any person obtaining a
5bc33f5e5SWenjing Liu  * copy of this software and associated documentation files (the "Software"),
6bc33f5e5SWenjing Liu  * to deal in the Software without restriction, including without limitation
7bc33f5e5SWenjing Liu  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8bc33f5e5SWenjing Liu  * and/or sell copies of the Software, and to permit persons to whom the
9bc33f5e5SWenjing Liu  * Software is furnished to do so, subject to the following conditions:
10bc33f5e5SWenjing Liu  *
11bc33f5e5SWenjing Liu  * The above copyright notice and this permission notice shall be included in
12bc33f5e5SWenjing Liu  * all copies or substantial portions of the Software.
13bc33f5e5SWenjing Liu  *
14bc33f5e5SWenjing Liu  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15bc33f5e5SWenjing Liu  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16bc33f5e5SWenjing Liu  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17bc33f5e5SWenjing Liu  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18bc33f5e5SWenjing Liu  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19bc33f5e5SWenjing Liu  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20bc33f5e5SWenjing Liu  * OTHER DEALINGS IN THE SOFTWARE.
21bc33f5e5SWenjing Liu  *
22bc33f5e5SWenjing Liu  * Authors: AMD
23bc33f5e5SWenjing Liu  *
24bc33f5e5SWenjing Liu  */
25bc33f5e5SWenjing Liu 
26bc33f5e5SWenjing Liu /* FILE POLICY AND INTENDED USAGE:
27bc33f5e5SWenjing Liu  *
28bc33f5e5SWenjing Liu  */
29bc33f5e5SWenjing Liu #include "link_dp_training_auxless.h"
30bc33f5e5SWenjing Liu #include "link_dp_phy.h"
31bc33f5e5SWenjing Liu #define DC_LOGGER \
32bc33f5e5SWenjing Liu 	link->ctx->logger
dp_perform_link_training_skip_aux(struct dc_link * link,const struct link_resource * link_res,const struct dc_link_settings * link_setting)33*202a3816SWenjing Liu bool dp_perform_link_training_skip_aux(
34bc33f5e5SWenjing Liu 	struct dc_link *link,
35bc33f5e5SWenjing Liu 	const struct link_resource *link_res,
36bc33f5e5SWenjing Liu 	const struct dc_link_settings *link_setting)
37bc33f5e5SWenjing Liu {
38bc33f5e5SWenjing Liu 	struct link_training_settings lt_settings = {0};
39bc33f5e5SWenjing Liu 
40bc33f5e5SWenjing Liu 	dp_decide_training_settings(
41bc33f5e5SWenjing Liu 			link,
42bc33f5e5SWenjing Liu 			link_setting,
43bc33f5e5SWenjing Liu 			&lt_settings);
44bc33f5e5SWenjing Liu 	override_training_settings(
45bc33f5e5SWenjing Liu 			link,
46bc33f5e5SWenjing Liu 			&link->preferred_training_settings,
47bc33f5e5SWenjing Liu 			&lt_settings);
48bc33f5e5SWenjing Liu 
49bc33f5e5SWenjing Liu 	/* 1. Perform_clock_recovery_sequence. */
50bc33f5e5SWenjing Liu 
51bc33f5e5SWenjing Liu 	/* transmit training pattern for clock recovery */
52bc33f5e5SWenjing Liu 	dp_set_hw_training_pattern(link, link_res, lt_settings.pattern_for_cr, DPRX);
53bc33f5e5SWenjing Liu 
54bc33f5e5SWenjing Liu 	/* call HWSS to set lane settings*/
55bc33f5e5SWenjing Liu 	dp_set_hw_lane_settings(link, link_res, &lt_settings, DPRX);
56bc33f5e5SWenjing Liu 
57bc33f5e5SWenjing Liu 	/* wait receiver to lock-on*/
58bc33f5e5SWenjing Liu 	dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
59bc33f5e5SWenjing Liu 
60bc33f5e5SWenjing Liu 	/* 2. Perform_channel_equalization_sequence. */
61bc33f5e5SWenjing Liu 
62bc33f5e5SWenjing Liu 	/* transmit training pattern for channel equalization. */
63bc33f5e5SWenjing Liu 	dp_set_hw_training_pattern(link, link_res, lt_settings.pattern_for_eq, DPRX);
64bc33f5e5SWenjing Liu 
65bc33f5e5SWenjing Liu 	/* call HWSS to set lane settings*/
66bc33f5e5SWenjing Liu 	dp_set_hw_lane_settings(link, link_res, &lt_settings, DPRX);
67bc33f5e5SWenjing Liu 
68bc33f5e5SWenjing Liu 	/* wait receiver to lock-on. */
69bc33f5e5SWenjing Liu 	dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
70bc33f5e5SWenjing Liu 
71bc33f5e5SWenjing Liu 	/* 3. Perform_link_training_int. */
72bc33f5e5SWenjing Liu 
73bc33f5e5SWenjing Liu 	/* Mainlink output idle pattern. */
74bc33f5e5SWenjing Liu 	dp_set_hw_test_pattern(link, link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
75bc33f5e5SWenjing Liu 
76bc33f5e5SWenjing Liu 	dp_log_training_result(link, &lt_settings, LINK_TRAINING_SUCCESS);
77bc33f5e5SWenjing Liu 
78bc33f5e5SWenjing Liu 	return true;
79bc33f5e5SWenjing Liu }
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