1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file implements dp specific link capability retrieval sequence. It is 28 * responsible for retrieving, parsing, overriding, deciding capability obtained 29 * from dp link. Link capability consists of encoders, DPRXs, cables, retimers, 30 * usb and all other possible backend capabilities. Other components should 31 * include this header file in order to access link capability. Accessing link 32 * capability by dereferencing dc_link outside dp_link_capability is not a 33 * recommended method as it makes the component dependent on the underlying data 34 * structure used to represent link capability instead of function interfaces. 35 */ 36 37 #include "link_dp_capability.h" 38 #include "link_ddc.h" 39 #include "link_dpcd.h" 40 #include "link_dp_dpia.h" 41 #include "link_dp_phy.h" 42 #include "link_edp_panel_control.h" 43 #include "link_dp_irq_handler.h" 44 #include "link/accessories/link_dp_trace.h" 45 #include "link/link_detection.h" 46 #include "link/link_validation.h" 47 #include "link_dp_training.h" 48 #include "atomfirmware.h" 49 #include "resource.h" 50 #include "link_enc_cfg.h" 51 #include "dc_dmub_srv.h" 52 #include "gpio_service_interface.h" 53 54 #define DC_LOGGER \ 55 link->ctx->logger 56 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ 57 58 #ifndef MAX 59 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 60 #endif 61 #ifndef MIN 62 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 63 #endif 64 65 struct dp_lt_fallback_entry { 66 enum dc_lane_count lane_count; 67 enum dc_link_rate link_rate; 68 }; 69 70 static const struct dp_lt_fallback_entry dp_lt_fallbacks[] = { 71 /* This link training fallback array is ordered by 72 * link bandwidth from highest to lowest. 73 * DP specs makes it a normative policy to always 74 * choose the next highest link bandwidth during 75 * link training fallback. 76 */ 77 {LANE_COUNT_FOUR, LINK_RATE_UHBR20}, 78 {LANE_COUNT_FOUR, LINK_RATE_UHBR13_5}, 79 {LANE_COUNT_TWO, LINK_RATE_UHBR20}, 80 {LANE_COUNT_FOUR, LINK_RATE_UHBR10}, 81 {LANE_COUNT_TWO, LINK_RATE_UHBR13_5}, 82 {LANE_COUNT_FOUR, LINK_RATE_HIGH3}, 83 {LANE_COUNT_ONE, LINK_RATE_UHBR20}, 84 {LANE_COUNT_TWO, LINK_RATE_UHBR10}, 85 {LANE_COUNT_FOUR, LINK_RATE_HIGH2}, 86 {LANE_COUNT_ONE, LINK_RATE_UHBR13_5}, 87 {LANE_COUNT_TWO, LINK_RATE_HIGH3}, 88 {LANE_COUNT_ONE, LINK_RATE_UHBR10}, 89 {LANE_COUNT_TWO, LINK_RATE_HIGH2}, 90 {LANE_COUNT_FOUR, LINK_RATE_HIGH}, 91 {LANE_COUNT_ONE, LINK_RATE_HIGH3}, 92 {LANE_COUNT_FOUR, LINK_RATE_LOW}, 93 {LANE_COUNT_ONE, LINK_RATE_HIGH2}, 94 {LANE_COUNT_TWO, LINK_RATE_HIGH}, 95 {LANE_COUNT_TWO, LINK_RATE_LOW}, 96 {LANE_COUNT_ONE, LINK_RATE_HIGH}, 97 {LANE_COUNT_ONE, LINK_RATE_LOW}, 98 }; 99 100 static const struct dc_link_settings fail_safe_link_settings = { 101 .lane_count = LANE_COUNT_ONE, 102 .link_rate = LINK_RATE_LOW, 103 .link_spread = LINK_SPREAD_DISABLED, 104 }; 105 106 bool is_dp_active_dongle(const struct dc_link *link) 107 { 108 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) && 109 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER); 110 } 111 112 bool is_dp_branch_device(const struct dc_link *link) 113 { 114 return link->dpcd_caps.is_branch_dev; 115 } 116 117 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc) 118 { 119 switch (bpc) { 120 case DOWN_STREAM_MAX_8BPC: 121 return 8; 122 case DOWN_STREAM_MAX_10BPC: 123 return 10; 124 case DOWN_STREAM_MAX_12BPC: 125 return 12; 126 case DOWN_STREAM_MAX_16BPC: 127 return 16; 128 default: 129 break; 130 } 131 132 return -1; 133 } 134 135 uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count) 136 { 137 switch (lttpr_repeater_count) { 138 case 0x80: // 1 lttpr repeater 139 return 1; 140 case 0x40: // 2 lttpr repeaters 141 return 2; 142 case 0x20: // 3 lttpr repeaters 143 return 3; 144 case 0x10: // 4 lttpr repeaters 145 return 4; 146 case 0x08: // 5 lttpr repeaters 147 return 5; 148 case 0x04: // 6 lttpr repeaters 149 return 6; 150 case 0x02: // 7 lttpr repeaters 151 return 7; 152 case 0x01: // 8 lttpr repeaters 153 return 8; 154 default: 155 break; 156 } 157 return 0; // invalid value 158 } 159 160 uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) 161 { 162 switch (bw) { 163 case 0b001: 164 return 9000000; 165 case 0b010: 166 return 18000000; 167 case 0b011: 168 return 24000000; 169 case 0b100: 170 return 32000000; 171 case 0b101: 172 return 40000000; 173 case 0b110: 174 return 48000000; 175 } 176 177 return 0; 178 } 179 180 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz) 181 { 182 enum dc_link_rate link_rate; 183 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation. 184 switch (link_rate_in_khz) { 185 case 1620000: 186 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane 187 break; 188 case 2160000: 189 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane 190 break; 191 case 2430000: 192 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane 193 break; 194 case 2700000: 195 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane 196 break; 197 case 3240000: 198 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane 199 break; 200 case 4320000: 201 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane 202 break; 203 case 5400000: 204 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2)- 5.40 Gbps/Lane 205 break; 206 case 6750000: 207 link_rate = LINK_RATE_RATE_8; // Rate_8 - 6.75 Gbps/Lane 208 break; 209 case 8100000: 210 link_rate = LINK_RATE_HIGH3; // Rate_9 (HBR3)- 8.10 Gbps/Lane 211 break; 212 default: 213 link_rate = LINK_RATE_UNKNOWN; 214 break; 215 } 216 return link_rate; 217 } 218 219 static union dp_cable_id intersect_cable_id( 220 union dp_cable_id *a, union dp_cable_id *b) 221 { 222 union dp_cable_id out; 223 224 out.bits.UHBR10_20_CAPABILITY = MIN(a->bits.UHBR10_20_CAPABILITY, 225 b->bits.UHBR10_20_CAPABILITY); 226 out.bits.UHBR13_5_CAPABILITY = MIN(a->bits.UHBR13_5_CAPABILITY, 227 b->bits.UHBR13_5_CAPABILITY); 228 out.bits.CABLE_TYPE = MAX(a->bits.CABLE_TYPE, b->bits.CABLE_TYPE); 229 230 return out; 231 } 232 233 /* 234 * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw. 235 */ 236 static uint32_t intersect_frl_link_bw_support( 237 const uint32_t max_supported_frl_bw_in_kbps, 238 const union hdmi_encoded_link_bw hdmi_encoded_link_bw) 239 { 240 uint32_t supported_bw_in_kbps = max_supported_frl_bw_in_kbps; 241 242 // HDMI_ENCODED_LINK_BW bits are only valid if HDMI Link Configuration bit is 1 (FRL mode) 243 if (hdmi_encoded_link_bw.bits.FRL_MODE) { 244 if (hdmi_encoded_link_bw.bits.BW_48Gbps) 245 supported_bw_in_kbps = 48000000; 246 else if (hdmi_encoded_link_bw.bits.BW_40Gbps) 247 supported_bw_in_kbps = 40000000; 248 else if (hdmi_encoded_link_bw.bits.BW_32Gbps) 249 supported_bw_in_kbps = 32000000; 250 else if (hdmi_encoded_link_bw.bits.BW_24Gbps) 251 supported_bw_in_kbps = 24000000; 252 else if (hdmi_encoded_link_bw.bits.BW_18Gbps) 253 supported_bw_in_kbps = 18000000; 254 else if (hdmi_encoded_link_bw.bits.BW_9Gbps) 255 supported_bw_in_kbps = 9000000; 256 } 257 258 return supported_bw_in_kbps; 259 } 260 261 static enum clock_source_id get_clock_source_id(struct dc_link *link) 262 { 263 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED; 264 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source; 265 266 if (dp_cs != NULL) { 267 dp_cs_id = dp_cs->id; 268 } else { 269 /* 270 * dp clock source is not initialized for some reason. 271 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used 272 */ 273 ASSERT(dp_cs); 274 } 275 276 return dp_cs_id; 277 } 278 279 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data, 280 int length) 281 { 282 int retry = 0; 283 284 if (!link->dpcd_caps.dpcd_rev.raw) { 285 do { 286 dpcd_write_rx_power_ctrl(link, true); 287 core_link_read_dpcd(link, DP_DPCD_REV, 288 dpcd_data, length); 289 link->dpcd_caps.dpcd_rev.raw = dpcd_data[ 290 DP_DPCD_REV - 291 DP_DPCD_REV]; 292 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw); 293 } 294 295 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) { 296 switch (link->dpcd_caps.branch_dev_id) { 297 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down 298 * all internal circuits including AUX communication preventing 299 * reading DPCD table and EDID (spec violation). 300 * Encoder will skip DP RX power down on disable_output to 301 * keep receiver powered all the time.*/ 302 case DP_BRANCH_DEVICE_ID_0010FA: 303 case DP_BRANCH_DEVICE_ID_0080E1: 304 case DP_BRANCH_DEVICE_ID_00E04C: 305 link->wa_flags.dp_keep_receiver_powered = true; 306 break; 307 308 /* TODO: May need work around for other dongles. */ 309 default: 310 link->wa_flags.dp_keep_receiver_powered = false; 311 break; 312 } 313 } else 314 link->wa_flags.dp_keep_receiver_powered = false; 315 } 316 317 bool dp_is_fec_supported(const struct dc_link *link) 318 { 319 /* TODO - use asic cap instead of link_enc->features 320 * we no longer know which link enc to use for this link before commit 321 */ 322 struct link_encoder *link_enc = NULL; 323 324 link_enc = link_enc_cfg_get_link_enc(link); 325 ASSERT(link_enc); 326 327 return (dc_is_dp_signal(link->connector_signal) && link_enc && 328 link_enc->features.fec_supported && 329 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE); 330 } 331 332 bool dp_should_enable_fec(const struct dc_link *link) 333 { 334 bool force_disable = false; 335 336 if (link->fec_state == dc_link_fec_enabled) 337 force_disable = false; 338 else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST && 339 link->local_sink && 340 link->local_sink->edid_caps.panel_patch.disable_fec) 341 force_disable = true; 342 else if (link->connector_signal == SIGNAL_TYPE_EDP 343 && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields. 344 dsc_support.DSC_SUPPORT == false 345 || link->panel_config.dsc.disable_dsc_edp 346 || !link->dc->caps.edp_dsc_support)) 347 force_disable = true; 348 349 return !force_disable && dp_is_fec_supported(link); 350 } 351 352 bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx) 353 { 354 /* If this assert is hit then we have a link encoder dynamic management issue */ 355 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); 356 return (pipe_ctx->stream_res.hpo_dp_stream_enc && 357 pipe_ctx->link_res.hpo_dp_link_enc && 358 dc_is_dp_signal(pipe_ctx->stream->signal)); 359 } 360 361 bool dp_is_lttpr_present(struct dc_link *link) 362 { 363 return (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 && 364 link->dpcd_caps.lttpr_caps.max_lane_count > 0 && 365 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 && 366 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14); 367 } 368 369 /* in DP compliance test, DPR-120 may have 370 * a random value in its MAX_LINK_BW dpcd field. 371 * We map it to the maximum supported link rate that 372 * is smaller than MAX_LINK_BW in this case. 373 */ 374 static enum dc_link_rate get_link_rate_from_max_link_bw( 375 uint8_t max_link_bw) 376 { 377 enum dc_link_rate link_rate; 378 379 if (max_link_bw >= LINK_RATE_HIGH3) { 380 link_rate = LINK_RATE_HIGH3; 381 } else if (max_link_bw < LINK_RATE_HIGH3 382 && max_link_bw >= LINK_RATE_HIGH2) { 383 link_rate = LINK_RATE_HIGH2; 384 } else if (max_link_bw < LINK_RATE_HIGH2 385 && max_link_bw >= LINK_RATE_HIGH) { 386 link_rate = LINK_RATE_HIGH; 387 } else if (max_link_bw < LINK_RATE_HIGH 388 && max_link_bw >= LINK_RATE_LOW) { 389 link_rate = LINK_RATE_LOW; 390 } else { 391 link_rate = LINK_RATE_UNKNOWN; 392 } 393 394 return link_rate; 395 } 396 397 static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link) 398 { 399 enum dc_link_rate lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate; 400 401 if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20) 402 lttpr_max_link_rate = LINK_RATE_UHBR20; 403 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5) 404 lttpr_max_link_rate = LINK_RATE_UHBR13_5; 405 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR10) 406 lttpr_max_link_rate = LINK_RATE_UHBR10; 407 408 return lttpr_max_link_rate; 409 } 410 411 static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) 412 { 413 enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN; 414 415 if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR20) 416 cable_max_link_rate = LINK_RATE_UHBR20; 417 else if (link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY) 418 cable_max_link_rate = LINK_RATE_UHBR13_5; 419 else if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR10) 420 cable_max_link_rate = LINK_RATE_UHBR10; 421 422 return cable_max_link_rate; 423 } 424 425 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) 426 { 427 return lane_count <= LANE_COUNT_ONE; 428 } 429 430 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate) 431 { 432 return link_rate <= LINK_RATE_LOW; 433 } 434 435 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) 436 { 437 switch (lane_count) { 438 case LANE_COUNT_FOUR: 439 return LANE_COUNT_TWO; 440 case LANE_COUNT_TWO: 441 return LANE_COUNT_ONE; 442 case LANE_COUNT_ONE: 443 return LANE_COUNT_UNKNOWN; 444 default: 445 return LANE_COUNT_UNKNOWN; 446 } 447 } 448 449 static enum dc_link_rate reduce_link_rate(const struct dc_link *link, enum dc_link_rate link_rate) 450 { 451 // NEEDSWORK: provide some details about why this function never returns some of the 452 // obscure link rates such as 4.32 Gbps or 3.24 Gbps and if such behavior is intended. 453 // 454 455 switch (link_rate) { 456 case LINK_RATE_UHBR20: 457 return LINK_RATE_UHBR13_5; 458 case LINK_RATE_UHBR13_5: 459 return LINK_RATE_UHBR10; 460 case LINK_RATE_UHBR10: 461 return LINK_RATE_HIGH3; 462 case LINK_RATE_HIGH3: 463 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->debug.support_eDP1_5) 464 return LINK_RATE_RATE_8; 465 return LINK_RATE_HIGH2; 466 case LINK_RATE_RATE_8: 467 return LINK_RATE_HIGH2; 468 case LINK_RATE_HIGH2: 469 return LINK_RATE_HIGH; 470 case LINK_RATE_RATE_6: 471 case LINK_RATE_RBR2: 472 return LINK_RATE_HIGH; 473 case LINK_RATE_HIGH: 474 return LINK_RATE_LOW; 475 case LINK_RATE_RATE_3: 476 case LINK_RATE_RATE_2: 477 return LINK_RATE_LOW; 478 case LINK_RATE_LOW: 479 default: 480 return LINK_RATE_UNKNOWN; 481 } 482 } 483 484 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) 485 { 486 switch (lane_count) { 487 case LANE_COUNT_ONE: 488 return LANE_COUNT_TWO; 489 case LANE_COUNT_TWO: 490 return LANE_COUNT_FOUR; 491 default: 492 return LANE_COUNT_UNKNOWN; 493 } 494 } 495 496 static enum dc_link_rate increase_link_rate(struct dc_link *link, 497 enum dc_link_rate link_rate) 498 { 499 switch (link_rate) { 500 case LINK_RATE_LOW: 501 return LINK_RATE_HIGH; 502 case LINK_RATE_HIGH: 503 return LINK_RATE_HIGH2; 504 case LINK_RATE_HIGH2: 505 return LINK_RATE_HIGH3; 506 case LINK_RATE_HIGH3: 507 return LINK_RATE_UHBR10; 508 case LINK_RATE_UHBR10: 509 /* upto DP2.x specs UHBR13.5 is the only link rate that could be 510 * not supported by DPRX when higher link rate is supported. 511 * so we treat it as a special case for code simplicity. When we 512 * have new specs with more link rates like this, we should 513 * consider a more generic solution to handle discrete link 514 * rate capabilities. 515 */ 516 return link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 ? 517 LINK_RATE_UHBR13_5 : LINK_RATE_UHBR20; 518 case LINK_RATE_UHBR13_5: 519 return LINK_RATE_UHBR20; 520 default: 521 return LINK_RATE_UNKNOWN; 522 } 523 } 524 525 static bool decide_fallback_link_setting_max_bw_policy( 526 struct dc_link *link, 527 const struct dc_link_settings *max, 528 struct dc_link_settings *cur, 529 enum link_training_result training_result) 530 { 531 uint8_t cur_idx = 0, next_idx; 532 bool found = false; 533 534 if (training_result == LINK_TRAINING_ABORT) 535 return false; 536 537 while (cur_idx < ARRAY_SIZE(dp_lt_fallbacks)) 538 /* find current index */ 539 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count && 540 dp_lt_fallbacks[cur_idx].link_rate == cur->link_rate) 541 break; 542 else 543 cur_idx++; 544 545 next_idx = cur_idx + 1; 546 547 while (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) 548 /* find next index */ 549 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count || 550 dp_lt_fallbacks[next_idx].link_rate > max->link_rate) 551 next_idx++; 552 else if (dp_lt_fallbacks[next_idx].link_rate == LINK_RATE_UHBR13_5 && 553 link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 == 0) 554 /* upto DP2.x specs UHBR13.5 is the only link rate that 555 * could be not supported by DPRX when higher link rate 556 * is supported. so we treat it as a special case for 557 * code simplicity. When we have new specs with more 558 * link rates like this, we should consider a more 559 * generic solution to handle discrete link rate 560 * capabilities. 561 */ 562 next_idx++; 563 else 564 break; 565 566 if (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) { 567 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count; 568 cur->link_rate = dp_lt_fallbacks[next_idx].link_rate; 569 found = true; 570 } 571 572 return found; 573 } 574 575 /* 576 * function: set link rate and lane count fallback based 577 * on current link setting and last link training result 578 * return value: 579 * true - link setting could be set 580 * false - has reached minimum setting 581 * and no further fallback could be done 582 */ 583 bool decide_fallback_link_setting( 584 struct dc_link *link, 585 struct dc_link_settings *max, 586 struct dc_link_settings *cur, 587 enum link_training_result training_result) 588 { 589 if (link_dp_get_encoding_format(max) == DP_128b_132b_ENCODING || 590 link->dc->debug.force_dp2_lt_fallback_method) 591 return decide_fallback_link_setting_max_bw_policy(link, max, 592 cur, training_result); 593 594 switch (training_result) { 595 case LINK_TRAINING_CR_FAIL_LANE0: 596 case LINK_TRAINING_CR_FAIL_LANE1: 597 case LINK_TRAINING_CR_FAIL_LANE23: 598 case LINK_TRAINING_LQA_FAIL: 599 { 600 if (!reached_minimum_link_rate(cur->link_rate)) { 601 cur->link_rate = reduce_link_rate(link, cur->link_rate); 602 } else if (!reached_minimum_lane_count(cur->lane_count)) { 603 cur->link_rate = max->link_rate; 604 if (training_result == LINK_TRAINING_CR_FAIL_LANE0) 605 return false; 606 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1) 607 cur->lane_count = LANE_COUNT_ONE; 608 else if (training_result == LINK_TRAINING_CR_FAIL_LANE23) 609 cur->lane_count = LANE_COUNT_TWO; 610 else 611 cur->lane_count = reduce_lane_count(cur->lane_count); 612 } else { 613 return false; 614 } 615 break; 616 } 617 case LINK_TRAINING_EQ_FAIL_EQ: 618 case LINK_TRAINING_EQ_FAIL_CR_PARTIAL: 619 { 620 if (!reached_minimum_lane_count(cur->lane_count)) { 621 cur->lane_count = reduce_lane_count(cur->lane_count); 622 } else if (!reached_minimum_link_rate(cur->link_rate)) { 623 cur->link_rate = reduce_link_rate(link, cur->link_rate); 624 /* Reduce max link rate to avoid potential infinite loop. 625 * Needed so that any subsequent CR_FAIL fallback can't 626 * re-set the link rate higher than the link rate from 627 * the latest EQ_FAIL fallback. 628 */ 629 max->link_rate = cur->link_rate; 630 cur->lane_count = max->lane_count; 631 } else { 632 return false; 633 } 634 break; 635 } 636 case LINK_TRAINING_EQ_FAIL_CR: 637 { 638 if (!reached_minimum_link_rate(cur->link_rate)) { 639 cur->link_rate = reduce_link_rate(link, cur->link_rate); 640 /* Reduce max link rate to avoid potential infinite loop. 641 * Needed so that any subsequent CR_FAIL fallback can't 642 * re-set the link rate higher than the link rate from 643 * the latest EQ_FAIL fallback. 644 */ 645 max->link_rate = cur->link_rate; 646 cur->lane_count = max->lane_count; 647 } else { 648 return false; 649 } 650 break; 651 } 652 default: 653 return false; 654 } 655 return true; 656 } 657 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw) 658 { 659 struct dc_link_settings initial_link_setting = { 660 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0}; 661 struct dc_link_settings current_link_setting = 662 initial_link_setting; 663 uint32_t link_bw; 664 665 if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap)) 666 return false; 667 668 /* search for the minimum link setting that: 669 * 1. is supported according to the link training result 670 * 2. could support the b/w requested by the timing 671 */ 672 while (current_link_setting.link_rate <= 673 link->verified_link_cap.link_rate) { 674 link_bw = dp_link_bandwidth_kbps( 675 link, 676 ¤t_link_setting); 677 if (req_bw <= link_bw) { 678 *link_setting = current_link_setting; 679 return true; 680 } 681 682 if (current_link_setting.lane_count < 683 link->verified_link_cap.lane_count) { 684 current_link_setting.lane_count = 685 increase_lane_count( 686 current_link_setting.lane_count); 687 } else { 688 current_link_setting.link_rate = 689 increase_link_rate(link, 690 current_link_setting.link_rate); 691 current_link_setting.lane_count = 692 initial_link_setting.lane_count; 693 } 694 } 695 696 return false; 697 } 698 699 bool edp_decide_link_settings(struct dc_link *link, 700 struct dc_link_settings *link_setting, uint32_t req_bw) 701 { 702 struct dc_link_settings initial_link_setting; 703 struct dc_link_settings current_link_setting; 704 uint32_t link_bw; 705 706 /* 707 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher. 708 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h" 709 */ 710 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 || 711 link->dpcd_caps.edp_supported_link_rates_count == 0) { 712 *link_setting = link->verified_link_cap; 713 return true; 714 } 715 716 memset(&initial_link_setting, 0, sizeof(initial_link_setting)); 717 initial_link_setting.lane_count = LANE_COUNT_ONE; 718 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0]; 719 initial_link_setting.link_spread = LINK_SPREAD_DISABLED; 720 initial_link_setting.use_link_rate_set = true; 721 initial_link_setting.link_rate_set = 0; 722 current_link_setting = initial_link_setting; 723 724 /* search for the minimum link setting that: 725 * 1. is supported according to the link training result 726 * 2. could support the b/w requested by the timing 727 */ 728 while (current_link_setting.link_rate <= 729 link->verified_link_cap.link_rate) { 730 link_bw = dp_link_bandwidth_kbps( 731 link, 732 ¤t_link_setting); 733 if (req_bw <= link_bw) { 734 *link_setting = current_link_setting; 735 return true; 736 } 737 738 if (current_link_setting.lane_count < 739 link->verified_link_cap.lane_count) { 740 current_link_setting.lane_count = 741 increase_lane_count( 742 current_link_setting.lane_count); 743 } else { 744 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { 745 current_link_setting.link_rate_set++; 746 current_link_setting.link_rate = 747 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set]; 748 current_link_setting.lane_count = 749 initial_link_setting.lane_count; 750 } else 751 break; 752 } 753 } 754 return false; 755 } 756 757 bool decide_edp_link_settings_with_dsc(struct dc_link *link, 758 struct dc_link_settings *link_setting, 759 uint32_t req_bw, 760 enum dc_link_rate max_link_rate) 761 { 762 struct dc_link_settings initial_link_setting; 763 struct dc_link_settings current_link_setting; 764 uint32_t link_bw; 765 766 unsigned int policy = 0; 767 768 policy = link->panel_config.dsc.force_dsc_edp_policy; 769 if (max_link_rate == LINK_RATE_UNKNOWN) 770 max_link_rate = link->verified_link_cap.link_rate; 771 /* 772 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher. 773 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h" 774 */ 775 if ((link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 || 776 link->dpcd_caps.edp_supported_link_rates_count == 0)) { 777 /* for DSC enabled case, we search for minimum lane count */ 778 memset(&initial_link_setting, 0, sizeof(initial_link_setting)); 779 initial_link_setting.lane_count = LANE_COUNT_ONE; 780 initial_link_setting.link_rate = LINK_RATE_LOW; 781 initial_link_setting.link_spread = LINK_SPREAD_DISABLED; 782 initial_link_setting.use_link_rate_set = false; 783 initial_link_setting.link_rate_set = 0; 784 current_link_setting = initial_link_setting; 785 if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap)) 786 return false; 787 788 /* search for the minimum link setting that: 789 * 1. is supported according to the link training result 790 * 2. could support the b/w requested by the timing 791 */ 792 while (current_link_setting.link_rate <= 793 max_link_rate) { 794 link_bw = dp_link_bandwidth_kbps( 795 link, 796 ¤t_link_setting); 797 if (req_bw <= link_bw) { 798 *link_setting = current_link_setting; 799 return true; 800 } 801 if (policy) { 802 /* minimize lane */ 803 if (current_link_setting.link_rate < max_link_rate) { 804 current_link_setting.link_rate = 805 increase_link_rate(link, 806 current_link_setting.link_rate); 807 } else { 808 if (current_link_setting.lane_count < 809 link->verified_link_cap.lane_count) { 810 current_link_setting.lane_count = 811 increase_lane_count( 812 current_link_setting.lane_count); 813 current_link_setting.link_rate = initial_link_setting.link_rate; 814 } else 815 break; 816 } 817 } else { 818 /* minimize link rate */ 819 if (current_link_setting.lane_count < 820 link->verified_link_cap.lane_count) { 821 current_link_setting.lane_count = 822 increase_lane_count( 823 current_link_setting.lane_count); 824 } else { 825 current_link_setting.link_rate = 826 increase_link_rate(link, 827 current_link_setting.link_rate); 828 current_link_setting.lane_count = 829 initial_link_setting.lane_count; 830 } 831 } 832 } 833 return false; 834 } 835 836 /* if optimize edp link is supported */ 837 memset(&initial_link_setting, 0, sizeof(initial_link_setting)); 838 initial_link_setting.lane_count = LANE_COUNT_ONE; 839 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0]; 840 initial_link_setting.link_spread = LINK_SPREAD_DISABLED; 841 initial_link_setting.use_link_rate_set = true; 842 initial_link_setting.link_rate_set = 0; 843 current_link_setting = initial_link_setting; 844 845 /* search for the minimum link setting that: 846 * 1. is supported according to the link training result 847 * 2. could support the b/w requested by the timing 848 */ 849 while (current_link_setting.link_rate <= 850 max_link_rate) { 851 link_bw = dp_link_bandwidth_kbps( 852 link, 853 ¤t_link_setting); 854 if (req_bw <= link_bw) { 855 *link_setting = current_link_setting; 856 return true; 857 } 858 if (policy) { 859 /* minimize lane */ 860 if (current_link_setting.link_rate_set < 861 link->dpcd_caps.edp_supported_link_rates_count 862 && current_link_setting.link_rate < max_link_rate) { 863 current_link_setting.link_rate_set++; 864 current_link_setting.link_rate = 865 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set]; 866 } else { 867 if (current_link_setting.lane_count < link->verified_link_cap.lane_count) { 868 current_link_setting.lane_count = 869 increase_lane_count( 870 current_link_setting.lane_count); 871 current_link_setting.link_rate_set = initial_link_setting.link_rate_set; 872 current_link_setting.link_rate = 873 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set]; 874 } else 875 break; 876 } 877 } else { 878 /* minimize link rate */ 879 if (current_link_setting.lane_count < 880 link->verified_link_cap.lane_count) { 881 current_link_setting.lane_count = 882 increase_lane_count( 883 current_link_setting.lane_count); 884 } else { 885 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { 886 current_link_setting.link_rate_set++; 887 current_link_setting.link_rate = 888 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set]; 889 current_link_setting.lane_count = 890 initial_link_setting.lane_count; 891 } else 892 break; 893 } 894 } 895 } 896 return false; 897 } 898 899 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting) 900 { 901 *link_setting = link->verified_link_cap; 902 return true; 903 } 904 905 bool link_decide_link_settings(struct dc_stream_state *stream, 906 struct dc_link_settings *link_setting) 907 { 908 struct dc_link *link = stream->link; 909 uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing); 910 911 memset(link_setting, 0, sizeof(*link_setting)); 912 913 /* if preferred is specified through AMDDP, use it, if it's enough 914 * to drive the mode 915 */ 916 if (link->preferred_link_setting.lane_count != 917 LANE_COUNT_UNKNOWN && 918 link->preferred_link_setting.link_rate != 919 LINK_RATE_UNKNOWN) { 920 *link_setting = link->preferred_link_setting; 921 return true; 922 } 923 924 /* MST doesn't perform link training for now 925 * TODO: add MST specific link training routine 926 */ 927 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 928 decide_mst_link_settings(link, link_setting); 929 } else if (link->connector_signal == SIGNAL_TYPE_EDP) { 930 /* enable edp link optimization for DSC eDP case */ 931 if (stream->timing.flags.DSC) { 932 enum dc_link_rate max_link_rate = LINK_RATE_UNKNOWN; 933 934 if (link->panel_config.dsc.force_dsc_edp_policy) { 935 /* calculate link max link rate cap*/ 936 struct dc_link_settings tmp_link_setting; 937 struct dc_crtc_timing tmp_timing = stream->timing; 938 uint32_t orig_req_bw; 939 940 tmp_link_setting.link_rate = LINK_RATE_UNKNOWN; 941 tmp_timing.flags.DSC = 0; 942 orig_req_bw = dc_bandwidth_in_kbps_from_timing(&tmp_timing); 943 edp_decide_link_settings(link, &tmp_link_setting, orig_req_bw); 944 max_link_rate = tmp_link_setting.link_rate; 945 } 946 decide_edp_link_settings_with_dsc(link, link_setting, req_bw, max_link_rate); 947 } else { 948 edp_decide_link_settings(link, link_setting, req_bw); 949 } 950 } else { 951 decide_dp_link_settings(link, link_setting, req_bw); 952 } 953 954 return link_setting->lane_count != LANE_COUNT_UNKNOWN && 955 link_setting->link_rate != LINK_RATE_UNKNOWN; 956 } 957 958 enum dp_link_encoding link_dp_get_encoding_format(const struct dc_link_settings *link_settings) 959 { 960 if ((link_settings->link_rate >= LINK_RATE_LOW) && 961 (link_settings->link_rate <= LINK_RATE_HIGH3)) 962 return DP_8b_10b_ENCODING; 963 else if ((link_settings->link_rate >= LINK_RATE_UHBR10) && 964 (link_settings->link_rate <= LINK_RATE_UHBR20)) 965 return DP_128b_132b_ENCODING; 966 return DP_UNKNOWN_ENCODING; 967 } 968 969 enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link) 970 { 971 struct dc_link_settings link_settings = {0}; 972 973 if (!dc_is_dp_signal(link->connector_signal)) 974 return DP_UNKNOWN_ENCODING; 975 976 if (link->preferred_link_setting.lane_count != 977 LANE_COUNT_UNKNOWN && 978 link->preferred_link_setting.link_rate != 979 LINK_RATE_UNKNOWN) { 980 link_settings = link->preferred_link_setting; 981 } else { 982 decide_mst_link_settings(link, &link_settings); 983 } 984 985 return link_dp_get_encoding_format(&link_settings); 986 } 987 988 static void read_dp_device_vendor_id(struct dc_link *link) 989 { 990 struct dp_device_vendor_id dp_id; 991 992 /* read IEEE branch device id */ 993 core_link_read_dpcd( 994 link, 995 DP_BRANCH_OUI, 996 (uint8_t *)&dp_id, 997 sizeof(dp_id)); 998 999 link->dpcd_caps.branch_dev_id = 1000 (dp_id.ieee_oui[0] << 16) + 1001 (dp_id.ieee_oui[1] << 8) + 1002 dp_id.ieee_oui[2]; 1003 1004 memmove( 1005 link->dpcd_caps.branch_dev_name, 1006 dp_id.ieee_device_id, 1007 sizeof(dp_id.ieee_device_id)); 1008 } 1009 1010 static enum dc_status wake_up_aux_channel(struct dc_link *link) 1011 { 1012 enum dc_status status = DC_ERROR_UNEXPECTED; 1013 uint32_t aux_channel_retry_cnt = 0; 1014 uint8_t dpcd_power_state = '\0'; 1015 1016 while (status != DC_OK && aux_channel_retry_cnt < 10) { 1017 status = core_link_read_dpcd(link, DP_SET_POWER, 1018 &dpcd_power_state, sizeof(dpcd_power_state)); 1019 1020 /* Delay 1 ms if AUX CH is in power down state. Based on spec 1021 * section 2.3.1.2, if AUX CH may be powered down due to 1022 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential 1023 * signal and may need up to 1 ms before being able to reply. 1024 */ 1025 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) { 1026 fsleep(1000); 1027 aux_channel_retry_cnt++; 1028 } 1029 } 1030 1031 if (status != DC_OK) { 1032 dpcd_power_state = DP_SET_POWER_D0; 1033 status = core_link_write_dpcd( 1034 link, 1035 DP_SET_POWER, 1036 &dpcd_power_state, 1037 sizeof(dpcd_power_state)); 1038 1039 dpcd_power_state = DP_SET_POWER_D3; 1040 status = core_link_write_dpcd( 1041 link, 1042 DP_SET_POWER, 1043 &dpcd_power_state, 1044 sizeof(dpcd_power_state)); 1045 DC_LOG_DC("%s: Failed to power up sink\n", __func__); 1046 return DC_ERROR_UNEXPECTED; 1047 } 1048 1049 return DC_OK; 1050 } 1051 1052 static void get_active_converter_info( 1053 uint8_t data, struct dc_link *link) 1054 { 1055 union dp_downstream_port_present ds_port = { .byte = data }; 1056 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps)); 1057 1058 /* decode converter info*/ 1059 if (!ds_port.fields.PORT_PRESENT) { 1060 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; 1061 set_dongle_type(link->ddc, 1062 link->dpcd_caps.dongle_type); 1063 link->dpcd_caps.is_branch_dev = false; 1064 return; 1065 } 1066 1067 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */ 1068 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT; 1069 1070 switch (ds_port.fields.PORT_TYPE) { 1071 case DOWNSTREAM_VGA: 1072 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER; 1073 break; 1074 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS: 1075 /* At this point we don't know is it DVI or HDMI or DP++, 1076 * assume DVI.*/ 1077 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER; 1078 break; 1079 default: 1080 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; 1081 break; 1082 } 1083 1084 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) { 1085 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/ 1086 union dwnstream_port_caps_byte0 *port_caps = 1087 (union dwnstream_port_caps_byte0 *)det_caps; 1088 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0, 1089 det_caps, sizeof(det_caps)) == DC_OK) { 1090 1091 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) { 1092 /*Handle DP case as DONGLE_NONE*/ 1093 case DOWN_STREAM_DETAILED_DP: 1094 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; 1095 break; 1096 case DOWN_STREAM_DETAILED_VGA: 1097 link->dpcd_caps.dongle_type = 1098 DISPLAY_DONGLE_DP_VGA_CONVERTER; 1099 break; 1100 case DOWN_STREAM_DETAILED_DVI: 1101 link->dpcd_caps.dongle_type = 1102 DISPLAY_DONGLE_DP_DVI_CONVERTER; 1103 break; 1104 case DOWN_STREAM_DETAILED_HDMI: 1105 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS: 1106 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/ 1107 link->dpcd_caps.dongle_type = 1108 DISPLAY_DONGLE_DP_HDMI_CONVERTER; 1109 1110 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type; 1111 if (ds_port.fields.DETAILED_CAPS) { 1112 1113 union dwnstream_port_caps_byte3_hdmi 1114 hdmi_caps = {.raw = det_caps[3] }; 1115 union dwnstream_port_caps_byte2 1116 hdmi_color_caps = {.raw = det_caps[2] }; 1117 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz = 1118 det_caps[1] * 2500; 1119 1120 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter = 1121 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK; 1122 /*YCBCR capability only for HDMI case*/ 1123 if (port_caps->bits.DWN_STRM_PORTX_TYPE 1124 == DOWN_STREAM_DETAILED_HDMI) { 1125 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through = 1126 hdmi_caps.bits.YCrCr422_PASS_THROUGH; 1127 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through = 1128 hdmi_caps.bits.YCrCr420_PASS_THROUGH; 1129 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter = 1130 hdmi_caps.bits.YCrCr422_CONVERSION; 1131 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter = 1132 hdmi_caps.bits.YCrCr420_CONVERSION; 1133 } 1134 1135 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc = 1136 translate_dpcd_max_bpc( 1137 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); 1138 1139 if (link->dc->caps.dp_hdmi21_pcon_support) { 1140 union hdmi_encoded_link_bw hdmi_encoded_link_bw; 1141 1142 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = 1143 link_bw_kbps_from_raw_frl_link_rate_data( 1144 hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT); 1145 1146 // Intersect reported max link bw support with the supported link rate post FRL link training 1147 if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS, 1148 &hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) { 1149 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support( 1150 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps, 1151 hdmi_encoded_link_bw); 1152 } 1153 1154 if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0) 1155 link->dpcd_caps.dongle_caps.extendedCapValid = true; 1156 } 1157 1158 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0) 1159 link->dpcd_caps.dongle_caps.extendedCapValid = true; 1160 } 1161 1162 break; 1163 } 1164 } 1165 } 1166 1167 set_dongle_type(link->ddc, link->dpcd_caps.dongle_type); 1168 1169 { 1170 struct dp_sink_hw_fw_revision dp_hw_fw_revision; 1171 1172 core_link_read_dpcd( 1173 link, 1174 DP_BRANCH_REVISION_START, 1175 (uint8_t *)&dp_hw_fw_revision, 1176 sizeof(dp_hw_fw_revision)); 1177 1178 link->dpcd_caps.branch_hw_revision = 1179 dp_hw_fw_revision.ieee_hw_rev; 1180 1181 memmove( 1182 link->dpcd_caps.branch_fw_revision, 1183 dp_hw_fw_revision.ieee_fw_rev, 1184 sizeof(dp_hw_fw_revision.ieee_fw_rev)); 1185 } 1186 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 && 1187 link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) { 1188 union dp_dfp_cap_ext dfp_cap_ext; 1189 memset(&dfp_cap_ext, '\0', sizeof (dfp_cap_ext)); 1190 core_link_read_dpcd( 1191 link, 1192 DP_DFP_CAPABILITY_EXTENSION_SUPPORT, 1193 dfp_cap_ext.raw, 1194 sizeof(dfp_cap_ext.raw)); 1195 link->dpcd_caps.dongle_caps.dfp_cap_ext.supported = dfp_cap_ext.fields.supported; 1196 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps = 1197 dfp_cap_ext.fields.max_pixel_rate_in_mps[0] + 1198 (dfp_cap_ext.fields.max_pixel_rate_in_mps[1] << 8); 1199 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width = 1200 dfp_cap_ext.fields.max_video_h_active_width[0] + 1201 (dfp_cap_ext.fields.max_video_h_active_width[1] << 8); 1202 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height = 1203 dfp_cap_ext.fields.max_video_v_active_height[0] + 1204 (dfp_cap_ext.fields.max_video_v_active_height[1] << 8); 1205 link->dpcd_caps.dongle_caps.dfp_cap_ext.encoding_format_caps = 1206 dfp_cap_ext.fields.encoding_format_caps; 1207 link->dpcd_caps.dongle_caps.dfp_cap_ext.rgb_color_depth_caps = 1208 dfp_cap_ext.fields.rgb_color_depth_caps; 1209 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr444_color_depth_caps = 1210 dfp_cap_ext.fields.ycbcr444_color_depth_caps; 1211 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr422_color_depth_caps = 1212 dfp_cap_ext.fields.ycbcr422_color_depth_caps; 1213 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr420_color_depth_caps = 1214 dfp_cap_ext.fields.ycbcr420_color_depth_caps; 1215 DC_LOG_DP2("DFP capability extension is read at link %d", link->link_index); 1216 DC_LOG_DP2("\tdfp_cap_ext.supported = %s", link->dpcd_caps.dongle_caps.dfp_cap_ext.supported ? "true" : "false"); 1217 DC_LOG_DP2("\tdfp_cap_ext.max_pixel_rate_in_mps = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps); 1218 DC_LOG_DP2("\tdfp_cap_ext.max_video_h_active_width = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width); 1219 DC_LOG_DP2("\tdfp_cap_ext.max_video_v_active_height = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height); 1220 } 1221 } 1222 1223 static void apply_usbc_combo_phy_reset_wa(struct dc_link *link, 1224 struct dc_link_settings *link_settings) 1225 { 1226 /* Temporary Renoir-specific workaround PHY will sometimes be in bad 1227 * state on hotplugging display from certain USB-C dongle, so add extra 1228 * cycle of enabling and disabling the PHY before first link training. 1229 */ 1230 struct link_resource link_res = {0}; 1231 enum clock_source_id dp_cs_id = get_clock_source_id(link); 1232 1233 dp_enable_link_phy(link, &link_res, link->connector_signal, 1234 dp_cs_id, link_settings); 1235 dp_disable_link_phy(link, &link_res, link->connector_signal); 1236 } 1237 1238 bool dp_overwrite_extended_receiver_cap(struct dc_link *link) 1239 { 1240 uint8_t dpcd_data[16]; 1241 uint32_t read_dpcd_retry_cnt = 3; 1242 enum dc_status status = DC_ERROR_UNEXPECTED; 1243 union dp_downstream_port_present ds_port = { 0 }; 1244 union down_stream_port_count down_strm_port_count; 1245 union edp_configuration_cap edp_config_cap; 1246 1247 int i; 1248 1249 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1250 status = core_link_read_dpcd( 1251 link, 1252 DP_DPCD_REV, 1253 dpcd_data, 1254 sizeof(dpcd_data)); 1255 if (status == DC_OK) 1256 break; 1257 } 1258 1259 link->dpcd_caps.dpcd_rev.raw = 1260 dpcd_data[DP_DPCD_REV - DP_DPCD_REV]; 1261 1262 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0) 1263 return false; 1264 1265 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT - 1266 DP_DPCD_REV]; 1267 1268 get_active_converter_info(ds_port.byte, link); 1269 1270 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT - 1271 DP_DPCD_REV]; 1272 1273 link->dpcd_caps.allow_invalid_MSA_timing_param = 1274 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM; 1275 1276 link->dpcd_caps.max_ln_count.raw = dpcd_data[ 1277 DP_MAX_LANE_COUNT - DP_DPCD_REV]; 1278 1279 link->dpcd_caps.max_down_spread.raw = dpcd_data[ 1280 DP_MAX_DOWNSPREAD - DP_DPCD_REV]; 1281 1282 link->reported_link_cap.lane_count = 1283 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT; 1284 link->reported_link_cap.link_rate = dpcd_data[ 1285 DP_MAX_LINK_RATE - DP_DPCD_REV]; 1286 link->reported_link_cap.link_spread = 1287 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ? 1288 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; 1289 1290 edp_config_cap.raw = dpcd_data[ 1291 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV]; 1292 link->dpcd_caps.panel_mode_edp = 1293 edp_config_cap.bits.ALT_SCRAMBLER_RESET; 1294 link->dpcd_caps.dpcd_display_control_capable = 1295 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE; 1296 1297 return true; 1298 } 1299 1300 void dpcd_set_source_specific_data(struct dc_link *link) 1301 { 1302 if (!link->dc->vendor_signature.is_valid) { 1303 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED; 1304 struct dpcd_amd_signature amd_signature = {0}; 1305 struct dpcd_amd_device_id amd_device_id = {0}; 1306 1307 amd_device_id.device_id_byte1 = 1308 (uint8_t)(link->ctx->asic_id.chip_id); 1309 amd_device_id.device_id_byte2 = 1310 (uint8_t)(link->ctx->asic_id.chip_id >> 8); 1311 amd_device_id.dce_version = 1312 (uint8_t)(link->ctx->dce_version); 1313 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get? 1314 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get? 1315 1316 core_link_read_dpcd(link, DP_SOURCE_OUI, 1317 (uint8_t *)(&amd_signature), 1318 sizeof(amd_signature)); 1319 1320 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) && 1321 (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) && 1322 (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) { 1323 1324 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0; 1325 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0; 1326 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A; 1327 1328 core_link_write_dpcd(link, DP_SOURCE_OUI, 1329 (uint8_t *)(&amd_signature), 1330 sizeof(amd_signature)); 1331 } 1332 1333 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03, 1334 (uint8_t *)(&amd_device_id), 1335 sizeof(amd_device_id)); 1336 1337 if (link->ctx->dce_version >= DCN_VERSION_2_0 && 1338 link->dc->caps.min_horizontal_blanking_period != 0) { 1339 1340 uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period; 1341 1342 result_write_min_hblank = core_link_write_dpcd(link, 1343 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size), 1344 sizeof(hblank_size)); 1345 } 1346 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, 1347 WPP_BIT_FLAG_DC_DETECTION_DP_CAPS, 1348 "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'", 1349 result_write_min_hblank, 1350 link->link_index, 1351 link->ctx->dce_version, 1352 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, 1353 link->dc->caps.min_horizontal_blanking_period, 1354 link->dpcd_caps.branch_dev_id, 1355 link->dpcd_caps.branch_dev_name[0], 1356 link->dpcd_caps.branch_dev_name[1], 1357 link->dpcd_caps.branch_dev_name[2], 1358 link->dpcd_caps.branch_dev_name[3], 1359 link->dpcd_caps.branch_dev_name[4], 1360 link->dpcd_caps.branch_dev_name[5]); 1361 } else { 1362 core_link_write_dpcd(link, DP_SOURCE_OUI, 1363 link->dc->vendor_signature.data.raw, 1364 sizeof(link->dc->vendor_signature.data.raw)); 1365 } 1366 } 1367 1368 void dpcd_write_cable_id_to_dprx(struct dc_link *link) 1369 { 1370 if (!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED || 1371 link->dpcd_caps.cable_id.raw == 0 || 1372 link->dprx_states.cable_id_written) 1373 return; 1374 1375 core_link_write_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX, 1376 &link->dpcd_caps.cable_id.raw, 1377 sizeof(link->dpcd_caps.cable_id.raw)); 1378 1379 link->dprx_states.cable_id_written = 1; 1380 } 1381 1382 static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id) 1383 { 1384 union dmub_rb_cmd cmd; 1385 1386 if (!link->ctx->dmub_srv || 1387 link->ep_type != DISPLAY_ENDPOINT_PHY || 1388 link->link_enc->features.flags.bits.DP_IS_USB_C == 0) 1389 return false; 1390 1391 memset(&cmd, 0, sizeof(cmd)); 1392 cmd.cable_id.header.type = DMUB_CMD_GET_USBC_CABLE_ID; 1393 cmd.cable_id.header.payload_bytes = sizeof(cmd.cable_id.data); 1394 cmd.cable_id.data.input.phy_inst = resource_transmitter_to_phy_idx( 1395 link->dc, link->link_enc->transmitter); 1396 if (dm_execute_dmub_cmd(link->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && 1397 cmd.cable_id.header.ret_status == 1) { 1398 cable_id->raw = cmd.cable_id.data.output_raw; 1399 DC_LOG_DC("usbc_cable_id = %d.\n", cable_id->raw); 1400 } 1401 return cmd.cable_id.header.ret_status == 1; 1402 } 1403 1404 static void retrieve_cable_id(struct dc_link *link) 1405 { 1406 union dp_cable_id usbc_cable_id; 1407 1408 link->dpcd_caps.cable_id.raw = 0; 1409 core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX, 1410 &link->dpcd_caps.cable_id.raw, sizeof(uint8_t)); 1411 1412 if (get_usbc_cable_id(link, &usbc_cable_id)) 1413 link->dpcd_caps.cable_id = intersect_cable_id( 1414 &link->dpcd_caps.cable_id, &usbc_cable_id); 1415 } 1416 1417 bool read_is_mst_supported(struct dc_link *link) 1418 { 1419 bool mst = false; 1420 enum dc_status st = DC_OK; 1421 union dpcd_rev rev; 1422 union mstm_cap cap; 1423 1424 if (link->preferred_training_settings.mst_enable && 1425 *link->preferred_training_settings.mst_enable == false) { 1426 return false; 1427 } 1428 1429 rev.raw = 0; 1430 cap.raw = 0; 1431 1432 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw, 1433 sizeof(rev)); 1434 1435 if (st == DC_OK && rev.raw >= DPCD_REV_12) { 1436 1437 st = core_link_read_dpcd(link, DP_MSTM_CAP, 1438 &cap.raw, sizeof(cap)); 1439 if (st == DC_OK && cap.bits.MST_CAP == 1) 1440 mst = true; 1441 } 1442 return mst; 1443 1444 } 1445 1446 /* Read additional sink caps defined in source specific DPCD area 1447 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP) 1448 * TODO: Add FS caps and read from DP_SOURCE_SINK_FS_CAP as well 1449 */ 1450 static bool dpcd_read_sink_ext_caps(struct dc_link *link) 1451 { 1452 uint8_t dpcd_data = 0; 1453 uint8_t edp_general_cap2 = 0; 1454 1455 if (!link) 1456 return false; 1457 1458 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK) 1459 return false; 1460 1461 link->dpcd_sink_ext_caps.raw = dpcd_data; 1462 1463 if (core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, &edp_general_cap2, 1) != DC_OK) 1464 return false; 1465 1466 link->dpcd_caps.panel_luminance_control = (edp_general_cap2 & DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) != 0; 1467 1468 return true; 1469 } 1470 1471 enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link) 1472 { 1473 uint8_t lttpr_dpcd_data[8]; 1474 enum dc_status status; 1475 bool is_lttpr_present; 1476 1477 /* Logic to determine LTTPR support*/ 1478 bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware; 1479 1480 if (!vbios_lttpr_interop || !link->dc->caps.extended_aux_timeout_support) 1481 return DC_NOT_SUPPORTED; 1482 1483 /* By reading LTTPR capability, RX assumes that we will enable 1484 * LTTPR extended aux timeout if LTTPR is present. 1485 */ 1486 status = core_link_read_dpcd( 1487 link, 1488 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, 1489 lttpr_dpcd_data, 1490 sizeof(lttpr_dpcd_data)); 1491 1492 link->dpcd_caps.lttpr_caps.revision.raw = 1493 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV - 1494 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1495 1496 link->dpcd_caps.lttpr_caps.max_link_rate = 1497 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER - 1498 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1499 1500 link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 1501 lttpr_dpcd_data[DP_PHY_REPEATER_CNT - 1502 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1503 1504 link->dpcd_caps.lttpr_caps.max_lane_count = 1505 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER - 1506 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1507 1508 link->dpcd_caps.lttpr_caps.mode = 1509 lttpr_dpcd_data[DP_PHY_REPEATER_MODE - 1510 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1511 1512 link->dpcd_caps.lttpr_caps.max_ext_timeout = 1513 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT - 1514 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1515 link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw = 1516 lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - 1517 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1518 1519 link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw = 1520 lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES - 1521 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1522 1523 /* If this chip cap is set, at least one retimer must exist in the chain 1524 * Override count to 1 if we receive a known bad count (0 or an invalid value) */ 1525 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 1526 (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == 0)) { 1527 ASSERT(0); 1528 link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80; 1529 DC_LOG_DC("lttpr_caps forced phy_repeater_cnt = %d\n", link->dpcd_caps.lttpr_caps.phy_repeater_cnt); 1530 } 1531 1532 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */ 1533 is_lttpr_present = dp_is_lttpr_present(link); 1534 1535 if (is_lttpr_present) 1536 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: "); 1537 1538 DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present); 1539 return status; 1540 } 1541 1542 static bool retrieve_link_cap(struct dc_link *link) 1543 { 1544 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16, 1545 * which means size 16 will be good for both of those DPCD register block reads 1546 */ 1547 uint8_t dpcd_data[16]; 1548 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST. 1549 */ 1550 uint8_t dpcd_dprx_data = '\0'; 1551 1552 struct dp_device_vendor_id sink_id; 1553 union down_stream_port_count down_strm_port_count; 1554 union edp_configuration_cap edp_config_cap; 1555 union dp_downstream_port_present ds_port = { 0 }; 1556 enum dc_status status = DC_ERROR_UNEXPECTED; 1557 uint32_t read_dpcd_retry_cnt = 3; 1558 int i; 1559 struct dp_sink_hw_fw_revision dp_hw_fw_revision; 1560 const uint32_t post_oui_delay = 30; // 30ms 1561 bool is_fec_supported = false; 1562 bool is_dsc_basic_supported = false; 1563 bool is_dsc_passthrough_supported = false; 1564 1565 memset(dpcd_data, '\0', sizeof(dpcd_data)); 1566 memset(&down_strm_port_count, 1567 '\0', sizeof(union down_stream_port_count)); 1568 memset(&edp_config_cap, '\0', 1569 sizeof(union edp_configuration_cap)); 1570 1571 /* if extended timeout is supported in hardware, 1572 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 1573 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 1574 */ 1575 try_to_configure_aux_timeout(link->ddc, 1576 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 1577 1578 status = dp_retrieve_lttpr_cap(link); 1579 1580 if (status != DC_OK) { 1581 status = wake_up_aux_channel(link); 1582 if (status == DC_OK) 1583 dp_retrieve_lttpr_cap(link); 1584 else 1585 return false; 1586 } 1587 1588 if (dp_is_lttpr_present(link)) 1589 configure_lttpr_mode_transparent(link); 1590 1591 /* Read DP tunneling information. */ 1592 status = dpcd_get_tunneling_device_data(link); 1593 1594 dpcd_set_source_specific_data(link); 1595 /* Sink may need to configure internals based on vendor, so allow some 1596 * time before proceeding with possibly vendor specific transactions 1597 */ 1598 msleep(post_oui_delay); 1599 1600 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1601 status = core_link_read_dpcd( 1602 link, 1603 DP_DPCD_REV, 1604 dpcd_data, 1605 sizeof(dpcd_data)); 1606 if (status == DC_OK) 1607 break; 1608 } 1609 1610 1611 if (status != DC_OK) { 1612 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__); 1613 return false; 1614 } 1615 1616 if (!dp_is_lttpr_present(link)) 1617 try_to_configure_aux_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 1618 1619 1620 { 1621 union training_aux_rd_interval aux_rd_interval; 1622 1623 aux_rd_interval.raw = 1624 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL]; 1625 1626 link->dpcd_caps.ext_receiver_cap_field_present = 1627 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1; 1628 1629 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) { 1630 uint8_t ext_cap_data[16]; 1631 1632 memset(ext_cap_data, '\0', sizeof(ext_cap_data)); 1633 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1634 status = core_link_read_dpcd( 1635 link, 1636 DP_DP13_DPCD_REV, 1637 ext_cap_data, 1638 sizeof(ext_cap_data)); 1639 if (status == DC_OK) { 1640 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data)); 1641 break; 1642 } 1643 } 1644 if (status != DC_OK) 1645 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__); 1646 } 1647 } 1648 1649 link->dpcd_caps.dpcd_rev.raw = 1650 dpcd_data[DP_DPCD_REV - DP_DPCD_REV]; 1651 1652 if (link->dpcd_caps.ext_receiver_cap_field_present) { 1653 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1654 status = core_link_read_dpcd( 1655 link, 1656 DP_DPRX_FEATURE_ENUMERATION_LIST, 1657 &dpcd_dprx_data, 1658 sizeof(dpcd_dprx_data)); 1659 if (status == DC_OK) 1660 break; 1661 } 1662 1663 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data; 1664 1665 if (status != DC_OK) 1666 dm_error("%s: Read DPRX caps data failed.\n", __func__); 1667 1668 /* AdaptiveSyncCapability */ 1669 dpcd_dprx_data = 0; 1670 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1671 status = core_link_read_dpcd( 1672 link, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1, 1673 &dpcd_dprx_data, sizeof(dpcd_dprx_data)); 1674 if (status == DC_OK) 1675 break; 1676 } 1677 1678 link->dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.raw = dpcd_dprx_data; 1679 1680 if (status != DC_OK) 1681 dm_error("%s: Read DPRX caps data failed. Addr:%#x\n", 1682 __func__, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1); 1683 } 1684 1685 else { 1686 link->dpcd_caps.dprx_feature.raw = 0; 1687 } 1688 1689 1690 /* Error condition checking... 1691 * It is impossible for Sink to report Max Lane Count = 0. 1692 * It is possible for Sink to report Max Link Rate = 0, if it is 1693 * an eDP device that is reporting specialized link rates in the 1694 * SUPPORTED_LINK_RATE table. 1695 */ 1696 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0) 1697 return false; 1698 1699 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT - 1700 DP_DPCD_REV]; 1701 1702 read_dp_device_vendor_id(link); 1703 1704 /* TODO - decouple raw mst capability from policy decision */ 1705 link->dpcd_caps.is_mst_capable = read_is_mst_supported(link); 1706 DC_LOG_DC("%s: MST_Support: %s\n", __func__, str_yes_no(link->dpcd_caps.is_mst_capable)); 1707 1708 get_active_converter_info(ds_port.byte, link); 1709 1710 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data)); 1711 1712 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT - 1713 DP_DPCD_REV]; 1714 1715 link->dpcd_caps.allow_invalid_MSA_timing_param = 1716 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM; 1717 1718 link->dpcd_caps.max_ln_count.raw = dpcd_data[ 1719 DP_MAX_LANE_COUNT - DP_DPCD_REV]; 1720 1721 link->dpcd_caps.max_down_spread.raw = dpcd_data[ 1722 DP_MAX_DOWNSPREAD - DP_DPCD_REV]; 1723 1724 link->reported_link_cap.lane_count = 1725 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT; 1726 link->reported_link_cap.link_rate = get_link_rate_from_max_link_bw( 1727 dpcd_data[DP_MAX_LINK_RATE - DP_DPCD_REV]); 1728 link->reported_link_cap.link_spread = 1729 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ? 1730 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; 1731 1732 edp_config_cap.raw = dpcd_data[ 1733 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV]; 1734 link->dpcd_caps.panel_mode_edp = 1735 edp_config_cap.bits.ALT_SCRAMBLER_RESET; 1736 link->dpcd_caps.dpcd_display_control_capable = 1737 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE; 1738 link->dpcd_caps.channel_coding_cap.raw = 1739 dpcd_data[DP_MAIN_LINK_CHANNEL_CODING - DP_DPCD_REV]; 1740 link->test_pattern_enabled = false; 1741 link->compliance_test_state.raw = 0; 1742 1743 /* read sink count */ 1744 core_link_read_dpcd(link, 1745 DP_SINK_COUNT, 1746 &link->dpcd_caps.sink_count.raw, 1747 sizeof(link->dpcd_caps.sink_count.raw)); 1748 1749 /* read sink ieee oui */ 1750 core_link_read_dpcd(link, 1751 DP_SINK_OUI, 1752 (uint8_t *)(&sink_id), 1753 sizeof(sink_id)); 1754 1755 link->dpcd_caps.sink_dev_id = 1756 (sink_id.ieee_oui[0] << 16) + 1757 (sink_id.ieee_oui[1] << 8) + 1758 (sink_id.ieee_oui[2]); 1759 1760 memmove( 1761 link->dpcd_caps.sink_dev_id_str, 1762 sink_id.ieee_device_id, 1763 sizeof(sink_id.ieee_device_id)); 1764 1765 core_link_read_dpcd( 1766 link, 1767 DP_SINK_HW_REVISION_START, 1768 (uint8_t *)&dp_hw_fw_revision, 1769 sizeof(dp_hw_fw_revision)); 1770 1771 link->dpcd_caps.sink_hw_revision = 1772 dp_hw_fw_revision.ieee_hw_rev; 1773 1774 memmove( 1775 link->dpcd_caps.sink_fw_revision, 1776 dp_hw_fw_revision.ieee_fw_rev, 1777 sizeof(dp_hw_fw_revision.ieee_fw_rev)); 1778 1779 /* Quirk for Retina panels: wrong DP_MAX_LINK_RATE */ 1780 { 1781 uint8_t str_mbp_2018[] = { 101, 68, 21, 103, 98, 97 }; 1782 uint8_t fwrev_mbp_2018[] = { 7, 4 }; 1783 uint8_t fwrev_mbp_2018_vega[] = { 8, 4 }; 1784 1785 /* We also check for the firmware revision as 16,1 models have an 1786 * identical device id and are incorrectly quirked otherwise. 1787 */ 1788 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) && 1789 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2018, 1790 sizeof(str_mbp_2018)) && 1791 (!memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018, 1792 sizeof(fwrev_mbp_2018)) || 1793 !memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018_vega, 1794 sizeof(fwrev_mbp_2018_vega)))) { 1795 link->reported_link_cap.link_rate = LINK_RATE_RBR2; 1796 } 1797 } 1798 1799 memset(&link->dpcd_caps.dsc_caps, '\0', 1800 sizeof(link->dpcd_caps.dsc_caps)); 1801 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); 1802 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */ 1803 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) { 1804 status = core_link_read_dpcd( 1805 link, 1806 DP_FEC_CAPABILITY, 1807 &link->dpcd_caps.fec_cap.raw, 1808 sizeof(link->dpcd_caps.fec_cap.raw)); 1809 status = core_link_read_dpcd( 1810 link, 1811 DP_DSC_SUPPORT, 1812 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 1813 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw)); 1814 if (status == DC_OK) { 1815 is_fec_supported = link->dpcd_caps.fec_cap.bits.FEC_CAPABLE; 1816 is_dsc_basic_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT; 1817 is_dsc_passthrough_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT; 1818 DC_LOG_DC("%s: FEC_Sink_Support: %s\n", __func__, 1819 str_yes_no(is_fec_supported)); 1820 DC_LOG_DC("%s: DSC_Basic_Sink_Support: %s\n", __func__, 1821 str_yes_no(is_dsc_basic_supported)); 1822 DC_LOG_DC("%s: DSC_Passthrough_Sink_Support: %s\n", __func__, 1823 str_yes_no(is_dsc_passthrough_supported)); 1824 } 1825 if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) { 1826 status = core_link_read_dpcd( 1827 link, 1828 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, 1829 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 1830 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw)); 1831 DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index); 1832 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x", 1833 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_0); 1834 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_1 = 0x%02x", 1835 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_1); 1836 DC_LOG_DSC("\tBRANCH_MAX_LINE_WIDTH 0x%02x", 1837 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_MAX_LINE_WIDTH); 1838 } 1839 1840 /* Apply work around to disable FEC and DSC for USB4 tunneling in TBT3 compatibility mode 1841 * only if required. 1842 */ 1843 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 1844 link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around && 1845 link->dpcd_caps.is_branch_dev && 1846 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 1847 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 && 1848 (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE || 1849 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)) { 1850 /* A TBT3 device is expected to report no support for FEC or DSC to a USB4 DPIA. 1851 * Clear FEC and DSC capabilities as a work around if that is not the case. 1852 */ 1853 link->wa_flags.dpia_forced_tbt3_mode = true; 1854 memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps)); 1855 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); 1856 DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index); 1857 } else 1858 link->wa_flags.dpia_forced_tbt3_mode = false; 1859 } 1860 1861 if (!dpcd_read_sink_ext_caps(link)) 1862 link->dpcd_sink_ext_caps.raw = 0; 1863 1864 if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) { 1865 DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index); 1866 1867 core_link_read_dpcd(link, 1868 DP_128B132B_SUPPORTED_LINK_RATES, 1869 &link->dpcd_caps.dp_128b_132b_supported_link_rates.raw, 1870 sizeof(link->dpcd_caps.dp_128b_132b_supported_link_rates.raw)); 1871 if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR20) 1872 link->reported_link_cap.link_rate = LINK_RATE_UHBR20; 1873 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5) 1874 link->reported_link_cap.link_rate = LINK_RATE_UHBR13_5; 1875 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR10) 1876 link->reported_link_cap.link_rate = LINK_RATE_UHBR10; 1877 else 1878 dm_error("%s: Invalid RX 128b_132b_supported_link_rates\n", __func__); 1879 DC_LOG_DP2("128b/132b supported link rates is read at link %d", link->link_index); 1880 DC_LOG_DP2("\tmax 128b/132b link rate support is %d.%d GHz", 1881 link->reported_link_cap.link_rate / 100, 1882 link->reported_link_cap.link_rate % 100); 1883 1884 core_link_read_dpcd(link, 1885 DP_SINK_VIDEO_FALLBACK_FORMATS, 1886 &link->dpcd_caps.fallback_formats.raw, 1887 sizeof(link->dpcd_caps.fallback_formats.raw)); 1888 DC_LOG_DP2("sink video fallback format is read at link %d", link->link_index); 1889 if (link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support) 1890 DC_LOG_DP2("\t1920x1080@60Hz 24bpp fallback format supported"); 1891 if (link->dpcd_caps.fallback_formats.bits.dp_1280x720_60Hz_24bpp_support) 1892 DC_LOG_DP2("\t1280x720@60Hz 24bpp fallback format supported"); 1893 if (link->dpcd_caps.fallback_formats.bits.dp_1024x768_60Hz_24bpp_support) 1894 DC_LOG_DP2("\t1024x768@60Hz 24bpp fallback format supported"); 1895 if (link->dpcd_caps.fallback_formats.raw == 0) { 1896 DC_LOG_DP2("\tno supported fallback formats, assume 1920x1080@60Hz 24bpp is supported"); 1897 link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support = 1; 1898 } 1899 1900 core_link_read_dpcd(link, 1901 DP_FEC_CAPABILITY_1, 1902 &link->dpcd_caps.fec_cap1.raw, 1903 sizeof(link->dpcd_caps.fec_cap1.raw)); 1904 DC_LOG_DP2("FEC CAPABILITY 1 is read at link %d", link->link_index); 1905 if (link->dpcd_caps.fec_cap1.bits.AGGREGATED_ERROR_COUNTERS_CAPABLE) 1906 DC_LOG_DP2("\tFEC aggregated error counters are supported"); 1907 } 1908 1909 retrieve_cable_id(link); 1910 dpcd_write_cable_id_to_dprx(link); 1911 1912 /* Connectivity log: detection */ 1913 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: "); 1914 1915 return true; 1916 } 1917 1918 bool detect_dp_sink_caps(struct dc_link *link) 1919 { 1920 return retrieve_link_cap(link); 1921 } 1922 1923 void detect_edp_sink_caps(struct dc_link *link) 1924 { 1925 uint8_t supported_link_rates[16]; 1926 uint32_t entry; 1927 uint32_t link_rate_in_khz; 1928 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN; 1929 uint8_t backlight_adj_cap; 1930 uint8_t general_edp_cap; 1931 1932 retrieve_link_cap(link); 1933 link->dpcd_caps.edp_supported_link_rates_count = 0; 1934 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 1935 1936 /* 1937 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher. 1938 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h" 1939 */ 1940 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 && 1941 (link->panel_config.ilr.optimize_edp_link_rate || 1942 link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) { 1943 // Read DPCD 00010h - 0001Fh 16 bytes at one shot 1944 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES, 1945 supported_link_rates, sizeof(supported_link_rates)); 1946 1947 for (entry = 0; entry < 16; entry += 2) { 1948 // DPCD register reports per-lane link rate = 16-bit link rate capability 1949 // value X 200 kHz. Need multiplier to find link rate in kHz. 1950 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 1951 supported_link_rates[entry]) * 200; 1952 1953 DC_LOG_DC("%s: eDP v1.4 supported sink rates: [%d] %d kHz\n", __func__, 1954 entry / 2, link_rate_in_khz); 1955 1956 if (link_rate_in_khz != 0) { 1957 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz); 1958 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate; 1959 link->dpcd_caps.edp_supported_link_rates_count++; 1960 1961 if (link->reported_link_cap.link_rate < link_rate) 1962 link->reported_link_cap.link_rate = link_rate; 1963 } 1964 } 1965 } 1966 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP, 1967 &backlight_adj_cap, sizeof(backlight_adj_cap)); 1968 1969 link->dpcd_caps.dynamic_backlight_capable_edp = 1970 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false; 1971 1972 core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1, 1973 &general_edp_cap, sizeof(general_edp_cap)); 1974 1975 link->dpcd_caps.set_power_state_capable_edp = 1976 (general_edp_cap & DP_EDP_SET_POWER_CAP) ? true:false; 1977 1978 set_default_brightness_aux(link); 1979 1980 core_link_read_dpcd(link, DP_EDP_DPCD_REV, 1981 &link->dpcd_caps.edp_rev, 1982 sizeof(link->dpcd_caps.edp_rev)); 1983 /* 1984 * PSR is only valid for eDP v1.3 or higher. 1985 */ 1986 if (link->dpcd_caps.edp_rev >= DP_EDP_13) { 1987 core_link_read_dpcd(link, DP_PSR_SUPPORT, 1988 &link->dpcd_caps.psr_info.psr_version, 1989 sizeof(link->dpcd_caps.psr_info.psr_version)); 1990 if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) 1991 core_link_read_dpcd(link, DP_FORCE_PSRSU_CAPABILITY, 1992 &link->dpcd_caps.psr_info.force_psrsu_cap, 1993 sizeof(link->dpcd_caps.psr_info.force_psrsu_cap)); 1994 core_link_read_dpcd(link, DP_PSR_CAPS, 1995 &link->dpcd_caps.psr_info.psr_dpcd_caps.raw, 1996 sizeof(link->dpcd_caps.psr_info.psr_dpcd_caps.raw)); 1997 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) { 1998 core_link_read_dpcd(link, DP_PSR2_SU_Y_GRANULARITY, 1999 &link->dpcd_caps.psr_info.psr2_su_y_granularity_cap, 2000 sizeof(link->dpcd_caps.psr_info.psr2_su_y_granularity_cap)); 2001 } 2002 } 2003 2004 /* 2005 * ALPM is only valid for eDP v1.4 or higher. 2006 */ 2007 if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14) 2008 core_link_read_dpcd(link, DP_RECEIVER_ALPM_CAP, 2009 &link->dpcd_caps.alpm_caps.raw, 2010 sizeof(link->dpcd_caps.alpm_caps.raw)); 2011 } 2012 2013 bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap) 2014 { 2015 struct link_encoder *link_enc = NULL; 2016 2017 if (!max_link_enc_cap) { 2018 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__); 2019 return false; 2020 } 2021 2022 link_enc = link_enc_cfg_get_link_enc(link); 2023 ASSERT(link_enc); 2024 2025 if (link_enc && link_enc->funcs->get_max_link_cap) { 2026 link_enc->funcs->get_max_link_cap(link_enc, max_link_enc_cap); 2027 return true; 2028 } 2029 2030 DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__); 2031 max_link_enc_cap->lane_count = 1; 2032 max_link_enc_cap->link_rate = 6; 2033 return false; 2034 } 2035 2036 const struct dc_link_settings *dp_get_verified_link_cap( 2037 const struct dc_link *link) 2038 { 2039 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN && 2040 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) 2041 return &link->preferred_link_setting; 2042 return &link->verified_link_cap; 2043 } 2044 2045 struct dc_link_settings dp_get_max_link_cap(struct dc_link *link) 2046 { 2047 struct dc_link_settings max_link_cap = {0}; 2048 enum dc_link_rate lttpr_max_link_rate; 2049 enum dc_link_rate cable_max_link_rate; 2050 struct link_encoder *link_enc = NULL; 2051 2052 2053 link_enc = link_enc_cfg_get_link_enc(link); 2054 ASSERT(link_enc); 2055 2056 /* get max link encoder capability */ 2057 if (link_enc) 2058 link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap); 2059 2060 /* Lower link settings based on sink's link cap */ 2061 if (link->reported_link_cap.lane_count < max_link_cap.lane_count) 2062 max_link_cap.lane_count = 2063 link->reported_link_cap.lane_count; 2064 if (link->reported_link_cap.link_rate < max_link_cap.link_rate) 2065 max_link_cap.link_rate = 2066 link->reported_link_cap.link_rate; 2067 if (link->reported_link_cap.link_spread < 2068 max_link_cap.link_spread) 2069 max_link_cap.link_spread = 2070 link->reported_link_cap.link_spread; 2071 2072 /* Lower link settings based on cable attributes 2073 * Cable ID is a DP2 feature to identify max certified link rate that 2074 * a cable can carry. The cable identification method requires both 2075 * cable and display hardware support. Since the specs comes late, it is 2076 * anticipated that the first round of DP2 cables and displays may not 2077 * be fully compatible to reliably return cable ID data. Therefore the 2078 * decision of our cable id policy is that if the cable can return non 2079 * zero cable id data, we will take cable's link rate capability into 2080 * account. However if we get zero data, the cable link rate capability 2081 * is considered inconclusive. In this case, we will not take cable's 2082 * capability into account to avoid of over limiting hardware capability 2083 * from users. The max overall link rate capability is still determined 2084 * after actual dp pre-training. Cable id is considered as an auxiliary 2085 * method of determining max link bandwidth capability. 2086 */ 2087 cable_max_link_rate = get_cable_max_link_rate(link); 2088 2089 if (!link->dc->debug.ignore_cable_id && 2090 cable_max_link_rate != LINK_RATE_UNKNOWN && 2091 cable_max_link_rate < max_link_cap.link_rate) 2092 max_link_cap.link_rate = cable_max_link_rate; 2093 2094 /* account for lttpr repeaters cap 2095 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3). 2096 */ 2097 if (dp_is_lttpr_present(link)) { 2098 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count) 2099 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count; 2100 lttpr_max_link_rate = get_lttpr_max_link_rate(link); 2101 2102 if (lttpr_max_link_rate < max_link_cap.link_rate) 2103 max_link_cap.link_rate = lttpr_max_link_rate; 2104 2105 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n", 2106 __func__, 2107 max_link_cap.lane_count, 2108 max_link_cap.link_rate); 2109 } 2110 2111 if (link_dp_get_encoding_format(&max_link_cap) == DP_128b_132b_ENCODING && 2112 link->dc->debug.disable_uhbr) 2113 max_link_cap.link_rate = LINK_RATE_HIGH3; 2114 2115 return max_link_cap; 2116 } 2117 2118 static bool dp_verify_link_cap( 2119 struct dc_link *link, 2120 struct dc_link_settings *known_limit_link_setting, 2121 int *fail_count) 2122 { 2123 struct dc_link_settings cur_link_settings = {0}; 2124 struct dc_link_settings max_link_settings = *known_limit_link_setting; 2125 bool success = false; 2126 bool skip_video_pattern; 2127 enum clock_source_id dp_cs_id = get_clock_source_id(link); 2128 enum link_training_result status = LINK_TRAINING_SUCCESS; 2129 union hpd_irq_data irq_data; 2130 struct link_resource link_res; 2131 2132 memset(&irq_data, 0, sizeof(irq_data)); 2133 cur_link_settings = max_link_settings; 2134 2135 /* Grant extended timeout request */ 2136 if (dp_is_lttpr_present(link) && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) { 2137 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80; 2138 2139 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant)); 2140 } 2141 2142 do { 2143 if (!get_temp_dp_link_res(link, &link_res, &cur_link_settings)) 2144 continue; 2145 2146 skip_video_pattern = cur_link_settings.link_rate != LINK_RATE_LOW; 2147 dp_enable_link_phy( 2148 link, 2149 &link_res, 2150 link->connector_signal, 2151 dp_cs_id, 2152 &cur_link_settings); 2153 2154 status = dp_perform_link_training( 2155 link, 2156 &link_res, 2157 &cur_link_settings, 2158 skip_video_pattern); 2159 2160 if (status == LINK_TRAINING_SUCCESS) { 2161 success = true; 2162 fsleep(1000); 2163 if (dp_read_hpd_rx_irq_data(link, &irq_data) == DC_OK && 2164 dp_parse_link_loss_status( 2165 link, 2166 &irq_data)) 2167 (*fail_count)++; 2168 2169 } else { 2170 (*fail_count)++; 2171 } 2172 dp_trace_lt_total_count_increment(link, true); 2173 dp_trace_lt_result_update(link, status, true); 2174 dp_disable_link_phy(link, &link_res, link->connector_signal); 2175 } while (!success && decide_fallback_link_setting(link, 2176 &max_link_settings, &cur_link_settings, status)); 2177 2178 link->verified_link_cap = success ? 2179 cur_link_settings : fail_safe_link_settings; 2180 return success; 2181 } 2182 2183 bool dp_verify_link_cap_with_retries( 2184 struct dc_link *link, 2185 struct dc_link_settings *known_limit_link_setting, 2186 int attempts) 2187 { 2188 int i = 0; 2189 bool success = false; 2190 int fail_count = 0; 2191 2192 dp_trace_detect_lt_init(link); 2193 2194 if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C && 2195 link->dc->debug.usbc_combo_phy_reset_wa) 2196 apply_usbc_combo_phy_reset_wa(link, known_limit_link_setting); 2197 2198 dp_trace_set_lt_start_timestamp(link, false); 2199 for (i = 0; i < attempts; i++) { 2200 enum dc_connection_type type = dc_connection_none; 2201 2202 memset(&link->verified_link_cap, 0, 2203 sizeof(struct dc_link_settings)); 2204 if (!link_detect_connection_type(link, &type) || type == dc_connection_none) { 2205 link->verified_link_cap = fail_safe_link_settings; 2206 break; 2207 } else if (dp_verify_link_cap(link, known_limit_link_setting, 2208 &fail_count) && fail_count == 0) { 2209 success = true; 2210 break; 2211 } 2212 fsleep(10 * 1000); 2213 } 2214 2215 dp_trace_lt_fail_count_update(link, fail_count, true); 2216 dp_trace_set_lt_end_timestamp(link, true); 2217 2218 return success; 2219 } 2220 2221 /* 2222 * Check if there is a native DP or passive DP-HDMI dongle connected 2223 */ 2224 bool dp_is_sink_present(struct dc_link *link) 2225 { 2226 enum gpio_result gpio_result; 2227 uint32_t clock_pin = 0; 2228 uint8_t retry = 0; 2229 struct ddc *ddc; 2230 2231 enum connector_id connector_id = 2232 dal_graphics_object_id_get_connector_id(link->link_id); 2233 2234 bool present = 2235 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) || 2236 (connector_id == CONNECTOR_ID_EDP) || 2237 (connector_id == CONNECTOR_ID_USBC)); 2238 2239 ddc = get_ddc_pin(link->ddc); 2240 2241 if (!ddc) { 2242 BREAK_TO_DEBUGGER(); 2243 return present; 2244 } 2245 2246 /* Open GPIO and set it to I2C mode */ 2247 /* Note: this GpioMode_Input will be converted 2248 * to GpioConfigType_I2cAuxDualMode in GPIO component, 2249 * which indicates we need additional delay 2250 */ 2251 2252 if (dal_ddc_open(ddc, GPIO_MODE_INPUT, 2253 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) { 2254 dal_ddc_close(ddc); 2255 2256 return present; 2257 } 2258 2259 /* 2260 * Read GPIO: DP sink is present if both clock and data pins are zero 2261 * 2262 * [W/A] plug-unplug DP cable, sometimes customer board has 2263 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI 2264 * then monitor can't br light up. Add retry 3 times 2265 * But in real passive dongle, it need additional 3ms to detect 2266 */ 2267 do { 2268 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin); 2269 ASSERT(gpio_result == GPIO_RESULT_OK); 2270 if (clock_pin) 2271 fsleep(1000); 2272 else 2273 break; 2274 } while (retry++ < 3); 2275 2276 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin; 2277 2278 dal_ddc_close(ddc); 2279 2280 return present; 2281 } 2282