1 /*
2  * Copyright 2023 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 /* FILE POLICY AND INTENDED USAGE:
27  * This file owns timing validation against various link limitations. (ex.
28  * link bandwidth, receiver capability or our hardware capability) It also
29  * provides helper functions exposing bandwidth formulas used in validation.
30  */
31 #include "link_validation.h"
32 #include "protocols/link_dp_capability.h"
33 #include "protocols/link_dp_dpia_bw.h"
34 #include "resource.h"
35 
36 #define DC_LOGGER_INIT(logger)
37 
38 static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing)
39 {
40 
41 	uint32_t pxl_clk = timing->pix_clk_100hz;
42 
43 	if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
44 		pxl_clk /= 2;
45 	else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
46 		pxl_clk = pxl_clk * 2 / 3;
47 
48 	if (timing->display_color_depth == COLOR_DEPTH_101010)
49 		pxl_clk = pxl_clk * 10 / 8;
50 	else if (timing->display_color_depth == COLOR_DEPTH_121212)
51 		pxl_clk = pxl_clk * 12 / 8;
52 
53 	return pxl_clk;
54 }
55 
56 static bool dp_active_dongle_validate_timing(
57 		const struct dc_crtc_timing *timing,
58 		const struct dpcd_caps *dpcd_caps)
59 {
60 	const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
61 
62 	switch (dpcd_caps->dongle_type) {
63 	case DISPLAY_DONGLE_DP_VGA_CONVERTER:
64 	case DISPLAY_DONGLE_DP_DVI_CONVERTER:
65 	case DISPLAY_DONGLE_DP_DVI_DONGLE:
66 		if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
67 			return true;
68 		else
69 			return false;
70 	default:
71 		break;
72 	}
73 
74 	if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
75 			dongle_caps->extendedCapValid == true) {
76 		/* Check Pixel Encoding */
77 		switch (timing->pixel_encoding) {
78 		case PIXEL_ENCODING_RGB:
79 		case PIXEL_ENCODING_YCBCR444:
80 			break;
81 		case PIXEL_ENCODING_YCBCR422:
82 			if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
83 				return false;
84 			break;
85 		case PIXEL_ENCODING_YCBCR420:
86 			if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
87 				return false;
88 			break;
89 		default:
90 			/* Invalid Pixel Encoding*/
91 			return false;
92 		}
93 
94 		switch (timing->display_color_depth) {
95 		case COLOR_DEPTH_666:
96 		case COLOR_DEPTH_888:
97 			/*888 and 666 should always be supported*/
98 			break;
99 		case COLOR_DEPTH_101010:
100 			if (dongle_caps->dp_hdmi_max_bpc < 10)
101 				return false;
102 			break;
103 		case COLOR_DEPTH_121212:
104 			if (dongle_caps->dp_hdmi_max_bpc < 12)
105 				return false;
106 			break;
107 		case COLOR_DEPTH_141414:
108 		case COLOR_DEPTH_161616:
109 		default:
110 			/* These color depths are currently not supported */
111 			return false;
112 		}
113 
114 		/* Check 3D format */
115 		switch (timing->timing_3d_format) {
116 		case TIMING_3D_FORMAT_NONE:
117 		case TIMING_3D_FORMAT_FRAME_ALTERNATE:
118 			/*Only frame alternate 3D is supported on active dongle*/
119 			break;
120 		default:
121 			/*other 3D formats are not supported due to bad infoframe translation */
122 			return false;
123 		}
124 
125 		if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter
126 			struct dc_crtc_timing outputTiming = *timing;
127 
128 #if defined(CONFIG_DRM_AMD_DC_FP)
129 			if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
130 				/* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */
131 				outputTiming.flags.DSC = 0;
132 #endif
133 			if (dc_bandwidth_in_kbps_from_timing(&outputTiming) > dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
134 				return false;
135 		} else { // DP to HDMI TMDS converter
136 			if (get_tmds_output_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
137 				return false;
138 		}
139 	}
140 
141 	if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
142 			dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
143 			dongle_caps->dfp_cap_ext.supported) {
144 
145 		if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
146 			return false;
147 
148 		if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
149 			return false;
150 
151 		if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
152 			return false;
153 
154 		if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
155 			if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
156 				return false;
157 			if (timing->display_color_depth == COLOR_DEPTH_666 &&
158 					!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
159 				return false;
160 			else if (timing->display_color_depth == COLOR_DEPTH_888 &&
161 					!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
162 				return false;
163 			else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
164 					!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
165 				return false;
166 			else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
167 					!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
168 				return false;
169 			else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
170 					!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
171 				return false;
172 		} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
173 			if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
174 				return false;
175 			if (timing->display_color_depth == COLOR_DEPTH_888 &&
176 					!dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
177 				return false;
178 			else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
179 					!dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
180 				return false;
181 			else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
182 					!dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
183 				return false;
184 			else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
185 					!dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
186 				return false;
187 		} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
188 			if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
189 				return false;
190 			if (timing->display_color_depth == COLOR_DEPTH_888 &&
191 					!dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
192 				return false;
193 			else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
194 					!dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
195 				return false;
196 			else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
197 					!dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
198 				return false;
199 			else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
200 					!dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
201 				return false;
202 		} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
203 			if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
204 				return false;
205 			if (timing->display_color_depth == COLOR_DEPTH_888 &&
206 					!dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
207 				return false;
208 			else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
209 					!dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
210 				return false;
211 			else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
212 					!dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
213 				return false;
214 			else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
215 					!dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
216 				return false;
217 		}
218 	}
219 
220 	return true;
221 }
222 
223 uint32_t dp_link_bandwidth_kbps(
224 	const struct dc_link *link,
225 	const struct dc_link_settings *link_settings)
226 {
227 	uint32_t total_data_bw_efficiency_x10000 = 0;
228 	uint32_t link_rate_per_lane_kbps = 0;
229 
230 	switch (link_dp_get_encoding_format(link_settings)) {
231 	case DP_8b_10b_ENCODING:
232 		/* For 8b/10b encoding:
233 		 * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
234 		 * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
235 		 */
236 		link_rate_per_lane_kbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
237 		total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
238 		if (dp_should_enable_fec(link)) {
239 			total_data_bw_efficiency_x10000 /= 100;
240 			total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
241 		}
242 		break;
243 	case DP_128b_132b_ENCODING:
244 		/* For 128b/132b encoding:
245 		 * link rate is defined in the unit of 10mbps per lane.
246 		 * total data bandwidth efficiency is always 96.71%.
247 		 */
248 		link_rate_per_lane_kbps = link_settings->link_rate * 10000;
249 		total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
250 		break;
251 	default:
252 		break;
253 	}
254 
255 	/* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
256 	return link_rate_per_lane_kbps * link_settings->lane_count / 10000 * total_data_bw_efficiency_x10000;
257 }
258 
259 static bool dp_validate_mode_timing(
260 	struct dc_link *link,
261 	const struct dc_crtc_timing *timing)
262 {
263 	uint32_t req_bw;
264 	uint32_t max_bw;
265 
266 	const struct dc_link_settings *link_setting;
267 
268 	/* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
269 	if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
270 			!link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
271 			dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
272 		return false;
273 
274 	/*always DP fail safe mode*/
275 	if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
276 		timing->h_addressable == (uint32_t) 640 &&
277 		timing->v_addressable == (uint32_t) 480)
278 		return true;
279 
280 	link_setting = dp_get_verified_link_cap(link);
281 
282 	/* TODO: DYNAMIC_VALIDATION needs to be implemented */
283 	/*if (flags.DYNAMIC_VALIDATION == 1 &&
284 		link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
285 		link_setting = &link->verified_link_cap;
286 	*/
287 
288 	req_bw = dc_bandwidth_in_kbps_from_timing(timing);
289 	max_bw = dp_link_bandwidth_kbps(link, link_setting);
290 
291 	if (req_bw <= max_bw) {
292 		/* remember the biggest mode here, during
293 		 * initial link training (to get
294 		 * verified_link_cap), LS sends event about
295 		 * cannot train at reported cap to upper
296 		 * layer and upper layer will re-enumerate modes.
297 		 * this is not necessary if the lower
298 		 * verified_link_cap is enough to drive
299 		 * all the modes */
300 
301 		/* TODO: DYNAMIC_VALIDATION needs to be implemented */
302 		/* if (flags.DYNAMIC_VALIDATION == 1)
303 			dpsst->max_req_bw_for_verified_linkcap = dal_max(
304 				dpsst->max_req_bw_for_verified_linkcap, req_bw); */
305 		return true;
306 	} else
307 		return false;
308 }
309 
310 enum dc_status link_validate_mode_timing(
311 		const struct dc_stream_state *stream,
312 		struct dc_link *link,
313 		const struct dc_crtc_timing *timing)
314 {
315 	uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
316 	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
317 
318 	/* A hack to avoid failing any modes for EDID override feature on
319 	 * topology change such as lower quality cable for DP or different dongle
320 	 */
321 	if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
322 		return DC_OK;
323 
324 	/* Passive Dongle */
325 	if (max_pix_clk != 0 && get_tmds_output_pixel_clock_100hz(timing) > max_pix_clk)
326 		return DC_EXCEED_DONGLE_CAP;
327 
328 	/* Active Dongle*/
329 	if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
330 		return DC_EXCEED_DONGLE_CAP;
331 
332 	switch (stream->signal) {
333 	case SIGNAL_TYPE_EDP:
334 	case SIGNAL_TYPE_DISPLAY_PORT:
335 		if (!dp_validate_mode_timing(
336 				link,
337 				timing))
338 			return DC_NO_DP_LINK_BANDWIDTH;
339 		break;
340 
341 	default:
342 		break;
343 	}
344 
345 	return DC_OK;
346 }
347 
348 bool link_validate_dpia_bandwidth(const struct dc_stream_state *stream, const unsigned int num_streams)
349 {
350 	bool ret = true;
351 	int bw_needed[MAX_DPIA_NUM];
352 	struct dc_link *link[MAX_DPIA_NUM];
353 
354 	if (!num_streams || num_streams > MAX_DPIA_NUM)
355 		return ret;
356 
357 	for (uint8_t i = 0; i < num_streams; ++i) {
358 
359 		link[i] = stream[i].link;
360 		bw_needed[i] = dc_bandwidth_in_kbps_from_timing(&stream[i].timing);
361 	}
362 	return ret;
363 }
364